1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_ppc.hpp"
37 #include "oops/compressedOops.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/os.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/macros.hpp"
46 #include "utilities/powerOfTwo.hpp"
47
48 #define __ _masm->
49
50
51 const ConditionRegister LIR_Assembler::BOOL_RESULT = CR5;
52
53
54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
55 Unimplemented(); return false; // Currently not used on this platform.
56 }
57
58
59 LIR_Opr LIR_Assembler::receiverOpr() {
60 return FrameMap::R3_oop_opr;
61 }
62
63
64 LIR_Opr LIR_Assembler::osrBufferPointer() {
65 return FrameMap::R3_opr;
66 }
67
68
69 // This specifies the stack pointer decrement needed to build the frame.
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74
75 // Inline cache check: the inline cached class is in inline_cache_reg;
76 // we fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = R20;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
92 __ mtctr(klass);
93 __ bctr();
94
95 __ bind(L_skip_barrier);
96 }
97
98 void LIR_Assembler::osr_entry() {
99 // On-stack-replacement entry sequence:
100 //
101 // 1. Create a new compiled activation.
102 // 2. Initialize local variables in the compiled activation. The expression
103 // stack must be empty at the osr_bci; it is not initialized.
104 // 3. Jump to the continuation address in compiled code to resume execution.
105
106 // OSR entry point
107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
108 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
109 ValueStack* entry_state = osr_entry->end()->state();
110 int number_of_locks = entry_state->locks_size();
111
112 // Create a frame for the compiled activation.
113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
114
115 // OSR buffer is
116 //
117 // locals[nlocals-1..0]
118 // monitors[number_of_locks-1..0]
119 //
120 // Locals is a direct copy of the interpreter frame so in the osr buffer
121 // the first slot in the local array is the last local from the interpreter
122 // and the last slot is local[0] (receiver) from the interpreter.
123 //
124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
126 // in the interpreter frame (the method lock if a sync method).
127
128 // Initialize monitors in the compiled activation.
129 // R3: pointer to osr buffer
130 //
131 // All other registers are dead at this point and the locals will be
132 // copied into place by code emitted in the IR.
133
134 Register OSR_buf = osrBufferPointer()->as_register();
135 {
136 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137
138 const int locals_space = BytesPerWord * method()->max_locals();
139 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
140 bool use_OSR_bias = false;
141
142 if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
143 // Offsets too large for ld instructions. Use bias.
144 __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
145 monitor_offset -= locals_space;
146 use_OSR_bias = true;
147 }
148
149 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
150 // the OSR buffer using 2 word entries: first the lock and then
151 // the oop.
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
154 #ifdef ASSERT
155 // Verify the interpreter's monitor has a non-null object.
156 {
157 Label L;
158 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
159 __ cmpdi(CR0, R0, 0);
160 __ bne(CR0, L);
161 __ stop("locked object is null");
162 __ bind(L);
163 }
164 #endif // ASSERT
165 // Copy the lock field into the compiled activation.
166 Address ml = frame_map()->address_for_monitor_lock(i),
167 mo = frame_map()->address_for_monitor_object(i);
168 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
169 __ ld(R0, slot_offset + 0, OSR_buf);
170 __ std(R0, ml);
171 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
172 __ std(R0, mo);
173 }
174
175 if (use_OSR_bias) {
176 // Restore.
177 __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
178 }
179 }
180 }
181
182
183 int LIR_Assembler::emit_exception_handler() {
184 // Generate code for the exception handler.
185 address handler_base = __ start_a_stub(exception_handler_size());
186
187 if (handler_base == nullptr) {
188 // Not enough space left for the handler.
189 bailout("exception handler overflow");
190 return -1;
191 }
192
193 int offset = code_offset();
194 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id));
195 //__ load_const_optimized(R0, entry_point);
196 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
197 __ mtctr(R0);
198 __ bctr();
199
200 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
201 __ end_a_stub();
202
203 return offset;
204 }
205
206
207 // Emit the code to remove the frame from the stack in the exception
208 // unwind path.
209 int LIR_Assembler::emit_unwind_handler() {
210 _masm->block_comment("Unwind handler");
211
212 int offset = code_offset();
213 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
214 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
215
216 // Fetch the exception from TLS and clear out exception related thread state.
217 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
218 __ li(R0, 0);
219 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
220 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
221
222 __ bind(_unwind_handler_entry);
223 __ verify_not_null_oop(Rexception);
224 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
225
226 // Perform needed unlocking
227 MonitorExitStub* stub = nullptr;
228 if (method()->is_synchronized()) {
229 monitor_address(0, FrameMap::R4_opr);
230 stub = new MonitorExitStub(FrameMap::R4_opr, 0);
231 __ unlock_object(R5, R6, R4, *stub->entry());
232 __ bind(*stub->continuation());
233 }
234
235 if (compilation()->env()->dtrace_method_probes()) {
236 Unimplemented();
237 }
238
239 // Dispatch to the unwind logic.
240 address unwind_stub = Runtime1::entry_for(StubId::c1_unwind_exception_id);
241 //__ load_const_optimized(R0, unwind_stub);
242 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
243 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
244 __ mtctr(R0);
245 __ bctr();
246
247 // Emit the slow path assembly.
248 if (stub != nullptr) {
249 stub->emit_code(this);
250 }
251
252 return offset;
253 }
254
255
256 int LIR_Assembler::emit_deopt_handler() {
257 // Generate code for deopt handler.
258 address handler_base = __ start_a_stub(deopt_handler_size());
259
260 if (handler_base == nullptr) {
261 // Not enough space left for the handler.
262 bailout("deopt handler overflow");
263 return -1;
264 }
265
266 int offset = code_offset();
267 Label start;
268
269 __ bind(start);
270 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
271 int entry_offset = __ offset();
272 __ b(start);
273
274 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
275 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
276 "out of bounds read in post-call NOP check");
277 __ end_a_stub();
278
279 return entry_offset;
280 }
281
282
283 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
284 if (o == nullptr) {
285 __ li(reg, 0);
286 } else {
287 AddressLiteral addrlit = __ constant_oop_address(o);
288 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
289 }
290 }
291
292
293 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
294 // Allocate a new index in table to hold the object once it's been patched.
295 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
296 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
297
298 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
299 __ load_const(reg, addrlit, R0);
300
301 patching_epilog(patch, lir_patch_normal, reg, info);
302 }
303
304
305 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
306 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
307 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
308 }
309
310
311 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
312 // Allocate a new index in table to hold the klass once it's been patched.
313 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
314 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
315
316 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
317 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
318 __ load_const(reg, addrlit, R0);
319
320 patching_epilog(patch, lir_patch_normal, reg, info);
321 }
322
323
324 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
325 const bool is_int = result->is_single_cpu();
326 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
327 Register Rdivisor = noreg;
328 Register Rscratch = temp->as_register();
329 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
330 long divisor = -1;
331
332 if (right->is_register()) {
333 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
334 } else {
335 divisor = is_int ? right->as_constant_ptr()->as_jint()
336 : right->as_constant_ptr()->as_jlong();
337 }
338
339 assert(Rdividend != Rscratch, "");
340 assert(Rdivisor != Rscratch, "");
341 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
342
343 if (Rdivisor == noreg) {
344 if (divisor == 1) { // stupid, but can happen
345 if (code == lir_idiv) {
346 __ mr_if_needed(Rresult, Rdividend);
347 } else {
348 __ li(Rresult, 0);
349 }
350
351 } else if (is_power_of_2(divisor)) {
352 // Convert division by a power of two into some shifts and logical operations.
353 int log2 = log2i_exact(divisor);
354
355 // Round towards 0.
356 if (divisor == 2) {
357 if (is_int) {
358 __ srwi(Rscratch, Rdividend, 31);
359 } else {
360 __ srdi(Rscratch, Rdividend, 63);
361 }
362 } else {
363 if (is_int) {
364 __ srawi(Rscratch, Rdividend, 31);
365 } else {
366 __ sradi(Rscratch, Rdividend, 63);
367 }
368 __ clrldi(Rscratch, Rscratch, 64-log2);
369 }
370 __ add(Rscratch, Rdividend, Rscratch);
371
372 if (code == lir_idiv) {
373 if (is_int) {
374 __ srawi(Rresult, Rscratch, log2);
375 } else {
376 __ sradi(Rresult, Rscratch, log2);
377 }
378 } else { // lir_irem
379 __ clrrdi(Rscratch, Rscratch, log2);
380 __ sub(Rresult, Rdividend, Rscratch);
381 }
382
383 } else if (divisor == -1) {
384 if (code == lir_idiv) {
385 __ neg(Rresult, Rdividend);
386 } else {
387 __ li(Rresult, 0);
388 }
389
390 } else {
391 __ load_const_optimized(Rscratch, divisor);
392 if (code == lir_idiv) {
393 if (is_int) {
394 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
395 } else {
396 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
397 }
398 } else {
399 assert(Rscratch != R0, "need both");
400 if (is_int) {
401 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
402 __ mullw(Rscratch, R0, Rscratch);
403 } else {
404 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
405 __ mulld(Rscratch, R0, Rscratch);
406 }
407 __ sub(Rresult, Rdividend, Rscratch);
408 }
409
410 }
411 return;
412 }
413
414 Label regular, done;
415 if (is_int) {
416 __ cmpwi(CR0, Rdivisor, -1);
417 } else {
418 __ cmpdi(CR0, Rdivisor, -1);
419 }
420 __ bne(CR0, regular);
421 if (code == lir_idiv) {
422 __ neg(Rresult, Rdividend);
423 __ b(done);
424 __ bind(regular);
425 if (is_int) {
426 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
427 } else {
428 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
429 }
430 } else { // lir_irem
431 __ li(Rresult, 0);
432 __ b(done);
433 __ bind(regular);
434 if (is_int) {
435 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
436 __ mullw(Rscratch, Rscratch, Rdivisor);
437 } else {
438 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
439 __ mulld(Rscratch, Rscratch, Rdivisor);
440 }
441 __ sub(Rresult, Rdividend, Rscratch);
442 }
443 __ bind(done);
444 }
445
446
447 void LIR_Assembler::emit_op3(LIR_Op3* op) {
448 switch (op->code()) {
449 case lir_idiv:
450 case lir_irem:
451 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
452 op->result_opr(), op->info());
453 break;
454 case lir_fmad:
455 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
456 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
457 break;
458 case lir_fmaf:
459 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
460 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
461 break;
462 default: ShouldNotReachHere(); break;
463 }
464 }
465
466
467 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
468 #ifdef ASSERT
469 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
470 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
471 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
472 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
473 #endif
474
475 Label *L = op->label();
476 if (op->cond() == lir_cond_always) {
477 __ b(*L);
478 } else {
479 Label done;
480 bool is_unordered = false;
481 if (op->code() == lir_cond_float_branch) {
482 assert(op->ublock() != nullptr, "must have unordered successor");
483 is_unordered = true;
484 } else {
485 assert(op->code() == lir_branch, "just checking");
486 }
487
488 bool positive = false;
489 Assembler::Condition cond = Assembler::equal;
490 switch (op->cond()) {
491 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
492 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
493 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
494 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
495 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
496 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
497 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
498 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
499 default: ShouldNotReachHere();
500 }
501 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
502 int bi = Assembler::bi0(BOOL_RESULT, cond);
503 if (is_unordered) {
504 if (positive) {
505 if (op->ublock() == op->block()) {
506 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
507 }
508 } else {
509 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
510 }
511 }
512 __ bc_far_optimized(bo, bi, *L);
513 __ bind(done);
514 }
515 }
516
517
518 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
519 Bytecodes::Code code = op->bytecode();
520 LIR_Opr src = op->in_opr(),
521 dst = op->result_opr();
522
523 switch(code) {
524 case Bytecodes::_i2l: {
525 __ extsw(dst->as_register_lo(), src->as_register());
526 break;
527 }
528 case Bytecodes::_l2i: {
529 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
530 break;
531 }
532 case Bytecodes::_i2b: {
533 __ extsb(dst->as_register(), src->as_register());
534 break;
535 }
536 case Bytecodes::_i2c: {
537 __ clrldi(dst->as_register(), src->as_register(), 64-16);
538 break;
539 }
540 case Bytecodes::_i2s: {
541 __ extsh(dst->as_register(), src->as_register());
542 break;
543 }
544 case Bytecodes::_i2d:{
545 FloatRegister rdst = dst->as_double_reg();
546 // move src to dst register
547 __ mtfprwa(rdst, src->as_register());
548 __ fcfid(rdst, rdst);
549 break;
550 }
551 case Bytecodes::_l2d: {
552 FloatRegister rdst = dst->as_double_reg();
553 // move src to dst register
554 __ mtfprd(rdst, src->as_register_lo());
555 __ fcfid(rdst, rdst);
556 break;
557 }
558 case Bytecodes::_i2f:{
559 FloatRegister rdst = dst->as_float_reg();
560 // move src to dst register
561 __ mtfprwa(rdst, src->as_register());
562 __ fcfids(rdst, rdst);
563 break;
564 }
565 case Bytecodes::_l2f: {
566 FloatRegister rdst = dst->as_float_reg();
567 // move src to dst register
568 __ mtfprd(rdst, src->as_register_lo());
569 __ fcfids(rdst, rdst);
570 break;
571 }
572 case Bytecodes::_f2d: {
573 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
574 break;
575 }
576 case Bytecodes::_d2f: {
577 __ frsp(dst->as_float_reg(), src->as_double_reg());
578 break;
579 }
580 case Bytecodes::_d2i:
581 case Bytecodes::_f2i: {
582 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
583 Label L;
584 // Result must be 0 if value is NaN; test by comparing value to itself.
585 __ fcmpu(CR0, rsrc, rsrc);
586 __ li(dst->as_register(), 0);
587 __ bso(CR0, L);
588 __ fctiwz(rsrc, rsrc); // USE_KILL
589 __ mffprd(dst->as_register(), rsrc);
590 __ bind(L);
591 break;
592 }
593 case Bytecodes::_d2l:
594 case Bytecodes::_f2l: {
595 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
596 Label L;
597 // Result must be 0 if value is NaN; test by comparing value to itself.
598 __ fcmpu(CR0, rsrc, rsrc);
599 __ li(dst->as_register_lo(), 0);
600 __ bso(CR0, L);
601 __ fctidz(rsrc, rsrc); // USE_KILL
602 __ mffprd(dst->as_register_lo(), rsrc);
603 __ bind(L);
604 break;
605 }
606
607 default: ShouldNotReachHere();
608 }
609 }
610
611
612 void LIR_Assembler::align_call(LIR_Code) {
613 // do nothing since all instructions are word aligned on ppc
614 }
615
616
617 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
618 int start_offset = __ offset();
619 // Put the entry point as a constant into the constant pool.
620 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
621 if (entry_point_toc_addr == nullptr) {
622 bailout("const section overflow");
623 return false;
624 }
625 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
626
627 // Emit the trampoline stub which will be related to the branch-and-link below.
628 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
629 if (!stub) {
630 bailout("no space for trampoline stub");
631 return false;
632 }
633 return true;
634 }
635
636
637 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
638 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
639
640 bool success = emit_trampoline_stub_for_call(op->addr());
641 if (!success) { return; }
642
643 __ relocate(rtype);
644 // Note: At this point we do not have the address of the trampoline
645 // stub, and the entry point might be too far away for bl, so __ pc()
646 // serves as dummy and the bl will be patched later.
647 __ code()->set_insts_mark();
648 __ bl(__ pc());
649 add_call_info(code_offset(), op->info());
650 __ post_call_nop();
651 }
652
653
654 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
655 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
656
657 // Virtual call relocation will point to ic load.
658 address virtual_call_meta_addr = __ pc();
659 // Load a clear inline cache.
660 AddressLiteral empty_ic((address) Universe::non_oop_word());
661 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
662 if (!success) {
663 bailout("const section overflow");
664 return;
665 }
666 // Call to fixup routine. Fixup routine uses ScopeDesc info
667 // to determine who we intended to call.
668 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
669
670 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
671 if (!success) { return; }
672
673 // Note: At this point we do not have the address of the trampoline
674 // stub, and the entry point might be too far away for bl, so __ pc()
675 // serves as dummy and the bl will be patched later.
676 __ bl(__ pc());
677 add_call_info(code_offset(), op->info());
678 __ post_call_nop();
679 }
680
681 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
682 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
683 __ null_check(addr, stub->entry());
684 append_code_stub(stub);
685 }
686
687
688 // Attention: caller must encode oop if needed
689 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
690 int store_offset;
691 if (!Assembler::is_simm16(offset)) {
692 // For offsets larger than a simm16 we setup the offset.
693 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
694 __ load_const_optimized(R0, offset);
695 store_offset = store(from_reg, base, R0, type, wide);
696 } else {
697 store_offset = code_offset();
698 switch (type) {
699 case T_BOOLEAN: // fall through
700 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
701 case T_CHAR :
702 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
703 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
704 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
705 case T_ADDRESS:
706 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
707 case T_ARRAY : // fall through
708 case T_OBJECT:
709 {
710 if (UseCompressedOops && !wide) {
711 // Encoding done in caller
712 __ stw(from_reg->as_register(), offset, base);
713 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
714 } else {
715 __ std(from_reg->as_register(), offset, base);
716 if (VerifyOops) {
717 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
718 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
719 }
720 }
721 break;
722 }
723 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
724 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
725 default : ShouldNotReachHere();
726 }
727 }
728 return store_offset;
729 }
730
731
732 // Attention: caller must encode oop if needed
733 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
734 int store_offset = code_offset();
735 switch (type) {
736 case T_BOOLEAN: // fall through
737 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
738 case T_CHAR :
739 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
740 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
741 case T_LONG :
742 #ifdef _LP64
743 __ stdx(from_reg->as_register_lo(), base, disp);
744 #else
745 Unimplemented();
746 #endif
747 break;
748 case T_ADDRESS:
749 __ stdx(from_reg->as_register(), base, disp);
750 break;
751 case T_ARRAY : // fall through
752 case T_OBJECT:
753 {
754 if (UseCompressedOops && !wide) {
755 // Encoding done in caller.
756 __ stwx(from_reg->as_register(), base, disp);
757 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
758 } else {
759 __ stdx(from_reg->as_register(), base, disp);
760 if (VerifyOops) {
761 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
762 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
763 }
764 }
765 break;
766 }
767 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
768 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
769 default : ShouldNotReachHere();
770 }
771 return store_offset;
772 }
773
774
775 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
776 int load_offset;
777 if (!Assembler::is_simm16(offset)) {
778 // For offsets larger than a simm16 we setup the offset.
779 __ load_const_optimized(R0, offset);
780 load_offset = load(base, R0, to_reg, type, wide);
781 } else {
782 load_offset = code_offset();
783 switch(type) {
784 case T_BOOLEAN: // fall through
785 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
786 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
787 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
788 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
789 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
790 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
791 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
792 case T_ADDRESS:
793 __ ld(to_reg->as_register(), offset, base);
794 break;
795 case T_ARRAY : // fall through
796 case T_OBJECT:
797 {
798 if (UseCompressedOops && !wide) {
799 __ lwz(to_reg->as_register(), offset, base);
800 __ decode_heap_oop(to_reg->as_register());
801 } else {
802 __ ld(to_reg->as_register(), offset, base);
803 }
804 break;
805 }
806 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
807 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
808 default : ShouldNotReachHere();
809 }
810 }
811 return load_offset;
812 }
813
814
815 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
816 int load_offset = code_offset();
817 switch(type) {
818 case T_BOOLEAN: // fall through
819 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
820 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
821 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
822 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
823 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
824 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
825 case T_ARRAY : // fall through
826 case T_OBJECT:
827 {
828 if (UseCompressedOops && !wide) {
829 __ lwzx(to_reg->as_register(), base, disp);
830 __ decode_heap_oop(to_reg->as_register());
831 } else {
832 __ ldx(to_reg->as_register(), base, disp);
833 }
834 break;
835 }
836 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
837 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
838 case T_LONG :
839 #ifdef _LP64
840 __ ldx(to_reg->as_register_lo(), base, disp);
841 #else
842 Unimplemented();
843 #endif
844 break;
845 default : ShouldNotReachHere();
846 }
847 return load_offset;
848 }
849
850
851 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
852 LIR_Const* c = src->as_constant_ptr();
853 Register src_reg = R0;
854 switch (c->type()) {
855 case T_INT:
856 case T_FLOAT: {
857 int value = c->as_jint_bits();
858 __ load_const_optimized(src_reg, value);
859 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
860 __ stw(src_reg, addr);
861 break;
862 }
863 case T_ADDRESS: {
864 int value = c->as_jint_bits();
865 __ load_const_optimized(src_reg, value);
866 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
867 __ std(src_reg, addr);
868 break;
869 }
870 case T_OBJECT: {
871 jobject2reg(c->as_jobject(), src_reg);
872 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
873 __ std(src_reg, addr);
874 break;
875 }
876 case T_LONG:
877 case T_DOUBLE: {
878 int value = c->as_jlong_bits();
879 __ load_const_optimized(src_reg, value);
880 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
881 __ std(src_reg, addr);
882 break;
883 }
884 default:
885 Unimplemented();
886 }
887 }
888
889
890 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
891 LIR_Const* c = src->as_constant_ptr();
892 LIR_Address* addr = dest->as_address_ptr();
893 Register base = addr->base()->as_pointer_register();
894 LIR_Opr tmp = LIR_OprFact::illegalOpr;
895 int offset = -1;
896 // Null check for large offsets in LIRGenerator::do_StoreField.
897 bool needs_explicit_null_check = !ImplicitNullChecks;
898
899 if (info != nullptr && needs_explicit_null_check) {
900 explicit_null_check(base, info);
901 }
902
903 switch (c->type()) {
904 case T_FLOAT: type = T_INT;
905 case T_INT:
906 case T_ADDRESS: {
907 tmp = FrameMap::R0_opr;
908 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
909 break;
910 }
911 case T_DOUBLE: type = T_LONG;
912 case T_LONG: {
913 tmp = FrameMap::R0_long_opr;
914 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
915 break;
916 }
917 case T_OBJECT: {
918 tmp = FrameMap::R0_opr;
919 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
920 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
921 // Don't care about sign extend (will use stw).
922 __ lis(R0, 0); // Will get patched.
923 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
924 __ ori(R0, R0, 0); // Will get patched.
925 } else {
926 jobject2reg(c->as_jobject(), R0);
927 }
928 break;
929 }
930 default:
931 Unimplemented();
932 }
933
934 // Handle either reg+reg or reg+disp address.
935 if (addr->index()->is_valid()) {
936 assert(addr->disp() == 0, "must be zero");
937 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
938 } else {
939 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
940 offset = store(tmp, base, addr->disp(), type, wide);
941 }
942
943 if (info != nullptr) {
944 assert(offset != -1, "offset should've been set");
945 if (!needs_explicit_null_check) {
946 add_debug_info_for_null_check(offset, info);
947 }
948 }
949 }
950
951
952 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
953 LIR_Const* c = src->as_constant_ptr();
954 LIR_Opr to_reg = dest;
955
956 switch (c->type()) {
957 case T_INT: {
958 assert(patch_code == lir_patch_none, "no patching handled here");
959 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
960 break;
961 }
962 case T_ADDRESS: {
963 assert(patch_code == lir_patch_none, "no patching handled here");
964 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
965 break;
966 }
967 case T_LONG: {
968 assert(patch_code == lir_patch_none, "no patching handled here");
969 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
970 break;
971 }
972
973 case T_OBJECT: {
974 if (patch_code == lir_patch_none) {
975 jobject2reg(c->as_jobject(), to_reg->as_register());
976 } else {
977 jobject2reg_with_patching(to_reg->as_register(), info);
978 }
979 break;
980 }
981
982 case T_METADATA:
983 {
984 if (patch_code == lir_patch_none) {
985 metadata2reg(c->as_metadata(), to_reg->as_register());
986 } else {
987 klass2reg_with_patching(to_reg->as_register(), info);
988 }
989 }
990 break;
991
992 case T_FLOAT:
993 {
994 if (to_reg->is_single_fpu()) {
995 address const_addr = __ float_constant(c->as_jfloat());
996 if (const_addr == nullptr) {
997 bailout("const section overflow");
998 break;
999 }
1000 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1001 __ relocate(rspec);
1002 __ load_const(R0, const_addr);
1003 __ lfsx(to_reg->as_float_reg(), R0);
1004 } else {
1005 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1006 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1007 }
1008 }
1009 break;
1010
1011 case T_DOUBLE:
1012 {
1013 if (to_reg->is_double_fpu()) {
1014 address const_addr = __ double_constant(c->as_jdouble());
1015 if (const_addr == nullptr) {
1016 bailout("const section overflow");
1017 break;
1018 }
1019 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1020 __ relocate(rspec);
1021 __ load_const(R0, const_addr);
1022 __ lfdx(to_reg->as_double_reg(), R0);
1023 } else {
1024 assert(to_reg->is_double_cpu(), "Must be a long register.");
1025 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1026 }
1027 }
1028 break;
1029
1030 default:
1031 ShouldNotReachHere();
1032 }
1033 }
1034
1035
1036 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1037 Unimplemented(); return Address();
1038 }
1039
1040
1041 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1042 if (addr->index()->is_illegal()) {
1043 return (RegisterOrConstant)(addr->disp());
1044 } else {
1045 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1046 }
1047 }
1048
1049
1050 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1051 const Register tmp = R0;
1052 switch (type) {
1053 case T_INT:
1054 case T_FLOAT: {
1055 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1056 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1057 __ lwz(tmp, from);
1058 __ stw(tmp, to);
1059 break;
1060 }
1061 case T_ADDRESS:
1062 case T_OBJECT: {
1063 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1064 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1065 __ ld(tmp, from);
1066 __ std(tmp, to);
1067 break;
1068 }
1069 case T_LONG:
1070 case T_DOUBLE: {
1071 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1072 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1073 __ ld(tmp, from);
1074 __ std(tmp, to);
1075 break;
1076 }
1077
1078 default:
1079 ShouldNotReachHere();
1080 }
1081 }
1082
1083
1084 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1085 Unimplemented(); return Address();
1086 }
1087
1088
1089 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1090 Unimplemented(); return Address();
1091 }
1092
1093
1094 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1095 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1096
1097 assert(type != T_METADATA, "load of metadata ptr not supported");
1098 LIR_Address* addr = src_opr->as_address_ptr();
1099 LIR_Opr to_reg = dest;
1100
1101 Register src = addr->base()->as_pointer_register();
1102 Register disp_reg = noreg;
1103 int disp_value = addr->disp();
1104 bool needs_patching = (patch_code != lir_patch_none);
1105 // null check for large offsets in LIRGenerator::do_LoadField
1106 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1107
1108 if (info != nullptr && needs_explicit_null_check) {
1109 explicit_null_check(src, info);
1110 }
1111
1112 if (addr->base()->type() == T_OBJECT) {
1113 __ verify_oop(src, FILE_AND_LINE);
1114 }
1115
1116 PatchingStub* patch = nullptr;
1117 if (needs_patching) {
1118 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1119 assert(!to_reg->is_double_cpu() ||
1120 patch_code == lir_patch_none ||
1121 patch_code == lir_patch_normal, "patching doesn't match register");
1122 }
1123
1124 if (addr->index()->is_illegal()) {
1125 if (!Assembler::is_simm16(disp_value)) {
1126 if (needs_patching) {
1127 __ load_const32(R0, 0); // patchable int
1128 } else {
1129 __ load_const_optimized(R0, disp_value);
1130 }
1131 disp_reg = R0;
1132 }
1133 } else {
1134 disp_reg = addr->index()->as_pointer_register();
1135 assert(disp_value == 0, "can't handle 3 operand addresses");
1136 }
1137
1138 // Remember the offset of the load. The patching_epilog must be done
1139 // before the call to add_debug_info, otherwise the PcDescs don't get
1140 // entered in increasing order.
1141 int offset;
1142
1143 if (disp_reg == noreg) {
1144 assert(Assembler::is_simm16(disp_value), "should have set this up");
1145 offset = load(src, disp_value, to_reg, type, wide);
1146 } else {
1147 offset = load(src, disp_reg, to_reg, type, wide);
1148 }
1149
1150 if (patch != nullptr) {
1151 patching_epilog(patch, patch_code, src, info);
1152 }
1153 if (info != nullptr && !needs_explicit_null_check) {
1154 add_debug_info_for_null_check(offset, info);
1155 }
1156 }
1157
1158
1159 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1160 Address addr;
1161 if (src->is_single_word()) {
1162 addr = frame_map()->address_for_slot(src->single_stack_ix());
1163 } else if (src->is_double_word()) {
1164 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1165 }
1166
1167 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1168 }
1169
1170
1171 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) {
1172 Address addr;
1173 if (dest->is_single_word()) {
1174 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1175 } else if (dest->is_double_word()) {
1176 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1177 }
1178
1179 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1180 }
1181
1182
1183 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1184 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1185 if (from_reg->is_double_fpu()) {
1186 // double to double moves
1187 assert(to_reg->is_double_fpu(), "should match");
1188 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1189 } else {
1190 // float to float moves
1191 assert(to_reg->is_single_fpu(), "should match");
1192 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1193 }
1194 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1195 if (from_reg->is_double_cpu()) {
1196 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1197 } else if (to_reg->is_double_cpu()) {
1198 // int to int moves
1199 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1200 } else {
1201 // int to int moves
1202 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1203 }
1204 } else {
1205 ShouldNotReachHere();
1206 }
1207 if (is_reference_type(to_reg->type())) {
1208 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1209 }
1210 }
1211
1212
1213 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1214 LIR_PatchCode patch_code, CodeEmitInfo* info,
1215 bool wide) {
1216 assert(type != T_METADATA, "store of metadata ptr not supported");
1217 LIR_Address* addr = dest->as_address_ptr();
1218
1219 Register src = addr->base()->as_pointer_register();
1220 Register disp_reg = noreg;
1221 int disp_value = addr->disp();
1222 bool needs_patching = (patch_code != lir_patch_none);
1223 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1224 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1225 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1226 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1227 // Null check for large offsets in LIRGenerator::do_StoreField.
1228 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1229
1230 if (info != nullptr && needs_explicit_null_check) {
1231 explicit_null_check(src, info);
1232 }
1233
1234 if (addr->base()->is_oop_register()) {
1235 __ verify_oop(src, FILE_AND_LINE);
1236 }
1237
1238 PatchingStub* patch = nullptr;
1239 if (needs_patching) {
1240 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1241 assert(!from_reg->is_double_cpu() ||
1242 patch_code == lir_patch_none ||
1243 patch_code == lir_patch_normal, "patching doesn't match register");
1244 }
1245
1246 if (addr->index()->is_illegal()) {
1247 if (load_disp) {
1248 disp_reg = use_R29 ? R29_TOC : R0;
1249 if (needs_patching) {
1250 __ load_const32(disp_reg, 0); // patchable int
1251 } else {
1252 __ load_const_optimized(disp_reg, disp_value);
1253 }
1254 }
1255 } else {
1256 disp_reg = addr->index()->as_pointer_register();
1257 assert(disp_value == 0, "can't handle 3 operand addresses");
1258 }
1259
1260 // remember the offset of the store. The patching_epilog must be done
1261 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1262 // entered in increasing order.
1263 int offset;
1264
1265 if (compress_oop) {
1266 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1267 from_reg = FrameMap::as_opr(co);
1268 }
1269
1270 if (disp_reg == noreg) {
1271 assert(Assembler::is_simm16(disp_value), "should have set this up");
1272 offset = store(from_reg, src, disp_value, type, wide);
1273 } else {
1274 offset = store(from_reg, src, disp_reg, type, wide);
1275 }
1276
1277 if (use_R29) {
1278 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1279 }
1280
1281 if (patch != nullptr) {
1282 patching_epilog(patch, patch_code, src, info);
1283 }
1284
1285 if (info != nullptr && !needs_explicit_null_check) {
1286 add_debug_info_for_null_check(offset, info);
1287 }
1288 }
1289
1290
1291 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1292 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1293 const Register temp = R12;
1294
1295 // Pop the stack before the safepoint code.
1296 int frame_size = initial_frame_size_in_bytes();
1297 if (Assembler::is_simm(frame_size, 16)) {
1298 __ addi(R1_SP, R1_SP, frame_size);
1299 } else {
1300 __ pop_frame();
1301 }
1302
1303 // Restore return pc relative to callers' sp.
1304 __ ld(return_pc, _abi0(lr), R1_SP);
1305 // Move return pc to LR.
1306 __ mtlr(return_pc);
1307
1308 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1309 __ reserved_stack_check(return_pc);
1310 }
1311
1312 // We need to mark the code position where the load from the safepoint
1313 // polling page was emitted as relocInfo::poll_return_type here.
1314 if (!UseSIGTRAP) {
1315 code_stub->set_safepoint_offset(__ offset());
1316 __ relocate(relocInfo::poll_return_type);
1317 }
1318 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1319
1320 // Return.
1321 __ blr();
1322 }
1323
1324
1325 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1326 const Register poll_addr = tmp->as_register();
1327 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1328 if (info != nullptr) {
1329 add_debug_info_for_branch(info);
1330 }
1331 int offset = __ offset();
1332 __ relocate(relocInfo::poll_type);
1333 __ load_from_polling_page(poll_addr);
1334
1335 return offset;
1336 }
1337
1338
1339 void LIR_Assembler::emit_static_call_stub() {
1340 address call_pc = __ pc();
1341 address stub = __ start_a_stub(static_call_stub_size());
1342 if (stub == nullptr) {
1343 bailout("static call stub overflow");
1344 return;
1345 }
1346
1347 // For java_to_interp stubs we use R11_scratch1 as scratch register
1348 // and in call trampoline stubs we use R12_scratch2. This way we
1349 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1350 const Register reg_scratch = R11_scratch1;
1351
1352 // Create a static stub relocation which relates this stub
1353 // with the call instruction at insts_call_instruction_offset in the
1354 // instructions code-section.
1355 int start = __ offset();
1356 __ relocate(static_stub_Relocation::spec(call_pc));
1357
1358 // Now, create the stub's code:
1359 // - load the TOC
1360 // - load the inline cache oop from the constant pool
1361 // - load the call target from the constant pool
1362 // - call
1363 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1364 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1365 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1366
1367 if (ReoptimizeCallSequences) {
1368 __ b64_patchable((address)-1, relocInfo::none);
1369 } else {
1370 AddressLiteral a((address)-1);
1371 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1372 __ mtctr(reg_scratch);
1373 __ bctr();
1374 }
1375 if (!success) {
1376 bailout("const section overflow");
1377 return;
1378 }
1379
1380 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1381 __ end_a_stub();
1382 }
1383
1384
1385 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1386 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1387 if (opr1->is_single_fpu()) {
1388 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1389 } else if (opr1->is_double_fpu()) {
1390 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1391 } else if (opr1->is_single_cpu()) {
1392 if (opr2->is_constant()) {
1393 switch (opr2->as_constant_ptr()->type()) {
1394 case T_INT:
1395 {
1396 jint con = opr2->as_constant_ptr()->as_jint();
1397 if (unsigned_comp) {
1398 if (Assembler::is_uimm(con, 16)) {
1399 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1400 } else {
1401 __ load_const_optimized(R0, con);
1402 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1403 }
1404 } else {
1405 if (Assembler::is_simm(con, 16)) {
1406 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1407 } else {
1408 __ load_const_optimized(R0, con);
1409 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1410 }
1411 }
1412 }
1413 break;
1414
1415 case T_OBJECT:
1416 // There are only equal/notequal comparisons on objects.
1417 {
1418 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1419 jobject con = opr2->as_constant_ptr()->as_jobject();
1420 if (con == nullptr) {
1421 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1422 } else {
1423 jobject2reg(con, R0);
1424 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1425 }
1426 }
1427 break;
1428
1429 case T_METADATA:
1430 // We only need, for now, comparison with null for metadata.
1431 {
1432 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1433 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1434 if (p == nullptr) {
1435 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1436 } else {
1437 ShouldNotReachHere();
1438 }
1439 }
1440 break;
1441
1442 default:
1443 ShouldNotReachHere();
1444 break;
1445 }
1446 } else {
1447 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1448 if (is_reference_type(opr1->type())) {
1449 // There are only equal/notequal comparisons on objects.
1450 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1451 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1452 } else {
1453 if (unsigned_comp) {
1454 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1455 } else {
1456 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1457 }
1458 }
1459 }
1460 } else if (opr1->is_double_cpu()) {
1461 if (opr2->is_constant()) {
1462 jlong con = opr2->as_constant_ptr()->as_jlong();
1463 if (unsigned_comp) {
1464 if (Assembler::is_uimm(con, 16)) {
1465 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1466 } else {
1467 __ load_const_optimized(R0, con);
1468 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1469 }
1470 } else {
1471 if (Assembler::is_simm(con, 16)) {
1472 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1473 } else {
1474 __ load_const_optimized(R0, con);
1475 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1476 }
1477 }
1478 } else if (opr2->is_register()) {
1479 if (unsigned_comp) {
1480 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1481 } else {
1482 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1483 }
1484 } else {
1485 ShouldNotReachHere();
1486 }
1487 } else {
1488 ShouldNotReachHere();
1489 }
1490 }
1491
1492
1493 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1494 const Register Rdst = dst->as_register();
1495 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1496 bool is_unordered_less = (code == lir_ucmp_fd2i);
1497 if (left->is_single_fpu()) {
1498 __ fcmpu(CR0, left->as_float_reg(), right->as_float_reg());
1499 } else if (left->is_double_fpu()) {
1500 __ fcmpu(CR0, left->as_double_reg(), right->as_double_reg());
1501 } else {
1502 ShouldNotReachHere();
1503 }
1504 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1505 } else if (code == lir_cmp_l2i) {
1506 __ cmpd(CR0, left->as_register_lo(), right->as_register_lo());
1507 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1508 } else {
1509 ShouldNotReachHere();
1510 }
1511 }
1512
1513
1514 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1515 if (src->is_constant()) {
1516 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1517 } else if (src->is_register()) {
1518 lasm->reg2reg(src, dst);
1519 } else if (src->is_stack()) {
1520 lasm->stack2reg(src, dst, dst->type());
1521 } else {
1522 ShouldNotReachHere();
1523 }
1524 }
1525
1526 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1527 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1528 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1529
1530 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1531 load_to_reg(this, opr1, result); // Condition doesn't matter.
1532 return;
1533 }
1534
1535 bool positive = false;
1536 Assembler::Condition cond = Assembler::equal;
1537 switch (condition) {
1538 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1539 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1540 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1541 case lir_cond_belowEqual:
1542 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1543 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1544 case lir_cond_aboveEqual:
1545 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1546 default: ShouldNotReachHere();
1547 }
1548
1549 if (result->is_cpu_register()) {
1550 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1551 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1552
1553 // We can use result_reg to load one operand if not already in register.
1554 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1555 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1556
1557 if (first != second) {
1558 if (!o1_is_reg) {
1559 load_to_reg(this, opr1, result);
1560 }
1561
1562 if (!o2_is_reg) {
1563 load_to_reg(this, opr2, result);
1564 }
1565
1566 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1567 return;
1568 }
1569 } // isel
1570
1571 load_to_reg(this, opr1, result);
1572
1573 Label skip;
1574 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1575 int bi = Assembler::bi0(BOOL_RESULT, cond);
1576 __ bc(bo, bi, skip);
1577
1578 load_to_reg(this, opr2, result);
1579 __ bind(skip);
1580 }
1581
1582
1583 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1584 CodeEmitInfo* info) {
1585 assert(info == nullptr, "unused on this code path");
1586 assert(left->is_register(), "wrong items state");
1587 assert(dest->is_register(), "wrong items state");
1588
1589 if (right->is_register()) {
1590 if (dest->is_float_kind()) {
1591
1592 FloatRegister lreg, rreg, res;
1593 if (right->is_single_fpu()) {
1594 lreg = left->as_float_reg();
1595 rreg = right->as_float_reg();
1596 res = dest->as_float_reg();
1597 switch (code) {
1598 case lir_add: __ fadds(res, lreg, rreg); break;
1599 case lir_sub: __ fsubs(res, lreg, rreg); break;
1600 case lir_mul: __ fmuls(res, lreg, rreg); break;
1601 case lir_div: __ fdivs(res, lreg, rreg); break;
1602 default: ShouldNotReachHere();
1603 }
1604 } else {
1605 lreg = left->as_double_reg();
1606 rreg = right->as_double_reg();
1607 res = dest->as_double_reg();
1608 switch (code) {
1609 case lir_add: __ fadd(res, lreg, rreg); break;
1610 case lir_sub: __ fsub(res, lreg, rreg); break;
1611 case lir_mul: __ fmul(res, lreg, rreg); break;
1612 case lir_div: __ fdiv(res, lreg, rreg); break;
1613 default: ShouldNotReachHere();
1614 }
1615 }
1616
1617 } else if (dest->is_double_cpu()) {
1618
1619 Register dst_lo = dest->as_register_lo();
1620 Register op1_lo = left->as_pointer_register();
1621 Register op2_lo = right->as_pointer_register();
1622
1623 switch (code) {
1624 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1625 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1626 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1627 default: ShouldNotReachHere();
1628 }
1629 } else {
1630 assert (right->is_single_cpu(), "Just Checking");
1631
1632 Register lreg = left->as_register();
1633 Register res = dest->as_register();
1634 Register rreg = right->as_register();
1635 switch (code) {
1636 case lir_add: __ add (res, lreg, rreg); break;
1637 case lir_sub: __ sub (res, lreg, rreg); break;
1638 case lir_mul: __ mullw(res, lreg, rreg); break;
1639 default: ShouldNotReachHere();
1640 }
1641 }
1642 } else {
1643 assert (right->is_constant(), "must be constant");
1644
1645 if (dest->is_single_cpu()) {
1646 Register lreg = left->as_register();
1647 Register res = dest->as_register();
1648 int simm16 = right->as_constant_ptr()->as_jint();
1649
1650 switch (code) {
1651 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1652 simm16 = -simm16;
1653 case lir_add: if (res == lreg && simm16 == 0) break;
1654 __ addi(res, lreg, simm16); break;
1655 case lir_mul: if (res == lreg && simm16 == 1) break;
1656 __ mulli(res, lreg, simm16); break;
1657 default: ShouldNotReachHere();
1658 }
1659 } else {
1660 Register lreg = left->as_pointer_register();
1661 Register res = dest->as_register_lo();
1662 long con = right->as_constant_ptr()->as_jlong();
1663 assert(Assembler::is_simm16(con), "must be simm16");
1664
1665 switch (code) {
1666 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1667 con = -con;
1668 case lir_add: if (res == lreg && con == 0) break;
1669 __ addi(res, lreg, (int)con); break;
1670 case lir_mul: if (res == lreg && con == 1) break;
1671 __ mulli(res, lreg, (int)con); break;
1672 default: ShouldNotReachHere();
1673 }
1674 }
1675 }
1676 }
1677
1678
1679 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1680 switch (code) {
1681 case lir_sqrt: {
1682 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1683 break;
1684 }
1685 case lir_abs: {
1686 __ fabs(dest->as_double_reg(), value->as_double_reg());
1687 break;
1688 }
1689 case lir_f2hf: {
1690 __ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1691 break;
1692 }
1693 case lir_hf2f: {
1694 __ hf2f(dest->as_float_reg(), value.as_register());
1695 break;
1696 }
1697 default: {
1698 ShouldNotReachHere();
1699 break;
1700 }
1701 }
1702 }
1703
1704
1705 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1706 if (right->is_constant()) { // see do_LogicOp
1707 long uimm;
1708 Register d, l;
1709 if (dest->is_single_cpu()) {
1710 uimm = right->as_constant_ptr()->as_jint();
1711 d = dest->as_register();
1712 l = left->as_register();
1713 } else {
1714 uimm = right->as_constant_ptr()->as_jlong();
1715 d = dest->as_register_lo();
1716 l = left->as_register_lo();
1717 }
1718 long uimms = (unsigned long)uimm >> 16,
1719 uimmss = (unsigned long)uimm >> 32;
1720
1721 switch (code) {
1722 case lir_logic_and:
1723 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1724 __ andi(d, l, uimm); // special cases
1725 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1726 else { __ andi_(d, l, uimm); }
1727 break;
1728
1729 case lir_logic_or:
1730 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1731 else { __ ori(d, l, uimm); }
1732 break;
1733
1734 case lir_logic_xor:
1735 if (uimm == -1) { __ nand(d, l, l); } // special case
1736 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1737 else { __ xori(d, l, uimm); }
1738 break;
1739
1740 default: ShouldNotReachHere();
1741 }
1742 } else {
1743 assert(right->is_register(), "right should be in register");
1744
1745 if (dest->is_single_cpu()) {
1746 switch (code) {
1747 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1748 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1749 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1750 default: ShouldNotReachHere();
1751 }
1752 } else {
1753 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1754 left->as_register_lo();
1755 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1756 right->as_register_lo();
1757
1758 switch (code) {
1759 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1760 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1761 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1762 default: ShouldNotReachHere();
1763 }
1764 }
1765 }
1766 }
1767
1768
1769 int LIR_Assembler::shift_amount(BasicType t) {
1770 int elem_size = type2aelembytes(t);
1771 switch (elem_size) {
1772 case 1 : return 0;
1773 case 2 : return 1;
1774 case 4 : return 2;
1775 case 8 : return 3;
1776 }
1777 ShouldNotReachHere();
1778 return -1;
1779 }
1780
1781
1782 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1783 info->add_register_oop(exceptionOop);
1784
1785 // Reuse the debug info from the safepoint poll for the throw op itself.
1786 address pc_for_athrow = __ pc();
1787 int pc_for_athrow_offset = __ offset();
1788 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1789 //__ relocate(rspec);
1790 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1791 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1792 add_call_info(pc_for_athrow_offset, info); // for exception handler
1793
1794 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1795 : StubId::c1_handle_exception_nofpu_id);
1796 //__ load_const_optimized(R0, stub);
1797 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1798 __ mtctr(R0);
1799 __ bctr();
1800 }
1801
1802
1803 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1804 // Note: Not used with EnableDebuggingOnDemand.
1805 assert(exceptionOop->as_register() == R3, "should match");
1806 __ b(_unwind_handler_entry);
1807 }
1808
1809
1810 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1811 Register src = op->src()->as_register();
1812 Register dst = op->dst()->as_register();
1813 Register src_pos = op->src_pos()->as_register();
1814 Register dst_pos = op->dst_pos()->as_register();
1815 Register length = op->length()->as_register();
1816 Register tmp = op->tmp()->as_register();
1817 Register tmp2 = R0;
1818
1819 int flags = op->flags();
1820 ciArrayKlass* default_type = op->expected_type();
1821 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1822 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1823
1824 // Set up the arraycopy stub information.
1825 ArrayCopyStub* stub = op->stub();
1826
1827 // Always do stub if no type information is available. It's ok if
1828 // the known type isn't loaded since the code sanity checks
1829 // in debug mode and the type isn't required when we know the exact type
1830 // also check that the type is an array type.
1831 if (default_type == nullptr) {
1832 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1833 length->is_nonvolatile(), "must preserve");
1834 address copyfunc_addr = StubRoutines::generic_arraycopy();
1835 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1836
1837 // 3 parms are int. Convert to long.
1838 __ mr(R3_ARG1, src);
1839 __ extsw(R4_ARG2, src_pos);
1840 __ mr(R5_ARG3, dst);
1841 __ extsw(R6_ARG4, dst_pos);
1842 __ extsw(R7_ARG5, length);
1843
1844 #ifndef PRODUCT
1845 if (PrintC1Statistics) {
1846 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1847 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1848 __ lwz(R11_scratch1, simm16_offs, tmp);
1849 __ addi(R11_scratch1, R11_scratch1, 1);
1850 __ stw(R11_scratch1, simm16_offs, tmp);
1851 }
1852 #endif
1853 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1854
1855 __ nand(tmp, R3_RET, R3_RET);
1856 __ subf(length, tmp, length);
1857 __ add(src_pos, tmp, src_pos);
1858 __ add(dst_pos, tmp, dst_pos);
1859
1860 __ cmpwi(CR0, R3_RET, 0);
1861 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CR0, Assembler::less), *stub->entry());
1862 __ bind(*stub->continuation());
1863 return;
1864 }
1865
1866 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1867 Label cont, slow, copyfunc;
1868
1869 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1870 LIR_OpArrayCopy::dst_null_check |
1871 LIR_OpArrayCopy::src_pos_positive_check |
1872 LIR_OpArrayCopy::dst_pos_positive_check |
1873 LIR_OpArrayCopy::length_positive_check);
1874
1875 // Use only one conditional branch for simple checks.
1876 if (simple_check_flag_set) {
1877 ConditionRegister combined_check = CR1, tmp_check = CR1;
1878
1879 // Make sure src and dst are non-null.
1880 if (flags & LIR_OpArrayCopy::src_null_check) {
1881 __ cmpdi(combined_check, src, 0);
1882 tmp_check = CR0;
1883 }
1884
1885 if (flags & LIR_OpArrayCopy::dst_null_check) {
1886 __ cmpdi(tmp_check, dst, 0);
1887 if (tmp_check != combined_check) {
1888 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1889 }
1890 tmp_check = CR0;
1891 }
1892
1893 // Clear combined_check.eq if not already used.
1894 if (tmp_check == combined_check) {
1895 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1896 tmp_check = CR0;
1897 }
1898
1899 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1900 // Test src_pos register.
1901 __ cmpwi(tmp_check, src_pos, 0);
1902 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1903 }
1904
1905 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1906 // Test dst_pos register.
1907 __ cmpwi(tmp_check, dst_pos, 0);
1908 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1909 }
1910
1911 if (flags & LIR_OpArrayCopy::length_positive_check) {
1912 // Make sure length isn't negative.
1913 __ cmpwi(tmp_check, length, 0);
1914 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1915 }
1916
1917 __ beq(combined_check, slow);
1918 }
1919
1920 // If the compiler was not able to prove that exact type of the source or the destination
1921 // of the arraycopy is an array type, check at runtime if the source or the destination is
1922 // an instance type.
1923 if (flags & LIR_OpArrayCopy::type_check) {
1924 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1925 __ load_klass(tmp, dst);
1926 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1927 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1928 __ bge(CR0, slow);
1929 }
1930
1931 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1932 __ load_klass(tmp, src);
1933 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1934 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1935 __ bge(CR0, slow);
1936 }
1937 }
1938
1939 // Higher 32bits must be null.
1940 __ extsw(length, length);
1941
1942 __ extsw(src_pos, src_pos);
1943 if (flags & LIR_OpArrayCopy::src_range_check) {
1944 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1945 __ add(tmp, length, src_pos);
1946 __ cmpld(CR0, tmp2, tmp);
1947 __ ble(CR0, slow);
1948 }
1949
1950 __ extsw(dst_pos, dst_pos);
1951 if (flags & LIR_OpArrayCopy::dst_range_check) {
1952 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1953 __ add(tmp, length, dst_pos);
1954 __ cmpld(CR0, tmp2, tmp);
1955 __ ble(CR0, slow);
1956 }
1957
1958 int shift = shift_amount(basic_type);
1959
1960 if (!(flags & LIR_OpArrayCopy::type_check)) {
1961 if (stub != nullptr) {
1962 __ b(cont);
1963 __ bind(slow);
1964 __ b(*stub->entry());
1965 }
1966 } else {
1967 // We don't know the array types are compatible.
1968 if (basic_type != T_OBJECT) {
1969 // Simple test for basic type arrays.
1970 __ cmp_klasses_from_objects(CR0, src, dst, tmp, tmp2);
1971 __ beq(CR0, cont);
1972 } else {
1973 // For object arrays, if src is a sub class of dst then we can
1974 // safely do the copy.
1975 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1976
1977 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1978 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1979
1980 __ load_klass(sub_klass, src);
1981 __ load_klass(super_klass, dst);
1982
1983 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1984 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
1985
1986 address slow_stc = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
1987 //__ load_const_optimized(tmp, slow_stc, tmp2);
1988 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1989 __ mtctr(tmp);
1990 __ bctrl(); // sets CR0
1991 __ beq(CR0, cont);
1992
1993 if (copyfunc_addr != nullptr) { // Use stub if available.
1994 __ bind(copyfunc);
1995 // Src is not a sub class of dst so we have to do a
1996 // per-element check.
1997 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1998 if ((flags & mask) != mask) {
1999 assert(flags & mask, "one of the two should be known to be an object array");
2000
2001 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2002 __ load_klass(tmp, src);
2003 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2004 __ load_klass(tmp, dst);
2005 }
2006
2007 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2008
2009 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2010 __ load_const_optimized(tmp, objArray_lh);
2011 __ cmpw(CR0, tmp, tmp2);
2012 __ bne(CR0, slow);
2013 }
2014
2015 Register src_ptr = R3_ARG1;
2016 Register dst_ptr = R4_ARG2;
2017 Register len = R5_ARG3;
2018 Register chk_off = R6_ARG4;
2019 Register super_k = R7_ARG5;
2020
2021 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2022 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2023 if (shift == 0) {
2024 __ add(src_ptr, src_pos, src_ptr);
2025 __ add(dst_ptr, dst_pos, dst_ptr);
2026 } else {
2027 __ sldi(tmp, src_pos, shift);
2028 __ sldi(tmp2, dst_pos, shift);
2029 __ add(src_ptr, tmp, src_ptr);
2030 __ add(dst_ptr, tmp2, dst_ptr);
2031 }
2032
2033 __ load_klass(tmp, dst);
2034 __ mr(len, length);
2035
2036 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2037 __ ld(super_k, ek_offset, tmp);
2038
2039 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2040 __ lwz(chk_off, sco_offset, super_k);
2041
2042 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2043
2044 #ifndef PRODUCT
2045 if (PrintC1Statistics) {
2046 Label failed;
2047 __ cmpwi(CR0, R3_RET, 0);
2048 __ bne(CR0, failed);
2049 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2050 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2051 __ lwz(R11_scratch1, simm16_offs, tmp);
2052 __ addi(R11_scratch1, R11_scratch1, 1);
2053 __ stw(R11_scratch1, simm16_offs, tmp);
2054 __ bind(failed);
2055 }
2056 #endif
2057
2058 __ nand(tmp, R3_RET, R3_RET);
2059 __ cmpwi(CR0, R3_RET, 0);
2060 __ beq(CR0, *stub->continuation());
2061
2062 #ifndef PRODUCT
2063 if (PrintC1Statistics) {
2064 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2065 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2066 __ lwz(R11_scratch1, simm16_offs, tmp);
2067 __ addi(R11_scratch1, R11_scratch1, 1);
2068 __ stw(R11_scratch1, simm16_offs, tmp);
2069 }
2070 #endif
2071
2072 __ subf(length, tmp, length);
2073 __ add(src_pos, tmp, src_pos);
2074 __ add(dst_pos, tmp, dst_pos);
2075 }
2076 }
2077 __ bind(slow);
2078 __ b(*stub->entry());
2079 }
2080 __ bind(cont);
2081
2082 #ifdef ASSERT
2083 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2084 // Sanity check the known type with the incoming class. For the
2085 // primitive case the types must match exactly with src.klass and
2086 // dst.klass each exactly matching the default type. For the
2087 // object array case, if no type check is needed then either the
2088 // dst type is exactly the expected type and the src type is a
2089 // subtype which we can't check or src is the same array as dst
2090 // but not necessarily exactly of type default_type.
2091 Label known_ok, halt;
2092 metadata2reg(default_type->constant_encoding(), tmp);
2093 __ cmp_klass(CR0, dst, tmp, R11_scratch1, R12_scratch2);
2094 if (basic_type != T_OBJECT) {
2095 __ bne(CR0, halt);
2096 __ cmp_klass(CR0, src, tmp, R11_scratch1, R12_scratch2);
2097 __ beq(CR0, known_ok);
2098 } else {
2099 __ beq(CR0, known_ok);
2100 __ cmpw(CR0, src, dst);
2101 __ beq(CR0, known_ok);
2102 }
2103 __ bind(halt);
2104 __ stop("incorrect type information in arraycopy");
2105 __ bind(known_ok);
2106 }
2107 #endif
2108
2109 #ifndef PRODUCT
2110 if (PrintC1Statistics) {
2111 address counter = Runtime1::arraycopy_count_address(basic_type);
2112 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2113 __ lwz(R11_scratch1, simm16_offs, tmp);
2114 __ addi(R11_scratch1, R11_scratch1, 1);
2115 __ stw(R11_scratch1, simm16_offs, tmp);
2116 }
2117 #endif
2118
2119 Register src_ptr = R3_ARG1;
2120 Register dst_ptr = R4_ARG2;
2121 Register len = R5_ARG3;
2122
2123 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2124 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2125 if (shift == 0) {
2126 __ add(src_ptr, src_pos, src_ptr);
2127 __ add(dst_ptr, dst_pos, dst_ptr);
2128 } else {
2129 __ sldi(tmp, src_pos, shift);
2130 __ sldi(tmp2, dst_pos, shift);
2131 __ add(src_ptr, tmp, src_ptr);
2132 __ add(dst_ptr, tmp2, dst_ptr);
2133 }
2134
2135 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2136 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2137 const char *name;
2138 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2139
2140 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2141 __ mr(len, length);
2142 __ call_c(entry, relocInfo::runtime_call_type);
2143
2144 if (stub != nullptr) {
2145 __ bind(*stub->continuation());
2146 }
2147 }
2148
2149
2150 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2151 if (dest->is_single_cpu()) {
2152 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2153 #ifdef _LP64
2154 if (left->type() == T_OBJECT) {
2155 switch (code) {
2156 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2157 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2158 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2159 default: ShouldNotReachHere();
2160 }
2161 } else
2162 #endif
2163 switch (code) {
2164 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2165 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2166 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2167 default: ShouldNotReachHere();
2168 }
2169 } else {
2170 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2171 switch (code) {
2172 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2173 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2174 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2175 default: ShouldNotReachHere();
2176 }
2177 }
2178 }
2179
2180
2181 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2182 #ifdef _LP64
2183 if (left->type() == T_OBJECT) {
2184 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2185 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2186 else {
2187 switch (code) {
2188 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2189 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2190 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2191 default: ShouldNotReachHere();
2192 }
2193 }
2194 return;
2195 }
2196 #endif
2197
2198 if (dest->is_single_cpu()) {
2199 count = count & 0x1F; // Java spec
2200 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2201 else {
2202 switch (code) {
2203 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2204 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2205 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2206 default: ShouldNotReachHere();
2207 }
2208 }
2209 } else if (dest->is_double_cpu()) {
2210 count = count & 63; // Java spec
2211 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2212 else {
2213 switch (code) {
2214 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2215 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2216 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2217 default: ShouldNotReachHere();
2218 }
2219 }
2220 } else {
2221 ShouldNotReachHere();
2222 }
2223 }
2224
2225
2226 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2227 if (op->init_check()) {
2228 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2229 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2230 } else {
2231 add_debug_info_for_null_check_here(op->stub()->info());
2232 }
2233 __ lbz(op->tmp1()->as_register(),
2234 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2235 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2236 __ cmpwi(CR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2237 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CR0, Assembler::equal), *op->stub()->entry());
2238 }
2239 __ allocate_object(op->obj()->as_register(),
2240 op->tmp1()->as_register(),
2241 op->tmp2()->as_register(),
2242 op->tmp3()->as_register(),
2243 op->header_size(),
2244 op->object_size(),
2245 op->klass()->as_register(),
2246 *op->stub()->entry());
2247
2248 __ bind(*op->stub()->continuation());
2249 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2250 }
2251
2252
2253 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2254 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2255 if (UseSlowPath ||
2256 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2257 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2258 __ b(*op->stub()->entry());
2259 } else {
2260 __ allocate_array(op->obj()->as_register(),
2261 op->len()->as_register(),
2262 op->tmp1()->as_register(),
2263 op->tmp2()->as_register(),
2264 op->tmp3()->as_register(),
2265 arrayOopDesc::base_offset_in_bytes(op->type()),
2266 type2aelembytes(op->type()),
2267 op->klass()->as_register(),
2268 *op->stub()->entry(),
2269 op->zero_array());
2270 }
2271 __ bind(*op->stub()->continuation());
2272 }
2273
2274
2275 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2276 ciMethodData *md, ciProfileData *data,
2277 Register recv, Register tmp1, Label* update_done) {
2278 uint i;
2279 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2280 Label next_test;
2281 // See if the receiver is receiver[n].
2282 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2283 __ verify_klass_ptr(tmp1);
2284 __ cmpd(CR0, recv, tmp1);
2285 __ bne(CR0, next_test);
2286
2287 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2288 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2289 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2290 __ b(*update_done);
2291
2292 __ bind(next_test);
2293 }
2294
2295 // Didn't find receiver; find next empty slot and fill it in.
2296 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2297 Label next_test;
2298 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2299 __ cmpdi(CR0, tmp1, 0);
2300 __ bne(CR0, next_test);
2301 __ li(tmp1, DataLayout::counter_increment);
2302 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2303 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2304 __ b(*update_done);
2305
2306 __ bind(next_test);
2307 }
2308 }
2309
2310
2311 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2312 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2313 md = method->method_data_or_null();
2314 assert(md != nullptr, "Sanity");
2315 data = md->bci_to_data(bci);
2316 assert(data != nullptr, "need data for checkcast");
2317 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2318 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2319 // The offset is large so bias the mdo by the base of the slot so
2320 // that the ld can use simm16s to reference the slots of the data.
2321 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2322 }
2323 }
2324
2325
2326 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2327 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2328 Register k_RInfo = op->tmp1()->as_register();
2329 Register klass_RInfo = op->tmp2()->as_register();
2330 Register Rtmp1 = op->tmp3()->as_register();
2331 Register dst = op->result_opr()->as_register();
2332 ciKlass* k = op->klass();
2333 bool should_profile = op->should_profile();
2334 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2335 bool reg_conflict = false;
2336 if (obj == k_RInfo) {
2337 k_RInfo = dst;
2338 reg_conflict = true;
2339 } else if (obj == klass_RInfo) {
2340 klass_RInfo = dst;
2341 reg_conflict = true;
2342 } else if (obj == Rtmp1) {
2343 Rtmp1 = dst;
2344 reg_conflict = true;
2345 }
2346 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2347
2348 ciMethodData* md = nullptr;
2349 ciProfileData* data = nullptr;
2350 int mdo_offset_bias = 0;
2351 if (should_profile) {
2352 ciMethod* method = op->profiled_method();
2353 assert(method != nullptr, "Should have method");
2354 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2355
2356 Register mdo = k_RInfo;
2357 Register data_val = Rtmp1;
2358 Label not_null;
2359 metadata2reg(md->constant_encoding(), mdo);
2360 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2361 __ cmpdi(CR0, obj, 0);
2362 __ bne(CR0, not_null);
2363 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2364 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2365 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2366 __ b(*obj_is_null);
2367 __ bind(not_null);
2368
2369 Label update_done;
2370 Register recv = klass_RInfo;
2371 __ load_klass(recv, obj);
2372 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2373 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2374 __ ld(Rtmp1, slot_offset, mdo);
2375 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2376 __ std(Rtmp1, slot_offset, mdo);
2377 __ bind(update_done);
2378 } else {
2379 __ cmpdi(CR0, obj, 0);
2380 __ beq(CR0, *obj_is_null);
2381 }
2382
2383 // get object class
2384 __ load_klass(klass_RInfo, obj);
2385
2386 if (k->is_loaded()) {
2387 metadata2reg(k->constant_encoding(), k_RInfo);
2388 } else {
2389 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2390 }
2391
2392 if (op->fast_check()) {
2393 assert_different_registers(klass_RInfo, k_RInfo);
2394 __ cmpd(CR0, k_RInfo, klass_RInfo);
2395 __ beq(CR0, *success);
2396 // Fall through to failure case.
2397 } else {
2398 bool need_slow_path = true;
2399 if (k->is_loaded()) {
2400 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2401 need_slow_path = false;
2402 }
2403 // Perform the fast part of the checking logic.
2404 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2405 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2406 } else {
2407 // Perform the fast part of the checking logic.
2408 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2409 }
2410 if (!need_slow_path) {
2411 __ b(*success);
2412 } else {
2413 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2414 address entry = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2415 // Stub needs fixed registers (tmp1-3).
2416 Register original_k_RInfo = op->tmp1()->as_register();
2417 Register original_klass_RInfo = op->tmp2()->as_register();
2418 Register original_Rtmp1 = op->tmp3()->as_register();
2419 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2420 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2421 __ mr_if_needed(original_k_RInfo, k_RInfo);
2422 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2423 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2424 //__ load_const_optimized(original_Rtmp1, entry, R0);
2425 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2426 __ mtctr(original_Rtmp1);
2427 __ bctrl(); // sets CR0
2428 if (keep_obj_alive) { __ mr(obj, dst); }
2429 __ beq(CR0, *success);
2430 // Fall through to failure case.
2431 }
2432 }
2433
2434 __ bind(*failure);
2435 }
2436
2437
2438 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2439 LIR_Code code = op->code();
2440 if (code == lir_store_check) {
2441 Register value = op->object()->as_register();
2442 Register array = op->array()->as_register();
2443 Register k_RInfo = op->tmp1()->as_register();
2444 Register klass_RInfo = op->tmp2()->as_register();
2445 Register Rtmp1 = op->tmp3()->as_register();
2446 bool should_profile = op->should_profile();
2447
2448 __ verify_oop(value, FILE_AND_LINE);
2449 CodeStub* stub = op->stub();
2450 // Check if it needs to be profiled.
2451 ciMethodData* md = nullptr;
2452 ciProfileData* data = nullptr;
2453 int mdo_offset_bias = 0;
2454 if (should_profile) {
2455 ciMethod* method = op->profiled_method();
2456 assert(method != nullptr, "Should have method");
2457 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2458 }
2459
2460 Label done;
2461
2462 if (should_profile) {
2463 Label not_null;
2464 Register mdo = k_RInfo;
2465 Register data_val = Rtmp1;
2466 metadata2reg(md->constant_encoding(), mdo);
2467 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2468 __ cmpdi(CR0, value, 0);
2469 __ bne(CR0, not_null);
2470 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2471 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2472 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2473 __ b(done);
2474 __ bind(not_null);
2475
2476 Label update_done;
2477 Register recv = klass_RInfo;
2478 __ load_klass(recv, value);
2479 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2480 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2481 __ ld(Rtmp1, slot_offset, mdo);
2482 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2483 __ std(Rtmp1, slot_offset, mdo);
2484 __ bind(update_done);
2485 } else {
2486 __ cmpdi(CR0, value, 0);
2487 __ beq(CR0, done);
2488 }
2489 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2490 explicit_null_check(array, op->info_for_exception());
2491 } else {
2492 add_debug_info_for_null_check_here(op->info_for_exception());
2493 }
2494 __ load_klass(k_RInfo, array);
2495 __ load_klass(klass_RInfo, value);
2496
2497 Label failure;
2498
2499 // Get instance klass.
2500 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2501 // Perform the fast part of the checking logic.
2502 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2503
2504 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2505 const address slow_path = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2506 //__ load_const_optimized(R0, slow_path);
2507 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2508 __ mtctr(R0);
2509 __ bctrl(); // sets CR0
2510 __ beq(CR0, done);
2511
2512 __ bind(failure);
2513 __ b(*stub->entry());
2514 __ align(32, 12);
2515 __ bind(done);
2516
2517 } else if (code == lir_checkcast) {
2518 Label success, failure;
2519 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2520 __ b(*op->stub()->entry());
2521 __ align(32, 12);
2522 __ bind(success);
2523 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2524 } else if (code == lir_instanceof) {
2525 Register dst = op->result_opr()->as_register();
2526 Label success, failure, done;
2527 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2528 __ li(dst, 0);
2529 __ b(done);
2530 __ align(32, 12);
2531 __ bind(success);
2532 __ li(dst, 1);
2533 __ bind(done);
2534 } else {
2535 ShouldNotReachHere();
2536 }
2537 }
2538
2539
2540 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2541 Register addr = op->addr()->as_pointer_register();
2542 Register cmp_value = noreg, new_value = noreg;
2543 bool is_64bit = false;
2544
2545 if (op->code() == lir_cas_long) {
2546 cmp_value = op->cmp_value()->as_register_lo();
2547 new_value = op->new_value()->as_register_lo();
2548 is_64bit = true;
2549 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2550 cmp_value = op->cmp_value()->as_register();
2551 new_value = op->new_value()->as_register();
2552 if (op->code() == lir_cas_obj) {
2553 if (UseCompressedOops) {
2554 Register t1 = op->tmp1()->as_register();
2555 Register t2 = op->tmp2()->as_register();
2556 cmp_value = __ encode_heap_oop(t1, cmp_value);
2557 new_value = __ encode_heap_oop(t2, new_value);
2558 } else {
2559 is_64bit = true;
2560 }
2561 }
2562 } else {
2563 Unimplemented();
2564 }
2565
2566 // There might be a volatile load before this Unsafe CAS.
2567 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2568 __ sync();
2569 } else {
2570 __ lwsync();
2571 }
2572
2573 if (is_64bit) {
2574 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2575 MacroAssembler::MemBarNone,
2576 MacroAssembler::cmpxchgx_hint_atomic_update(),
2577 noreg, nullptr, /*check without ldarx first*/true);
2578 } else {
2579 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2580 MacroAssembler::MemBarNone,
2581 MacroAssembler::cmpxchgx_hint_atomic_update(),
2582 noreg, nullptr, /*check without ldarx first*/true);
2583 }
2584
2585 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2586 __ isync();
2587 } else {
2588 __ sync();
2589 }
2590 }
2591
2592 void LIR_Assembler::breakpoint() {
2593 __ illtrap();
2594 }
2595
2596
2597 void LIR_Assembler::push(LIR_Opr opr) {
2598 Unimplemented();
2599 }
2600
2601 void LIR_Assembler::pop(LIR_Opr opr) {
2602 Unimplemented();
2603 }
2604
2605
2606 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2607 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2608 Register dst = dst_opr->as_register();
2609 Register reg = mon_addr.base();
2610 int offset = mon_addr.disp();
2611 // Compute pointer to BasicLock.
2612 __ add_const_optimized(dst, reg, offset);
2613 }
2614
2615
2616 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2617 Register obj = op->obj_opr()->as_register();
2618 Register hdr = op->hdr_opr()->as_register();
2619 Register lock = op->lock_opr()->as_register();
2620
2621 // Obj may not be an oop.
2622 if (op->code() == lir_lock) {
2623 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2624 // Add debug info for NullPointerException only if one is possible.
2625 if (op->info() != nullptr) {
2626 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2627 explicit_null_check(obj, op->info());
2628 } else {
2629 add_debug_info_for_null_check_here(op->info());
2630 }
2631 }
2632 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2633 } else {
2634 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2635 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2636 }
2637 __ bind(*op->stub()->continuation());
2638 }
2639
2640 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2641 Register obj = op->obj()->as_pointer_register();
2642 Register result = op->result_opr()->as_pointer_register();
2643
2644 CodeEmitInfo* info = op->info();
2645 if (info != nullptr) {
2646 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2647 explicit_null_check(obj, info);
2648 } else {
2649 add_debug_info_for_null_check_here(info);
2650 }
2651 }
2652
2653 __ load_klass(result, obj);
2654 }
2655
2656 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2657 ciMethod* method = op->profiled_method();
2658 int bci = op->profiled_bci();
2659 ciMethod* callee = op->profiled_callee();
2660
2661 // Update counter for all call types.
2662 ciMethodData* md = method->method_data_or_null();
2663 assert(md != nullptr, "Sanity");
2664 ciProfileData* data = md->bci_to_data(bci);
2665 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2666 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2667 Register mdo = op->mdo()->as_register();
2668 #ifdef _LP64
2669 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2670 Register tmp1 = op->tmp1()->as_register_lo();
2671 #else
2672 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2673 Register tmp1 = op->tmp1()->as_register();
2674 #endif
2675 metadata2reg(md->constant_encoding(), mdo);
2676 int mdo_offset_bias = 0;
2677 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2678 data->size_in_bytes())) {
2679 // The offset is large so bias the mdo by the base of the slot so
2680 // that the ld can use simm16s to reference the slots of the data.
2681 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2682 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2683 }
2684
2685 // Perform additional virtual call profiling for invokevirtual and
2686 // invokeinterface bytecodes
2687 if (op->should_profile_receiver_type()) {
2688 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2689 Register recv = op->recv()->as_register();
2690 assert_different_registers(mdo, tmp1, recv);
2691 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2692 ciKlass* known_klass = op->known_holder();
2693 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2694 // We know the type that will be seen at this call site; we can
2695 // statically update the MethodData* rather than needing to do
2696 // dynamic tests on the receiver type.
2697
2698 // NOTE: we should probably put a lock around this search to
2699 // avoid collisions by concurrent compilations.
2700 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2701 uint i;
2702 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2703 ciKlass* receiver = vc_data->receiver(i);
2704 if (known_klass->equals(receiver)) {
2705 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2706 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2707 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2708 return;
2709 }
2710 }
2711
2712 // Receiver type not found in profile data; select an empty slot.
2713
2714 // Note that this is less efficient than it should be because it
2715 // always does a write to the receiver part of the
2716 // VirtualCallData rather than just the first time.
2717 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2718 ciKlass* receiver = vc_data->receiver(i);
2719 if (receiver == nullptr) {
2720 metadata2reg(known_klass->constant_encoding(), tmp1);
2721 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2722
2723 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2724 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2725 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2726 return;
2727 }
2728 }
2729 } else {
2730 __ load_klass(recv, recv);
2731 Label update_done;
2732 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2733 // Receiver did not match any saved receiver and there is no empty row for it.
2734 // Increment total counter to indicate polymorphic case.
2735 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2736 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2737 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2738
2739 __ bind(update_done);
2740 }
2741 } else {
2742 // Static call
2743 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2744 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2745 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2746 }
2747 }
2748
2749
2750 void LIR_Assembler::align_backward_branch_target() {
2751 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2752 }
2753
2754
2755 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2756 // tmp must be unused
2757 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2758 assert(left->is_register(), "can only handle registers");
2759
2760 if (left->is_single_cpu()) {
2761 __ neg(dest->as_register(), left->as_register());
2762 } else if (left->is_single_fpu()) {
2763 __ fneg(dest->as_float_reg(), left->as_float_reg());
2764 } else if (left->is_double_fpu()) {
2765 __ fneg(dest->as_double_reg(), left->as_double_reg());
2766 } else {
2767 assert (left->is_double_cpu(), "Must be a long");
2768 __ neg(dest->as_register_lo(), left->as_register_lo());
2769 }
2770 }
2771
2772
2773 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2774 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2775 // Stubs: Called via rt_call, but dest is a stub address (no FunctionDescriptor).
2776 if (dest == Runtime1::entry_for(StubId::c1_register_finalizer_id) ||
2777 dest == Runtime1::entry_for(StubId::c1_new_multi_array_id ) ||
2778 dest == Runtime1::entry_for(StubId::c1_is_instance_of_id )) {
2779 assert(CodeCache::contains(dest), "simplified call is only for special C1 stubs");
2780 //__ load_const_optimized(R0, dest);
2781 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2782 __ mtctr(R0);
2783 __ bctrl();
2784 if (info != nullptr) {
2785 add_call_info_here(info);
2786 __ post_call_nop();
2787 }
2788 return;
2789 }
2790
2791 __ call_c(dest, relocInfo::runtime_call_type);
2792 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2793 if (info != nullptr) {
2794 add_call_info_here(info);
2795 __ post_call_nop();
2796 }
2797 }
2798
2799
2800 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2801 ShouldNotReachHere(); // Not needed on _LP64.
2802 }
2803
2804 void LIR_Assembler::membar() {
2805 __ fence();
2806 }
2807
2808 void LIR_Assembler::membar_acquire() {
2809 __ acquire();
2810 }
2811
2812 void LIR_Assembler::membar_release() {
2813 __ release();
2814 }
2815
2816 void LIR_Assembler::membar_loadload() {
2817 __ membar(Assembler::LoadLoad);
2818 }
2819
2820 void LIR_Assembler::membar_storestore() {
2821 __ membar(Assembler::StoreStore);
2822 }
2823
2824 void LIR_Assembler::membar_loadstore() {
2825 __ membar(Assembler::LoadStore);
2826 }
2827
2828 void LIR_Assembler::membar_storeload() {
2829 __ membar(Assembler::StoreLoad);
2830 }
2831
2832 void LIR_Assembler::on_spin_wait() {
2833 Unimplemented();
2834 }
2835
2836 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2837 LIR_Address* addr = addr_opr->as_address_ptr();
2838 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2839
2840 if (addr->index()->is_illegal()) {
2841 if (patch_code != lir_patch_none) {
2842 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2843 __ load_const32(R0, 0); // patchable int
2844 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2845 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2846 } else {
2847 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2848 }
2849 } else {
2850 assert(patch_code == lir_patch_none, "Patch code not supported");
2851 assert(addr->disp() == 0, "can't have both: index and disp");
2852 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2853 }
2854 }
2855
2856
2857 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2858 ShouldNotReachHere();
2859 }
2860
2861
2862 #ifdef ASSERT
2863 // Emit run-time assertion.
2864 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2865 Unimplemented();
2866 }
2867 #endif
2868
2869
2870 void LIR_Assembler::peephole(LIR_List* lir) {
2871 // Optimize instruction pairs before emitting.
2872 LIR_OpList* inst = lir->instructions_list();
2873 for (int i = 1; i < inst->length(); i++) {
2874 LIR_Op* op = inst->at(i);
2875
2876 // 2 register-register-moves
2877 if (op->code() == lir_move) {
2878 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2879 res2 = ((LIR_Op1*)op)->result_opr();
2880 if (in2->is_register() && res2->is_register()) {
2881 LIR_Op* prev = inst->at(i - 1);
2882 if (prev && prev->code() == lir_move) {
2883 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2884 res1 = ((LIR_Op1*)prev)->result_opr();
2885 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2886 inst->remove_at(i);
2887 }
2888 }
2889 }
2890 }
2891
2892 }
2893 return;
2894 }
2895
2896
2897 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2898 const LIR_Address *addr = src->as_address_ptr();
2899 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2900 const Register Rptr = addr->base()->as_pointer_register(),
2901 Rtmp = tmp->as_register();
2902 Register Robj = noreg;
2903 if (data->is_oop()) {
2904 if (UseCompressedOops) {
2905 Robj = __ encode_heap_oop(Rtmp, data->as_register());
2906 } else {
2907 Robj = data->as_register();
2908 if (Robj == dest->as_register()) { // May happen with ZGC.
2909 __ mr(Rtmp, Robj);
2910 Robj = Rtmp;
2911 }
2912 }
2913 }
2914
2915 // There might be a volatile load before this Unsafe OP.
2916 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2917 __ sync();
2918 } else {
2919 __ lwsync();
2920 }
2921
2922 Label Lretry;
2923 __ bind(Lretry);
2924
2925 if (data->type() == T_INT) {
2926 const Register Rold = dest->as_register(),
2927 Rsrc = data->as_register();
2928 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2929 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2930 if (code == lir_xadd) {
2931 __ add(Rtmp, Rsrc, Rold);
2932 __ stwcx_(Rtmp, Rptr);
2933 } else {
2934 __ stwcx_(Rsrc, Rptr);
2935 }
2936 } else if (data->is_oop()) {
2937 assert(code == lir_xchg, "xadd for oops");
2938 const Register Rold = dest->as_register();
2939 assert_different_registers(Rptr, Rold, Robj);
2940 if (UseCompressedOops) {
2941 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2942 __ stwcx_(Robj, Rptr);
2943 } else {
2944 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2945 __ stdcx_(Robj, Rptr);
2946 }
2947 } else if (data->type() == T_LONG) {
2948 const Register Rold = dest->as_register_lo(),
2949 Rsrc = data->as_register_lo();
2950 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2951 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2952 if (code == lir_xadd) {
2953 __ add(Rtmp, Rsrc, Rold);
2954 __ stdcx_(Rtmp, Rptr);
2955 } else {
2956 __ stdcx_(Rsrc, Rptr);
2957 }
2958 } else {
2959 ShouldNotReachHere();
2960 }
2961
2962 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2963 __ bne_predict_not_taken(CR0, Lretry);
2964 } else {
2965 __ bne( CR0, Lretry);
2966 }
2967
2968 if (UseCompressedOops && data->is_oop()) {
2969 __ decode_heap_oop(dest->as_register());
2970 }
2971
2972 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2973 __ isync();
2974 } else {
2975 __ sync();
2976 }
2977 }
2978
2979
2980 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2981 Register obj = op->obj()->as_register();
2982 Register tmp = op->tmp()->as_pointer_register();
2983 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
2984 ciKlass* exact_klass = op->exact_klass();
2985 intptr_t current_klass = op->current_klass();
2986 bool not_null = op->not_null();
2987 bool no_conflict = op->no_conflict();
2988
2989 Label Lupdate, Ldo_update, Ldone;
2990
2991 bool do_null = !not_null;
2992 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2993 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2994
2995 assert(do_null || do_update, "why are we here?");
2996 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2997
2998 __ verify_oop(obj, FILE_AND_LINE);
2999
3000 if (do_null) {
3001 if (!TypeEntries::was_null_seen(current_klass)) {
3002 __ cmpdi(CR0, obj, 0);
3003 __ bne(CR0, Lupdate);
3004 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3005 __ ori(R0, R0, TypeEntries::null_seen);
3006 if (do_update) {
3007 __ b(Ldo_update);
3008 } else {
3009 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3010 }
3011 } else {
3012 if (do_update) {
3013 __ cmpdi(CR0, obj, 0);
3014 __ beq(CR0, Ldone);
3015 }
3016 }
3017 #ifdef ASSERT
3018 } else {
3019 __ cmpdi(CR0, obj, 0);
3020 __ bne(CR0, Lupdate);
3021 __ stop("unexpected null obj");
3022 #endif
3023 }
3024
3025 __ bind(Lupdate);
3026 if (do_update) {
3027 Label Lnext;
3028 const Register klass = R29_TOC; // kill and reload
3029 bool klass_reg_used = false;
3030 #ifdef ASSERT
3031 if (exact_klass != nullptr) {
3032 Label ok;
3033 klass_reg_used = true;
3034 __ load_klass(klass, obj);
3035 metadata2reg(exact_klass->constant_encoding(), R0);
3036 __ cmpd(CR0, klass, R0);
3037 __ beq(CR0, ok);
3038 __ stop("exact klass and actual klass differ");
3039 __ bind(ok);
3040 }
3041 #endif
3042
3043 if (!no_conflict) {
3044 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3045 klass_reg_used = true;
3046 if (exact_klass != nullptr) {
3047 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3048 metadata2reg(exact_klass->constant_encoding(), klass);
3049 } else {
3050 __ load_klass(klass, obj);
3051 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3052 }
3053
3054 // Like InterpreterMacroAssembler::profile_obj_type
3055 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3056 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3057 __ cmpd(CR1, R0, klass);
3058 // Klass seen before, nothing to do (regardless of unknown bit).
3059 //beq(CR1, do_nothing);
3060
3061 __ andi_(R0, tmp, TypeEntries::type_unknown);
3062 // Already unknown. Nothing to do anymore.
3063 //bne(CR0, do_nothing);
3064 __ crorc(CR0, Assembler::equal, CR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3065 __ beq(CR0, Lnext);
3066
3067 if (TypeEntries::is_type_none(current_klass)) {
3068 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3069 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3070 __ beq(CR0, Ldo_update); // First time here. Set profile type.
3071 }
3072
3073 } else {
3074 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3075 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3076
3077 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3078 __ andi_(R0, tmp, TypeEntries::type_unknown);
3079 // Already unknown. Nothing to do anymore.
3080 __ bne(CR0, Lnext);
3081 }
3082
3083 // Different than before. Cannot keep accurate profile.
3084 __ ori(R0, tmp, TypeEntries::type_unknown);
3085 } else {
3086 // There's a single possible klass at this profile point
3087 assert(exact_klass != nullptr, "should be");
3088 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3089
3090 if (TypeEntries::is_type_none(current_klass)) {
3091 klass_reg_used = true;
3092 metadata2reg(exact_klass->constant_encoding(), klass);
3093
3094 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3095 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3096 __ cmpd(CR1, R0, klass);
3097 // Klass seen before, nothing to do (regardless of unknown bit).
3098 __ beq(CR1, Lnext);
3099 #ifdef ASSERT
3100 {
3101 Label ok;
3102 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3103 __ beq(CR0, ok); // First time here.
3104
3105 __ stop("unexpected profiling mismatch");
3106 __ bind(ok);
3107 }
3108 #endif
3109 // First time here. Set profile type.
3110 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3111 } else {
3112 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3113 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3114
3115 // Already unknown. Nothing to do anymore.
3116 __ andi_(R0, tmp, TypeEntries::type_unknown);
3117 __ bne(CR0, Lnext);
3118
3119 // Different than before. Cannot keep accurate profile.
3120 __ ori(R0, tmp, TypeEntries::type_unknown);
3121 }
3122 }
3123
3124 __ bind(Ldo_update);
3125 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3126
3127 __ bind(Lnext);
3128 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3129 }
3130 __ bind(Ldone);
3131 }
3132
3133 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3134 Unimplemented();
3135 }
3136
3137 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3138 assert(op->crc()->is_single_cpu(), "crc must be register");
3139 assert(op->val()->is_single_cpu(), "byte value must be register");
3140 assert(op->result_opr()->is_single_cpu(), "result must be register");
3141 Register crc = op->crc()->as_register();
3142 Register val = op->val()->as_register();
3143 Register res = op->result_opr()->as_register();
3144
3145 assert_different_registers(val, crc, res);
3146
3147 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3148 __ kernel_crc32_singleByteReg(crc, val, res, true);
3149 __ mr(res, crc);
3150 }
3151
3152 #undef __