1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/os.inline.hpp"
42 #include "runtime/safepointMechanism.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/vm_version.hpp"
46 #include "utilities/macros.hpp"
47 #include "utilities/powerOfTwo.hpp"
48
49 #define __ _masm->
50
51
52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
53
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 Unimplemented(); return false; // Currently not used on this platform.
57 }
58
59
60 LIR_Opr LIR_Assembler::receiverOpr() {
61 return FrameMap::R3_oop_opr;
62 }
63
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::R3_opr;
67 }
68
69
70 // This specifies the stack pointer decrement needed to build the frame.
71 int LIR_Assembler::initial_frame_size_in_bytes() const {
72 return in_bytes(frame_map()->framesize_in_bytes());
73 }
74
75
76 // Inline cache check: the inline cached class is in inline_cache_reg;
77 // we fetch the class of the receiver and compare it with the cached class.
78 // If they do not match we jump to slow case.
79 int LIR_Assembler::check_icache() {
80 int offset = __ offset();
81 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
82 return offset;
83 }
84
85 void LIR_Assembler::clinit_barrier(ciMethod* method) {
86 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
87
88 Label L_skip_barrier;
89 Register klass = R20;
90
91 metadata2reg(method->holder()->constant_encoding(), klass);
92 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
93
94 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
95 __ mtctr(klass);
96 __ bctr();
97
98 __ bind(L_skip_barrier);
99 }
100
101 void LIR_Assembler::osr_entry() {
102 // On-stack-replacement entry sequence:
103 //
104 // 1. Create a new compiled activation.
105 // 2. Initialize local variables in the compiled activation. The expression
106 // stack must be empty at the osr_bci; it is not initialized.
107 // 3. Jump to the continuation address in compiled code to resume execution.
108
109 // OSR entry point
110 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
111 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
112 ValueStack* entry_state = osr_entry->end()->state();
113 int number_of_locks = entry_state->locks_size();
114
115 // Create a frame for the compiled activation.
116 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
117
118 // OSR buffer is
119 //
120 // locals[nlocals-1..0]
121 // monitors[number_of_locks-1..0]
122 //
123 // Locals is a direct copy of the interpreter frame so in the osr buffer
124 // the first slot in the local array is the last local from the interpreter
125 // and the last slot is local[0] (receiver) from the interpreter.
126 //
127 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
128 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
129 // in the interpreter frame (the method lock if a sync method).
130
131 // Initialize monitors in the compiled activation.
132 // R3: pointer to osr buffer
133 //
134 // All other registers are dead at this point and the locals will be
135 // copied into place by code emitted in the IR.
136
137 Register OSR_buf = osrBufferPointer()->as_register();
138 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
139 int monitor_offset = BytesPerWord * method()->max_locals() +
140 (2 * BytesPerWord) * (number_of_locks - 1);
141 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
142 // the OSR buffer using 2 word entries: first the lock and then
143 // the oop.
144 for (int i = 0; i < number_of_locks; i++) {
145 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
146 #ifdef ASSERT
147 // Verify the interpreter's monitor has a non-null object.
148 {
149 Label L;
150 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
151 __ cmpdi(CCR0, R0, 0);
152 __ bne(CCR0, L);
153 __ stop("locked object is NULL");
154 __ bind(L);
155 }
156 #endif // ASSERT
157 // Copy the lock field into the compiled activation.
158 Address ml = frame_map()->address_for_monitor_lock(i),
159 mo = frame_map()->address_for_monitor_object(i);
160 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
161 __ ld(R0, slot_offset + 0, OSR_buf);
162 __ std(R0, ml.disp(), ml.base());
163 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
164 __ std(R0, mo.disp(), mo.base());
165 }
166 }
167 }
168
169
170 int LIR_Assembler::emit_exception_handler() {
171 // Generate code for the exception handler.
172 address handler_base = __ start_a_stub(exception_handler_size());
173
174 if (handler_base == NULL) {
175 // Not enough space left for the handler.
176 bailout("exception handler overflow");
177 return -1;
178 }
179
180 int offset = code_offset();
181 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
182 //__ load_const_optimized(R0, entry_point);
183 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
184 __ mtctr(R0);
185 __ bctr();
186
187 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
188 __ end_a_stub();
189
190 return offset;
191 }
192
193
194 // Emit the code to remove the frame from the stack in the exception
195 // unwind path.
196 int LIR_Assembler::emit_unwind_handler() {
197 _masm->block_comment("Unwind handler");
198
199 int offset = code_offset();
200 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
201 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
202
203 // Fetch the exception from TLS and clear out exception related thread state.
204 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
205 __ li(R0, 0);
206 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
207 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
208
209 __ bind(_unwind_handler_entry);
210 __ verify_not_null_oop(Rexception);
211 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
212
213 // Perform needed unlocking
214 MonitorExitStub* stub = NULL;
215 if (method()->is_synchronized()) {
216 monitor_address(0, FrameMap::R4_opr);
217 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
218 __ unlock_object(R5, R6, R4, *stub->entry());
219 __ bind(*stub->continuation());
220 }
221
222 if (compilation()->env()->dtrace_method_probes()) {
223 Unimplemented();
224 }
225
226 // Dispatch to the unwind logic.
227 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
228 //__ load_const_optimized(R0, unwind_stub);
229 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
230 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
231 __ mtctr(R0);
232 __ bctr();
233
234 // Emit the slow path assembly.
235 if (stub != NULL) {
236 stub->emit_code(this);
237 }
238
239 return offset;
240 }
241
242
243 int LIR_Assembler::emit_deopt_handler() {
244 // Generate code for deopt handler.
245 address handler_base = __ start_a_stub(deopt_handler_size());
246
247 if (handler_base == NULL) {
248 // Not enough space left for the handler.
249 bailout("deopt handler overflow");
250 return -1;
251 }
252
253 int offset = code_offset();
254 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
255
256 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
257 __ end_a_stub();
258
259 return offset;
260 }
261
262
263 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
264 if (o == NULL) {
265 __ li(reg, 0);
266 } else {
267 AddressLiteral addrlit = __ constant_oop_address(o);
268 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
269 }
270 }
271
272
273 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
274 // Allocate a new index in table to hold the object once it's been patched.
275 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
276 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
277
278 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
279 __ load_const(reg, addrlit, R0);
280
281 patching_epilog(patch, lir_patch_normal, reg, info);
282 }
283
284
285 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
286 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
287 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
288 }
289
290
291 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
292 // Allocate a new index in table to hold the klass once it's been patched.
293 int index = __ oop_recorder()->allocate_metadata_index(NULL);
294 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
295
296 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
297 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
298 __ load_const(reg, addrlit, R0);
299
300 patching_epilog(patch, lir_patch_normal, reg, info);
301 }
302
303
304 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
305 const bool is_int = result->is_single_cpu();
306 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
307 Register Rdivisor = noreg;
308 Register Rscratch = temp->as_register();
309 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
310 long divisor = -1;
311
312 if (right->is_register()) {
313 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
314 } else {
315 divisor = is_int ? right->as_constant_ptr()->as_jint()
316 : right->as_constant_ptr()->as_jlong();
317 }
318
319 assert(Rdividend != Rscratch, "");
320 assert(Rdivisor != Rscratch, "");
321 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
322
323 if (Rdivisor == noreg) {
324 if (divisor == 1) { // stupid, but can happen
325 if (code == lir_idiv) {
326 __ mr_if_needed(Rresult, Rdividend);
327 } else {
328 __ li(Rresult, 0);
329 }
330
331 } else if (is_power_of_2(divisor)) {
332 // Convert division by a power of two into some shifts and logical operations.
333 int log2 = log2i_exact(divisor);
334
335 // Round towards 0.
336 if (divisor == 2) {
337 if (is_int) {
338 __ srwi(Rscratch, Rdividend, 31);
339 } else {
340 __ srdi(Rscratch, Rdividend, 63);
341 }
342 } else {
343 if (is_int) {
344 __ srawi(Rscratch, Rdividend, 31);
345 } else {
346 __ sradi(Rscratch, Rdividend, 63);
347 }
348 __ clrldi(Rscratch, Rscratch, 64-log2);
349 }
350 __ add(Rscratch, Rdividend, Rscratch);
351
352 if (code == lir_idiv) {
353 if (is_int) {
354 __ srawi(Rresult, Rscratch, log2);
355 } else {
356 __ sradi(Rresult, Rscratch, log2);
357 }
358 } else { // lir_irem
359 __ clrrdi(Rscratch, Rscratch, log2);
360 __ sub(Rresult, Rdividend, Rscratch);
361 }
362
363 } else if (divisor == -1) {
364 if (code == lir_idiv) {
365 __ neg(Rresult, Rdividend);
366 } else {
367 __ li(Rresult, 0);
368 }
369
370 } else {
371 __ load_const_optimized(Rscratch, divisor);
372 if (code == lir_idiv) {
373 if (is_int) {
374 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
375 } else {
376 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
377 }
378 } else {
379 assert(Rscratch != R0, "need both");
380 if (is_int) {
381 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
382 __ mullw(Rscratch, R0, Rscratch);
383 } else {
384 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
385 __ mulld(Rscratch, R0, Rscratch);
386 }
387 __ sub(Rresult, Rdividend, Rscratch);
388 }
389
390 }
391 return;
392 }
393
394 Label regular, done;
395 if (is_int) {
396 __ cmpwi(CCR0, Rdivisor, -1);
397 } else {
398 __ cmpdi(CCR0, Rdivisor, -1);
399 }
400 __ bne(CCR0, regular);
401 if (code == lir_idiv) {
402 __ neg(Rresult, Rdividend);
403 __ b(done);
404 __ bind(regular);
405 if (is_int) {
406 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
407 } else {
408 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
409 }
410 } else { // lir_irem
411 __ li(Rresult, 0);
412 __ b(done);
413 __ bind(regular);
414 if (is_int) {
415 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
416 __ mullw(Rscratch, Rscratch, Rdivisor);
417 } else {
418 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
419 __ mulld(Rscratch, Rscratch, Rdivisor);
420 }
421 __ sub(Rresult, Rdividend, Rscratch);
422 }
423 __ bind(done);
424 }
425
426
427 void LIR_Assembler::emit_op3(LIR_Op3* op) {
428 switch (op->code()) {
429 case lir_idiv:
430 case lir_irem:
431 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
432 op->result_opr(), op->info());
433 break;
434 case lir_fmad:
435 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
436 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
437 break;
438 case lir_fmaf:
439 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
440 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
441 break;
442 default: ShouldNotReachHere(); break;
443 }
444 }
445
446
447 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
448 #ifdef ASSERT
449 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
450 if (op->block() != NULL) _branch_target_blocks.append(op->block());
451 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
452 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
453 #endif
454
455 Label *L = op->label();
456 if (op->cond() == lir_cond_always) {
457 __ b(*L);
458 } else {
459 Label done;
460 bool is_unordered = false;
461 if (op->code() == lir_cond_float_branch) {
462 assert(op->ublock() != NULL, "must have unordered successor");
463 is_unordered = true;
464 } else {
465 assert(op->code() == lir_branch, "just checking");
466 }
467
468 bool positive = false;
469 Assembler::Condition cond = Assembler::equal;
470 switch (op->cond()) {
471 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
472 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
473 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
474 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
475 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
476 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
477 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
478 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
479 default: ShouldNotReachHere();
480 }
481 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
482 int bi = Assembler::bi0(BOOL_RESULT, cond);
483 if (is_unordered) {
484 if (positive) {
485 if (op->ublock() == op->block()) {
486 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
487 }
488 } else {
489 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
490 }
491 }
492 __ bc_far_optimized(bo, bi, *L);
493 __ bind(done);
494 }
495 }
496
497
498 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
499 Bytecodes::Code code = op->bytecode();
500 LIR_Opr src = op->in_opr(),
501 dst = op->result_opr();
502
503 switch(code) {
504 case Bytecodes::_i2l: {
505 __ extsw(dst->as_register_lo(), src->as_register());
506 break;
507 }
508 case Bytecodes::_l2i: {
509 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
510 break;
511 }
512 case Bytecodes::_i2b: {
513 __ extsb(dst->as_register(), src->as_register());
514 break;
515 }
516 case Bytecodes::_i2c: {
517 __ clrldi(dst->as_register(), src->as_register(), 64-16);
518 break;
519 }
520 case Bytecodes::_i2s: {
521 __ extsh(dst->as_register(), src->as_register());
522 break;
523 }
524 case Bytecodes::_i2d:
525 case Bytecodes::_l2d: {
526 bool src_in_memory = !VM_Version::has_mtfprd();
527 FloatRegister rdst = dst->as_double_reg();
528 FloatRegister rsrc;
529 if (src_in_memory) {
530 rsrc = src->as_double_reg(); // via mem
531 } else {
532 // move src to dst register
533 if (code == Bytecodes::_i2d) {
534 __ mtfprwa(rdst, src->as_register());
535 } else {
536 __ mtfprd(rdst, src->as_register_lo());
537 }
538 rsrc = rdst;
539 }
540 __ fcfid(rdst, rsrc);
541 break;
542 }
543 case Bytecodes::_i2f:
544 case Bytecodes::_l2f: {
545 bool src_in_memory = !VM_Version::has_mtfprd();
546 FloatRegister rdst = dst->as_float_reg();
547 FloatRegister rsrc;
548 if (src_in_memory) {
549 rsrc = src->as_double_reg(); // via mem
550 } else {
551 // move src to dst register
552 if (code == Bytecodes::_i2f) {
553 __ mtfprwa(rdst, src->as_register());
554 } else {
555 __ mtfprd(rdst, src->as_register_lo());
556 }
557 rsrc = rdst;
558 }
559 if (VM_Version::has_fcfids()) {
560 __ fcfids(rdst, rsrc);
561 } else {
562 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
563 __ fcfid(rdst, rsrc);
564 __ frsp(rdst, rdst);
565 }
566 break;
567 }
568 case Bytecodes::_f2d: {
569 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
570 break;
571 }
572 case Bytecodes::_d2f: {
573 __ frsp(dst->as_float_reg(), src->as_double_reg());
574 break;
575 }
576 case Bytecodes::_d2i:
577 case Bytecodes::_f2i: {
578 bool dst_in_memory = !VM_Version::has_mtfprd();
579 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
580 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
581 Label L;
582 // Result must be 0 if value is NaN; test by comparing value to itself.
583 __ fcmpu(CCR0, rsrc, rsrc);
584 if (dst_in_memory) {
585 __ li(R0, 0); // 0 in case of NAN
586 __ std(R0, addr.disp(), addr.base());
587 } else {
588 __ li(dst->as_register(), 0);
589 }
590 __ bso(CCR0, L);
591 __ fctiwz(rsrc, rsrc); // USE_KILL
592 if (dst_in_memory) {
593 __ stfd(rsrc, addr.disp(), addr.base());
594 } else {
595 __ mffprd(dst->as_register(), rsrc);
596 }
597 __ bind(L);
598 break;
599 }
600 case Bytecodes::_d2l:
601 case Bytecodes::_f2l: {
602 bool dst_in_memory = !VM_Version::has_mtfprd();
603 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
604 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
605 Label L;
606 // Result must be 0 if value is NaN; test by comparing value to itself.
607 __ fcmpu(CCR0, rsrc, rsrc);
608 if (dst_in_memory) {
609 __ li(R0, 0); // 0 in case of NAN
610 __ std(R0, addr.disp(), addr.base());
611 } else {
612 __ li(dst->as_register_lo(), 0);
613 }
614 __ bso(CCR0, L);
615 __ fctidz(rsrc, rsrc); // USE_KILL
616 if (dst_in_memory) {
617 __ stfd(rsrc, addr.disp(), addr.base());
618 } else {
619 __ mffprd(dst->as_register_lo(), rsrc);
620 }
621 __ bind(L);
622 break;
623 }
624
625 default: ShouldNotReachHere();
626 }
627 }
628
629
630 void LIR_Assembler::align_call(LIR_Code) {
631 // do nothing since all instructions are word aligned on ppc
632 }
633
634
635 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
636 int start_offset = __ offset();
637 // Put the entry point as a constant into the constant pool.
638 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
639 if (entry_point_toc_addr == NULL) {
640 bailout("const section overflow");
641 return false;
642 }
643 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
644
645 // Emit the trampoline stub which will be related to the branch-and-link below.
646 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
647 if (!stub) {
648 bailout("no space for trampoline stub");
649 return false;
650 }
651 return true;
652 }
653
654
655 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
656 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
657
658 bool success = emit_trampoline_stub_for_call(op->addr());
659 if (!success) { return; }
660
661 __ relocate(rtype);
662 // Note: At this point we do not have the address of the trampoline
663 // stub, and the entry point might be too far away for bl, so __ pc()
664 // serves as dummy and the bl will be patched later.
665 __ code()->set_insts_mark();
666 __ bl(__ pc());
667 add_call_info(code_offset(), op->info());
668 }
669
670
671 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
672 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
673
674 // Virtual call relocation will point to ic load.
675 address virtual_call_meta_addr = __ pc();
676 // Load a clear inline cache.
677 AddressLiteral empty_ic((address) Universe::non_oop_word());
678 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
679 if (!success) {
680 bailout("const section overflow");
681 return;
682 }
683 // Call to fixup routine. Fixup routine uses ScopeDesc info
684 // to determine who we intended to call.
685 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
686
687 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
688 if (!success) { return; }
689
690 // Note: At this point we do not have the address of the trampoline
691 // stub, and the entry point might be too far away for bl, so __ pc()
692 // serves as dummy and the bl will be patched later.
693 __ bl(__ pc());
694 add_call_info(code_offset(), op->info());
695 }
696
697 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
698 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
699 __ null_check(addr, stub->entry());
700 append_code_stub(stub);
701 }
702
703
704 // Attention: caller must encode oop if needed
705 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
706 int store_offset;
707 if (!Assembler::is_simm16(offset)) {
708 // For offsets larger than a simm16 we setup the offset.
709 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
710 __ load_const_optimized(R0, offset);
711 store_offset = store(from_reg, base, R0, type, wide);
712 } else {
713 store_offset = code_offset();
714 switch (type) {
715 case T_BOOLEAN: // fall through
716 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
717 case T_CHAR :
718 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
719 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
720 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
721 case T_ADDRESS:
722 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
723 case T_ARRAY : // fall through
724 case T_OBJECT:
725 {
726 if (UseCompressedOops && !wide) {
727 // Encoding done in caller
728 __ stw(from_reg->as_register(), offset, base);
729 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
730 } else {
731 __ std(from_reg->as_register(), offset, base);
732 __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
733 }
734 break;
735 }
736 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
737 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
738 default : ShouldNotReachHere();
739 }
740 }
741 return store_offset;
742 }
743
744
745 // Attention: caller must encode oop if needed
746 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
747 int store_offset = code_offset();
748 switch (type) {
749 case T_BOOLEAN: // fall through
750 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
751 case T_CHAR :
752 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
753 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
754 case T_LONG :
755 #ifdef _LP64
756 __ stdx(from_reg->as_register_lo(), base, disp);
757 #else
758 Unimplemented();
759 #endif
760 break;
761 case T_ADDRESS:
762 __ stdx(from_reg->as_register(), base, disp);
763 break;
764 case T_ARRAY : // fall through
765 case T_OBJECT:
766 {
767 if (UseCompressedOops && !wide) {
768 // Encoding done in caller.
769 __ stwx(from_reg->as_register(), base, disp);
770 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
771 } else {
772 __ stdx(from_reg->as_register(), base, disp);
773 __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
774 }
775 break;
776 }
777 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
778 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
779 default : ShouldNotReachHere();
780 }
781 return store_offset;
782 }
783
784
785 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
786 int load_offset;
787 if (!Assembler::is_simm16(offset)) {
788 // For offsets larger than a simm16 we setup the offset.
789 __ load_const_optimized(R0, offset);
790 load_offset = load(base, R0, to_reg, type, wide);
791 } else {
792 load_offset = code_offset();
793 switch(type) {
794 case T_BOOLEAN: // fall through
795 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
796 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
797 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
798 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
799 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
800 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
801 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
802 case T_ADDRESS:
803 __ ld(to_reg->as_register(), offset, base);
804 break;
805 case T_ARRAY : // fall through
806 case T_OBJECT:
807 {
808 if (UseCompressedOops && !wide) {
809 __ lwz(to_reg->as_register(), offset, base);
810 __ decode_heap_oop(to_reg->as_register());
811 } else {
812 __ ld(to_reg->as_register(), offset, base);
813 }
814 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
815 break;
816 }
817 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
818 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
819 default : ShouldNotReachHere();
820 }
821 }
822 return load_offset;
823 }
824
825
826 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
827 int load_offset = code_offset();
828 switch(type) {
829 case T_BOOLEAN: // fall through
830 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
831 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
832 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
833 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
834 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
835 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
836 case T_ARRAY : // fall through
837 case T_OBJECT:
838 {
839 if (UseCompressedOops && !wide) {
840 __ lwzx(to_reg->as_register(), base, disp);
841 __ decode_heap_oop(to_reg->as_register());
842 } else {
843 __ ldx(to_reg->as_register(), base, disp);
844 }
845 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
846 break;
847 }
848 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
849 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
850 case T_LONG :
851 #ifdef _LP64
852 __ ldx(to_reg->as_register_lo(), base, disp);
853 #else
854 Unimplemented();
855 #endif
856 break;
857 default : ShouldNotReachHere();
858 }
859 return load_offset;
860 }
861
862
863 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
864 LIR_Const* c = src->as_constant_ptr();
865 Register src_reg = R0;
866 switch (c->type()) {
867 case T_INT:
868 case T_FLOAT: {
869 int value = c->as_jint_bits();
870 __ load_const_optimized(src_reg, value);
871 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
872 __ stw(src_reg, addr.disp(), addr.base());
873 break;
874 }
875 case T_ADDRESS: {
876 int value = c->as_jint_bits();
877 __ load_const_optimized(src_reg, value);
878 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
879 __ std(src_reg, addr.disp(), addr.base());
880 break;
881 }
882 case T_OBJECT: {
883 jobject2reg(c->as_jobject(), src_reg);
884 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
885 __ std(src_reg, addr.disp(), addr.base());
886 break;
887 }
888 case T_LONG:
889 case T_DOUBLE: {
890 int value = c->as_jlong_bits();
891 __ load_const_optimized(src_reg, value);
892 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
893 __ std(src_reg, addr.disp(), addr.base());
894 break;
895 }
896 default:
897 Unimplemented();
898 }
899 }
900
901
902 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
903 LIR_Const* c = src->as_constant_ptr();
904 LIR_Address* addr = dest->as_address_ptr();
905 Register base = addr->base()->as_pointer_register();
906 LIR_Opr tmp = LIR_OprFact::illegalOpr;
907 int offset = -1;
908 // Null check for large offsets in LIRGenerator::do_StoreField.
909 bool needs_explicit_null_check = !ImplicitNullChecks;
910
911 if (info != NULL && needs_explicit_null_check) {
912 explicit_null_check(base, info);
913 }
914
915 switch (c->type()) {
916 case T_FLOAT: type = T_INT;
917 case T_INT:
918 case T_ADDRESS: {
919 tmp = FrameMap::R0_opr;
920 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
921 break;
922 }
923 case T_DOUBLE: type = T_LONG;
924 case T_LONG: {
925 tmp = FrameMap::R0_long_opr;
926 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
927 break;
928 }
929 case T_OBJECT: {
930 tmp = FrameMap::R0_opr;
931 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
932 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
933 // Don't care about sign extend (will use stw).
934 __ lis(R0, 0); // Will get patched.
935 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
936 __ ori(R0, R0, 0); // Will get patched.
937 } else {
938 jobject2reg(c->as_jobject(), R0);
939 }
940 break;
941 }
942 default:
943 Unimplemented();
944 }
945
946 // Handle either reg+reg or reg+disp address.
947 if (addr->index()->is_valid()) {
948 assert(addr->disp() == 0, "must be zero");
949 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
950 } else {
951 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
952 offset = store(tmp, base, addr->disp(), type, wide);
953 }
954
955 if (info != NULL) {
956 assert(offset != -1, "offset should've been set");
957 if (!needs_explicit_null_check) {
958 add_debug_info_for_null_check(offset, info);
959 }
960 }
961 }
962
963
964 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
965 LIR_Const* c = src->as_constant_ptr();
966 LIR_Opr to_reg = dest;
967
968 switch (c->type()) {
969 case T_INT: {
970 assert(patch_code == lir_patch_none, "no patching handled here");
971 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
972 break;
973 }
974 case T_ADDRESS: {
975 assert(patch_code == lir_patch_none, "no patching handled here");
976 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
977 break;
978 }
979 case T_LONG: {
980 assert(patch_code == lir_patch_none, "no patching handled here");
981 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
982 break;
983 }
984
985 case T_OBJECT: {
986 if (patch_code == lir_patch_none) {
987 jobject2reg(c->as_jobject(), to_reg->as_register());
988 } else {
989 jobject2reg_with_patching(to_reg->as_register(), info);
990 }
991 break;
992 }
993
994 case T_METADATA:
995 {
996 if (patch_code == lir_patch_none) {
997 metadata2reg(c->as_metadata(), to_reg->as_register());
998 } else {
999 klass2reg_with_patching(to_reg->as_register(), info);
1000 }
1001 }
1002 break;
1003
1004 case T_FLOAT:
1005 {
1006 if (to_reg->is_single_fpu()) {
1007 address const_addr = __ float_constant(c->as_jfloat());
1008 if (const_addr == NULL) {
1009 bailout("const section overflow");
1010 break;
1011 }
1012 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1013 __ relocate(rspec);
1014 __ load_const(R0, const_addr);
1015 __ lfsx(to_reg->as_float_reg(), R0);
1016 } else {
1017 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1018 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1019 }
1020 }
1021 break;
1022
1023 case T_DOUBLE:
1024 {
1025 if (to_reg->is_double_fpu()) {
1026 address const_addr = __ double_constant(c->as_jdouble());
1027 if (const_addr == NULL) {
1028 bailout("const section overflow");
1029 break;
1030 }
1031 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1032 __ relocate(rspec);
1033 __ load_const(R0, const_addr);
1034 __ lfdx(to_reg->as_double_reg(), R0);
1035 } else {
1036 assert(to_reg->is_double_cpu(), "Must be a long register.");
1037 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1038 }
1039 }
1040 break;
1041
1042 default:
1043 ShouldNotReachHere();
1044 }
1045 }
1046
1047
1048 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1049 Unimplemented(); return Address();
1050 }
1051
1052
1053 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1054 if (addr->index()->is_illegal()) {
1055 return (RegisterOrConstant)(addr->disp());
1056 } else {
1057 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1058 }
1059 }
1060
1061
1062 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1063 const Register tmp = R0;
1064 switch (type) {
1065 case T_INT:
1066 case T_FLOAT: {
1067 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1068 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1069 __ lwz(tmp, from.disp(), from.base());
1070 __ stw(tmp, to.disp(), to.base());
1071 break;
1072 }
1073 case T_ADDRESS:
1074 case T_OBJECT: {
1075 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1076 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1077 __ ld(tmp, from.disp(), from.base());
1078 __ std(tmp, to.disp(), to.base());
1079 break;
1080 }
1081 case T_LONG:
1082 case T_DOUBLE: {
1083 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1084 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1085 __ ld(tmp, from.disp(), from.base());
1086 __ std(tmp, to.disp(), to.base());
1087 break;
1088 }
1089
1090 default:
1091 ShouldNotReachHere();
1092 }
1093 }
1094
1095
1096 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1097 Unimplemented(); return Address();
1098 }
1099
1100
1101 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1102 Unimplemented(); return Address();
1103 }
1104
1105
1106 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1107 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1108
1109 assert(type != T_METADATA, "load of metadata ptr not supported");
1110 LIR_Address* addr = src_opr->as_address_ptr();
1111 LIR_Opr to_reg = dest;
1112
1113 Register src = addr->base()->as_pointer_register();
1114 Register disp_reg = noreg;
1115 int disp_value = addr->disp();
1116 bool needs_patching = (patch_code != lir_patch_none);
1117 // null check for large offsets in LIRGenerator::do_LoadField
1118 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1119
1120 if (info != NULL && needs_explicit_null_check) {
1121 explicit_null_check(src, info);
1122 }
1123
1124 if (addr->base()->type() == T_OBJECT) {
1125 __ verify_oop(src, FILE_AND_LINE);
1126 }
1127
1128 PatchingStub* patch = NULL;
1129 if (needs_patching) {
1130 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1131 assert(!to_reg->is_double_cpu() ||
1132 patch_code == lir_patch_none ||
1133 patch_code == lir_patch_normal, "patching doesn't match register");
1134 }
1135
1136 if (addr->index()->is_illegal()) {
1137 if (!Assembler::is_simm16(disp_value)) {
1138 if (needs_patching) {
1139 __ load_const32(R0, 0); // patchable int
1140 } else {
1141 __ load_const_optimized(R0, disp_value);
1142 }
1143 disp_reg = R0;
1144 }
1145 } else {
1146 disp_reg = addr->index()->as_pointer_register();
1147 assert(disp_value == 0, "can't handle 3 operand addresses");
1148 }
1149
1150 // Remember the offset of the load. The patching_epilog must be done
1151 // before the call to add_debug_info, otherwise the PcDescs don't get
1152 // entered in increasing order.
1153 int offset;
1154
1155 if (disp_reg == noreg) {
1156 assert(Assembler::is_simm16(disp_value), "should have set this up");
1157 offset = load(src, disp_value, to_reg, type, wide);
1158 } else {
1159 offset = load(src, disp_reg, to_reg, type, wide);
1160 }
1161
1162 if (patch != NULL) {
1163 patching_epilog(patch, patch_code, src, info);
1164 }
1165 if (info != NULL && !needs_explicit_null_check) {
1166 add_debug_info_for_null_check(offset, info);
1167 }
1168 }
1169
1170
1171 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1172 Address addr;
1173 if (src->is_single_word()) {
1174 addr = frame_map()->address_for_slot(src->single_stack_ix());
1175 } else if (src->is_double_word()) {
1176 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1177 }
1178
1179 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1180 }
1181
1182
1183 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1184 Address addr;
1185 if (dest->is_single_word()) {
1186 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1187 } else if (dest->is_double_word()) {
1188 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1189 }
1190
1191 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1192 }
1193
1194
1195 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1196 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1197 if (from_reg->is_double_fpu()) {
1198 // double to double moves
1199 assert(to_reg->is_double_fpu(), "should match");
1200 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1201 } else {
1202 // float to float moves
1203 assert(to_reg->is_single_fpu(), "should match");
1204 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1205 }
1206 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1207 if (from_reg->is_double_cpu()) {
1208 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1209 } else if (to_reg->is_double_cpu()) {
1210 // int to int moves
1211 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1212 } else {
1213 // int to int moves
1214 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1215 }
1216 } else {
1217 ShouldNotReachHere();
1218 }
1219 if (is_reference_type(to_reg->type())) {
1220 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1221 }
1222 }
1223
1224
1225 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1226 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1227 bool wide) {
1228 assert(type != T_METADATA, "store of metadata ptr not supported");
1229 LIR_Address* addr = dest->as_address_ptr();
1230
1231 Register src = addr->base()->as_pointer_register();
1232 Register disp_reg = noreg;
1233 int disp_value = addr->disp();
1234 bool needs_patching = (patch_code != lir_patch_none);
1235 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1236 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1237 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1238 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1239 // Null check for large offsets in LIRGenerator::do_StoreField.
1240 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1241
1242 if (info != NULL && needs_explicit_null_check) {
1243 explicit_null_check(src, info);
1244 }
1245
1246 if (addr->base()->is_oop_register()) {
1247 __ verify_oop(src, FILE_AND_LINE);
1248 }
1249
1250 PatchingStub* patch = NULL;
1251 if (needs_patching) {
1252 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1253 assert(!from_reg->is_double_cpu() ||
1254 patch_code == lir_patch_none ||
1255 patch_code == lir_patch_normal, "patching doesn't match register");
1256 }
1257
1258 if (addr->index()->is_illegal()) {
1259 if (load_disp) {
1260 disp_reg = use_R29 ? R29_TOC : R0;
1261 if (needs_patching) {
1262 __ load_const32(disp_reg, 0); // patchable int
1263 } else {
1264 __ load_const_optimized(disp_reg, disp_value);
1265 }
1266 }
1267 } else {
1268 disp_reg = addr->index()->as_pointer_register();
1269 assert(disp_value == 0, "can't handle 3 operand addresses");
1270 }
1271
1272 // remember the offset of the store. The patching_epilog must be done
1273 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1274 // entered in increasing order.
1275 int offset;
1276
1277 if (compress_oop) {
1278 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1279 from_reg = FrameMap::as_opr(co);
1280 }
1281
1282 if (disp_reg == noreg) {
1283 assert(Assembler::is_simm16(disp_value), "should have set this up");
1284 offset = store(from_reg, src, disp_value, type, wide);
1285 } else {
1286 offset = store(from_reg, src, disp_reg, type, wide);
1287 }
1288
1289 if (use_R29) {
1290 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1291 }
1292
1293 if (patch != NULL) {
1294 patching_epilog(patch, patch_code, src, info);
1295 }
1296
1297 if (info != NULL && !needs_explicit_null_check) {
1298 add_debug_info_for_null_check(offset, info);
1299 }
1300 }
1301
1302
1303 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1304 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1305 const Register temp = R12;
1306
1307 // Pop the stack before the safepoint code.
1308 int frame_size = initial_frame_size_in_bytes();
1309 if (Assembler::is_simm(frame_size, 16)) {
1310 __ addi(R1_SP, R1_SP, frame_size);
1311 } else {
1312 __ pop_frame();
1313 }
1314
1315 // Restore return pc relative to callers' sp.
1316 __ ld(return_pc, _abi0(lr), R1_SP);
1317 // Move return pc to LR.
1318 __ mtlr(return_pc);
1319
1320 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1321 __ reserved_stack_check(return_pc);
1322 }
1323
1324 // We need to mark the code position where the load from the safepoint
1325 // polling page was emitted as relocInfo::poll_return_type here.
1326 if (!UseSIGTRAP) {
1327 code_stub->set_safepoint_offset(__ offset());
1328 __ relocate(relocInfo::poll_return_type);
1329 }
1330 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1331
1332 // Return.
1333 __ blr();
1334 }
1335
1336
1337 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1338 const Register poll_addr = tmp->as_register();
1339 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1340 if (info != NULL) {
1341 add_debug_info_for_branch(info);
1342 }
1343 int offset = __ offset();
1344 __ relocate(relocInfo::poll_type);
1345 __ load_from_polling_page(poll_addr);
1346
1347 return offset;
1348 }
1349
1350
1351 void LIR_Assembler::emit_static_call_stub() {
1352 address call_pc = __ pc();
1353 address stub = __ start_a_stub(static_call_stub_size());
1354 if (stub == NULL) {
1355 bailout("static call stub overflow");
1356 return;
1357 }
1358
1359 // For java_to_interp stubs we use R11_scratch1 as scratch register
1360 // and in call trampoline stubs we use R12_scratch2. This way we
1361 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1362 const Register reg_scratch = R11_scratch1;
1363
1364 // Create a static stub relocation which relates this stub
1365 // with the call instruction at insts_call_instruction_offset in the
1366 // instructions code-section.
1367 int start = __ offset();
1368 __ relocate(static_stub_Relocation::spec(call_pc));
1369
1370 // Now, create the stub's code:
1371 // - load the TOC
1372 // - load the inline cache oop from the constant pool
1373 // - load the call target from the constant pool
1374 // - call
1375 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1376 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1377 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1378
1379 if (ReoptimizeCallSequences) {
1380 __ b64_patchable((address)-1, relocInfo::none);
1381 } else {
1382 AddressLiteral a((address)-1);
1383 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1384 __ mtctr(reg_scratch);
1385 __ bctr();
1386 }
1387 if (!success) {
1388 bailout("const section overflow");
1389 return;
1390 }
1391
1392 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1393 __ end_a_stub();
1394 }
1395
1396
1397 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1398 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1399 if (opr1->is_single_fpu()) {
1400 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1401 } else if (opr1->is_double_fpu()) {
1402 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1403 } else if (opr1->is_single_cpu()) {
1404 if (opr2->is_constant()) {
1405 switch (opr2->as_constant_ptr()->type()) {
1406 case T_INT:
1407 {
1408 jint con = opr2->as_constant_ptr()->as_jint();
1409 if (unsigned_comp) {
1410 if (Assembler::is_uimm(con, 16)) {
1411 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1412 } else {
1413 __ load_const_optimized(R0, con);
1414 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1415 }
1416 } else {
1417 if (Assembler::is_simm(con, 16)) {
1418 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1419 } else {
1420 __ load_const_optimized(R0, con);
1421 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1422 }
1423 }
1424 }
1425 break;
1426
1427 case T_OBJECT:
1428 // There are only equal/notequal comparisons on objects.
1429 {
1430 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1431 jobject con = opr2->as_constant_ptr()->as_jobject();
1432 if (con == NULL) {
1433 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1434 } else {
1435 jobject2reg(con, R0);
1436 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1437 }
1438 }
1439 break;
1440
1441 case T_METADATA:
1442 // We only need, for now, comparison with NULL for metadata.
1443 {
1444 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1445 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1446 if (p == NULL) {
1447 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1448 } else {
1449 ShouldNotReachHere();
1450 }
1451 }
1452 break;
1453
1454 default:
1455 ShouldNotReachHere();
1456 break;
1457 }
1458 } else {
1459 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1460 if (is_reference_type(opr1->type())) {
1461 // There are only equal/notequal comparisons on objects.
1462 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1463 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1464 } else {
1465 if (unsigned_comp) {
1466 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1467 } else {
1468 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1469 }
1470 }
1471 }
1472 } else if (opr1->is_double_cpu()) {
1473 if (opr2->is_constant()) {
1474 jlong con = opr2->as_constant_ptr()->as_jlong();
1475 if (unsigned_comp) {
1476 if (Assembler::is_uimm(con, 16)) {
1477 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1478 } else {
1479 __ load_const_optimized(R0, con);
1480 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1481 }
1482 } else {
1483 if (Assembler::is_simm(con, 16)) {
1484 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1485 } else {
1486 __ load_const_optimized(R0, con);
1487 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1488 }
1489 }
1490 } else if (opr2->is_register()) {
1491 if (unsigned_comp) {
1492 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1493 } else {
1494 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1495 }
1496 } else {
1497 ShouldNotReachHere();
1498 }
1499 } else {
1500 ShouldNotReachHere();
1501 }
1502 }
1503
1504
1505 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1506 const Register Rdst = dst->as_register();
1507 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1508 bool is_unordered_less = (code == lir_ucmp_fd2i);
1509 if (left->is_single_fpu()) {
1510 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1511 } else if (left->is_double_fpu()) {
1512 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1513 } else {
1514 ShouldNotReachHere();
1515 }
1516 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1517 } else if (code == lir_cmp_l2i) {
1518 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1519 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1520 } else {
1521 ShouldNotReachHere();
1522 }
1523 }
1524
1525
1526 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1527 if (src->is_constant()) {
1528 lasm->const2reg(src, dst, lir_patch_none, NULL);
1529 } else if (src->is_register()) {
1530 lasm->reg2reg(src, dst);
1531 } else if (src->is_stack()) {
1532 lasm->stack2reg(src, dst, dst->type());
1533 } else {
1534 ShouldNotReachHere();
1535 }
1536 }
1537
1538 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1539 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1540 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1541
1542 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1543 load_to_reg(this, opr1, result); // Condition doesn't matter.
1544 return;
1545 }
1546
1547 bool positive = false;
1548 Assembler::Condition cond = Assembler::equal;
1549 switch (condition) {
1550 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1551 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1552 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1553 case lir_cond_belowEqual:
1554 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1555 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1556 case lir_cond_aboveEqual:
1557 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1558 default: ShouldNotReachHere();
1559 }
1560
1561 // Try to use isel on >=Power7.
1562 if (VM_Version::has_isel() && result->is_cpu_register()) {
1563 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1564 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1565
1566 // We can use result_reg to load one operand if not already in register.
1567 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1568 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1569
1570 if (first != second) {
1571 if (!o1_is_reg) {
1572 load_to_reg(this, opr1, result);
1573 }
1574
1575 if (!o2_is_reg) {
1576 load_to_reg(this, opr2, result);
1577 }
1578
1579 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1580 return;
1581 }
1582 } // isel
1583
1584 load_to_reg(this, opr1, result);
1585
1586 Label skip;
1587 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1588 int bi = Assembler::bi0(BOOL_RESULT, cond);
1589 __ bc(bo, bi, skip);
1590
1591 load_to_reg(this, opr2, result);
1592 __ bind(skip);
1593 }
1594
1595
1596 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1597 CodeEmitInfo* info, bool pop_fpu_stack) {
1598 assert(info == NULL, "unused on this code path");
1599 assert(left->is_register(), "wrong items state");
1600 assert(dest->is_register(), "wrong items state");
1601
1602 if (right->is_register()) {
1603 if (dest->is_float_kind()) {
1604
1605 FloatRegister lreg, rreg, res;
1606 if (right->is_single_fpu()) {
1607 lreg = left->as_float_reg();
1608 rreg = right->as_float_reg();
1609 res = dest->as_float_reg();
1610 switch (code) {
1611 case lir_add: __ fadds(res, lreg, rreg); break;
1612 case lir_sub: __ fsubs(res, lreg, rreg); break;
1613 case lir_mul: __ fmuls(res, lreg, rreg); break;
1614 case lir_div: __ fdivs(res, lreg, rreg); break;
1615 default: ShouldNotReachHere();
1616 }
1617 } else {
1618 lreg = left->as_double_reg();
1619 rreg = right->as_double_reg();
1620 res = dest->as_double_reg();
1621 switch (code) {
1622 case lir_add: __ fadd(res, lreg, rreg); break;
1623 case lir_sub: __ fsub(res, lreg, rreg); break;
1624 case lir_mul: __ fmul(res, lreg, rreg); break;
1625 case lir_div: __ fdiv(res, lreg, rreg); break;
1626 default: ShouldNotReachHere();
1627 }
1628 }
1629
1630 } else if (dest->is_double_cpu()) {
1631
1632 Register dst_lo = dest->as_register_lo();
1633 Register op1_lo = left->as_pointer_register();
1634 Register op2_lo = right->as_pointer_register();
1635
1636 switch (code) {
1637 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1638 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1639 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1640 default: ShouldNotReachHere();
1641 }
1642 } else {
1643 assert (right->is_single_cpu(), "Just Checking");
1644
1645 Register lreg = left->as_register();
1646 Register res = dest->as_register();
1647 Register rreg = right->as_register();
1648 switch (code) {
1649 case lir_add: __ add (res, lreg, rreg); break;
1650 case lir_sub: __ sub (res, lreg, rreg); break;
1651 case lir_mul: __ mullw(res, lreg, rreg); break;
1652 default: ShouldNotReachHere();
1653 }
1654 }
1655 } else {
1656 assert (right->is_constant(), "must be constant");
1657
1658 if (dest->is_single_cpu()) {
1659 Register lreg = left->as_register();
1660 Register res = dest->as_register();
1661 int simm16 = right->as_constant_ptr()->as_jint();
1662
1663 switch (code) {
1664 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1665 simm16 = -simm16;
1666 case lir_add: if (res == lreg && simm16 == 0) break;
1667 __ addi(res, lreg, simm16); break;
1668 case lir_mul: if (res == lreg && simm16 == 1) break;
1669 __ mulli(res, lreg, simm16); break;
1670 default: ShouldNotReachHere();
1671 }
1672 } else {
1673 Register lreg = left->as_pointer_register();
1674 Register res = dest->as_register_lo();
1675 long con = right->as_constant_ptr()->as_jlong();
1676 assert(Assembler::is_simm16(con), "must be simm16");
1677
1678 switch (code) {
1679 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1680 con = -con;
1681 case lir_add: if (res == lreg && con == 0) break;
1682 __ addi(res, lreg, (int)con); break;
1683 case lir_mul: if (res == lreg && con == 1) break;
1684 __ mulli(res, lreg, (int)con); break;
1685 default: ShouldNotReachHere();
1686 }
1687 }
1688 }
1689 }
1690
1691
1692 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1693 switch (code) {
1694 case lir_sqrt: {
1695 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1696 break;
1697 }
1698 case lir_abs: {
1699 __ fabs(dest->as_double_reg(), value->as_double_reg());
1700 break;
1701 }
1702 default: {
1703 ShouldNotReachHere();
1704 break;
1705 }
1706 }
1707 }
1708
1709
1710 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1711 if (right->is_constant()) { // see do_LogicOp
1712 long uimm;
1713 Register d, l;
1714 if (dest->is_single_cpu()) {
1715 uimm = right->as_constant_ptr()->as_jint();
1716 d = dest->as_register();
1717 l = left->as_register();
1718 } else {
1719 uimm = right->as_constant_ptr()->as_jlong();
1720 d = dest->as_register_lo();
1721 l = left->as_register_lo();
1722 }
1723 long uimms = (unsigned long)uimm >> 16,
1724 uimmss = (unsigned long)uimm >> 32;
1725
1726 switch (code) {
1727 case lir_logic_and:
1728 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1729 __ andi(d, l, uimm); // special cases
1730 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1731 else { __ andi_(d, l, uimm); }
1732 break;
1733
1734 case lir_logic_or:
1735 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1736 else { __ ori(d, l, uimm); }
1737 break;
1738
1739 case lir_logic_xor:
1740 if (uimm == -1) { __ nand(d, l, l); } // special case
1741 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1742 else { __ xori(d, l, uimm); }
1743 break;
1744
1745 default: ShouldNotReachHere();
1746 }
1747 } else {
1748 assert(right->is_register(), "right should be in register");
1749
1750 if (dest->is_single_cpu()) {
1751 switch (code) {
1752 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1753 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1754 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1755 default: ShouldNotReachHere();
1756 }
1757 } else {
1758 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1759 left->as_register_lo();
1760 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1761 right->as_register_lo();
1762
1763 switch (code) {
1764 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1765 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1766 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1767 default: ShouldNotReachHere();
1768 }
1769 }
1770 }
1771 }
1772
1773
1774 int LIR_Assembler::shift_amount(BasicType t) {
1775 int elem_size = type2aelembytes(t);
1776 switch (elem_size) {
1777 case 1 : return 0;
1778 case 2 : return 1;
1779 case 4 : return 2;
1780 case 8 : return 3;
1781 }
1782 ShouldNotReachHere();
1783 return -1;
1784 }
1785
1786
1787 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1788 info->add_register_oop(exceptionOop);
1789
1790 // Reuse the debug info from the safepoint poll for the throw op itself.
1791 address pc_for_athrow = __ pc();
1792 int pc_for_athrow_offset = __ offset();
1793 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1794 //__ relocate(rspec);
1795 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1796 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1797 add_call_info(pc_for_athrow_offset, info); // for exception handler
1798
1799 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1800 : Runtime1::handle_exception_nofpu_id);
1801 //__ load_const_optimized(R0, stub);
1802 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1803 __ mtctr(R0);
1804 __ bctr();
1805 }
1806
1807
1808 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1809 // Note: Not used with EnableDebuggingOnDemand.
1810 assert(exceptionOop->as_register() == R3, "should match");
1811 __ b(_unwind_handler_entry);
1812 }
1813
1814
1815 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1816 Register src = op->src()->as_register();
1817 Register dst = op->dst()->as_register();
1818 Register src_pos = op->src_pos()->as_register();
1819 Register dst_pos = op->dst_pos()->as_register();
1820 Register length = op->length()->as_register();
1821 Register tmp = op->tmp()->as_register();
1822 Register tmp2 = R0;
1823
1824 int flags = op->flags();
1825 ciArrayKlass* default_type = op->expected_type();
1826 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1827 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1828
1829 // Set up the arraycopy stub information.
1830 ArrayCopyStub* stub = op->stub();
1831 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1832
1833 // Always do stub if no type information is available. It's ok if
1834 // the known type isn't loaded since the code sanity checks
1835 // in debug mode and the type isn't required when we know the exact type
1836 // also check that the type is an array type.
1837 if (op->expected_type() == NULL) {
1838 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1839 length->is_nonvolatile(), "must preserve");
1840 address copyfunc_addr = StubRoutines::generic_arraycopy();
1841 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1842
1843 // 3 parms are int. Convert to long.
1844 __ mr(R3_ARG1, src);
1845 __ extsw(R4_ARG2, src_pos);
1846 __ mr(R5_ARG3, dst);
1847 __ extsw(R6_ARG4, dst_pos);
1848 __ extsw(R7_ARG5, length);
1849
1850 #ifndef PRODUCT
1851 if (PrintC1Statistics) {
1852 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1853 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1854 __ lwz(R11_scratch1, simm16_offs, tmp);
1855 __ addi(R11_scratch1, R11_scratch1, 1);
1856 __ stw(R11_scratch1, simm16_offs, tmp);
1857 }
1858 #endif
1859 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1860
1861 __ nand(tmp, R3_RET, R3_RET);
1862 __ subf(length, tmp, length);
1863 __ add(src_pos, tmp, src_pos);
1864 __ add(dst_pos, tmp, dst_pos);
1865
1866 __ cmpwi(CCR0, R3_RET, 0);
1867 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1868 __ bind(*stub->continuation());
1869 return;
1870 }
1871
1872 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1873 Label cont, slow, copyfunc;
1874
1875 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1876 LIR_OpArrayCopy::dst_null_check |
1877 LIR_OpArrayCopy::src_pos_positive_check |
1878 LIR_OpArrayCopy::dst_pos_positive_check |
1879 LIR_OpArrayCopy::length_positive_check);
1880
1881 // Use only one conditional branch for simple checks.
1882 if (simple_check_flag_set) {
1883 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1884
1885 // Make sure src and dst are non-null.
1886 if (flags & LIR_OpArrayCopy::src_null_check) {
1887 __ cmpdi(combined_check, src, 0);
1888 tmp_check = CCR0;
1889 }
1890
1891 if (flags & LIR_OpArrayCopy::dst_null_check) {
1892 __ cmpdi(tmp_check, dst, 0);
1893 if (tmp_check != combined_check) {
1894 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1895 }
1896 tmp_check = CCR0;
1897 }
1898
1899 // Clear combined_check.eq if not already used.
1900 if (tmp_check == combined_check) {
1901 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1902 tmp_check = CCR0;
1903 }
1904
1905 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1906 // Test src_pos register.
1907 __ cmpwi(tmp_check, src_pos, 0);
1908 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1909 }
1910
1911 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1912 // Test dst_pos register.
1913 __ cmpwi(tmp_check, dst_pos, 0);
1914 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1915 }
1916
1917 if (flags & LIR_OpArrayCopy::length_positive_check) {
1918 // Make sure length isn't negative.
1919 __ cmpwi(tmp_check, length, 0);
1920 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1921 }
1922
1923 __ beq(combined_check, slow);
1924 }
1925
1926 // If the compiler was not able to prove that exact type of the source or the destination
1927 // of the arraycopy is an array type, check at runtime if the source or the destination is
1928 // an instance type.
1929 if (flags & LIR_OpArrayCopy::type_check) {
1930 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1931 __ load_klass(tmp, dst);
1932 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1933 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1934 __ bge(CCR0, slow);
1935 }
1936
1937 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1938 __ load_klass(tmp, src);
1939 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1940 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1941 __ bge(CCR0, slow);
1942 }
1943 }
1944
1945 // Higher 32bits must be null.
1946 __ extsw(length, length);
1947
1948 __ extsw(src_pos, src_pos);
1949 if (flags & LIR_OpArrayCopy::src_range_check) {
1950 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1951 __ add(tmp, length, src_pos);
1952 __ cmpld(CCR0, tmp2, tmp);
1953 __ ble(CCR0, slow);
1954 }
1955
1956 __ extsw(dst_pos, dst_pos);
1957 if (flags & LIR_OpArrayCopy::dst_range_check) {
1958 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1959 __ add(tmp, length, dst_pos);
1960 __ cmpld(CCR0, tmp2, tmp);
1961 __ ble(CCR0, slow);
1962 }
1963
1964 int shift = shift_amount(basic_type);
1965
1966 if (!(flags & LIR_OpArrayCopy::type_check)) {
1967 __ b(cont);
1968 } else {
1969 // We don't know the array types are compatible.
1970 if (basic_type != T_OBJECT) {
1971 // Simple test for basic type arrays.
1972 if (UseCompressedClassPointers) {
1973 // We don't need decode because we just need to compare.
1974 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1975 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1976 __ cmpw(CCR0, tmp, tmp2);
1977 } else {
1978 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1979 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1980 __ cmpd(CCR0, tmp, tmp2);
1981 }
1982 __ beq(CCR0, cont);
1983 } else {
1984 // For object arrays, if src is a sub class of dst then we can
1985 // safely do the copy.
1986 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1987
1988 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1989 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1990
1991 __ load_klass(sub_klass, src);
1992 __ load_klass(super_klass, dst);
1993
1994 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1995 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
1996
1997 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
1998 //__ load_const_optimized(tmp, slow_stc, tmp2);
1999 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2000 __ mtctr(tmp);
2001 __ bctrl(); // sets CR0
2002 __ beq(CCR0, cont);
2003
2004 if (copyfunc_addr != NULL) { // Use stub if available.
2005 __ bind(copyfunc);
2006 // Src is not a sub class of dst so we have to do a
2007 // per-element check.
2008 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2009 if ((flags & mask) != mask) {
2010 assert(flags & mask, "one of the two should be known to be an object array");
2011
2012 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2013 __ load_klass(tmp, src);
2014 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2015 __ load_klass(tmp, dst);
2016 }
2017
2018 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2019
2020 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2021 __ load_const_optimized(tmp, objArray_lh);
2022 __ cmpw(CCR0, tmp, tmp2);
2023 __ bne(CCR0, slow);
2024 }
2025
2026 Register src_ptr = R3_ARG1;
2027 Register dst_ptr = R4_ARG2;
2028 Register len = R5_ARG3;
2029 Register chk_off = R6_ARG4;
2030 Register super_k = R7_ARG5;
2031
2032 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2033 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2034 if (shift == 0) {
2035 __ add(src_ptr, src_pos, src_ptr);
2036 __ add(dst_ptr, dst_pos, dst_ptr);
2037 } else {
2038 __ sldi(tmp, src_pos, shift);
2039 __ sldi(tmp2, dst_pos, shift);
2040 __ add(src_ptr, tmp, src_ptr);
2041 __ add(dst_ptr, tmp2, dst_ptr);
2042 }
2043
2044 __ load_klass(tmp, dst);
2045 __ mr(len, length);
2046
2047 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2048 __ ld(super_k, ek_offset, tmp);
2049
2050 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2051 __ lwz(chk_off, sco_offset, super_k);
2052
2053 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2054
2055 #ifndef PRODUCT
2056 if (PrintC1Statistics) {
2057 Label failed;
2058 __ cmpwi(CCR0, R3_RET, 0);
2059 __ bne(CCR0, failed);
2060 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2061 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2062 __ lwz(R11_scratch1, simm16_offs, tmp);
2063 __ addi(R11_scratch1, R11_scratch1, 1);
2064 __ stw(R11_scratch1, simm16_offs, tmp);
2065 __ bind(failed);
2066 }
2067 #endif
2068
2069 __ nand(tmp, R3_RET, R3_RET);
2070 __ cmpwi(CCR0, R3_RET, 0);
2071 __ beq(CCR0, *stub->continuation());
2072
2073 #ifndef PRODUCT
2074 if (PrintC1Statistics) {
2075 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2076 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2077 __ lwz(R11_scratch1, simm16_offs, tmp);
2078 __ addi(R11_scratch1, R11_scratch1, 1);
2079 __ stw(R11_scratch1, simm16_offs, tmp);
2080 }
2081 #endif
2082
2083 __ subf(length, tmp, length);
2084 __ add(src_pos, tmp, src_pos);
2085 __ add(dst_pos, tmp, dst_pos);
2086 }
2087 }
2088 }
2089 __ bind(slow);
2090 __ b(*stub->entry());
2091 __ bind(cont);
2092
2093 #ifdef ASSERT
2094 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2095 // Sanity check the known type with the incoming class. For the
2096 // primitive case the types must match exactly with src.klass and
2097 // dst.klass each exactly matching the default type. For the
2098 // object array case, if no type check is needed then either the
2099 // dst type is exactly the expected type and the src type is a
2100 // subtype which we can't check or src is the same array as dst
2101 // but not necessarily exactly of type default_type.
2102 Label known_ok, halt;
2103 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2104 if (UseCompressedClassPointers) {
2105 // Tmp holds the default type. It currently comes uncompressed after the
2106 // load of a constant, so encode it.
2107 __ encode_klass_not_null(tmp);
2108 // Load the raw value of the dst klass, since we will be comparing
2109 // uncompressed values directly.
2110 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2111 __ cmpw(CCR0, tmp, tmp2);
2112 if (basic_type != T_OBJECT) {
2113 __ bne(CCR0, halt);
2114 // Load the raw value of the src klass.
2115 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2116 __ cmpw(CCR0, tmp, tmp2);
2117 __ beq(CCR0, known_ok);
2118 } else {
2119 __ beq(CCR0, known_ok);
2120 __ cmpw(CCR0, src, dst);
2121 __ beq(CCR0, known_ok);
2122 }
2123 } else {
2124 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2125 __ cmpd(CCR0, tmp, tmp2);
2126 if (basic_type != T_OBJECT) {
2127 __ bne(CCR0, halt);
2128 // Load the raw value of the src klass.
2129 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2130 __ cmpd(CCR0, tmp, tmp2);
2131 __ beq(CCR0, known_ok);
2132 } else {
2133 __ beq(CCR0, known_ok);
2134 __ cmpd(CCR0, src, dst);
2135 __ beq(CCR0, known_ok);
2136 }
2137 }
2138 __ bind(halt);
2139 __ stop("incorrect type information in arraycopy");
2140 __ bind(known_ok);
2141 }
2142 #endif
2143
2144 #ifndef PRODUCT
2145 if (PrintC1Statistics) {
2146 address counter = Runtime1::arraycopy_count_address(basic_type);
2147 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2148 __ lwz(R11_scratch1, simm16_offs, tmp);
2149 __ addi(R11_scratch1, R11_scratch1, 1);
2150 __ stw(R11_scratch1, simm16_offs, tmp);
2151 }
2152 #endif
2153
2154 Register src_ptr = R3_ARG1;
2155 Register dst_ptr = R4_ARG2;
2156 Register len = R5_ARG3;
2157
2158 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2159 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2160 if (shift == 0) {
2161 __ add(src_ptr, src_pos, src_ptr);
2162 __ add(dst_ptr, dst_pos, dst_ptr);
2163 } else {
2164 __ sldi(tmp, src_pos, shift);
2165 __ sldi(tmp2, dst_pos, shift);
2166 __ add(src_ptr, tmp, src_ptr);
2167 __ add(dst_ptr, tmp2, dst_ptr);
2168 }
2169
2170 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2171 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2172 const char *name;
2173 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2174
2175 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2176 __ mr(len, length);
2177 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2178
2179 __ bind(*stub->continuation());
2180 }
2181
2182
2183 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2184 if (dest->is_single_cpu()) {
2185 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2186 #ifdef _LP64
2187 if (left->type() == T_OBJECT) {
2188 switch (code) {
2189 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2190 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2191 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2192 default: ShouldNotReachHere();
2193 }
2194 } else
2195 #endif
2196 switch (code) {
2197 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2198 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2199 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2200 default: ShouldNotReachHere();
2201 }
2202 } else {
2203 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2204 switch (code) {
2205 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2206 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2207 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2208 default: ShouldNotReachHere();
2209 }
2210 }
2211 }
2212
2213
2214 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2215 #ifdef _LP64
2216 if (left->type() == T_OBJECT) {
2217 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2218 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2219 else {
2220 switch (code) {
2221 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2222 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2223 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2224 default: ShouldNotReachHere();
2225 }
2226 }
2227 return;
2228 }
2229 #endif
2230
2231 if (dest->is_single_cpu()) {
2232 count = count & 0x1F; // Java spec
2233 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2234 else {
2235 switch (code) {
2236 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2237 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2238 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2239 default: ShouldNotReachHere();
2240 }
2241 }
2242 } else if (dest->is_double_cpu()) {
2243 count = count & 63; // Java spec
2244 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2245 else {
2246 switch (code) {
2247 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2248 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2249 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2250 default: ShouldNotReachHere();
2251 }
2252 }
2253 } else {
2254 ShouldNotReachHere();
2255 }
2256 }
2257
2258
2259 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2260 if (op->init_check()) {
2261 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2262 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2263 } else {
2264 add_debug_info_for_null_check_here(op->stub()->info());
2265 }
2266 __ lbz(op->tmp1()->as_register(),
2267 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2268 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2269 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2270 }
2271 __ allocate_object(op->obj()->as_register(),
2272 op->tmp1()->as_register(),
2273 op->tmp2()->as_register(),
2274 op->tmp3()->as_register(),
2275 op->header_size(),
2276 op->object_size(),
2277 op->klass()->as_register(),
2278 *op->stub()->entry());
2279
2280 __ bind(*op->stub()->continuation());
2281 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2282 }
2283
2284
2285 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2286 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2287 if (UseSlowPath ||
2288 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2289 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2290 __ b(*op->stub()->entry());
2291 } else {
2292 __ allocate_array(op->obj()->as_register(),
2293 op->len()->as_register(),
2294 op->tmp1()->as_register(),
2295 op->tmp2()->as_register(),
2296 op->tmp3()->as_register(),
2297 arrayOopDesc::header_size(op->type()),
2298 type2aelembytes(op->type()),
2299 op->klass()->as_register(),
2300 *op->stub()->entry());
2301 }
2302 __ bind(*op->stub()->continuation());
2303 }
2304
2305
2306 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2307 ciMethodData *md, ciProfileData *data,
2308 Register recv, Register tmp1, Label* update_done) {
2309 uint i;
2310 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2311 Label next_test;
2312 // See if the receiver is receiver[n].
2313 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2314 __ verify_klass_ptr(tmp1);
2315 __ cmpd(CCR0, recv, tmp1);
2316 __ bne(CCR0, next_test);
2317
2318 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2319 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2320 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2321 __ b(*update_done);
2322
2323 __ bind(next_test);
2324 }
2325
2326 // Didn't find receiver; find next empty slot and fill it in.
2327 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2328 Label next_test;
2329 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2330 __ cmpdi(CCR0, tmp1, 0);
2331 __ bne(CCR0, next_test);
2332 __ li(tmp1, DataLayout::counter_increment);
2333 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2334 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2335 __ b(*update_done);
2336
2337 __ bind(next_test);
2338 }
2339 }
2340
2341
2342 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2343 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2344 md = method->method_data_or_null();
2345 assert(md != NULL, "Sanity");
2346 data = md->bci_to_data(bci);
2347 assert(data != NULL, "need data for checkcast");
2348 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2349 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2350 // The offset is large so bias the mdo by the base of the slot so
2351 // that the ld can use simm16s to reference the slots of the data.
2352 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2353 }
2354 }
2355
2356
2357 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2358 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2359 Register k_RInfo = op->tmp1()->as_register();
2360 Register klass_RInfo = op->tmp2()->as_register();
2361 Register Rtmp1 = op->tmp3()->as_register();
2362 Register dst = op->result_opr()->as_register();
2363 ciKlass* k = op->klass();
2364 bool should_profile = op->should_profile();
2365 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2366 bool reg_conflict = false;
2367 if (obj == k_RInfo) {
2368 k_RInfo = dst;
2369 reg_conflict = true;
2370 } else if (obj == klass_RInfo) {
2371 klass_RInfo = dst;
2372 reg_conflict = true;
2373 } else if (obj == Rtmp1) {
2374 Rtmp1 = dst;
2375 reg_conflict = true;
2376 }
2377 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2378
2379 __ cmpdi(CCR0, obj, 0);
2380
2381 ciMethodData* md = NULL;
2382 ciProfileData* data = NULL;
2383 int mdo_offset_bias = 0;
2384 if (should_profile) {
2385 ciMethod* method = op->profiled_method();
2386 assert(method != NULL, "Should have method");
2387 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2388
2389 Register mdo = k_RInfo;
2390 Register data_val = Rtmp1;
2391 Label not_null;
2392 __ bne(CCR0, not_null);
2393 metadata2reg(md->constant_encoding(), mdo);
2394 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2395 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2396 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2397 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2398 __ b(*obj_is_null);
2399 __ bind(not_null);
2400 } else {
2401 __ beq(CCR0, *obj_is_null);
2402 }
2403
2404 // get object class
2405 __ load_klass(klass_RInfo, obj);
2406
2407 if (k->is_loaded()) {
2408 metadata2reg(k->constant_encoding(), k_RInfo);
2409 } else {
2410 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2411 }
2412
2413 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2414 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2415 Label *success_target = should_profile ? &profile_cast_success : success;
2416
2417 if (op->fast_check()) {
2418 assert_different_registers(klass_RInfo, k_RInfo);
2419 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2420 if (should_profile) {
2421 __ bne(CCR0, *failure_target);
2422 // Fall through to success case.
2423 } else {
2424 __ beq(CCR0, *success);
2425 // Fall through to failure case.
2426 }
2427 } else {
2428 bool need_slow_path = true;
2429 if (k->is_loaded()) {
2430 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2431 need_slow_path = false;
2432 }
2433 // Perform the fast part of the checking logic.
2434 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2435 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2436 } else {
2437 // Perform the fast part of the checking logic.
2438 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2439 }
2440 if (!need_slow_path) {
2441 if (!should_profile) { __ b(*success); }
2442 } else {
2443 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2444 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2445 // Stub needs fixed registers (tmp1-3).
2446 Register original_k_RInfo = op->tmp1()->as_register();
2447 Register original_klass_RInfo = op->tmp2()->as_register();
2448 Register original_Rtmp1 = op->tmp3()->as_register();
2449 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2450 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2451 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2452 __ mr_if_needed(original_k_RInfo, k_RInfo);
2453 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2454 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2455 //__ load_const_optimized(original_Rtmp1, entry, R0);
2456 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2457 __ mtctr(original_Rtmp1);
2458 __ bctrl(); // sets CR0
2459 if (keep_obj_alive) {
2460 if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2461 __ mr(obj, dst);
2462 }
2463 if (should_profile) {
2464 __ bne(CCR0, *failure_target);
2465 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2466 // Fall through to success case.
2467 } else {
2468 __ beq(CCR0, *success);
2469 // Fall through to failure case.
2470 }
2471 }
2472 }
2473
2474 if (should_profile) {
2475 Register mdo = k_RInfo, recv = klass_RInfo;
2476 assert_different_registers(mdo, recv, Rtmp1);
2477 __ bind(profile_cast_success);
2478 metadata2reg(md->constant_encoding(), mdo);
2479 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2480 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2481 __ b(*success);
2482
2483 // Cast failure case.
2484 __ bind(profile_cast_failure);
2485 metadata2reg(md->constant_encoding(), mdo);
2486 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2487 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2488 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2489 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2490 }
2491
2492 __ bind(*failure);
2493 }
2494
2495
2496 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2497 LIR_Code code = op->code();
2498 if (code == lir_store_check) {
2499 Register value = op->object()->as_register();
2500 Register array = op->array()->as_register();
2501 Register k_RInfo = op->tmp1()->as_register();
2502 Register klass_RInfo = op->tmp2()->as_register();
2503 Register Rtmp1 = op->tmp3()->as_register();
2504 bool should_profile = op->should_profile();
2505
2506 __ verify_oop(value, FILE_AND_LINE);
2507 CodeStub* stub = op->stub();
2508 // Check if it needs to be profiled.
2509 ciMethodData* md = NULL;
2510 ciProfileData* data = NULL;
2511 int mdo_offset_bias = 0;
2512 if (should_profile) {
2513 ciMethod* method = op->profiled_method();
2514 assert(method != NULL, "Should have method");
2515 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2516 }
2517 Label profile_cast_success, failure, done;
2518 Label *success_target = should_profile ? &profile_cast_success : &done;
2519
2520 __ cmpdi(CCR0, value, 0);
2521 if (should_profile) {
2522 Label not_null;
2523 __ bne(CCR0, not_null);
2524 Register mdo = k_RInfo;
2525 Register data_val = Rtmp1;
2526 metadata2reg(md->constant_encoding(), mdo);
2527 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2528 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2529 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2530 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2531 __ b(done);
2532 __ bind(not_null);
2533 } else {
2534 __ beq(CCR0, done);
2535 }
2536 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2537 explicit_null_check(array, op->info_for_exception());
2538 } else {
2539 add_debug_info_for_null_check_here(op->info_for_exception());
2540 }
2541 __ load_klass(k_RInfo, array);
2542 __ load_klass(klass_RInfo, value);
2543
2544 // Get instance klass.
2545 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2546 // Perform the fast part of the checking logic.
2547 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2548
2549 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2550 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2551 //__ load_const_optimized(R0, slow_path);
2552 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2553 __ mtctr(R0);
2554 __ bctrl(); // sets CR0
2555 if (!should_profile) {
2556 __ beq(CCR0, done);
2557 __ bind(failure);
2558 } else {
2559 __ bne(CCR0, failure);
2560 // Fall through to the success case.
2561
2562 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2563 assert_different_registers(value, mdo, recv, tmp1);
2564 __ bind(profile_cast_success);
2565 metadata2reg(md->constant_encoding(), mdo);
2566 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2567 __ load_klass(recv, value);
2568 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2569 __ b(done);
2570
2571 // Cast failure case.
2572 __ bind(failure);
2573 metadata2reg(md->constant_encoding(), mdo);
2574 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2575 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2576 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2577 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2578 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2579 }
2580 __ b(*stub->entry());
2581 __ bind(done);
2582
2583 } else if (code == lir_checkcast) {
2584 Label success, failure;
2585 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2586 __ b(*op->stub()->entry());
2587 __ align(32, 12);
2588 __ bind(success);
2589 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2590 } else if (code == lir_instanceof) {
2591 Register dst = op->result_opr()->as_register();
2592 Label success, failure, done;
2593 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2594 __ li(dst, 0);
2595 __ b(done);
2596 __ align(32, 12);
2597 __ bind(success);
2598 __ li(dst, 1);
2599 __ bind(done);
2600 } else {
2601 ShouldNotReachHere();
2602 }
2603 }
2604
2605
2606 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2607 Register addr = op->addr()->as_pointer_register();
2608 Register cmp_value = noreg, new_value = noreg;
2609 bool is_64bit = false;
2610
2611 if (op->code() == lir_cas_long) {
2612 cmp_value = op->cmp_value()->as_register_lo();
2613 new_value = op->new_value()->as_register_lo();
2614 is_64bit = true;
2615 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2616 cmp_value = op->cmp_value()->as_register();
2617 new_value = op->new_value()->as_register();
2618 if (op->code() == lir_cas_obj) {
2619 if (UseCompressedOops) {
2620 Register t1 = op->tmp1()->as_register();
2621 Register t2 = op->tmp2()->as_register();
2622 cmp_value = __ encode_heap_oop(t1, cmp_value);
2623 new_value = __ encode_heap_oop(t2, new_value);
2624 } else {
2625 is_64bit = true;
2626 }
2627 }
2628 } else {
2629 Unimplemented();
2630 }
2631
2632 if (is_64bit) {
2633 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2634 MacroAssembler::MemBarNone,
2635 MacroAssembler::cmpxchgx_hint_atomic_update(),
2636 noreg, NULL, /*check without ldarx first*/true);
2637 } else {
2638 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2639 MacroAssembler::MemBarNone,
2640 MacroAssembler::cmpxchgx_hint_atomic_update(),
2641 noreg, /*check without ldarx first*/true);
2642 }
2643
2644 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2645 __ isync();
2646 } else {
2647 __ sync();
2648 }
2649 }
2650
2651 void LIR_Assembler::breakpoint() {
2652 __ illtrap();
2653 }
2654
2655
2656 void LIR_Assembler::push(LIR_Opr opr) {
2657 Unimplemented();
2658 }
2659
2660 void LIR_Assembler::pop(LIR_Opr opr) {
2661 Unimplemented();
2662 }
2663
2664
2665 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2666 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2667 Register dst = dst_opr->as_register();
2668 Register reg = mon_addr.base();
2669 int offset = mon_addr.disp();
2670 // Compute pointer to BasicLock.
2671 __ add_const_optimized(dst, reg, offset);
2672 }
2673
2674
2675 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2676 Register obj = op->obj_opr()->as_register();
2677 Register hdr = op->hdr_opr()->as_register();
2678 Register lock = op->lock_opr()->as_register();
2679
2680 // Obj may not be an oop.
2681 if (op->code() == lir_lock) {
2682 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2683 if (!UseHeavyMonitors) {
2684 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2685 // Add debug info for NullPointerException only if one is possible.
2686 if (op->info() != NULL) {
2687 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2688 explicit_null_check(obj, op->info());
2689 } else {
2690 add_debug_info_for_null_check_here(op->info());
2691 }
2692 }
2693 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2694 } else {
2695 // always do slow locking
2696 // note: The slow locking code could be inlined here, however if we use
2697 // slow locking, speed doesn't matter anyway and this solution is
2698 // simpler and requires less duplicated code - additionally, the
2699 // slow locking code is the same in either case which simplifies
2700 // debugging.
2701 if (op->info() != NULL) {
2702 add_debug_info_for_null_check_here(op->info());
2703 __ null_check(obj);
2704 }
2705 __ b(*op->stub()->entry());
2706 }
2707 } else {
2708 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2709 if (!UseHeavyMonitors) {
2710 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2711 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2712 } else {
2713 // always do slow unlocking
2714 // note: The slow unlocking code could be inlined here, however if we use
2715 // slow unlocking, speed doesn't matter anyway and this solution is
2716 // simpler and requires less duplicated code - additionally, the
2717 // slow unlocking code is the same in either case which simplifies
2718 // debugging.
2719 __ b(*op->stub()->entry());
2720 }
2721 }
2722 __ bind(*op->stub()->continuation());
2723 }
2724
2725 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2726 Register obj = op->obj()->as_pointer_register();
2727 Register result = op->result_opr()->as_pointer_register();
2728
2729 CodeEmitInfo* info = op->info();
2730 if (info != NULL) {
2731 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2732 explicit_null_check(obj, info);
2733 } else {
2734 add_debug_info_for_null_check_here(info);
2735 }
2736 }
2737
2738 if (UseCompressedClassPointers) {
2739 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2740 __ decode_klass_not_null(result);
2741 } else {
2742 __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2743 }
2744 }
2745
2746 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2747 ciMethod* method = op->profiled_method();
2748 int bci = op->profiled_bci();
2749 ciMethod* callee = op->profiled_callee();
2750
2751 // Update counter for all call types.
2752 ciMethodData* md = method->method_data_or_null();
2753 assert(md != NULL, "Sanity");
2754 ciProfileData* data = md->bci_to_data(bci);
2755 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2756 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2757 Register mdo = op->mdo()->as_register();
2758 #ifdef _LP64
2759 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2760 Register tmp1 = op->tmp1()->as_register_lo();
2761 #else
2762 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2763 Register tmp1 = op->tmp1()->as_register();
2764 #endif
2765 metadata2reg(md->constant_encoding(), mdo);
2766 int mdo_offset_bias = 0;
2767 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2768 data->size_in_bytes())) {
2769 // The offset is large so bias the mdo by the base of the slot so
2770 // that the ld can use simm16s to reference the slots of the data.
2771 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2772 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2773 }
2774
2775 // Perform additional virtual call profiling for invokevirtual and
2776 // invokeinterface bytecodes
2777 if (op->should_profile_receiver_type()) {
2778 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2779 Register recv = op->recv()->as_register();
2780 assert_different_registers(mdo, tmp1, recv);
2781 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2782 ciKlass* known_klass = op->known_holder();
2783 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2784 // We know the type that will be seen at this call site; we can
2785 // statically update the MethodData* rather than needing to do
2786 // dynamic tests on the receiver type.
2787
2788 // NOTE: we should probably put a lock around this search to
2789 // avoid collisions by concurrent compilations.
2790 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2791 uint i;
2792 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2793 ciKlass* receiver = vc_data->receiver(i);
2794 if (known_klass->equals(receiver)) {
2795 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2796 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2797 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2798 return;
2799 }
2800 }
2801
2802 // Receiver type not found in profile data; select an empty slot.
2803
2804 // Note that this is less efficient than it should be because it
2805 // always does a write to the receiver part of the
2806 // VirtualCallData rather than just the first time.
2807 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2808 ciKlass* receiver = vc_data->receiver(i);
2809 if (receiver == NULL) {
2810 metadata2reg(known_klass->constant_encoding(), tmp1);
2811 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2812
2813 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2814 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2815 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2816 return;
2817 }
2818 }
2819 } else {
2820 __ load_klass(recv, recv);
2821 Label update_done;
2822 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2823 // Receiver did not match any saved receiver and there is no empty row for it.
2824 // Increment total counter to indicate polymorphic case.
2825 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2826 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2827 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2828
2829 __ bind(update_done);
2830 }
2831 } else {
2832 // Static call
2833 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2834 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2835 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2836 }
2837 }
2838
2839
2840 void LIR_Assembler::align_backward_branch_target() {
2841 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2842 }
2843
2844
2845 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2846 Unimplemented();
2847 }
2848
2849
2850 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2851 // tmp must be unused
2852 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2853 assert(left->is_register(), "can only handle registers");
2854
2855 if (left->is_single_cpu()) {
2856 __ neg(dest->as_register(), left->as_register());
2857 } else if (left->is_single_fpu()) {
2858 __ fneg(dest->as_float_reg(), left->as_float_reg());
2859 } else if (left->is_double_fpu()) {
2860 __ fneg(dest->as_double_reg(), left->as_double_reg());
2861 } else {
2862 assert (left->is_double_cpu(), "Must be a long");
2863 __ neg(dest->as_register_lo(), left->as_register_lo());
2864 }
2865 }
2866
2867
2868 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2869 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2870 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2871 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2872 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2873 //__ load_const_optimized(R0, dest);
2874 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2875 __ mtctr(R0);
2876 __ bctrl();
2877 assert(info != NULL, "sanity");
2878 add_call_info_here(info);
2879 return;
2880 }
2881
2882 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2883 if (info != NULL) {
2884 add_call_info_here(info);
2885 }
2886 }
2887
2888
2889 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2890 ShouldNotReachHere(); // Not needed on _LP64.
2891 }
2892
2893 void LIR_Assembler::membar() {
2894 __ fence();
2895 }
2896
2897 void LIR_Assembler::membar_acquire() {
2898 __ acquire();
2899 }
2900
2901 void LIR_Assembler::membar_release() {
2902 __ release();
2903 }
2904
2905 void LIR_Assembler::membar_loadload() {
2906 __ membar(Assembler::LoadLoad);
2907 }
2908
2909 void LIR_Assembler::membar_storestore() {
2910 __ membar(Assembler::StoreStore);
2911 }
2912
2913 void LIR_Assembler::membar_loadstore() {
2914 __ membar(Assembler::LoadStore);
2915 }
2916
2917 void LIR_Assembler::membar_storeload() {
2918 __ membar(Assembler::StoreLoad);
2919 }
2920
2921 void LIR_Assembler::on_spin_wait() {
2922 Unimplemented();
2923 }
2924
2925 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2926 LIR_Address* addr = addr_opr->as_address_ptr();
2927 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2928
2929 if (addr->index()->is_illegal()) {
2930 if (patch_code != lir_patch_none) {
2931 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2932 __ load_const32(R0, 0); // patchable int
2933 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2934 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2935 } else {
2936 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2937 }
2938 } else {
2939 assert(patch_code == lir_patch_none, "Patch code not supported");
2940 assert(addr->disp() == 0, "can't have both: index and disp");
2941 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2942 }
2943 }
2944
2945
2946 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2947 ShouldNotReachHere();
2948 }
2949
2950
2951 #ifdef ASSERT
2952 // Emit run-time assertion.
2953 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2954 Unimplemented();
2955 }
2956 #endif
2957
2958
2959 void LIR_Assembler::peephole(LIR_List* lir) {
2960 // Optimize instruction pairs before emitting.
2961 LIR_OpList* inst = lir->instructions_list();
2962 for (int i = 1; i < inst->length(); i++) {
2963 LIR_Op* op = inst->at(i);
2964
2965 // 2 register-register-moves
2966 if (op->code() == lir_move) {
2967 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2968 res2 = ((LIR_Op1*)op)->result_opr();
2969 if (in2->is_register() && res2->is_register()) {
2970 LIR_Op* prev = inst->at(i - 1);
2971 if (prev && prev->code() == lir_move) {
2972 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2973 res1 = ((LIR_Op1*)prev)->result_opr();
2974 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2975 inst->remove_at(i);
2976 }
2977 }
2978 }
2979 }
2980
2981 }
2982 return;
2983 }
2984
2985
2986 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2987 const LIR_Address *addr = src->as_address_ptr();
2988 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2989 const Register Rptr = addr->base()->as_pointer_register(),
2990 Rtmp = tmp->as_register();
2991 Register Rco = noreg;
2992 if (UseCompressedOops && data->is_oop()) {
2993 Rco = __ encode_heap_oop(Rtmp, data->as_register());
2994 }
2995
2996 Label Lretry;
2997 __ bind(Lretry);
2998
2999 if (data->type() == T_INT) {
3000 const Register Rold = dest->as_register(),
3001 Rsrc = data->as_register();
3002 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3003 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3004 if (code == lir_xadd) {
3005 __ add(Rtmp, Rsrc, Rold);
3006 __ stwcx_(Rtmp, Rptr);
3007 } else {
3008 __ stwcx_(Rsrc, Rptr);
3009 }
3010 } else if (data->is_oop()) {
3011 assert(code == lir_xchg, "xadd for oops");
3012 const Register Rold = dest->as_register();
3013 if (UseCompressedOops) {
3014 assert_different_registers(Rptr, Rold, Rco);
3015 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3016 __ stwcx_(Rco, Rptr);
3017 } else {
3018 const Register Robj = data->as_register();
3019 assert_different_registers(Rptr, Rold, Robj);
3020 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3021 __ stdcx_(Robj, Rptr);
3022 }
3023 } else if (data->type() == T_LONG) {
3024 const Register Rold = dest->as_register_lo(),
3025 Rsrc = data->as_register_lo();
3026 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3027 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3028 if (code == lir_xadd) {
3029 __ add(Rtmp, Rsrc, Rold);
3030 __ stdcx_(Rtmp, Rptr);
3031 } else {
3032 __ stdcx_(Rsrc, Rptr);
3033 }
3034 } else {
3035 ShouldNotReachHere();
3036 }
3037
3038 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3039 __ bne_predict_not_taken(CCR0, Lretry);
3040 } else {
3041 __ bne( CCR0, Lretry);
3042 }
3043
3044 if (UseCompressedOops && data->is_oop()) {
3045 __ decode_heap_oop(dest->as_register());
3046 }
3047 }
3048
3049
3050 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3051 Register obj = op->obj()->as_register();
3052 Register tmp = op->tmp()->as_pointer_register();
3053 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3054 ciKlass* exact_klass = op->exact_klass();
3055 intptr_t current_klass = op->current_klass();
3056 bool not_null = op->not_null();
3057 bool no_conflict = op->no_conflict();
3058
3059 Label Lupdate, Ldo_update, Ldone;
3060
3061 bool do_null = !not_null;
3062 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3063 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3064
3065 assert(do_null || do_update, "why are we here?");
3066 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3067
3068 __ verify_oop(obj, FILE_AND_LINE);
3069
3070 if (do_null) {
3071 if (!TypeEntries::was_null_seen(current_klass)) {
3072 __ cmpdi(CCR0, obj, 0);
3073 __ bne(CCR0, Lupdate);
3074 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3075 __ ori(R0, R0, TypeEntries::null_seen);
3076 if (do_update) {
3077 __ b(Ldo_update);
3078 } else {
3079 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3080 }
3081 } else {
3082 if (do_update) {
3083 __ cmpdi(CCR0, obj, 0);
3084 __ beq(CCR0, Ldone);
3085 }
3086 }
3087 #ifdef ASSERT
3088 } else {
3089 __ cmpdi(CCR0, obj, 0);
3090 __ bne(CCR0, Lupdate);
3091 __ stop("unexpected null obj");
3092 #endif
3093 }
3094
3095 __ bind(Lupdate);
3096 if (do_update) {
3097 Label Lnext;
3098 const Register klass = R29_TOC; // kill and reload
3099 bool klass_reg_used = false;
3100 #ifdef ASSERT
3101 if (exact_klass != NULL) {
3102 Label ok;
3103 klass_reg_used = true;
3104 __ load_klass(klass, obj);
3105 metadata2reg(exact_klass->constant_encoding(), R0);
3106 __ cmpd(CCR0, klass, R0);
3107 __ beq(CCR0, ok);
3108 __ stop("exact klass and actual klass differ");
3109 __ bind(ok);
3110 }
3111 #endif
3112
3113 if (!no_conflict) {
3114 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3115 klass_reg_used = true;
3116 if (exact_klass != NULL) {
3117 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3118 metadata2reg(exact_klass->constant_encoding(), klass);
3119 } else {
3120 __ load_klass(klass, obj);
3121 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3122 }
3123
3124 // Like InterpreterMacroAssembler::profile_obj_type
3125 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3126 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3127 __ cmpd(CCR1, R0, klass);
3128 // Klass seen before, nothing to do (regardless of unknown bit).
3129 //beq(CCR1, do_nothing);
3130
3131 __ andi_(R0, klass, TypeEntries::type_unknown);
3132 // Already unknown. Nothing to do anymore.
3133 //bne(CCR0, do_nothing);
3134 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3135 __ beq(CCR0, Lnext);
3136
3137 if (TypeEntries::is_type_none(current_klass)) {
3138 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3139 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3140 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3141 }
3142
3143 } else {
3144 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3145 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3146
3147 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3148 __ andi_(R0, tmp, TypeEntries::type_unknown);
3149 // Already unknown. Nothing to do anymore.
3150 __ bne(CCR0, Lnext);
3151 }
3152
3153 // Different than before. Cannot keep accurate profile.
3154 __ ori(R0, tmp, TypeEntries::type_unknown);
3155 } else {
3156 // There's a single possible klass at this profile point
3157 assert(exact_klass != NULL, "should be");
3158 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3159
3160 if (TypeEntries::is_type_none(current_klass)) {
3161 klass_reg_used = true;
3162 metadata2reg(exact_klass->constant_encoding(), klass);
3163
3164 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3165 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3166 __ cmpd(CCR1, R0, klass);
3167 // Klass seen before, nothing to do (regardless of unknown bit).
3168 __ beq(CCR1, Lnext);
3169 #ifdef ASSERT
3170 {
3171 Label ok;
3172 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3173 __ beq(CCR0, ok); // First time here.
3174
3175 __ stop("unexpected profiling mismatch");
3176 __ bind(ok);
3177 }
3178 #endif
3179 // First time here. Set profile type.
3180 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3181 } else {
3182 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3183 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3184
3185 // Already unknown. Nothing to do anymore.
3186 __ andi_(R0, tmp, TypeEntries::type_unknown);
3187 __ bne(CCR0, Lnext);
3188
3189 // Different than before. Cannot keep accurate profile.
3190 __ ori(R0, tmp, TypeEntries::type_unknown);
3191 }
3192 }
3193
3194 __ bind(Ldo_update);
3195 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3196
3197 __ bind(Lnext);
3198 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3199 }
3200 __ bind(Ldone);
3201 }
3202
3203 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3204 Unimplemented();
3205 }
3206
3207 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3208 assert(op->crc()->is_single_cpu(), "crc must be register");
3209 assert(op->val()->is_single_cpu(), "byte value must be register");
3210 assert(op->result_opr()->is_single_cpu(), "result must be register");
3211 Register crc = op->crc()->as_register();
3212 Register val = op->val()->as_register();
3213 Register res = op->result_opr()->as_register();
3214
3215 assert_different_registers(val, crc, res);
3216
3217 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3218 __ kernel_crc32_singleByteReg(crc, val, res, true);
3219 __ mr(res, crc);
3220 }
3221
3222 #undef __