1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/os.inline.hpp"
42 #include "runtime/safepointMechanism.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/vm_version.hpp"
46 #include "utilities/macros.hpp"
47 #include "utilities/powerOfTwo.hpp"
48
49 #define __ _masm->
50
51
52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
53
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 Unimplemented(); return false; // Currently not used on this platform.
57 }
58
59
60 LIR_Opr LIR_Assembler::receiverOpr() {
61 return FrameMap::R3_oop_opr;
62 }
63
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::R3_opr;
67 }
68
69
70 // This specifies the stack pointer decrement needed to build the frame.
71 int LIR_Assembler::initial_frame_size_in_bytes() const {
72 return in_bytes(frame_map()->framesize_in_bytes());
73 }
74
75
76 // Inline cache check: the inline cached class is in inline_cache_reg;
77 // we fetch the class of the receiver and compare it with the cached class.
78 // If they do not match we jump to slow case.
79 int LIR_Assembler::check_icache() {
80 return __ ic_check(CodeEntryAlignment);
81 }
82
83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
84 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
85
86 Label L_skip_barrier;
87 Register klass = R20;
88
89 metadata2reg(method->holder()->constant_encoding(), klass);
90 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
91
92 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
93 __ mtctr(klass);
94 __ bctr();
95
96 __ bind(L_skip_barrier);
97 }
98
99 void LIR_Assembler::osr_entry() {
100 // On-stack-replacement entry sequence:
101 //
102 // 1. Create a new compiled activation.
103 // 2. Initialize local variables in the compiled activation. The expression
104 // stack must be empty at the osr_bci; it is not initialized.
105 // 3. Jump to the continuation address in compiled code to resume execution.
106
107 // OSR entry point
108 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
109 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
110 ValueStack* entry_state = osr_entry->end()->state();
111 int number_of_locks = entry_state->locks_size();
112
113 // Create a frame for the compiled activation.
114 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
115
116 // OSR buffer is
117 //
118 // locals[nlocals-1..0]
119 // monitors[number_of_locks-1..0]
120 //
121 // Locals is a direct copy of the interpreter frame so in the osr buffer
122 // the first slot in the local array is the last local from the interpreter
123 // and the last slot is local[0] (receiver) from the interpreter.
124 //
125 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
126 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
127 // in the interpreter frame (the method lock if a sync method).
128
129 // Initialize monitors in the compiled activation.
130 // R3: pointer to osr buffer
131 //
132 // All other registers are dead at this point and the locals will be
133 // copied into place by code emitted in the IR.
134
135 Register OSR_buf = osrBufferPointer()->as_register();
136 {
137 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
138
139 const int locals_space = BytesPerWord * method()->max_locals();
140 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
141 bool use_OSR_bias = false;
142
143 if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
144 // Offsets too large for ld instructions. Use bias.
145 __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
146 monitor_offset -= locals_space;
147 use_OSR_bias = true;
148 }
149
150 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
151 // the OSR buffer using 2 word entries: first the lock and then
152 // the oop.
153 for (int i = 0; i < number_of_locks; i++) {
154 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
155 #ifdef ASSERT
156 // Verify the interpreter's monitor has a non-null object.
157 {
158 Label L;
159 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
160 __ cmpdi(CCR0, R0, 0);
161 __ bne(CCR0, L);
162 __ stop("locked object is null");
163 __ bind(L);
164 }
165 #endif // ASSERT
166 // Copy the lock field into the compiled activation.
167 Address ml = frame_map()->address_for_monitor_lock(i),
168 mo = frame_map()->address_for_monitor_object(i);
169 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
170 __ ld(R0, slot_offset + 0, OSR_buf);
171 __ std(R0, ml);
172 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
173 __ std(R0, mo);
174 }
175
176 if (use_OSR_bias) {
177 // Restore.
178 __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
179 }
180 }
181 }
182
183
184 int LIR_Assembler::emit_exception_handler() {
185 // Generate code for the exception handler.
186 address handler_base = __ start_a_stub(exception_handler_size());
187
188 if (handler_base == nullptr) {
189 // Not enough space left for the handler.
190 bailout("exception handler overflow");
191 return -1;
192 }
193
194 int offset = code_offset();
195 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(C1StubId::handle_exception_from_callee_id));
196 //__ load_const_optimized(R0, entry_point);
197 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
198 __ mtctr(R0);
199 __ bctr();
200
201 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
202 __ end_a_stub();
203
204 return offset;
205 }
206
207
208 // Emit the code to remove the frame from the stack in the exception
209 // unwind path.
210 int LIR_Assembler::emit_unwind_handler() {
211 _masm->block_comment("Unwind handler");
212
213 int offset = code_offset();
214 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
215 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
216
217 // Fetch the exception from TLS and clear out exception related thread state.
218 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
219 __ li(R0, 0);
220 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
221 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
222
223 __ bind(_unwind_handler_entry);
224 __ verify_not_null_oop(Rexception);
225 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
226
227 // Perform needed unlocking
228 MonitorExitStub* stub = nullptr;
229 if (method()->is_synchronized()) {
230 monitor_address(0, FrameMap::R4_opr);
231 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
232 if (LockingMode == LM_MONITOR) {
233 __ b(*stub->entry());
234 } else {
235 __ unlock_object(R5, R6, R4, *stub->entry());
236 }
237 __ bind(*stub->continuation());
238 }
239
240 if (compilation()->env()->dtrace_method_probes()) {
241 Unimplemented();
242 }
243
244 // Dispatch to the unwind logic.
245 address unwind_stub = Runtime1::entry_for(C1StubId::unwind_exception_id);
246 //__ load_const_optimized(R0, unwind_stub);
247 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
248 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
249 __ mtctr(R0);
250 __ bctr();
251
252 // Emit the slow path assembly.
253 if (stub != nullptr) {
254 stub->emit_code(this);
255 }
256
257 return offset;
258 }
259
260
261 int LIR_Assembler::emit_deopt_handler() {
262 // Generate code for deopt handler.
263 address handler_base = __ start_a_stub(deopt_handler_size());
264
265 if (handler_base == nullptr) {
266 // Not enough space left for the handler.
267 bailout("deopt handler overflow");
268 return -1;
269 }
270
271 int offset = code_offset();
272 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
273
274 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
275 __ end_a_stub();
276
277 return offset;
278 }
279
280
281 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
282 if (o == nullptr) {
283 __ li(reg, 0);
284 } else {
285 AddressLiteral addrlit = __ constant_oop_address(o);
286 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
287 }
288 }
289
290
291 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
292 // Allocate a new index in table to hold the object once it's been patched.
293 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
294 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
295
296 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
297 __ load_const(reg, addrlit, R0);
298
299 patching_epilog(patch, lir_patch_normal, reg, info);
300 }
301
302
303 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
304 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
305 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
306 }
307
308
309 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
310 // Allocate a new index in table to hold the klass once it's been patched.
311 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
312 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
313
314 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
315 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
316 __ load_const(reg, addrlit, R0);
317
318 patching_epilog(patch, lir_patch_normal, reg, info);
319 }
320
321
322 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
323 const bool is_int = result->is_single_cpu();
324 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
325 Register Rdivisor = noreg;
326 Register Rscratch = temp->as_register();
327 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
328 long divisor = -1;
329
330 if (right->is_register()) {
331 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
332 } else {
333 divisor = is_int ? right->as_constant_ptr()->as_jint()
334 : right->as_constant_ptr()->as_jlong();
335 }
336
337 assert(Rdividend != Rscratch, "");
338 assert(Rdivisor != Rscratch, "");
339 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
340
341 if (Rdivisor == noreg) {
342 if (divisor == 1) { // stupid, but can happen
343 if (code == lir_idiv) {
344 __ mr_if_needed(Rresult, Rdividend);
345 } else {
346 __ li(Rresult, 0);
347 }
348
349 } else if (is_power_of_2(divisor)) {
350 // Convert division by a power of two into some shifts and logical operations.
351 int log2 = log2i_exact(divisor);
352
353 // Round towards 0.
354 if (divisor == 2) {
355 if (is_int) {
356 __ srwi(Rscratch, Rdividend, 31);
357 } else {
358 __ srdi(Rscratch, Rdividend, 63);
359 }
360 } else {
361 if (is_int) {
362 __ srawi(Rscratch, Rdividend, 31);
363 } else {
364 __ sradi(Rscratch, Rdividend, 63);
365 }
366 __ clrldi(Rscratch, Rscratch, 64-log2);
367 }
368 __ add(Rscratch, Rdividend, Rscratch);
369
370 if (code == lir_idiv) {
371 if (is_int) {
372 __ srawi(Rresult, Rscratch, log2);
373 } else {
374 __ sradi(Rresult, Rscratch, log2);
375 }
376 } else { // lir_irem
377 __ clrrdi(Rscratch, Rscratch, log2);
378 __ sub(Rresult, Rdividend, Rscratch);
379 }
380
381 } else if (divisor == -1) {
382 if (code == lir_idiv) {
383 __ neg(Rresult, Rdividend);
384 } else {
385 __ li(Rresult, 0);
386 }
387
388 } else {
389 __ load_const_optimized(Rscratch, divisor);
390 if (code == lir_idiv) {
391 if (is_int) {
392 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
393 } else {
394 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
395 }
396 } else {
397 assert(Rscratch != R0, "need both");
398 if (is_int) {
399 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
400 __ mullw(Rscratch, R0, Rscratch);
401 } else {
402 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
403 __ mulld(Rscratch, R0, Rscratch);
404 }
405 __ sub(Rresult, Rdividend, Rscratch);
406 }
407
408 }
409 return;
410 }
411
412 Label regular, done;
413 if (is_int) {
414 __ cmpwi(CCR0, Rdivisor, -1);
415 } else {
416 __ cmpdi(CCR0, Rdivisor, -1);
417 }
418 __ bne(CCR0, regular);
419 if (code == lir_idiv) {
420 __ neg(Rresult, Rdividend);
421 __ b(done);
422 __ bind(regular);
423 if (is_int) {
424 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
425 } else {
426 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
427 }
428 } else { // lir_irem
429 __ li(Rresult, 0);
430 __ b(done);
431 __ bind(regular);
432 if (is_int) {
433 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
434 __ mullw(Rscratch, Rscratch, Rdivisor);
435 } else {
436 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
437 __ mulld(Rscratch, Rscratch, Rdivisor);
438 }
439 __ sub(Rresult, Rdividend, Rscratch);
440 }
441 __ bind(done);
442 }
443
444
445 void LIR_Assembler::emit_op3(LIR_Op3* op) {
446 switch (op->code()) {
447 case lir_idiv:
448 case lir_irem:
449 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
450 op->result_opr(), op->info());
451 break;
452 case lir_fmad:
453 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
454 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
455 break;
456 case lir_fmaf:
457 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
458 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
459 break;
460 default: ShouldNotReachHere(); break;
461 }
462 }
463
464
465 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
466 #ifdef ASSERT
467 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
468 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
469 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
470 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
471 #endif
472
473 Label *L = op->label();
474 if (op->cond() == lir_cond_always) {
475 __ b(*L);
476 } else {
477 Label done;
478 bool is_unordered = false;
479 if (op->code() == lir_cond_float_branch) {
480 assert(op->ublock() != nullptr, "must have unordered successor");
481 is_unordered = true;
482 } else {
483 assert(op->code() == lir_branch, "just checking");
484 }
485
486 bool positive = false;
487 Assembler::Condition cond = Assembler::equal;
488 switch (op->cond()) {
489 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
490 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
491 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
492 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
493 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
494 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
495 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
496 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
497 default: ShouldNotReachHere();
498 }
499 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
500 int bi = Assembler::bi0(BOOL_RESULT, cond);
501 if (is_unordered) {
502 if (positive) {
503 if (op->ublock() == op->block()) {
504 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
505 }
506 } else {
507 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
508 }
509 }
510 __ bc_far_optimized(bo, bi, *L);
511 __ bind(done);
512 }
513 }
514
515
516 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
517 Bytecodes::Code code = op->bytecode();
518 LIR_Opr src = op->in_opr(),
519 dst = op->result_opr();
520
521 switch(code) {
522 case Bytecodes::_i2l: {
523 __ extsw(dst->as_register_lo(), src->as_register());
524 break;
525 }
526 case Bytecodes::_l2i: {
527 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
528 break;
529 }
530 case Bytecodes::_i2b: {
531 __ extsb(dst->as_register(), src->as_register());
532 break;
533 }
534 case Bytecodes::_i2c: {
535 __ clrldi(dst->as_register(), src->as_register(), 64-16);
536 break;
537 }
538 case Bytecodes::_i2s: {
539 __ extsh(dst->as_register(), src->as_register());
540 break;
541 }
542 case Bytecodes::_i2d:
543 case Bytecodes::_l2d: {
544 bool src_in_memory = !VM_Version::has_mtfprd();
545 FloatRegister rdst = dst->as_double_reg();
546 FloatRegister rsrc;
547 if (src_in_memory) {
548 rsrc = src->as_double_reg(); // via mem
549 } else {
550 // move src to dst register
551 if (code == Bytecodes::_i2d) {
552 __ mtfprwa(rdst, src->as_register());
553 } else {
554 __ mtfprd(rdst, src->as_register_lo());
555 }
556 rsrc = rdst;
557 }
558 __ fcfid(rdst, rsrc);
559 break;
560 }
561 case Bytecodes::_i2f:
562 case Bytecodes::_l2f: {
563 bool src_in_memory = !VM_Version::has_mtfprd();
564 FloatRegister rdst = dst->as_float_reg();
565 FloatRegister rsrc;
566 if (src_in_memory) {
567 rsrc = src->as_double_reg(); // via mem
568 } else {
569 // move src to dst register
570 if (code == Bytecodes::_i2f) {
571 __ mtfprwa(rdst, src->as_register());
572 } else {
573 __ mtfprd(rdst, src->as_register_lo());
574 }
575 rsrc = rdst;
576 }
577 if (VM_Version::has_fcfids()) {
578 __ fcfids(rdst, rsrc);
579 } else {
580 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
581 __ fcfid(rdst, rsrc);
582 __ frsp(rdst, rdst);
583 }
584 break;
585 }
586 case Bytecodes::_f2d: {
587 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
588 break;
589 }
590 case Bytecodes::_d2f: {
591 __ frsp(dst->as_float_reg(), src->as_double_reg());
592 break;
593 }
594 case Bytecodes::_d2i:
595 case Bytecodes::_f2i: {
596 bool dst_in_memory = !VM_Version::has_mtfprd();
597 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
598 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
599 Label L;
600 // Result must be 0 if value is NaN; test by comparing value to itself.
601 __ fcmpu(CCR0, rsrc, rsrc);
602 if (dst_in_memory) {
603 __ li(R0, 0); // 0 in case of NAN
604 __ std(R0, addr);
605 } else {
606 __ li(dst->as_register(), 0);
607 }
608 __ bso(CCR0, L);
609 __ fctiwz(rsrc, rsrc); // USE_KILL
610 if (dst_in_memory) {
611 __ stfd(rsrc, addr.disp(), addr.base());
612 } else {
613 __ mffprd(dst->as_register(), rsrc);
614 }
615 __ bind(L);
616 break;
617 }
618 case Bytecodes::_d2l:
619 case Bytecodes::_f2l: {
620 bool dst_in_memory = !VM_Version::has_mtfprd();
621 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
622 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
623 Label L;
624 // Result must be 0 if value is NaN; test by comparing value to itself.
625 __ fcmpu(CCR0, rsrc, rsrc);
626 if (dst_in_memory) {
627 __ li(R0, 0); // 0 in case of NAN
628 __ std(R0, addr);
629 } else {
630 __ li(dst->as_register_lo(), 0);
631 }
632 __ bso(CCR0, L);
633 __ fctidz(rsrc, rsrc); // USE_KILL
634 if (dst_in_memory) {
635 __ stfd(rsrc, addr.disp(), addr.base());
636 } else {
637 __ mffprd(dst->as_register_lo(), rsrc);
638 }
639 __ bind(L);
640 break;
641 }
642
643 default: ShouldNotReachHere();
644 }
645 }
646
647
648 void LIR_Assembler::align_call(LIR_Code) {
649 // do nothing since all instructions are word aligned on ppc
650 }
651
652
653 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
654 int start_offset = __ offset();
655 // Put the entry point as a constant into the constant pool.
656 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
657 if (entry_point_toc_addr == nullptr) {
658 bailout("const section overflow");
659 return false;
660 }
661 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
662
663 // Emit the trampoline stub which will be related to the branch-and-link below.
664 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
665 if (!stub) {
666 bailout("no space for trampoline stub");
667 return false;
668 }
669 return true;
670 }
671
672
673 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
674 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
675
676 bool success = emit_trampoline_stub_for_call(op->addr());
677 if (!success) { return; }
678
679 __ relocate(rtype);
680 // Note: At this point we do not have the address of the trampoline
681 // stub, and the entry point might be too far away for bl, so __ pc()
682 // serves as dummy and the bl will be patched later.
683 __ code()->set_insts_mark();
684 __ bl(__ pc());
685 add_call_info(code_offset(), op->info());
686 __ post_call_nop();
687 }
688
689
690 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
691 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
692
693 // Virtual call relocation will point to ic load.
694 address virtual_call_meta_addr = __ pc();
695 // Load a clear inline cache.
696 AddressLiteral empty_ic((address) Universe::non_oop_word());
697 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
698 if (!success) {
699 bailout("const section overflow");
700 return;
701 }
702 // Call to fixup routine. Fixup routine uses ScopeDesc info
703 // to determine who we intended to call.
704 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
705
706 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
707 if (!success) { return; }
708
709 // Note: At this point we do not have the address of the trampoline
710 // stub, and the entry point might be too far away for bl, so __ pc()
711 // serves as dummy and the bl will be patched later.
712 __ bl(__ pc());
713 add_call_info(code_offset(), op->info());
714 __ post_call_nop();
715 }
716
717 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
718 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
719 __ null_check(addr, stub->entry());
720 append_code_stub(stub);
721 }
722
723
724 // Attention: caller must encode oop if needed
725 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
726 int store_offset;
727 if (!Assembler::is_simm16(offset)) {
728 // For offsets larger than a simm16 we setup the offset.
729 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
730 __ load_const_optimized(R0, offset);
731 store_offset = store(from_reg, base, R0, type, wide);
732 } else {
733 store_offset = code_offset();
734 switch (type) {
735 case T_BOOLEAN: // fall through
736 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
737 case T_CHAR :
738 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
739 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
740 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
741 case T_ADDRESS:
742 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
743 case T_ARRAY : // fall through
744 case T_OBJECT:
745 {
746 if (UseCompressedOops && !wide) {
747 // Encoding done in caller
748 __ stw(from_reg->as_register(), offset, base);
749 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
750 } else {
751 __ std(from_reg->as_register(), offset, base);
752 if (VerifyOops) {
753 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
754 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
755 }
756 }
757 break;
758 }
759 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
760 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
761 default : ShouldNotReachHere();
762 }
763 }
764 return store_offset;
765 }
766
767
768 // Attention: caller must encode oop if needed
769 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
770 int store_offset = code_offset();
771 switch (type) {
772 case T_BOOLEAN: // fall through
773 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
774 case T_CHAR :
775 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
776 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
777 case T_LONG :
778 #ifdef _LP64
779 __ stdx(from_reg->as_register_lo(), base, disp);
780 #else
781 Unimplemented();
782 #endif
783 break;
784 case T_ADDRESS:
785 __ stdx(from_reg->as_register(), base, disp);
786 break;
787 case T_ARRAY : // fall through
788 case T_OBJECT:
789 {
790 if (UseCompressedOops && !wide) {
791 // Encoding done in caller.
792 __ stwx(from_reg->as_register(), base, disp);
793 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
794 } else {
795 __ stdx(from_reg->as_register(), base, disp);
796 if (VerifyOops) {
797 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
798 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
799 }
800 }
801 break;
802 }
803 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
804 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
805 default : ShouldNotReachHere();
806 }
807 return store_offset;
808 }
809
810
811 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
812 int load_offset;
813 if (!Assembler::is_simm16(offset)) {
814 // For offsets larger than a simm16 we setup the offset.
815 __ load_const_optimized(R0, offset);
816 load_offset = load(base, R0, to_reg, type, wide);
817 } else {
818 load_offset = code_offset();
819 switch(type) {
820 case T_BOOLEAN: // fall through
821 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
822 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
823 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
824 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
825 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
826 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
827 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
828 case T_ADDRESS:
829 __ ld(to_reg->as_register(), offset, base);
830 break;
831 case T_ARRAY : // fall through
832 case T_OBJECT:
833 {
834 if (UseCompressedOops && !wide) {
835 __ lwz(to_reg->as_register(), offset, base);
836 __ decode_heap_oop(to_reg->as_register());
837 } else {
838 __ ld(to_reg->as_register(), offset, base);
839 }
840 break;
841 }
842 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
843 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
844 default : ShouldNotReachHere();
845 }
846 }
847 return load_offset;
848 }
849
850
851 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
852 int load_offset = code_offset();
853 switch(type) {
854 case T_BOOLEAN: // fall through
855 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
856 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
857 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
858 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
859 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
860 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
861 case T_ARRAY : // fall through
862 case T_OBJECT:
863 {
864 if (UseCompressedOops && !wide) {
865 __ lwzx(to_reg->as_register(), base, disp);
866 __ decode_heap_oop(to_reg->as_register());
867 } else {
868 __ ldx(to_reg->as_register(), base, disp);
869 }
870 break;
871 }
872 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
873 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
874 case T_LONG :
875 #ifdef _LP64
876 __ ldx(to_reg->as_register_lo(), base, disp);
877 #else
878 Unimplemented();
879 #endif
880 break;
881 default : ShouldNotReachHere();
882 }
883 return load_offset;
884 }
885
886
887 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
888 LIR_Const* c = src->as_constant_ptr();
889 Register src_reg = R0;
890 switch (c->type()) {
891 case T_INT:
892 case T_FLOAT: {
893 int value = c->as_jint_bits();
894 __ load_const_optimized(src_reg, value);
895 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
896 __ stw(src_reg, addr);
897 break;
898 }
899 case T_ADDRESS: {
900 int value = c->as_jint_bits();
901 __ load_const_optimized(src_reg, value);
902 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
903 __ std(src_reg, addr);
904 break;
905 }
906 case T_OBJECT: {
907 jobject2reg(c->as_jobject(), src_reg);
908 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
909 __ std(src_reg, addr);
910 break;
911 }
912 case T_LONG:
913 case T_DOUBLE: {
914 int value = c->as_jlong_bits();
915 __ load_const_optimized(src_reg, value);
916 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
917 __ std(src_reg, addr);
918 break;
919 }
920 default:
921 Unimplemented();
922 }
923 }
924
925
926 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
927 LIR_Const* c = src->as_constant_ptr();
928 LIR_Address* addr = dest->as_address_ptr();
929 Register base = addr->base()->as_pointer_register();
930 LIR_Opr tmp = LIR_OprFact::illegalOpr;
931 int offset = -1;
932 // Null check for large offsets in LIRGenerator::do_StoreField.
933 bool needs_explicit_null_check = !ImplicitNullChecks;
934
935 if (info != nullptr && needs_explicit_null_check) {
936 explicit_null_check(base, info);
937 }
938
939 switch (c->type()) {
940 case T_FLOAT: type = T_INT;
941 case T_INT:
942 case T_ADDRESS: {
943 tmp = FrameMap::R0_opr;
944 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
945 break;
946 }
947 case T_DOUBLE: type = T_LONG;
948 case T_LONG: {
949 tmp = FrameMap::R0_long_opr;
950 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
951 break;
952 }
953 case T_OBJECT: {
954 tmp = FrameMap::R0_opr;
955 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
956 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
957 // Don't care about sign extend (will use stw).
958 __ lis(R0, 0); // Will get patched.
959 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
960 __ ori(R0, R0, 0); // Will get patched.
961 } else {
962 jobject2reg(c->as_jobject(), R0);
963 }
964 break;
965 }
966 default:
967 Unimplemented();
968 }
969
970 // Handle either reg+reg or reg+disp address.
971 if (addr->index()->is_valid()) {
972 assert(addr->disp() == 0, "must be zero");
973 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
974 } else {
975 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
976 offset = store(tmp, base, addr->disp(), type, wide);
977 }
978
979 if (info != nullptr) {
980 assert(offset != -1, "offset should've been set");
981 if (!needs_explicit_null_check) {
982 add_debug_info_for_null_check(offset, info);
983 }
984 }
985 }
986
987
988 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
989 LIR_Const* c = src->as_constant_ptr();
990 LIR_Opr to_reg = dest;
991
992 switch (c->type()) {
993 case T_INT: {
994 assert(patch_code == lir_patch_none, "no patching handled here");
995 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
996 break;
997 }
998 case T_ADDRESS: {
999 assert(patch_code == lir_patch_none, "no patching handled here");
1000 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
1001 break;
1002 }
1003 case T_LONG: {
1004 assert(patch_code == lir_patch_none, "no patching handled here");
1005 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
1006 break;
1007 }
1008
1009 case T_OBJECT: {
1010 if (patch_code == lir_patch_none) {
1011 jobject2reg(c->as_jobject(), to_reg->as_register());
1012 } else {
1013 jobject2reg_with_patching(to_reg->as_register(), info);
1014 }
1015 break;
1016 }
1017
1018 case T_METADATA:
1019 {
1020 if (patch_code == lir_patch_none) {
1021 metadata2reg(c->as_metadata(), to_reg->as_register());
1022 } else {
1023 klass2reg_with_patching(to_reg->as_register(), info);
1024 }
1025 }
1026 break;
1027
1028 case T_FLOAT:
1029 {
1030 if (to_reg->is_single_fpu()) {
1031 address const_addr = __ float_constant(c->as_jfloat());
1032 if (const_addr == nullptr) {
1033 bailout("const section overflow");
1034 break;
1035 }
1036 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1037 __ relocate(rspec);
1038 __ load_const(R0, const_addr);
1039 __ lfsx(to_reg->as_float_reg(), R0);
1040 } else {
1041 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1042 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1043 }
1044 }
1045 break;
1046
1047 case T_DOUBLE:
1048 {
1049 if (to_reg->is_double_fpu()) {
1050 address const_addr = __ double_constant(c->as_jdouble());
1051 if (const_addr == nullptr) {
1052 bailout("const section overflow");
1053 break;
1054 }
1055 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1056 __ relocate(rspec);
1057 __ load_const(R0, const_addr);
1058 __ lfdx(to_reg->as_double_reg(), R0);
1059 } else {
1060 assert(to_reg->is_double_cpu(), "Must be a long register.");
1061 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1062 }
1063 }
1064 break;
1065
1066 default:
1067 ShouldNotReachHere();
1068 }
1069 }
1070
1071
1072 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1073 Unimplemented(); return Address();
1074 }
1075
1076
1077 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1078 if (addr->index()->is_illegal()) {
1079 return (RegisterOrConstant)(addr->disp());
1080 } else {
1081 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1082 }
1083 }
1084
1085
1086 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1087 const Register tmp = R0;
1088 switch (type) {
1089 case T_INT:
1090 case T_FLOAT: {
1091 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1092 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1093 __ lwz(tmp, from);
1094 __ stw(tmp, to);
1095 break;
1096 }
1097 case T_ADDRESS:
1098 case T_OBJECT: {
1099 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1100 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1101 __ ld(tmp, from);
1102 __ std(tmp, to);
1103 break;
1104 }
1105 case T_LONG:
1106 case T_DOUBLE: {
1107 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1108 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1109 __ ld(tmp, from);
1110 __ std(tmp, to);
1111 break;
1112 }
1113
1114 default:
1115 ShouldNotReachHere();
1116 }
1117 }
1118
1119
1120 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1121 Unimplemented(); return Address();
1122 }
1123
1124
1125 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1126 Unimplemented(); return Address();
1127 }
1128
1129
1130 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1131 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1132
1133 assert(type != T_METADATA, "load of metadata ptr not supported");
1134 LIR_Address* addr = src_opr->as_address_ptr();
1135 LIR_Opr to_reg = dest;
1136
1137 Register src = addr->base()->as_pointer_register();
1138 Register disp_reg = noreg;
1139 int disp_value = addr->disp();
1140 bool needs_patching = (patch_code != lir_patch_none);
1141 // null check for large offsets in LIRGenerator::do_LoadField
1142 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1143
1144 if (info != nullptr && needs_explicit_null_check) {
1145 explicit_null_check(src, info);
1146 }
1147
1148 if (addr->base()->type() == T_OBJECT) {
1149 __ verify_oop(src, FILE_AND_LINE);
1150 }
1151
1152 PatchingStub* patch = nullptr;
1153 if (needs_patching) {
1154 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1155 assert(!to_reg->is_double_cpu() ||
1156 patch_code == lir_patch_none ||
1157 patch_code == lir_patch_normal, "patching doesn't match register");
1158 }
1159
1160 if (addr->index()->is_illegal()) {
1161 if (!Assembler::is_simm16(disp_value)) {
1162 if (needs_patching) {
1163 __ load_const32(R0, 0); // patchable int
1164 } else {
1165 __ load_const_optimized(R0, disp_value);
1166 }
1167 disp_reg = R0;
1168 }
1169 } else {
1170 disp_reg = addr->index()->as_pointer_register();
1171 assert(disp_value == 0, "can't handle 3 operand addresses");
1172 }
1173
1174 // Remember the offset of the load. The patching_epilog must be done
1175 // before the call to add_debug_info, otherwise the PcDescs don't get
1176 // entered in increasing order.
1177 int offset;
1178
1179 if (disp_reg == noreg) {
1180 assert(Assembler::is_simm16(disp_value), "should have set this up");
1181 offset = load(src, disp_value, to_reg, type, wide);
1182 } else {
1183 offset = load(src, disp_reg, to_reg, type, wide);
1184 }
1185
1186 if (patch != nullptr) {
1187 patching_epilog(patch, patch_code, src, info);
1188 }
1189 if (info != nullptr && !needs_explicit_null_check) {
1190 add_debug_info_for_null_check(offset, info);
1191 }
1192 }
1193
1194
1195 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1196 Address addr;
1197 if (src->is_single_word()) {
1198 addr = frame_map()->address_for_slot(src->single_stack_ix());
1199 } else if (src->is_double_word()) {
1200 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1201 }
1202
1203 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1204 }
1205
1206
1207 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1208 Address addr;
1209 if (dest->is_single_word()) {
1210 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1211 } else if (dest->is_double_word()) {
1212 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1213 }
1214
1215 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1216 }
1217
1218
1219 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1220 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1221 if (from_reg->is_double_fpu()) {
1222 // double to double moves
1223 assert(to_reg->is_double_fpu(), "should match");
1224 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1225 } else {
1226 // float to float moves
1227 assert(to_reg->is_single_fpu(), "should match");
1228 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1229 }
1230 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1231 if (from_reg->is_double_cpu()) {
1232 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1233 } else if (to_reg->is_double_cpu()) {
1234 // int to int moves
1235 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1236 } else {
1237 // int to int moves
1238 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1239 }
1240 } else {
1241 ShouldNotReachHere();
1242 }
1243 if (is_reference_type(to_reg->type())) {
1244 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1245 }
1246 }
1247
1248
1249 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1250 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1251 bool wide) {
1252 assert(type != T_METADATA, "store of metadata ptr not supported");
1253 LIR_Address* addr = dest->as_address_ptr();
1254
1255 Register src = addr->base()->as_pointer_register();
1256 Register disp_reg = noreg;
1257 int disp_value = addr->disp();
1258 bool needs_patching = (patch_code != lir_patch_none);
1259 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1260 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1261 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1262 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1263 // Null check for large offsets in LIRGenerator::do_StoreField.
1264 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1265
1266 if (info != nullptr && needs_explicit_null_check) {
1267 explicit_null_check(src, info);
1268 }
1269
1270 if (addr->base()->is_oop_register()) {
1271 __ verify_oop(src, FILE_AND_LINE);
1272 }
1273
1274 PatchingStub* patch = nullptr;
1275 if (needs_patching) {
1276 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1277 assert(!from_reg->is_double_cpu() ||
1278 patch_code == lir_patch_none ||
1279 patch_code == lir_patch_normal, "patching doesn't match register");
1280 }
1281
1282 if (addr->index()->is_illegal()) {
1283 if (load_disp) {
1284 disp_reg = use_R29 ? R29_TOC : R0;
1285 if (needs_patching) {
1286 __ load_const32(disp_reg, 0); // patchable int
1287 } else {
1288 __ load_const_optimized(disp_reg, disp_value);
1289 }
1290 }
1291 } else {
1292 disp_reg = addr->index()->as_pointer_register();
1293 assert(disp_value == 0, "can't handle 3 operand addresses");
1294 }
1295
1296 // remember the offset of the store. The patching_epilog must be done
1297 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1298 // entered in increasing order.
1299 int offset;
1300
1301 if (compress_oop) {
1302 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1303 from_reg = FrameMap::as_opr(co);
1304 }
1305
1306 if (disp_reg == noreg) {
1307 assert(Assembler::is_simm16(disp_value), "should have set this up");
1308 offset = store(from_reg, src, disp_value, type, wide);
1309 } else {
1310 offset = store(from_reg, src, disp_reg, type, wide);
1311 }
1312
1313 if (use_R29) {
1314 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1315 }
1316
1317 if (patch != nullptr) {
1318 patching_epilog(patch, patch_code, src, info);
1319 }
1320
1321 if (info != nullptr && !needs_explicit_null_check) {
1322 add_debug_info_for_null_check(offset, info);
1323 }
1324 }
1325
1326
1327 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1328 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1329 const Register temp = R12;
1330
1331 // Pop the stack before the safepoint code.
1332 int frame_size = initial_frame_size_in_bytes();
1333 if (Assembler::is_simm(frame_size, 16)) {
1334 __ addi(R1_SP, R1_SP, frame_size);
1335 } else {
1336 __ pop_frame();
1337 }
1338
1339 // Restore return pc relative to callers' sp.
1340 __ ld(return_pc, _abi0(lr), R1_SP);
1341 // Move return pc to LR.
1342 __ mtlr(return_pc);
1343
1344 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1345 __ reserved_stack_check(return_pc);
1346 }
1347
1348 // We need to mark the code position where the load from the safepoint
1349 // polling page was emitted as relocInfo::poll_return_type here.
1350 if (!UseSIGTRAP) {
1351 code_stub->set_safepoint_offset(__ offset());
1352 __ relocate(relocInfo::poll_return_type);
1353 }
1354 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1355
1356 // Return.
1357 __ blr();
1358 }
1359
1360
1361 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1362 const Register poll_addr = tmp->as_register();
1363 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1364 if (info != nullptr) {
1365 add_debug_info_for_branch(info);
1366 }
1367 int offset = __ offset();
1368 __ relocate(relocInfo::poll_type);
1369 __ load_from_polling_page(poll_addr);
1370
1371 return offset;
1372 }
1373
1374
1375 void LIR_Assembler::emit_static_call_stub() {
1376 address call_pc = __ pc();
1377 address stub = __ start_a_stub(static_call_stub_size());
1378 if (stub == nullptr) {
1379 bailout("static call stub overflow");
1380 return;
1381 }
1382
1383 // For java_to_interp stubs we use R11_scratch1 as scratch register
1384 // and in call trampoline stubs we use R12_scratch2. This way we
1385 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1386 const Register reg_scratch = R11_scratch1;
1387
1388 // Create a static stub relocation which relates this stub
1389 // with the call instruction at insts_call_instruction_offset in the
1390 // instructions code-section.
1391 int start = __ offset();
1392 __ relocate(static_stub_Relocation::spec(call_pc));
1393
1394 // Now, create the stub's code:
1395 // - load the TOC
1396 // - load the inline cache oop from the constant pool
1397 // - load the call target from the constant pool
1398 // - call
1399 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1400 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1401 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1402
1403 if (ReoptimizeCallSequences) {
1404 __ b64_patchable((address)-1, relocInfo::none);
1405 } else {
1406 AddressLiteral a((address)-1);
1407 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1408 __ mtctr(reg_scratch);
1409 __ bctr();
1410 }
1411 if (!success) {
1412 bailout("const section overflow");
1413 return;
1414 }
1415
1416 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1417 __ end_a_stub();
1418 }
1419
1420
1421 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1422 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1423 if (opr1->is_single_fpu()) {
1424 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1425 } else if (opr1->is_double_fpu()) {
1426 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1427 } else if (opr1->is_single_cpu()) {
1428 if (opr2->is_constant()) {
1429 switch (opr2->as_constant_ptr()->type()) {
1430 case T_INT:
1431 {
1432 jint con = opr2->as_constant_ptr()->as_jint();
1433 if (unsigned_comp) {
1434 if (Assembler::is_uimm(con, 16)) {
1435 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1436 } else {
1437 __ load_const_optimized(R0, con);
1438 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1439 }
1440 } else {
1441 if (Assembler::is_simm(con, 16)) {
1442 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1443 } else {
1444 __ load_const_optimized(R0, con);
1445 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1446 }
1447 }
1448 }
1449 break;
1450
1451 case T_OBJECT:
1452 // There are only equal/notequal comparisons on objects.
1453 {
1454 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1455 jobject con = opr2->as_constant_ptr()->as_jobject();
1456 if (con == nullptr) {
1457 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1458 } else {
1459 jobject2reg(con, R0);
1460 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1461 }
1462 }
1463 break;
1464
1465 case T_METADATA:
1466 // We only need, for now, comparison with null for metadata.
1467 {
1468 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1469 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1470 if (p == nullptr) {
1471 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1472 } else {
1473 ShouldNotReachHere();
1474 }
1475 }
1476 break;
1477
1478 default:
1479 ShouldNotReachHere();
1480 break;
1481 }
1482 } else {
1483 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1484 if (is_reference_type(opr1->type())) {
1485 // There are only equal/notequal comparisons on objects.
1486 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1487 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1488 } else {
1489 if (unsigned_comp) {
1490 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1491 } else {
1492 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1493 }
1494 }
1495 }
1496 } else if (opr1->is_double_cpu()) {
1497 if (opr2->is_constant()) {
1498 jlong con = opr2->as_constant_ptr()->as_jlong();
1499 if (unsigned_comp) {
1500 if (Assembler::is_uimm(con, 16)) {
1501 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1502 } else {
1503 __ load_const_optimized(R0, con);
1504 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1505 }
1506 } else {
1507 if (Assembler::is_simm(con, 16)) {
1508 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1509 } else {
1510 __ load_const_optimized(R0, con);
1511 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1512 }
1513 }
1514 } else if (opr2->is_register()) {
1515 if (unsigned_comp) {
1516 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1517 } else {
1518 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1519 }
1520 } else {
1521 ShouldNotReachHere();
1522 }
1523 } else {
1524 ShouldNotReachHere();
1525 }
1526 }
1527
1528
1529 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1530 const Register Rdst = dst->as_register();
1531 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1532 bool is_unordered_less = (code == lir_ucmp_fd2i);
1533 if (left->is_single_fpu()) {
1534 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1535 } else if (left->is_double_fpu()) {
1536 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1537 } else {
1538 ShouldNotReachHere();
1539 }
1540 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1541 } else if (code == lir_cmp_l2i) {
1542 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1543 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1544 } else {
1545 ShouldNotReachHere();
1546 }
1547 }
1548
1549
1550 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1551 if (src->is_constant()) {
1552 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1553 } else if (src->is_register()) {
1554 lasm->reg2reg(src, dst);
1555 } else if (src->is_stack()) {
1556 lasm->stack2reg(src, dst, dst->type());
1557 } else {
1558 ShouldNotReachHere();
1559 }
1560 }
1561
1562 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1563 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1564 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1565
1566 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1567 load_to_reg(this, opr1, result); // Condition doesn't matter.
1568 return;
1569 }
1570
1571 bool positive = false;
1572 Assembler::Condition cond = Assembler::equal;
1573 switch (condition) {
1574 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1575 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1576 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1577 case lir_cond_belowEqual:
1578 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1579 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1580 case lir_cond_aboveEqual:
1581 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1582 default: ShouldNotReachHere();
1583 }
1584
1585 // Try to use isel on >=Power7.
1586 if (VM_Version::has_isel() && result->is_cpu_register()) {
1587 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1588 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1589
1590 // We can use result_reg to load one operand if not already in register.
1591 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1592 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1593
1594 if (first != second) {
1595 if (!o1_is_reg) {
1596 load_to_reg(this, opr1, result);
1597 }
1598
1599 if (!o2_is_reg) {
1600 load_to_reg(this, opr2, result);
1601 }
1602
1603 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1604 return;
1605 }
1606 } // isel
1607
1608 load_to_reg(this, opr1, result);
1609
1610 Label skip;
1611 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1612 int bi = Assembler::bi0(BOOL_RESULT, cond);
1613 __ bc(bo, bi, skip);
1614
1615 load_to_reg(this, opr2, result);
1616 __ bind(skip);
1617 }
1618
1619
1620 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1621 CodeEmitInfo* info, bool pop_fpu_stack) {
1622 assert(info == nullptr, "unused on this code path");
1623 assert(left->is_register(), "wrong items state");
1624 assert(dest->is_register(), "wrong items state");
1625
1626 if (right->is_register()) {
1627 if (dest->is_float_kind()) {
1628
1629 FloatRegister lreg, rreg, res;
1630 if (right->is_single_fpu()) {
1631 lreg = left->as_float_reg();
1632 rreg = right->as_float_reg();
1633 res = dest->as_float_reg();
1634 switch (code) {
1635 case lir_add: __ fadds(res, lreg, rreg); break;
1636 case lir_sub: __ fsubs(res, lreg, rreg); break;
1637 case lir_mul: __ fmuls(res, lreg, rreg); break;
1638 case lir_div: __ fdivs(res, lreg, rreg); break;
1639 default: ShouldNotReachHere();
1640 }
1641 } else {
1642 lreg = left->as_double_reg();
1643 rreg = right->as_double_reg();
1644 res = dest->as_double_reg();
1645 switch (code) {
1646 case lir_add: __ fadd(res, lreg, rreg); break;
1647 case lir_sub: __ fsub(res, lreg, rreg); break;
1648 case lir_mul: __ fmul(res, lreg, rreg); break;
1649 case lir_div: __ fdiv(res, lreg, rreg); break;
1650 default: ShouldNotReachHere();
1651 }
1652 }
1653
1654 } else if (dest->is_double_cpu()) {
1655
1656 Register dst_lo = dest->as_register_lo();
1657 Register op1_lo = left->as_pointer_register();
1658 Register op2_lo = right->as_pointer_register();
1659
1660 switch (code) {
1661 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1662 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1663 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1664 default: ShouldNotReachHere();
1665 }
1666 } else {
1667 assert (right->is_single_cpu(), "Just Checking");
1668
1669 Register lreg = left->as_register();
1670 Register res = dest->as_register();
1671 Register rreg = right->as_register();
1672 switch (code) {
1673 case lir_add: __ add (res, lreg, rreg); break;
1674 case lir_sub: __ sub (res, lreg, rreg); break;
1675 case lir_mul: __ mullw(res, lreg, rreg); break;
1676 default: ShouldNotReachHere();
1677 }
1678 }
1679 } else {
1680 assert (right->is_constant(), "must be constant");
1681
1682 if (dest->is_single_cpu()) {
1683 Register lreg = left->as_register();
1684 Register res = dest->as_register();
1685 int simm16 = right->as_constant_ptr()->as_jint();
1686
1687 switch (code) {
1688 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1689 simm16 = -simm16;
1690 case lir_add: if (res == lreg && simm16 == 0) break;
1691 __ addi(res, lreg, simm16); break;
1692 case lir_mul: if (res == lreg && simm16 == 1) break;
1693 __ mulli(res, lreg, simm16); break;
1694 default: ShouldNotReachHere();
1695 }
1696 } else {
1697 Register lreg = left->as_pointer_register();
1698 Register res = dest->as_register_lo();
1699 long con = right->as_constant_ptr()->as_jlong();
1700 assert(Assembler::is_simm16(con), "must be simm16");
1701
1702 switch (code) {
1703 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1704 con = -con;
1705 case lir_add: if (res == lreg && con == 0) break;
1706 __ addi(res, lreg, (int)con); break;
1707 case lir_mul: if (res == lreg && con == 1) break;
1708 __ mulli(res, lreg, (int)con); break;
1709 default: ShouldNotReachHere();
1710 }
1711 }
1712 }
1713 }
1714
1715
1716 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1717 switch (code) {
1718 case lir_sqrt: {
1719 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1720 break;
1721 }
1722 case lir_abs: {
1723 __ fabs(dest->as_double_reg(), value->as_double_reg());
1724 break;
1725 }
1726 default: {
1727 ShouldNotReachHere();
1728 break;
1729 }
1730 }
1731 }
1732
1733
1734 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1735 if (right->is_constant()) { // see do_LogicOp
1736 long uimm;
1737 Register d, l;
1738 if (dest->is_single_cpu()) {
1739 uimm = right->as_constant_ptr()->as_jint();
1740 d = dest->as_register();
1741 l = left->as_register();
1742 } else {
1743 uimm = right->as_constant_ptr()->as_jlong();
1744 d = dest->as_register_lo();
1745 l = left->as_register_lo();
1746 }
1747 long uimms = (unsigned long)uimm >> 16,
1748 uimmss = (unsigned long)uimm >> 32;
1749
1750 switch (code) {
1751 case lir_logic_and:
1752 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1753 __ andi(d, l, uimm); // special cases
1754 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1755 else { __ andi_(d, l, uimm); }
1756 break;
1757
1758 case lir_logic_or:
1759 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1760 else { __ ori(d, l, uimm); }
1761 break;
1762
1763 case lir_logic_xor:
1764 if (uimm == -1) { __ nand(d, l, l); } // special case
1765 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1766 else { __ xori(d, l, uimm); }
1767 break;
1768
1769 default: ShouldNotReachHere();
1770 }
1771 } else {
1772 assert(right->is_register(), "right should be in register");
1773
1774 if (dest->is_single_cpu()) {
1775 switch (code) {
1776 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1777 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1778 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1779 default: ShouldNotReachHere();
1780 }
1781 } else {
1782 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1783 left->as_register_lo();
1784 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1785 right->as_register_lo();
1786
1787 switch (code) {
1788 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1789 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1790 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1791 default: ShouldNotReachHere();
1792 }
1793 }
1794 }
1795 }
1796
1797
1798 int LIR_Assembler::shift_amount(BasicType t) {
1799 int elem_size = type2aelembytes(t);
1800 switch (elem_size) {
1801 case 1 : return 0;
1802 case 2 : return 1;
1803 case 4 : return 2;
1804 case 8 : return 3;
1805 }
1806 ShouldNotReachHere();
1807 return -1;
1808 }
1809
1810
1811 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1812 info->add_register_oop(exceptionOop);
1813
1814 // Reuse the debug info from the safepoint poll for the throw op itself.
1815 address pc_for_athrow = __ pc();
1816 int pc_for_athrow_offset = __ offset();
1817 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1818 //__ relocate(rspec);
1819 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1820 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1821 add_call_info(pc_for_athrow_offset, info); // for exception handler
1822
1823 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? C1StubId::handle_exception_id
1824 : C1StubId::handle_exception_nofpu_id);
1825 //__ load_const_optimized(R0, stub);
1826 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1827 __ mtctr(R0);
1828 __ bctr();
1829 }
1830
1831
1832 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1833 // Note: Not used with EnableDebuggingOnDemand.
1834 assert(exceptionOop->as_register() == R3, "should match");
1835 __ b(_unwind_handler_entry);
1836 }
1837
1838
1839 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1840 Register src = op->src()->as_register();
1841 Register dst = op->dst()->as_register();
1842 Register src_pos = op->src_pos()->as_register();
1843 Register dst_pos = op->dst_pos()->as_register();
1844 Register length = op->length()->as_register();
1845 Register tmp = op->tmp()->as_register();
1846 Register tmp2 = R0;
1847
1848 int flags = op->flags();
1849 ciArrayKlass* default_type = op->expected_type();
1850 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1851 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1852
1853 // Set up the arraycopy stub information.
1854 ArrayCopyStub* stub = op->stub();
1855
1856 // Always do stub if no type information is available. It's ok if
1857 // the known type isn't loaded since the code sanity checks
1858 // in debug mode and the type isn't required when we know the exact type
1859 // also check that the type is an array type.
1860 if (default_type == nullptr) {
1861 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1862 length->is_nonvolatile(), "must preserve");
1863 address copyfunc_addr = StubRoutines::generic_arraycopy();
1864 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1865
1866 // 3 parms are int. Convert to long.
1867 __ mr(R3_ARG1, src);
1868 __ extsw(R4_ARG2, src_pos);
1869 __ mr(R5_ARG3, dst);
1870 __ extsw(R6_ARG4, dst_pos);
1871 __ extsw(R7_ARG5, length);
1872
1873 #ifndef PRODUCT
1874 if (PrintC1Statistics) {
1875 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1876 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1877 __ lwz(R11_scratch1, simm16_offs, tmp);
1878 __ addi(R11_scratch1, R11_scratch1, 1);
1879 __ stw(R11_scratch1, simm16_offs, tmp);
1880 }
1881 #endif
1882 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1883
1884 __ nand(tmp, R3_RET, R3_RET);
1885 __ subf(length, tmp, length);
1886 __ add(src_pos, tmp, src_pos);
1887 __ add(dst_pos, tmp, dst_pos);
1888
1889 __ cmpwi(CCR0, R3_RET, 0);
1890 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1891 __ bind(*stub->continuation());
1892 return;
1893 }
1894
1895 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1896 Label cont, slow, copyfunc;
1897
1898 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1899 LIR_OpArrayCopy::dst_null_check |
1900 LIR_OpArrayCopy::src_pos_positive_check |
1901 LIR_OpArrayCopy::dst_pos_positive_check |
1902 LIR_OpArrayCopy::length_positive_check);
1903
1904 // Use only one conditional branch for simple checks.
1905 if (simple_check_flag_set) {
1906 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1907
1908 // Make sure src and dst are non-null.
1909 if (flags & LIR_OpArrayCopy::src_null_check) {
1910 __ cmpdi(combined_check, src, 0);
1911 tmp_check = CCR0;
1912 }
1913
1914 if (flags & LIR_OpArrayCopy::dst_null_check) {
1915 __ cmpdi(tmp_check, dst, 0);
1916 if (tmp_check != combined_check) {
1917 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1918 }
1919 tmp_check = CCR0;
1920 }
1921
1922 // Clear combined_check.eq if not already used.
1923 if (tmp_check == combined_check) {
1924 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1925 tmp_check = CCR0;
1926 }
1927
1928 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1929 // Test src_pos register.
1930 __ cmpwi(tmp_check, src_pos, 0);
1931 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1932 }
1933
1934 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1935 // Test dst_pos register.
1936 __ cmpwi(tmp_check, dst_pos, 0);
1937 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1938 }
1939
1940 if (flags & LIR_OpArrayCopy::length_positive_check) {
1941 // Make sure length isn't negative.
1942 __ cmpwi(tmp_check, length, 0);
1943 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1944 }
1945
1946 __ beq(combined_check, slow);
1947 }
1948
1949 // If the compiler was not able to prove that exact type of the source or the destination
1950 // of the arraycopy is an array type, check at runtime if the source or the destination is
1951 // an instance type.
1952 if (flags & LIR_OpArrayCopy::type_check) {
1953 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1954 __ load_klass(tmp, dst);
1955 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1956 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1957 __ bge(CCR0, slow);
1958 }
1959
1960 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1961 __ load_klass(tmp, src);
1962 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1963 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1964 __ bge(CCR0, slow);
1965 }
1966 }
1967
1968 // Higher 32bits must be null.
1969 __ extsw(length, length);
1970
1971 __ extsw(src_pos, src_pos);
1972 if (flags & LIR_OpArrayCopy::src_range_check) {
1973 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1974 __ add(tmp, length, src_pos);
1975 __ cmpld(CCR0, tmp2, tmp);
1976 __ ble(CCR0, slow);
1977 }
1978
1979 __ extsw(dst_pos, dst_pos);
1980 if (flags & LIR_OpArrayCopy::dst_range_check) {
1981 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1982 __ add(tmp, length, dst_pos);
1983 __ cmpld(CCR0, tmp2, tmp);
1984 __ ble(CCR0, slow);
1985 }
1986
1987 int shift = shift_amount(basic_type);
1988
1989 if (!(flags & LIR_OpArrayCopy::type_check)) {
1990 if (stub != nullptr) {
1991 __ b(cont);
1992 __ bind(slow);
1993 __ b(*stub->entry());
1994 }
1995 } else {
1996 // We don't know the array types are compatible.
1997 if (basic_type != T_OBJECT) {
1998 // Simple test for basic type arrays.
1999 if (UseCompressedClassPointers) {
2000 // We don't need decode because we just need to compare.
2001 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
2002 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2003 __ cmpw(CCR0, tmp, tmp2);
2004 } else {
2005 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
2006 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2007 __ cmpd(CCR0, tmp, tmp2);
2008 }
2009 __ beq(CCR0, cont);
2010 } else {
2011 // For object arrays, if src is a sub class of dst then we can
2012 // safely do the copy.
2013 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2014
2015 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2016 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2017
2018 __ load_klass(sub_klass, src);
2019 __ load_klass(super_klass, dst);
2020
2021 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2022 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
2023
2024 address slow_stc = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2025 //__ load_const_optimized(tmp, slow_stc, tmp2);
2026 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2027 __ mtctr(tmp);
2028 __ bctrl(); // sets CR0
2029 __ beq(CCR0, cont);
2030
2031 if (copyfunc_addr != nullptr) { // Use stub if available.
2032 __ bind(copyfunc);
2033 // Src is not a sub class of dst so we have to do a
2034 // per-element check.
2035 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2036 if ((flags & mask) != mask) {
2037 assert(flags & mask, "one of the two should be known to be an object array");
2038
2039 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2040 __ load_klass(tmp, src);
2041 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2042 __ load_klass(tmp, dst);
2043 }
2044
2045 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2046
2047 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2048 __ load_const_optimized(tmp, objArray_lh);
2049 __ cmpw(CCR0, tmp, tmp2);
2050 __ bne(CCR0, slow);
2051 }
2052
2053 Register src_ptr = R3_ARG1;
2054 Register dst_ptr = R4_ARG2;
2055 Register len = R5_ARG3;
2056 Register chk_off = R6_ARG4;
2057 Register super_k = R7_ARG5;
2058
2059 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2060 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2061 if (shift == 0) {
2062 __ add(src_ptr, src_pos, src_ptr);
2063 __ add(dst_ptr, dst_pos, dst_ptr);
2064 } else {
2065 __ sldi(tmp, src_pos, shift);
2066 __ sldi(tmp2, dst_pos, shift);
2067 __ add(src_ptr, tmp, src_ptr);
2068 __ add(dst_ptr, tmp2, dst_ptr);
2069 }
2070
2071 __ load_klass(tmp, dst);
2072 __ mr(len, length);
2073
2074 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2075 __ ld(super_k, ek_offset, tmp);
2076
2077 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2078 __ lwz(chk_off, sco_offset, super_k);
2079
2080 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2081
2082 #ifndef PRODUCT
2083 if (PrintC1Statistics) {
2084 Label failed;
2085 __ cmpwi(CCR0, R3_RET, 0);
2086 __ bne(CCR0, failed);
2087 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2088 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2089 __ lwz(R11_scratch1, simm16_offs, tmp);
2090 __ addi(R11_scratch1, R11_scratch1, 1);
2091 __ stw(R11_scratch1, simm16_offs, tmp);
2092 __ bind(failed);
2093 }
2094 #endif
2095
2096 __ nand(tmp, R3_RET, R3_RET);
2097 __ cmpwi(CCR0, R3_RET, 0);
2098 __ beq(CCR0, *stub->continuation());
2099
2100 #ifndef PRODUCT
2101 if (PrintC1Statistics) {
2102 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2103 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2104 __ lwz(R11_scratch1, simm16_offs, tmp);
2105 __ addi(R11_scratch1, R11_scratch1, 1);
2106 __ stw(R11_scratch1, simm16_offs, tmp);
2107 }
2108 #endif
2109
2110 __ subf(length, tmp, length);
2111 __ add(src_pos, tmp, src_pos);
2112 __ add(dst_pos, tmp, dst_pos);
2113 }
2114 }
2115 __ bind(slow);
2116 __ b(*stub->entry());
2117 }
2118 __ bind(cont);
2119
2120 #ifdef ASSERT
2121 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2122 // Sanity check the known type with the incoming class. For the
2123 // primitive case the types must match exactly with src.klass and
2124 // dst.klass each exactly matching the default type. For the
2125 // object array case, if no type check is needed then either the
2126 // dst type is exactly the expected type and the src type is a
2127 // subtype which we can't check or src is the same array as dst
2128 // but not necessarily exactly of type default_type.
2129 Label known_ok, halt;
2130 metadata2reg(default_type->constant_encoding(), tmp);
2131 if (UseCompressedClassPointers) {
2132 // Tmp holds the default type. It currently comes uncompressed after the
2133 // load of a constant, so encode it.
2134 __ encode_klass_not_null(tmp);
2135 // Load the raw value of the dst klass, since we will be comparing
2136 // uncompressed values directly.
2137 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2138 __ cmpw(CCR0, tmp, tmp2);
2139 if (basic_type != T_OBJECT) {
2140 __ bne(CCR0, halt);
2141 // Load the raw value of the src klass.
2142 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2143 __ cmpw(CCR0, tmp, tmp2);
2144 __ beq(CCR0, known_ok);
2145 } else {
2146 __ beq(CCR0, known_ok);
2147 __ cmpw(CCR0, src, dst);
2148 __ beq(CCR0, known_ok);
2149 }
2150 } else {
2151 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2152 __ cmpd(CCR0, tmp, tmp2);
2153 if (basic_type != T_OBJECT) {
2154 __ bne(CCR0, halt);
2155 // Load the raw value of the src klass.
2156 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2157 __ cmpd(CCR0, tmp, tmp2);
2158 __ beq(CCR0, known_ok);
2159 } else {
2160 __ beq(CCR0, known_ok);
2161 __ cmpd(CCR0, src, dst);
2162 __ beq(CCR0, known_ok);
2163 }
2164 }
2165 __ bind(halt);
2166 __ stop("incorrect type information in arraycopy");
2167 __ bind(known_ok);
2168 }
2169 #endif
2170
2171 #ifndef PRODUCT
2172 if (PrintC1Statistics) {
2173 address counter = Runtime1::arraycopy_count_address(basic_type);
2174 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2175 __ lwz(R11_scratch1, simm16_offs, tmp);
2176 __ addi(R11_scratch1, R11_scratch1, 1);
2177 __ stw(R11_scratch1, simm16_offs, tmp);
2178 }
2179 #endif
2180
2181 Register src_ptr = R3_ARG1;
2182 Register dst_ptr = R4_ARG2;
2183 Register len = R5_ARG3;
2184
2185 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2186 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2187 if (shift == 0) {
2188 __ add(src_ptr, src_pos, src_ptr);
2189 __ add(dst_ptr, dst_pos, dst_ptr);
2190 } else {
2191 __ sldi(tmp, src_pos, shift);
2192 __ sldi(tmp2, dst_pos, shift);
2193 __ add(src_ptr, tmp, src_ptr);
2194 __ add(dst_ptr, tmp2, dst_ptr);
2195 }
2196
2197 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2198 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2199 const char *name;
2200 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2201
2202 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2203 __ mr(len, length);
2204 __ call_c(entry, relocInfo::runtime_call_type);
2205
2206 if (stub != nullptr) {
2207 __ bind(*stub->continuation());
2208 }
2209 }
2210
2211
2212 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2213 if (dest->is_single_cpu()) {
2214 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2215 #ifdef _LP64
2216 if (left->type() == T_OBJECT) {
2217 switch (code) {
2218 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2219 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2220 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2221 default: ShouldNotReachHere();
2222 }
2223 } else
2224 #endif
2225 switch (code) {
2226 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2227 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2228 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2229 default: ShouldNotReachHere();
2230 }
2231 } else {
2232 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2233 switch (code) {
2234 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2235 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2236 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2237 default: ShouldNotReachHere();
2238 }
2239 }
2240 }
2241
2242
2243 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2244 #ifdef _LP64
2245 if (left->type() == T_OBJECT) {
2246 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2247 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2248 else {
2249 switch (code) {
2250 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2251 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2252 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2253 default: ShouldNotReachHere();
2254 }
2255 }
2256 return;
2257 }
2258 #endif
2259
2260 if (dest->is_single_cpu()) {
2261 count = count & 0x1F; // Java spec
2262 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2263 else {
2264 switch (code) {
2265 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2266 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2267 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2268 default: ShouldNotReachHere();
2269 }
2270 }
2271 } else if (dest->is_double_cpu()) {
2272 count = count & 63; // Java spec
2273 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2274 else {
2275 switch (code) {
2276 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2277 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2278 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2279 default: ShouldNotReachHere();
2280 }
2281 }
2282 } else {
2283 ShouldNotReachHere();
2284 }
2285 }
2286
2287
2288 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2289 if (op->init_check()) {
2290 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2291 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2292 } else {
2293 add_debug_info_for_null_check_here(op->stub()->info());
2294 }
2295 __ lbz(op->tmp1()->as_register(),
2296 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2297 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2298 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2299 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2300 }
2301 __ allocate_object(op->obj()->as_register(),
2302 op->tmp1()->as_register(),
2303 op->tmp2()->as_register(),
2304 op->tmp3()->as_register(),
2305 op->header_size(),
2306 op->object_size(),
2307 op->klass()->as_register(),
2308 *op->stub()->entry());
2309
2310 __ bind(*op->stub()->continuation());
2311 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2312 }
2313
2314
2315 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2316 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2317 if (UseSlowPath ||
2318 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2319 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2320 __ b(*op->stub()->entry());
2321 } else {
2322 __ allocate_array(op->obj()->as_register(),
2323 op->len()->as_register(),
2324 op->tmp1()->as_register(),
2325 op->tmp2()->as_register(),
2326 op->tmp3()->as_register(),
2327 arrayOopDesc::base_offset_in_bytes(op->type()),
2328 type2aelembytes(op->type()),
2329 op->klass()->as_register(),
2330 *op->stub()->entry(),
2331 op->zero_array());
2332 }
2333 __ bind(*op->stub()->continuation());
2334 }
2335
2336
2337 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2338 ciMethodData *md, ciProfileData *data,
2339 Register recv, Register tmp1, Label* update_done) {
2340 uint i;
2341 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2342 Label next_test;
2343 // See if the receiver is receiver[n].
2344 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2345 __ verify_klass_ptr(tmp1);
2346 __ cmpd(CCR0, recv, tmp1);
2347 __ bne(CCR0, next_test);
2348
2349 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2350 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2351 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2352 __ b(*update_done);
2353
2354 __ bind(next_test);
2355 }
2356
2357 // Didn't find receiver; find next empty slot and fill it in.
2358 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2359 Label next_test;
2360 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2361 __ cmpdi(CCR0, tmp1, 0);
2362 __ bne(CCR0, next_test);
2363 __ li(tmp1, DataLayout::counter_increment);
2364 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2365 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2366 __ b(*update_done);
2367
2368 __ bind(next_test);
2369 }
2370 }
2371
2372
2373 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2374 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2375 md = method->method_data_or_null();
2376 assert(md != nullptr, "Sanity");
2377 data = md->bci_to_data(bci);
2378 assert(data != nullptr, "need data for checkcast");
2379 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2380 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2381 // The offset is large so bias the mdo by the base of the slot so
2382 // that the ld can use simm16s to reference the slots of the data.
2383 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2384 }
2385 }
2386
2387
2388 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2389 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2390 Register k_RInfo = op->tmp1()->as_register();
2391 Register klass_RInfo = op->tmp2()->as_register();
2392 Register Rtmp1 = op->tmp3()->as_register();
2393 Register dst = op->result_opr()->as_register();
2394 ciKlass* k = op->klass();
2395 bool should_profile = op->should_profile();
2396 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2397 bool reg_conflict = false;
2398 if (obj == k_RInfo) {
2399 k_RInfo = dst;
2400 reg_conflict = true;
2401 } else if (obj == klass_RInfo) {
2402 klass_RInfo = dst;
2403 reg_conflict = true;
2404 } else if (obj == Rtmp1) {
2405 Rtmp1 = dst;
2406 reg_conflict = true;
2407 }
2408 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2409
2410 ciMethodData* md = nullptr;
2411 ciProfileData* data = nullptr;
2412 int mdo_offset_bias = 0;
2413 if (should_profile) {
2414 ciMethod* method = op->profiled_method();
2415 assert(method != nullptr, "Should have method");
2416 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2417
2418 Register mdo = k_RInfo;
2419 Register data_val = Rtmp1;
2420 Label not_null;
2421 metadata2reg(md->constant_encoding(), mdo);
2422 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2423 __ cmpdi(CCR0, obj, 0);
2424 __ bne(CCR0, not_null);
2425 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2426 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2427 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2428 __ b(*obj_is_null);
2429 __ bind(not_null);
2430
2431 Label update_done;
2432 Register recv = klass_RInfo;
2433 __ load_klass(recv, obj);
2434 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2435 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2436 __ ld(Rtmp1, slot_offset, mdo);
2437 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2438 __ std(Rtmp1, slot_offset, mdo);
2439 __ bind(update_done);
2440 } else {
2441 __ cmpdi(CCR0, obj, 0);
2442 __ beq(CCR0, *obj_is_null);
2443 }
2444
2445 // get object class
2446 __ load_klass(klass_RInfo, obj);
2447
2448 if (k->is_loaded()) {
2449 metadata2reg(k->constant_encoding(), k_RInfo);
2450 } else {
2451 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2452 }
2453
2454 if (op->fast_check()) {
2455 assert_different_registers(klass_RInfo, k_RInfo);
2456 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2457 __ beq(CCR0, *success);
2458 // Fall through to failure case.
2459 } else {
2460 bool need_slow_path = true;
2461 if (k->is_loaded()) {
2462 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2463 need_slow_path = false;
2464 }
2465 // Perform the fast part of the checking logic.
2466 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2467 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2468 } else {
2469 // Perform the fast part of the checking logic.
2470 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2471 }
2472 if (!need_slow_path) {
2473 __ b(*success);
2474 } else {
2475 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2476 address entry = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2477 // Stub needs fixed registers (tmp1-3).
2478 Register original_k_RInfo = op->tmp1()->as_register();
2479 Register original_klass_RInfo = op->tmp2()->as_register();
2480 Register original_Rtmp1 = op->tmp3()->as_register();
2481 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2482 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2483 __ mr_if_needed(original_k_RInfo, k_RInfo);
2484 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2485 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2486 //__ load_const_optimized(original_Rtmp1, entry, R0);
2487 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2488 __ mtctr(original_Rtmp1);
2489 __ bctrl(); // sets CR0
2490 if (keep_obj_alive) { __ mr(obj, dst); }
2491 __ beq(CCR0, *success);
2492 // Fall through to failure case.
2493 }
2494 }
2495
2496 __ bind(*failure);
2497 }
2498
2499
2500 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2501 LIR_Code code = op->code();
2502 if (code == lir_store_check) {
2503 Register value = op->object()->as_register();
2504 Register array = op->array()->as_register();
2505 Register k_RInfo = op->tmp1()->as_register();
2506 Register klass_RInfo = op->tmp2()->as_register();
2507 Register Rtmp1 = op->tmp3()->as_register();
2508 bool should_profile = op->should_profile();
2509
2510 __ verify_oop(value, FILE_AND_LINE);
2511 CodeStub* stub = op->stub();
2512 // Check if it needs to be profiled.
2513 ciMethodData* md = nullptr;
2514 ciProfileData* data = nullptr;
2515 int mdo_offset_bias = 0;
2516 if (should_profile) {
2517 ciMethod* method = op->profiled_method();
2518 assert(method != nullptr, "Should have method");
2519 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2520 }
2521
2522 Label done;
2523
2524 if (should_profile) {
2525 Label not_null;
2526 Register mdo = k_RInfo;
2527 Register data_val = Rtmp1;
2528 metadata2reg(md->constant_encoding(), mdo);
2529 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2530 __ cmpdi(CCR0, value, 0);
2531 __ bne(CCR0, not_null);
2532 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2533 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2534 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2535 __ b(done);
2536 __ bind(not_null);
2537
2538 Label update_done;
2539 Register recv = klass_RInfo;
2540 __ load_klass(recv, value);
2541 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2542 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2543 __ ld(Rtmp1, slot_offset, mdo);
2544 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2545 __ std(Rtmp1, slot_offset, mdo);
2546 __ bind(update_done);
2547 } else {
2548 __ cmpdi(CCR0, value, 0);
2549 __ beq(CCR0, done);
2550 }
2551 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2552 explicit_null_check(array, op->info_for_exception());
2553 } else {
2554 add_debug_info_for_null_check_here(op->info_for_exception());
2555 }
2556 __ load_klass(k_RInfo, array);
2557 __ load_klass(klass_RInfo, value);
2558
2559 Label failure;
2560
2561 // Get instance klass.
2562 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2563 // Perform the fast part of the checking logic.
2564 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2565
2566 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2567 const address slow_path = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2568 //__ load_const_optimized(R0, slow_path);
2569 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2570 __ mtctr(R0);
2571 __ bctrl(); // sets CR0
2572 __ beq(CCR0, done);
2573
2574 __ bind(failure);
2575 __ b(*stub->entry());
2576 __ align(32, 12);
2577 __ bind(done);
2578
2579 } else if (code == lir_checkcast) {
2580 Label success, failure;
2581 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2582 __ b(*op->stub()->entry());
2583 __ align(32, 12);
2584 __ bind(success);
2585 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2586 } else if (code == lir_instanceof) {
2587 Register dst = op->result_opr()->as_register();
2588 Label success, failure, done;
2589 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2590 __ li(dst, 0);
2591 __ b(done);
2592 __ align(32, 12);
2593 __ bind(success);
2594 __ li(dst, 1);
2595 __ bind(done);
2596 } else {
2597 ShouldNotReachHere();
2598 }
2599 }
2600
2601
2602 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2603 Register addr = op->addr()->as_pointer_register();
2604 Register cmp_value = noreg, new_value = noreg;
2605 bool is_64bit = false;
2606
2607 if (op->code() == lir_cas_long) {
2608 cmp_value = op->cmp_value()->as_register_lo();
2609 new_value = op->new_value()->as_register_lo();
2610 is_64bit = true;
2611 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2612 cmp_value = op->cmp_value()->as_register();
2613 new_value = op->new_value()->as_register();
2614 if (op->code() == lir_cas_obj) {
2615 if (UseCompressedOops) {
2616 Register t1 = op->tmp1()->as_register();
2617 Register t2 = op->tmp2()->as_register();
2618 cmp_value = __ encode_heap_oop(t1, cmp_value);
2619 new_value = __ encode_heap_oop(t2, new_value);
2620 } else {
2621 is_64bit = true;
2622 }
2623 }
2624 } else {
2625 Unimplemented();
2626 }
2627
2628 // There might be a volatile load before this Unsafe CAS.
2629 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2630 __ sync();
2631 } else {
2632 __ lwsync();
2633 }
2634
2635 if (is_64bit) {
2636 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2637 MacroAssembler::MemBarNone,
2638 MacroAssembler::cmpxchgx_hint_atomic_update(),
2639 noreg, nullptr, /*check without ldarx first*/true);
2640 } else {
2641 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2642 MacroAssembler::MemBarNone,
2643 MacroAssembler::cmpxchgx_hint_atomic_update(),
2644 noreg, nullptr, /*check without ldarx first*/true);
2645 }
2646
2647 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2648 __ isync();
2649 } else {
2650 __ sync();
2651 }
2652 }
2653
2654 void LIR_Assembler::breakpoint() {
2655 __ illtrap();
2656 }
2657
2658
2659 void LIR_Assembler::push(LIR_Opr opr) {
2660 Unimplemented();
2661 }
2662
2663 void LIR_Assembler::pop(LIR_Opr opr) {
2664 Unimplemented();
2665 }
2666
2667
2668 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2669 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2670 Register dst = dst_opr->as_register();
2671 Register reg = mon_addr.base();
2672 int offset = mon_addr.disp();
2673 // Compute pointer to BasicLock.
2674 __ add_const_optimized(dst, reg, offset);
2675 }
2676
2677
2678 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2679 Register obj = op->obj_opr()->as_register();
2680 Register hdr = op->hdr_opr()->as_register();
2681 Register lock = op->lock_opr()->as_register();
2682
2683 // Obj may not be an oop.
2684 if (op->code() == lir_lock) {
2685 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2686 if (LockingMode != LM_MONITOR) {
2687 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2688 // Add debug info for NullPointerException only if one is possible.
2689 if (op->info() != nullptr) {
2690 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2691 explicit_null_check(obj, op->info());
2692 } else {
2693 add_debug_info_for_null_check_here(op->info());
2694 }
2695 }
2696 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2697 } else {
2698 // always do slow locking
2699 // note: The slow locking code could be inlined here, however if we use
2700 // slow locking, speed doesn't matter anyway and this solution is
2701 // simpler and requires less duplicated code - additionally, the
2702 // slow locking code is the same in either case which simplifies
2703 // debugging.
2704 if (op->info() != nullptr) {
2705 add_debug_info_for_null_check_here(op->info());
2706 __ null_check(obj);
2707 }
2708 __ b(*op->stub()->entry());
2709 }
2710 } else {
2711 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2712 if (LockingMode != LM_MONITOR) {
2713 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2714 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2715 } else {
2716 // always do slow unlocking
2717 // note: The slow unlocking code could be inlined here, however if we use
2718 // slow unlocking, speed doesn't matter anyway and this solution is
2719 // simpler and requires less duplicated code - additionally, the
2720 // slow unlocking code is the same in either case which simplifies
2721 // debugging.
2722 __ b(*op->stub()->entry());
2723 }
2724 }
2725 __ bind(*op->stub()->continuation());
2726 }
2727
2728 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2729 Register obj = op->obj()->as_pointer_register();
2730 Register result = op->result_opr()->as_pointer_register();
2731
2732 CodeEmitInfo* info = op->info();
2733 if (info != nullptr) {
2734 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2735 explicit_null_check(obj, info);
2736 } else {
2737 add_debug_info_for_null_check_here(info);
2738 }
2739 }
2740
2741 if (UseCompressedClassPointers) {
2742 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2743 __ decode_klass_not_null(result);
2744 } else {
2745 __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2746 }
2747 }
2748
2749 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2750 ciMethod* method = op->profiled_method();
2751 int bci = op->profiled_bci();
2752 ciMethod* callee = op->profiled_callee();
2753
2754 // Update counter for all call types.
2755 ciMethodData* md = method->method_data_or_null();
2756 assert(md != nullptr, "Sanity");
2757 ciProfileData* data = md->bci_to_data(bci);
2758 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2759 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2760 Register mdo = op->mdo()->as_register();
2761 #ifdef _LP64
2762 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2763 Register tmp1 = op->tmp1()->as_register_lo();
2764 #else
2765 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2766 Register tmp1 = op->tmp1()->as_register();
2767 #endif
2768 metadata2reg(md->constant_encoding(), mdo);
2769 int mdo_offset_bias = 0;
2770 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2771 data->size_in_bytes())) {
2772 // The offset is large so bias the mdo by the base of the slot so
2773 // that the ld can use simm16s to reference the slots of the data.
2774 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2775 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2776 }
2777
2778 // Perform additional virtual call profiling for invokevirtual and
2779 // invokeinterface bytecodes
2780 if (op->should_profile_receiver_type()) {
2781 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2782 Register recv = op->recv()->as_register();
2783 assert_different_registers(mdo, tmp1, recv);
2784 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2785 ciKlass* known_klass = op->known_holder();
2786 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2787 // We know the type that will be seen at this call site; we can
2788 // statically update the MethodData* rather than needing to do
2789 // dynamic tests on the receiver type.
2790
2791 // NOTE: we should probably put a lock around this search to
2792 // avoid collisions by concurrent compilations.
2793 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2794 uint i;
2795 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2796 ciKlass* receiver = vc_data->receiver(i);
2797 if (known_klass->equals(receiver)) {
2798 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2799 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2800 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2801 return;
2802 }
2803 }
2804
2805 // Receiver type not found in profile data; select an empty slot.
2806
2807 // Note that this is less efficient than it should be because it
2808 // always does a write to the receiver part of the
2809 // VirtualCallData rather than just the first time.
2810 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2811 ciKlass* receiver = vc_data->receiver(i);
2812 if (receiver == nullptr) {
2813 metadata2reg(known_klass->constant_encoding(), tmp1);
2814 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2815
2816 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2817 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2818 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2819 return;
2820 }
2821 }
2822 } else {
2823 __ load_klass(recv, recv);
2824 Label update_done;
2825 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2826 // Receiver did not match any saved receiver and there is no empty row for it.
2827 // Increment total counter to indicate polymorphic case.
2828 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2829 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2830 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2831
2832 __ bind(update_done);
2833 }
2834 } else {
2835 // Static call
2836 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2837 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2838 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2839 }
2840 }
2841
2842
2843 void LIR_Assembler::align_backward_branch_target() {
2844 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2845 }
2846
2847
2848 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2849 Unimplemented();
2850 }
2851
2852
2853 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2854 // tmp must be unused
2855 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2856 assert(left->is_register(), "can only handle registers");
2857
2858 if (left->is_single_cpu()) {
2859 __ neg(dest->as_register(), left->as_register());
2860 } else if (left->is_single_fpu()) {
2861 __ fneg(dest->as_float_reg(), left->as_float_reg());
2862 } else if (left->is_double_fpu()) {
2863 __ fneg(dest->as_double_reg(), left->as_double_reg());
2864 } else {
2865 assert (left->is_double_cpu(), "Must be a long");
2866 __ neg(dest->as_register_lo(), left->as_register_lo());
2867 }
2868 }
2869
2870
2871 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2872 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2873 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2874 if (dest == Runtime1::entry_for(C1StubId::register_finalizer_id) ||
2875 dest == Runtime1::entry_for(C1StubId::new_multi_array_id )) {
2876 //__ load_const_optimized(R0, dest);
2877 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2878 __ mtctr(R0);
2879 __ bctrl();
2880 assert(info != nullptr, "sanity");
2881 add_call_info_here(info);
2882 __ post_call_nop();
2883 return;
2884 }
2885
2886 __ call_c(dest, relocInfo::runtime_call_type);
2887 if (info != nullptr) {
2888 add_call_info_here(info);
2889 }
2890 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2891 __ post_call_nop();
2892 }
2893
2894
2895 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2896 ShouldNotReachHere(); // Not needed on _LP64.
2897 }
2898
2899 void LIR_Assembler::membar() {
2900 __ fence();
2901 }
2902
2903 void LIR_Assembler::membar_acquire() {
2904 __ acquire();
2905 }
2906
2907 void LIR_Assembler::membar_release() {
2908 __ release();
2909 }
2910
2911 void LIR_Assembler::membar_loadload() {
2912 __ membar(Assembler::LoadLoad);
2913 }
2914
2915 void LIR_Assembler::membar_storestore() {
2916 __ membar(Assembler::StoreStore);
2917 }
2918
2919 void LIR_Assembler::membar_loadstore() {
2920 __ membar(Assembler::LoadStore);
2921 }
2922
2923 void LIR_Assembler::membar_storeload() {
2924 __ membar(Assembler::StoreLoad);
2925 }
2926
2927 void LIR_Assembler::on_spin_wait() {
2928 Unimplemented();
2929 }
2930
2931 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2932 LIR_Address* addr = addr_opr->as_address_ptr();
2933 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2934
2935 if (addr->index()->is_illegal()) {
2936 if (patch_code != lir_patch_none) {
2937 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2938 __ load_const32(R0, 0); // patchable int
2939 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2940 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2941 } else {
2942 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2943 }
2944 } else {
2945 assert(patch_code == lir_patch_none, "Patch code not supported");
2946 assert(addr->disp() == 0, "can't have both: index and disp");
2947 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2948 }
2949 }
2950
2951
2952 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2953 ShouldNotReachHere();
2954 }
2955
2956
2957 #ifdef ASSERT
2958 // Emit run-time assertion.
2959 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2960 Unimplemented();
2961 }
2962 #endif
2963
2964
2965 void LIR_Assembler::peephole(LIR_List* lir) {
2966 // Optimize instruction pairs before emitting.
2967 LIR_OpList* inst = lir->instructions_list();
2968 for (int i = 1; i < inst->length(); i++) {
2969 LIR_Op* op = inst->at(i);
2970
2971 // 2 register-register-moves
2972 if (op->code() == lir_move) {
2973 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2974 res2 = ((LIR_Op1*)op)->result_opr();
2975 if (in2->is_register() && res2->is_register()) {
2976 LIR_Op* prev = inst->at(i - 1);
2977 if (prev && prev->code() == lir_move) {
2978 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2979 res1 = ((LIR_Op1*)prev)->result_opr();
2980 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2981 inst->remove_at(i);
2982 }
2983 }
2984 }
2985 }
2986
2987 }
2988 return;
2989 }
2990
2991
2992 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2993 const LIR_Address *addr = src->as_address_ptr();
2994 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2995 const Register Rptr = addr->base()->as_pointer_register(),
2996 Rtmp = tmp->as_register();
2997 Register Robj = noreg;
2998 if (data->is_oop()) {
2999 if (UseCompressedOops) {
3000 Robj = __ encode_heap_oop(Rtmp, data->as_register());
3001 } else {
3002 Robj = data->as_register();
3003 if (Robj == dest->as_register()) { // May happen with ZGC.
3004 __ mr(Rtmp, Robj);
3005 Robj = Rtmp;
3006 }
3007 }
3008 }
3009
3010 // There might be a volatile load before this Unsafe OP.
3011 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3012 __ sync();
3013 } else {
3014 __ lwsync();
3015 }
3016
3017 Label Lretry;
3018 __ bind(Lretry);
3019
3020 if (data->type() == T_INT) {
3021 const Register Rold = dest->as_register(),
3022 Rsrc = data->as_register();
3023 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3024 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3025 if (code == lir_xadd) {
3026 __ add(Rtmp, Rsrc, Rold);
3027 __ stwcx_(Rtmp, Rptr);
3028 } else {
3029 __ stwcx_(Rsrc, Rptr);
3030 }
3031 } else if (data->is_oop()) {
3032 assert(code == lir_xchg, "xadd for oops");
3033 const Register Rold = dest->as_register();
3034 assert_different_registers(Rptr, Rold, Robj);
3035 if (UseCompressedOops) {
3036 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3037 __ stwcx_(Robj, Rptr);
3038 } else {
3039 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3040 __ stdcx_(Robj, Rptr);
3041 }
3042 } else if (data->type() == T_LONG) {
3043 const Register Rold = dest->as_register_lo(),
3044 Rsrc = data->as_register_lo();
3045 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3046 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3047 if (code == lir_xadd) {
3048 __ add(Rtmp, Rsrc, Rold);
3049 __ stdcx_(Rtmp, Rptr);
3050 } else {
3051 __ stdcx_(Rsrc, Rptr);
3052 }
3053 } else {
3054 ShouldNotReachHere();
3055 }
3056
3057 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3058 __ bne_predict_not_taken(CCR0, Lretry);
3059 } else {
3060 __ bne( CCR0, Lretry);
3061 }
3062
3063 if (UseCompressedOops && data->is_oop()) {
3064 __ decode_heap_oop(dest->as_register());
3065 }
3066
3067 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3068 __ isync();
3069 } else {
3070 __ sync();
3071 }
3072 }
3073
3074
3075 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3076 Register obj = op->obj()->as_register();
3077 Register tmp = op->tmp()->as_pointer_register();
3078 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3079 ciKlass* exact_klass = op->exact_klass();
3080 intptr_t current_klass = op->current_klass();
3081 bool not_null = op->not_null();
3082 bool no_conflict = op->no_conflict();
3083
3084 Label Lupdate, Ldo_update, Ldone;
3085
3086 bool do_null = !not_null;
3087 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3088 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3089
3090 assert(do_null || do_update, "why are we here?");
3091 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3092
3093 __ verify_oop(obj, FILE_AND_LINE);
3094
3095 if (do_null) {
3096 if (!TypeEntries::was_null_seen(current_klass)) {
3097 __ cmpdi(CCR0, obj, 0);
3098 __ bne(CCR0, Lupdate);
3099 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3100 __ ori(R0, R0, TypeEntries::null_seen);
3101 if (do_update) {
3102 __ b(Ldo_update);
3103 } else {
3104 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3105 }
3106 } else {
3107 if (do_update) {
3108 __ cmpdi(CCR0, obj, 0);
3109 __ beq(CCR0, Ldone);
3110 }
3111 }
3112 #ifdef ASSERT
3113 } else {
3114 __ cmpdi(CCR0, obj, 0);
3115 __ bne(CCR0, Lupdate);
3116 __ stop("unexpected null obj");
3117 #endif
3118 }
3119
3120 __ bind(Lupdate);
3121 if (do_update) {
3122 Label Lnext;
3123 const Register klass = R29_TOC; // kill and reload
3124 bool klass_reg_used = false;
3125 #ifdef ASSERT
3126 if (exact_klass != nullptr) {
3127 Label ok;
3128 klass_reg_used = true;
3129 __ load_klass(klass, obj);
3130 metadata2reg(exact_klass->constant_encoding(), R0);
3131 __ cmpd(CCR0, klass, R0);
3132 __ beq(CCR0, ok);
3133 __ stop("exact klass and actual klass differ");
3134 __ bind(ok);
3135 }
3136 #endif
3137
3138 if (!no_conflict) {
3139 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3140 klass_reg_used = true;
3141 if (exact_klass != nullptr) {
3142 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3143 metadata2reg(exact_klass->constant_encoding(), klass);
3144 } else {
3145 __ load_klass(klass, obj);
3146 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3147 }
3148
3149 // Like InterpreterMacroAssembler::profile_obj_type
3150 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3151 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3152 __ cmpd(CCR1, R0, klass);
3153 // Klass seen before, nothing to do (regardless of unknown bit).
3154 //beq(CCR1, do_nothing);
3155
3156 __ andi_(R0, tmp, TypeEntries::type_unknown);
3157 // Already unknown. Nothing to do anymore.
3158 //bne(CCR0, do_nothing);
3159 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3160 __ beq(CCR0, Lnext);
3161
3162 if (TypeEntries::is_type_none(current_klass)) {
3163 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3164 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3165 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3166 }
3167
3168 } else {
3169 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3170 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3171
3172 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3173 __ andi_(R0, tmp, TypeEntries::type_unknown);
3174 // Already unknown. Nothing to do anymore.
3175 __ bne(CCR0, Lnext);
3176 }
3177
3178 // Different than before. Cannot keep accurate profile.
3179 __ ori(R0, tmp, TypeEntries::type_unknown);
3180 } else {
3181 // There's a single possible klass at this profile point
3182 assert(exact_klass != nullptr, "should be");
3183 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3184
3185 if (TypeEntries::is_type_none(current_klass)) {
3186 klass_reg_used = true;
3187 metadata2reg(exact_klass->constant_encoding(), klass);
3188
3189 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3190 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3191 __ cmpd(CCR1, R0, klass);
3192 // Klass seen before, nothing to do (regardless of unknown bit).
3193 __ beq(CCR1, Lnext);
3194 #ifdef ASSERT
3195 {
3196 Label ok;
3197 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3198 __ beq(CCR0, ok); // First time here.
3199
3200 __ stop("unexpected profiling mismatch");
3201 __ bind(ok);
3202 }
3203 #endif
3204 // First time here. Set profile type.
3205 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3206 } else {
3207 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3208 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3209
3210 // Already unknown. Nothing to do anymore.
3211 __ andi_(R0, tmp, TypeEntries::type_unknown);
3212 __ bne(CCR0, Lnext);
3213
3214 // Different than before. Cannot keep accurate profile.
3215 __ ori(R0, tmp, TypeEntries::type_unknown);
3216 }
3217 }
3218
3219 __ bind(Ldo_update);
3220 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3221
3222 __ bind(Lnext);
3223 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3224 }
3225 __ bind(Ldone);
3226 }
3227
3228 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3229 Unimplemented();
3230 }
3231
3232 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3233 assert(op->crc()->is_single_cpu(), "crc must be register");
3234 assert(op->val()->is_single_cpu(), "byte value must be register");
3235 assert(op->result_opr()->is_single_cpu(), "result must be register");
3236 Register crc = op->crc()->as_register();
3237 Register val = op->val()->as_register();
3238 Register res = op->result_opr()->as_register();
3239
3240 assert_different_registers(val, crc, res);
3241
3242 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3243 __ kernel_crc32_singleByteReg(crc, val, res, true);
3244 __ mr(res, crc);
3245 }
3246
3247 #undef __