1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_ppc.hpp"
37 #include "oops/compressedOops.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/os.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/macros.hpp"
46 #include "utilities/powerOfTwo.hpp"
47
48 #define __ _masm->
49
50
51 const ConditionRegister LIR_Assembler::BOOL_RESULT = CR5;
52
53
54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
55 Unimplemented(); return false; // Currently not used on this platform.
56 }
57
58
59 LIR_Opr LIR_Assembler::receiverOpr() {
60 return FrameMap::R3_oop_opr;
61 }
62
63
64 LIR_Opr LIR_Assembler::osrBufferPointer() {
65 return FrameMap::R3_opr;
66 }
67
68
69 // This specifies the stack pointer decrement needed to build the frame.
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74
75 // Inline cache check: the inline cached class is in inline_cache_reg;
76 // we fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = R20;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
92 __ mtctr(klass);
93 __ bctr();
94
95 __ bind(L_skip_barrier);
96 }
97
98 void LIR_Assembler::osr_entry() {
99 // On-stack-replacement entry sequence:
100 //
101 // 1. Create a new compiled activation.
102 // 2. Initialize local variables in the compiled activation. The expression
103 // stack must be empty at the osr_bci; it is not initialized.
104 // 3. Jump to the continuation address in compiled code to resume execution.
105
106 // OSR entry point
107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
108 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
109 ValueStack* entry_state = osr_entry->end()->state();
110 int number_of_locks = entry_state->locks_size();
111
112 // Create a frame for the compiled activation.
113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
114
115 // OSR buffer is
116 //
117 // locals[nlocals-1..0]
118 // monitors[number_of_locks-1..0]
119 //
120 // Locals is a direct copy of the interpreter frame so in the osr buffer
121 // the first slot in the local array is the last local from the interpreter
122 // and the last slot is local[0] (receiver) from the interpreter.
123 //
124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
126 // in the interpreter frame (the method lock if a sync method).
127
128 // Initialize monitors in the compiled activation.
129 // R3: pointer to osr buffer
130 //
131 // All other registers are dead at this point and the locals will be
132 // copied into place by code emitted in the IR.
133
134 Register OSR_buf = osrBufferPointer()->as_register();
135 {
136 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137
138 const int locals_space = BytesPerWord * method()->max_locals();
139 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
140 bool use_OSR_bias = false;
141
142 if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
143 // Offsets too large for ld instructions. Use bias.
144 __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
145 monitor_offset -= locals_space;
146 use_OSR_bias = true;
147 }
148
149 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
150 // the OSR buffer using 2 word entries: first the lock and then
151 // the oop.
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
154 #ifdef ASSERT
155 // Verify the interpreter's monitor has a non-null object.
156 {
157 Label L;
158 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
159 __ cmpdi(CR0, R0, 0);
160 __ bne(CR0, L);
161 __ stop("locked object is null");
162 __ bind(L);
163 }
164 #endif // ASSERT
165 // Copy the lock field into the compiled activation.
166 Address ml = frame_map()->address_for_monitor_lock(i),
167 mo = frame_map()->address_for_monitor_object(i);
168 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
169 __ ld(R0, slot_offset + 0, OSR_buf);
170 __ std(R0, ml);
171 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
172 __ std(R0, mo);
173 }
174
175 if (use_OSR_bias) {
176 // Restore.
177 __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
178 }
179 }
180 }
181
182
183 int LIR_Assembler::emit_exception_handler() {
184 // Generate code for the exception handler.
185 address handler_base = __ start_a_stub(exception_handler_size());
186
187 if (handler_base == nullptr) {
188 // Not enough space left for the handler.
189 bailout("exception handler overflow");
190 return -1;
191 }
192
193 int offset = code_offset();
194 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id));
195 //__ load_const_optimized(R0, entry_point);
196 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
197 __ mtctr(R0);
198 __ bctr();
199
200 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
201 __ end_a_stub();
202
203 return offset;
204 }
205
206
207 // Emit the code to remove the frame from the stack in the exception
208 // unwind path.
209 int LIR_Assembler::emit_unwind_handler() {
210 _masm->block_comment("Unwind handler");
211
212 int offset = code_offset();
213 bool preserve_exception = method()->is_synchronized();
214 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
215
216 // Fetch the exception from TLS and clear out exception related thread state.
217 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
218 __ li(R0, 0);
219 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
220 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
221
222 __ bind(_unwind_handler_entry);
223 __ verify_not_null_oop(Rexception);
224 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
225
226 // Perform needed unlocking
227 MonitorExitStub* stub = nullptr;
228 if (method()->is_synchronized()) {
229 monitor_address(0, FrameMap::R4_opr);
230 stub = new MonitorExitStub(FrameMap::R4_opr, 0);
231 __ unlock_object(R5, R6, R4, *stub->entry());
232 __ bind(*stub->continuation());
233 }
234
235 // Dispatch to the unwind logic.
236 address unwind_stub = Runtime1::entry_for(StubId::c1_unwind_exception_id);
237 //__ load_const_optimized(R0, unwind_stub);
238 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
239 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
240 __ mtctr(R0);
241 __ bctr();
242
243 // Emit the slow path assembly.
244 if (stub != nullptr) {
245 stub->emit_code(this);
246 }
247
248 return offset;
249 }
250
251
252 int LIR_Assembler::emit_deopt_handler() {
253 // Generate code for deopt handler.
254 address handler_base = __ start_a_stub(deopt_handler_size());
255
256 if (handler_base == nullptr) {
257 // Not enough space left for the handler.
258 bailout("deopt handler overflow");
259 return -1;
260 }
261
262 int offset = code_offset();
263 Label start;
264
265 __ bind(start);
266 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
267 int entry_offset = __ offset();
268 __ b(start);
269
270 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
271 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
272 "out of bounds read in post-call NOP check");
273 __ end_a_stub();
274
275 return entry_offset;
276 }
277
278
279 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
280 if (o == nullptr) {
281 __ li(reg, 0);
282 } else {
283 AddressLiteral addrlit = __ constant_oop_address(o);
284 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
285 }
286 }
287
288
289 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
290 // Allocate a new index in table to hold the object once it's been patched.
291 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
292 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
293
294 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
295 __ load_const(reg, addrlit, R0);
296
297 patching_epilog(patch, lir_patch_normal, reg, info);
298 }
299
300
301 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
302 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
303 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
304 }
305
306
307 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
308 // Allocate a new index in table to hold the klass once it's been patched.
309 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
310 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
311
312 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
313 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
314 __ load_const(reg, addrlit, R0);
315
316 patching_epilog(patch, lir_patch_normal, reg, info);
317 }
318
319
320 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
321 const bool is_int = result->is_single_cpu();
322 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
323 Register Rdivisor = noreg;
324 Register Rscratch = temp->as_register();
325 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
326 long divisor = -1;
327
328 if (right->is_register()) {
329 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
330 } else {
331 divisor = is_int ? right->as_constant_ptr()->as_jint()
332 : right->as_constant_ptr()->as_jlong();
333 }
334
335 assert(Rdividend != Rscratch, "");
336 assert(Rdivisor != Rscratch, "");
337 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
338
339 if (Rdivisor == noreg) {
340 if (divisor == 1) { // stupid, but can happen
341 if (code == lir_idiv) {
342 __ mr_if_needed(Rresult, Rdividend);
343 } else {
344 __ li(Rresult, 0);
345 }
346
347 } else if (is_power_of_2(divisor)) {
348 // Convert division by a power of two into some shifts and logical operations.
349 int log2 = log2i_exact(divisor);
350
351 // Round towards 0.
352 if (divisor == 2) {
353 if (is_int) {
354 __ srwi(Rscratch, Rdividend, 31);
355 } else {
356 __ srdi(Rscratch, Rdividend, 63);
357 }
358 } else {
359 if (is_int) {
360 __ srawi(Rscratch, Rdividend, 31);
361 } else {
362 __ sradi(Rscratch, Rdividend, 63);
363 }
364 __ clrldi(Rscratch, Rscratch, 64-log2);
365 }
366 __ add(Rscratch, Rdividend, Rscratch);
367
368 if (code == lir_idiv) {
369 if (is_int) {
370 __ srawi(Rresult, Rscratch, log2);
371 } else {
372 __ sradi(Rresult, Rscratch, log2);
373 }
374 } else { // lir_irem
375 __ clrrdi(Rscratch, Rscratch, log2);
376 __ sub(Rresult, Rdividend, Rscratch);
377 }
378
379 } else if (divisor == -1) {
380 if (code == lir_idiv) {
381 __ neg(Rresult, Rdividend);
382 } else {
383 __ li(Rresult, 0);
384 }
385
386 } else {
387 __ load_const_optimized(Rscratch, divisor);
388 if (code == lir_idiv) {
389 if (is_int) {
390 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
391 } else {
392 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
393 }
394 } else {
395 assert(Rscratch != R0, "need both");
396 if (is_int) {
397 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
398 __ mullw(Rscratch, R0, Rscratch);
399 } else {
400 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
401 __ mulld(Rscratch, R0, Rscratch);
402 }
403 __ sub(Rresult, Rdividend, Rscratch);
404 }
405
406 }
407 return;
408 }
409
410 Label regular, done;
411 if (is_int) {
412 __ cmpwi(CR0, Rdivisor, -1);
413 } else {
414 __ cmpdi(CR0, Rdivisor, -1);
415 }
416 __ bne(CR0, regular);
417 if (code == lir_idiv) {
418 __ neg(Rresult, Rdividend);
419 __ b(done);
420 __ bind(regular);
421 if (is_int) {
422 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
423 } else {
424 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
425 }
426 } else { // lir_irem
427 __ li(Rresult, 0);
428 __ b(done);
429 __ bind(regular);
430 if (is_int) {
431 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
432 __ mullw(Rscratch, Rscratch, Rdivisor);
433 } else {
434 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
435 __ mulld(Rscratch, Rscratch, Rdivisor);
436 }
437 __ sub(Rresult, Rdividend, Rscratch);
438 }
439 __ bind(done);
440 }
441
442
443 void LIR_Assembler::emit_op3(LIR_Op3* op) {
444 switch (op->code()) {
445 case lir_idiv:
446 case lir_irem:
447 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
448 op->result_opr(), op->info());
449 break;
450 case lir_fmad:
451 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
452 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
453 break;
454 case lir_fmaf:
455 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
456 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
457 break;
458 default: ShouldNotReachHere(); break;
459 }
460 }
461
462
463 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
464 #ifdef ASSERT
465 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
466 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
467 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
468 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
469 #endif
470
471 Label *L = op->label();
472 if (op->cond() == lir_cond_always) {
473 __ b(*L);
474 } else {
475 Label done;
476 bool is_unordered = false;
477 if (op->code() == lir_cond_float_branch) {
478 assert(op->ublock() != nullptr, "must have unordered successor");
479 is_unordered = true;
480 } else {
481 assert(op->code() == lir_branch, "just checking");
482 }
483
484 bool positive = false;
485 Assembler::Condition cond = Assembler::equal;
486 switch (op->cond()) {
487 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
488 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
489 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
490 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
491 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
492 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
493 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
494 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
495 default: ShouldNotReachHere();
496 }
497 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
498 int bi = Assembler::bi0(BOOL_RESULT, cond);
499 if (is_unordered) {
500 if (positive) {
501 if (op->ublock() == op->block()) {
502 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
503 }
504 } else {
505 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
506 }
507 }
508 __ bc_far_optimized(bo, bi, *L);
509 __ bind(done);
510 }
511 }
512
513
514 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
515 Bytecodes::Code code = op->bytecode();
516 LIR_Opr src = op->in_opr(),
517 dst = op->result_opr();
518
519 switch(code) {
520 case Bytecodes::_i2l: {
521 __ extsw(dst->as_register_lo(), src->as_register());
522 break;
523 }
524 case Bytecodes::_l2i: {
525 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
526 break;
527 }
528 case Bytecodes::_i2b: {
529 __ extsb(dst->as_register(), src->as_register());
530 break;
531 }
532 case Bytecodes::_i2c: {
533 __ clrldi(dst->as_register(), src->as_register(), 64-16);
534 break;
535 }
536 case Bytecodes::_i2s: {
537 __ extsh(dst->as_register(), src->as_register());
538 break;
539 }
540 case Bytecodes::_i2d:{
541 FloatRegister rdst = dst->as_double_reg();
542 // move src to dst register
543 __ mtfprwa(rdst, src->as_register());
544 __ fcfid(rdst, rdst);
545 break;
546 }
547 case Bytecodes::_l2d: {
548 FloatRegister rdst = dst->as_double_reg();
549 // move src to dst register
550 __ mtfprd(rdst, src->as_register_lo());
551 __ fcfid(rdst, rdst);
552 break;
553 }
554 case Bytecodes::_i2f:{
555 FloatRegister rdst = dst->as_float_reg();
556 // move src to dst register
557 __ mtfprwa(rdst, src->as_register());
558 __ fcfids(rdst, rdst);
559 break;
560 }
561 case Bytecodes::_l2f: {
562 FloatRegister rdst = dst->as_float_reg();
563 // move src to dst register
564 __ mtfprd(rdst, src->as_register_lo());
565 __ fcfids(rdst, rdst);
566 break;
567 }
568 case Bytecodes::_f2d: {
569 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
570 break;
571 }
572 case Bytecodes::_d2f: {
573 __ frsp(dst->as_float_reg(), src->as_double_reg());
574 break;
575 }
576 case Bytecodes::_d2i:
577 case Bytecodes::_f2i: {
578 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
579 Label L;
580 // Result must be 0 if value is NaN; test by comparing value to itself.
581 __ fcmpu(CR0, rsrc, rsrc);
582 __ li(dst->as_register(), 0);
583 __ bso(CR0, L);
584 __ fctiwz(rsrc, rsrc); // USE_KILL
585 __ mffprd(dst->as_register(), rsrc);
586 __ bind(L);
587 break;
588 }
589 case Bytecodes::_d2l:
590 case Bytecodes::_f2l: {
591 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
592 Label L;
593 // Result must be 0 if value is NaN; test by comparing value to itself.
594 __ fcmpu(CR0, rsrc, rsrc);
595 __ li(dst->as_register_lo(), 0);
596 __ bso(CR0, L);
597 __ fctidz(rsrc, rsrc); // USE_KILL
598 __ mffprd(dst->as_register_lo(), rsrc);
599 __ bind(L);
600 break;
601 }
602
603 default: ShouldNotReachHere();
604 }
605 }
606
607
608 void LIR_Assembler::align_call(LIR_Code) {
609 // do nothing since all instructions are word aligned on ppc
610 }
611
612
613 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
614 int start_offset = __ offset();
615 // Put the entry point as a constant into the constant pool.
616 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
617 if (entry_point_toc_addr == nullptr) {
618 bailout("const section overflow");
619 return false;
620 }
621 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
622
623 // Emit the trampoline stub which will be related to the branch-and-link below.
624 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
625 if (!stub) {
626 bailout("no space for trampoline stub");
627 return false;
628 }
629 return true;
630 }
631
632
633 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
634 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
635
636 bool success = emit_trampoline_stub_for_call(op->addr());
637 if (!success) { return; }
638
639 __ relocate(rtype);
640 // Note: At this point we do not have the address of the trampoline
641 // stub, and the entry point might be too far away for bl, so __ pc()
642 // serves as dummy and the bl will be patched later.
643 __ code()->set_insts_mark();
644 __ bl(__ pc());
645 add_call_info(code_offset(), op->info());
646 __ post_call_nop();
647 }
648
649
650 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
651 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
652
653 // Virtual call relocation will point to ic load.
654 address virtual_call_meta_addr = __ pc();
655 // Load a clear inline cache.
656 AddressLiteral empty_ic((address) Universe::non_oop_word());
657 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
658 if (!success) {
659 bailout("const section overflow");
660 return;
661 }
662 // Call to fixup routine. Fixup routine uses ScopeDesc info
663 // to determine who we intended to call.
664 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
665
666 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
667 if (!success) { return; }
668
669 // Note: At this point we do not have the address of the trampoline
670 // stub, and the entry point might be too far away for bl, so __ pc()
671 // serves as dummy and the bl will be patched later.
672 __ bl(__ pc());
673 add_call_info(code_offset(), op->info());
674 __ post_call_nop();
675 }
676
677 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
678 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
679 __ null_check(addr, stub->entry());
680 append_code_stub(stub);
681 }
682
683
684 // Attention: caller must encode oop if needed
685 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
686 int store_offset;
687 if (!Assembler::is_simm16(offset)) {
688 // For offsets larger than a simm16 we setup the offset.
689 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
690 __ load_const_optimized(R0, offset);
691 store_offset = store(from_reg, base, R0, type, wide);
692 } else {
693 store_offset = code_offset();
694 switch (type) {
695 case T_BOOLEAN: // fall through
696 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
697 case T_CHAR :
698 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
699 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
700 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
701 case T_ADDRESS:
702 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
703 case T_ARRAY : // fall through
704 case T_OBJECT:
705 {
706 if (UseCompressedOops && !wide) {
707 // Encoding done in caller
708 __ stw(from_reg->as_register(), offset, base);
709 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
710 } else {
711 __ std(from_reg->as_register(), offset, base);
712 if (VerifyOops) {
713 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
714 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
715 }
716 }
717 break;
718 }
719 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
720 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
721 default : ShouldNotReachHere();
722 }
723 }
724 return store_offset;
725 }
726
727
728 // Attention: caller must encode oop if needed
729 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
730 int store_offset = code_offset();
731 switch (type) {
732 case T_BOOLEAN: // fall through
733 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
734 case T_CHAR :
735 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
736 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
737 case T_LONG :
738 #ifdef _LP64
739 __ stdx(from_reg->as_register_lo(), base, disp);
740 #else
741 Unimplemented();
742 #endif
743 break;
744 case T_ADDRESS:
745 __ stdx(from_reg->as_register(), base, disp);
746 break;
747 case T_ARRAY : // fall through
748 case T_OBJECT:
749 {
750 if (UseCompressedOops && !wide) {
751 // Encoding done in caller.
752 __ stwx(from_reg->as_register(), base, disp);
753 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
754 } else {
755 __ stdx(from_reg->as_register(), base, disp);
756 if (VerifyOops) {
757 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
758 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
759 }
760 }
761 break;
762 }
763 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
764 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
765 default : ShouldNotReachHere();
766 }
767 return store_offset;
768 }
769
770
771 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
772 int load_offset;
773 if (!Assembler::is_simm16(offset)) {
774 // For offsets larger than a simm16 we setup the offset.
775 __ load_const_optimized(R0, offset);
776 load_offset = load(base, R0, to_reg, type, wide);
777 } else {
778 load_offset = code_offset();
779 switch(type) {
780 case T_BOOLEAN: // fall through
781 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
782 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
783 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
784 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
785 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
786 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
787 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
788 case T_ADDRESS:
789 __ ld(to_reg->as_register(), offset, base);
790 break;
791 case T_ARRAY : // fall through
792 case T_OBJECT:
793 {
794 if (UseCompressedOops && !wide) {
795 __ lwz(to_reg->as_register(), offset, base);
796 __ decode_heap_oop(to_reg->as_register());
797 } else {
798 __ ld(to_reg->as_register(), offset, base);
799 }
800 break;
801 }
802 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
803 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
804 default : ShouldNotReachHere();
805 }
806 }
807 return load_offset;
808 }
809
810
811 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
812 int load_offset = code_offset();
813 switch(type) {
814 case T_BOOLEAN: // fall through
815 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
816 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
817 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
818 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
819 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
820 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
821 case T_ARRAY : // fall through
822 case T_OBJECT:
823 {
824 if (UseCompressedOops && !wide) {
825 __ lwzx(to_reg->as_register(), base, disp);
826 __ decode_heap_oop(to_reg->as_register());
827 } else {
828 __ ldx(to_reg->as_register(), base, disp);
829 }
830 break;
831 }
832 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
833 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
834 case T_LONG :
835 #ifdef _LP64
836 __ ldx(to_reg->as_register_lo(), base, disp);
837 #else
838 Unimplemented();
839 #endif
840 break;
841 default : ShouldNotReachHere();
842 }
843 return load_offset;
844 }
845
846
847 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
848 LIR_Const* c = src->as_constant_ptr();
849 Register src_reg = R0;
850 switch (c->type()) {
851 case T_INT:
852 case T_FLOAT: {
853 int value = c->as_jint_bits();
854 __ load_const_optimized(src_reg, value);
855 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
856 __ stw(src_reg, addr);
857 break;
858 }
859 case T_ADDRESS: {
860 int value = c->as_jint_bits();
861 __ load_const_optimized(src_reg, value);
862 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
863 __ std(src_reg, addr);
864 break;
865 }
866 case T_OBJECT: {
867 jobject2reg(c->as_jobject(), src_reg);
868 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
869 __ std(src_reg, addr);
870 break;
871 }
872 case T_LONG:
873 case T_DOUBLE: {
874 int value = c->as_jlong_bits();
875 __ load_const_optimized(src_reg, value);
876 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
877 __ std(src_reg, addr);
878 break;
879 }
880 default:
881 Unimplemented();
882 }
883 }
884
885
886 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
887 LIR_Const* c = src->as_constant_ptr();
888 LIR_Address* addr = dest->as_address_ptr();
889 Register base = addr->base()->as_pointer_register();
890 LIR_Opr tmp = LIR_OprFact::illegalOpr;
891 int offset = -1;
892 // Null check for large offsets in LIRGenerator::do_StoreField.
893 bool needs_explicit_null_check = !ImplicitNullChecks;
894
895 if (info != nullptr && needs_explicit_null_check) {
896 explicit_null_check(base, info);
897 }
898
899 switch (c->type()) {
900 case T_FLOAT: type = T_INT;
901 case T_INT:
902 case T_ADDRESS: {
903 tmp = FrameMap::R0_opr;
904 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
905 break;
906 }
907 case T_DOUBLE: type = T_LONG;
908 case T_LONG: {
909 tmp = FrameMap::R0_long_opr;
910 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
911 break;
912 }
913 case T_OBJECT: {
914 tmp = FrameMap::R0_opr;
915 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
916 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
917 // Don't care about sign extend (will use stw).
918 __ lis(R0, 0); // Will get patched.
919 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
920 __ ori(R0, R0, 0); // Will get patched.
921 } else {
922 jobject2reg(c->as_jobject(), R0);
923 }
924 break;
925 }
926 default:
927 Unimplemented();
928 }
929
930 // Handle either reg+reg or reg+disp address.
931 if (addr->index()->is_valid()) {
932 assert(addr->disp() == 0, "must be zero");
933 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
934 } else {
935 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
936 offset = store(tmp, base, addr->disp(), type, wide);
937 }
938
939 if (info != nullptr) {
940 assert(offset != -1, "offset should've been set");
941 if (!needs_explicit_null_check) {
942 add_debug_info_for_null_check(offset, info);
943 }
944 }
945 }
946
947
948 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
949 LIR_Const* c = src->as_constant_ptr();
950 LIR_Opr to_reg = dest;
951
952 switch (c->type()) {
953 case T_INT: {
954 assert(patch_code == lir_patch_none, "no patching handled here");
955 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
956 break;
957 }
958 case T_ADDRESS: {
959 assert(patch_code == lir_patch_none, "no patching handled here");
960 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
961 break;
962 }
963 case T_LONG: {
964 assert(patch_code == lir_patch_none, "no patching handled here");
965 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
966 break;
967 }
968
969 case T_OBJECT: {
970 if (patch_code == lir_patch_none) {
971 jobject2reg(c->as_jobject(), to_reg->as_register());
972 } else {
973 jobject2reg_with_patching(to_reg->as_register(), info);
974 }
975 break;
976 }
977
978 case T_METADATA:
979 {
980 if (patch_code == lir_patch_none) {
981 metadata2reg(c->as_metadata(), to_reg->as_register());
982 } else {
983 klass2reg_with_patching(to_reg->as_register(), info);
984 }
985 }
986 break;
987
988 case T_FLOAT:
989 {
990 if (to_reg->is_single_fpu()) {
991 address const_addr = __ float_constant(c->as_jfloat());
992 if (const_addr == nullptr) {
993 bailout("const section overflow");
994 break;
995 }
996 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
997 __ relocate(rspec);
998 __ load_const(R0, const_addr);
999 __ lfsx(to_reg->as_float_reg(), R0);
1000 } else {
1001 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1002 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1003 }
1004 }
1005 break;
1006
1007 case T_DOUBLE:
1008 {
1009 if (to_reg->is_double_fpu()) {
1010 address const_addr = __ double_constant(c->as_jdouble());
1011 if (const_addr == nullptr) {
1012 bailout("const section overflow");
1013 break;
1014 }
1015 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1016 __ relocate(rspec);
1017 __ load_const(R0, const_addr);
1018 __ lfdx(to_reg->as_double_reg(), R0);
1019 } else {
1020 assert(to_reg->is_double_cpu(), "Must be a long register.");
1021 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1022 }
1023 }
1024 break;
1025
1026 default:
1027 ShouldNotReachHere();
1028 }
1029 }
1030
1031
1032 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1033 Unimplemented(); return Address();
1034 }
1035
1036
1037 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1038 if (addr->index()->is_illegal()) {
1039 return (RegisterOrConstant)(addr->disp());
1040 } else {
1041 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1042 }
1043 }
1044
1045
1046 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1047 const Register tmp = R0;
1048 switch (type) {
1049 case T_INT:
1050 case T_FLOAT: {
1051 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1052 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1053 __ lwz(tmp, from);
1054 __ stw(tmp, to);
1055 break;
1056 }
1057 case T_ADDRESS:
1058 case T_OBJECT: {
1059 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1060 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1061 __ ld(tmp, from);
1062 __ std(tmp, to);
1063 break;
1064 }
1065 case T_LONG:
1066 case T_DOUBLE: {
1067 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1068 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1069 __ ld(tmp, from);
1070 __ std(tmp, to);
1071 break;
1072 }
1073
1074 default:
1075 ShouldNotReachHere();
1076 }
1077 }
1078
1079
1080 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1081 Unimplemented(); return Address();
1082 }
1083
1084
1085 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1086 Unimplemented(); return Address();
1087 }
1088
1089
1090 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1091 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1092
1093 assert(type != T_METADATA, "load of metadata ptr not supported");
1094 LIR_Address* addr = src_opr->as_address_ptr();
1095 LIR_Opr to_reg = dest;
1096
1097 Register src = addr->base()->as_pointer_register();
1098 Register disp_reg = noreg;
1099 int disp_value = addr->disp();
1100 bool needs_patching = (patch_code != lir_patch_none);
1101 // null check for large offsets in LIRGenerator::do_LoadField
1102 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1103
1104 if (info != nullptr && needs_explicit_null_check) {
1105 explicit_null_check(src, info);
1106 }
1107
1108 if (addr->base()->type() == T_OBJECT) {
1109 __ verify_oop(src, FILE_AND_LINE);
1110 }
1111
1112 PatchingStub* patch = nullptr;
1113 if (needs_patching) {
1114 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1115 assert(!to_reg->is_double_cpu() ||
1116 patch_code == lir_patch_none ||
1117 patch_code == lir_patch_normal, "patching doesn't match register");
1118 }
1119
1120 if (addr->index()->is_illegal()) {
1121 if (!Assembler::is_simm16(disp_value)) {
1122 if (needs_patching) {
1123 __ load_const32(R0, 0); // patchable int
1124 } else {
1125 __ load_const_optimized(R0, disp_value);
1126 }
1127 disp_reg = R0;
1128 }
1129 } else {
1130 disp_reg = addr->index()->as_pointer_register();
1131 assert(disp_value == 0, "can't handle 3 operand addresses");
1132 }
1133
1134 // Remember the offset of the load. The patching_epilog must be done
1135 // before the call to add_debug_info, otherwise the PcDescs don't get
1136 // entered in increasing order.
1137 int offset;
1138
1139 if (disp_reg == noreg) {
1140 assert(Assembler::is_simm16(disp_value), "should have set this up");
1141 offset = load(src, disp_value, to_reg, type, wide);
1142 } else {
1143 offset = load(src, disp_reg, to_reg, type, wide);
1144 }
1145
1146 if (patch != nullptr) {
1147 patching_epilog(patch, patch_code, src, info);
1148 }
1149 if (info != nullptr && !needs_explicit_null_check) {
1150 add_debug_info_for_null_check(offset, info);
1151 }
1152 }
1153
1154
1155 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1156 Address addr;
1157 if (src->is_single_word()) {
1158 addr = frame_map()->address_for_slot(src->single_stack_ix());
1159 } else if (src->is_double_word()) {
1160 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1161 }
1162
1163 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1164 }
1165
1166
1167 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) {
1168 Address addr;
1169 if (dest->is_single_word()) {
1170 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1171 } else if (dest->is_double_word()) {
1172 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1173 }
1174
1175 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1176 }
1177
1178
1179 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1180 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1181 if (from_reg->is_double_fpu()) {
1182 // double to double moves
1183 assert(to_reg->is_double_fpu(), "should match");
1184 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1185 } else {
1186 // float to float moves
1187 assert(to_reg->is_single_fpu(), "should match");
1188 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1189 }
1190 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1191 if (from_reg->is_double_cpu()) {
1192 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1193 } else if (to_reg->is_double_cpu()) {
1194 // int to int moves
1195 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1196 } else {
1197 // int to int moves
1198 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1199 }
1200 } else {
1201 ShouldNotReachHere();
1202 }
1203 if (is_reference_type(to_reg->type())) {
1204 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1205 }
1206 }
1207
1208
1209 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1210 LIR_PatchCode patch_code, CodeEmitInfo* info,
1211 bool wide) {
1212 assert(type != T_METADATA, "store of metadata ptr not supported");
1213 LIR_Address* addr = dest->as_address_ptr();
1214
1215 Register src = addr->base()->as_pointer_register();
1216 Register disp_reg = noreg;
1217 int disp_value = addr->disp();
1218 bool needs_patching = (patch_code != lir_patch_none);
1219 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1220 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1221 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1222 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1223 // Null check for large offsets in LIRGenerator::do_StoreField.
1224 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1225
1226 if (info != nullptr && needs_explicit_null_check) {
1227 explicit_null_check(src, info);
1228 }
1229
1230 if (addr->base()->is_oop_register()) {
1231 __ verify_oop(src, FILE_AND_LINE);
1232 }
1233
1234 PatchingStub* patch = nullptr;
1235 if (needs_patching) {
1236 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1237 assert(!from_reg->is_double_cpu() ||
1238 patch_code == lir_patch_none ||
1239 patch_code == lir_patch_normal, "patching doesn't match register");
1240 }
1241
1242 if (addr->index()->is_illegal()) {
1243 if (load_disp) {
1244 disp_reg = use_R29 ? R29_TOC : R0;
1245 if (needs_patching) {
1246 __ load_const32(disp_reg, 0); // patchable int
1247 } else {
1248 __ load_const_optimized(disp_reg, disp_value);
1249 }
1250 }
1251 } else {
1252 disp_reg = addr->index()->as_pointer_register();
1253 assert(disp_value == 0, "can't handle 3 operand addresses");
1254 }
1255
1256 // remember the offset of the store. The patching_epilog must be done
1257 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1258 // entered in increasing order.
1259 int offset;
1260
1261 if (compress_oop) {
1262 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1263 from_reg = FrameMap::as_opr(co);
1264 }
1265
1266 if (disp_reg == noreg) {
1267 assert(Assembler::is_simm16(disp_value), "should have set this up");
1268 offset = store(from_reg, src, disp_value, type, wide);
1269 } else {
1270 offset = store(from_reg, src, disp_reg, type, wide);
1271 }
1272
1273 if (use_R29) {
1274 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1275 }
1276
1277 if (patch != nullptr) {
1278 patching_epilog(patch, patch_code, src, info);
1279 }
1280
1281 if (info != nullptr && !needs_explicit_null_check) {
1282 add_debug_info_for_null_check(offset, info);
1283 }
1284 }
1285
1286
1287 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1288 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1289 const Register temp = R12;
1290
1291 // Pop the stack before the safepoint code.
1292 int frame_size = initial_frame_size_in_bytes();
1293 if (Assembler::is_simm(frame_size, 16)) {
1294 __ addi(R1_SP, R1_SP, frame_size);
1295 } else {
1296 __ pop_frame();
1297 }
1298
1299 // Restore return pc relative to callers' sp.
1300 __ ld(return_pc, _abi0(lr), R1_SP);
1301 // Move return pc to LR.
1302 __ mtlr(return_pc);
1303
1304 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1305 __ reserved_stack_check(return_pc);
1306 }
1307
1308 // We need to mark the code position where the load from the safepoint
1309 // polling page was emitted as relocInfo::poll_return_type here.
1310 if (!UseSIGTRAP) {
1311 code_stub->set_safepoint_offset(__ offset());
1312 __ relocate(relocInfo::poll_return_type);
1313 }
1314 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1315
1316 // Return.
1317 __ blr();
1318 }
1319
1320
1321 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1322 const Register poll_addr = tmp->as_register();
1323 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1324 if (info != nullptr) {
1325 add_debug_info_for_branch(info);
1326 }
1327 int offset = __ offset();
1328 __ relocate(relocInfo::poll_type);
1329 __ load_from_polling_page(poll_addr);
1330
1331 return offset;
1332 }
1333
1334
1335 void LIR_Assembler::emit_static_call_stub() {
1336 address call_pc = __ pc();
1337 address stub = __ start_a_stub(static_call_stub_size());
1338 if (stub == nullptr) {
1339 bailout("static call stub overflow");
1340 return;
1341 }
1342
1343 // For java_to_interp stubs we use R11_scratch1 as scratch register
1344 // and in call trampoline stubs we use R12_scratch2. This way we
1345 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1346 const Register reg_scratch = R11_scratch1;
1347
1348 // Create a static stub relocation which relates this stub
1349 // with the call instruction at insts_call_instruction_offset in the
1350 // instructions code-section.
1351 int start = __ offset();
1352 __ relocate(static_stub_Relocation::spec(call_pc));
1353
1354 // Now, create the stub's code:
1355 // - load the TOC
1356 // - load the inline cache oop from the constant pool
1357 // - load the call target from the constant pool
1358 // - call
1359 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1360 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1361 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1362
1363 if (ReoptimizeCallSequences) {
1364 __ b64_patchable((address)-1, relocInfo::none);
1365 } else {
1366 AddressLiteral a((address)-1);
1367 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1368 __ mtctr(reg_scratch);
1369 __ bctr();
1370 }
1371 if (!success) {
1372 bailout("const section overflow");
1373 return;
1374 }
1375
1376 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1377 __ end_a_stub();
1378 }
1379
1380
1381 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1382 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1383 if (opr1->is_single_fpu()) {
1384 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1385 } else if (opr1->is_double_fpu()) {
1386 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1387 } else if (opr1->is_single_cpu()) {
1388 if (opr2->is_constant()) {
1389 switch (opr2->as_constant_ptr()->type()) {
1390 case T_INT:
1391 {
1392 jint con = opr2->as_constant_ptr()->as_jint();
1393 if (unsigned_comp) {
1394 if (Assembler::is_uimm(con, 16)) {
1395 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1396 } else {
1397 __ load_const_optimized(R0, con);
1398 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1399 }
1400 } else {
1401 if (Assembler::is_simm(con, 16)) {
1402 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1403 } else {
1404 __ load_const_optimized(R0, con);
1405 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1406 }
1407 }
1408 }
1409 break;
1410
1411 case T_OBJECT:
1412 // There are only equal/notequal comparisons on objects.
1413 {
1414 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1415 jobject con = opr2->as_constant_ptr()->as_jobject();
1416 if (con == nullptr) {
1417 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1418 } else {
1419 jobject2reg(con, R0);
1420 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1421 }
1422 }
1423 break;
1424
1425 case T_METADATA:
1426 // We only need, for now, comparison with null for metadata.
1427 {
1428 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1429 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1430 if (p == nullptr) {
1431 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1432 } else {
1433 ShouldNotReachHere();
1434 }
1435 }
1436 break;
1437
1438 default:
1439 ShouldNotReachHere();
1440 break;
1441 }
1442 } else {
1443 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1444 if (is_reference_type(opr1->type())) {
1445 // There are only equal/notequal comparisons on objects.
1446 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1447 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1448 } else {
1449 if (unsigned_comp) {
1450 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1451 } else {
1452 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1453 }
1454 }
1455 }
1456 } else if (opr1->is_double_cpu()) {
1457 if (opr2->is_constant()) {
1458 jlong con = opr2->as_constant_ptr()->as_jlong();
1459 if (unsigned_comp) {
1460 if (Assembler::is_uimm(con, 16)) {
1461 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1462 } else {
1463 __ load_const_optimized(R0, con);
1464 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1465 }
1466 } else {
1467 if (Assembler::is_simm(con, 16)) {
1468 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1469 } else {
1470 __ load_const_optimized(R0, con);
1471 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1472 }
1473 }
1474 } else if (opr2->is_register()) {
1475 if (unsigned_comp) {
1476 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1477 } else {
1478 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1479 }
1480 } else {
1481 ShouldNotReachHere();
1482 }
1483 } else {
1484 ShouldNotReachHere();
1485 }
1486 }
1487
1488
1489 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1490 const Register Rdst = dst->as_register();
1491 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1492 bool is_unordered_less = (code == lir_ucmp_fd2i);
1493 if (left->is_single_fpu()) {
1494 __ fcmpu(CR0, left->as_float_reg(), right->as_float_reg());
1495 } else if (left->is_double_fpu()) {
1496 __ fcmpu(CR0, left->as_double_reg(), right->as_double_reg());
1497 } else {
1498 ShouldNotReachHere();
1499 }
1500 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1501 } else if (code == lir_cmp_l2i) {
1502 __ cmpd(CR0, left->as_register_lo(), right->as_register_lo());
1503 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1504 } else {
1505 ShouldNotReachHere();
1506 }
1507 }
1508
1509
1510 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1511 if (src->is_constant()) {
1512 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1513 } else if (src->is_register()) {
1514 lasm->reg2reg(src, dst);
1515 } else if (src->is_stack()) {
1516 lasm->stack2reg(src, dst, dst->type());
1517 } else {
1518 ShouldNotReachHere();
1519 }
1520 }
1521
1522 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1523 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1524 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1525
1526 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1527 load_to_reg(this, opr1, result); // Condition doesn't matter.
1528 return;
1529 }
1530
1531 bool positive = false;
1532 Assembler::Condition cond = Assembler::equal;
1533 switch (condition) {
1534 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1535 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1536 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1537 case lir_cond_belowEqual:
1538 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1539 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1540 case lir_cond_aboveEqual:
1541 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1542 default: ShouldNotReachHere();
1543 }
1544
1545 if (result->is_cpu_register()) {
1546 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1547 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1548
1549 // We can use result_reg to load one operand if not already in register.
1550 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1551 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1552
1553 if (first != second) {
1554 if (!o1_is_reg) {
1555 load_to_reg(this, opr1, result);
1556 }
1557
1558 if (!o2_is_reg) {
1559 load_to_reg(this, opr2, result);
1560 }
1561
1562 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1563 return;
1564 }
1565 } // isel
1566
1567 load_to_reg(this, opr1, result);
1568
1569 Label skip;
1570 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1571 int bi = Assembler::bi0(BOOL_RESULT, cond);
1572 __ bc(bo, bi, skip);
1573
1574 load_to_reg(this, opr2, result);
1575 __ bind(skip);
1576 }
1577
1578
1579 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1580 CodeEmitInfo* info) {
1581 assert(info == nullptr, "unused on this code path");
1582 assert(left->is_register(), "wrong items state");
1583 assert(dest->is_register(), "wrong items state");
1584
1585 if (right->is_register()) {
1586 if (dest->is_float_kind()) {
1587
1588 FloatRegister lreg, rreg, res;
1589 if (right->is_single_fpu()) {
1590 lreg = left->as_float_reg();
1591 rreg = right->as_float_reg();
1592 res = dest->as_float_reg();
1593 switch (code) {
1594 case lir_add: __ fadds(res, lreg, rreg); break;
1595 case lir_sub: __ fsubs(res, lreg, rreg); break;
1596 case lir_mul: __ fmuls(res, lreg, rreg); break;
1597 case lir_div: __ fdivs(res, lreg, rreg); break;
1598 default: ShouldNotReachHere();
1599 }
1600 } else {
1601 lreg = left->as_double_reg();
1602 rreg = right->as_double_reg();
1603 res = dest->as_double_reg();
1604 switch (code) {
1605 case lir_add: __ fadd(res, lreg, rreg); break;
1606 case lir_sub: __ fsub(res, lreg, rreg); break;
1607 case lir_mul: __ fmul(res, lreg, rreg); break;
1608 case lir_div: __ fdiv(res, lreg, rreg); break;
1609 default: ShouldNotReachHere();
1610 }
1611 }
1612
1613 } else if (dest->is_double_cpu()) {
1614
1615 Register dst_lo = dest->as_register_lo();
1616 Register op1_lo = left->as_pointer_register();
1617 Register op2_lo = right->as_pointer_register();
1618
1619 switch (code) {
1620 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1621 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1622 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1623 default: ShouldNotReachHere();
1624 }
1625 } else {
1626 assert (right->is_single_cpu(), "Just Checking");
1627
1628 Register lreg = left->as_register();
1629 Register res = dest->as_register();
1630 Register rreg = right->as_register();
1631 switch (code) {
1632 case lir_add: __ add (res, lreg, rreg); break;
1633 case lir_sub: __ sub (res, lreg, rreg); break;
1634 case lir_mul: __ mullw(res, lreg, rreg); break;
1635 default: ShouldNotReachHere();
1636 }
1637 }
1638 } else {
1639 assert (right->is_constant(), "must be constant");
1640
1641 if (dest->is_single_cpu()) {
1642 Register lreg = left->as_register();
1643 Register res = dest->as_register();
1644 int simm16 = right->as_constant_ptr()->as_jint();
1645
1646 switch (code) {
1647 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1648 simm16 = -simm16;
1649 case lir_add: if (res == lreg && simm16 == 0) break;
1650 __ addi(res, lreg, simm16); break;
1651 case lir_mul: if (res == lreg && simm16 == 1) break;
1652 __ mulli(res, lreg, simm16); break;
1653 default: ShouldNotReachHere();
1654 }
1655 } else {
1656 Register lreg = left->as_pointer_register();
1657 Register res = dest->as_register_lo();
1658 long con = right->as_constant_ptr()->as_jlong();
1659 assert(Assembler::is_simm16(con), "must be simm16");
1660
1661 switch (code) {
1662 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1663 con = -con;
1664 case lir_add: if (res == lreg && con == 0) break;
1665 __ addi(res, lreg, (int)con); break;
1666 case lir_mul: if (res == lreg && con == 1) break;
1667 __ mulli(res, lreg, (int)con); break;
1668 default: ShouldNotReachHere();
1669 }
1670 }
1671 }
1672 }
1673
1674
1675 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1676 switch (code) {
1677 case lir_sqrt: {
1678 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1679 break;
1680 }
1681 case lir_abs: {
1682 __ fabs(dest->as_double_reg(), value->as_double_reg());
1683 break;
1684 }
1685 case lir_f2hf: {
1686 __ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1687 break;
1688 }
1689 case lir_hf2f: {
1690 __ hf2f(dest->as_float_reg(), value.as_register());
1691 break;
1692 }
1693 default: {
1694 ShouldNotReachHere();
1695 break;
1696 }
1697 }
1698 }
1699
1700
1701 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1702 if (right->is_constant()) { // see do_LogicOp
1703 long uimm;
1704 Register d, l;
1705 if (dest->is_single_cpu()) {
1706 uimm = right->as_constant_ptr()->as_jint();
1707 d = dest->as_register();
1708 l = left->as_register();
1709 } else {
1710 uimm = right->as_constant_ptr()->as_jlong();
1711 d = dest->as_register_lo();
1712 l = left->as_register_lo();
1713 }
1714 long uimms = (unsigned long)uimm >> 16,
1715 uimmss = (unsigned long)uimm >> 32;
1716
1717 switch (code) {
1718 case lir_logic_and:
1719 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1720 __ andi(d, l, uimm); // special cases
1721 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1722 else { __ andi_(d, l, uimm); }
1723 break;
1724
1725 case lir_logic_or:
1726 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1727 else { __ ori(d, l, uimm); }
1728 break;
1729
1730 case lir_logic_xor:
1731 if (uimm == -1) { __ nand(d, l, l); } // special case
1732 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1733 else { __ xori(d, l, uimm); }
1734 break;
1735
1736 default: ShouldNotReachHere();
1737 }
1738 } else {
1739 assert(right->is_register(), "right should be in register");
1740
1741 if (dest->is_single_cpu()) {
1742 switch (code) {
1743 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1744 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1745 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1746 default: ShouldNotReachHere();
1747 }
1748 } else {
1749 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1750 left->as_register_lo();
1751 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1752 right->as_register_lo();
1753
1754 switch (code) {
1755 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1756 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1757 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1758 default: ShouldNotReachHere();
1759 }
1760 }
1761 }
1762 }
1763
1764
1765 int LIR_Assembler::shift_amount(BasicType t) {
1766 int elem_size = type2aelembytes(t);
1767 switch (elem_size) {
1768 case 1 : return 0;
1769 case 2 : return 1;
1770 case 4 : return 2;
1771 case 8 : return 3;
1772 }
1773 ShouldNotReachHere();
1774 return -1;
1775 }
1776
1777
1778 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1779 info->add_register_oop(exceptionOop);
1780
1781 // Reuse the debug info from the safepoint poll for the throw op itself.
1782 address pc_for_athrow = __ pc();
1783 int pc_for_athrow_offset = __ offset();
1784 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1785 //__ relocate(rspec);
1786 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1787 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1788 add_call_info(pc_for_athrow_offset, info); // for exception handler
1789
1790 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1791 : StubId::c1_handle_exception_nofpu_id);
1792 //__ load_const_optimized(R0, stub);
1793 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1794 __ mtctr(R0);
1795 __ bctr();
1796 }
1797
1798
1799 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1800 // Note: Not used with EnableDebuggingOnDemand.
1801 assert(exceptionOop->as_register() == R3, "should match");
1802 __ b(_unwind_handler_entry);
1803 }
1804
1805
1806 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1807 Register src = op->src()->as_register();
1808 Register dst = op->dst()->as_register();
1809 Register src_pos = op->src_pos()->as_register();
1810 Register dst_pos = op->dst_pos()->as_register();
1811 Register length = op->length()->as_register();
1812 Register tmp = op->tmp()->as_register();
1813 Register tmp2 = R0;
1814
1815 int flags = op->flags();
1816 ciArrayKlass* default_type = op->expected_type();
1817 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1818 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1819
1820 // Set up the arraycopy stub information.
1821 ArrayCopyStub* stub = op->stub();
1822
1823 // Always do stub if no type information is available. It's ok if
1824 // the known type isn't loaded since the code sanity checks
1825 // in debug mode and the type isn't required when we know the exact type
1826 // also check that the type is an array type.
1827 if (default_type == nullptr) {
1828 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1829 length->is_nonvolatile(), "must preserve");
1830 address copyfunc_addr = StubRoutines::generic_arraycopy();
1831 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1832
1833 // 3 parms are int. Convert to long.
1834 __ mr(R3_ARG1, src);
1835 __ extsw(R4_ARG2, src_pos);
1836 __ mr(R5_ARG3, dst);
1837 __ extsw(R6_ARG4, dst_pos);
1838 __ extsw(R7_ARG5, length);
1839
1840 #ifndef PRODUCT
1841 if (PrintC1Statistics) {
1842 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1843 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1844 __ lwz(R11_scratch1, simm16_offs, tmp);
1845 __ addi(R11_scratch1, R11_scratch1, 1);
1846 __ stw(R11_scratch1, simm16_offs, tmp);
1847 }
1848 #endif
1849 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1850
1851 __ nand(tmp, R3_RET, R3_RET);
1852 __ subf(length, tmp, length);
1853 __ add(src_pos, tmp, src_pos);
1854 __ add(dst_pos, tmp, dst_pos);
1855
1856 __ cmpwi(CR0, R3_RET, 0);
1857 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CR0, Assembler::less), *stub->entry());
1858 __ bind(*stub->continuation());
1859 return;
1860 }
1861
1862 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1863 Label cont, slow, copyfunc;
1864
1865 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1866 LIR_OpArrayCopy::dst_null_check |
1867 LIR_OpArrayCopy::src_pos_positive_check |
1868 LIR_OpArrayCopy::dst_pos_positive_check |
1869 LIR_OpArrayCopy::length_positive_check);
1870
1871 // Use only one conditional branch for simple checks.
1872 if (simple_check_flag_set) {
1873 ConditionRegister combined_check = CR1, tmp_check = CR1;
1874
1875 // Make sure src and dst are non-null.
1876 if (flags & LIR_OpArrayCopy::src_null_check) {
1877 __ cmpdi(combined_check, src, 0);
1878 tmp_check = CR0;
1879 }
1880
1881 if (flags & LIR_OpArrayCopy::dst_null_check) {
1882 __ cmpdi(tmp_check, dst, 0);
1883 if (tmp_check != combined_check) {
1884 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1885 }
1886 tmp_check = CR0;
1887 }
1888
1889 // Clear combined_check.eq if not already used.
1890 if (tmp_check == combined_check) {
1891 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1892 tmp_check = CR0;
1893 }
1894
1895 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1896 // Test src_pos register.
1897 __ cmpwi(tmp_check, src_pos, 0);
1898 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1899 }
1900
1901 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1902 // Test dst_pos register.
1903 __ cmpwi(tmp_check, dst_pos, 0);
1904 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1905 }
1906
1907 if (flags & LIR_OpArrayCopy::length_positive_check) {
1908 // Make sure length isn't negative.
1909 __ cmpwi(tmp_check, length, 0);
1910 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1911 }
1912
1913 __ beq(combined_check, slow);
1914 }
1915
1916 // If the compiler was not able to prove that exact type of the source or the destination
1917 // of the arraycopy is an array type, check at runtime if the source or the destination is
1918 // an instance type.
1919 if (flags & LIR_OpArrayCopy::type_check) {
1920 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1921 __ load_klass(tmp, dst);
1922 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1923 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1924 __ bge(CR0, slow);
1925 }
1926
1927 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1928 __ load_klass(tmp, src);
1929 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1930 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1931 __ bge(CR0, slow);
1932 }
1933 }
1934
1935 // Higher 32bits must be null.
1936 __ extsw(length, length);
1937
1938 __ extsw(src_pos, src_pos);
1939 if (flags & LIR_OpArrayCopy::src_range_check) {
1940 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1941 __ add(tmp, length, src_pos);
1942 __ cmpld(CR0, tmp2, tmp);
1943 __ ble(CR0, slow);
1944 }
1945
1946 __ extsw(dst_pos, dst_pos);
1947 if (flags & LIR_OpArrayCopy::dst_range_check) {
1948 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1949 __ add(tmp, length, dst_pos);
1950 __ cmpld(CR0, tmp2, tmp);
1951 __ ble(CR0, slow);
1952 }
1953
1954 int shift = shift_amount(basic_type);
1955
1956 if (!(flags & LIR_OpArrayCopy::type_check)) {
1957 if (stub != nullptr) {
1958 __ b(cont);
1959 __ bind(slow);
1960 __ b(*stub->entry());
1961 }
1962 } else {
1963 // We don't know the array types are compatible.
1964 if (basic_type != T_OBJECT) {
1965 // Simple test for basic type arrays.
1966 __ cmp_klasses_from_objects(CR0, src, dst, tmp, tmp2);
1967 __ beq(CR0, cont);
1968 } else {
1969 // For object arrays, if src is a sub class of dst then we can
1970 // safely do the copy.
1971 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1972
1973 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1974 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1975
1976 __ load_klass(sub_klass, src);
1977 __ load_klass(super_klass, dst);
1978
1979 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1980 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
1981
1982 address slow_stc = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
1983 //__ load_const_optimized(tmp, slow_stc, tmp2);
1984 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1985 __ mtctr(tmp);
1986 __ bctrl(); // sets CR0
1987 __ beq(CR0, cont);
1988
1989 if (copyfunc_addr != nullptr) { // Use stub if available.
1990 __ bind(copyfunc);
1991 // Src is not a sub class of dst so we have to do a
1992 // per-element check.
1993 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1994 if ((flags & mask) != mask) {
1995 assert(flags & mask, "one of the two should be known to be an object array");
1996
1997 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1998 __ load_klass(tmp, src);
1999 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2000 __ load_klass(tmp, dst);
2001 }
2002
2003 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2004
2005 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2006 __ load_const_optimized(tmp, objArray_lh);
2007 __ cmpw(CR0, tmp, tmp2);
2008 __ bne(CR0, slow);
2009 }
2010
2011 Register src_ptr = R3_ARG1;
2012 Register dst_ptr = R4_ARG2;
2013 Register len = R5_ARG3;
2014 Register chk_off = R6_ARG4;
2015 Register super_k = R7_ARG5;
2016
2017 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2018 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2019 if (shift == 0) {
2020 __ add(src_ptr, src_pos, src_ptr);
2021 __ add(dst_ptr, dst_pos, dst_ptr);
2022 } else {
2023 __ sldi(tmp, src_pos, shift);
2024 __ sldi(tmp2, dst_pos, shift);
2025 __ add(src_ptr, tmp, src_ptr);
2026 __ add(dst_ptr, tmp2, dst_ptr);
2027 }
2028
2029 __ load_klass(tmp, dst);
2030 __ mr(len, length);
2031
2032 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2033 __ ld(super_k, ek_offset, tmp);
2034
2035 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2036 __ lwz(chk_off, sco_offset, super_k);
2037
2038 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2039
2040 #ifndef PRODUCT
2041 if (PrintC1Statistics) {
2042 Label failed;
2043 __ cmpwi(CR0, R3_RET, 0);
2044 __ bne(CR0, failed);
2045 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2046 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2047 __ lwz(R11_scratch1, simm16_offs, tmp);
2048 __ addi(R11_scratch1, R11_scratch1, 1);
2049 __ stw(R11_scratch1, simm16_offs, tmp);
2050 __ bind(failed);
2051 }
2052 #endif
2053
2054 __ nand(tmp, R3_RET, R3_RET);
2055 __ cmpwi(CR0, R3_RET, 0);
2056 __ beq(CR0, *stub->continuation());
2057
2058 #ifndef PRODUCT
2059 if (PrintC1Statistics) {
2060 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2061 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2062 __ lwz(R11_scratch1, simm16_offs, tmp);
2063 __ addi(R11_scratch1, R11_scratch1, 1);
2064 __ stw(R11_scratch1, simm16_offs, tmp);
2065 }
2066 #endif
2067
2068 __ subf(length, tmp, length);
2069 __ add(src_pos, tmp, src_pos);
2070 __ add(dst_pos, tmp, dst_pos);
2071 }
2072 }
2073 __ bind(slow);
2074 __ b(*stub->entry());
2075 }
2076 __ bind(cont);
2077
2078 #ifdef ASSERT
2079 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2080 // Sanity check the known type with the incoming class. For the
2081 // primitive case the types must match exactly with src.klass and
2082 // dst.klass each exactly matching the default type. For the
2083 // object array case, if no type check is needed then either the
2084 // dst type is exactly the expected type and the src type is a
2085 // subtype which we can't check or src is the same array as dst
2086 // but not necessarily exactly of type default_type.
2087 Label known_ok, halt;
2088 metadata2reg(default_type->constant_encoding(), tmp);
2089 __ cmp_klass(CR0, dst, tmp, R11_scratch1, R12_scratch2);
2090 if (basic_type != T_OBJECT) {
2091 __ bne(CR0, halt);
2092 __ cmp_klass(CR0, src, tmp, R11_scratch1, R12_scratch2);
2093 __ beq(CR0, known_ok);
2094 } else {
2095 __ beq(CR0, known_ok);
2096 __ cmpw(CR0, src, dst);
2097 __ beq(CR0, known_ok);
2098 }
2099 __ bind(halt);
2100 __ stop("incorrect type information in arraycopy");
2101 __ bind(known_ok);
2102 }
2103 #endif
2104
2105 #ifndef PRODUCT
2106 if (PrintC1Statistics) {
2107 address counter = Runtime1::arraycopy_count_address(basic_type);
2108 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2109 __ lwz(R11_scratch1, simm16_offs, tmp);
2110 __ addi(R11_scratch1, R11_scratch1, 1);
2111 __ stw(R11_scratch1, simm16_offs, tmp);
2112 }
2113 #endif
2114
2115 Register src_ptr = R3_ARG1;
2116 Register dst_ptr = R4_ARG2;
2117 Register len = R5_ARG3;
2118
2119 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2120 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2121 if (shift == 0) {
2122 __ add(src_ptr, src_pos, src_ptr);
2123 __ add(dst_ptr, dst_pos, dst_ptr);
2124 } else {
2125 __ sldi(tmp, src_pos, shift);
2126 __ sldi(tmp2, dst_pos, shift);
2127 __ add(src_ptr, tmp, src_ptr);
2128 __ add(dst_ptr, tmp2, dst_ptr);
2129 }
2130
2131 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2132 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2133 const char *name;
2134 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2135
2136 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2137 __ mr(len, length);
2138 __ call_c(entry, relocInfo::runtime_call_type);
2139
2140 if (stub != nullptr) {
2141 __ bind(*stub->continuation());
2142 }
2143 }
2144
2145
2146 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2147 if (dest->is_single_cpu()) {
2148 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2149 #ifdef _LP64
2150 if (left->type() == T_OBJECT) {
2151 switch (code) {
2152 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2153 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2154 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2155 default: ShouldNotReachHere();
2156 }
2157 } else
2158 #endif
2159 switch (code) {
2160 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2161 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2162 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2163 default: ShouldNotReachHere();
2164 }
2165 } else {
2166 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2167 switch (code) {
2168 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2169 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2170 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2171 default: ShouldNotReachHere();
2172 }
2173 }
2174 }
2175
2176
2177 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2178 #ifdef _LP64
2179 if (left->type() == T_OBJECT) {
2180 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2181 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2182 else {
2183 switch (code) {
2184 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2185 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2186 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2187 default: ShouldNotReachHere();
2188 }
2189 }
2190 return;
2191 }
2192 #endif
2193
2194 if (dest->is_single_cpu()) {
2195 count = count & 0x1F; // Java spec
2196 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2197 else {
2198 switch (code) {
2199 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2200 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2201 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2202 default: ShouldNotReachHere();
2203 }
2204 }
2205 } else if (dest->is_double_cpu()) {
2206 count = count & 63; // Java spec
2207 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2208 else {
2209 switch (code) {
2210 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2211 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2212 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2213 default: ShouldNotReachHere();
2214 }
2215 }
2216 } else {
2217 ShouldNotReachHere();
2218 }
2219 }
2220
2221
2222 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2223 if (op->init_check()) {
2224 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2225 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2226 } else {
2227 add_debug_info_for_null_check_here(op->stub()->info());
2228 }
2229 __ lbz(op->tmp1()->as_register(),
2230 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2231 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2232 __ cmpwi(CR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2233 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CR0, Assembler::equal), *op->stub()->entry());
2234 }
2235 __ allocate_object(op->obj()->as_register(),
2236 op->tmp1()->as_register(),
2237 op->tmp2()->as_register(),
2238 op->tmp3()->as_register(),
2239 op->header_size(),
2240 op->object_size(),
2241 op->klass()->as_register(),
2242 *op->stub()->entry());
2243
2244 __ bind(*op->stub()->continuation());
2245 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2246 }
2247
2248
2249 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2250 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2251 if (UseSlowPath ||
2252 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2253 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2254 __ b(*op->stub()->entry());
2255 } else {
2256 __ allocate_array(op->obj()->as_register(),
2257 op->len()->as_register(),
2258 op->tmp1()->as_register(),
2259 op->tmp2()->as_register(),
2260 op->tmp3()->as_register(),
2261 arrayOopDesc::base_offset_in_bytes(op->type()),
2262 type2aelembytes(op->type()),
2263 op->klass()->as_register(),
2264 *op->stub()->entry(),
2265 op->zero_array());
2266 }
2267 __ bind(*op->stub()->continuation());
2268 }
2269
2270
2271 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2272 ciMethodData *md, ciProfileData *data,
2273 Register recv, Register tmp1, Label* update_done) {
2274 uint i;
2275 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2276 Label next_test;
2277 // See if the receiver is receiver[n].
2278 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2279 __ verify_klass_ptr(tmp1);
2280 __ cmpd(CR0, recv, tmp1);
2281 __ bne(CR0, next_test);
2282
2283 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2284 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2285 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2286 __ b(*update_done);
2287
2288 __ bind(next_test);
2289 }
2290
2291 // Didn't find receiver; find next empty slot and fill it in.
2292 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2293 Label next_test;
2294 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2295 __ cmpdi(CR0, tmp1, 0);
2296 __ bne(CR0, next_test);
2297 __ li(tmp1, DataLayout::counter_increment);
2298 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2299 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2300 __ b(*update_done);
2301
2302 __ bind(next_test);
2303 }
2304 }
2305
2306
2307 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2308 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2309 md = method->method_data_or_null();
2310 assert(md != nullptr, "Sanity");
2311 data = md->bci_to_data(bci);
2312 assert(data != nullptr, "need data for checkcast");
2313 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2314 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2315 // The offset is large so bias the mdo by the base of the slot so
2316 // that the ld can use simm16s to reference the slots of the data.
2317 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2318 }
2319 }
2320
2321
2322 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2323 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2324 Register k_RInfo = op->tmp1()->as_register();
2325 Register klass_RInfo = op->tmp2()->as_register();
2326 Register Rtmp1 = op->tmp3()->as_register();
2327 Register dst = op->result_opr()->as_register();
2328 ciKlass* k = op->klass();
2329 bool should_profile = op->should_profile();
2330 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2331 bool reg_conflict = false;
2332 if (obj == k_RInfo) {
2333 k_RInfo = dst;
2334 reg_conflict = true;
2335 } else if (obj == klass_RInfo) {
2336 klass_RInfo = dst;
2337 reg_conflict = true;
2338 } else if (obj == Rtmp1) {
2339 Rtmp1 = dst;
2340 reg_conflict = true;
2341 }
2342 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2343
2344 ciMethodData* md = nullptr;
2345 ciProfileData* data = nullptr;
2346 int mdo_offset_bias = 0;
2347 if (should_profile) {
2348 ciMethod* method = op->profiled_method();
2349 assert(method != nullptr, "Should have method");
2350 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2351
2352 Register mdo = k_RInfo;
2353 Register data_val = Rtmp1;
2354 Label not_null;
2355 metadata2reg(md->constant_encoding(), mdo);
2356 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2357 __ cmpdi(CR0, obj, 0);
2358 __ bne(CR0, not_null);
2359 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2360 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2361 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2362 __ b(*obj_is_null);
2363 __ bind(not_null);
2364
2365 Label update_done;
2366 Register recv = klass_RInfo;
2367 __ load_klass(recv, obj);
2368 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2369 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2370 __ ld(Rtmp1, slot_offset, mdo);
2371 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2372 __ std(Rtmp1, slot_offset, mdo);
2373 __ bind(update_done);
2374 } else {
2375 __ cmpdi(CR0, obj, 0);
2376 __ beq(CR0, *obj_is_null);
2377 }
2378
2379 // get object class
2380 __ load_klass(klass_RInfo, obj);
2381
2382 if (k->is_loaded()) {
2383 metadata2reg(k->constant_encoding(), k_RInfo);
2384 } else {
2385 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2386 }
2387
2388 if (op->fast_check()) {
2389 assert_different_registers(klass_RInfo, k_RInfo);
2390 __ cmpd(CR0, k_RInfo, klass_RInfo);
2391 __ beq(CR0, *success);
2392 // Fall through to failure case.
2393 } else {
2394 bool need_slow_path = true;
2395 if (k->is_loaded()) {
2396 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2397 need_slow_path = false;
2398 }
2399 // Perform the fast part of the checking logic.
2400 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2401 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2402 } else {
2403 // Perform the fast part of the checking logic.
2404 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2405 }
2406 if (!need_slow_path) {
2407 __ b(*success);
2408 } else {
2409 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2410 address entry = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2411 // Stub needs fixed registers (tmp1-3).
2412 Register original_k_RInfo = op->tmp1()->as_register();
2413 Register original_klass_RInfo = op->tmp2()->as_register();
2414 Register original_Rtmp1 = op->tmp3()->as_register();
2415 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2416 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2417 __ mr_if_needed(original_k_RInfo, k_RInfo);
2418 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2419 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2420 //__ load_const_optimized(original_Rtmp1, entry, R0);
2421 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2422 __ mtctr(original_Rtmp1);
2423 __ bctrl(); // sets CR0
2424 if (keep_obj_alive) { __ mr(obj, dst); }
2425 __ beq(CR0, *success);
2426 // Fall through to failure case.
2427 }
2428 }
2429
2430 __ bind(*failure);
2431 }
2432
2433
2434 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2435 LIR_Code code = op->code();
2436 if (code == lir_store_check) {
2437 Register value = op->object()->as_register();
2438 Register array = op->array()->as_register();
2439 Register k_RInfo = op->tmp1()->as_register();
2440 Register klass_RInfo = op->tmp2()->as_register();
2441 Register Rtmp1 = op->tmp3()->as_register();
2442 bool should_profile = op->should_profile();
2443
2444 __ verify_oop(value, FILE_AND_LINE);
2445 CodeStub* stub = op->stub();
2446 // Check if it needs to be profiled.
2447 ciMethodData* md = nullptr;
2448 ciProfileData* data = nullptr;
2449 int mdo_offset_bias = 0;
2450 if (should_profile) {
2451 ciMethod* method = op->profiled_method();
2452 assert(method != nullptr, "Should have method");
2453 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2454 }
2455
2456 Label done;
2457
2458 if (should_profile) {
2459 Label not_null;
2460 Register mdo = k_RInfo;
2461 Register data_val = Rtmp1;
2462 metadata2reg(md->constant_encoding(), mdo);
2463 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2464 __ cmpdi(CR0, value, 0);
2465 __ bne(CR0, not_null);
2466 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2467 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2468 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2469 __ b(done);
2470 __ bind(not_null);
2471
2472 Label update_done;
2473 Register recv = klass_RInfo;
2474 __ load_klass(recv, value);
2475 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2476 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2477 __ ld(Rtmp1, slot_offset, mdo);
2478 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2479 __ std(Rtmp1, slot_offset, mdo);
2480 __ bind(update_done);
2481 } else {
2482 __ cmpdi(CR0, value, 0);
2483 __ beq(CR0, done);
2484 }
2485 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2486 explicit_null_check(array, op->info_for_exception());
2487 } else {
2488 add_debug_info_for_null_check_here(op->info_for_exception());
2489 }
2490 __ load_klass(k_RInfo, array);
2491 __ load_klass(klass_RInfo, value);
2492
2493 Label failure;
2494
2495 // Get instance klass.
2496 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2497 // Perform the fast part of the checking logic.
2498 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2499
2500 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2501 const address slow_path = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2502 //__ load_const_optimized(R0, slow_path);
2503 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2504 __ mtctr(R0);
2505 __ bctrl(); // sets CR0
2506 __ beq(CR0, done);
2507
2508 __ bind(failure);
2509 __ b(*stub->entry());
2510 __ align(32, 12);
2511 __ bind(done);
2512
2513 } else if (code == lir_checkcast) {
2514 Label success, failure;
2515 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2516 __ b(*op->stub()->entry());
2517 __ align(32, 12);
2518 __ bind(success);
2519 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2520 } else if (code == lir_instanceof) {
2521 Register dst = op->result_opr()->as_register();
2522 Label success, failure, done;
2523 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2524 __ li(dst, 0);
2525 __ b(done);
2526 __ align(32, 12);
2527 __ bind(success);
2528 __ li(dst, 1);
2529 __ bind(done);
2530 } else {
2531 ShouldNotReachHere();
2532 }
2533 }
2534
2535
2536 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2537 Register addr = op->addr()->as_pointer_register();
2538 Register cmp_value = noreg, new_value = noreg;
2539 bool is_64bit = false;
2540
2541 if (op->code() == lir_cas_long) {
2542 cmp_value = op->cmp_value()->as_register_lo();
2543 new_value = op->new_value()->as_register_lo();
2544 is_64bit = true;
2545 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2546 cmp_value = op->cmp_value()->as_register();
2547 new_value = op->new_value()->as_register();
2548 if (op->code() == lir_cas_obj) {
2549 if (UseCompressedOops) {
2550 Register t1 = op->tmp1()->as_register();
2551 Register t2 = op->tmp2()->as_register();
2552 cmp_value = __ encode_heap_oop(t1, cmp_value);
2553 new_value = __ encode_heap_oop(t2, new_value);
2554 } else {
2555 is_64bit = true;
2556 }
2557 }
2558 } else {
2559 Unimplemented();
2560 }
2561
2562 // There might be a volatile load before this Unsafe CAS.
2563 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2564 __ sync();
2565 } else {
2566 __ lwsync();
2567 }
2568
2569 if (is_64bit) {
2570 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2571 MacroAssembler::MemBarNone,
2572 MacroAssembler::cmpxchgx_hint_atomic_update(),
2573 noreg, nullptr, /*check without ldarx first*/true);
2574 } else {
2575 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2576 MacroAssembler::MemBarNone,
2577 MacroAssembler::cmpxchgx_hint_atomic_update(),
2578 noreg, nullptr, /*check without ldarx first*/true);
2579 }
2580
2581 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2582 __ isync();
2583 } else {
2584 __ sync();
2585 }
2586 }
2587
2588 void LIR_Assembler::breakpoint() {
2589 __ illtrap();
2590 }
2591
2592
2593 void LIR_Assembler::push(LIR_Opr opr) {
2594 Unimplemented();
2595 }
2596
2597 void LIR_Assembler::pop(LIR_Opr opr) {
2598 Unimplemented();
2599 }
2600
2601
2602 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2603 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2604 Register dst = dst_opr->as_register();
2605 Register reg = mon_addr.base();
2606 int offset = mon_addr.disp();
2607 // Compute pointer to BasicLock.
2608 __ add_const_optimized(dst, reg, offset);
2609 }
2610
2611
2612 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2613 Register obj = op->obj_opr()->as_register();
2614 Register hdr = op->hdr_opr()->as_register();
2615 Register lock = op->lock_opr()->as_register();
2616
2617 // Obj may not be an oop.
2618 if (op->code() == lir_lock) {
2619 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2620 // Add debug info for NullPointerException only if one is possible.
2621 if (op->info() != nullptr) {
2622 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2623 explicit_null_check(obj, op->info());
2624 } else {
2625 add_debug_info_for_null_check_here(op->info());
2626 }
2627 }
2628 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2629 } else {
2630 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2631 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2632 }
2633 __ bind(*op->stub()->continuation());
2634 }
2635
2636 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2637 Register obj = op->obj()->as_pointer_register();
2638 Register result = op->result_opr()->as_pointer_register();
2639
2640 CodeEmitInfo* info = op->info();
2641 if (info != nullptr) {
2642 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2643 explicit_null_check(obj, info);
2644 } else {
2645 add_debug_info_for_null_check_here(info);
2646 }
2647 }
2648
2649 __ load_klass(result, obj);
2650 }
2651
2652 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2653 ciMethod* method = op->profiled_method();
2654 int bci = op->profiled_bci();
2655 ciMethod* callee = op->profiled_callee();
2656
2657 // Update counter for all call types.
2658 ciMethodData* md = method->method_data_or_null();
2659 assert(md != nullptr, "Sanity");
2660 ciProfileData* data = md->bci_to_data(bci);
2661 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2662 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2663 Register mdo = op->mdo()->as_register();
2664 #ifdef _LP64
2665 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2666 Register tmp1 = op->tmp1()->as_register_lo();
2667 #else
2668 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2669 Register tmp1 = op->tmp1()->as_register();
2670 #endif
2671 metadata2reg(md->constant_encoding(), mdo);
2672 int mdo_offset_bias = 0;
2673 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2674 data->size_in_bytes())) {
2675 // The offset is large so bias the mdo by the base of the slot so
2676 // that the ld can use simm16s to reference the slots of the data.
2677 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2678 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2679 }
2680
2681 // Perform additional virtual call profiling for invokevirtual and
2682 // invokeinterface bytecodes
2683 if (op->should_profile_receiver_type()) {
2684 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2685 Register recv = op->recv()->as_register();
2686 assert_different_registers(mdo, tmp1, recv);
2687 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2688 ciKlass* known_klass = op->known_holder();
2689 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2690 // We know the type that will be seen at this call site; we can
2691 // statically update the MethodData* rather than needing to do
2692 // dynamic tests on the receiver type.
2693
2694 // NOTE: we should probably put a lock around this search to
2695 // avoid collisions by concurrent compilations.
2696 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2697 uint i;
2698 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2699 ciKlass* receiver = vc_data->receiver(i);
2700 if (known_klass->equals(receiver)) {
2701 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2702 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2703 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2704 return;
2705 }
2706 }
2707
2708 // Receiver type not found in profile data; select an empty slot.
2709
2710 // Note that this is less efficient than it should be because it
2711 // always does a write to the receiver part of the
2712 // VirtualCallData rather than just the first time.
2713 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2714 ciKlass* receiver = vc_data->receiver(i);
2715 if (receiver == nullptr) {
2716 metadata2reg(known_klass->constant_encoding(), tmp1);
2717 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2718
2719 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2720 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2721 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2722 return;
2723 }
2724 }
2725 } else {
2726 __ load_klass(recv, recv);
2727 Label update_done;
2728 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2729 // Receiver did not match any saved receiver and there is no empty row for it.
2730 // Increment total counter to indicate polymorphic case.
2731 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2732 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2733 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2734
2735 __ bind(update_done);
2736 }
2737 } else {
2738 // Static call
2739 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2740 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2741 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2742 }
2743 }
2744
2745
2746 void LIR_Assembler::align_backward_branch_target() {
2747 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2748 }
2749
2750
2751 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2752 // tmp must be unused
2753 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2754 assert(left->is_register(), "can only handle registers");
2755
2756 if (left->is_single_cpu()) {
2757 __ neg(dest->as_register(), left->as_register());
2758 } else if (left->is_single_fpu()) {
2759 __ fneg(dest->as_float_reg(), left->as_float_reg());
2760 } else if (left->is_double_fpu()) {
2761 __ fneg(dest->as_double_reg(), left->as_double_reg());
2762 } else {
2763 assert (left->is_double_cpu(), "Must be a long");
2764 __ neg(dest->as_register_lo(), left->as_register_lo());
2765 }
2766 }
2767
2768
2769 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2770 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2771 // Stubs: Called via rt_call, but dest is a stub address (no FunctionDescriptor).
2772 if (dest == Runtime1::entry_for(StubId::c1_register_finalizer_id) ||
2773 dest == Runtime1::entry_for(StubId::c1_new_multi_array_id ) ||
2774 dest == Runtime1::entry_for(StubId::c1_is_instance_of_id )) {
2775 assert(CodeCache::contains(dest), "simplified call is only for special C1 stubs");
2776 //__ load_const_optimized(R0, dest);
2777 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2778 __ mtctr(R0);
2779 __ bctrl();
2780 if (info != nullptr) {
2781 add_call_info_here(info);
2782 __ post_call_nop();
2783 }
2784 return;
2785 }
2786
2787 __ call_c(dest, relocInfo::runtime_call_type);
2788 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2789 if (info != nullptr) {
2790 add_call_info_here(info);
2791 __ post_call_nop();
2792 }
2793 }
2794
2795
2796 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2797 ShouldNotReachHere(); // Not needed on _LP64.
2798 }
2799
2800 void LIR_Assembler::membar() {
2801 __ fence();
2802 }
2803
2804 void LIR_Assembler::membar_acquire() {
2805 __ acquire();
2806 }
2807
2808 void LIR_Assembler::membar_release() {
2809 __ release();
2810 }
2811
2812 void LIR_Assembler::membar_loadload() {
2813 __ membar(Assembler::LoadLoad);
2814 }
2815
2816 void LIR_Assembler::membar_storestore() {
2817 __ membar(Assembler::StoreStore);
2818 }
2819
2820 void LIR_Assembler::membar_loadstore() {
2821 __ membar(Assembler::LoadStore);
2822 }
2823
2824 void LIR_Assembler::membar_storeload() {
2825 __ membar(Assembler::StoreLoad);
2826 }
2827
2828 void LIR_Assembler::on_spin_wait() {
2829 Unimplemented();
2830 }
2831
2832 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2833 LIR_Address* addr = addr_opr->as_address_ptr();
2834 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2835
2836 if (addr->index()->is_illegal()) {
2837 if (patch_code != lir_patch_none) {
2838 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2839 __ load_const32(R0, 0); // patchable int
2840 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2841 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2842 } else {
2843 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2844 }
2845 } else {
2846 assert(patch_code == lir_patch_none, "Patch code not supported");
2847 assert(addr->disp() == 0, "can't have both: index and disp");
2848 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2849 }
2850 }
2851
2852
2853 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2854 ShouldNotReachHere();
2855 }
2856
2857
2858 #ifdef ASSERT
2859 // Emit run-time assertion.
2860 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2861 Unimplemented();
2862 }
2863 #endif
2864
2865
2866 void LIR_Assembler::peephole(LIR_List* lir) {
2867 // Optimize instruction pairs before emitting.
2868 LIR_OpList* inst = lir->instructions_list();
2869 for (int i = 1; i < inst->length(); i++) {
2870 LIR_Op* op = inst->at(i);
2871
2872 // 2 register-register-moves
2873 if (op->code() == lir_move) {
2874 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2875 res2 = ((LIR_Op1*)op)->result_opr();
2876 if (in2->is_register() && res2->is_register()) {
2877 LIR_Op* prev = inst->at(i - 1);
2878 if (prev && prev->code() == lir_move) {
2879 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2880 res1 = ((LIR_Op1*)prev)->result_opr();
2881 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2882 inst->remove_at(i);
2883 }
2884 }
2885 }
2886 }
2887
2888 }
2889 return;
2890 }
2891
2892
2893 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2894 const LIR_Address *addr = src->as_address_ptr();
2895 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2896 const Register Rptr = addr->base()->as_pointer_register(),
2897 Rtmp = tmp->as_register();
2898 Register Robj = noreg;
2899 if (data->is_oop()) {
2900 if (UseCompressedOops) {
2901 Robj = __ encode_heap_oop(Rtmp, data->as_register());
2902 } else {
2903 Robj = data->as_register();
2904 if (Robj == dest->as_register()) { // May happen with ZGC.
2905 __ mr(Rtmp, Robj);
2906 Robj = Rtmp;
2907 }
2908 }
2909 }
2910
2911 // There might be a volatile load before this Unsafe OP.
2912 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2913 __ sync();
2914 } else {
2915 __ lwsync();
2916 }
2917
2918 Label Lretry;
2919 __ bind(Lretry);
2920
2921 if (data->type() == T_INT) {
2922 const Register Rold = dest->as_register(),
2923 Rsrc = data->as_register();
2924 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2925 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2926 if (code == lir_xadd) {
2927 __ add(Rtmp, Rsrc, Rold);
2928 __ stwcx_(Rtmp, Rptr);
2929 } else {
2930 __ stwcx_(Rsrc, Rptr);
2931 }
2932 } else if (data->is_oop()) {
2933 assert(code == lir_xchg, "xadd for oops");
2934 const Register Rold = dest->as_register();
2935 assert_different_registers(Rptr, Rold, Robj);
2936 if (UseCompressedOops) {
2937 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2938 __ stwcx_(Robj, Rptr);
2939 } else {
2940 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2941 __ stdcx_(Robj, Rptr);
2942 }
2943 } else if (data->type() == T_LONG) {
2944 const Register Rold = dest->as_register_lo(),
2945 Rsrc = data->as_register_lo();
2946 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2947 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2948 if (code == lir_xadd) {
2949 __ add(Rtmp, Rsrc, Rold);
2950 __ stdcx_(Rtmp, Rptr);
2951 } else {
2952 __ stdcx_(Rsrc, Rptr);
2953 }
2954 } else {
2955 ShouldNotReachHere();
2956 }
2957
2958 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2959 __ bne_predict_not_taken(CR0, Lretry);
2960 } else {
2961 __ bne( CR0, Lretry);
2962 }
2963
2964 if (UseCompressedOops && data->is_oop()) {
2965 __ decode_heap_oop(dest->as_register());
2966 }
2967
2968 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2969 __ isync();
2970 } else {
2971 __ sync();
2972 }
2973 }
2974
2975
2976 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2977 Register obj = op->obj()->as_register();
2978 Register tmp = op->tmp()->as_pointer_register();
2979 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
2980 ciKlass* exact_klass = op->exact_klass();
2981 intptr_t current_klass = op->current_klass();
2982 bool not_null = op->not_null();
2983 bool no_conflict = op->no_conflict();
2984
2985 Label Lupdate, Ldo_update, Ldone;
2986
2987 bool do_null = !not_null;
2988 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2989 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2990
2991 assert(do_null || do_update, "why are we here?");
2992 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2993
2994 __ verify_oop(obj, FILE_AND_LINE);
2995
2996 if (do_null) {
2997 if (!TypeEntries::was_null_seen(current_klass)) {
2998 __ cmpdi(CR0, obj, 0);
2999 __ bne(CR0, Lupdate);
3000 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3001 __ ori(R0, R0, TypeEntries::null_seen);
3002 if (do_update) {
3003 __ b(Ldo_update);
3004 } else {
3005 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3006 }
3007 } else {
3008 if (do_update) {
3009 __ cmpdi(CR0, obj, 0);
3010 __ beq(CR0, Ldone);
3011 }
3012 }
3013 #ifdef ASSERT
3014 } else {
3015 __ cmpdi(CR0, obj, 0);
3016 __ bne(CR0, Lupdate);
3017 __ stop("unexpected null obj");
3018 #endif
3019 }
3020
3021 __ bind(Lupdate);
3022 if (do_update) {
3023 Label Lnext;
3024 const Register klass = R29_TOC; // kill and reload
3025 bool klass_reg_used = false;
3026 #ifdef ASSERT
3027 if (exact_klass != nullptr) {
3028 Label ok;
3029 klass_reg_used = true;
3030 __ load_klass(klass, obj);
3031 metadata2reg(exact_klass->constant_encoding(), R0);
3032 __ cmpd(CR0, klass, R0);
3033 __ beq(CR0, ok);
3034 __ stop("exact klass and actual klass differ");
3035 __ bind(ok);
3036 }
3037 #endif
3038
3039 if (!no_conflict) {
3040 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3041 klass_reg_used = true;
3042 if (exact_klass != nullptr) {
3043 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3044 metadata2reg(exact_klass->constant_encoding(), klass);
3045 } else {
3046 __ load_klass(klass, obj);
3047 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3048 }
3049
3050 // Like InterpreterMacroAssembler::profile_obj_type
3051 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3052 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3053 __ cmpd(CR1, R0, klass);
3054 // Klass seen before, nothing to do (regardless of unknown bit).
3055 //beq(CR1, do_nothing);
3056
3057 __ andi_(R0, tmp, TypeEntries::type_unknown);
3058 // Already unknown. Nothing to do anymore.
3059 //bne(CR0, do_nothing);
3060 __ crorc(CR0, Assembler::equal, CR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3061 __ beq(CR0, Lnext);
3062
3063 if (TypeEntries::is_type_none(current_klass)) {
3064 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3065 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3066 __ beq(CR0, Ldo_update); // First time here. Set profile type.
3067 }
3068
3069 } else {
3070 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3071 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3072
3073 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3074 __ andi_(R0, tmp, TypeEntries::type_unknown);
3075 // Already unknown. Nothing to do anymore.
3076 __ bne(CR0, Lnext);
3077 }
3078
3079 // Different than before. Cannot keep accurate profile.
3080 __ ori(R0, tmp, TypeEntries::type_unknown);
3081 } else {
3082 // There's a single possible klass at this profile point
3083 assert(exact_klass != nullptr, "should be");
3084 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3085
3086 if (TypeEntries::is_type_none(current_klass)) {
3087 klass_reg_used = true;
3088 metadata2reg(exact_klass->constant_encoding(), klass);
3089
3090 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3091 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3092 __ cmpd(CR1, R0, klass);
3093 // Klass seen before, nothing to do (regardless of unknown bit).
3094 __ beq(CR1, Lnext);
3095 #ifdef ASSERT
3096 {
3097 Label ok;
3098 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3099 __ beq(CR0, ok); // First time here.
3100
3101 __ stop("unexpected profiling mismatch");
3102 __ bind(ok);
3103 }
3104 #endif
3105 // First time here. Set profile type.
3106 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3107 } else {
3108 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3109 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3110
3111 // Already unknown. Nothing to do anymore.
3112 __ andi_(R0, tmp, TypeEntries::type_unknown);
3113 __ bne(CR0, Lnext);
3114
3115 // Different than before. Cannot keep accurate profile.
3116 __ ori(R0, tmp, TypeEntries::type_unknown);
3117 }
3118 }
3119
3120 __ bind(Ldo_update);
3121 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3122
3123 __ bind(Lnext);
3124 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3125 }
3126 __ bind(Ldone);
3127 }
3128
3129 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3130 Unimplemented();
3131 }
3132
3133 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3134 assert(op->crc()->is_single_cpu(), "crc must be register");
3135 assert(op->val()->is_single_cpu(), "byte value must be register");
3136 assert(op->result_opr()->is_single_cpu(), "result must be register");
3137 Register crc = op->crc()->as_register();
3138 Register val = op->val()->as_register();
3139 Register res = op->result_opr()->as_register();
3140
3141 assert_different_registers(val, crc, res);
3142
3143 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3144 __ kernel_crc32_singleByteReg(crc, val, res, true);
3145 __ mr(res, crc);
3146 }
3147
3148 // Valhalla support
3149
3150 void LIR_Assembler::check_orig_pc() {
3151 Unimplemented();
3152 }
3153
3154 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
3155 Unimplemented();
3156 return 0;
3157 }
3158
3159 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
3160 Unimplemented();
3161 }
3162
3163 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
3164 Unimplemented();
3165 }
3166
3167 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
3168 Unimplemented();
3169 }
3170 #undef __