1 /*
   2  * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "c1/c1_Compilation.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "c1/c1_ValueStack.hpp"
  32 #include "ci/ciArrayKlass.hpp"
  33 #include "ci/ciInstance.hpp"
  34 #include "gc/shared/collectedHeap.hpp"
  35 #include "memory/universe.hpp"
  36 #include "nativeInst_ppc.hpp"
  37 #include "oops/compressedOops.hpp"
  38 #include "oops/objArrayKlass.hpp"
  39 #include "runtime/frame.inline.hpp"
  40 #include "runtime/os.inline.hpp"
  41 #include "runtime/safepointMechanism.inline.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "runtime/stubRoutines.hpp"
  44 #include "runtime/vm_version.hpp"
  45 #include "utilities/macros.hpp"
  46 #include "utilities/powerOfTwo.hpp"
  47 
  48 #define __ _masm->
  49 
  50 
  51 const ConditionRegister LIR_Assembler::BOOL_RESULT = CR5;
  52 
  53 
  54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  55   Unimplemented(); return false; // Currently not used on this platform.
  56 }
  57 
  58 
  59 LIR_Opr LIR_Assembler::receiverOpr() {
  60   return FrameMap::R3_oop_opr;
  61 }
  62 
  63 
  64 LIR_Opr LIR_Assembler::osrBufferPointer() {
  65   return FrameMap::R3_opr;
  66 }
  67 
  68 
  69 // This specifies the stack pointer decrement needed to build the frame.
  70 int LIR_Assembler::initial_frame_size_in_bytes() const {
  71   return in_bytes(frame_map()->framesize_in_bytes());
  72 }
  73 
  74 
  75 // Inline cache check: the inline cached class is in inline_cache_reg;
  76 // we fetch the class of the receiver and compare it with the cached class.
  77 // If they do not match we jump to slow case.
  78 int LIR_Assembler::check_icache() {
  79   return __ ic_check(CodeEntryAlignment);
  80 }
  81 
  82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
  83   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
  84 
  85   Label L_skip_barrier;
  86   Register klass = R20;
  87 
  88   metadata2reg(method->holder()->constant_encoding(), klass);
  89   __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
  90 
  91   __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
  92   __ mtctr(klass);
  93   __ bctr();
  94 
  95   __ bind(L_skip_barrier);
  96 }
  97 
  98 void LIR_Assembler::osr_entry() {
  99   // On-stack-replacement entry sequence:
 100   //
 101   //   1. Create a new compiled activation.
 102   //   2. Initialize local variables in the compiled activation. The expression
 103   //      stack must be empty at the osr_bci; it is not initialized.
 104   //   3. Jump to the continuation address in compiled code to resume execution.
 105 
 106   // OSR entry point
 107   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 108   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 109   ValueStack* entry_state = osr_entry->end()->state();
 110   int number_of_locks = entry_state->locks_size();
 111 
 112   // Create a frame for the compiled activation.
 113   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 114 
 115   // OSR buffer is
 116   //
 117   // locals[nlocals-1..0]
 118   // monitors[number_of_locks-1..0]
 119   //
 120   // Locals is a direct copy of the interpreter frame so in the osr buffer
 121   // the first slot in the local array is the last local from the interpreter
 122   // and the last slot is local[0] (receiver) from the interpreter.
 123   //
 124   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 125   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 126   // in the interpreter frame (the method lock if a sync method).
 127 
 128   // Initialize monitors in the compiled activation.
 129   //   R3: pointer to osr buffer
 130   //
 131   // All other registers are dead at this point and the locals will be
 132   // copied into place by code emitted in the IR.
 133 
 134   Register OSR_buf = osrBufferPointer()->as_register();
 135   {
 136     assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 137 
 138     const int locals_space = BytesPerWord * method()->max_locals();
 139     int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
 140     bool use_OSR_bias = false;
 141 
 142     if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
 143       // Offsets too large for ld instructions. Use bias.
 144       __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
 145       monitor_offset -= locals_space;
 146       use_OSR_bias = true;
 147     }
 148 
 149     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 150     // the OSR buffer using 2 word entries: first the lock and then
 151     // the oop.
 152     for (int i = 0; i < number_of_locks; i++) {
 153       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 154 #ifdef ASSERT
 155       // Verify the interpreter's monitor has a non-null object.
 156       {
 157         Label L;
 158         __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 159         __ cmpdi(CR0, R0, 0);
 160         __ bne(CR0, L);
 161         __ stop("locked object is null");
 162         __ bind(L);
 163       }
 164 #endif // ASSERT
 165       // Copy the lock field into the compiled activation.
 166       Address ml = frame_map()->address_for_monitor_lock(i),
 167               mo = frame_map()->address_for_monitor_object(i);
 168       assert(ml.index() == noreg && mo.index() == noreg, "sanity");
 169       __ ld(R0, slot_offset + 0, OSR_buf);
 170       __ std(R0, ml);
 171       __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 172       __ std(R0, mo);
 173     }
 174 
 175     if (use_OSR_bias) {
 176       // Restore.
 177       __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
 178     }
 179   }
 180 }
 181 
 182 
 183 int LIR_Assembler::emit_exception_handler() {
 184   // Generate code for the exception handler.
 185   address handler_base = __ start_a_stub(exception_handler_size());
 186 
 187   if (handler_base == nullptr) {
 188     // Not enough space left for the handler.
 189     bailout("exception handler overflow");
 190     return -1;
 191   }
 192 
 193   int offset = code_offset();
 194   address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id));
 195   //__ load_const_optimized(R0, entry_point);
 196   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
 197   __ mtctr(R0);
 198   __ bctr();
 199 
 200   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 201   __ end_a_stub();
 202 
 203   return offset;
 204 }
 205 
 206 
 207 // Emit the code to remove the frame from the stack in the exception
 208 // unwind path.
 209 int LIR_Assembler::emit_unwind_handler() {
 210   _masm->block_comment("Unwind handler");
 211 
 212   int offset = code_offset();
 213   bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
 214   const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
 215 
 216   // Fetch the exception from TLS and clear out exception related thread state.
 217   __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 218   __ li(R0, 0);
 219   __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 220   __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
 221 
 222   __ bind(_unwind_handler_entry);
 223   __ verify_not_null_oop(Rexception);
 224   if (preserve_exception) { __ mr(Rexception_save, Rexception); }
 225 
 226   // Perform needed unlocking
 227   MonitorExitStub* stub = nullptr;
 228   if (method()->is_synchronized()) {
 229     monitor_address(0, FrameMap::R4_opr);
 230     stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
 231     __ unlock_object(R5, R6, R4, *stub->entry());
 232     __ bind(*stub->continuation());
 233   }
 234 
 235   if (compilation()->env()->dtrace_method_probes()) {
 236     Unimplemented();
 237   }
 238 
 239   // Dispatch to the unwind logic.
 240   address unwind_stub = Runtime1::entry_for(StubId::c1_unwind_exception_id);
 241   //__ load_const_optimized(R0, unwind_stub);
 242   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
 243   if (preserve_exception) { __ mr(Rexception, Rexception_save); }
 244   __ mtctr(R0);
 245   __ bctr();
 246 
 247   // Emit the slow path assembly.
 248   if (stub != nullptr) {
 249     stub->emit_code(this);
 250   }
 251 
 252   return offset;
 253 }
 254 
 255 
 256 int LIR_Assembler::emit_deopt_handler() {
 257   // Generate code for deopt handler.
 258   address handler_base = __ start_a_stub(deopt_handler_size());
 259 
 260   if (handler_base == nullptr) {
 261     // Not enough space left for the handler.
 262     bailout("deopt handler overflow");
 263     return -1;
 264   }
 265 
 266   int offset = code_offset();
 267   __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
 268 
 269   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 270   __ end_a_stub();
 271 
 272   return offset;
 273 }
 274 
 275 
 276 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 277   if (o == nullptr) {
 278     __ li(reg, 0);
 279   } else {
 280     AddressLiteral addrlit = __ constant_oop_address(o);
 281     __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
 282   }
 283 }
 284 
 285 
 286 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 287   // Allocate a new index in table to hold the object once it's been patched.
 288   int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
 289   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 290 
 291   AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
 292   __ load_const(reg, addrlit, R0);
 293 
 294   patching_epilog(patch, lir_patch_normal, reg, info);
 295 }
 296 
 297 
 298 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
 299   AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
 300   __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
 301 }
 302 
 303 
 304 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 305   // Allocate a new index in table to hold the klass once it's been patched.
 306   int index = __ oop_recorder()->allocate_metadata_index(nullptr);
 307   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 308 
 309   AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
 310   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 311   __ load_const(reg, addrlit, R0);
 312 
 313   patching_epilog(patch, lir_patch_normal, reg, info);
 314 }
 315 
 316 
 317 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
 318   const bool is_int = result->is_single_cpu();
 319   Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
 320   Register Rdivisor  = noreg;
 321   Register Rscratch  = temp->as_register();
 322   Register Rresult   = is_int ? result->as_register() : result->as_register_lo();
 323   long divisor = -1;
 324 
 325   if (right->is_register()) {
 326     Rdivisor = is_int ? right->as_register() : right->as_register_lo();
 327   } else {
 328     divisor = is_int ? right->as_constant_ptr()->as_jint()
 329                      : right->as_constant_ptr()->as_jlong();
 330   }
 331 
 332   assert(Rdividend != Rscratch, "");
 333   assert(Rdivisor  != Rscratch, "");
 334   assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
 335 
 336   if (Rdivisor == noreg) {
 337     if (divisor == 1) { // stupid, but can happen
 338       if (code == lir_idiv) {
 339         __ mr_if_needed(Rresult, Rdividend);
 340       } else {
 341         __ li(Rresult, 0);
 342       }
 343 
 344     } else if (is_power_of_2(divisor)) {
 345       // Convert division by a power of two into some shifts and logical operations.
 346       int log2 = log2i_exact(divisor);
 347 
 348       // Round towards 0.
 349       if (divisor == 2) {
 350         if (is_int) {
 351           __ srwi(Rscratch, Rdividend, 31);
 352         } else {
 353           __ srdi(Rscratch, Rdividend, 63);
 354         }
 355       } else {
 356         if (is_int) {
 357           __ srawi(Rscratch, Rdividend, 31);
 358         } else {
 359           __ sradi(Rscratch, Rdividend, 63);
 360         }
 361         __ clrldi(Rscratch, Rscratch, 64-log2);
 362       }
 363       __ add(Rscratch, Rdividend, Rscratch);
 364 
 365       if (code == lir_idiv) {
 366         if (is_int) {
 367           __ srawi(Rresult, Rscratch, log2);
 368         } else {
 369           __ sradi(Rresult, Rscratch, log2);
 370         }
 371       } else { // lir_irem
 372         __ clrrdi(Rscratch, Rscratch, log2);
 373         __ sub(Rresult, Rdividend, Rscratch);
 374       }
 375 
 376     } else if (divisor == -1) {
 377       if (code == lir_idiv) {
 378         __ neg(Rresult, Rdividend);
 379       } else {
 380         __ li(Rresult, 0);
 381       }
 382 
 383     } else {
 384       __ load_const_optimized(Rscratch, divisor);
 385       if (code == lir_idiv) {
 386         if (is_int) {
 387           __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 388         } else {
 389           __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 390         }
 391       } else {
 392         assert(Rscratch != R0, "need both");
 393         if (is_int) {
 394           __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 395           __ mullw(Rscratch, R0, Rscratch);
 396         } else {
 397           __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 398           __ mulld(Rscratch, R0, Rscratch);
 399         }
 400         __ sub(Rresult, Rdividend, Rscratch);
 401       }
 402 
 403     }
 404     return;
 405   }
 406 
 407   Label regular, done;
 408   if (is_int) {
 409     __ cmpwi(CR0, Rdivisor, -1);
 410   } else {
 411     __ cmpdi(CR0, Rdivisor, -1);
 412   }
 413   __ bne(CR0, regular);
 414   if (code == lir_idiv) {
 415     __ neg(Rresult, Rdividend);
 416     __ b(done);
 417     __ bind(regular);
 418     if (is_int) {
 419       __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 420     } else {
 421       __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 422     }
 423   } else { // lir_irem
 424     __ li(Rresult, 0);
 425     __ b(done);
 426     __ bind(regular);
 427     if (is_int) {
 428       __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 429       __ mullw(Rscratch, Rscratch, Rdivisor);
 430     } else {
 431       __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 432       __ mulld(Rscratch, Rscratch, Rdivisor);
 433     }
 434     __ sub(Rresult, Rdividend, Rscratch);
 435   }
 436   __ bind(done);
 437 }
 438 
 439 
 440 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 441   switch (op->code()) {
 442   case lir_idiv:
 443   case lir_irem:
 444     arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
 445                     op->result_opr(), op->info());
 446     break;
 447   case lir_fmad:
 448     __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
 449              op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
 450     break;
 451   case lir_fmaf:
 452     __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
 453               op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
 454     break;
 455   default: ShouldNotReachHere(); break;
 456   }
 457 }
 458 
 459 
 460 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 461 #ifdef ASSERT
 462   assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
 463   if (op->block() != nullptr)  _branch_target_blocks.append(op->block());
 464   if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
 465   assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
 466 #endif
 467 
 468   Label *L = op->label();
 469   if (op->cond() == lir_cond_always) {
 470     __ b(*L);
 471   } else {
 472     Label done;
 473     bool is_unordered = false;
 474     if (op->code() == lir_cond_float_branch) {
 475       assert(op->ublock() != nullptr, "must have unordered successor");
 476       is_unordered = true;
 477     } else {
 478       assert(op->code() == lir_branch, "just checking");
 479     }
 480 
 481     bool positive = false;
 482     Assembler::Condition cond = Assembler::equal;
 483     switch (op->cond()) {
 484       case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; is_unordered = false; break;
 485       case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; is_unordered = false; break;
 486       case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
 487       case lir_cond_belowEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 488       case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
 489       case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
 490       case lir_cond_aboveEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 491       case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
 492       default:                    ShouldNotReachHere();
 493     }
 494     int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
 495     int bi = Assembler::bi0(BOOL_RESULT, cond);
 496     if (is_unordered) {
 497       if (positive) {
 498         if (op->ublock() == op->block()) {
 499           __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
 500         }
 501       } else {
 502         if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
 503       }
 504     }
 505     __ bc_far_optimized(bo, bi, *L);
 506     __ bind(done);
 507   }
 508 }
 509 
 510 
 511 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 512   Bytecodes::Code code = op->bytecode();
 513   LIR_Opr src = op->in_opr(),
 514           dst = op->result_opr();
 515 
 516   switch(code) {
 517     case Bytecodes::_i2l: {
 518       __ extsw(dst->as_register_lo(), src->as_register());
 519       break;
 520     }
 521     case Bytecodes::_l2i: {
 522       __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
 523       break;
 524     }
 525     case Bytecodes::_i2b: {
 526       __ extsb(dst->as_register(), src->as_register());
 527       break;
 528     }
 529     case Bytecodes::_i2c: {
 530       __ clrldi(dst->as_register(), src->as_register(), 64-16);
 531       break;
 532     }
 533     case Bytecodes::_i2s: {
 534       __ extsh(dst->as_register(), src->as_register());
 535       break;
 536     }
 537     case Bytecodes::_i2d:{
 538       FloatRegister rdst = dst->as_double_reg();
 539       // move src to dst register
 540       __ mtfprwa(rdst, src->as_register());
 541       __ fcfid(rdst, rdst);
 542       break;
 543     }
 544     case Bytecodes::_l2d: {
 545       FloatRegister rdst = dst->as_double_reg();
 546       // move src to dst register
 547       __ mtfprd(rdst, src->as_register_lo());
 548       __ fcfid(rdst, rdst);
 549       break;
 550     }
 551     case Bytecodes::_i2f:{
 552       FloatRegister rdst = dst->as_float_reg();
 553       // move src to dst register
 554       __ mtfprwa(rdst, src->as_register());
 555       __ fcfids(rdst, rdst);
 556       break;
 557     }
 558     case Bytecodes::_l2f: {
 559       FloatRegister rdst = dst->as_float_reg();
 560       // move src to dst register
 561       __ mtfprd(rdst, src->as_register_lo());
 562       __ fcfids(rdst, rdst);
 563       break;
 564     }
 565     case Bytecodes::_f2d: {
 566       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
 567       break;
 568     }
 569     case Bytecodes::_d2f: {
 570       __ frsp(dst->as_float_reg(), src->as_double_reg());
 571       break;
 572     }
 573     case Bytecodes::_d2i:
 574     case Bytecodes::_f2i: {
 575       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
 576       Label L;
 577       // Result must be 0 if value is NaN; test by comparing value to itself.
 578       __ fcmpu(CR0, rsrc, rsrc);
 579       __ li(dst->as_register(), 0);
 580       __ bso(CR0, L);
 581       __ fctiwz(rsrc, rsrc); // USE_KILL
 582       __ mffprd(dst->as_register(), rsrc);
 583       __ bind(L);
 584       break;
 585     }
 586     case Bytecodes::_d2l:
 587     case Bytecodes::_f2l: {
 588       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
 589       Label L;
 590       // Result must be 0 if value is NaN; test by comparing value to itself.
 591       __ fcmpu(CR0, rsrc, rsrc);
 592       __ li(dst->as_register_lo(), 0);
 593       __ bso(CR0, L);
 594       __ fctidz(rsrc, rsrc); // USE_KILL
 595       __ mffprd(dst->as_register_lo(), rsrc);
 596       __ bind(L);
 597       break;
 598     }
 599 
 600     default: ShouldNotReachHere();
 601   }
 602 }
 603 
 604 
 605 void LIR_Assembler::align_call(LIR_Code) {
 606   // do nothing since all instructions are word aligned on ppc
 607 }
 608 
 609 
 610 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
 611   int start_offset = __ offset();
 612   // Put the entry point as a constant into the constant pool.
 613   const address entry_point_toc_addr   = __ address_constant(target, RelocationHolder::none);
 614   if (entry_point_toc_addr == nullptr) {
 615     bailout("const section overflow");
 616     return false;
 617   }
 618   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
 619 
 620   // Emit the trampoline stub which will be related to the branch-and-link below.
 621   address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
 622   if (!stub) {
 623     bailout("no space for trampoline stub");
 624     return false;
 625   }
 626   return true;
 627 }
 628 
 629 
 630 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 631   assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
 632 
 633   bool success = emit_trampoline_stub_for_call(op->addr());
 634   if (!success) { return; }
 635 
 636   __ relocate(rtype);
 637   // Note: At this point we do not have the address of the trampoline
 638   // stub, and the entry point might be too far away for bl, so __ pc()
 639   // serves as dummy and the bl will be patched later.
 640   __ code()->set_insts_mark();
 641   __ bl(__ pc());
 642   add_call_info(code_offset(), op->info());
 643   __ post_call_nop();
 644 }
 645 
 646 
 647 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 648   __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
 649 
 650   // Virtual call relocation will point to ic load.
 651   address virtual_call_meta_addr = __ pc();
 652   // Load a clear inline cache.
 653   AddressLiteral empty_ic((address) Universe::non_oop_word());
 654   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
 655   if (!success) {
 656     bailout("const section overflow");
 657     return;
 658   }
 659   // Call to fixup routine. Fixup routine uses ScopeDesc info
 660   // to determine who we intended to call.
 661   __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
 662 
 663   success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
 664   if (!success) { return; }
 665 
 666   // Note: At this point we do not have the address of the trampoline
 667   // stub, and the entry point might be too far away for bl, so __ pc()
 668   // serves as dummy and the bl will be patched later.
 669   __ bl(__ pc());
 670   add_call_info(code_offset(), op->info());
 671   __ post_call_nop();
 672 }
 673 
 674 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
 675   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
 676   __ null_check(addr, stub->entry());
 677   append_code_stub(stub);
 678 }
 679 
 680 
 681 // Attention: caller must encode oop if needed
 682 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
 683   int store_offset;
 684   if (!Assembler::is_simm16(offset)) {
 685     // For offsets larger than a simm16 we setup the offset.
 686     assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
 687     __ load_const_optimized(R0, offset);
 688     store_offset = store(from_reg, base, R0, type, wide);
 689   } else {
 690     store_offset = code_offset();
 691     switch (type) {
 692       case T_BOOLEAN: // fall through
 693       case T_BYTE  : __ stb(from_reg->as_register(), offset, base); break;
 694       case T_CHAR  :
 695       case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
 696       case T_INT   : __ stw(from_reg->as_register(), offset, base); break;
 697       case T_LONG  : __ std(from_reg->as_register_lo(), offset, base); break;
 698       case T_ADDRESS:
 699       case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
 700       case T_ARRAY : // fall through
 701       case T_OBJECT:
 702         {
 703           if (UseCompressedOops && !wide) {
 704             // Encoding done in caller
 705             __ stw(from_reg->as_register(), offset, base);
 706             __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
 707           } else {
 708             __ std(from_reg->as_register(), offset, base);
 709             if (VerifyOops) {
 710               BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 711               bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
 712             }
 713           }
 714           break;
 715         }
 716       case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
 717       case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
 718       default      : ShouldNotReachHere();
 719     }
 720   }
 721   return store_offset;
 722 }
 723 
 724 
 725 // Attention: caller must encode oop if needed
 726 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
 727   int store_offset = code_offset();
 728   switch (type) {
 729     case T_BOOLEAN: // fall through
 730     case T_BYTE  : __ stbx(from_reg->as_register(), base, disp); break;
 731     case T_CHAR  :
 732     case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
 733     case T_INT   : __ stwx(from_reg->as_register(), base, disp); break;
 734     case T_LONG  :
 735 #ifdef _LP64
 736       __ stdx(from_reg->as_register_lo(), base, disp);
 737 #else
 738       Unimplemented();
 739 #endif
 740       break;
 741     case T_ADDRESS:
 742       __ stdx(from_reg->as_register(), base, disp);
 743       break;
 744     case T_ARRAY : // fall through
 745     case T_OBJECT:
 746       {
 747         if (UseCompressedOops && !wide) {
 748           // Encoding done in caller.
 749           __ stwx(from_reg->as_register(), base, disp);
 750           __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 751         } else {
 752           __ stdx(from_reg->as_register(), base, disp);
 753           if (VerifyOops) {
 754             BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 755             bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
 756           }
 757         }
 758         break;
 759       }
 760     case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
 761     case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
 762     default      : ShouldNotReachHere();
 763   }
 764   return store_offset;
 765 }
 766 
 767 
 768 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
 769   int load_offset;
 770   if (!Assembler::is_simm16(offset)) {
 771     // For offsets larger than a simm16 we setup the offset.
 772     __ load_const_optimized(R0, offset);
 773     load_offset = load(base, R0, to_reg, type, wide);
 774   } else {
 775     load_offset = code_offset();
 776     switch(type) {
 777       case T_BOOLEAN: // fall through
 778       case T_BYTE  :   __ lbz(to_reg->as_register(), offset, base);
 779                        __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 780       case T_CHAR  :   __ lhz(to_reg->as_register(), offset, base); break;
 781       case T_SHORT :   __ lha(to_reg->as_register(), offset, base); break;
 782       case T_INT   :   __ lwa(to_reg->as_register(), offset, base); break;
 783       case T_LONG  :   __ ld(to_reg->as_register_lo(), offset, base); break;
 784       case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
 785       case T_ADDRESS:
 786         __ ld(to_reg->as_register(), offset, base);
 787         break;
 788       case T_ARRAY : // fall through
 789       case T_OBJECT:
 790         {
 791           if (UseCompressedOops && !wide) {
 792             __ lwz(to_reg->as_register(), offset, base);
 793             __ decode_heap_oop(to_reg->as_register());
 794           } else {
 795             __ ld(to_reg->as_register(), offset, base);
 796           }
 797           break;
 798         }
 799       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
 800       case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
 801       default      : ShouldNotReachHere();
 802     }
 803   }
 804   return load_offset;
 805 }
 806 
 807 
 808 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
 809   int load_offset = code_offset();
 810   switch(type) {
 811     case T_BOOLEAN: // fall through
 812     case T_BYTE  :  __ lbzx(to_reg->as_register(), base, disp);
 813                     __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 814     case T_CHAR  :  __ lhzx(to_reg->as_register(), base, disp); break;
 815     case T_SHORT :  __ lhax(to_reg->as_register(), base, disp); break;
 816     case T_INT   :  __ lwax(to_reg->as_register(), base, disp); break;
 817     case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
 818     case T_ARRAY : // fall through
 819     case T_OBJECT:
 820       {
 821         if (UseCompressedOops && !wide) {
 822           __ lwzx(to_reg->as_register(), base, disp);
 823           __ decode_heap_oop(to_reg->as_register());
 824         } else {
 825           __ ldx(to_reg->as_register(), base, disp);
 826         }
 827         break;
 828       }
 829     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;
 830     case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
 831     case T_LONG  :
 832 #ifdef _LP64
 833       __ ldx(to_reg->as_register_lo(), base, disp);
 834 #else
 835       Unimplemented();
 836 #endif
 837       break;
 838     default      : ShouldNotReachHere();
 839   }
 840   return load_offset;
 841 }
 842 
 843 
 844 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 845   LIR_Const* c = src->as_constant_ptr();
 846   Register src_reg = R0;
 847   switch (c->type()) {
 848     case T_INT:
 849     case T_FLOAT: {
 850       int value = c->as_jint_bits();
 851       __ load_const_optimized(src_reg, value);
 852       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 853       __ stw(src_reg, addr);
 854       break;
 855     }
 856     case T_ADDRESS: {
 857       int value = c->as_jint_bits();
 858       __ load_const_optimized(src_reg, value);
 859       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 860       __ std(src_reg, addr);
 861       break;
 862     }
 863     case T_OBJECT: {
 864       jobject2reg(c->as_jobject(), src_reg);
 865       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 866       __ std(src_reg, addr);
 867       break;
 868     }
 869     case T_LONG:
 870     case T_DOUBLE: {
 871       int value = c->as_jlong_bits();
 872       __ load_const_optimized(src_reg, value);
 873       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
 874       __ std(src_reg, addr);
 875       break;
 876     }
 877     default:
 878       Unimplemented();
 879   }
 880 }
 881 
 882 
 883 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 884   LIR_Const* c = src->as_constant_ptr();
 885   LIR_Address* addr = dest->as_address_ptr();
 886   Register base = addr->base()->as_pointer_register();
 887   LIR_Opr tmp = LIR_OprFact::illegalOpr;
 888   int offset = -1;
 889   // Null check for large offsets in LIRGenerator::do_StoreField.
 890   bool needs_explicit_null_check = !ImplicitNullChecks;
 891 
 892   if (info != nullptr && needs_explicit_null_check) {
 893     explicit_null_check(base, info);
 894   }
 895 
 896   switch (c->type()) {
 897     case T_FLOAT: type = T_INT;
 898     case T_INT:
 899     case T_ADDRESS: {
 900       tmp = FrameMap::R0_opr;
 901       __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
 902       break;
 903     }
 904     case T_DOUBLE: type = T_LONG;
 905     case T_LONG: {
 906       tmp = FrameMap::R0_long_opr;
 907       __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
 908       break;
 909     }
 910     case T_OBJECT: {
 911       tmp = FrameMap::R0_opr;
 912       if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
 913         AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
 914         // Don't care about sign extend (will use stw).
 915         __ lis(R0, 0); // Will get patched.
 916         __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
 917         __ ori(R0, R0, 0); // Will get patched.
 918       } else {
 919         jobject2reg(c->as_jobject(), R0);
 920       }
 921       break;
 922     }
 923     default:
 924       Unimplemented();
 925   }
 926 
 927   // Handle either reg+reg or reg+disp address.
 928   if (addr->index()->is_valid()) {
 929     assert(addr->disp() == 0, "must be zero");
 930     offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
 931   } else {
 932     assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
 933     offset = store(tmp, base, addr->disp(), type, wide);
 934   }
 935 
 936   if (info != nullptr) {
 937     assert(offset != -1, "offset should've been set");
 938     if (!needs_explicit_null_check) {
 939       add_debug_info_for_null_check(offset, info);
 940     }
 941   }
 942 }
 943 
 944 
 945 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 946   LIR_Const* c = src->as_constant_ptr();
 947   LIR_Opr to_reg = dest;
 948 
 949   switch (c->type()) {
 950     case T_INT: {
 951       assert(patch_code == lir_patch_none, "no patching handled here");
 952       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
 953       break;
 954     }
 955     case T_ADDRESS: {
 956       assert(patch_code == lir_patch_none, "no patching handled here");
 957       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);  // Yes, as_jint ...
 958       break;
 959     }
 960     case T_LONG: {
 961       assert(patch_code == lir_patch_none, "no patching handled here");
 962       __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
 963       break;
 964     }
 965 
 966     case T_OBJECT: {
 967       if (patch_code == lir_patch_none) {
 968         jobject2reg(c->as_jobject(), to_reg->as_register());
 969       } else {
 970         jobject2reg_with_patching(to_reg->as_register(), info);
 971       }
 972       break;
 973     }
 974 
 975     case T_METADATA:
 976       {
 977         if (patch_code == lir_patch_none) {
 978           metadata2reg(c->as_metadata(), to_reg->as_register());
 979         } else {
 980           klass2reg_with_patching(to_reg->as_register(), info);
 981         }
 982       }
 983       break;
 984 
 985     case T_FLOAT:
 986       {
 987         if (to_reg->is_single_fpu()) {
 988           address const_addr = __ float_constant(c->as_jfloat());
 989           if (const_addr == nullptr) {
 990             bailout("const section overflow");
 991             break;
 992           }
 993           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
 994           __ relocate(rspec);
 995           __ load_const(R0, const_addr);
 996           __ lfsx(to_reg->as_float_reg(), R0);
 997         } else {
 998           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
 999           __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1000         }
1001       }
1002       break;
1003 
1004     case T_DOUBLE:
1005       {
1006         if (to_reg->is_double_fpu()) {
1007           address const_addr = __ double_constant(c->as_jdouble());
1008           if (const_addr == nullptr) {
1009             bailout("const section overflow");
1010             break;
1011           }
1012           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1013           __ relocate(rspec);
1014           __ load_const(R0, const_addr);
1015           __ lfdx(to_reg->as_double_reg(), R0);
1016         } else {
1017           assert(to_reg->is_double_cpu(), "Must be a long register.");
1018           __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1019         }
1020       }
1021       break;
1022 
1023     default:
1024       ShouldNotReachHere();
1025   }
1026 }
1027 
1028 
1029 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1030   Unimplemented(); return Address();
1031 }
1032 
1033 
1034 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1035   if (addr->index()->is_illegal()) {
1036     return (RegisterOrConstant)(addr->disp());
1037   } else {
1038     return (RegisterOrConstant)(addr->index()->as_pointer_register());
1039   }
1040 }
1041 
1042 
1043 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1044   const Register tmp = R0;
1045   switch (type) {
1046     case T_INT:
1047     case T_FLOAT: {
1048       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1049       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1050       __ lwz(tmp, from);
1051       __ stw(tmp, to);
1052       break;
1053     }
1054     case T_ADDRESS:
1055     case T_OBJECT: {
1056       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1057       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1058       __ ld(tmp, from);
1059       __ std(tmp, to);
1060       break;
1061     }
1062     case T_LONG:
1063     case T_DOUBLE: {
1064       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1065       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1066       __ ld(tmp, from);
1067       __ std(tmp, to);
1068       break;
1069     }
1070 
1071     default:
1072       ShouldNotReachHere();
1073   }
1074 }
1075 
1076 
1077 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1078   Unimplemented(); return Address();
1079 }
1080 
1081 
1082 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1083   Unimplemented(); return Address();
1084 }
1085 
1086 
1087 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1088                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1089 
1090   assert(type != T_METADATA, "load of metadata ptr not supported");
1091   LIR_Address* addr = src_opr->as_address_ptr();
1092   LIR_Opr to_reg = dest;
1093 
1094   Register src = addr->base()->as_pointer_register();
1095   Register disp_reg = noreg;
1096   int disp_value = addr->disp();
1097   bool needs_patching = (patch_code != lir_patch_none);
1098   // null check for large offsets in LIRGenerator::do_LoadField
1099   bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1100 
1101   if (info != nullptr && needs_explicit_null_check) {
1102     explicit_null_check(src, info);
1103   }
1104 
1105   if (addr->base()->type() == T_OBJECT) {
1106     __ verify_oop(src, FILE_AND_LINE);
1107   }
1108 
1109   PatchingStub* patch = nullptr;
1110   if (needs_patching) {
1111     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1112     assert(!to_reg->is_double_cpu() ||
1113            patch_code == lir_patch_none ||
1114            patch_code == lir_patch_normal, "patching doesn't match register");
1115   }
1116 
1117   if (addr->index()->is_illegal()) {
1118     if (!Assembler::is_simm16(disp_value)) {
1119       if (needs_patching) {
1120         __ load_const32(R0, 0); // patchable int
1121       } else {
1122         __ load_const_optimized(R0, disp_value);
1123       }
1124       disp_reg = R0;
1125     }
1126   } else {
1127     disp_reg = addr->index()->as_pointer_register();
1128     assert(disp_value == 0, "can't handle 3 operand addresses");
1129   }
1130 
1131   // Remember the offset of the load. The patching_epilog must be done
1132   // before the call to add_debug_info, otherwise the PcDescs don't get
1133   // entered in increasing order.
1134   int offset;
1135 
1136   if (disp_reg == noreg) {
1137     assert(Assembler::is_simm16(disp_value), "should have set this up");
1138     offset = load(src, disp_value, to_reg, type, wide);
1139   } else {
1140     offset = load(src, disp_reg, to_reg, type, wide);
1141   }
1142 
1143   if (patch != nullptr) {
1144     patching_epilog(patch, patch_code, src, info);
1145   }
1146   if (info != nullptr && !needs_explicit_null_check) {
1147     add_debug_info_for_null_check(offset, info);
1148   }
1149 }
1150 
1151 
1152 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1153   Address addr;
1154   if (src->is_single_word()) {
1155     addr = frame_map()->address_for_slot(src->single_stack_ix());
1156   } else if (src->is_double_word())  {
1157     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1158   }
1159 
1160   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1161 }
1162 
1163 
1164 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) {
1165   Address addr;
1166   if (dest->is_single_word()) {
1167     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1168   } else if (dest->is_double_word())  {
1169     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1170   }
1171 
1172   store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1173 }
1174 
1175 
1176 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1177   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1178     if (from_reg->is_double_fpu()) {
1179       // double to double moves
1180       assert(to_reg->is_double_fpu(), "should match");
1181       __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1182     } else {
1183       // float to float moves
1184       assert(to_reg->is_single_fpu(), "should match");
1185       __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1186     }
1187   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1188     if (from_reg->is_double_cpu()) {
1189       __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1190     } else if (to_reg->is_double_cpu()) {
1191       // int to int moves
1192       __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1193     } else {
1194       // int to int moves
1195       __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1196     }
1197   } else {
1198     ShouldNotReachHere();
1199   }
1200   if (is_reference_type(to_reg->type())) {
1201     __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1202   }
1203 }
1204 
1205 
1206 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1207                             LIR_PatchCode patch_code, CodeEmitInfo* info,
1208                             bool wide) {
1209   assert(type != T_METADATA, "store of metadata ptr not supported");
1210   LIR_Address* addr = dest->as_address_ptr();
1211 
1212   Register src = addr->base()->as_pointer_register();
1213   Register disp_reg = noreg;
1214   int disp_value = addr->disp();
1215   bool needs_patching = (patch_code != lir_patch_none);
1216   bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1217                       CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1218   bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1219   bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1220   // Null check for large offsets in LIRGenerator::do_StoreField.
1221   bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1222 
1223   if (info != nullptr && needs_explicit_null_check) {
1224     explicit_null_check(src, info);
1225   }
1226 
1227   if (addr->base()->is_oop_register()) {
1228     __ verify_oop(src, FILE_AND_LINE);
1229   }
1230 
1231   PatchingStub* patch = nullptr;
1232   if (needs_patching) {
1233     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1234     assert(!from_reg->is_double_cpu() ||
1235            patch_code == lir_patch_none ||
1236            patch_code == lir_patch_normal, "patching doesn't match register");
1237   }
1238 
1239   if (addr->index()->is_illegal()) {
1240     if (load_disp) {
1241       disp_reg = use_R29 ? R29_TOC : R0;
1242       if (needs_patching) {
1243         __ load_const32(disp_reg, 0); // patchable int
1244       } else {
1245         __ load_const_optimized(disp_reg, disp_value);
1246       }
1247     }
1248   } else {
1249     disp_reg = addr->index()->as_pointer_register();
1250     assert(disp_value == 0, "can't handle 3 operand addresses");
1251   }
1252 
1253   // remember the offset of the store. The patching_epilog must be done
1254   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1255   // entered in increasing order.
1256   int offset;
1257 
1258   if (compress_oop) {
1259     Register co = __ encode_heap_oop(R0, from_reg->as_register());
1260     from_reg = FrameMap::as_opr(co);
1261   }
1262 
1263   if (disp_reg == noreg) {
1264     assert(Assembler::is_simm16(disp_value), "should have set this up");
1265     offset = store(from_reg, src, disp_value, type, wide);
1266   } else {
1267     offset = store(from_reg, src, disp_reg, type, wide);
1268   }
1269 
1270   if (use_R29) {
1271     __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1272   }
1273 
1274   if (patch != nullptr) {
1275     patching_epilog(patch, patch_code, src, info);
1276   }
1277 
1278   if (info != nullptr && !needs_explicit_null_check) {
1279     add_debug_info_for_null_check(offset, info);
1280   }
1281 }
1282 
1283 
1284 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1285   const Register return_pc = R31;  // Must survive C-call to enable_stack_reserved_zone().
1286   const Register temp      = R12;
1287 
1288   // Pop the stack before the safepoint code.
1289   int frame_size = initial_frame_size_in_bytes();
1290   if (Assembler::is_simm(frame_size, 16)) {
1291     __ addi(R1_SP, R1_SP, frame_size);
1292   } else {
1293     __ pop_frame();
1294   }
1295 
1296   // Restore return pc relative to callers' sp.
1297   __ ld(return_pc, _abi0(lr), R1_SP);
1298   // Move return pc to LR.
1299   __ mtlr(return_pc);
1300 
1301   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1302     __ reserved_stack_check(return_pc);
1303   }
1304 
1305   // We need to mark the code position where the load from the safepoint
1306   // polling page was emitted as relocInfo::poll_return_type here.
1307   if (!UseSIGTRAP) {
1308     code_stub->set_safepoint_offset(__ offset());
1309     __ relocate(relocInfo::poll_return_type);
1310   }
1311   __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1312 
1313   // Return.
1314   __ blr();
1315 }
1316 
1317 
1318 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1319   const Register poll_addr = tmp->as_register();
1320   __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1321   if (info != nullptr) {
1322     add_debug_info_for_branch(info);
1323   }
1324   int offset = __ offset();
1325   __ relocate(relocInfo::poll_type);
1326   __ load_from_polling_page(poll_addr);
1327 
1328   return offset;
1329 }
1330 
1331 
1332 void LIR_Assembler::emit_static_call_stub() {
1333   address call_pc = __ pc();
1334   address stub = __ start_a_stub(static_call_stub_size());
1335   if (stub == nullptr) {
1336     bailout("static call stub overflow");
1337     return;
1338   }
1339 
1340   // For java_to_interp stubs we use R11_scratch1 as scratch register
1341   // and in call trampoline stubs we use R12_scratch2. This way we
1342   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1343   const Register reg_scratch = R11_scratch1;
1344 
1345   // Create a static stub relocation which relates this stub
1346   // with the call instruction at insts_call_instruction_offset in the
1347   // instructions code-section.
1348   int start = __ offset();
1349   __ relocate(static_stub_Relocation::spec(call_pc));
1350 
1351   // Now, create the stub's code:
1352   // - load the TOC
1353   // - load the inline cache oop from the constant pool
1354   // - load the call target from the constant pool
1355   // - call
1356   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1357   AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1358   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1359 
1360   if (ReoptimizeCallSequences) {
1361     __ b64_patchable((address)-1, relocInfo::none);
1362   } else {
1363     AddressLiteral a((address)-1);
1364     success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1365     __ mtctr(reg_scratch);
1366     __ bctr();
1367   }
1368   if (!success) {
1369     bailout("const section overflow");
1370     return;
1371   }
1372 
1373   assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1374   __ end_a_stub();
1375 }
1376 
1377 
1378 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1379   bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1380   if (opr1->is_single_fpu()) {
1381     __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1382   } else if (opr1->is_double_fpu()) {
1383     __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1384   } else if (opr1->is_single_cpu()) {
1385     if (opr2->is_constant()) {
1386       switch (opr2->as_constant_ptr()->type()) {
1387         case T_INT:
1388           {
1389             jint con = opr2->as_constant_ptr()->as_jint();
1390             if (unsigned_comp) {
1391               if (Assembler::is_uimm(con, 16)) {
1392                 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1393               } else {
1394                 __ load_const_optimized(R0, con);
1395                 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1396               }
1397             } else {
1398               if (Assembler::is_simm(con, 16)) {
1399                 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1400               } else {
1401                 __ load_const_optimized(R0, con);
1402                 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1403               }
1404             }
1405           }
1406           break;
1407 
1408         case T_OBJECT:
1409           // There are only equal/notequal comparisons on objects.
1410           {
1411             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1412             jobject con = opr2->as_constant_ptr()->as_jobject();
1413             if (con == nullptr) {
1414               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1415             } else {
1416               jobject2reg(con, R0);
1417               __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1418             }
1419           }
1420           break;
1421 
1422         case T_METADATA:
1423           // We only need, for now, comparison with null for metadata.
1424           {
1425             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1426             Metadata* p = opr2->as_constant_ptr()->as_metadata();
1427             if (p == nullptr) {
1428               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1429             } else {
1430               ShouldNotReachHere();
1431             }
1432           }
1433           break;
1434 
1435         default:
1436           ShouldNotReachHere();
1437           break;
1438       }
1439     } else {
1440       assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1441       if (is_reference_type(opr1->type())) {
1442         // There are only equal/notequal comparisons on objects.
1443         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1444         __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1445       } else {
1446         if (unsigned_comp) {
1447           __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1448         } else {
1449           __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1450         }
1451       }
1452     }
1453   } else if (opr1->is_double_cpu()) {
1454     if (opr2->is_constant()) {
1455       jlong con = opr2->as_constant_ptr()->as_jlong();
1456       if (unsigned_comp) {
1457         if (Assembler::is_uimm(con, 16)) {
1458           __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1459         } else {
1460           __ load_const_optimized(R0, con);
1461           __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1462         }
1463       } else {
1464         if (Assembler::is_simm(con, 16)) {
1465           __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1466         } else {
1467           __ load_const_optimized(R0, con);
1468           __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1469         }
1470       }
1471     } else if (opr2->is_register()) {
1472       if (unsigned_comp) {
1473         __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1474       } else {
1475         __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1476       }
1477     } else {
1478       ShouldNotReachHere();
1479     }
1480   } else {
1481     ShouldNotReachHere();
1482   }
1483 }
1484 
1485 
1486 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1487   const Register Rdst = dst->as_register();
1488   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1489     bool is_unordered_less = (code == lir_ucmp_fd2i);
1490     if (left->is_single_fpu()) {
1491       __ fcmpu(CR0, left->as_float_reg(), right->as_float_reg());
1492     } else if (left->is_double_fpu()) {
1493       __ fcmpu(CR0, left->as_double_reg(), right->as_double_reg());
1494     } else {
1495       ShouldNotReachHere();
1496     }
1497     __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1498   } else if (code == lir_cmp_l2i) {
1499     __ cmpd(CR0, left->as_register_lo(), right->as_register_lo());
1500     __ set_cmp3(Rdst);  // set result as follows: <: -1, =: 0, >: 1
1501   } else {
1502     ShouldNotReachHere();
1503   }
1504 }
1505 
1506 
1507 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1508   if (src->is_constant()) {
1509     lasm->const2reg(src, dst, lir_patch_none, nullptr);
1510   } else if (src->is_register()) {
1511     lasm->reg2reg(src, dst);
1512   } else if (src->is_stack()) {
1513     lasm->stack2reg(src, dst, dst->type());
1514   } else {
1515     ShouldNotReachHere();
1516   }
1517 }
1518 
1519 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1520                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1521   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1522 
1523   if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1524     load_to_reg(this, opr1, result); // Condition doesn't matter.
1525     return;
1526   }
1527 
1528   bool positive = false;
1529   Assembler::Condition cond = Assembler::equal;
1530   switch (condition) {
1531     case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; break;
1532     case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; break;
1533     case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
1534     case lir_cond_belowEqual:
1535     case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
1536     case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
1537     case lir_cond_aboveEqual:
1538     case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
1539     default:                    ShouldNotReachHere();
1540   }
1541 
1542   if (result->is_cpu_register()) {
1543     bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1544     const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1545 
1546     // We can use result_reg to load one operand if not already in register.
1547     Register first  = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1548              second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1549 
1550     if (first != second) {
1551       if (!o1_is_reg) {
1552         load_to_reg(this, opr1, result);
1553       }
1554 
1555       if (!o2_is_reg) {
1556         load_to_reg(this, opr2, result);
1557       }
1558 
1559       __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1560       return;
1561     }
1562   } // isel
1563 
1564   load_to_reg(this, opr1, result);
1565 
1566   Label skip;
1567   int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1568   int bi = Assembler::bi0(BOOL_RESULT, cond);
1569   __ bc(bo, bi, skip);
1570 
1571   load_to_reg(this, opr2, result);
1572   __ bind(skip);
1573 }
1574 
1575 
1576 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1577                              CodeEmitInfo* info) {
1578   assert(info == nullptr, "unused on this code path");
1579   assert(left->is_register(), "wrong items state");
1580   assert(dest->is_register(), "wrong items state");
1581 
1582   if (right->is_register()) {
1583     if (dest->is_float_kind()) {
1584 
1585       FloatRegister lreg, rreg, res;
1586       if (right->is_single_fpu()) {
1587         lreg = left->as_float_reg();
1588         rreg = right->as_float_reg();
1589         res  = dest->as_float_reg();
1590         switch (code) {
1591           case lir_add: __ fadds(res, lreg, rreg); break;
1592           case lir_sub: __ fsubs(res, lreg, rreg); break;
1593           case lir_mul: __ fmuls(res, lreg, rreg); break;
1594           case lir_div: __ fdivs(res, lreg, rreg); break;
1595           default: ShouldNotReachHere();
1596         }
1597       } else {
1598         lreg = left->as_double_reg();
1599         rreg = right->as_double_reg();
1600         res  = dest->as_double_reg();
1601         switch (code) {
1602           case lir_add: __ fadd(res, lreg, rreg); break;
1603           case lir_sub: __ fsub(res, lreg, rreg); break;
1604           case lir_mul: __ fmul(res, lreg, rreg); break;
1605           case lir_div: __ fdiv(res, lreg, rreg); break;
1606           default: ShouldNotReachHere();
1607         }
1608       }
1609 
1610     } else if (dest->is_double_cpu()) {
1611 
1612       Register dst_lo = dest->as_register_lo();
1613       Register op1_lo = left->as_pointer_register();
1614       Register op2_lo = right->as_pointer_register();
1615 
1616       switch (code) {
1617         case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1618         case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1619         case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1620         default: ShouldNotReachHere();
1621       }
1622     } else {
1623       assert (right->is_single_cpu(), "Just Checking");
1624 
1625       Register lreg = left->as_register();
1626       Register res  = dest->as_register();
1627       Register rreg = right->as_register();
1628       switch (code) {
1629         case lir_add:  __ add  (res, lreg, rreg); break;
1630         case lir_sub:  __ sub  (res, lreg, rreg); break;
1631         case lir_mul:  __ mullw(res, lreg, rreg); break;
1632         default: ShouldNotReachHere();
1633       }
1634     }
1635   } else {
1636     assert (right->is_constant(), "must be constant");
1637 
1638     if (dest->is_single_cpu()) {
1639       Register lreg = left->as_register();
1640       Register res  = dest->as_register();
1641       int    simm16 = right->as_constant_ptr()->as_jint();
1642 
1643       switch (code) {
1644         case lir_sub:  assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1645                        simm16 = -simm16;
1646         case lir_add:  if (res == lreg && simm16 == 0) break;
1647                        __ addi(res, lreg, simm16); break;
1648         case lir_mul:  if (res == lreg && simm16 == 1) break;
1649                        __ mulli(res, lreg, simm16); break;
1650         default: ShouldNotReachHere();
1651       }
1652     } else {
1653       Register lreg = left->as_pointer_register();
1654       Register res  = dest->as_register_lo();
1655       long con = right->as_constant_ptr()->as_jlong();
1656       assert(Assembler::is_simm16(con), "must be simm16");
1657 
1658       switch (code) {
1659         case lir_sub:  assert(Assembler::is_simm16(-con), "cannot encode");  // see do_ArithmeticOp_Long
1660                        con = -con;
1661         case lir_add:  if (res == lreg && con == 0) break;
1662                        __ addi(res, lreg, (int)con); break;
1663         case lir_mul:  if (res == lreg && con == 1) break;
1664                        __ mulli(res, lreg, (int)con); break;
1665         default: ShouldNotReachHere();
1666       }
1667     }
1668   }
1669 }
1670 
1671 
1672 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1673   switch (code) {
1674     case lir_sqrt: {
1675       __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1676       break;
1677     }
1678     case lir_abs: {
1679       __ fabs(dest->as_double_reg(), value->as_double_reg());
1680       break;
1681     }
1682     case lir_f2hf: {
1683       __ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1684       break;
1685     }
1686     case lir_hf2f: {
1687       __ hf2f(dest->as_float_reg(), value.as_register());
1688       break;
1689     }
1690     default: {
1691       ShouldNotReachHere();
1692       break;
1693     }
1694   }
1695 }
1696 
1697 
1698 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1699   if (right->is_constant()) { // see do_LogicOp
1700     long uimm;
1701     Register d, l;
1702     if (dest->is_single_cpu()) {
1703       uimm = right->as_constant_ptr()->as_jint();
1704       d = dest->as_register();
1705       l = left->as_register();
1706     } else {
1707       uimm = right->as_constant_ptr()->as_jlong();
1708       d = dest->as_register_lo();
1709       l = left->as_register_lo();
1710     }
1711     long uimms  = (unsigned long)uimm >> 16,
1712          uimmss = (unsigned long)uimm >> 32;
1713 
1714     switch (code) {
1715       case lir_logic_and:
1716         if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1717           __ andi(d, l, uimm); // special cases
1718         } else if (uimms != 0) { __ andis_(d, l, uimms); }
1719         else { __ andi_(d, l, uimm); }
1720         break;
1721 
1722       case lir_logic_or:
1723         if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1724         else { __ ori(d, l, uimm); }
1725         break;
1726 
1727       case lir_logic_xor:
1728         if (uimm == -1) { __ nand(d, l, l); } // special case
1729         else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1730         else { __ xori(d, l, uimm); }
1731         break;
1732 
1733       default: ShouldNotReachHere();
1734     }
1735   } else {
1736     assert(right->is_register(), "right should be in register");
1737 
1738     if (dest->is_single_cpu()) {
1739       switch (code) {
1740         case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1741         case lir_logic_or:  __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1742         case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1743         default: ShouldNotReachHere();
1744       }
1745     } else {
1746       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1747                                                                         left->as_register_lo();
1748       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1749                                                                           right->as_register_lo();
1750 
1751       switch (code) {
1752         case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1753         case lir_logic_or:  __ orr (dest->as_register_lo(), l, r); break;
1754         case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1755         default: ShouldNotReachHere();
1756       }
1757     }
1758   }
1759 }
1760 
1761 
1762 int LIR_Assembler::shift_amount(BasicType t) {
1763   int elem_size = type2aelembytes(t);
1764   switch (elem_size) {
1765     case 1 : return 0;
1766     case 2 : return 1;
1767     case 4 : return 2;
1768     case 8 : return 3;
1769   }
1770   ShouldNotReachHere();
1771   return -1;
1772 }
1773 
1774 
1775 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1776   info->add_register_oop(exceptionOop);
1777 
1778   // Reuse the debug info from the safepoint poll for the throw op itself.
1779   address pc_for_athrow = __ pc();
1780   int pc_for_athrow_offset = __ offset();
1781   //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1782   //__ relocate(rspec);
1783   //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1784   __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1785   add_call_info(pc_for_athrow_offset, info); // for exception handler
1786 
1787   address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1788                                                                    : StubId::c1_handle_exception_nofpu_id);
1789   //__ load_const_optimized(R0, stub);
1790   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1791   __ mtctr(R0);
1792   __ bctr();
1793 }
1794 
1795 
1796 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1797   // Note: Not used with EnableDebuggingOnDemand.
1798   assert(exceptionOop->as_register() == R3, "should match");
1799   __ b(_unwind_handler_entry);
1800 }
1801 
1802 
1803 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1804   Register src = op->src()->as_register();
1805   Register dst = op->dst()->as_register();
1806   Register src_pos = op->src_pos()->as_register();
1807   Register dst_pos = op->dst_pos()->as_register();
1808   Register length  = op->length()->as_register();
1809   Register tmp = op->tmp()->as_register();
1810   Register tmp2 = R0;
1811 
1812   int flags = op->flags();
1813   ciArrayKlass* default_type = op->expected_type();
1814   BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1815   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1816 
1817   // Set up the arraycopy stub information.
1818   ArrayCopyStub* stub = op->stub();
1819 
1820   // Always do stub if no type information is available. It's ok if
1821   // the known type isn't loaded since the code sanity checks
1822   // in debug mode and the type isn't required when we know the exact type
1823   // also check that the type is an array type.
1824   if (default_type == nullptr) {
1825     assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1826            length->is_nonvolatile(), "must preserve");
1827     address copyfunc_addr = StubRoutines::generic_arraycopy();
1828     assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1829 
1830     // 3 parms are int. Convert to long.
1831     __ mr(R3_ARG1, src);
1832     __ extsw(R4_ARG2, src_pos);
1833     __ mr(R5_ARG3, dst);
1834     __ extsw(R6_ARG4, dst_pos);
1835     __ extsw(R7_ARG5, length);
1836 
1837 #ifndef PRODUCT
1838     if (PrintC1Statistics) {
1839       address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1840       int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1841       __ lwz(R11_scratch1, simm16_offs, tmp);
1842       __ addi(R11_scratch1, R11_scratch1, 1);
1843       __ stw(R11_scratch1, simm16_offs, tmp);
1844     }
1845 #endif
1846     __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1847 
1848     __ nand(tmp, R3_RET, R3_RET);
1849     __ subf(length, tmp, length);
1850     __ add(src_pos, tmp, src_pos);
1851     __ add(dst_pos, tmp, dst_pos);
1852 
1853     __ cmpwi(CR0, R3_RET, 0);
1854     __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CR0, Assembler::less), *stub->entry());
1855     __ bind(*stub->continuation());
1856     return;
1857   }
1858 
1859   assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1860   Label cont, slow, copyfunc;
1861 
1862   bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1863                                         LIR_OpArrayCopy::dst_null_check |
1864                                         LIR_OpArrayCopy::src_pos_positive_check |
1865                                         LIR_OpArrayCopy::dst_pos_positive_check |
1866                                         LIR_OpArrayCopy::length_positive_check);
1867 
1868   // Use only one conditional branch for simple checks.
1869   if (simple_check_flag_set) {
1870     ConditionRegister combined_check = CR1, tmp_check = CR1;
1871 
1872     // Make sure src and dst are non-null.
1873     if (flags & LIR_OpArrayCopy::src_null_check) {
1874       __ cmpdi(combined_check, src, 0);
1875       tmp_check = CR0;
1876     }
1877 
1878     if (flags & LIR_OpArrayCopy::dst_null_check) {
1879       __ cmpdi(tmp_check, dst, 0);
1880       if (tmp_check != combined_check) {
1881         __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1882       }
1883       tmp_check = CR0;
1884     }
1885 
1886     // Clear combined_check.eq if not already used.
1887     if (tmp_check == combined_check) {
1888       __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1889       tmp_check = CR0;
1890     }
1891 
1892     if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1893       // Test src_pos register.
1894       __ cmpwi(tmp_check, src_pos, 0);
1895       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1896     }
1897 
1898     if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1899       // Test dst_pos register.
1900       __ cmpwi(tmp_check, dst_pos, 0);
1901       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1902     }
1903 
1904     if (flags & LIR_OpArrayCopy::length_positive_check) {
1905       // Make sure length isn't negative.
1906       __ cmpwi(tmp_check, length, 0);
1907       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1908     }
1909 
1910     __ beq(combined_check, slow);
1911   }
1912 
1913   // If the compiler was not able to prove that exact type of the source or the destination
1914   // of the arraycopy is an array type, check at runtime if the source or the destination is
1915   // an instance type.
1916   if (flags & LIR_OpArrayCopy::type_check) {
1917     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1918       __ load_klass(tmp, dst);
1919       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1920       __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1921       __ bge(CR0, slow);
1922     }
1923 
1924     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1925       __ load_klass(tmp, src);
1926       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1927       __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1928       __ bge(CR0, slow);
1929     }
1930   }
1931 
1932   // Higher 32bits must be null.
1933   __ extsw(length, length);
1934 
1935   __ extsw(src_pos, src_pos);
1936   if (flags & LIR_OpArrayCopy::src_range_check) {
1937     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1938     __ add(tmp, length, src_pos);
1939     __ cmpld(CR0, tmp2, tmp);
1940     __ ble(CR0, slow);
1941   }
1942 
1943   __ extsw(dst_pos, dst_pos);
1944   if (flags & LIR_OpArrayCopy::dst_range_check) {
1945     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1946     __ add(tmp, length, dst_pos);
1947     __ cmpld(CR0, tmp2, tmp);
1948     __ ble(CR0, slow);
1949   }
1950 
1951   int shift = shift_amount(basic_type);
1952 
1953   if (!(flags & LIR_OpArrayCopy::type_check)) {
1954     if (stub != nullptr) {
1955       __ b(cont);
1956       __ bind(slow);
1957       __ b(*stub->entry());
1958     }
1959   } else {
1960     // We don't know the array types are compatible.
1961     if (basic_type != T_OBJECT) {
1962       // Simple test for basic type arrays.
1963       __ cmp_klasses_from_objects(CR0, src, dst, tmp, tmp2);
1964       __ beq(CR0, cont);
1965     } else {
1966       // For object arrays, if src is a sub class of dst then we can
1967       // safely do the copy.
1968       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1969 
1970       const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1971       assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1972 
1973       __ load_klass(sub_klass, src);
1974       __ load_klass(super_klass, dst);
1975 
1976       __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1977                                        &cont, copyfunc_addr != nullptr ? &copyfunc : &slow, nullptr);
1978 
1979       address slow_stc = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
1980       //__ load_const_optimized(tmp, slow_stc, tmp2);
1981       __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1982       __ mtctr(tmp);
1983       __ bctrl(); // sets CR0
1984       __ beq(CR0, cont);
1985 
1986       if (copyfunc_addr != nullptr) { // Use stub if available.
1987         __ bind(copyfunc);
1988         // Src is not a sub class of dst so we have to do a
1989         // per-element check.
1990         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1991         if ((flags & mask) != mask) {
1992           assert(flags & mask, "one of the two should be known to be an object array");
1993 
1994           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1995             __ load_klass(tmp, src);
1996           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1997             __ load_klass(tmp, dst);
1998           }
1999 
2000           __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2001 
2002           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2003           __ load_const_optimized(tmp, objArray_lh);
2004           __ cmpw(CR0, tmp, tmp2);
2005           __ bne(CR0, slow);
2006         }
2007 
2008         Register src_ptr = R3_ARG1;
2009         Register dst_ptr = R4_ARG2;
2010         Register len     = R5_ARG3;
2011         Register chk_off = R6_ARG4;
2012         Register super_k = R7_ARG5;
2013 
2014         __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2015         __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2016         if (shift == 0) {
2017           __ add(src_ptr, src_pos, src_ptr);
2018           __ add(dst_ptr, dst_pos, dst_ptr);
2019         } else {
2020           __ sldi(tmp, src_pos, shift);
2021           __ sldi(tmp2, dst_pos, shift);
2022           __ add(src_ptr, tmp, src_ptr);
2023           __ add(dst_ptr, tmp2, dst_ptr);
2024         }
2025 
2026         __ load_klass(tmp, dst);
2027         __ mr(len, length);
2028 
2029         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2030         __ ld(super_k, ek_offset, tmp);
2031 
2032         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2033         __ lwz(chk_off, sco_offset, super_k);
2034 
2035         __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2036 
2037 #ifndef PRODUCT
2038         if (PrintC1Statistics) {
2039           Label failed;
2040           __ cmpwi(CR0, R3_RET, 0);
2041           __ bne(CR0, failed);
2042           address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2043           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2044           __ lwz(R11_scratch1, simm16_offs, tmp);
2045           __ addi(R11_scratch1, R11_scratch1, 1);
2046           __ stw(R11_scratch1, simm16_offs, tmp);
2047           __ bind(failed);
2048         }
2049 #endif
2050 
2051         __ nand(tmp, R3_RET, R3_RET);
2052         __ cmpwi(CR0, R3_RET, 0);
2053         __ beq(CR0, *stub->continuation());
2054 
2055 #ifndef PRODUCT
2056         if (PrintC1Statistics) {
2057           address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2058           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2059           __ lwz(R11_scratch1, simm16_offs, tmp);
2060           __ addi(R11_scratch1, R11_scratch1, 1);
2061           __ stw(R11_scratch1, simm16_offs, tmp);
2062         }
2063 #endif
2064 
2065         __ subf(length, tmp, length);
2066         __ add(src_pos, tmp, src_pos);
2067         __ add(dst_pos, tmp, dst_pos);
2068       }
2069     }
2070     __ bind(slow);
2071     __ b(*stub->entry());
2072   }
2073   __ bind(cont);
2074 
2075 #ifdef ASSERT
2076   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2077     // Sanity check the known type with the incoming class. For the
2078     // primitive case the types must match exactly with src.klass and
2079     // dst.klass each exactly matching the default type. For the
2080     // object array case, if no type check is needed then either the
2081     // dst type is exactly the expected type and the src type is a
2082     // subtype which we can't check or src is the same array as dst
2083     // but not necessarily exactly of type default_type.
2084     Label known_ok, halt;
2085     metadata2reg(default_type->constant_encoding(), tmp);
2086     __ cmp_klass(CR0, dst, tmp, R11_scratch1, R12_scratch2);
2087     if (basic_type != T_OBJECT) {
2088       __ bne(CR0, halt);
2089       __ cmp_klass(CR0, src, tmp, R11_scratch1, R12_scratch2);
2090       __ beq(CR0, known_ok);
2091     } else {
2092       __ beq(CR0, known_ok);
2093       __ cmpw(CR0, src, dst);
2094       __ beq(CR0, known_ok);
2095     }
2096     __ bind(halt);
2097     __ stop("incorrect type information in arraycopy");
2098     __ bind(known_ok);
2099   }
2100 #endif
2101 
2102 #ifndef PRODUCT
2103   if (PrintC1Statistics) {
2104     address counter = Runtime1::arraycopy_count_address(basic_type);
2105     int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2106     __ lwz(R11_scratch1, simm16_offs, tmp);
2107     __ addi(R11_scratch1, R11_scratch1, 1);
2108     __ stw(R11_scratch1, simm16_offs, tmp);
2109   }
2110 #endif
2111 
2112   Register src_ptr = R3_ARG1;
2113   Register dst_ptr = R4_ARG2;
2114   Register len     = R5_ARG3;
2115 
2116   __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2117   __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2118   if (shift == 0) {
2119     __ add(src_ptr, src_pos, src_ptr);
2120     __ add(dst_ptr, dst_pos, dst_ptr);
2121   } else {
2122     __ sldi(tmp, src_pos, shift);
2123     __ sldi(tmp2, dst_pos, shift);
2124     __ add(src_ptr, tmp, src_ptr);
2125     __ add(dst_ptr, tmp2, dst_ptr);
2126   }
2127 
2128   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2129   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2130   const char *name;
2131   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2132 
2133   // Arraycopy stubs takes a length in number of elements, so don't scale it.
2134   __ mr(len, length);
2135   __ call_c(entry, relocInfo::runtime_call_type);
2136 
2137   if (stub != nullptr) {
2138     __ bind(*stub->continuation());
2139   }
2140 }
2141 
2142 
2143 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2144   if (dest->is_single_cpu()) {
2145     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2146 #ifdef _LP64
2147     if (left->type() == T_OBJECT) {
2148       switch (code) {
2149         case lir_shl:  __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2150         case lir_shr:  __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2151         case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2152         default: ShouldNotReachHere();
2153       }
2154     } else
2155 #endif
2156       switch (code) {
2157         case lir_shl:  __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2158         case lir_shr:  __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2159         case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2160         default: ShouldNotReachHere();
2161       }
2162   } else {
2163     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2164     switch (code) {
2165       case lir_shl:  __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2166       case lir_shr:  __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2167       case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2168       default: ShouldNotReachHere();
2169     }
2170   }
2171 }
2172 
2173 
2174 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2175 #ifdef _LP64
2176   if (left->type() == T_OBJECT) {
2177     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2178     if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2179     else {
2180       switch (code) {
2181         case lir_shl:  __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2182         case lir_shr:  __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2183         case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2184         default: ShouldNotReachHere();
2185       }
2186     }
2187     return;
2188   }
2189 #endif
2190 
2191   if (dest->is_single_cpu()) {
2192     count = count & 0x1F; // Java spec
2193     if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2194     else {
2195       switch (code) {
2196         case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2197         case lir_shr:  __ srawi(dest->as_register(), left->as_register(), count); break;
2198         case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2199         default: ShouldNotReachHere();
2200       }
2201     }
2202   } else if (dest->is_double_cpu()) {
2203     count = count & 63; // Java spec
2204     if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2205     else {
2206       switch (code) {
2207         case lir_shl:  __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2208         case lir_shr:  __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2209         case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2210         default: ShouldNotReachHere();
2211       }
2212     }
2213   } else {
2214     ShouldNotReachHere();
2215   }
2216 }
2217 
2218 
2219 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2220   if (op->init_check()) {
2221     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2222       explicit_null_check(op->klass()->as_register(), op->stub()->info());
2223     } else {
2224       add_debug_info_for_null_check_here(op->stub()->info());
2225     }
2226     __ lbz(op->tmp1()->as_register(),
2227            in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2228     // acquire barrier included in membar_storestore() which follows the allocation immediately.
2229     __ cmpwi(CR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2230     __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CR0, Assembler::equal), *op->stub()->entry());
2231   }
2232   __ allocate_object(op->obj()->as_register(),
2233                      op->tmp1()->as_register(),
2234                      op->tmp2()->as_register(),
2235                      op->tmp3()->as_register(),
2236                      op->header_size(),
2237                      op->object_size(),
2238                      op->klass()->as_register(),
2239                      *op->stub()->entry());
2240 
2241   __ bind(*op->stub()->continuation());
2242   __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2243 }
2244 
2245 
2246 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2247   LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2248   if (UseSlowPath ||
2249       (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2250       (!UseFastNewTypeArray   && (!is_reference_type(op->type())))) {
2251     __ b(*op->stub()->entry());
2252   } else {
2253     __ allocate_array(op->obj()->as_register(),
2254                       op->len()->as_register(),
2255                       op->tmp1()->as_register(),
2256                       op->tmp2()->as_register(),
2257                       op->tmp3()->as_register(),
2258                       arrayOopDesc::base_offset_in_bytes(op->type()),
2259                       type2aelembytes(op->type()),
2260                       op->klass()->as_register(),
2261                       *op->stub()->entry(),
2262                       op->zero_array());
2263   }
2264   __ bind(*op->stub()->continuation());
2265 }
2266 
2267 
2268 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2269                                         ciMethodData *md, ciProfileData *data,
2270                                         Register recv, Register tmp1, Label* update_done) {
2271   uint i;
2272   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2273     Label next_test;
2274     // See if the receiver is receiver[n].
2275     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2276     __ verify_klass_ptr(tmp1);
2277     __ cmpd(CR0, recv, tmp1);
2278     __ bne(CR0, next_test);
2279 
2280     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2281     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2282     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2283     __ b(*update_done);
2284 
2285     __ bind(next_test);
2286   }
2287 
2288   // Didn't find receiver; find next empty slot and fill it in.
2289   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2290     Label next_test;
2291     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2292     __ cmpdi(CR0, tmp1, 0);
2293     __ bne(CR0, next_test);
2294     __ li(tmp1, DataLayout::counter_increment);
2295     __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2296     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2297     __ b(*update_done);
2298 
2299     __ bind(next_test);
2300   }
2301 }
2302 
2303 
2304 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2305                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2306   md = method->method_data_or_null();
2307   assert(md != nullptr, "Sanity");
2308   data = md->bci_to_data(bci);
2309   assert(data != nullptr,       "need data for checkcast");
2310   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2311   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2312     // The offset is large so bias the mdo by the base of the slot so
2313     // that the ld can use simm16s to reference the slots of the data.
2314     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2315   }
2316 }
2317 
2318 
2319 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2320   const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2321   Register k_RInfo = op->tmp1()->as_register();
2322   Register klass_RInfo = op->tmp2()->as_register();
2323   Register Rtmp1 = op->tmp3()->as_register();
2324   Register dst = op->result_opr()->as_register();
2325   ciKlass* k = op->klass();
2326   bool should_profile = op->should_profile();
2327   // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2328   bool reg_conflict = false;
2329   if (obj == k_RInfo) {
2330     k_RInfo = dst;
2331     reg_conflict = true;
2332   } else if (obj == klass_RInfo) {
2333     klass_RInfo = dst;
2334     reg_conflict = true;
2335   } else if (obj == Rtmp1) {
2336     Rtmp1 = dst;
2337     reg_conflict = true;
2338   }
2339   assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2340 
2341   ciMethodData* md = nullptr;
2342   ciProfileData* data = nullptr;
2343   int mdo_offset_bias = 0;
2344   if (should_profile) {
2345     ciMethod* method = op->profiled_method();
2346     assert(method != nullptr, "Should have method");
2347     setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2348 
2349     Register mdo      = k_RInfo;
2350     Register data_val = Rtmp1;
2351     Label not_null;
2352     metadata2reg(md->constant_encoding(), mdo);
2353     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2354     __ cmpdi(CR0, obj, 0);
2355     __ bne(CR0, not_null);
2356     __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2357     __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2358     __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2359     __ b(*obj_is_null);
2360     __ bind(not_null);
2361 
2362     Label update_done;
2363     Register recv = klass_RInfo;
2364     __ load_klass(recv, obj);
2365     type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2366     const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2367     __ ld(Rtmp1, slot_offset, mdo);
2368     __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2369     __ std(Rtmp1, slot_offset, mdo);
2370     __ bind(update_done);
2371   } else {
2372     __ cmpdi(CR0, obj, 0);
2373     __ beq(CR0, *obj_is_null);
2374   }
2375 
2376   // get object class
2377   __ load_klass(klass_RInfo, obj);
2378 
2379   if (k->is_loaded()) {
2380     metadata2reg(k->constant_encoding(), k_RInfo);
2381   } else {
2382     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2383   }
2384 
2385   if (op->fast_check()) {
2386     assert_different_registers(klass_RInfo, k_RInfo);
2387     __ cmpd(CR0, k_RInfo, klass_RInfo);
2388     __ beq(CR0, *success);
2389     // Fall through to failure case.
2390   } else {
2391     bool need_slow_path = true;
2392     if (k->is_loaded()) {
2393       if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2394         need_slow_path = false;
2395       }
2396       // Perform the fast part of the checking logic.
2397       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2398                                        failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2399     } else {
2400       // Perform the fast part of the checking logic.
2401       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2402     }
2403     if (!need_slow_path) {
2404       __ b(*success);
2405     } else {
2406       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2407       address entry = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2408       // Stub needs fixed registers (tmp1-3).
2409       Register original_k_RInfo = op->tmp1()->as_register();
2410       Register original_klass_RInfo = op->tmp2()->as_register();
2411       Register original_Rtmp1 = op->tmp3()->as_register();
2412       bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2413       if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2414       __ mr_if_needed(original_k_RInfo, k_RInfo);
2415       __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2416       if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2417       //__ load_const_optimized(original_Rtmp1, entry, R0);
2418       __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2419       __ mtctr(original_Rtmp1);
2420       __ bctrl(); // sets CR0
2421       if (keep_obj_alive) { __ mr(obj, dst); }
2422       __ beq(CR0, *success);
2423       // Fall through to failure case.
2424     }
2425   }
2426 
2427   __ bind(*failure);
2428 }
2429 
2430 
2431 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2432   LIR_Code code = op->code();
2433   if (code == lir_store_check) {
2434     Register value = op->object()->as_register();
2435     Register array = op->array()->as_register();
2436     Register k_RInfo = op->tmp1()->as_register();
2437     Register klass_RInfo = op->tmp2()->as_register();
2438     Register Rtmp1 = op->tmp3()->as_register();
2439     bool should_profile = op->should_profile();
2440 
2441     __ verify_oop(value, FILE_AND_LINE);
2442     CodeStub* stub = op->stub();
2443     // Check if it needs to be profiled.
2444     ciMethodData* md = nullptr;
2445     ciProfileData* data = nullptr;
2446     int mdo_offset_bias = 0;
2447     if (should_profile) {
2448       ciMethod* method = op->profiled_method();
2449       assert(method != nullptr, "Should have method");
2450       setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2451     }
2452 
2453     Label done;
2454 
2455     if (should_profile) {
2456       Label not_null;
2457       Register mdo      = k_RInfo;
2458       Register data_val = Rtmp1;
2459       metadata2reg(md->constant_encoding(), mdo);
2460       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2461       __ cmpdi(CR0, value, 0);
2462       __ bne(CR0, not_null);
2463       __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2464       __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2465       __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2466       __ b(done);
2467       __ bind(not_null);
2468 
2469       Label update_done;
2470       Register recv = klass_RInfo;
2471       __ load_klass(recv, value);
2472       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2473       const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2474       __ ld(Rtmp1, slot_offset, mdo);
2475       __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2476       __ std(Rtmp1, slot_offset, mdo);
2477       __ bind(update_done);
2478     } else {
2479       __ cmpdi(CR0, value, 0);
2480       __ beq(CR0, done);
2481     }
2482     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2483       explicit_null_check(array, op->info_for_exception());
2484     } else {
2485       add_debug_info_for_null_check_here(op->info_for_exception());
2486     }
2487     __ load_klass(k_RInfo, array);
2488     __ load_klass(klass_RInfo, value);
2489 
2490     Label failure;
2491 
2492     // Get instance klass.
2493     __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2494     // Perform the fast part of the checking logic.
2495     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2496 
2497     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2498     const address slow_path = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2499     //__ load_const_optimized(R0, slow_path);
2500     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2501     __ mtctr(R0);
2502     __ bctrl(); // sets CR0
2503     __ beq(CR0, done);
2504 
2505     __ bind(failure);
2506     __ b(*stub->entry());
2507     __ align(32, 12);
2508     __ bind(done);
2509 
2510   } else if (code == lir_checkcast) {
2511     Label success, failure;
2512     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2513     __ b(*op->stub()->entry());
2514     __ align(32, 12);
2515     __ bind(success);
2516     __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2517   } else if (code == lir_instanceof) {
2518     Register dst = op->result_opr()->as_register();
2519     Label success, failure, done;
2520     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2521     __ li(dst, 0);
2522     __ b(done);
2523     __ align(32, 12);
2524     __ bind(success);
2525     __ li(dst, 1);
2526     __ bind(done);
2527   } else {
2528     ShouldNotReachHere();
2529   }
2530 }
2531 
2532 
2533 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2534   Register addr = op->addr()->as_pointer_register();
2535   Register cmp_value = noreg, new_value = noreg;
2536   bool is_64bit = false;
2537 
2538   if (op->code() == lir_cas_long) {
2539     cmp_value = op->cmp_value()->as_register_lo();
2540     new_value = op->new_value()->as_register_lo();
2541     is_64bit = true;
2542   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2543     cmp_value = op->cmp_value()->as_register();
2544     new_value = op->new_value()->as_register();
2545     if (op->code() == lir_cas_obj) {
2546       if (UseCompressedOops) {
2547         Register t1 = op->tmp1()->as_register();
2548         Register t2 = op->tmp2()->as_register();
2549         cmp_value = __ encode_heap_oop(t1, cmp_value);
2550         new_value = __ encode_heap_oop(t2, new_value);
2551       } else {
2552         is_64bit = true;
2553       }
2554     }
2555   } else {
2556     Unimplemented();
2557   }
2558 
2559   // There might be a volatile load before this Unsafe CAS.
2560   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2561     __ sync();
2562   } else {
2563     __ lwsync();
2564   }
2565 
2566   if (is_64bit) {
2567     __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2568                 MacroAssembler::MemBarNone,
2569                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2570                 noreg, nullptr, /*check without ldarx first*/true);
2571   } else {
2572     __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2573                 MacroAssembler::MemBarNone,
2574                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2575                 noreg, nullptr, /*check without ldarx first*/true);
2576   }
2577 
2578   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2579     __ isync();
2580   } else {
2581     __ sync();
2582   }
2583 }
2584 
2585 void LIR_Assembler::breakpoint() {
2586   __ illtrap();
2587 }
2588 
2589 
2590 void LIR_Assembler::push(LIR_Opr opr) {
2591   Unimplemented();
2592 }
2593 
2594 void LIR_Assembler::pop(LIR_Opr opr) {
2595   Unimplemented();
2596 }
2597 
2598 
2599 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2600   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2601   Register dst = dst_opr->as_register();
2602   Register reg = mon_addr.base();
2603   int offset = mon_addr.disp();
2604   // Compute pointer to BasicLock.
2605   __ add_const_optimized(dst, reg, offset);
2606 }
2607 
2608 
2609 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2610   Register obj = op->obj_opr()->as_register();
2611   Register hdr = op->hdr_opr()->as_register();
2612   Register lock = op->lock_opr()->as_register();
2613 
2614   // Obj may not be an oop.
2615   if (op->code() == lir_lock) {
2616     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2617     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2618     // Add debug info for NullPointerException only if one is possible.
2619     if (op->info() != nullptr) {
2620       if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2621         explicit_null_check(obj, op->info());
2622       } else {
2623         add_debug_info_for_null_check_here(op->info());
2624       }
2625     }
2626     __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2627   } else {
2628     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2629     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2630     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2631   }
2632   __ bind(*op->stub()->continuation());
2633 }
2634 
2635 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2636   Register obj = op->obj()->as_pointer_register();
2637   Register result = op->result_opr()->as_pointer_register();
2638 
2639   CodeEmitInfo* info = op->info();
2640   if (info != nullptr) {
2641     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2642       explicit_null_check(obj, info);
2643     } else {
2644       add_debug_info_for_null_check_here(info);
2645     }
2646   }
2647 
2648   __ load_klass(result, obj);
2649 }
2650 
2651 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2652   ciMethod* method = op->profiled_method();
2653   int bci          = op->profiled_bci();
2654   ciMethod* callee = op->profiled_callee();
2655 
2656   // Update counter for all call types.
2657   ciMethodData* md = method->method_data_or_null();
2658   assert(md != nullptr, "Sanity");
2659   ciProfileData* data = md->bci_to_data(bci);
2660   assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2661   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2662   Register mdo = op->mdo()->as_register();
2663 #ifdef _LP64
2664   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2665   Register tmp1 = op->tmp1()->as_register_lo();
2666 #else
2667   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2668   Register tmp1 = op->tmp1()->as_register();
2669 #endif
2670   metadata2reg(md->constant_encoding(), mdo);
2671   int mdo_offset_bias = 0;
2672   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2673                             data->size_in_bytes())) {
2674     // The offset is large so bias the mdo by the base of the slot so
2675     // that the ld can use simm16s to reference the slots of the data.
2676     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2677     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2678   }
2679 
2680   // Perform additional virtual call profiling for invokevirtual and
2681   // invokeinterface bytecodes
2682   if (op->should_profile_receiver_type()) {
2683     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2684     Register recv = op->recv()->as_register();
2685     assert_different_registers(mdo, tmp1, recv);
2686     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2687     ciKlass* known_klass = op->known_holder();
2688     if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2689       // We know the type that will be seen at this call site; we can
2690       // statically update the MethodData* rather than needing to do
2691       // dynamic tests on the receiver type.
2692 
2693       // NOTE: we should probably put a lock around this search to
2694       // avoid collisions by concurrent compilations.
2695       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2696       uint i;
2697       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2698         ciKlass* receiver = vc_data->receiver(i);
2699         if (known_klass->equals(receiver)) {
2700           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2701           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2702           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2703           return;
2704         }
2705       }
2706 
2707       // Receiver type not found in profile data; select an empty slot.
2708 
2709       // Note that this is less efficient than it should be because it
2710       // always does a write to the receiver part of the
2711       // VirtualCallData rather than just the first time.
2712       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2713         ciKlass* receiver = vc_data->receiver(i);
2714         if (receiver == nullptr) {
2715           metadata2reg(known_klass->constant_encoding(), tmp1);
2716           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2717 
2718           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2719           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2720           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2721           return;
2722         }
2723       }
2724     } else {
2725       __ load_klass(recv, recv);
2726       Label update_done;
2727       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2728       // Receiver did not match any saved receiver and there is no empty row for it.
2729       // Increment total counter to indicate polymorphic case.
2730       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2731       __ addi(tmp1, tmp1, DataLayout::counter_increment);
2732       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2733 
2734       __ bind(update_done);
2735     }
2736   } else {
2737     // Static call
2738     __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2739     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2740     __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2741   }
2742 }
2743 
2744 
2745 void LIR_Assembler::align_backward_branch_target() {
2746   __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2747 }
2748 
2749 
2750 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2751   Unimplemented();
2752 }
2753 
2754 
2755 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2756   // tmp must be unused
2757   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2758   assert(left->is_register(), "can only handle registers");
2759 
2760   if (left->is_single_cpu()) {
2761     __ neg(dest->as_register(), left->as_register());
2762   } else if (left->is_single_fpu()) {
2763     __ fneg(dest->as_float_reg(), left->as_float_reg());
2764   } else if (left->is_double_fpu()) {
2765     __ fneg(dest->as_double_reg(), left->as_double_reg());
2766   } else {
2767     assert (left->is_double_cpu(), "Must be a long");
2768     __ neg(dest->as_register_lo(), left->as_register_lo());
2769   }
2770 }
2771 
2772 
2773 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2774                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2775   // Stubs: Called via rt_call, but dest is a stub address (no FunctionDescriptor).
2776   if (dest == Runtime1::entry_for(StubId::c1_register_finalizer_id) ||
2777       dest == Runtime1::entry_for(StubId::c1_new_multi_array_id   ) ||
2778       dest == Runtime1::entry_for(StubId::c1_is_instance_of_id    )) {
2779     assert(CodeCache::contains(dest), "simplified call is only for special C1 stubs");
2780     //__ load_const_optimized(R0, dest);
2781     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2782     __ mtctr(R0);
2783     __ bctrl();
2784     if (info != nullptr) {
2785       add_call_info_here(info);
2786       __ post_call_nop();
2787     }
2788     return;
2789   }
2790 
2791   __ call_c(dest, relocInfo::runtime_call_type);
2792   assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2793   if (info != nullptr) {
2794     add_call_info_here(info);
2795     __ post_call_nop();
2796   }
2797 }
2798 
2799 
2800 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2801   ShouldNotReachHere(); // Not needed on _LP64.
2802 }
2803 
2804 void LIR_Assembler::membar() {
2805   __ fence();
2806 }
2807 
2808 void LIR_Assembler::membar_acquire() {
2809   __ acquire();
2810 }
2811 
2812 void LIR_Assembler::membar_release() {
2813   __ release();
2814 }
2815 
2816 void LIR_Assembler::membar_loadload() {
2817   __ membar(Assembler::LoadLoad);
2818 }
2819 
2820 void LIR_Assembler::membar_storestore() {
2821   __ membar(Assembler::StoreStore);
2822 }
2823 
2824 void LIR_Assembler::membar_loadstore() {
2825   __ membar(Assembler::LoadStore);
2826 }
2827 
2828 void LIR_Assembler::membar_storeload() {
2829   __ membar(Assembler::StoreLoad);
2830 }
2831 
2832 void LIR_Assembler::on_spin_wait() {
2833   Unimplemented();
2834 }
2835 
2836 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2837   LIR_Address* addr = addr_opr->as_address_ptr();
2838   assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2839 
2840   if (addr->index()->is_illegal()) {
2841     if (patch_code != lir_patch_none) {
2842       PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2843       __ load_const32(R0, 0); // patchable int
2844       __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2845       patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2846     } else {
2847       __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2848     }
2849   } else {
2850     assert(patch_code == lir_patch_none, "Patch code not supported");
2851     assert(addr->disp() == 0, "can't have both: index and disp");
2852     __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2853   }
2854 }
2855 
2856 
2857 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2858   ShouldNotReachHere();
2859 }
2860 
2861 
2862 #ifdef ASSERT
2863 // Emit run-time assertion.
2864 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2865   Unimplemented();
2866 }
2867 #endif
2868 
2869 
2870 void LIR_Assembler::peephole(LIR_List* lir) {
2871   // Optimize instruction pairs before emitting.
2872   LIR_OpList* inst = lir->instructions_list();
2873   for (int i = 1; i < inst->length(); i++) {
2874     LIR_Op* op = inst->at(i);
2875 
2876     // 2 register-register-moves
2877     if (op->code() == lir_move) {
2878       LIR_Opr in2  = ((LIR_Op1*)op)->in_opr(),
2879               res2 = ((LIR_Op1*)op)->result_opr();
2880       if (in2->is_register() && res2->is_register()) {
2881         LIR_Op* prev = inst->at(i - 1);
2882         if (prev && prev->code() == lir_move) {
2883           LIR_Opr in1  = ((LIR_Op1*)prev)->in_opr(),
2884                   res1 = ((LIR_Op1*)prev)->result_opr();
2885           if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2886             inst->remove_at(i);
2887           }
2888         }
2889       }
2890     }
2891 
2892   }
2893   return;
2894 }
2895 
2896 
2897 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2898   const LIR_Address *addr = src->as_address_ptr();
2899   assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2900   const Register Rptr = addr->base()->as_pointer_register(),
2901                  Rtmp = tmp->as_register();
2902   Register Robj = noreg;
2903   if (data->is_oop()) {
2904     if (UseCompressedOops) {
2905       Robj = __ encode_heap_oop(Rtmp, data->as_register());
2906     } else {
2907       Robj = data->as_register();
2908       if (Robj == dest->as_register()) { // May happen with ZGC.
2909         __ mr(Rtmp, Robj);
2910         Robj = Rtmp;
2911       }
2912     }
2913   }
2914 
2915   // There might be a volatile load before this Unsafe OP.
2916   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2917     __ sync();
2918   } else {
2919     __ lwsync();
2920   }
2921 
2922   Label Lretry;
2923   __ bind(Lretry);
2924 
2925   if (data->type() == T_INT) {
2926     const Register Rold = dest->as_register(),
2927                    Rsrc = data->as_register();
2928     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2929     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2930     if (code == lir_xadd) {
2931       __ add(Rtmp, Rsrc, Rold);
2932       __ stwcx_(Rtmp, Rptr);
2933     } else {
2934       __ stwcx_(Rsrc, Rptr);
2935     }
2936   } else if (data->is_oop()) {
2937     assert(code == lir_xchg, "xadd for oops");
2938     const Register Rold = dest->as_register();
2939     assert_different_registers(Rptr, Rold, Robj);
2940     if (UseCompressedOops) {
2941       __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2942       __ stwcx_(Robj, Rptr);
2943     } else {
2944       __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2945       __ stdcx_(Robj, Rptr);
2946     }
2947   } else if (data->type() == T_LONG) {
2948     const Register Rold = dest->as_register_lo(),
2949                    Rsrc = data->as_register_lo();
2950     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2951     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2952     if (code == lir_xadd) {
2953       __ add(Rtmp, Rsrc, Rold);
2954       __ stdcx_(Rtmp, Rptr);
2955     } else {
2956       __ stdcx_(Rsrc, Rptr);
2957     }
2958   } else {
2959     ShouldNotReachHere();
2960   }
2961 
2962   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2963     __ bne_predict_not_taken(CR0, Lretry);
2964   } else {
2965     __ bne(                  CR0, Lretry);
2966   }
2967 
2968   if (UseCompressedOops && data->is_oop()) {
2969     __ decode_heap_oop(dest->as_register());
2970   }
2971 
2972   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2973     __ isync();
2974   } else {
2975     __ sync();
2976   }
2977 }
2978 
2979 
2980 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2981   Register obj = op->obj()->as_register();
2982   Register tmp = op->tmp()->as_pointer_register();
2983   LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
2984   ciKlass* exact_klass = op->exact_klass();
2985   intptr_t current_klass = op->current_klass();
2986   bool not_null = op->not_null();
2987   bool no_conflict = op->no_conflict();
2988 
2989   Label Lupdate, Ldo_update, Ldone;
2990 
2991   bool do_null = !not_null;
2992   bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2993   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2994 
2995   assert(do_null || do_update, "why are we here?");
2996   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2997 
2998   __ verify_oop(obj, FILE_AND_LINE);
2999 
3000   if (do_null) {
3001     if (!TypeEntries::was_null_seen(current_klass)) {
3002       __ cmpdi(CR0, obj, 0);
3003       __ bne(CR0, Lupdate);
3004       __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3005       __ ori(R0, R0, TypeEntries::null_seen);
3006       if (do_update) {
3007         __ b(Ldo_update);
3008       } else {
3009         __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3010       }
3011     } else {
3012       if (do_update) {
3013         __ cmpdi(CR0, obj, 0);
3014         __ beq(CR0, Ldone);
3015       }
3016     }
3017 #ifdef ASSERT
3018   } else {
3019     __ cmpdi(CR0, obj, 0);
3020     __ bne(CR0, Lupdate);
3021     __ stop("unexpected null obj");
3022 #endif
3023   }
3024 
3025   __ bind(Lupdate);
3026   if (do_update) {
3027     Label Lnext;
3028     const Register klass = R29_TOC; // kill and reload
3029     bool klass_reg_used = false;
3030 #ifdef ASSERT
3031     if (exact_klass != nullptr) {
3032       Label ok;
3033       klass_reg_used = true;
3034       __ load_klass(klass, obj);
3035       metadata2reg(exact_klass->constant_encoding(), R0);
3036       __ cmpd(CR0, klass, R0);
3037       __ beq(CR0, ok);
3038       __ stop("exact klass and actual klass differ");
3039       __ bind(ok);
3040     }
3041 #endif
3042 
3043     if (!no_conflict) {
3044       if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3045         klass_reg_used = true;
3046         if (exact_klass != nullptr) {
3047           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3048           metadata2reg(exact_klass->constant_encoding(), klass);
3049         } else {
3050           __ load_klass(klass, obj);
3051           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3052         }
3053 
3054         // Like InterpreterMacroAssembler::profile_obj_type
3055         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3056         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3057         __ cmpd(CR1, R0, klass);
3058         // Klass seen before, nothing to do (regardless of unknown bit).
3059         //beq(CR1, do_nothing);
3060 
3061         __ andi_(R0, tmp, TypeEntries::type_unknown);
3062         // Already unknown. Nothing to do anymore.
3063         //bne(CR0, do_nothing);
3064         __ crorc(CR0, Assembler::equal, CR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3065         __ beq(CR0, Lnext);
3066 
3067         if (TypeEntries::is_type_none(current_klass)) {
3068           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3069           __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3070           __ beq(CR0, Ldo_update); // First time here. Set profile type.
3071         }
3072 
3073       } else {
3074         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3075                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3076 
3077         __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3078         __ andi_(R0, tmp, TypeEntries::type_unknown);
3079         // Already unknown. Nothing to do anymore.
3080         __ bne(CR0, Lnext);
3081       }
3082 
3083       // Different than before. Cannot keep accurate profile.
3084       __ ori(R0, tmp, TypeEntries::type_unknown);
3085     } else {
3086       // There's a single possible klass at this profile point
3087       assert(exact_klass != nullptr, "should be");
3088       __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3089 
3090       if (TypeEntries::is_type_none(current_klass)) {
3091         klass_reg_used = true;
3092         metadata2reg(exact_klass->constant_encoding(), klass);
3093 
3094         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3095         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3096         __ cmpd(CR1, R0, klass);
3097         // Klass seen before, nothing to do (regardless of unknown bit).
3098         __ beq(CR1, Lnext);
3099 #ifdef ASSERT
3100         {
3101           Label ok;
3102           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3103           __ beq(CR0, ok); // First time here.
3104 
3105           __ stop("unexpected profiling mismatch");
3106           __ bind(ok);
3107         }
3108 #endif
3109         // First time here. Set profile type.
3110         __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3111       } else {
3112         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3113                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3114 
3115         // Already unknown. Nothing to do anymore.
3116         __ andi_(R0, tmp, TypeEntries::type_unknown);
3117         __ bne(CR0, Lnext);
3118 
3119         // Different than before. Cannot keep accurate profile.
3120         __ ori(R0, tmp, TypeEntries::type_unknown);
3121       }
3122     }
3123 
3124     __ bind(Ldo_update);
3125     __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3126 
3127     __ bind(Lnext);
3128     if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3129   }
3130   __ bind(Ldone);
3131 }
3132 
3133 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3134   Unimplemented();
3135 }
3136 
3137 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3138   assert(op->crc()->is_single_cpu(), "crc must be register");
3139   assert(op->val()->is_single_cpu(), "byte value must be register");
3140   assert(op->result_opr()->is_single_cpu(), "result must be register");
3141   Register crc = op->crc()->as_register();
3142   Register val = op->val()->as_register();
3143   Register res = op->result_opr()->as_register();
3144 
3145   assert_different_registers(val, crc, res);
3146 
3147   __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3148   __ kernel_crc32_singleByteReg(crc, val, res, true);
3149   __ mr(res, crc);
3150 }
3151 
3152 #undef __