1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_ppc.hpp"
37 #include "oops/compressedOops.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/os.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/macros.hpp"
46 #include "utilities/powerOfTwo.hpp"
47
48 #define __ _masm->
49
50
51 const ConditionRegister LIR_Assembler::BOOL_RESULT = CR5;
52
53
54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
55 Unimplemented(); return false; // Currently not used on this platform.
56 }
57
58
59 LIR_Opr LIR_Assembler::receiverOpr() {
60 return FrameMap::R3_oop_opr;
61 }
62
63
64 LIR_Opr LIR_Assembler::osrBufferPointer() {
65 return FrameMap::R3_opr;
66 }
67
68
69 // This specifies the stack pointer decrement needed to build the frame.
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74
75 // Inline cache check: the inline cached class is in inline_cache_reg;
76 // we fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = R20;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
92 __ mtctr(klass);
93 __ bctr();
94
95 __ bind(L_skip_barrier);
96 }
97
98 void LIR_Assembler::osr_entry() {
99 // On-stack-replacement entry sequence:
100 //
101 // 1. Create a new compiled activation.
102 // 2. Initialize local variables in the compiled activation. The expression
103 // stack must be empty at the osr_bci; it is not initialized.
104 // 3. Jump to the continuation address in compiled code to resume execution.
105
106 // OSR entry point
107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
108 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
109 ValueStack* entry_state = osr_entry->end()->state();
110 int number_of_locks = entry_state->locks_size();
111
112 // Create a frame for the compiled activation.
113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
114
115 // OSR buffer is
116 //
117 // locals[nlocals-1..0]
118 // monitors[number_of_locks-1..0]
119 //
120 // Locals is a direct copy of the interpreter frame so in the osr buffer
121 // the first slot in the local array is the last local from the interpreter
122 // and the last slot is local[0] (receiver) from the interpreter.
123 //
124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
126 // in the interpreter frame (the method lock if a sync method).
127
128 // Initialize monitors in the compiled activation.
129 // R3: pointer to osr buffer
130 //
131 // All other registers are dead at this point and the locals will be
132 // copied into place by code emitted in the IR.
133
134 Register OSR_buf = osrBufferPointer()->as_register();
135 {
136 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137
138 const int locals_space = BytesPerWord * method()->max_locals();
139 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
140 bool use_OSR_bias = false;
141
142 if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
143 // Offsets too large for ld instructions. Use bias.
144 __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
145 monitor_offset -= locals_space;
146 use_OSR_bias = true;
147 }
148
149 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
150 // the OSR buffer using 2 word entries: first the lock and then
151 // the oop.
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
154 #ifdef ASSERT
155 // Verify the interpreter's monitor has a non-null object.
156 {
157 Label L;
158 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
159 __ cmpdi(CR0, R0, 0);
160 __ bne(CR0, L);
161 __ stop("locked object is null");
162 __ bind(L);
163 }
164 #endif // ASSERT
165 // Copy the lock field into the compiled activation.
166 Address ml = frame_map()->address_for_monitor_lock(i),
167 mo = frame_map()->address_for_monitor_object(i);
168 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
169 __ ld(R0, slot_offset + 0, OSR_buf);
170 __ std(R0, ml);
171 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
172 __ std(R0, mo);
173 }
174
175 if (use_OSR_bias) {
176 // Restore.
177 __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
178 }
179 }
180 }
181
182
183 int LIR_Assembler::emit_exception_handler() {
184 // Generate code for the exception handler.
185 address handler_base = __ start_a_stub(exception_handler_size());
186
187 if (handler_base == nullptr) {
188 // Not enough space left for the handler.
189 bailout("exception handler overflow");
190 return -1;
191 }
192
193 int offset = code_offset();
194 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(C1StubId::handle_exception_from_callee_id));
195 //__ load_const_optimized(R0, entry_point);
196 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
197 __ mtctr(R0);
198 __ bctr();
199
200 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
201 __ end_a_stub();
202
203 return offset;
204 }
205
206
207 // Emit the code to remove the frame from the stack in the exception
208 // unwind path.
209 int LIR_Assembler::emit_unwind_handler() {
210 _masm->block_comment("Unwind handler");
211
212 int offset = code_offset();
213 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
214 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
215
216 // Fetch the exception from TLS and clear out exception related thread state.
217 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
218 __ li(R0, 0);
219 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
220 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
221
222 __ bind(_unwind_handler_entry);
223 __ verify_not_null_oop(Rexception);
224 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
225
226 // Perform needed unlocking
227 MonitorExitStub* stub = nullptr;
228 if (method()->is_synchronized()) {
229 monitor_address(0, FrameMap::R4_opr);
230 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
231 if (LockingMode == LM_MONITOR) {
232 __ b(*stub->entry());
233 } else {
234 __ unlock_object(R5, R6, R4, *stub->entry());
235 }
236 __ bind(*stub->continuation());
237 }
238
239 if (compilation()->env()->dtrace_method_probes()) {
240 Unimplemented();
241 }
242
243 // Dispatch to the unwind logic.
244 address unwind_stub = Runtime1::entry_for(C1StubId::unwind_exception_id);
245 //__ load_const_optimized(R0, unwind_stub);
246 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
247 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
248 __ mtctr(R0);
249 __ bctr();
250
251 // Emit the slow path assembly.
252 if (stub != nullptr) {
253 stub->emit_code(this);
254 }
255
256 return offset;
257 }
258
259
260 int LIR_Assembler::emit_deopt_handler() {
261 // Generate code for deopt handler.
262 address handler_base = __ start_a_stub(deopt_handler_size());
263
264 if (handler_base == nullptr) {
265 // Not enough space left for the handler.
266 bailout("deopt handler overflow");
267 return -1;
268 }
269
270 int offset = code_offset();
271 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
272
273 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
274 __ end_a_stub();
275
276 return offset;
277 }
278
279
280 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
281 if (o == nullptr) {
282 __ li(reg, 0);
283 } else {
284 AddressLiteral addrlit = __ constant_oop_address(o);
285 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
286 }
287 }
288
289
290 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
291 // Allocate a new index in table to hold the object once it's been patched.
292 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
293 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
294
295 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
296 __ load_const(reg, addrlit, R0);
297
298 patching_epilog(patch, lir_patch_normal, reg, info);
299 }
300
301
302 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
303 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
304 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
305 }
306
307
308 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
309 // Allocate a new index in table to hold the klass once it's been patched.
310 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
311 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
312
313 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
314 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
315 __ load_const(reg, addrlit, R0);
316
317 patching_epilog(patch, lir_patch_normal, reg, info);
318 }
319
320
321 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
322 const bool is_int = result->is_single_cpu();
323 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
324 Register Rdivisor = noreg;
325 Register Rscratch = temp->as_register();
326 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
327 long divisor = -1;
328
329 if (right->is_register()) {
330 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
331 } else {
332 divisor = is_int ? right->as_constant_ptr()->as_jint()
333 : right->as_constant_ptr()->as_jlong();
334 }
335
336 assert(Rdividend != Rscratch, "");
337 assert(Rdivisor != Rscratch, "");
338 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
339
340 if (Rdivisor == noreg) {
341 if (divisor == 1) { // stupid, but can happen
342 if (code == lir_idiv) {
343 __ mr_if_needed(Rresult, Rdividend);
344 } else {
345 __ li(Rresult, 0);
346 }
347
348 } else if (is_power_of_2(divisor)) {
349 // Convert division by a power of two into some shifts and logical operations.
350 int log2 = log2i_exact(divisor);
351
352 // Round towards 0.
353 if (divisor == 2) {
354 if (is_int) {
355 __ srwi(Rscratch, Rdividend, 31);
356 } else {
357 __ srdi(Rscratch, Rdividend, 63);
358 }
359 } else {
360 if (is_int) {
361 __ srawi(Rscratch, Rdividend, 31);
362 } else {
363 __ sradi(Rscratch, Rdividend, 63);
364 }
365 __ clrldi(Rscratch, Rscratch, 64-log2);
366 }
367 __ add(Rscratch, Rdividend, Rscratch);
368
369 if (code == lir_idiv) {
370 if (is_int) {
371 __ srawi(Rresult, Rscratch, log2);
372 } else {
373 __ sradi(Rresult, Rscratch, log2);
374 }
375 } else { // lir_irem
376 __ clrrdi(Rscratch, Rscratch, log2);
377 __ sub(Rresult, Rdividend, Rscratch);
378 }
379
380 } else if (divisor == -1) {
381 if (code == lir_idiv) {
382 __ neg(Rresult, Rdividend);
383 } else {
384 __ li(Rresult, 0);
385 }
386
387 } else {
388 __ load_const_optimized(Rscratch, divisor);
389 if (code == lir_idiv) {
390 if (is_int) {
391 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
392 } else {
393 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
394 }
395 } else {
396 assert(Rscratch != R0, "need both");
397 if (is_int) {
398 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
399 __ mullw(Rscratch, R0, Rscratch);
400 } else {
401 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
402 __ mulld(Rscratch, R0, Rscratch);
403 }
404 __ sub(Rresult, Rdividend, Rscratch);
405 }
406
407 }
408 return;
409 }
410
411 Label regular, done;
412 if (is_int) {
413 __ cmpwi(CR0, Rdivisor, -1);
414 } else {
415 __ cmpdi(CR0, Rdivisor, -1);
416 }
417 __ bne(CR0, regular);
418 if (code == lir_idiv) {
419 __ neg(Rresult, Rdividend);
420 __ b(done);
421 __ bind(regular);
422 if (is_int) {
423 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
424 } else {
425 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
426 }
427 } else { // lir_irem
428 __ li(Rresult, 0);
429 __ b(done);
430 __ bind(regular);
431 if (is_int) {
432 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
433 __ mullw(Rscratch, Rscratch, Rdivisor);
434 } else {
435 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
436 __ mulld(Rscratch, Rscratch, Rdivisor);
437 }
438 __ sub(Rresult, Rdividend, Rscratch);
439 }
440 __ bind(done);
441 }
442
443
444 void LIR_Assembler::emit_op3(LIR_Op3* op) {
445 switch (op->code()) {
446 case lir_idiv:
447 case lir_irem:
448 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
449 op->result_opr(), op->info());
450 break;
451 case lir_fmad:
452 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
453 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
454 break;
455 case lir_fmaf:
456 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
457 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
458 break;
459 default: ShouldNotReachHere(); break;
460 }
461 }
462
463
464 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
465 #ifdef ASSERT
466 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
467 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
468 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
469 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
470 #endif
471
472 Label *L = op->label();
473 if (op->cond() == lir_cond_always) {
474 __ b(*L);
475 } else {
476 Label done;
477 bool is_unordered = false;
478 if (op->code() == lir_cond_float_branch) {
479 assert(op->ublock() != nullptr, "must have unordered successor");
480 is_unordered = true;
481 } else {
482 assert(op->code() == lir_branch, "just checking");
483 }
484
485 bool positive = false;
486 Assembler::Condition cond = Assembler::equal;
487 switch (op->cond()) {
488 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
489 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
490 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
491 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
492 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
493 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
494 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
495 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
496 default: ShouldNotReachHere();
497 }
498 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
499 int bi = Assembler::bi0(BOOL_RESULT, cond);
500 if (is_unordered) {
501 if (positive) {
502 if (op->ublock() == op->block()) {
503 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
504 }
505 } else {
506 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
507 }
508 }
509 __ bc_far_optimized(bo, bi, *L);
510 __ bind(done);
511 }
512 }
513
514
515 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
516 Bytecodes::Code code = op->bytecode();
517 LIR_Opr src = op->in_opr(),
518 dst = op->result_opr();
519
520 switch(code) {
521 case Bytecodes::_i2l: {
522 __ extsw(dst->as_register_lo(), src->as_register());
523 break;
524 }
525 case Bytecodes::_l2i: {
526 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
527 break;
528 }
529 case Bytecodes::_i2b: {
530 __ extsb(dst->as_register(), src->as_register());
531 break;
532 }
533 case Bytecodes::_i2c: {
534 __ clrldi(dst->as_register(), src->as_register(), 64-16);
535 break;
536 }
537 case Bytecodes::_i2s: {
538 __ extsh(dst->as_register(), src->as_register());
539 break;
540 }
541 case Bytecodes::_i2d:
542 case Bytecodes::_l2d: {
543 bool src_in_memory = !VM_Version::has_mtfprd();
544 FloatRegister rdst = dst->as_double_reg();
545 FloatRegister rsrc;
546 if (src_in_memory) {
547 rsrc = src->as_double_reg(); // via mem
548 } else {
549 // move src to dst register
550 if (code == Bytecodes::_i2d) {
551 __ mtfprwa(rdst, src->as_register());
552 } else {
553 __ mtfprd(rdst, src->as_register_lo());
554 }
555 rsrc = rdst;
556 }
557 __ fcfid(rdst, rsrc);
558 break;
559 }
560 case Bytecodes::_i2f:
561 case Bytecodes::_l2f: {
562 bool src_in_memory = !VM_Version::has_mtfprd();
563 FloatRegister rdst = dst->as_float_reg();
564 FloatRegister rsrc;
565 if (src_in_memory) {
566 rsrc = src->as_double_reg(); // via mem
567 } else {
568 // move src to dst register
569 if (code == Bytecodes::_i2f) {
570 __ mtfprwa(rdst, src->as_register());
571 } else {
572 __ mtfprd(rdst, src->as_register_lo());
573 }
574 rsrc = rdst;
575 }
576 if (VM_Version::has_fcfids()) {
577 __ fcfids(rdst, rsrc);
578 } else {
579 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
580 __ fcfid(rdst, rsrc);
581 __ frsp(rdst, rdst);
582 }
583 break;
584 }
585 case Bytecodes::_f2d: {
586 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
587 break;
588 }
589 case Bytecodes::_d2f: {
590 __ frsp(dst->as_float_reg(), src->as_double_reg());
591 break;
592 }
593 case Bytecodes::_d2i:
594 case Bytecodes::_f2i: {
595 bool dst_in_memory = !VM_Version::has_mtfprd();
596 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
597 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
598 Label L;
599 // Result must be 0 if value is NaN; test by comparing value to itself.
600 __ fcmpu(CR0, rsrc, rsrc);
601 if (dst_in_memory) {
602 __ li(R0, 0); // 0 in case of NAN
603 __ std(R0, addr);
604 } else {
605 __ li(dst->as_register(), 0);
606 }
607 __ bso(CR0, L);
608 __ fctiwz(rsrc, rsrc); // USE_KILL
609 if (dst_in_memory) {
610 __ stfd(rsrc, addr.disp(), addr.base());
611 } else {
612 __ mffprd(dst->as_register(), rsrc);
613 }
614 __ bind(L);
615 break;
616 }
617 case Bytecodes::_d2l:
618 case Bytecodes::_f2l: {
619 bool dst_in_memory = !VM_Version::has_mtfprd();
620 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
621 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
622 Label L;
623 // Result must be 0 if value is NaN; test by comparing value to itself.
624 __ fcmpu(CR0, rsrc, rsrc);
625 if (dst_in_memory) {
626 __ li(R0, 0); // 0 in case of NAN
627 __ std(R0, addr);
628 } else {
629 __ li(dst->as_register_lo(), 0);
630 }
631 __ bso(CR0, L);
632 __ fctidz(rsrc, rsrc); // USE_KILL
633 if (dst_in_memory) {
634 __ stfd(rsrc, addr.disp(), addr.base());
635 } else {
636 __ mffprd(dst->as_register_lo(), rsrc);
637 }
638 __ bind(L);
639 break;
640 }
641
642 default: ShouldNotReachHere();
643 }
644 }
645
646
647 void LIR_Assembler::align_call(LIR_Code) {
648 // do nothing since all instructions are word aligned on ppc
649 }
650
651
652 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
653 int start_offset = __ offset();
654 // Put the entry point as a constant into the constant pool.
655 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
656 if (entry_point_toc_addr == nullptr) {
657 bailout("const section overflow");
658 return false;
659 }
660 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
661
662 // Emit the trampoline stub which will be related to the branch-and-link below.
663 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
664 if (!stub) {
665 bailout("no space for trampoline stub");
666 return false;
667 }
668 return true;
669 }
670
671
672 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
673 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
674
675 bool success = emit_trampoline_stub_for_call(op->addr());
676 if (!success) { return; }
677
678 __ relocate(rtype);
679 // Note: At this point we do not have the address of the trampoline
680 // stub, and the entry point might be too far away for bl, so __ pc()
681 // serves as dummy and the bl will be patched later.
682 __ code()->set_insts_mark();
683 __ bl(__ pc());
684 add_call_info(code_offset(), op->info());
685 __ post_call_nop();
686 }
687
688
689 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
690 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
691
692 // Virtual call relocation will point to ic load.
693 address virtual_call_meta_addr = __ pc();
694 // Load a clear inline cache.
695 AddressLiteral empty_ic((address) Universe::non_oop_word());
696 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
697 if (!success) {
698 bailout("const section overflow");
699 return;
700 }
701 // Call to fixup routine. Fixup routine uses ScopeDesc info
702 // to determine who we intended to call.
703 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
704
705 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
706 if (!success) { return; }
707
708 // Note: At this point we do not have the address of the trampoline
709 // stub, and the entry point might be too far away for bl, so __ pc()
710 // serves as dummy and the bl will be patched later.
711 __ bl(__ pc());
712 add_call_info(code_offset(), op->info());
713 __ post_call_nop();
714 }
715
716 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
717 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
718 __ null_check(addr, stub->entry());
719 append_code_stub(stub);
720 }
721
722
723 // Attention: caller must encode oop if needed
724 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
725 int store_offset;
726 if (!Assembler::is_simm16(offset)) {
727 // For offsets larger than a simm16 we setup the offset.
728 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
729 __ load_const_optimized(R0, offset);
730 store_offset = store(from_reg, base, R0, type, wide);
731 } else {
732 store_offset = code_offset();
733 switch (type) {
734 case T_BOOLEAN: // fall through
735 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
736 case T_CHAR :
737 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
738 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
739 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
740 case T_ADDRESS:
741 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
742 case T_ARRAY : // fall through
743 case T_OBJECT:
744 {
745 if (UseCompressedOops && !wide) {
746 // Encoding done in caller
747 __ stw(from_reg->as_register(), offset, base);
748 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
749 } else {
750 __ std(from_reg->as_register(), offset, base);
751 if (VerifyOops) {
752 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
753 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
754 }
755 }
756 break;
757 }
758 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
759 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
760 default : ShouldNotReachHere();
761 }
762 }
763 return store_offset;
764 }
765
766
767 // Attention: caller must encode oop if needed
768 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
769 int store_offset = code_offset();
770 switch (type) {
771 case T_BOOLEAN: // fall through
772 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
773 case T_CHAR :
774 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
775 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
776 case T_LONG :
777 #ifdef _LP64
778 __ stdx(from_reg->as_register_lo(), base, disp);
779 #else
780 Unimplemented();
781 #endif
782 break;
783 case T_ADDRESS:
784 __ stdx(from_reg->as_register(), base, disp);
785 break;
786 case T_ARRAY : // fall through
787 case T_OBJECT:
788 {
789 if (UseCompressedOops && !wide) {
790 // Encoding done in caller.
791 __ stwx(from_reg->as_register(), base, disp);
792 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
793 } else {
794 __ stdx(from_reg->as_register(), base, disp);
795 if (VerifyOops) {
796 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
797 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
798 }
799 }
800 break;
801 }
802 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
803 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
804 default : ShouldNotReachHere();
805 }
806 return store_offset;
807 }
808
809
810 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
811 int load_offset;
812 if (!Assembler::is_simm16(offset)) {
813 // For offsets larger than a simm16 we setup the offset.
814 __ load_const_optimized(R0, offset);
815 load_offset = load(base, R0, to_reg, type, wide);
816 } else {
817 load_offset = code_offset();
818 switch(type) {
819 case T_BOOLEAN: // fall through
820 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
821 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
822 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
823 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
824 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
825 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
826 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
827 case T_ADDRESS:
828 __ ld(to_reg->as_register(), offset, base);
829 break;
830 case T_ARRAY : // fall through
831 case T_OBJECT:
832 {
833 if (UseCompressedOops && !wide) {
834 __ lwz(to_reg->as_register(), offset, base);
835 __ decode_heap_oop(to_reg->as_register());
836 } else {
837 __ ld(to_reg->as_register(), offset, base);
838 }
839 break;
840 }
841 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
842 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
843 default : ShouldNotReachHere();
844 }
845 }
846 return load_offset;
847 }
848
849
850 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
851 int load_offset = code_offset();
852 switch(type) {
853 case T_BOOLEAN: // fall through
854 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
855 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
856 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
857 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
858 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
859 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
860 case T_ARRAY : // fall through
861 case T_OBJECT:
862 {
863 if (UseCompressedOops && !wide) {
864 __ lwzx(to_reg->as_register(), base, disp);
865 __ decode_heap_oop(to_reg->as_register());
866 } else {
867 __ ldx(to_reg->as_register(), base, disp);
868 }
869 break;
870 }
871 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
872 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
873 case T_LONG :
874 #ifdef _LP64
875 __ ldx(to_reg->as_register_lo(), base, disp);
876 #else
877 Unimplemented();
878 #endif
879 break;
880 default : ShouldNotReachHere();
881 }
882 return load_offset;
883 }
884
885
886 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
887 LIR_Const* c = src->as_constant_ptr();
888 Register src_reg = R0;
889 switch (c->type()) {
890 case T_INT:
891 case T_FLOAT: {
892 int value = c->as_jint_bits();
893 __ load_const_optimized(src_reg, value);
894 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
895 __ stw(src_reg, addr);
896 break;
897 }
898 case T_ADDRESS: {
899 int value = c->as_jint_bits();
900 __ load_const_optimized(src_reg, value);
901 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
902 __ std(src_reg, addr);
903 break;
904 }
905 case T_OBJECT: {
906 jobject2reg(c->as_jobject(), src_reg);
907 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
908 __ std(src_reg, addr);
909 break;
910 }
911 case T_LONG:
912 case T_DOUBLE: {
913 int value = c->as_jlong_bits();
914 __ load_const_optimized(src_reg, value);
915 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
916 __ std(src_reg, addr);
917 break;
918 }
919 default:
920 Unimplemented();
921 }
922 }
923
924
925 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
926 LIR_Const* c = src->as_constant_ptr();
927 LIR_Address* addr = dest->as_address_ptr();
928 Register base = addr->base()->as_pointer_register();
929 LIR_Opr tmp = LIR_OprFact::illegalOpr;
930 int offset = -1;
931 // Null check for large offsets in LIRGenerator::do_StoreField.
932 bool needs_explicit_null_check = !ImplicitNullChecks;
933
934 if (info != nullptr && needs_explicit_null_check) {
935 explicit_null_check(base, info);
936 }
937
938 switch (c->type()) {
939 case T_FLOAT: type = T_INT;
940 case T_INT:
941 case T_ADDRESS: {
942 tmp = FrameMap::R0_opr;
943 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
944 break;
945 }
946 case T_DOUBLE: type = T_LONG;
947 case T_LONG: {
948 tmp = FrameMap::R0_long_opr;
949 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
950 break;
951 }
952 case T_OBJECT: {
953 tmp = FrameMap::R0_opr;
954 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
955 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
956 // Don't care about sign extend (will use stw).
957 __ lis(R0, 0); // Will get patched.
958 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
959 __ ori(R0, R0, 0); // Will get patched.
960 } else {
961 jobject2reg(c->as_jobject(), R0);
962 }
963 break;
964 }
965 default:
966 Unimplemented();
967 }
968
969 // Handle either reg+reg or reg+disp address.
970 if (addr->index()->is_valid()) {
971 assert(addr->disp() == 0, "must be zero");
972 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
973 } else {
974 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
975 offset = store(tmp, base, addr->disp(), type, wide);
976 }
977
978 if (info != nullptr) {
979 assert(offset != -1, "offset should've been set");
980 if (!needs_explicit_null_check) {
981 add_debug_info_for_null_check(offset, info);
982 }
983 }
984 }
985
986
987 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
988 LIR_Const* c = src->as_constant_ptr();
989 LIR_Opr to_reg = dest;
990
991 switch (c->type()) {
992 case T_INT: {
993 assert(patch_code == lir_patch_none, "no patching handled here");
994 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
995 break;
996 }
997 case T_ADDRESS: {
998 assert(patch_code == lir_patch_none, "no patching handled here");
999 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
1000 break;
1001 }
1002 case T_LONG: {
1003 assert(patch_code == lir_patch_none, "no patching handled here");
1004 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
1005 break;
1006 }
1007
1008 case T_OBJECT: {
1009 if (patch_code == lir_patch_none) {
1010 jobject2reg(c->as_jobject(), to_reg->as_register());
1011 } else {
1012 jobject2reg_with_patching(to_reg->as_register(), info);
1013 }
1014 break;
1015 }
1016
1017 case T_METADATA:
1018 {
1019 if (patch_code == lir_patch_none) {
1020 metadata2reg(c->as_metadata(), to_reg->as_register());
1021 } else {
1022 klass2reg_with_patching(to_reg->as_register(), info);
1023 }
1024 }
1025 break;
1026
1027 case T_FLOAT:
1028 {
1029 if (to_reg->is_single_fpu()) {
1030 address const_addr = __ float_constant(c->as_jfloat());
1031 if (const_addr == nullptr) {
1032 bailout("const section overflow");
1033 break;
1034 }
1035 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1036 __ relocate(rspec);
1037 __ load_const(R0, const_addr);
1038 __ lfsx(to_reg->as_float_reg(), R0);
1039 } else {
1040 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1041 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1042 }
1043 }
1044 break;
1045
1046 case T_DOUBLE:
1047 {
1048 if (to_reg->is_double_fpu()) {
1049 address const_addr = __ double_constant(c->as_jdouble());
1050 if (const_addr == nullptr) {
1051 bailout("const section overflow");
1052 break;
1053 }
1054 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1055 __ relocate(rspec);
1056 __ load_const(R0, const_addr);
1057 __ lfdx(to_reg->as_double_reg(), R0);
1058 } else {
1059 assert(to_reg->is_double_cpu(), "Must be a long register.");
1060 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1061 }
1062 }
1063 break;
1064
1065 default:
1066 ShouldNotReachHere();
1067 }
1068 }
1069
1070
1071 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1072 Unimplemented(); return Address();
1073 }
1074
1075
1076 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1077 if (addr->index()->is_illegal()) {
1078 return (RegisterOrConstant)(addr->disp());
1079 } else {
1080 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1081 }
1082 }
1083
1084
1085 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1086 const Register tmp = R0;
1087 switch (type) {
1088 case T_INT:
1089 case T_FLOAT: {
1090 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1091 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1092 __ lwz(tmp, from);
1093 __ stw(tmp, to);
1094 break;
1095 }
1096 case T_ADDRESS:
1097 case T_OBJECT: {
1098 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1099 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1100 __ ld(tmp, from);
1101 __ std(tmp, to);
1102 break;
1103 }
1104 case T_LONG:
1105 case T_DOUBLE: {
1106 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1107 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1108 __ ld(tmp, from);
1109 __ std(tmp, to);
1110 break;
1111 }
1112
1113 default:
1114 ShouldNotReachHere();
1115 }
1116 }
1117
1118
1119 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1120 Unimplemented(); return Address();
1121 }
1122
1123
1124 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1125 Unimplemented(); return Address();
1126 }
1127
1128
1129 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1130 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1131
1132 assert(type != T_METADATA, "load of metadata ptr not supported");
1133 LIR_Address* addr = src_opr->as_address_ptr();
1134 LIR_Opr to_reg = dest;
1135
1136 Register src = addr->base()->as_pointer_register();
1137 Register disp_reg = noreg;
1138 int disp_value = addr->disp();
1139 bool needs_patching = (patch_code != lir_patch_none);
1140 // null check for large offsets in LIRGenerator::do_LoadField
1141 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1142
1143 if (info != nullptr && needs_explicit_null_check) {
1144 explicit_null_check(src, info);
1145 }
1146
1147 if (addr->base()->type() == T_OBJECT) {
1148 __ verify_oop(src, FILE_AND_LINE);
1149 }
1150
1151 PatchingStub* patch = nullptr;
1152 if (needs_patching) {
1153 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1154 assert(!to_reg->is_double_cpu() ||
1155 patch_code == lir_patch_none ||
1156 patch_code == lir_patch_normal, "patching doesn't match register");
1157 }
1158
1159 if (addr->index()->is_illegal()) {
1160 if (!Assembler::is_simm16(disp_value)) {
1161 if (needs_patching) {
1162 __ load_const32(R0, 0); // patchable int
1163 } else {
1164 __ load_const_optimized(R0, disp_value);
1165 }
1166 disp_reg = R0;
1167 }
1168 } else {
1169 disp_reg = addr->index()->as_pointer_register();
1170 assert(disp_value == 0, "can't handle 3 operand addresses");
1171 }
1172
1173 // Remember the offset of the load. The patching_epilog must be done
1174 // before the call to add_debug_info, otherwise the PcDescs don't get
1175 // entered in increasing order.
1176 int offset;
1177
1178 if (disp_reg == noreg) {
1179 assert(Assembler::is_simm16(disp_value), "should have set this up");
1180 offset = load(src, disp_value, to_reg, type, wide);
1181 } else {
1182 offset = load(src, disp_reg, to_reg, type, wide);
1183 }
1184
1185 if (patch != nullptr) {
1186 patching_epilog(patch, patch_code, src, info);
1187 }
1188 if (info != nullptr && !needs_explicit_null_check) {
1189 add_debug_info_for_null_check(offset, info);
1190 }
1191 }
1192
1193
1194 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1195 Address addr;
1196 if (src->is_single_word()) {
1197 addr = frame_map()->address_for_slot(src->single_stack_ix());
1198 } else if (src->is_double_word()) {
1199 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1200 }
1201
1202 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1203 }
1204
1205
1206 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) {
1207 Address addr;
1208 if (dest->is_single_word()) {
1209 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1210 } else if (dest->is_double_word()) {
1211 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1212 }
1213
1214 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1215 }
1216
1217
1218 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1219 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1220 if (from_reg->is_double_fpu()) {
1221 // double to double moves
1222 assert(to_reg->is_double_fpu(), "should match");
1223 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1224 } else {
1225 // float to float moves
1226 assert(to_reg->is_single_fpu(), "should match");
1227 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1228 }
1229 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1230 if (from_reg->is_double_cpu()) {
1231 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1232 } else if (to_reg->is_double_cpu()) {
1233 // int to int moves
1234 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1235 } else {
1236 // int to int moves
1237 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1238 }
1239 } else {
1240 ShouldNotReachHere();
1241 }
1242 if (is_reference_type(to_reg->type())) {
1243 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1244 }
1245 }
1246
1247
1248 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1249 LIR_PatchCode patch_code, CodeEmitInfo* info,
1250 bool wide) {
1251 assert(type != T_METADATA, "store of metadata ptr not supported");
1252 LIR_Address* addr = dest->as_address_ptr();
1253
1254 Register src = addr->base()->as_pointer_register();
1255 Register disp_reg = noreg;
1256 int disp_value = addr->disp();
1257 bool needs_patching = (patch_code != lir_patch_none);
1258 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1259 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1260 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1261 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1262 // Null check for large offsets in LIRGenerator::do_StoreField.
1263 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1264
1265 if (info != nullptr && needs_explicit_null_check) {
1266 explicit_null_check(src, info);
1267 }
1268
1269 if (addr->base()->is_oop_register()) {
1270 __ verify_oop(src, FILE_AND_LINE);
1271 }
1272
1273 PatchingStub* patch = nullptr;
1274 if (needs_patching) {
1275 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1276 assert(!from_reg->is_double_cpu() ||
1277 patch_code == lir_patch_none ||
1278 patch_code == lir_patch_normal, "patching doesn't match register");
1279 }
1280
1281 if (addr->index()->is_illegal()) {
1282 if (load_disp) {
1283 disp_reg = use_R29 ? R29_TOC : R0;
1284 if (needs_patching) {
1285 __ load_const32(disp_reg, 0); // patchable int
1286 } else {
1287 __ load_const_optimized(disp_reg, disp_value);
1288 }
1289 }
1290 } else {
1291 disp_reg = addr->index()->as_pointer_register();
1292 assert(disp_value == 0, "can't handle 3 operand addresses");
1293 }
1294
1295 // remember the offset of the store. The patching_epilog must be done
1296 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1297 // entered in increasing order.
1298 int offset;
1299
1300 if (compress_oop) {
1301 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1302 from_reg = FrameMap::as_opr(co);
1303 }
1304
1305 if (disp_reg == noreg) {
1306 assert(Assembler::is_simm16(disp_value), "should have set this up");
1307 offset = store(from_reg, src, disp_value, type, wide);
1308 } else {
1309 offset = store(from_reg, src, disp_reg, type, wide);
1310 }
1311
1312 if (use_R29) {
1313 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1314 }
1315
1316 if (patch != nullptr) {
1317 patching_epilog(patch, patch_code, src, info);
1318 }
1319
1320 if (info != nullptr && !needs_explicit_null_check) {
1321 add_debug_info_for_null_check(offset, info);
1322 }
1323 }
1324
1325
1326 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1327 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1328 const Register temp = R12;
1329
1330 // Pop the stack before the safepoint code.
1331 int frame_size = initial_frame_size_in_bytes();
1332 if (Assembler::is_simm(frame_size, 16)) {
1333 __ addi(R1_SP, R1_SP, frame_size);
1334 } else {
1335 __ pop_frame();
1336 }
1337
1338 // Restore return pc relative to callers' sp.
1339 __ ld(return_pc, _abi0(lr), R1_SP);
1340 // Move return pc to LR.
1341 __ mtlr(return_pc);
1342
1343 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1344 __ reserved_stack_check(return_pc);
1345 }
1346
1347 // We need to mark the code position where the load from the safepoint
1348 // polling page was emitted as relocInfo::poll_return_type here.
1349 if (!UseSIGTRAP) {
1350 code_stub->set_safepoint_offset(__ offset());
1351 __ relocate(relocInfo::poll_return_type);
1352 }
1353 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1354
1355 // Return.
1356 __ blr();
1357 }
1358
1359
1360 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1361 const Register poll_addr = tmp->as_register();
1362 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1363 if (info != nullptr) {
1364 add_debug_info_for_branch(info);
1365 }
1366 int offset = __ offset();
1367 __ relocate(relocInfo::poll_type);
1368 __ load_from_polling_page(poll_addr);
1369
1370 return offset;
1371 }
1372
1373
1374 void LIR_Assembler::emit_static_call_stub() {
1375 address call_pc = __ pc();
1376 address stub = __ start_a_stub(static_call_stub_size());
1377 if (stub == nullptr) {
1378 bailout("static call stub overflow");
1379 return;
1380 }
1381
1382 // For java_to_interp stubs we use R11_scratch1 as scratch register
1383 // and in call trampoline stubs we use R12_scratch2. This way we
1384 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1385 const Register reg_scratch = R11_scratch1;
1386
1387 // Create a static stub relocation which relates this stub
1388 // with the call instruction at insts_call_instruction_offset in the
1389 // instructions code-section.
1390 int start = __ offset();
1391 __ relocate(static_stub_Relocation::spec(call_pc));
1392
1393 // Now, create the stub's code:
1394 // - load the TOC
1395 // - load the inline cache oop from the constant pool
1396 // - load the call target from the constant pool
1397 // - call
1398 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1399 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1400 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1401
1402 if (ReoptimizeCallSequences) {
1403 __ b64_patchable((address)-1, relocInfo::none);
1404 } else {
1405 AddressLiteral a((address)-1);
1406 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1407 __ mtctr(reg_scratch);
1408 __ bctr();
1409 }
1410 if (!success) {
1411 bailout("const section overflow");
1412 return;
1413 }
1414
1415 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1416 __ end_a_stub();
1417 }
1418
1419
1420 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1421 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1422 if (opr1->is_single_fpu()) {
1423 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1424 } else if (opr1->is_double_fpu()) {
1425 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1426 } else if (opr1->is_single_cpu()) {
1427 if (opr2->is_constant()) {
1428 switch (opr2->as_constant_ptr()->type()) {
1429 case T_INT:
1430 {
1431 jint con = opr2->as_constant_ptr()->as_jint();
1432 if (unsigned_comp) {
1433 if (Assembler::is_uimm(con, 16)) {
1434 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1435 } else {
1436 __ load_const_optimized(R0, con);
1437 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1438 }
1439 } else {
1440 if (Assembler::is_simm(con, 16)) {
1441 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1442 } else {
1443 __ load_const_optimized(R0, con);
1444 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1445 }
1446 }
1447 }
1448 break;
1449
1450 case T_OBJECT:
1451 // There are only equal/notequal comparisons on objects.
1452 {
1453 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1454 jobject con = opr2->as_constant_ptr()->as_jobject();
1455 if (con == nullptr) {
1456 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1457 } else {
1458 jobject2reg(con, R0);
1459 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1460 }
1461 }
1462 break;
1463
1464 case T_METADATA:
1465 // We only need, for now, comparison with null for metadata.
1466 {
1467 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1468 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1469 if (p == nullptr) {
1470 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1471 } else {
1472 ShouldNotReachHere();
1473 }
1474 }
1475 break;
1476
1477 default:
1478 ShouldNotReachHere();
1479 break;
1480 }
1481 } else {
1482 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1483 if (is_reference_type(opr1->type())) {
1484 // There are only equal/notequal comparisons on objects.
1485 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1486 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1487 } else {
1488 if (unsigned_comp) {
1489 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1490 } else {
1491 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1492 }
1493 }
1494 }
1495 } else if (opr1->is_double_cpu()) {
1496 if (opr2->is_constant()) {
1497 jlong con = opr2->as_constant_ptr()->as_jlong();
1498 if (unsigned_comp) {
1499 if (Assembler::is_uimm(con, 16)) {
1500 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1501 } else {
1502 __ load_const_optimized(R0, con);
1503 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1504 }
1505 } else {
1506 if (Assembler::is_simm(con, 16)) {
1507 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1508 } else {
1509 __ load_const_optimized(R0, con);
1510 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1511 }
1512 }
1513 } else if (opr2->is_register()) {
1514 if (unsigned_comp) {
1515 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1516 } else {
1517 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1518 }
1519 } else {
1520 ShouldNotReachHere();
1521 }
1522 } else {
1523 ShouldNotReachHere();
1524 }
1525 }
1526
1527
1528 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1529 const Register Rdst = dst->as_register();
1530 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1531 bool is_unordered_less = (code == lir_ucmp_fd2i);
1532 if (left->is_single_fpu()) {
1533 __ fcmpu(CR0, left->as_float_reg(), right->as_float_reg());
1534 } else if (left->is_double_fpu()) {
1535 __ fcmpu(CR0, left->as_double_reg(), right->as_double_reg());
1536 } else {
1537 ShouldNotReachHere();
1538 }
1539 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1540 } else if (code == lir_cmp_l2i) {
1541 __ cmpd(CR0, left->as_register_lo(), right->as_register_lo());
1542 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1543 } else {
1544 ShouldNotReachHere();
1545 }
1546 }
1547
1548
1549 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1550 if (src->is_constant()) {
1551 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1552 } else if (src->is_register()) {
1553 lasm->reg2reg(src, dst);
1554 } else if (src->is_stack()) {
1555 lasm->stack2reg(src, dst, dst->type());
1556 } else {
1557 ShouldNotReachHere();
1558 }
1559 }
1560
1561 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1562 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1563 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1564
1565 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1566 load_to_reg(this, opr1, result); // Condition doesn't matter.
1567 return;
1568 }
1569
1570 bool positive = false;
1571 Assembler::Condition cond = Assembler::equal;
1572 switch (condition) {
1573 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1574 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1575 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1576 case lir_cond_belowEqual:
1577 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1578 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1579 case lir_cond_aboveEqual:
1580 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1581 default: ShouldNotReachHere();
1582 }
1583
1584 // Try to use isel on >=Power7.
1585 if (VM_Version::has_isel() && result->is_cpu_register()) {
1586 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1587 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1588
1589 // We can use result_reg to load one operand if not already in register.
1590 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1591 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1592
1593 if (first != second) {
1594 if (!o1_is_reg) {
1595 load_to_reg(this, opr1, result);
1596 }
1597
1598 if (!o2_is_reg) {
1599 load_to_reg(this, opr2, result);
1600 }
1601
1602 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1603 return;
1604 }
1605 } // isel
1606
1607 load_to_reg(this, opr1, result);
1608
1609 Label skip;
1610 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1611 int bi = Assembler::bi0(BOOL_RESULT, cond);
1612 __ bc(bo, bi, skip);
1613
1614 load_to_reg(this, opr2, result);
1615 __ bind(skip);
1616 }
1617
1618
1619 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1620 CodeEmitInfo* info) {
1621 assert(info == nullptr, "unused on this code path");
1622 assert(left->is_register(), "wrong items state");
1623 assert(dest->is_register(), "wrong items state");
1624
1625 if (right->is_register()) {
1626 if (dest->is_float_kind()) {
1627
1628 FloatRegister lreg, rreg, res;
1629 if (right->is_single_fpu()) {
1630 lreg = left->as_float_reg();
1631 rreg = right->as_float_reg();
1632 res = dest->as_float_reg();
1633 switch (code) {
1634 case lir_add: __ fadds(res, lreg, rreg); break;
1635 case lir_sub: __ fsubs(res, lreg, rreg); break;
1636 case lir_mul: __ fmuls(res, lreg, rreg); break;
1637 case lir_div: __ fdivs(res, lreg, rreg); break;
1638 default: ShouldNotReachHere();
1639 }
1640 } else {
1641 lreg = left->as_double_reg();
1642 rreg = right->as_double_reg();
1643 res = dest->as_double_reg();
1644 switch (code) {
1645 case lir_add: __ fadd(res, lreg, rreg); break;
1646 case lir_sub: __ fsub(res, lreg, rreg); break;
1647 case lir_mul: __ fmul(res, lreg, rreg); break;
1648 case lir_div: __ fdiv(res, lreg, rreg); break;
1649 default: ShouldNotReachHere();
1650 }
1651 }
1652
1653 } else if (dest->is_double_cpu()) {
1654
1655 Register dst_lo = dest->as_register_lo();
1656 Register op1_lo = left->as_pointer_register();
1657 Register op2_lo = right->as_pointer_register();
1658
1659 switch (code) {
1660 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1661 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1662 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1663 default: ShouldNotReachHere();
1664 }
1665 } else {
1666 assert (right->is_single_cpu(), "Just Checking");
1667
1668 Register lreg = left->as_register();
1669 Register res = dest->as_register();
1670 Register rreg = right->as_register();
1671 switch (code) {
1672 case lir_add: __ add (res, lreg, rreg); break;
1673 case lir_sub: __ sub (res, lreg, rreg); break;
1674 case lir_mul: __ mullw(res, lreg, rreg); break;
1675 default: ShouldNotReachHere();
1676 }
1677 }
1678 } else {
1679 assert (right->is_constant(), "must be constant");
1680
1681 if (dest->is_single_cpu()) {
1682 Register lreg = left->as_register();
1683 Register res = dest->as_register();
1684 int simm16 = right->as_constant_ptr()->as_jint();
1685
1686 switch (code) {
1687 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1688 simm16 = -simm16;
1689 case lir_add: if (res == lreg && simm16 == 0) break;
1690 __ addi(res, lreg, simm16); break;
1691 case lir_mul: if (res == lreg && simm16 == 1) break;
1692 __ mulli(res, lreg, simm16); break;
1693 default: ShouldNotReachHere();
1694 }
1695 } else {
1696 Register lreg = left->as_pointer_register();
1697 Register res = dest->as_register_lo();
1698 long con = right->as_constant_ptr()->as_jlong();
1699 assert(Assembler::is_simm16(con), "must be simm16");
1700
1701 switch (code) {
1702 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1703 con = -con;
1704 case lir_add: if (res == lreg && con == 0) break;
1705 __ addi(res, lreg, (int)con); break;
1706 case lir_mul: if (res == lreg && con == 1) break;
1707 __ mulli(res, lreg, (int)con); break;
1708 default: ShouldNotReachHere();
1709 }
1710 }
1711 }
1712 }
1713
1714
1715 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1716 switch (code) {
1717 case lir_sqrt: {
1718 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1719 break;
1720 }
1721 case lir_abs: {
1722 __ fabs(dest->as_double_reg(), value->as_double_reg());
1723 break;
1724 }
1725 case lir_f2hf: {
1726 __ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1727 break;
1728 }
1729 case lir_hf2f: {
1730 __ hf2f(dest->as_float_reg(), value.as_register());
1731 break;
1732 }
1733 default: {
1734 ShouldNotReachHere();
1735 break;
1736 }
1737 }
1738 }
1739
1740
1741 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1742 if (right->is_constant()) { // see do_LogicOp
1743 long uimm;
1744 Register d, l;
1745 if (dest->is_single_cpu()) {
1746 uimm = right->as_constant_ptr()->as_jint();
1747 d = dest->as_register();
1748 l = left->as_register();
1749 } else {
1750 uimm = right->as_constant_ptr()->as_jlong();
1751 d = dest->as_register_lo();
1752 l = left->as_register_lo();
1753 }
1754 long uimms = (unsigned long)uimm >> 16,
1755 uimmss = (unsigned long)uimm >> 32;
1756
1757 switch (code) {
1758 case lir_logic_and:
1759 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1760 __ andi(d, l, uimm); // special cases
1761 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1762 else { __ andi_(d, l, uimm); }
1763 break;
1764
1765 case lir_logic_or:
1766 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1767 else { __ ori(d, l, uimm); }
1768 break;
1769
1770 case lir_logic_xor:
1771 if (uimm == -1) { __ nand(d, l, l); } // special case
1772 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1773 else { __ xori(d, l, uimm); }
1774 break;
1775
1776 default: ShouldNotReachHere();
1777 }
1778 } else {
1779 assert(right->is_register(), "right should be in register");
1780
1781 if (dest->is_single_cpu()) {
1782 switch (code) {
1783 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1784 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1785 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1786 default: ShouldNotReachHere();
1787 }
1788 } else {
1789 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1790 left->as_register_lo();
1791 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1792 right->as_register_lo();
1793
1794 switch (code) {
1795 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1796 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1797 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1798 default: ShouldNotReachHere();
1799 }
1800 }
1801 }
1802 }
1803
1804
1805 int LIR_Assembler::shift_amount(BasicType t) {
1806 int elem_size = type2aelembytes(t);
1807 switch (elem_size) {
1808 case 1 : return 0;
1809 case 2 : return 1;
1810 case 4 : return 2;
1811 case 8 : return 3;
1812 }
1813 ShouldNotReachHere();
1814 return -1;
1815 }
1816
1817
1818 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1819 info->add_register_oop(exceptionOop);
1820
1821 // Reuse the debug info from the safepoint poll for the throw op itself.
1822 address pc_for_athrow = __ pc();
1823 int pc_for_athrow_offset = __ offset();
1824 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1825 //__ relocate(rspec);
1826 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1827 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1828 add_call_info(pc_for_athrow_offset, info); // for exception handler
1829
1830 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? C1StubId::handle_exception_id
1831 : C1StubId::handle_exception_nofpu_id);
1832 //__ load_const_optimized(R0, stub);
1833 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1834 __ mtctr(R0);
1835 __ bctr();
1836 }
1837
1838
1839 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1840 // Note: Not used with EnableDebuggingOnDemand.
1841 assert(exceptionOop->as_register() == R3, "should match");
1842 __ b(_unwind_handler_entry);
1843 }
1844
1845
1846 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1847 Register src = op->src()->as_register();
1848 Register dst = op->dst()->as_register();
1849 Register src_pos = op->src_pos()->as_register();
1850 Register dst_pos = op->dst_pos()->as_register();
1851 Register length = op->length()->as_register();
1852 Register tmp = op->tmp()->as_register();
1853 Register tmp2 = R0;
1854
1855 int flags = op->flags();
1856 ciArrayKlass* default_type = op->expected_type();
1857 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1858 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1859
1860 // Set up the arraycopy stub information.
1861 ArrayCopyStub* stub = op->stub();
1862
1863 // Always do stub if no type information is available. It's ok if
1864 // the known type isn't loaded since the code sanity checks
1865 // in debug mode and the type isn't required when we know the exact type
1866 // also check that the type is an array type.
1867 if (default_type == nullptr) {
1868 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1869 length->is_nonvolatile(), "must preserve");
1870 address copyfunc_addr = StubRoutines::generic_arraycopy();
1871 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1872
1873 // 3 parms are int. Convert to long.
1874 __ mr(R3_ARG1, src);
1875 __ extsw(R4_ARG2, src_pos);
1876 __ mr(R5_ARG3, dst);
1877 __ extsw(R6_ARG4, dst_pos);
1878 __ extsw(R7_ARG5, length);
1879
1880 #ifndef PRODUCT
1881 if (PrintC1Statistics) {
1882 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1883 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1884 __ lwz(R11_scratch1, simm16_offs, tmp);
1885 __ addi(R11_scratch1, R11_scratch1, 1);
1886 __ stw(R11_scratch1, simm16_offs, tmp);
1887 }
1888 #endif
1889 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1890
1891 __ nand(tmp, R3_RET, R3_RET);
1892 __ subf(length, tmp, length);
1893 __ add(src_pos, tmp, src_pos);
1894 __ add(dst_pos, tmp, dst_pos);
1895
1896 __ cmpwi(CR0, R3_RET, 0);
1897 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CR0, Assembler::less), *stub->entry());
1898 __ bind(*stub->continuation());
1899 return;
1900 }
1901
1902 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1903 Label cont, slow, copyfunc;
1904
1905 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1906 LIR_OpArrayCopy::dst_null_check |
1907 LIR_OpArrayCopy::src_pos_positive_check |
1908 LIR_OpArrayCopy::dst_pos_positive_check |
1909 LIR_OpArrayCopy::length_positive_check);
1910
1911 // Use only one conditional branch for simple checks.
1912 if (simple_check_flag_set) {
1913 ConditionRegister combined_check = CR1, tmp_check = CR1;
1914
1915 // Make sure src and dst are non-null.
1916 if (flags & LIR_OpArrayCopy::src_null_check) {
1917 __ cmpdi(combined_check, src, 0);
1918 tmp_check = CR0;
1919 }
1920
1921 if (flags & LIR_OpArrayCopy::dst_null_check) {
1922 __ cmpdi(tmp_check, dst, 0);
1923 if (tmp_check != combined_check) {
1924 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1925 }
1926 tmp_check = CR0;
1927 }
1928
1929 // Clear combined_check.eq if not already used.
1930 if (tmp_check == combined_check) {
1931 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1932 tmp_check = CR0;
1933 }
1934
1935 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1936 // Test src_pos register.
1937 __ cmpwi(tmp_check, src_pos, 0);
1938 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1939 }
1940
1941 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1942 // Test dst_pos register.
1943 __ cmpwi(tmp_check, dst_pos, 0);
1944 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1945 }
1946
1947 if (flags & LIR_OpArrayCopy::length_positive_check) {
1948 // Make sure length isn't negative.
1949 __ cmpwi(tmp_check, length, 0);
1950 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1951 }
1952
1953 __ beq(combined_check, slow);
1954 }
1955
1956 // If the compiler was not able to prove that exact type of the source or the destination
1957 // of the arraycopy is an array type, check at runtime if the source or the destination is
1958 // an instance type.
1959 if (flags & LIR_OpArrayCopy::type_check) {
1960 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1961 __ load_klass(tmp, dst);
1962 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1963 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1964 __ bge(CR0, slow);
1965 }
1966
1967 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1968 __ load_klass(tmp, src);
1969 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1970 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1971 __ bge(CR0, slow);
1972 }
1973 }
1974
1975 // Higher 32bits must be null.
1976 __ extsw(length, length);
1977
1978 __ extsw(src_pos, src_pos);
1979 if (flags & LIR_OpArrayCopy::src_range_check) {
1980 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1981 __ add(tmp, length, src_pos);
1982 __ cmpld(CR0, tmp2, tmp);
1983 __ ble(CR0, slow);
1984 }
1985
1986 __ extsw(dst_pos, dst_pos);
1987 if (flags & LIR_OpArrayCopy::dst_range_check) {
1988 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1989 __ add(tmp, length, dst_pos);
1990 __ cmpld(CR0, tmp2, tmp);
1991 __ ble(CR0, slow);
1992 }
1993
1994 int shift = shift_amount(basic_type);
1995
1996 if (!(flags & LIR_OpArrayCopy::type_check)) {
1997 if (stub != nullptr) {
1998 __ b(cont);
1999 __ bind(slow);
2000 __ b(*stub->entry());
2001 }
2002 } else {
2003 // We don't know the array types are compatible.
2004 if (basic_type != T_OBJECT) {
2005 // Simple test for basic type arrays.
2006 __ cmp_klasses_from_objects(CR0, src, dst, tmp, tmp2);
2007 __ beq(CR0, cont);
2008 } else {
2009 // For object arrays, if src is a sub class of dst then we can
2010 // safely do the copy.
2011 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2012
2013 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2014 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2015
2016 __ load_klass(sub_klass, src);
2017 __ load_klass(super_klass, dst);
2018
2019 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2020 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
2021
2022 address slow_stc = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2023 //__ load_const_optimized(tmp, slow_stc, tmp2);
2024 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2025 __ mtctr(tmp);
2026 __ bctrl(); // sets CR0
2027 __ beq(CR0, cont);
2028
2029 if (copyfunc_addr != nullptr) { // Use stub if available.
2030 __ bind(copyfunc);
2031 // Src is not a sub class of dst so we have to do a
2032 // per-element check.
2033 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2034 if ((flags & mask) != mask) {
2035 assert(flags & mask, "one of the two should be known to be an object array");
2036
2037 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2038 __ load_klass(tmp, src);
2039 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2040 __ load_klass(tmp, dst);
2041 }
2042
2043 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2044
2045 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2046 __ load_const_optimized(tmp, objArray_lh);
2047 __ cmpw(CR0, tmp, tmp2);
2048 __ bne(CR0, slow);
2049 }
2050
2051 Register src_ptr = R3_ARG1;
2052 Register dst_ptr = R4_ARG2;
2053 Register len = R5_ARG3;
2054 Register chk_off = R6_ARG4;
2055 Register super_k = R7_ARG5;
2056
2057 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2058 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2059 if (shift == 0) {
2060 __ add(src_ptr, src_pos, src_ptr);
2061 __ add(dst_ptr, dst_pos, dst_ptr);
2062 } else {
2063 __ sldi(tmp, src_pos, shift);
2064 __ sldi(tmp2, dst_pos, shift);
2065 __ add(src_ptr, tmp, src_ptr);
2066 __ add(dst_ptr, tmp2, dst_ptr);
2067 }
2068
2069 __ load_klass(tmp, dst);
2070 __ mr(len, length);
2071
2072 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2073 __ ld(super_k, ek_offset, tmp);
2074
2075 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2076 __ lwz(chk_off, sco_offset, super_k);
2077
2078 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2079
2080 #ifndef PRODUCT
2081 if (PrintC1Statistics) {
2082 Label failed;
2083 __ cmpwi(CR0, R3_RET, 0);
2084 __ bne(CR0, failed);
2085 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2086 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2087 __ lwz(R11_scratch1, simm16_offs, tmp);
2088 __ addi(R11_scratch1, R11_scratch1, 1);
2089 __ stw(R11_scratch1, simm16_offs, tmp);
2090 __ bind(failed);
2091 }
2092 #endif
2093
2094 __ nand(tmp, R3_RET, R3_RET);
2095 __ cmpwi(CR0, R3_RET, 0);
2096 __ beq(CR0, *stub->continuation());
2097
2098 #ifndef PRODUCT
2099 if (PrintC1Statistics) {
2100 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2101 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2102 __ lwz(R11_scratch1, simm16_offs, tmp);
2103 __ addi(R11_scratch1, R11_scratch1, 1);
2104 __ stw(R11_scratch1, simm16_offs, tmp);
2105 }
2106 #endif
2107
2108 __ subf(length, tmp, length);
2109 __ add(src_pos, tmp, src_pos);
2110 __ add(dst_pos, tmp, dst_pos);
2111 }
2112 }
2113 __ bind(slow);
2114 __ b(*stub->entry());
2115 }
2116 __ bind(cont);
2117
2118 #ifdef ASSERT
2119 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2120 // Sanity check the known type with the incoming class. For the
2121 // primitive case the types must match exactly with src.klass and
2122 // dst.klass each exactly matching the default type. For the
2123 // object array case, if no type check is needed then either the
2124 // dst type is exactly the expected type and the src type is a
2125 // subtype which we can't check or src is the same array as dst
2126 // but not necessarily exactly of type default_type.
2127 Label known_ok, halt;
2128 metadata2reg(default_type->constant_encoding(), tmp);
2129 __ cmp_klass(CR0, dst, tmp, R11_scratch1, R12_scratch2);
2130 if (basic_type != T_OBJECT) {
2131 __ bne(CR0, halt);
2132 __ cmp_klass(CR0, src, tmp, R11_scratch1, R12_scratch2);
2133 __ beq(CR0, known_ok);
2134 } else {
2135 __ beq(CR0, known_ok);
2136 __ cmpw(CR0, src, dst);
2137 __ beq(CR0, known_ok);
2138 }
2139 __ bind(halt);
2140 __ stop("incorrect type information in arraycopy");
2141 __ bind(known_ok);
2142 }
2143 #endif
2144
2145 #ifndef PRODUCT
2146 if (PrintC1Statistics) {
2147 address counter = Runtime1::arraycopy_count_address(basic_type);
2148 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2149 __ lwz(R11_scratch1, simm16_offs, tmp);
2150 __ addi(R11_scratch1, R11_scratch1, 1);
2151 __ stw(R11_scratch1, simm16_offs, tmp);
2152 }
2153 #endif
2154
2155 Register src_ptr = R3_ARG1;
2156 Register dst_ptr = R4_ARG2;
2157 Register len = R5_ARG3;
2158
2159 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2160 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2161 if (shift == 0) {
2162 __ add(src_ptr, src_pos, src_ptr);
2163 __ add(dst_ptr, dst_pos, dst_ptr);
2164 } else {
2165 __ sldi(tmp, src_pos, shift);
2166 __ sldi(tmp2, dst_pos, shift);
2167 __ add(src_ptr, tmp, src_ptr);
2168 __ add(dst_ptr, tmp2, dst_ptr);
2169 }
2170
2171 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2172 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2173 const char *name;
2174 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2175
2176 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2177 __ mr(len, length);
2178 __ call_c(entry, relocInfo::runtime_call_type);
2179
2180 if (stub != nullptr) {
2181 __ bind(*stub->continuation());
2182 }
2183 }
2184
2185
2186 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2187 if (dest->is_single_cpu()) {
2188 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2189 #ifdef _LP64
2190 if (left->type() == T_OBJECT) {
2191 switch (code) {
2192 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2193 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2194 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2195 default: ShouldNotReachHere();
2196 }
2197 } else
2198 #endif
2199 switch (code) {
2200 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2201 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2202 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2203 default: ShouldNotReachHere();
2204 }
2205 } else {
2206 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2207 switch (code) {
2208 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2209 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2210 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2211 default: ShouldNotReachHere();
2212 }
2213 }
2214 }
2215
2216
2217 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2218 #ifdef _LP64
2219 if (left->type() == T_OBJECT) {
2220 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2221 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2222 else {
2223 switch (code) {
2224 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2225 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2226 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2227 default: ShouldNotReachHere();
2228 }
2229 }
2230 return;
2231 }
2232 #endif
2233
2234 if (dest->is_single_cpu()) {
2235 count = count & 0x1F; // Java spec
2236 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2237 else {
2238 switch (code) {
2239 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2240 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2241 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2242 default: ShouldNotReachHere();
2243 }
2244 }
2245 } else if (dest->is_double_cpu()) {
2246 count = count & 63; // Java spec
2247 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2248 else {
2249 switch (code) {
2250 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2251 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2252 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2253 default: ShouldNotReachHere();
2254 }
2255 }
2256 } else {
2257 ShouldNotReachHere();
2258 }
2259 }
2260
2261
2262 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2263 if (op->init_check()) {
2264 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2265 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2266 } else {
2267 add_debug_info_for_null_check_here(op->stub()->info());
2268 }
2269 __ lbz(op->tmp1()->as_register(),
2270 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2271 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2272 __ cmpwi(CR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2273 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CR0, Assembler::equal), *op->stub()->entry());
2274 }
2275 __ allocate_object(op->obj()->as_register(),
2276 op->tmp1()->as_register(),
2277 op->tmp2()->as_register(),
2278 op->tmp3()->as_register(),
2279 op->header_size(),
2280 op->object_size(),
2281 op->klass()->as_register(),
2282 *op->stub()->entry());
2283
2284 __ bind(*op->stub()->continuation());
2285 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2286 }
2287
2288
2289 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2290 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2291 if (UseSlowPath ||
2292 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2293 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2294 __ b(*op->stub()->entry());
2295 } else {
2296 __ allocate_array(op->obj()->as_register(),
2297 op->len()->as_register(),
2298 op->tmp1()->as_register(),
2299 op->tmp2()->as_register(),
2300 op->tmp3()->as_register(),
2301 arrayOopDesc::base_offset_in_bytes(op->type()),
2302 type2aelembytes(op->type()),
2303 op->klass()->as_register(),
2304 *op->stub()->entry(),
2305 op->zero_array());
2306 }
2307 __ bind(*op->stub()->continuation());
2308 }
2309
2310
2311 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2312 ciMethodData *md, ciProfileData *data,
2313 Register recv, Register tmp1, Label* update_done) {
2314 uint i;
2315 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2316 Label next_test;
2317 // See if the receiver is receiver[n].
2318 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2319 __ verify_klass_ptr(tmp1);
2320 __ cmpd(CR0, recv, tmp1);
2321 __ bne(CR0, next_test);
2322
2323 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2324 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2325 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2326 __ b(*update_done);
2327
2328 __ bind(next_test);
2329 }
2330
2331 // Didn't find receiver; find next empty slot and fill it in.
2332 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2333 Label next_test;
2334 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2335 __ cmpdi(CR0, tmp1, 0);
2336 __ bne(CR0, next_test);
2337 __ li(tmp1, DataLayout::counter_increment);
2338 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2339 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2340 __ b(*update_done);
2341
2342 __ bind(next_test);
2343 }
2344 }
2345
2346
2347 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2348 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2349 md = method->method_data_or_null();
2350 assert(md != nullptr, "Sanity");
2351 data = md->bci_to_data(bci);
2352 assert(data != nullptr, "need data for checkcast");
2353 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2354 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2355 // The offset is large so bias the mdo by the base of the slot so
2356 // that the ld can use simm16s to reference the slots of the data.
2357 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2358 }
2359 }
2360
2361
2362 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2363 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2364 Register k_RInfo = op->tmp1()->as_register();
2365 Register klass_RInfo = op->tmp2()->as_register();
2366 Register Rtmp1 = op->tmp3()->as_register();
2367 Register dst = op->result_opr()->as_register();
2368 ciKlass* k = op->klass();
2369 bool should_profile = op->should_profile();
2370 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2371 bool reg_conflict = false;
2372 if (obj == k_RInfo) {
2373 k_RInfo = dst;
2374 reg_conflict = true;
2375 } else if (obj == klass_RInfo) {
2376 klass_RInfo = dst;
2377 reg_conflict = true;
2378 } else if (obj == Rtmp1) {
2379 Rtmp1 = dst;
2380 reg_conflict = true;
2381 }
2382 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2383
2384 ciMethodData* md = nullptr;
2385 ciProfileData* data = nullptr;
2386 int mdo_offset_bias = 0;
2387 if (should_profile) {
2388 ciMethod* method = op->profiled_method();
2389 assert(method != nullptr, "Should have method");
2390 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2391
2392 Register mdo = k_RInfo;
2393 Register data_val = Rtmp1;
2394 Label not_null;
2395 metadata2reg(md->constant_encoding(), mdo);
2396 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2397 __ cmpdi(CR0, obj, 0);
2398 __ bne(CR0, not_null);
2399 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2400 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2401 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2402 __ b(*obj_is_null);
2403 __ bind(not_null);
2404
2405 Label update_done;
2406 Register recv = klass_RInfo;
2407 __ load_klass(recv, obj);
2408 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2409 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2410 __ ld(Rtmp1, slot_offset, mdo);
2411 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2412 __ std(Rtmp1, slot_offset, mdo);
2413 __ bind(update_done);
2414 } else {
2415 __ cmpdi(CR0, obj, 0);
2416 __ beq(CR0, *obj_is_null);
2417 }
2418
2419 // get object class
2420 __ load_klass(klass_RInfo, obj);
2421
2422 if (k->is_loaded()) {
2423 metadata2reg(k->constant_encoding(), k_RInfo);
2424 } else {
2425 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2426 }
2427
2428 if (op->fast_check()) {
2429 assert_different_registers(klass_RInfo, k_RInfo);
2430 __ cmpd(CR0, k_RInfo, klass_RInfo);
2431 __ beq(CR0, *success);
2432 // Fall through to failure case.
2433 } else {
2434 bool need_slow_path = true;
2435 if (k->is_loaded()) {
2436 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2437 need_slow_path = false;
2438 }
2439 // Perform the fast part of the checking logic.
2440 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2441 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2442 } else {
2443 // Perform the fast part of the checking logic.
2444 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2445 }
2446 if (!need_slow_path) {
2447 __ b(*success);
2448 } else {
2449 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2450 address entry = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2451 // Stub needs fixed registers (tmp1-3).
2452 Register original_k_RInfo = op->tmp1()->as_register();
2453 Register original_klass_RInfo = op->tmp2()->as_register();
2454 Register original_Rtmp1 = op->tmp3()->as_register();
2455 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2456 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2457 __ mr_if_needed(original_k_RInfo, k_RInfo);
2458 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2459 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2460 //__ load_const_optimized(original_Rtmp1, entry, R0);
2461 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2462 __ mtctr(original_Rtmp1);
2463 __ bctrl(); // sets CR0
2464 if (keep_obj_alive) { __ mr(obj, dst); }
2465 __ beq(CR0, *success);
2466 // Fall through to failure case.
2467 }
2468 }
2469
2470 __ bind(*failure);
2471 }
2472
2473
2474 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2475 LIR_Code code = op->code();
2476 if (code == lir_store_check) {
2477 Register value = op->object()->as_register();
2478 Register array = op->array()->as_register();
2479 Register k_RInfo = op->tmp1()->as_register();
2480 Register klass_RInfo = op->tmp2()->as_register();
2481 Register Rtmp1 = op->tmp3()->as_register();
2482 bool should_profile = op->should_profile();
2483
2484 __ verify_oop(value, FILE_AND_LINE);
2485 CodeStub* stub = op->stub();
2486 // Check if it needs to be profiled.
2487 ciMethodData* md = nullptr;
2488 ciProfileData* data = nullptr;
2489 int mdo_offset_bias = 0;
2490 if (should_profile) {
2491 ciMethod* method = op->profiled_method();
2492 assert(method != nullptr, "Should have method");
2493 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2494 }
2495
2496 Label done;
2497
2498 if (should_profile) {
2499 Label not_null;
2500 Register mdo = k_RInfo;
2501 Register data_val = Rtmp1;
2502 metadata2reg(md->constant_encoding(), mdo);
2503 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2504 __ cmpdi(CR0, value, 0);
2505 __ bne(CR0, not_null);
2506 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2507 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2508 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2509 __ b(done);
2510 __ bind(not_null);
2511
2512 Label update_done;
2513 Register recv = klass_RInfo;
2514 __ load_klass(recv, value);
2515 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2516 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2517 __ ld(Rtmp1, slot_offset, mdo);
2518 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2519 __ std(Rtmp1, slot_offset, mdo);
2520 __ bind(update_done);
2521 } else {
2522 __ cmpdi(CR0, value, 0);
2523 __ beq(CR0, done);
2524 }
2525 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2526 explicit_null_check(array, op->info_for_exception());
2527 } else {
2528 add_debug_info_for_null_check_here(op->info_for_exception());
2529 }
2530 __ load_klass(k_RInfo, array);
2531 __ load_klass(klass_RInfo, value);
2532
2533 Label failure;
2534
2535 // Get instance klass.
2536 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2537 // Perform the fast part of the checking logic.
2538 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2539
2540 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2541 const address slow_path = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2542 //__ load_const_optimized(R0, slow_path);
2543 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2544 __ mtctr(R0);
2545 __ bctrl(); // sets CR0
2546 __ beq(CR0, done);
2547
2548 __ bind(failure);
2549 __ b(*stub->entry());
2550 __ align(32, 12);
2551 __ bind(done);
2552
2553 } else if (code == lir_checkcast) {
2554 Label success, failure;
2555 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2556 __ b(*op->stub()->entry());
2557 __ align(32, 12);
2558 __ bind(success);
2559 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2560 } else if (code == lir_instanceof) {
2561 Register dst = op->result_opr()->as_register();
2562 Label success, failure, done;
2563 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2564 __ li(dst, 0);
2565 __ b(done);
2566 __ align(32, 12);
2567 __ bind(success);
2568 __ li(dst, 1);
2569 __ bind(done);
2570 } else {
2571 ShouldNotReachHere();
2572 }
2573 }
2574
2575
2576 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2577 Register addr = op->addr()->as_pointer_register();
2578 Register cmp_value = noreg, new_value = noreg;
2579 bool is_64bit = false;
2580
2581 if (op->code() == lir_cas_long) {
2582 cmp_value = op->cmp_value()->as_register_lo();
2583 new_value = op->new_value()->as_register_lo();
2584 is_64bit = true;
2585 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2586 cmp_value = op->cmp_value()->as_register();
2587 new_value = op->new_value()->as_register();
2588 if (op->code() == lir_cas_obj) {
2589 if (UseCompressedOops) {
2590 Register t1 = op->tmp1()->as_register();
2591 Register t2 = op->tmp2()->as_register();
2592 cmp_value = __ encode_heap_oop(t1, cmp_value);
2593 new_value = __ encode_heap_oop(t2, new_value);
2594 } else {
2595 is_64bit = true;
2596 }
2597 }
2598 } else {
2599 Unimplemented();
2600 }
2601
2602 // There might be a volatile load before this Unsafe CAS.
2603 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2604 __ sync();
2605 } else {
2606 __ lwsync();
2607 }
2608
2609 if (is_64bit) {
2610 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2611 MacroAssembler::MemBarNone,
2612 MacroAssembler::cmpxchgx_hint_atomic_update(),
2613 noreg, nullptr, /*check without ldarx first*/true);
2614 } else {
2615 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2616 MacroAssembler::MemBarNone,
2617 MacroAssembler::cmpxchgx_hint_atomic_update(),
2618 noreg, nullptr, /*check without ldarx first*/true);
2619 }
2620
2621 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2622 __ isync();
2623 } else {
2624 __ sync();
2625 }
2626 }
2627
2628 void LIR_Assembler::breakpoint() {
2629 __ illtrap();
2630 }
2631
2632
2633 void LIR_Assembler::push(LIR_Opr opr) {
2634 Unimplemented();
2635 }
2636
2637 void LIR_Assembler::pop(LIR_Opr opr) {
2638 Unimplemented();
2639 }
2640
2641
2642 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2643 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2644 Register dst = dst_opr->as_register();
2645 Register reg = mon_addr.base();
2646 int offset = mon_addr.disp();
2647 // Compute pointer to BasicLock.
2648 __ add_const_optimized(dst, reg, offset);
2649 }
2650
2651
2652 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2653 Register obj = op->obj_opr()->as_register();
2654 Register hdr = op->hdr_opr()->as_register();
2655 Register lock = op->lock_opr()->as_register();
2656
2657 // Obj may not be an oop.
2658 if (op->code() == lir_lock) {
2659 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2660 if (LockingMode != LM_MONITOR) {
2661 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2662 // Add debug info for NullPointerException only if one is possible.
2663 if (op->info() != nullptr) {
2664 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2665 explicit_null_check(obj, op->info());
2666 } else {
2667 add_debug_info_for_null_check_here(op->info());
2668 }
2669 }
2670 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2671 } else {
2672 // always do slow locking
2673 // note: The slow locking code could be inlined here, however if we use
2674 // slow locking, speed doesn't matter anyway and this solution is
2675 // simpler and requires less duplicated code - additionally, the
2676 // slow locking code is the same in either case which simplifies
2677 // debugging.
2678 if (op->info() != nullptr) {
2679 add_debug_info_for_null_check_here(op->info());
2680 __ null_check(obj);
2681 }
2682 __ b(*op->stub()->entry());
2683 }
2684 } else {
2685 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2686 if (LockingMode != LM_MONITOR) {
2687 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2688 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2689 } else {
2690 // always do slow unlocking
2691 // note: The slow unlocking code could be inlined here, however if we use
2692 // slow unlocking, speed doesn't matter anyway and this solution is
2693 // simpler and requires less duplicated code - additionally, the
2694 // slow unlocking code is the same in either case which simplifies
2695 // debugging.
2696 __ b(*op->stub()->entry());
2697 }
2698 }
2699 __ bind(*op->stub()->continuation());
2700 }
2701
2702 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2703 Register obj = op->obj()->as_pointer_register();
2704 Register result = op->result_opr()->as_pointer_register();
2705
2706 CodeEmitInfo* info = op->info();
2707 if (info != nullptr) {
2708 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2709 explicit_null_check(obj, info);
2710 } else {
2711 add_debug_info_for_null_check_here(info);
2712 }
2713 }
2714
2715 __ load_klass(result, obj);
2716 }
2717
2718 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2719 ciMethod* method = op->profiled_method();
2720 int bci = op->profiled_bci();
2721 ciMethod* callee = op->profiled_callee();
2722
2723 // Update counter for all call types.
2724 ciMethodData* md = method->method_data_or_null();
2725 assert(md != nullptr, "Sanity");
2726 ciProfileData* data = md->bci_to_data(bci);
2727 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2728 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2729 Register mdo = op->mdo()->as_register();
2730 #ifdef _LP64
2731 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2732 Register tmp1 = op->tmp1()->as_register_lo();
2733 #else
2734 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2735 Register tmp1 = op->tmp1()->as_register();
2736 #endif
2737 metadata2reg(md->constant_encoding(), mdo);
2738 int mdo_offset_bias = 0;
2739 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2740 data->size_in_bytes())) {
2741 // The offset is large so bias the mdo by the base of the slot so
2742 // that the ld can use simm16s to reference the slots of the data.
2743 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2744 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2745 }
2746
2747 // Perform additional virtual call profiling for invokevirtual and
2748 // invokeinterface bytecodes
2749 if (op->should_profile_receiver_type()) {
2750 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2751 Register recv = op->recv()->as_register();
2752 assert_different_registers(mdo, tmp1, recv);
2753 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2754 ciKlass* known_klass = op->known_holder();
2755 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2756 // We know the type that will be seen at this call site; we can
2757 // statically update the MethodData* rather than needing to do
2758 // dynamic tests on the receiver type.
2759
2760 // NOTE: we should probably put a lock around this search to
2761 // avoid collisions by concurrent compilations.
2762 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2763 uint i;
2764 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2765 ciKlass* receiver = vc_data->receiver(i);
2766 if (known_klass->equals(receiver)) {
2767 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2768 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2769 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2770 return;
2771 }
2772 }
2773
2774 // Receiver type not found in profile data; select an empty slot.
2775
2776 // Note that this is less efficient than it should be because it
2777 // always does a write to the receiver part of the
2778 // VirtualCallData rather than just the first time.
2779 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2780 ciKlass* receiver = vc_data->receiver(i);
2781 if (receiver == nullptr) {
2782 metadata2reg(known_klass->constant_encoding(), tmp1);
2783 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2784
2785 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2786 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2787 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2788 return;
2789 }
2790 }
2791 } else {
2792 __ load_klass(recv, recv);
2793 Label update_done;
2794 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2795 // Receiver did not match any saved receiver and there is no empty row for it.
2796 // Increment total counter to indicate polymorphic case.
2797 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2798 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2799 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2800
2801 __ bind(update_done);
2802 }
2803 } else {
2804 // Static call
2805 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2806 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2807 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2808 }
2809 }
2810
2811
2812 void LIR_Assembler::align_backward_branch_target() {
2813 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2814 }
2815
2816
2817 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2818 Unimplemented();
2819 }
2820
2821
2822 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2823 // tmp must be unused
2824 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2825 assert(left->is_register(), "can only handle registers");
2826
2827 if (left->is_single_cpu()) {
2828 __ neg(dest->as_register(), left->as_register());
2829 } else if (left->is_single_fpu()) {
2830 __ fneg(dest->as_float_reg(), left->as_float_reg());
2831 } else if (left->is_double_fpu()) {
2832 __ fneg(dest->as_double_reg(), left->as_double_reg());
2833 } else {
2834 assert (left->is_double_cpu(), "Must be a long");
2835 __ neg(dest->as_register_lo(), left->as_register_lo());
2836 }
2837 }
2838
2839
2840 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2841 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2842 // Stubs: Called via rt_call, but dest is a stub address (no FunctionDescriptor).
2843 if (dest == Runtime1::entry_for(C1StubId::register_finalizer_id) ||
2844 dest == Runtime1::entry_for(C1StubId::new_multi_array_id ) ||
2845 dest == Runtime1::entry_for(C1StubId::is_instance_of_id )) {
2846 assert(CodeCache::contains(dest), "simplified call is only for special C1 stubs");
2847 //__ load_const_optimized(R0, dest);
2848 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2849 __ mtctr(R0);
2850 __ bctrl();
2851 if (info != nullptr) {
2852 add_call_info_here(info);
2853 __ post_call_nop();
2854 }
2855 return;
2856 }
2857
2858 __ call_c(dest, relocInfo::runtime_call_type);
2859 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2860 if (info != nullptr) {
2861 add_call_info_here(info);
2862 __ post_call_nop();
2863 }
2864 }
2865
2866
2867 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2868 ShouldNotReachHere(); // Not needed on _LP64.
2869 }
2870
2871 void LIR_Assembler::membar() {
2872 __ fence();
2873 }
2874
2875 void LIR_Assembler::membar_acquire() {
2876 __ acquire();
2877 }
2878
2879 void LIR_Assembler::membar_release() {
2880 __ release();
2881 }
2882
2883 void LIR_Assembler::membar_loadload() {
2884 __ membar(Assembler::LoadLoad);
2885 }
2886
2887 void LIR_Assembler::membar_storestore() {
2888 __ membar(Assembler::StoreStore);
2889 }
2890
2891 void LIR_Assembler::membar_loadstore() {
2892 __ membar(Assembler::LoadStore);
2893 }
2894
2895 void LIR_Assembler::membar_storeload() {
2896 __ membar(Assembler::StoreLoad);
2897 }
2898
2899 void LIR_Assembler::on_spin_wait() {
2900 Unimplemented();
2901 }
2902
2903 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2904 LIR_Address* addr = addr_opr->as_address_ptr();
2905 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2906
2907 if (addr->index()->is_illegal()) {
2908 if (patch_code != lir_patch_none) {
2909 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2910 __ load_const32(R0, 0); // patchable int
2911 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2912 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2913 } else {
2914 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2915 }
2916 } else {
2917 assert(patch_code == lir_patch_none, "Patch code not supported");
2918 assert(addr->disp() == 0, "can't have both: index and disp");
2919 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2920 }
2921 }
2922
2923
2924 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2925 ShouldNotReachHere();
2926 }
2927
2928
2929 #ifdef ASSERT
2930 // Emit run-time assertion.
2931 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2932 Unimplemented();
2933 }
2934 #endif
2935
2936
2937 void LIR_Assembler::peephole(LIR_List* lir) {
2938 // Optimize instruction pairs before emitting.
2939 LIR_OpList* inst = lir->instructions_list();
2940 for (int i = 1; i < inst->length(); i++) {
2941 LIR_Op* op = inst->at(i);
2942
2943 // 2 register-register-moves
2944 if (op->code() == lir_move) {
2945 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2946 res2 = ((LIR_Op1*)op)->result_opr();
2947 if (in2->is_register() && res2->is_register()) {
2948 LIR_Op* prev = inst->at(i - 1);
2949 if (prev && prev->code() == lir_move) {
2950 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2951 res1 = ((LIR_Op1*)prev)->result_opr();
2952 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2953 inst->remove_at(i);
2954 }
2955 }
2956 }
2957 }
2958
2959 }
2960 return;
2961 }
2962
2963
2964 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2965 const LIR_Address *addr = src->as_address_ptr();
2966 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2967 const Register Rptr = addr->base()->as_pointer_register(),
2968 Rtmp = tmp->as_register();
2969 Register Robj = noreg;
2970 if (data->is_oop()) {
2971 if (UseCompressedOops) {
2972 Robj = __ encode_heap_oop(Rtmp, data->as_register());
2973 } else {
2974 Robj = data->as_register();
2975 if (Robj == dest->as_register()) { // May happen with ZGC.
2976 __ mr(Rtmp, Robj);
2977 Robj = Rtmp;
2978 }
2979 }
2980 }
2981
2982 // There might be a volatile load before this Unsafe OP.
2983 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2984 __ sync();
2985 } else {
2986 __ lwsync();
2987 }
2988
2989 Label Lretry;
2990 __ bind(Lretry);
2991
2992 if (data->type() == T_INT) {
2993 const Register Rold = dest->as_register(),
2994 Rsrc = data->as_register();
2995 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2996 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2997 if (code == lir_xadd) {
2998 __ add(Rtmp, Rsrc, Rold);
2999 __ stwcx_(Rtmp, Rptr);
3000 } else {
3001 __ stwcx_(Rsrc, Rptr);
3002 }
3003 } else if (data->is_oop()) {
3004 assert(code == lir_xchg, "xadd for oops");
3005 const Register Rold = dest->as_register();
3006 assert_different_registers(Rptr, Rold, Robj);
3007 if (UseCompressedOops) {
3008 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3009 __ stwcx_(Robj, Rptr);
3010 } else {
3011 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3012 __ stdcx_(Robj, Rptr);
3013 }
3014 } else if (data->type() == T_LONG) {
3015 const Register Rold = dest->as_register_lo(),
3016 Rsrc = data->as_register_lo();
3017 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3018 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3019 if (code == lir_xadd) {
3020 __ add(Rtmp, Rsrc, Rold);
3021 __ stdcx_(Rtmp, Rptr);
3022 } else {
3023 __ stdcx_(Rsrc, Rptr);
3024 }
3025 } else {
3026 ShouldNotReachHere();
3027 }
3028
3029 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3030 __ bne_predict_not_taken(CR0, Lretry);
3031 } else {
3032 __ bne( CR0, Lretry);
3033 }
3034
3035 if (UseCompressedOops && data->is_oop()) {
3036 __ decode_heap_oop(dest->as_register());
3037 }
3038
3039 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3040 __ isync();
3041 } else {
3042 __ sync();
3043 }
3044 }
3045
3046
3047 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3048 Register obj = op->obj()->as_register();
3049 Register tmp = op->tmp()->as_pointer_register();
3050 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3051 ciKlass* exact_klass = op->exact_klass();
3052 intptr_t current_klass = op->current_klass();
3053 bool not_null = op->not_null();
3054 bool no_conflict = op->no_conflict();
3055
3056 Label Lupdate, Ldo_update, Ldone;
3057
3058 bool do_null = !not_null;
3059 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3060 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3061
3062 assert(do_null || do_update, "why are we here?");
3063 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3064
3065 __ verify_oop(obj, FILE_AND_LINE);
3066
3067 if (do_null) {
3068 if (!TypeEntries::was_null_seen(current_klass)) {
3069 __ cmpdi(CR0, obj, 0);
3070 __ bne(CR0, Lupdate);
3071 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3072 __ ori(R0, R0, TypeEntries::null_seen);
3073 if (do_update) {
3074 __ b(Ldo_update);
3075 } else {
3076 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3077 }
3078 } else {
3079 if (do_update) {
3080 __ cmpdi(CR0, obj, 0);
3081 __ beq(CR0, Ldone);
3082 }
3083 }
3084 #ifdef ASSERT
3085 } else {
3086 __ cmpdi(CR0, obj, 0);
3087 __ bne(CR0, Lupdate);
3088 __ stop("unexpected null obj");
3089 #endif
3090 }
3091
3092 __ bind(Lupdate);
3093 if (do_update) {
3094 Label Lnext;
3095 const Register klass = R29_TOC; // kill and reload
3096 bool klass_reg_used = false;
3097 #ifdef ASSERT
3098 if (exact_klass != nullptr) {
3099 Label ok;
3100 klass_reg_used = true;
3101 __ load_klass(klass, obj);
3102 metadata2reg(exact_klass->constant_encoding(), R0);
3103 __ cmpd(CR0, klass, R0);
3104 __ beq(CR0, ok);
3105 __ stop("exact klass and actual klass differ");
3106 __ bind(ok);
3107 }
3108 #endif
3109
3110 if (!no_conflict) {
3111 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3112 klass_reg_used = true;
3113 if (exact_klass != nullptr) {
3114 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3115 metadata2reg(exact_klass->constant_encoding(), klass);
3116 } else {
3117 __ load_klass(klass, obj);
3118 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3119 }
3120
3121 // Like InterpreterMacroAssembler::profile_obj_type
3122 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3123 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3124 __ cmpd(CR1, R0, klass);
3125 // Klass seen before, nothing to do (regardless of unknown bit).
3126 //beq(CR1, do_nothing);
3127
3128 __ andi_(R0, tmp, TypeEntries::type_unknown);
3129 // Already unknown. Nothing to do anymore.
3130 //bne(CR0, do_nothing);
3131 __ crorc(CR0, Assembler::equal, CR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3132 __ beq(CR0, Lnext);
3133
3134 if (TypeEntries::is_type_none(current_klass)) {
3135 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3136 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3137 __ beq(CR0, Ldo_update); // First time here. Set profile type.
3138 }
3139
3140 } else {
3141 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3142 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3143
3144 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3145 __ andi_(R0, tmp, TypeEntries::type_unknown);
3146 // Already unknown. Nothing to do anymore.
3147 __ bne(CR0, Lnext);
3148 }
3149
3150 // Different than before. Cannot keep accurate profile.
3151 __ ori(R0, tmp, TypeEntries::type_unknown);
3152 } else {
3153 // There's a single possible klass at this profile point
3154 assert(exact_klass != nullptr, "should be");
3155 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3156
3157 if (TypeEntries::is_type_none(current_klass)) {
3158 klass_reg_used = true;
3159 metadata2reg(exact_klass->constant_encoding(), klass);
3160
3161 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3162 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3163 __ cmpd(CR1, R0, klass);
3164 // Klass seen before, nothing to do (regardless of unknown bit).
3165 __ beq(CR1, Lnext);
3166 #ifdef ASSERT
3167 {
3168 Label ok;
3169 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3170 __ beq(CR0, ok); // First time here.
3171
3172 __ stop("unexpected profiling mismatch");
3173 __ bind(ok);
3174 }
3175 #endif
3176 // First time here. Set profile type.
3177 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3178 } else {
3179 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3180 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3181
3182 // Already unknown. Nothing to do anymore.
3183 __ andi_(R0, tmp, TypeEntries::type_unknown);
3184 __ bne(CR0, Lnext);
3185
3186 // Different than before. Cannot keep accurate profile.
3187 __ ori(R0, tmp, TypeEntries::type_unknown);
3188 }
3189 }
3190
3191 __ bind(Ldo_update);
3192 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3193
3194 __ bind(Lnext);
3195 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3196 }
3197 __ bind(Ldone);
3198 }
3199
3200 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3201 Unimplemented();
3202 }
3203
3204 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3205 assert(op->crc()->is_single_cpu(), "crc must be register");
3206 assert(op->val()->is_single_cpu(), "byte value must be register");
3207 assert(op->result_opr()->is_single_cpu(), "result must be register");
3208 Register crc = op->crc()->as_register();
3209 Register val = op->val()->as_register();
3210 Register res = op->result_opr()->as_register();
3211
3212 assert_different_registers(val, crc, res);
3213
3214 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3215 __ kernel_crc32_singleByteReg(crc, val, res, true);
3216 __ mr(res, crc);
3217 }
3218
3219 #undef __