1 /* 2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2022 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/collectedHeap.hpp" 36 #include "memory/universe.hpp" 37 #include "nativeInst_ppc.hpp" 38 #include "oops/compressedOops.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/frame.inline.hpp" 41 #include "runtime/os.inline.hpp" 42 #include "runtime/safepointMechanism.inline.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/stubRoutines.hpp" 45 #include "runtime/vm_version.hpp" 46 #include "utilities/macros.hpp" 47 #include "utilities/powerOfTwo.hpp" 48 49 #define __ _masm-> 50 51 52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5; 53 54 55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 56 Unimplemented(); return false; // Currently not used on this platform. 57 } 58 59 60 LIR_Opr LIR_Assembler::receiverOpr() { 61 return FrameMap::R3_oop_opr; 62 } 63 64 65 LIR_Opr LIR_Assembler::osrBufferPointer() { 66 return FrameMap::R3_opr; 67 } 68 69 70 // This specifies the stack pointer decrement needed to build the frame. 71 int LIR_Assembler::initial_frame_size_in_bytes() const { 72 return in_bytes(frame_map()->framesize_in_bytes()); 73 } 74 75 76 // Inline cache check: the inline cached class is in inline_cache_reg; 77 // we fetch the class of the receiver and compare it with the cached class. 78 // If they do not match we jump to slow case. 79 int LIR_Assembler::check_icache() { 80 int offset = __ offset(); 81 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg); 82 return offset; 83 } 84 85 void LIR_Assembler::clinit_barrier(ciMethod* method) { 86 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 87 88 Label L_skip_barrier; 89 Register klass = R20; 90 91 metadata2reg(method->holder()->constant_encoding(), klass); 92 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/); 93 94 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0); 95 __ mtctr(klass); 96 __ bctr(); 97 98 __ bind(L_skip_barrier); 99 } 100 101 void LIR_Assembler::osr_entry() { 102 // On-stack-replacement entry sequence: 103 // 104 // 1. Create a new compiled activation. 105 // 2. Initialize local variables in the compiled activation. The expression 106 // stack must be empty at the osr_bci; it is not initialized. 107 // 3. Jump to the continuation address in compiled code to resume execution. 108 109 // OSR entry point 110 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 111 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 112 ValueStack* entry_state = osr_entry->end()->state(); 113 int number_of_locks = entry_state->locks_size(); 114 115 // Create a frame for the compiled activation. 116 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 117 118 // OSR buffer is 119 // 120 // locals[nlocals-1..0] 121 // monitors[number_of_locks-1..0] 122 // 123 // Locals is a direct copy of the interpreter frame so in the osr buffer 124 // the first slot in the local array is the last local from the interpreter 125 // and the last slot is local[0] (receiver) from the interpreter. 126 // 127 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 128 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 129 // in the interpreter frame (the method lock if a sync method). 130 131 // Initialize monitors in the compiled activation. 132 // R3: pointer to osr buffer 133 // 134 // All other registers are dead at this point and the locals will be 135 // copied into place by code emitted in the IR. 136 137 Register OSR_buf = osrBufferPointer()->as_register(); 138 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 139 int monitor_offset = BytesPerWord * method()->max_locals() + 140 (2 * BytesPerWord) * (number_of_locks - 1); 141 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 142 // the OSR buffer using 2 word entries: first the lock and then 143 // the oop. 144 for (int i = 0; i < number_of_locks; i++) { 145 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 146 #ifdef ASSERT 147 // Verify the interpreter's monitor has a non-null object. 148 { 149 Label L; 150 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); 151 __ cmpdi(CCR0, R0, 0); 152 __ bne(CCR0, L); 153 __ stop("locked object is NULL"); 154 __ bind(L); 155 } 156 #endif // ASSERT 157 // Copy the lock field into the compiled activation. 158 Address ml = frame_map()->address_for_monitor_lock(i), 159 mo = frame_map()->address_for_monitor_object(i); 160 assert(ml.index() == noreg && mo.index() == noreg, "sanity"); 161 __ ld(R0, slot_offset + 0, OSR_buf); 162 __ std(R0, ml.disp(), ml.base()); 163 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); 164 __ std(R0, mo.disp(), mo.base()); 165 } 166 } 167 } 168 169 170 int LIR_Assembler::emit_exception_handler() { 171 // Generate code for the exception handler. 172 address handler_base = __ start_a_stub(exception_handler_size()); 173 174 if (handler_base == NULL) { 175 // Not enough space left for the handler. 176 bailout("exception handler overflow"); 177 return -1; 178 } 179 180 int offset = code_offset(); 181 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)); 182 //__ load_const_optimized(R0, entry_point); 183 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point)); 184 __ mtctr(R0); 185 __ bctr(); 186 187 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 188 __ end_a_stub(); 189 190 return offset; 191 } 192 193 194 // Emit the code to remove the frame from the stack in the exception 195 // unwind path. 196 int LIR_Assembler::emit_unwind_handler() { 197 _masm->block_comment("Unwind handler"); 198 199 int offset = code_offset(); 200 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes(); 201 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31; 202 203 // Fetch the exception from TLS and clear out exception related thread state. 204 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread); 205 __ li(R0, 0); 206 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread); 207 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread); 208 209 __ bind(_unwind_handler_entry); 210 __ verify_not_null_oop(Rexception); 211 if (preserve_exception) { __ mr(Rexception_save, Rexception); } 212 213 // Perform needed unlocking 214 MonitorExitStub* stub = NULL; 215 if (method()->is_synchronized()) { 216 monitor_address(0, FrameMap::R4_opr); 217 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0); 218 __ unlock_object(R5, R6, R4, *stub->entry()); 219 __ bind(*stub->continuation()); 220 } 221 222 if (compilation()->env()->dtrace_method_probes()) { 223 Unimplemented(); 224 } 225 226 // Dispatch to the unwind logic. 227 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id); 228 //__ load_const_optimized(R0, unwind_stub); 229 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub)); 230 if (preserve_exception) { __ mr(Rexception, Rexception_save); } 231 __ mtctr(R0); 232 __ bctr(); 233 234 // Emit the slow path assembly. 235 if (stub != NULL) { 236 stub->emit_code(this); 237 } 238 239 return offset; 240 } 241 242 243 int LIR_Assembler::emit_deopt_handler() { 244 // Generate code for deopt handler. 245 address handler_base = __ start_a_stub(deopt_handler_size()); 246 247 if (handler_base == NULL) { 248 // Not enough space left for the handler. 249 bailout("deopt handler overflow"); 250 return -1; 251 } 252 253 int offset = code_offset(); 254 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type); 255 256 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 257 __ end_a_stub(); 258 259 return offset; 260 } 261 262 263 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 264 if (o == NULL) { 265 __ li(reg, 0); 266 } else { 267 AddressLiteral addrlit = __ constant_oop_address(o); 268 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg); 269 } 270 } 271 272 273 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 274 // Allocate a new index in table to hold the object once it's been patched. 275 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 276 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 277 278 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index)); 279 __ load_const(reg, addrlit, R0); 280 281 patching_epilog(patch, lir_patch_normal, reg, info); 282 } 283 284 285 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { 286 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation) 287 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg); 288 } 289 290 291 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 292 // Allocate a new index in table to hold the klass once it's been patched. 293 int index = __ oop_recorder()->allocate_metadata_index(NULL); 294 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 295 296 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index)); 297 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 298 __ load_const(reg, addrlit, R0); 299 300 patching_epilog(patch, lir_patch_normal, reg, info); 301 } 302 303 304 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 305 const bool is_int = result->is_single_cpu(); 306 Register Rdividend = is_int ? left->as_register() : left->as_register_lo(); 307 Register Rdivisor = noreg; 308 Register Rscratch = temp->as_register(); 309 Register Rresult = is_int ? result->as_register() : result->as_register_lo(); 310 long divisor = -1; 311 312 if (right->is_register()) { 313 Rdivisor = is_int ? right->as_register() : right->as_register_lo(); 314 } else { 315 divisor = is_int ? right->as_constant_ptr()->as_jint() 316 : right->as_constant_ptr()->as_jlong(); 317 } 318 319 assert(Rdividend != Rscratch, ""); 320 assert(Rdivisor != Rscratch, ""); 321 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv"); 322 323 if (Rdivisor == noreg) { 324 if (divisor == 1) { // stupid, but can happen 325 if (code == lir_idiv) { 326 __ mr_if_needed(Rresult, Rdividend); 327 } else { 328 __ li(Rresult, 0); 329 } 330 331 } else if (is_power_of_2(divisor)) { 332 // Convert division by a power of two into some shifts and logical operations. 333 int log2 = log2i_exact(divisor); 334 335 // Round towards 0. 336 if (divisor == 2) { 337 if (is_int) { 338 __ srwi(Rscratch, Rdividend, 31); 339 } else { 340 __ srdi(Rscratch, Rdividend, 63); 341 } 342 } else { 343 if (is_int) { 344 __ srawi(Rscratch, Rdividend, 31); 345 } else { 346 __ sradi(Rscratch, Rdividend, 63); 347 } 348 __ clrldi(Rscratch, Rscratch, 64-log2); 349 } 350 __ add(Rscratch, Rdividend, Rscratch); 351 352 if (code == lir_idiv) { 353 if (is_int) { 354 __ srawi(Rresult, Rscratch, log2); 355 } else { 356 __ sradi(Rresult, Rscratch, log2); 357 } 358 } else { // lir_irem 359 __ clrrdi(Rscratch, Rscratch, log2); 360 __ sub(Rresult, Rdividend, Rscratch); 361 } 362 363 } else if (divisor == -1) { 364 if (code == lir_idiv) { 365 __ neg(Rresult, Rdividend); 366 } else { 367 __ li(Rresult, 0); 368 } 369 370 } else { 371 __ load_const_optimized(Rscratch, divisor); 372 if (code == lir_idiv) { 373 if (is_int) { 374 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1. 375 } else { 376 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1. 377 } 378 } else { 379 assert(Rscratch != R0, "need both"); 380 if (is_int) { 381 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1. 382 __ mullw(Rscratch, R0, Rscratch); 383 } else { 384 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1. 385 __ mulld(Rscratch, R0, Rscratch); 386 } 387 __ sub(Rresult, Rdividend, Rscratch); 388 } 389 390 } 391 return; 392 } 393 394 Label regular, done; 395 if (is_int) { 396 __ cmpwi(CCR0, Rdivisor, -1); 397 } else { 398 __ cmpdi(CCR0, Rdivisor, -1); 399 } 400 __ bne(CCR0, regular); 401 if (code == lir_idiv) { 402 __ neg(Rresult, Rdividend); 403 __ b(done); 404 __ bind(regular); 405 if (is_int) { 406 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1. 407 } else { 408 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1. 409 } 410 } else { // lir_irem 411 __ li(Rresult, 0); 412 __ b(done); 413 __ bind(regular); 414 if (is_int) { 415 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1. 416 __ mullw(Rscratch, Rscratch, Rdivisor); 417 } else { 418 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1. 419 __ mulld(Rscratch, Rscratch, Rdivisor); 420 } 421 __ sub(Rresult, Rdividend, Rscratch); 422 } 423 __ bind(done); 424 } 425 426 427 void LIR_Assembler::emit_op3(LIR_Op3* op) { 428 switch (op->code()) { 429 case lir_idiv: 430 case lir_irem: 431 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(), 432 op->result_opr(), op->info()); 433 break; 434 case lir_fmad: 435 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(), 436 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg()); 437 break; 438 case lir_fmaf: 439 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(), 440 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg()); 441 break; 442 default: ShouldNotReachHere(); break; 443 } 444 } 445 446 447 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 448 #ifdef ASSERT 449 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 450 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 451 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 452 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 453 #endif 454 455 Label *L = op->label(); 456 if (op->cond() == lir_cond_always) { 457 __ b(*L); 458 } else { 459 Label done; 460 bool is_unordered = false; 461 if (op->code() == lir_cond_float_branch) { 462 assert(op->ublock() != NULL, "must have unordered successor"); 463 is_unordered = true; 464 } else { 465 assert(op->code() == lir_branch, "just checking"); 466 } 467 468 bool positive = false; 469 Assembler::Condition cond = Assembler::equal; 470 switch (op->cond()) { 471 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break; 472 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break; 473 case lir_cond_less: positive = true ; cond = Assembler::less ; break; 474 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru 475 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break; 476 case lir_cond_greater: positive = true ; cond = Assembler::greater; break; 477 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru 478 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break; 479 default: ShouldNotReachHere(); 480 } 481 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0; 482 int bi = Assembler::bi0(BOOL_RESULT, cond); 483 if (is_unordered) { 484 if (positive) { 485 if (op->ublock() == op->block()) { 486 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L); 487 } 488 } else { 489 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); } 490 } 491 } 492 __ bc_far_optimized(bo, bi, *L); 493 __ bind(done); 494 } 495 } 496 497 498 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 499 Bytecodes::Code code = op->bytecode(); 500 LIR_Opr src = op->in_opr(), 501 dst = op->result_opr(); 502 503 switch(code) { 504 case Bytecodes::_i2l: { 505 __ extsw(dst->as_register_lo(), src->as_register()); 506 break; 507 } 508 case Bytecodes::_l2i: { 509 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage 510 break; 511 } 512 case Bytecodes::_i2b: { 513 __ extsb(dst->as_register(), src->as_register()); 514 break; 515 } 516 case Bytecodes::_i2c: { 517 __ clrldi(dst->as_register(), src->as_register(), 64-16); 518 break; 519 } 520 case Bytecodes::_i2s: { 521 __ extsh(dst->as_register(), src->as_register()); 522 break; 523 } 524 case Bytecodes::_i2d: 525 case Bytecodes::_l2d: { 526 bool src_in_memory = !VM_Version::has_mtfprd(); 527 FloatRegister rdst = dst->as_double_reg(); 528 FloatRegister rsrc; 529 if (src_in_memory) { 530 rsrc = src->as_double_reg(); // via mem 531 } else { 532 // move src to dst register 533 if (code == Bytecodes::_i2d) { 534 __ mtfprwa(rdst, src->as_register()); 535 } else { 536 __ mtfprd(rdst, src->as_register_lo()); 537 } 538 rsrc = rdst; 539 } 540 __ fcfid(rdst, rsrc); 541 break; 542 } 543 case Bytecodes::_i2f: 544 case Bytecodes::_l2f: { 545 bool src_in_memory = !VM_Version::has_mtfprd(); 546 FloatRegister rdst = dst->as_float_reg(); 547 FloatRegister rsrc; 548 if (src_in_memory) { 549 rsrc = src->as_double_reg(); // via mem 550 } else { 551 // move src to dst register 552 if (code == Bytecodes::_i2f) { 553 __ mtfprwa(rdst, src->as_register()); 554 } else { 555 __ mtfprd(rdst, src->as_register_lo()); 556 } 557 rsrc = rdst; 558 } 559 if (VM_Version::has_fcfids()) { 560 __ fcfids(rdst, rsrc); 561 } else { 562 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility"); 563 __ fcfid(rdst, rsrc); 564 __ frsp(rdst, rdst); 565 } 566 break; 567 } 568 case Bytecodes::_f2d: { 569 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg()); 570 break; 571 } 572 case Bytecodes::_d2f: { 573 __ frsp(dst->as_float_reg(), src->as_double_reg()); 574 break; 575 } 576 case Bytecodes::_d2i: 577 case Bytecodes::_f2i: { 578 bool dst_in_memory = !VM_Version::has_mtfprd(); 579 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg(); 580 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address(); 581 Label L; 582 // Result must be 0 if value is NaN; test by comparing value to itself. 583 __ fcmpu(CCR0, rsrc, rsrc); 584 if (dst_in_memory) { 585 __ li(R0, 0); // 0 in case of NAN 586 __ std(R0, addr.disp(), addr.base()); 587 } else { 588 __ li(dst->as_register(), 0); 589 } 590 __ bso(CCR0, L); 591 __ fctiwz(rsrc, rsrc); // USE_KILL 592 if (dst_in_memory) { 593 __ stfd(rsrc, addr.disp(), addr.base()); 594 } else { 595 __ mffprd(dst->as_register(), rsrc); 596 } 597 __ bind(L); 598 break; 599 } 600 case Bytecodes::_d2l: 601 case Bytecodes::_f2l: { 602 bool dst_in_memory = !VM_Version::has_mtfprd(); 603 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg(); 604 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address(); 605 Label L; 606 // Result must be 0 if value is NaN; test by comparing value to itself. 607 __ fcmpu(CCR0, rsrc, rsrc); 608 if (dst_in_memory) { 609 __ li(R0, 0); // 0 in case of NAN 610 __ std(R0, addr.disp(), addr.base()); 611 } else { 612 __ li(dst->as_register_lo(), 0); 613 } 614 __ bso(CCR0, L); 615 __ fctidz(rsrc, rsrc); // USE_KILL 616 if (dst_in_memory) { 617 __ stfd(rsrc, addr.disp(), addr.base()); 618 } else { 619 __ mffprd(dst->as_register_lo(), rsrc); 620 } 621 __ bind(L); 622 break; 623 } 624 625 default: ShouldNotReachHere(); 626 } 627 } 628 629 630 void LIR_Assembler::align_call(LIR_Code) { 631 // do nothing since all instructions are word aligned on ppc 632 } 633 634 635 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) { 636 int start_offset = __ offset(); 637 // Put the entry point as a constant into the constant pool. 638 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none); 639 if (entry_point_toc_addr == NULL) { 640 bailout("const section overflow"); 641 return false; 642 } 643 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 644 645 // Emit the trampoline stub which will be related to the branch-and-link below. 646 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc); 647 if (!stub) { 648 bailout("no space for trampoline stub"); 649 return false; 650 } 651 return true; 652 } 653 654 655 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 656 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype"); 657 658 bool success = emit_trampoline_stub_for_call(op->addr()); 659 if (!success) { return; } 660 661 __ relocate(rtype); 662 // Note: At this point we do not have the address of the trampoline 663 // stub, and the entry point might be too far away for bl, so __ pc() 664 // serves as dummy and the bl will be patched later. 665 __ code()->set_insts_mark(); 666 __ bl(__ pc()); 667 add_call_info(code_offset(), op->info()); 668 __ post_call_nop(); 669 } 670 671 672 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 673 __ calculate_address_from_global_toc(R2_TOC, __ method_toc()); 674 675 // Virtual call relocation will point to ic load. 676 address virtual_call_meta_addr = __ pc(); 677 // Load a clear inline cache. 678 AddressLiteral empty_ic((address) Universe::non_oop_word()); 679 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC); 680 if (!success) { 681 bailout("const section overflow"); 682 return; 683 } 684 // Call to fixup routine. Fixup routine uses ScopeDesc info 685 // to determine who we intended to call. 686 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 687 688 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC); 689 if (!success) { return; } 690 691 // Note: At this point we do not have the address of the trampoline 692 // stub, and the entry point might be too far away for bl, so __ pc() 693 // serves as dummy and the bl will be patched later. 694 __ bl(__ pc()); 695 add_call_info(code_offset(), op->info()); 696 __ post_call_nop(); 697 } 698 699 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) { 700 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info); 701 __ null_check(addr, stub->entry()); 702 append_code_stub(stub); 703 } 704 705 706 // Attention: caller must encode oop if needed 707 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) { 708 int store_offset; 709 if (!Assembler::is_simm16(offset)) { 710 // For offsets larger than a simm16 we setup the offset. 711 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case"); 712 __ load_const_optimized(R0, offset); 713 store_offset = store(from_reg, base, R0, type, wide); 714 } else { 715 store_offset = code_offset(); 716 switch (type) { 717 case T_BOOLEAN: // fall through 718 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break; 719 case T_CHAR : 720 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break; 721 case T_INT : __ stw(from_reg->as_register(), offset, base); break; 722 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break; 723 case T_ADDRESS: 724 case T_METADATA: __ std(from_reg->as_register(), offset, base); break; 725 case T_ARRAY : // fall through 726 case T_OBJECT: 727 { 728 if (UseCompressedOops && !wide) { 729 // Encoding done in caller 730 __ stw(from_reg->as_register(), offset, base); 731 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); 732 } else { 733 __ std(from_reg->as_register(), offset, base); 734 __ verify_oop(from_reg->as_register(), FILE_AND_LINE); 735 } 736 break; 737 } 738 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break; 739 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break; 740 default : ShouldNotReachHere(); 741 } 742 } 743 return store_offset; 744 } 745 746 747 // Attention: caller must encode oop if needed 748 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { 749 int store_offset = code_offset(); 750 switch (type) { 751 case T_BOOLEAN: // fall through 752 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break; 753 case T_CHAR : 754 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break; 755 case T_INT : __ stwx(from_reg->as_register(), base, disp); break; 756 case T_LONG : 757 #ifdef _LP64 758 __ stdx(from_reg->as_register_lo(), base, disp); 759 #else 760 Unimplemented(); 761 #endif 762 break; 763 case T_ADDRESS: 764 __ stdx(from_reg->as_register(), base, disp); 765 break; 766 case T_ARRAY : // fall through 767 case T_OBJECT: 768 { 769 if (UseCompressedOops && !wide) { 770 // Encoding done in caller. 771 __ stwx(from_reg->as_register(), base, disp); 772 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0 773 } else { 774 __ stdx(from_reg->as_register(), base, disp); 775 __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0 776 } 777 break; 778 } 779 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break; 780 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break; 781 default : ShouldNotReachHere(); 782 } 783 return store_offset; 784 } 785 786 787 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) { 788 int load_offset; 789 if (!Assembler::is_simm16(offset)) { 790 // For offsets larger than a simm16 we setup the offset. 791 __ load_const_optimized(R0, offset); 792 load_offset = load(base, R0, to_reg, type, wide); 793 } else { 794 load_offset = code_offset(); 795 switch(type) { 796 case T_BOOLEAN: // fall through 797 case T_BYTE : __ lbz(to_reg->as_register(), offset, base); 798 __ extsb(to_reg->as_register(), to_reg->as_register()); break; 799 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break; 800 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break; 801 case T_INT : __ lwa(to_reg->as_register(), offset, base); break; 802 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break; 803 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break; 804 case T_ADDRESS: 805 __ ld(to_reg->as_register(), offset, base); 806 break; 807 case T_ARRAY : // fall through 808 case T_OBJECT: 809 { 810 if (UseCompressedOops && !wide) { 811 __ lwz(to_reg->as_register(), offset, base); 812 __ decode_heap_oop(to_reg->as_register()); 813 } else { 814 __ ld(to_reg->as_register(), offset, base); 815 } 816 __ verify_oop(to_reg->as_register(), FILE_AND_LINE); 817 break; 818 } 819 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break; 820 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break; 821 default : ShouldNotReachHere(); 822 } 823 } 824 return load_offset; 825 } 826 827 828 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { 829 int load_offset = code_offset(); 830 switch(type) { 831 case T_BOOLEAN: // fall through 832 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp); 833 __ extsb(to_reg->as_register(), to_reg->as_register()); break; 834 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break; 835 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break; 836 case T_INT : __ lwax(to_reg->as_register(), base, disp); break; 837 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break; 838 case T_ARRAY : // fall through 839 case T_OBJECT: 840 { 841 if (UseCompressedOops && !wide) { 842 __ lwzx(to_reg->as_register(), base, disp); 843 __ decode_heap_oop(to_reg->as_register()); 844 } else { 845 __ ldx(to_reg->as_register(), base, disp); 846 } 847 __ verify_oop(to_reg->as_register(), FILE_AND_LINE); 848 break; 849 } 850 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break; 851 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break; 852 case T_LONG : 853 #ifdef _LP64 854 __ ldx(to_reg->as_register_lo(), base, disp); 855 #else 856 Unimplemented(); 857 #endif 858 break; 859 default : ShouldNotReachHere(); 860 } 861 return load_offset; 862 } 863 864 865 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 866 LIR_Const* c = src->as_constant_ptr(); 867 Register src_reg = R0; 868 switch (c->type()) { 869 case T_INT: 870 case T_FLOAT: { 871 int value = c->as_jint_bits(); 872 __ load_const_optimized(src_reg, value); 873 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 874 __ stw(src_reg, addr.disp(), addr.base()); 875 break; 876 } 877 case T_ADDRESS: { 878 int value = c->as_jint_bits(); 879 __ load_const_optimized(src_reg, value); 880 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 881 __ std(src_reg, addr.disp(), addr.base()); 882 break; 883 } 884 case T_OBJECT: { 885 jobject2reg(c->as_jobject(), src_reg); 886 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 887 __ std(src_reg, addr.disp(), addr.base()); 888 break; 889 } 890 case T_LONG: 891 case T_DOUBLE: { 892 int value = c->as_jlong_bits(); 893 __ load_const_optimized(src_reg, value); 894 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 895 __ std(src_reg, addr.disp(), addr.base()); 896 break; 897 } 898 default: 899 Unimplemented(); 900 } 901 } 902 903 904 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 905 LIR_Const* c = src->as_constant_ptr(); 906 LIR_Address* addr = dest->as_address_ptr(); 907 Register base = addr->base()->as_pointer_register(); 908 LIR_Opr tmp = LIR_OprFact::illegalOpr; 909 int offset = -1; 910 // Null check for large offsets in LIRGenerator::do_StoreField. 911 bool needs_explicit_null_check = !ImplicitNullChecks; 912 913 if (info != NULL && needs_explicit_null_check) { 914 explicit_null_check(base, info); 915 } 916 917 switch (c->type()) { 918 case T_FLOAT: type = T_INT; 919 case T_INT: 920 case T_ADDRESS: { 921 tmp = FrameMap::R0_opr; 922 __ load_const_optimized(tmp->as_register(), c->as_jint_bits()); 923 break; 924 } 925 case T_DOUBLE: type = T_LONG; 926 case T_LONG: { 927 tmp = FrameMap::R0_long_opr; 928 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits()); 929 break; 930 } 931 case T_OBJECT: { 932 tmp = FrameMap::R0_opr; 933 if (UseCompressedOops && !wide && c->as_jobject() != NULL) { 934 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject()); 935 // Don't care about sign extend (will use stw). 936 __ lis(R0, 0); // Will get patched. 937 __ relocate(oop_addr.rspec(), /*compressed format*/ 1); 938 __ ori(R0, R0, 0); // Will get patched. 939 } else { 940 jobject2reg(c->as_jobject(), R0); 941 } 942 break; 943 } 944 default: 945 Unimplemented(); 946 } 947 948 // Handle either reg+reg or reg+disp address. 949 if (addr->index()->is_valid()) { 950 assert(addr->disp() == 0, "must be zero"); 951 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 952 } else { 953 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses"); 954 offset = store(tmp, base, addr->disp(), type, wide); 955 } 956 957 if (info != NULL) { 958 assert(offset != -1, "offset should've been set"); 959 if (!needs_explicit_null_check) { 960 add_debug_info_for_null_check(offset, info); 961 } 962 } 963 } 964 965 966 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 967 LIR_Const* c = src->as_constant_ptr(); 968 LIR_Opr to_reg = dest; 969 970 switch (c->type()) { 971 case T_INT: { 972 assert(patch_code == lir_patch_none, "no patching handled here"); 973 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); 974 break; 975 } 976 case T_ADDRESS: { 977 assert(patch_code == lir_patch_none, "no patching handled here"); 978 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ... 979 break; 980 } 981 case T_LONG: { 982 assert(patch_code == lir_patch_none, "no patching handled here"); 983 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0); 984 break; 985 } 986 987 case T_OBJECT: { 988 if (patch_code == lir_patch_none) { 989 jobject2reg(c->as_jobject(), to_reg->as_register()); 990 } else { 991 jobject2reg_with_patching(to_reg->as_register(), info); 992 } 993 break; 994 } 995 996 case T_METADATA: 997 { 998 if (patch_code == lir_patch_none) { 999 metadata2reg(c->as_metadata(), to_reg->as_register()); 1000 } else { 1001 klass2reg_with_patching(to_reg->as_register(), info); 1002 } 1003 } 1004 break; 1005 1006 case T_FLOAT: 1007 { 1008 if (to_reg->is_single_fpu()) { 1009 address const_addr = __ float_constant(c->as_jfloat()); 1010 if (const_addr == NULL) { 1011 bailout("const section overflow"); 1012 break; 1013 } 1014 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1015 __ relocate(rspec); 1016 __ load_const(R0, const_addr); 1017 __ lfsx(to_reg->as_float_reg(), R0); 1018 } else { 1019 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1020 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0); 1021 } 1022 } 1023 break; 1024 1025 case T_DOUBLE: 1026 { 1027 if (to_reg->is_double_fpu()) { 1028 address const_addr = __ double_constant(c->as_jdouble()); 1029 if (const_addr == NULL) { 1030 bailout("const section overflow"); 1031 break; 1032 } 1033 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1034 __ relocate(rspec); 1035 __ load_const(R0, const_addr); 1036 __ lfdx(to_reg->as_double_reg(), R0); 1037 } else { 1038 assert(to_reg->is_double_cpu(), "Must be a long register."); 1039 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0); 1040 } 1041 } 1042 break; 1043 1044 default: 1045 ShouldNotReachHere(); 1046 } 1047 } 1048 1049 1050 Address LIR_Assembler::as_Address(LIR_Address* addr) { 1051 Unimplemented(); return Address(); 1052 } 1053 1054 1055 inline RegisterOrConstant index_or_disp(LIR_Address* addr) { 1056 if (addr->index()->is_illegal()) { 1057 return (RegisterOrConstant)(addr->disp()); 1058 } else { 1059 return (RegisterOrConstant)(addr->index()->as_pointer_register()); 1060 } 1061 } 1062 1063 1064 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1065 const Register tmp = R0; 1066 switch (type) { 1067 case T_INT: 1068 case T_FLOAT: { 1069 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1070 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1071 __ lwz(tmp, from.disp(), from.base()); 1072 __ stw(tmp, to.disp(), to.base()); 1073 break; 1074 } 1075 case T_ADDRESS: 1076 case T_OBJECT: { 1077 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1078 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1079 __ ld(tmp, from.disp(), from.base()); 1080 __ std(tmp, to.disp(), to.base()); 1081 break; 1082 } 1083 case T_LONG: 1084 case T_DOUBLE: { 1085 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1086 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1087 __ ld(tmp, from.disp(), from.base()); 1088 __ std(tmp, to.disp(), to.base()); 1089 break; 1090 } 1091 1092 default: 1093 ShouldNotReachHere(); 1094 } 1095 } 1096 1097 1098 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1099 Unimplemented(); return Address(); 1100 } 1101 1102 1103 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1104 Unimplemented(); return Address(); 1105 } 1106 1107 1108 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1109 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 1110 1111 assert(type != T_METADATA, "load of metadata ptr not supported"); 1112 LIR_Address* addr = src_opr->as_address_ptr(); 1113 LIR_Opr to_reg = dest; 1114 1115 Register src = addr->base()->as_pointer_register(); 1116 Register disp_reg = noreg; 1117 int disp_value = addr->disp(); 1118 bool needs_patching = (patch_code != lir_patch_none); 1119 // null check for large offsets in LIRGenerator::do_LoadField 1120 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks; 1121 1122 if (info != NULL && needs_explicit_null_check) { 1123 explicit_null_check(src, info); 1124 } 1125 1126 if (addr->base()->type() == T_OBJECT) { 1127 __ verify_oop(src, FILE_AND_LINE); 1128 } 1129 1130 PatchingStub* patch = NULL; 1131 if (needs_patching) { 1132 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1133 assert(!to_reg->is_double_cpu() || 1134 patch_code == lir_patch_none || 1135 patch_code == lir_patch_normal, "patching doesn't match register"); 1136 } 1137 1138 if (addr->index()->is_illegal()) { 1139 if (!Assembler::is_simm16(disp_value)) { 1140 if (needs_patching) { 1141 __ load_const32(R0, 0); // patchable int 1142 } else { 1143 __ load_const_optimized(R0, disp_value); 1144 } 1145 disp_reg = R0; 1146 } 1147 } else { 1148 disp_reg = addr->index()->as_pointer_register(); 1149 assert(disp_value == 0, "can't handle 3 operand addresses"); 1150 } 1151 1152 // Remember the offset of the load. The patching_epilog must be done 1153 // before the call to add_debug_info, otherwise the PcDescs don't get 1154 // entered in increasing order. 1155 int offset; 1156 1157 if (disp_reg == noreg) { 1158 assert(Assembler::is_simm16(disp_value), "should have set this up"); 1159 offset = load(src, disp_value, to_reg, type, wide); 1160 } else { 1161 offset = load(src, disp_reg, to_reg, type, wide); 1162 } 1163 1164 if (patch != NULL) { 1165 patching_epilog(patch, patch_code, src, info); 1166 } 1167 if (info != NULL && !needs_explicit_null_check) { 1168 add_debug_info_for_null_check(offset, info); 1169 } 1170 } 1171 1172 1173 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1174 Address addr; 1175 if (src->is_single_word()) { 1176 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1177 } else if (src->is_double_word()) { 1178 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1179 } 1180 1181 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/); 1182 } 1183 1184 1185 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1186 Address addr; 1187 if (dest->is_single_word()) { 1188 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1189 } else if (dest->is_double_word()) { 1190 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1191 } 1192 1193 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/); 1194 } 1195 1196 1197 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1198 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1199 if (from_reg->is_double_fpu()) { 1200 // double to double moves 1201 assert(to_reg->is_double_fpu(), "should match"); 1202 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg()); 1203 } else { 1204 // float to float moves 1205 assert(to_reg->is_single_fpu(), "should match"); 1206 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg()); 1207 } 1208 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1209 if (from_reg->is_double_cpu()) { 1210 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register()); 1211 } else if (to_reg->is_double_cpu()) { 1212 // int to int moves 1213 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register()); 1214 } else { 1215 // int to int moves 1216 __ mr_if_needed(to_reg->as_register(), from_reg->as_register()); 1217 } 1218 } else { 1219 ShouldNotReachHere(); 1220 } 1221 if (is_reference_type(to_reg->type())) { 1222 __ verify_oop(to_reg->as_register(), FILE_AND_LINE); 1223 } 1224 } 1225 1226 1227 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1228 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1229 bool wide) { 1230 assert(type != T_METADATA, "store of metadata ptr not supported"); 1231 LIR_Address* addr = dest->as_address_ptr(); 1232 1233 Register src = addr->base()->as_pointer_register(); 1234 Register disp_reg = noreg; 1235 int disp_value = addr->disp(); 1236 bool needs_patching = (patch_code != lir_patch_none); 1237 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide && 1238 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop; 1239 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value); 1240 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29. 1241 // Null check for large offsets in LIRGenerator::do_StoreField. 1242 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29; 1243 1244 if (info != NULL && needs_explicit_null_check) { 1245 explicit_null_check(src, info); 1246 } 1247 1248 if (addr->base()->is_oop_register()) { 1249 __ verify_oop(src, FILE_AND_LINE); 1250 } 1251 1252 PatchingStub* patch = NULL; 1253 if (needs_patching) { 1254 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1255 assert(!from_reg->is_double_cpu() || 1256 patch_code == lir_patch_none || 1257 patch_code == lir_patch_normal, "patching doesn't match register"); 1258 } 1259 1260 if (addr->index()->is_illegal()) { 1261 if (load_disp) { 1262 disp_reg = use_R29 ? R29_TOC : R0; 1263 if (needs_patching) { 1264 __ load_const32(disp_reg, 0); // patchable int 1265 } else { 1266 __ load_const_optimized(disp_reg, disp_value); 1267 } 1268 } 1269 } else { 1270 disp_reg = addr->index()->as_pointer_register(); 1271 assert(disp_value == 0, "can't handle 3 operand addresses"); 1272 } 1273 1274 // remember the offset of the store. The patching_epilog must be done 1275 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1276 // entered in increasing order. 1277 int offset; 1278 1279 if (compress_oop) { 1280 Register co = __ encode_heap_oop(R0, from_reg->as_register()); 1281 from_reg = FrameMap::as_opr(co); 1282 } 1283 1284 if (disp_reg == noreg) { 1285 assert(Assembler::is_simm16(disp_value), "should have set this up"); 1286 offset = store(from_reg, src, disp_value, type, wide); 1287 } else { 1288 offset = store(from_reg, src, disp_reg, type, wide); 1289 } 1290 1291 if (use_R29) { 1292 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit 1293 } 1294 1295 if (patch != NULL) { 1296 patching_epilog(patch, patch_code, src, info); 1297 } 1298 1299 if (info != NULL && !needs_explicit_null_check) { 1300 add_debug_info_for_null_check(offset, info); 1301 } 1302 } 1303 1304 1305 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 1306 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone(). 1307 const Register temp = R12; 1308 1309 // Pop the stack before the safepoint code. 1310 int frame_size = initial_frame_size_in_bytes(); 1311 if (Assembler::is_simm(frame_size, 16)) { 1312 __ addi(R1_SP, R1_SP, frame_size); 1313 } else { 1314 __ pop_frame(); 1315 } 1316 1317 // Restore return pc relative to callers' sp. 1318 __ ld(return_pc, _abi0(lr), R1_SP); 1319 // Move return pc to LR. 1320 __ mtlr(return_pc); 1321 1322 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1323 __ reserved_stack_check(return_pc); 1324 } 1325 1326 // We need to mark the code position where the load from the safepoint 1327 // polling page was emitted as relocInfo::poll_return_type here. 1328 if (!UseSIGTRAP) { 1329 code_stub->set_safepoint_offset(__ offset()); 1330 __ relocate(relocInfo::poll_return_type); 1331 } 1332 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */); 1333 1334 // Return. 1335 __ blr(); 1336 } 1337 1338 1339 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1340 const Register poll_addr = tmp->as_register(); 1341 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread); 1342 if (info != NULL) { 1343 add_debug_info_for_branch(info); 1344 } 1345 int offset = __ offset(); 1346 __ relocate(relocInfo::poll_type); 1347 __ load_from_polling_page(poll_addr); 1348 1349 return offset; 1350 } 1351 1352 1353 void LIR_Assembler::emit_static_call_stub() { 1354 address call_pc = __ pc(); 1355 address stub = __ start_a_stub(static_call_stub_size()); 1356 if (stub == NULL) { 1357 bailout("static call stub overflow"); 1358 return; 1359 } 1360 1361 // For java_to_interp stubs we use R11_scratch1 as scratch register 1362 // and in call trampoline stubs we use R12_scratch2. This way we 1363 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1364 const Register reg_scratch = R11_scratch1; 1365 1366 // Create a static stub relocation which relates this stub 1367 // with the call instruction at insts_call_instruction_offset in the 1368 // instructions code-section. 1369 int start = __ offset(); 1370 __ relocate(static_stub_Relocation::spec(call_pc)); 1371 1372 // Now, create the stub's code: 1373 // - load the TOC 1374 // - load the inline cache oop from the constant pool 1375 // - load the call target from the constant pool 1376 // - call 1377 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1378 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL); 1379 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true); 1380 1381 if (ReoptimizeCallSequences) { 1382 __ b64_patchable((address)-1, relocInfo::none); 1383 } else { 1384 AddressLiteral a((address)-1); 1385 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true); 1386 __ mtctr(reg_scratch); 1387 __ bctr(); 1388 } 1389 if (!success) { 1390 bailout("const section overflow"); 1391 return; 1392 } 1393 1394 assert(__ offset() - start <= static_call_stub_size(), "stub too big"); 1395 __ end_a_stub(); 1396 } 1397 1398 1399 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1400 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual); 1401 if (opr1->is_single_fpu()) { 1402 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg()); 1403 } else if (opr1->is_double_fpu()) { 1404 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg()); 1405 } else if (opr1->is_single_cpu()) { 1406 if (opr2->is_constant()) { 1407 switch (opr2->as_constant_ptr()->type()) { 1408 case T_INT: 1409 { 1410 jint con = opr2->as_constant_ptr()->as_jint(); 1411 if (unsigned_comp) { 1412 if (Assembler::is_uimm(con, 16)) { 1413 __ cmplwi(BOOL_RESULT, opr1->as_register(), con); 1414 } else { 1415 __ load_const_optimized(R0, con); 1416 __ cmplw(BOOL_RESULT, opr1->as_register(), R0); 1417 } 1418 } else { 1419 if (Assembler::is_simm(con, 16)) { 1420 __ cmpwi(BOOL_RESULT, opr1->as_register(), con); 1421 } else { 1422 __ load_const_optimized(R0, con); 1423 __ cmpw(BOOL_RESULT, opr1->as_register(), R0); 1424 } 1425 } 1426 } 1427 break; 1428 1429 case T_OBJECT: 1430 // There are only equal/notequal comparisons on objects. 1431 { 1432 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1433 jobject con = opr2->as_constant_ptr()->as_jobject(); 1434 if (con == NULL) { 1435 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0); 1436 } else { 1437 jobject2reg(con, R0); 1438 __ cmpd(BOOL_RESULT, opr1->as_register(), R0); 1439 } 1440 } 1441 break; 1442 1443 case T_METADATA: 1444 // We only need, for now, comparison with NULL for metadata. 1445 { 1446 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1447 Metadata* p = opr2->as_constant_ptr()->as_metadata(); 1448 if (p == NULL) { 1449 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0); 1450 } else { 1451 ShouldNotReachHere(); 1452 } 1453 } 1454 break; 1455 1456 default: 1457 ShouldNotReachHere(); 1458 break; 1459 } 1460 } else { 1461 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported"); 1462 if (is_reference_type(opr1->type())) { 1463 // There are only equal/notequal comparisons on objects. 1464 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1465 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1466 } else { 1467 if (unsigned_comp) { 1468 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1469 } else { 1470 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1471 } 1472 } 1473 } 1474 } else if (opr1->is_double_cpu()) { 1475 if (opr2->is_constant()) { 1476 jlong con = opr2->as_constant_ptr()->as_jlong(); 1477 if (unsigned_comp) { 1478 if (Assembler::is_uimm(con, 16)) { 1479 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con); 1480 } else { 1481 __ load_const_optimized(R0, con); 1482 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0); 1483 } 1484 } else { 1485 if (Assembler::is_simm(con, 16)) { 1486 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con); 1487 } else { 1488 __ load_const_optimized(R0, con); 1489 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0); 1490 } 1491 } 1492 } else if (opr2->is_register()) { 1493 if (unsigned_comp) { 1494 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo()); 1495 } else { 1496 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo()); 1497 } 1498 } else { 1499 ShouldNotReachHere(); 1500 } 1501 } else { 1502 ShouldNotReachHere(); 1503 } 1504 } 1505 1506 1507 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1508 const Register Rdst = dst->as_register(); 1509 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1510 bool is_unordered_less = (code == lir_ucmp_fd2i); 1511 if (left->is_single_fpu()) { 1512 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg()); 1513 } else if (left->is_double_fpu()) { 1514 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg()); 1515 } else { 1516 ShouldNotReachHere(); 1517 } 1518 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1 1519 } else if (code == lir_cmp_l2i) { 1520 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo()); 1521 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1 1522 } else { 1523 ShouldNotReachHere(); 1524 } 1525 } 1526 1527 1528 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) { 1529 if (src->is_constant()) { 1530 lasm->const2reg(src, dst, lir_patch_none, NULL); 1531 } else if (src->is_register()) { 1532 lasm->reg2reg(src, dst); 1533 } else if (src->is_stack()) { 1534 lasm->stack2reg(src, dst, dst->type()); 1535 } else { 1536 ShouldNotReachHere(); 1537 } 1538 } 1539 1540 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 1541 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 1542 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc"); 1543 1544 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) { 1545 load_to_reg(this, opr1, result); // Condition doesn't matter. 1546 return; 1547 } 1548 1549 bool positive = false; 1550 Assembler::Condition cond = Assembler::equal; 1551 switch (condition) { 1552 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break; 1553 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break; 1554 case lir_cond_less: positive = true ; cond = Assembler::less ; break; 1555 case lir_cond_belowEqual: 1556 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break; 1557 case lir_cond_greater: positive = true ; cond = Assembler::greater; break; 1558 case lir_cond_aboveEqual: 1559 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break; 1560 default: ShouldNotReachHere(); 1561 } 1562 1563 // Try to use isel on >=Power7. 1564 if (VM_Version::has_isel() && result->is_cpu_register()) { 1565 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register(); 1566 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo(); 1567 1568 // We can use result_reg to load one operand if not already in register. 1569 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg, 1570 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg; 1571 1572 if (first != second) { 1573 if (!o1_is_reg) { 1574 load_to_reg(this, opr1, result); 1575 } 1576 1577 if (!o2_is_reg) { 1578 load_to_reg(this, opr2, result); 1579 } 1580 1581 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second); 1582 return; 1583 } 1584 } // isel 1585 1586 load_to_reg(this, opr1, result); 1587 1588 Label skip; 1589 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0; 1590 int bi = Assembler::bi0(BOOL_RESULT, cond); 1591 __ bc(bo, bi, skip); 1592 1593 load_to_reg(this, opr2, result); 1594 __ bind(skip); 1595 } 1596 1597 1598 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, 1599 CodeEmitInfo* info, bool pop_fpu_stack) { 1600 assert(info == NULL, "unused on this code path"); 1601 assert(left->is_register(), "wrong items state"); 1602 assert(dest->is_register(), "wrong items state"); 1603 1604 if (right->is_register()) { 1605 if (dest->is_float_kind()) { 1606 1607 FloatRegister lreg, rreg, res; 1608 if (right->is_single_fpu()) { 1609 lreg = left->as_float_reg(); 1610 rreg = right->as_float_reg(); 1611 res = dest->as_float_reg(); 1612 switch (code) { 1613 case lir_add: __ fadds(res, lreg, rreg); break; 1614 case lir_sub: __ fsubs(res, lreg, rreg); break; 1615 case lir_mul: __ fmuls(res, lreg, rreg); break; 1616 case lir_div: __ fdivs(res, lreg, rreg); break; 1617 default: ShouldNotReachHere(); 1618 } 1619 } else { 1620 lreg = left->as_double_reg(); 1621 rreg = right->as_double_reg(); 1622 res = dest->as_double_reg(); 1623 switch (code) { 1624 case lir_add: __ fadd(res, lreg, rreg); break; 1625 case lir_sub: __ fsub(res, lreg, rreg); break; 1626 case lir_mul: __ fmul(res, lreg, rreg); break; 1627 case lir_div: __ fdiv(res, lreg, rreg); break; 1628 default: ShouldNotReachHere(); 1629 } 1630 } 1631 1632 } else if (dest->is_double_cpu()) { 1633 1634 Register dst_lo = dest->as_register_lo(); 1635 Register op1_lo = left->as_pointer_register(); 1636 Register op2_lo = right->as_pointer_register(); 1637 1638 switch (code) { 1639 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break; 1640 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break; 1641 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break; 1642 default: ShouldNotReachHere(); 1643 } 1644 } else { 1645 assert (right->is_single_cpu(), "Just Checking"); 1646 1647 Register lreg = left->as_register(); 1648 Register res = dest->as_register(); 1649 Register rreg = right->as_register(); 1650 switch (code) { 1651 case lir_add: __ add (res, lreg, rreg); break; 1652 case lir_sub: __ sub (res, lreg, rreg); break; 1653 case lir_mul: __ mullw(res, lreg, rreg); break; 1654 default: ShouldNotReachHere(); 1655 } 1656 } 1657 } else { 1658 assert (right->is_constant(), "must be constant"); 1659 1660 if (dest->is_single_cpu()) { 1661 Register lreg = left->as_register(); 1662 Register res = dest->as_register(); 1663 int simm16 = right->as_constant_ptr()->as_jint(); 1664 1665 switch (code) { 1666 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int 1667 simm16 = -simm16; 1668 case lir_add: if (res == lreg && simm16 == 0) break; 1669 __ addi(res, lreg, simm16); break; 1670 case lir_mul: if (res == lreg && simm16 == 1) break; 1671 __ mulli(res, lreg, simm16); break; 1672 default: ShouldNotReachHere(); 1673 } 1674 } else { 1675 Register lreg = left->as_pointer_register(); 1676 Register res = dest->as_register_lo(); 1677 long con = right->as_constant_ptr()->as_jlong(); 1678 assert(Assembler::is_simm16(con), "must be simm16"); 1679 1680 switch (code) { 1681 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long 1682 con = -con; 1683 case lir_add: if (res == lreg && con == 0) break; 1684 __ addi(res, lreg, (int)con); break; 1685 case lir_mul: if (res == lreg && con == 1) break; 1686 __ mulli(res, lreg, (int)con); break; 1687 default: ShouldNotReachHere(); 1688 } 1689 } 1690 } 1691 } 1692 1693 1694 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1695 switch (code) { 1696 case lir_sqrt: { 1697 __ fsqrt(dest->as_double_reg(), value->as_double_reg()); 1698 break; 1699 } 1700 case lir_abs: { 1701 __ fabs(dest->as_double_reg(), value->as_double_reg()); 1702 break; 1703 } 1704 default: { 1705 ShouldNotReachHere(); 1706 break; 1707 } 1708 } 1709 } 1710 1711 1712 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1713 if (right->is_constant()) { // see do_LogicOp 1714 long uimm; 1715 Register d, l; 1716 if (dest->is_single_cpu()) { 1717 uimm = right->as_constant_ptr()->as_jint(); 1718 d = dest->as_register(); 1719 l = left->as_register(); 1720 } else { 1721 uimm = right->as_constant_ptr()->as_jlong(); 1722 d = dest->as_register_lo(); 1723 l = left->as_register_lo(); 1724 } 1725 long uimms = (unsigned long)uimm >> 16, 1726 uimmss = (unsigned long)uimm >> 32; 1727 1728 switch (code) { 1729 case lir_logic_and: 1730 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) { 1731 __ andi(d, l, uimm); // special cases 1732 } else if (uimms != 0) { __ andis_(d, l, uimms); } 1733 else { __ andi_(d, l, uimm); } 1734 break; 1735 1736 case lir_logic_or: 1737 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); } 1738 else { __ ori(d, l, uimm); } 1739 break; 1740 1741 case lir_logic_xor: 1742 if (uimm == -1) { __ nand(d, l, l); } // special case 1743 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); } 1744 else { __ xori(d, l, uimm); } 1745 break; 1746 1747 default: ShouldNotReachHere(); 1748 } 1749 } else { 1750 assert(right->is_register(), "right should be in register"); 1751 1752 if (dest->is_single_cpu()) { 1753 switch (code) { 1754 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break; 1755 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break; 1756 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break; 1757 default: ShouldNotReachHere(); 1758 } 1759 } else { 1760 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 1761 left->as_register_lo(); 1762 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 1763 right->as_register_lo(); 1764 1765 switch (code) { 1766 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break; 1767 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break; 1768 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break; 1769 default: ShouldNotReachHere(); 1770 } 1771 } 1772 } 1773 } 1774 1775 1776 int LIR_Assembler::shift_amount(BasicType t) { 1777 int elem_size = type2aelembytes(t); 1778 switch (elem_size) { 1779 case 1 : return 0; 1780 case 2 : return 1; 1781 case 4 : return 2; 1782 case 8 : return 3; 1783 } 1784 ShouldNotReachHere(); 1785 return -1; 1786 } 1787 1788 1789 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1790 info->add_register_oop(exceptionOop); 1791 1792 // Reuse the debug info from the safepoint poll for the throw op itself. 1793 address pc_for_athrow = __ pc(); 1794 int pc_for_athrow_offset = __ offset(); 1795 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 1796 //__ relocate(rspec); 1797 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0); 1798 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true); 1799 add_call_info(pc_for_athrow_offset, info); // for exception handler 1800 1801 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id 1802 : Runtime1::handle_exception_nofpu_id); 1803 //__ load_const_optimized(R0, stub); 1804 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub)); 1805 __ mtctr(R0); 1806 __ bctr(); 1807 } 1808 1809 1810 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1811 // Note: Not used with EnableDebuggingOnDemand. 1812 assert(exceptionOop->as_register() == R3, "should match"); 1813 __ b(_unwind_handler_entry); 1814 } 1815 1816 1817 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1818 Register src = op->src()->as_register(); 1819 Register dst = op->dst()->as_register(); 1820 Register src_pos = op->src_pos()->as_register(); 1821 Register dst_pos = op->dst_pos()->as_register(); 1822 Register length = op->length()->as_register(); 1823 Register tmp = op->tmp()->as_register(); 1824 Register tmp2 = R0; 1825 1826 int flags = op->flags(); 1827 ciArrayKlass* default_type = op->expected_type(); 1828 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1829 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1830 1831 // Set up the arraycopy stub information. 1832 ArrayCopyStub* stub = op->stub(); 1833 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame. 1834 1835 // Always do stub if no type information is available. It's ok if 1836 // the known type isn't loaded since the code sanity checks 1837 // in debug mode and the type isn't required when we know the exact type 1838 // also check that the type is an array type. 1839 if (op->expected_type() == NULL) { 1840 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() && 1841 length->is_nonvolatile(), "must preserve"); 1842 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1843 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 1844 1845 // 3 parms are int. Convert to long. 1846 __ mr(R3_ARG1, src); 1847 __ extsw(R4_ARG2, src_pos); 1848 __ mr(R5_ARG3, dst); 1849 __ extsw(R6_ARG4, dst_pos); 1850 __ extsw(R7_ARG5, length); 1851 1852 #ifndef PRODUCT 1853 if (PrintC1Statistics) { 1854 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; 1855 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 1856 __ lwz(R11_scratch1, simm16_offs, tmp); 1857 __ addi(R11_scratch1, R11_scratch1, 1); 1858 __ stw(R11_scratch1, simm16_offs, tmp); 1859 } 1860 #endif 1861 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0); 1862 1863 __ nand(tmp, R3_RET, R3_RET); 1864 __ subf(length, tmp, length); 1865 __ add(src_pos, tmp, src_pos); 1866 __ add(dst_pos, tmp, dst_pos); 1867 1868 __ cmpwi(CCR0, R3_RET, 0); 1869 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry()); 1870 __ bind(*stub->continuation()); 1871 return; 1872 } 1873 1874 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 1875 Label cont, slow, copyfunc; 1876 1877 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check | 1878 LIR_OpArrayCopy::dst_null_check | 1879 LIR_OpArrayCopy::src_pos_positive_check | 1880 LIR_OpArrayCopy::dst_pos_positive_check | 1881 LIR_OpArrayCopy::length_positive_check); 1882 1883 // Use only one conditional branch for simple checks. 1884 if (simple_check_flag_set) { 1885 ConditionRegister combined_check = CCR1, tmp_check = CCR1; 1886 1887 // Make sure src and dst are non-null. 1888 if (flags & LIR_OpArrayCopy::src_null_check) { 1889 __ cmpdi(combined_check, src, 0); 1890 tmp_check = CCR0; 1891 } 1892 1893 if (flags & LIR_OpArrayCopy::dst_null_check) { 1894 __ cmpdi(tmp_check, dst, 0); 1895 if (tmp_check != combined_check) { 1896 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal); 1897 } 1898 tmp_check = CCR0; 1899 } 1900 1901 // Clear combined_check.eq if not already used. 1902 if (tmp_check == combined_check) { 1903 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal); 1904 tmp_check = CCR0; 1905 } 1906 1907 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 1908 // Test src_pos register. 1909 __ cmpwi(tmp_check, src_pos, 0); 1910 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1911 } 1912 1913 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 1914 // Test dst_pos register. 1915 __ cmpwi(tmp_check, dst_pos, 0); 1916 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1917 } 1918 1919 if (flags & LIR_OpArrayCopy::length_positive_check) { 1920 // Make sure length isn't negative. 1921 __ cmpwi(tmp_check, length, 0); 1922 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1923 } 1924 1925 __ beq(combined_check, slow); 1926 } 1927 1928 // If the compiler was not able to prove that exact type of the source or the destination 1929 // of the arraycopy is an array type, check at runtime if the source or the destination is 1930 // an instance type. 1931 if (flags & LIR_OpArrayCopy::type_check) { 1932 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 1933 __ load_klass(tmp, dst); 1934 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 1935 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value); 1936 __ bge(CCR0, slow); 1937 } 1938 1939 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 1940 __ load_klass(tmp, src); 1941 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 1942 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value); 1943 __ bge(CCR0, slow); 1944 } 1945 } 1946 1947 // Higher 32bits must be null. 1948 __ extsw(length, length); 1949 1950 __ extsw(src_pos, src_pos); 1951 if (flags & LIR_OpArrayCopy::src_range_check) { 1952 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src); 1953 __ add(tmp, length, src_pos); 1954 __ cmpld(CCR0, tmp2, tmp); 1955 __ ble(CCR0, slow); 1956 } 1957 1958 __ extsw(dst_pos, dst_pos); 1959 if (flags & LIR_OpArrayCopy::dst_range_check) { 1960 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst); 1961 __ add(tmp, length, dst_pos); 1962 __ cmpld(CCR0, tmp2, tmp); 1963 __ ble(CCR0, slow); 1964 } 1965 1966 int shift = shift_amount(basic_type); 1967 1968 if (!(flags & LIR_OpArrayCopy::type_check)) { 1969 __ b(cont); 1970 } else { 1971 // We don't know the array types are compatible. 1972 if (basic_type != T_OBJECT) { 1973 // Simple test for basic type arrays. 1974 if (UseCompressedClassPointers) { 1975 // We don't need decode because we just need to compare. 1976 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src); 1977 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst); 1978 __ cmpw(CCR0, tmp, tmp2); 1979 } else { 1980 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src); 1981 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst); 1982 __ cmpd(CCR0, tmp, tmp2); 1983 } 1984 __ beq(CCR0, cont); 1985 } else { 1986 // For object arrays, if src is a sub class of dst then we can 1987 // safely do the copy. 1988 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 1989 1990 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf 1991 assert_different_registers(tmp, tmp2, sub_klass, super_klass); 1992 1993 __ load_klass(sub_klass, src); 1994 __ load_klass(super_klass, dst); 1995 1996 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2, 1997 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL); 1998 1999 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2000 //__ load_const_optimized(tmp, slow_stc, tmp2); 2001 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false); 2002 __ mtctr(tmp); 2003 __ bctrl(); // sets CR0 2004 __ beq(CCR0, cont); 2005 2006 if (copyfunc_addr != NULL) { // Use stub if available. 2007 __ bind(copyfunc); 2008 // Src is not a sub class of dst so we have to do a 2009 // per-element check. 2010 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2011 if ((flags & mask) != mask) { 2012 assert(flags & mask, "one of the two should be known to be an object array"); 2013 2014 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2015 __ load_klass(tmp, src); 2016 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2017 __ load_klass(tmp, dst); 2018 } 2019 2020 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 2021 2022 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2023 __ load_const_optimized(tmp, objArray_lh); 2024 __ cmpw(CCR0, tmp, tmp2); 2025 __ bne(CCR0, slow); 2026 } 2027 2028 Register src_ptr = R3_ARG1; 2029 Register dst_ptr = R4_ARG2; 2030 Register len = R5_ARG3; 2031 Register chk_off = R6_ARG4; 2032 Register super_k = R7_ARG5; 2033 2034 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type)); 2035 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type)); 2036 if (shift == 0) { 2037 __ add(src_ptr, src_pos, src_ptr); 2038 __ add(dst_ptr, dst_pos, dst_ptr); 2039 } else { 2040 __ sldi(tmp, src_pos, shift); 2041 __ sldi(tmp2, dst_pos, shift); 2042 __ add(src_ptr, tmp, src_ptr); 2043 __ add(dst_ptr, tmp2, dst_ptr); 2044 } 2045 2046 __ load_klass(tmp, dst); 2047 __ mr(len, length); 2048 2049 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); 2050 __ ld(super_k, ek_offset, tmp); 2051 2052 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2053 __ lwz(chk_off, sco_offset, super_k); 2054 2055 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0); 2056 2057 #ifndef PRODUCT 2058 if (PrintC1Statistics) { 2059 Label failed; 2060 __ cmpwi(CCR0, R3_RET, 0); 2061 __ bne(CCR0, failed); 2062 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt; 2063 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2064 __ lwz(R11_scratch1, simm16_offs, tmp); 2065 __ addi(R11_scratch1, R11_scratch1, 1); 2066 __ stw(R11_scratch1, simm16_offs, tmp); 2067 __ bind(failed); 2068 } 2069 #endif 2070 2071 __ nand(tmp, R3_RET, R3_RET); 2072 __ cmpwi(CCR0, R3_RET, 0); 2073 __ beq(CCR0, *stub->continuation()); 2074 2075 #ifndef PRODUCT 2076 if (PrintC1Statistics) { 2077 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt; 2078 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2079 __ lwz(R11_scratch1, simm16_offs, tmp); 2080 __ addi(R11_scratch1, R11_scratch1, 1); 2081 __ stw(R11_scratch1, simm16_offs, tmp); 2082 } 2083 #endif 2084 2085 __ subf(length, tmp, length); 2086 __ add(src_pos, tmp, src_pos); 2087 __ add(dst_pos, tmp, dst_pos); 2088 } 2089 } 2090 } 2091 __ bind(slow); 2092 __ b(*stub->entry()); 2093 __ bind(cont); 2094 2095 #ifdef ASSERT 2096 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2097 // Sanity check the known type with the incoming class. For the 2098 // primitive case the types must match exactly with src.klass and 2099 // dst.klass each exactly matching the default type. For the 2100 // object array case, if no type check is needed then either the 2101 // dst type is exactly the expected type and the src type is a 2102 // subtype which we can't check or src is the same array as dst 2103 // but not necessarily exactly of type default_type. 2104 Label known_ok, halt; 2105 metadata2reg(op->expected_type()->constant_encoding(), tmp); 2106 if (UseCompressedClassPointers) { 2107 // Tmp holds the default type. It currently comes uncompressed after the 2108 // load of a constant, so encode it. 2109 __ encode_klass_not_null(tmp); 2110 // Load the raw value of the dst klass, since we will be comparing 2111 // uncompressed values directly. 2112 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2113 __ cmpw(CCR0, tmp, tmp2); 2114 if (basic_type != T_OBJECT) { 2115 __ bne(CCR0, halt); 2116 // Load the raw value of the src klass. 2117 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src); 2118 __ cmpw(CCR0, tmp, tmp2); 2119 __ beq(CCR0, known_ok); 2120 } else { 2121 __ beq(CCR0, known_ok); 2122 __ cmpw(CCR0, src, dst); 2123 __ beq(CCR0, known_ok); 2124 } 2125 } else { 2126 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2127 __ cmpd(CCR0, tmp, tmp2); 2128 if (basic_type != T_OBJECT) { 2129 __ bne(CCR0, halt); 2130 // Load the raw value of the src klass. 2131 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src); 2132 __ cmpd(CCR0, tmp, tmp2); 2133 __ beq(CCR0, known_ok); 2134 } else { 2135 __ beq(CCR0, known_ok); 2136 __ cmpd(CCR0, src, dst); 2137 __ beq(CCR0, known_ok); 2138 } 2139 } 2140 __ bind(halt); 2141 __ stop("incorrect type information in arraycopy"); 2142 __ bind(known_ok); 2143 } 2144 #endif 2145 2146 #ifndef PRODUCT 2147 if (PrintC1Statistics) { 2148 address counter = Runtime1::arraycopy_count_address(basic_type); 2149 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2150 __ lwz(R11_scratch1, simm16_offs, tmp); 2151 __ addi(R11_scratch1, R11_scratch1, 1); 2152 __ stw(R11_scratch1, simm16_offs, tmp); 2153 } 2154 #endif 2155 2156 Register src_ptr = R3_ARG1; 2157 Register dst_ptr = R4_ARG2; 2158 Register len = R5_ARG3; 2159 2160 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type)); 2161 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type)); 2162 if (shift == 0) { 2163 __ add(src_ptr, src_pos, src_ptr); 2164 __ add(dst_ptr, dst_pos, dst_ptr); 2165 } else { 2166 __ sldi(tmp, src_pos, shift); 2167 __ sldi(tmp2, dst_pos, shift); 2168 __ add(src_ptr, tmp, src_ptr); 2169 __ add(dst_ptr, tmp2, dst_ptr); 2170 } 2171 2172 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2173 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2174 const char *name; 2175 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2176 2177 // Arraycopy stubs takes a length in number of elements, so don't scale it. 2178 __ mr(len, length); 2179 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0); 2180 2181 __ bind(*stub->continuation()); 2182 } 2183 2184 2185 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2186 if (dest->is_single_cpu()) { 2187 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5); 2188 #ifdef _LP64 2189 if (left->type() == T_OBJECT) { 2190 switch (code) { 2191 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break; 2192 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break; 2193 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break; 2194 default: ShouldNotReachHere(); 2195 } 2196 } else 2197 #endif 2198 switch (code) { 2199 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2200 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2201 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2202 default: ShouldNotReachHere(); 2203 } 2204 } else { 2205 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6); 2206 switch (code) { 2207 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2208 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2209 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2210 default: ShouldNotReachHere(); 2211 } 2212 } 2213 } 2214 2215 2216 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2217 #ifdef _LP64 2218 if (left->type() == T_OBJECT) { 2219 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t). 2220 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); } 2221 else { 2222 switch (code) { 2223 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break; 2224 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break; 2225 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break; 2226 default: ShouldNotReachHere(); 2227 } 2228 } 2229 return; 2230 } 2231 #endif 2232 2233 if (dest->is_single_cpu()) { 2234 count = count & 0x1F; // Java spec 2235 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); } 2236 else { 2237 switch (code) { 2238 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break; 2239 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break; 2240 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break; 2241 default: ShouldNotReachHere(); 2242 } 2243 } 2244 } else if (dest->is_double_cpu()) { 2245 count = count & 63; // Java spec 2246 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); } 2247 else { 2248 switch (code) { 2249 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2250 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2251 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2252 default: ShouldNotReachHere(); 2253 } 2254 } 2255 } else { 2256 ShouldNotReachHere(); 2257 } 2258 } 2259 2260 2261 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2262 if (op->init_check()) { 2263 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2264 explicit_null_check(op->klass()->as_register(), op->stub()->info()); 2265 } else { 2266 add_debug_info_for_null_check_here(op->stub()->info()); 2267 } 2268 __ lbz(op->tmp1()->as_register(), 2269 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register()); 2270 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized); 2271 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry()); 2272 } 2273 __ allocate_object(op->obj()->as_register(), 2274 op->tmp1()->as_register(), 2275 op->tmp2()->as_register(), 2276 op->tmp3()->as_register(), 2277 op->header_size(), 2278 op->object_size(), 2279 op->klass()->as_register(), 2280 *op->stub()->entry()); 2281 2282 __ bind(*op->stub()->continuation()); 2283 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE); 2284 } 2285 2286 2287 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2288 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); ) 2289 if (UseSlowPath || 2290 (!UseFastNewObjectArray && (is_reference_type(op->type()))) || 2291 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) { 2292 __ b(*op->stub()->entry()); 2293 } else { 2294 __ allocate_array(op->obj()->as_register(), 2295 op->len()->as_register(), 2296 op->tmp1()->as_register(), 2297 op->tmp2()->as_register(), 2298 op->tmp3()->as_register(), 2299 arrayOopDesc::header_size(op->type()), 2300 type2aelembytes(op->type()), 2301 op->klass()->as_register(), 2302 *op->stub()->entry()); 2303 } 2304 __ bind(*op->stub()->continuation()); 2305 } 2306 2307 2308 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2309 ciMethodData *md, ciProfileData *data, 2310 Register recv, Register tmp1, Label* update_done) { 2311 uint i; 2312 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2313 Label next_test; 2314 // See if the receiver is receiver[n]. 2315 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2316 __ verify_klass_ptr(tmp1); 2317 __ cmpd(CCR0, recv, tmp1); 2318 __ bne(CCR0, next_test); 2319 2320 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2321 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2322 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2323 __ b(*update_done); 2324 2325 __ bind(next_test); 2326 } 2327 2328 // Didn't find receiver; find next empty slot and fill it in. 2329 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2330 Label next_test; 2331 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2332 __ cmpdi(CCR0, tmp1, 0); 2333 __ bne(CCR0, next_test); 2334 __ li(tmp1, DataLayout::counter_increment); 2335 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2336 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2337 __ b(*update_done); 2338 2339 __ bind(next_test); 2340 } 2341 } 2342 2343 2344 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2345 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2346 md = method->method_data_or_null(); 2347 assert(md != NULL, "Sanity"); 2348 data = md->bci_to_data(bci); 2349 assert(data != NULL, "need data for checkcast"); 2350 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2351 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2352 // The offset is large so bias the mdo by the base of the slot so 2353 // that the ld can use simm16s to reference the slots of the data. 2354 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2355 } 2356 } 2357 2358 2359 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2360 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub). 2361 Register k_RInfo = op->tmp1()->as_register(); 2362 Register klass_RInfo = op->tmp2()->as_register(); 2363 Register Rtmp1 = op->tmp3()->as_register(); 2364 Register dst = op->result_opr()->as_register(); 2365 ciKlass* k = op->klass(); 2366 bool should_profile = op->should_profile(); 2367 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps. 2368 bool reg_conflict = false; 2369 if (obj == k_RInfo) { 2370 k_RInfo = dst; 2371 reg_conflict = true; 2372 } else if (obj == klass_RInfo) { 2373 klass_RInfo = dst; 2374 reg_conflict = true; 2375 } else if (obj == Rtmp1) { 2376 Rtmp1 = dst; 2377 reg_conflict = true; 2378 } 2379 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1); 2380 2381 __ cmpdi(CCR0, obj, 0); 2382 2383 ciMethodData* md = NULL; 2384 ciProfileData* data = NULL; 2385 int mdo_offset_bias = 0; 2386 if (should_profile) { 2387 ciMethod* method = op->profiled_method(); 2388 assert(method != NULL, "Should have method"); 2389 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2390 2391 Register mdo = k_RInfo; 2392 Register data_val = Rtmp1; 2393 Label not_null; 2394 __ bne(CCR0, not_null); 2395 metadata2reg(md->constant_encoding(), mdo); 2396 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2397 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2398 __ ori(data_val, data_val, BitData::null_seen_byte_constant()); 2399 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2400 __ b(*obj_is_null); 2401 __ bind(not_null); 2402 } else { 2403 __ beq(CCR0, *obj_is_null); 2404 } 2405 2406 // get object class 2407 __ load_klass(klass_RInfo, obj); 2408 2409 if (k->is_loaded()) { 2410 metadata2reg(k->constant_encoding(), k_RInfo); 2411 } else { 2412 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2413 } 2414 2415 Label profile_cast_failure, failure_restore_obj, profile_cast_success; 2416 Label *failure_target = should_profile ? &profile_cast_failure : failure; 2417 Label *success_target = should_profile ? &profile_cast_success : success; 2418 2419 if (op->fast_check()) { 2420 assert_different_registers(klass_RInfo, k_RInfo); 2421 __ cmpd(CCR0, k_RInfo, klass_RInfo); 2422 if (should_profile) { 2423 __ bne(CCR0, *failure_target); 2424 // Fall through to success case. 2425 } else { 2426 __ beq(CCR0, *success); 2427 // Fall through to failure case. 2428 } 2429 } else { 2430 bool need_slow_path = true; 2431 if (k->is_loaded()) { 2432 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) { 2433 need_slow_path = false; 2434 } 2435 // Perform the fast part of the checking logic. 2436 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL), 2437 failure_target, NULL, RegisterOrConstant(k->super_check_offset())); 2438 } else { 2439 // Perform the fast part of the checking logic. 2440 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target); 2441 } 2442 if (!need_slow_path) { 2443 if (!should_profile) { __ b(*success); } 2444 } else { 2445 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2446 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2447 // Stub needs fixed registers (tmp1-3). 2448 Register original_k_RInfo = op->tmp1()->as_register(); 2449 Register original_klass_RInfo = op->tmp2()->as_register(); 2450 Register original_Rtmp1 = op->tmp3()->as_register(); 2451 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast); 2452 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile; 2453 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); } 2454 __ mr_if_needed(original_k_RInfo, k_RInfo); 2455 __ mr_if_needed(original_klass_RInfo, klass_RInfo); 2456 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); } 2457 //__ load_const_optimized(original_Rtmp1, entry, R0); 2458 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false); 2459 __ mtctr(original_Rtmp1); 2460 __ bctrl(); // sets CR0 2461 if (keep_obj_alive) { 2462 if (keep_klass_RInfo_alive) { __ mr(R0, obj); } 2463 __ mr(obj, dst); 2464 } 2465 if (should_profile) { 2466 __ bne(CCR0, *failure_target); 2467 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); } 2468 // Fall through to success case. 2469 } else { 2470 __ beq(CCR0, *success); 2471 // Fall through to failure case. 2472 } 2473 } 2474 } 2475 2476 if (should_profile) { 2477 Register mdo = k_RInfo, recv = klass_RInfo; 2478 assert_different_registers(mdo, recv, Rtmp1); 2479 __ bind(profile_cast_success); 2480 metadata2reg(md->constant_encoding(), mdo); 2481 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2482 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success); 2483 __ b(*success); 2484 2485 // Cast failure case. 2486 __ bind(profile_cast_failure); 2487 metadata2reg(md->constant_encoding(), mdo); 2488 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2489 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2490 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment); 2491 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2492 } 2493 2494 __ bind(*failure); 2495 } 2496 2497 2498 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2499 LIR_Code code = op->code(); 2500 if (code == lir_store_check) { 2501 Register value = op->object()->as_register(); 2502 Register array = op->array()->as_register(); 2503 Register k_RInfo = op->tmp1()->as_register(); 2504 Register klass_RInfo = op->tmp2()->as_register(); 2505 Register Rtmp1 = op->tmp3()->as_register(); 2506 bool should_profile = op->should_profile(); 2507 2508 __ verify_oop(value, FILE_AND_LINE); 2509 CodeStub* stub = op->stub(); 2510 // Check if it needs to be profiled. 2511 ciMethodData* md = NULL; 2512 ciProfileData* data = NULL; 2513 int mdo_offset_bias = 0; 2514 if (should_profile) { 2515 ciMethod* method = op->profiled_method(); 2516 assert(method != NULL, "Should have method"); 2517 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2518 } 2519 Label profile_cast_success, failure, done; 2520 Label *success_target = should_profile ? &profile_cast_success : &done; 2521 2522 __ cmpdi(CCR0, value, 0); 2523 if (should_profile) { 2524 Label not_null; 2525 __ bne(CCR0, not_null); 2526 Register mdo = k_RInfo; 2527 Register data_val = Rtmp1; 2528 metadata2reg(md->constant_encoding(), mdo); 2529 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2530 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2531 __ ori(data_val, data_val, BitData::null_seen_byte_constant()); 2532 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2533 __ b(done); 2534 __ bind(not_null); 2535 } else { 2536 __ beq(CCR0, done); 2537 } 2538 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2539 explicit_null_check(array, op->info_for_exception()); 2540 } else { 2541 add_debug_info_for_null_check_here(op->info_for_exception()); 2542 } 2543 __ load_klass(k_RInfo, array); 2544 __ load_klass(klass_RInfo, value); 2545 2546 // Get instance klass. 2547 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo); 2548 // Perform the fast part of the checking logic. 2549 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL); 2550 2551 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2552 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2553 //__ load_const_optimized(R0, slow_path); 2554 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path)); 2555 __ mtctr(R0); 2556 __ bctrl(); // sets CR0 2557 if (!should_profile) { 2558 __ beq(CCR0, done); 2559 __ bind(failure); 2560 } else { 2561 __ bne(CCR0, failure); 2562 // Fall through to the success case. 2563 2564 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2565 assert_different_registers(value, mdo, recv, tmp1); 2566 __ bind(profile_cast_success); 2567 metadata2reg(md->constant_encoding(), mdo); 2568 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2569 __ load_klass(recv, value); 2570 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2571 __ b(done); 2572 2573 // Cast failure case. 2574 __ bind(failure); 2575 metadata2reg(md->constant_encoding(), mdo); 2576 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2577 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2578 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2579 __ addi(tmp1, tmp1, -DataLayout::counter_increment); 2580 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2581 } 2582 __ b(*stub->entry()); 2583 __ bind(done); 2584 2585 } else if (code == lir_checkcast) { 2586 Label success, failure; 2587 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success); 2588 __ b(*op->stub()->entry()); 2589 __ align(32, 12); 2590 __ bind(success); 2591 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register()); 2592 } else if (code == lir_instanceof) { 2593 Register dst = op->result_opr()->as_register(); 2594 Label success, failure, done; 2595 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure); 2596 __ li(dst, 0); 2597 __ b(done); 2598 __ align(32, 12); 2599 __ bind(success); 2600 __ li(dst, 1); 2601 __ bind(done); 2602 } else { 2603 ShouldNotReachHere(); 2604 } 2605 } 2606 2607 2608 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2609 Register addr = op->addr()->as_pointer_register(); 2610 Register cmp_value = noreg, new_value = noreg; 2611 bool is_64bit = false; 2612 2613 if (op->code() == lir_cas_long) { 2614 cmp_value = op->cmp_value()->as_register_lo(); 2615 new_value = op->new_value()->as_register_lo(); 2616 is_64bit = true; 2617 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2618 cmp_value = op->cmp_value()->as_register(); 2619 new_value = op->new_value()->as_register(); 2620 if (op->code() == lir_cas_obj) { 2621 if (UseCompressedOops) { 2622 Register t1 = op->tmp1()->as_register(); 2623 Register t2 = op->tmp2()->as_register(); 2624 cmp_value = __ encode_heap_oop(t1, cmp_value); 2625 new_value = __ encode_heap_oop(t2, new_value); 2626 } else { 2627 is_64bit = true; 2628 } 2629 } 2630 } else { 2631 Unimplemented(); 2632 } 2633 2634 if (is_64bit) { 2635 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2636 MacroAssembler::MemBarNone, 2637 MacroAssembler::cmpxchgx_hint_atomic_update(), 2638 noreg, NULL, /*check without ldarx first*/true); 2639 } else { 2640 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2641 MacroAssembler::MemBarNone, 2642 MacroAssembler::cmpxchgx_hint_atomic_update(), 2643 noreg, /*check without ldarx first*/true); 2644 } 2645 2646 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { 2647 __ isync(); 2648 } else { 2649 __ sync(); 2650 } 2651 } 2652 2653 void LIR_Assembler::breakpoint() { 2654 __ illtrap(); 2655 } 2656 2657 2658 void LIR_Assembler::push(LIR_Opr opr) { 2659 Unimplemented(); 2660 } 2661 2662 void LIR_Assembler::pop(LIR_Opr opr) { 2663 Unimplemented(); 2664 } 2665 2666 2667 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2668 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2669 Register dst = dst_opr->as_register(); 2670 Register reg = mon_addr.base(); 2671 int offset = mon_addr.disp(); 2672 // Compute pointer to BasicLock. 2673 __ add_const_optimized(dst, reg, offset); 2674 } 2675 2676 2677 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2678 Register obj = op->obj_opr()->as_register(); 2679 Register hdr = op->hdr_opr()->as_register(); 2680 Register lock = op->lock_opr()->as_register(); 2681 2682 // Obj may not be an oop. 2683 if (op->code() == lir_lock) { 2684 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2685 if (!UseHeavyMonitors) { 2686 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2687 // Add debug info for NullPointerException only if one is possible. 2688 if (op->info() != NULL) { 2689 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2690 explicit_null_check(obj, op->info()); 2691 } else { 2692 add_debug_info_for_null_check_here(op->info()); 2693 } 2694 } 2695 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2696 } else { 2697 // always do slow locking 2698 // note: The slow locking code could be inlined here, however if we use 2699 // slow locking, speed doesn't matter anyway and this solution is 2700 // simpler and requires less duplicated code - additionally, the 2701 // slow locking code is the same in either case which simplifies 2702 // debugging. 2703 if (op->info() != NULL) { 2704 add_debug_info_for_null_check_here(op->info()); 2705 __ null_check(obj); 2706 } 2707 __ b(*op->stub()->entry()); 2708 } 2709 } else { 2710 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2711 if (!UseHeavyMonitors) { 2712 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2713 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2714 } else { 2715 // always do slow unlocking 2716 // note: The slow unlocking code could be inlined here, however if we use 2717 // slow unlocking, speed doesn't matter anyway and this solution is 2718 // simpler and requires less duplicated code - additionally, the 2719 // slow unlocking code is the same in either case which simplifies 2720 // debugging. 2721 __ b(*op->stub()->entry()); 2722 } 2723 } 2724 __ bind(*op->stub()->continuation()); 2725 } 2726 2727 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 2728 Register obj = op->obj()->as_pointer_register(); 2729 Register result = op->result_opr()->as_pointer_register(); 2730 2731 CodeEmitInfo* info = op->info(); 2732 if (info != NULL) { 2733 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2734 explicit_null_check(obj, info); 2735 } else { 2736 add_debug_info_for_null_check_here(info); 2737 } 2738 } 2739 2740 if (UseCompressedClassPointers) { 2741 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj); 2742 __ decode_klass_not_null(result); 2743 } else { 2744 __ ld(result, oopDesc::klass_offset_in_bytes(), obj); 2745 } 2746 } 2747 2748 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2749 ciMethod* method = op->profiled_method(); 2750 int bci = op->profiled_bci(); 2751 ciMethod* callee = op->profiled_callee(); 2752 2753 // Update counter for all call types. 2754 ciMethodData* md = method->method_data_or_null(); 2755 assert(md != NULL, "Sanity"); 2756 ciProfileData* data = md->bci_to_data(bci); 2757 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2758 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2759 Register mdo = op->mdo()->as_register(); 2760 #ifdef _LP64 2761 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2762 Register tmp1 = op->tmp1()->as_register_lo(); 2763 #else 2764 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); 2765 Register tmp1 = op->tmp1()->as_register(); 2766 #endif 2767 metadata2reg(md->constant_encoding(), mdo); 2768 int mdo_offset_bias = 0; 2769 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2770 data->size_in_bytes())) { 2771 // The offset is large so bias the mdo by the base of the slot so 2772 // that the ld can use simm16s to reference the slots of the data. 2773 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2774 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2775 } 2776 2777 // Perform additional virtual call profiling for invokevirtual and 2778 // invokeinterface bytecodes 2779 if (op->should_profile_receiver_type()) { 2780 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2781 Register recv = op->recv()->as_register(); 2782 assert_different_registers(mdo, tmp1, recv); 2783 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2784 ciKlass* known_klass = op->known_holder(); 2785 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2786 // We know the type that will be seen at this call site; we can 2787 // statically update the MethodData* rather than needing to do 2788 // dynamic tests on the receiver type. 2789 2790 // NOTE: we should probably put a lock around this search to 2791 // avoid collisions by concurrent compilations. 2792 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2793 uint i; 2794 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2795 ciKlass* receiver = vc_data->receiver(i); 2796 if (known_klass->equals(receiver)) { 2797 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2798 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2799 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2800 return; 2801 } 2802 } 2803 2804 // Receiver type not found in profile data; select an empty slot. 2805 2806 // Note that this is less efficient than it should be because it 2807 // always does a write to the receiver part of the 2808 // VirtualCallData rather than just the first time. 2809 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2810 ciKlass* receiver = vc_data->receiver(i); 2811 if (receiver == NULL) { 2812 metadata2reg(known_klass->constant_encoding(), tmp1); 2813 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo); 2814 2815 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2816 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2817 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2818 return; 2819 } 2820 } 2821 } else { 2822 __ load_klass(recv, recv); 2823 Label update_done; 2824 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 2825 // Receiver did not match any saved receiver and there is no empty row for it. 2826 // Increment total counter to indicate polymorphic case. 2827 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2828 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2829 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2830 2831 __ bind(update_done); 2832 } 2833 } else { 2834 // Static call 2835 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2836 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2837 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2838 } 2839 } 2840 2841 2842 void LIR_Assembler::align_backward_branch_target() { 2843 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary. 2844 } 2845 2846 2847 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2848 Unimplemented(); 2849 } 2850 2851 2852 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 2853 // tmp must be unused 2854 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2855 assert(left->is_register(), "can only handle registers"); 2856 2857 if (left->is_single_cpu()) { 2858 __ neg(dest->as_register(), left->as_register()); 2859 } else if (left->is_single_fpu()) { 2860 __ fneg(dest->as_float_reg(), left->as_float_reg()); 2861 } else if (left->is_double_fpu()) { 2862 __ fneg(dest->as_double_reg(), left->as_double_reg()); 2863 } else { 2864 assert (left->is_double_cpu(), "Must be a long"); 2865 __ neg(dest->as_register_lo(), left->as_register_lo()); 2866 } 2867 } 2868 2869 2870 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 2871 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2872 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor). 2873 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) || 2874 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) { 2875 //__ load_const_optimized(R0, dest); 2876 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest)); 2877 __ mtctr(R0); 2878 __ bctrl(); 2879 assert(info != NULL, "sanity"); 2880 add_call_info_here(info); 2881 __ post_call_nop(); 2882 return; 2883 } 2884 2885 __ call_c_with_frame_resize(dest, /*no resizing*/ 0); 2886 if (info != NULL) { 2887 add_call_info_here(info); 2888 } 2889 __ post_call_nop(); 2890 } 2891 2892 2893 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2894 ShouldNotReachHere(); // Not needed on _LP64. 2895 } 2896 2897 void LIR_Assembler::membar() { 2898 __ fence(); 2899 } 2900 2901 void LIR_Assembler::membar_acquire() { 2902 __ acquire(); 2903 } 2904 2905 void LIR_Assembler::membar_release() { 2906 __ release(); 2907 } 2908 2909 void LIR_Assembler::membar_loadload() { 2910 __ membar(Assembler::LoadLoad); 2911 } 2912 2913 void LIR_Assembler::membar_storestore() { 2914 __ membar(Assembler::StoreStore); 2915 } 2916 2917 void LIR_Assembler::membar_loadstore() { 2918 __ membar(Assembler::LoadStore); 2919 } 2920 2921 void LIR_Assembler::membar_storeload() { 2922 __ membar(Assembler::StoreLoad); 2923 } 2924 2925 void LIR_Assembler::on_spin_wait() { 2926 Unimplemented(); 2927 } 2928 2929 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 2930 LIR_Address* addr = addr_opr->as_address_ptr(); 2931 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform"); 2932 2933 if (addr->index()->is_illegal()) { 2934 if (patch_code != lir_patch_none) { 2935 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id); 2936 __ load_const32(R0, 0); // patchable int 2937 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0); 2938 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 2939 } else { 2940 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp()); 2941 } 2942 } else { 2943 assert(patch_code == lir_patch_none, "Patch code not supported"); 2944 assert(addr->disp() == 0, "can't have both: index and disp"); 2945 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register()); 2946 } 2947 } 2948 2949 2950 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2951 ShouldNotReachHere(); 2952 } 2953 2954 2955 #ifdef ASSERT 2956 // Emit run-time assertion. 2957 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2958 Unimplemented(); 2959 } 2960 #endif 2961 2962 2963 void LIR_Assembler::peephole(LIR_List* lir) { 2964 // Optimize instruction pairs before emitting. 2965 LIR_OpList* inst = lir->instructions_list(); 2966 for (int i = 1; i < inst->length(); i++) { 2967 LIR_Op* op = inst->at(i); 2968 2969 // 2 register-register-moves 2970 if (op->code() == lir_move) { 2971 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(), 2972 res2 = ((LIR_Op1*)op)->result_opr(); 2973 if (in2->is_register() && res2->is_register()) { 2974 LIR_Op* prev = inst->at(i - 1); 2975 if (prev && prev->code() == lir_move) { 2976 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(), 2977 res1 = ((LIR_Op1*)prev)->result_opr(); 2978 if (in1->is_same_register(res2) && in2->is_same_register(res1)) { 2979 inst->remove_at(i); 2980 } 2981 } 2982 } 2983 } 2984 2985 } 2986 return; 2987 } 2988 2989 2990 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 2991 const LIR_Address *addr = src->as_address_ptr(); 2992 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!"); 2993 const Register Rptr = addr->base()->as_pointer_register(), 2994 Rtmp = tmp->as_register(); 2995 Register Rco = noreg; 2996 if (UseCompressedOops && data->is_oop()) { 2997 Rco = __ encode_heap_oop(Rtmp, data->as_register()); 2998 } 2999 3000 Label Lretry; 3001 __ bind(Lretry); 3002 3003 if (data->type() == T_INT) { 3004 const Register Rold = dest->as_register(), 3005 Rsrc = data->as_register(); 3006 assert_different_registers(Rptr, Rtmp, Rold, Rsrc); 3007 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3008 if (code == lir_xadd) { 3009 __ add(Rtmp, Rsrc, Rold); 3010 __ stwcx_(Rtmp, Rptr); 3011 } else { 3012 __ stwcx_(Rsrc, Rptr); 3013 } 3014 } else if (data->is_oop()) { 3015 assert(code == lir_xchg, "xadd for oops"); 3016 const Register Rold = dest->as_register(); 3017 if (UseCompressedOops) { 3018 assert_different_registers(Rptr, Rold, Rco); 3019 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3020 __ stwcx_(Rco, Rptr); 3021 } else { 3022 const Register Robj = data->as_register(); 3023 assert_different_registers(Rptr, Rold, Robj); 3024 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3025 __ stdcx_(Robj, Rptr); 3026 } 3027 } else if (data->type() == T_LONG) { 3028 const Register Rold = dest->as_register_lo(), 3029 Rsrc = data->as_register_lo(); 3030 assert_different_registers(Rptr, Rtmp, Rold, Rsrc); 3031 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3032 if (code == lir_xadd) { 3033 __ add(Rtmp, Rsrc, Rold); 3034 __ stdcx_(Rtmp, Rptr); 3035 } else { 3036 __ stdcx_(Rsrc, Rptr); 3037 } 3038 } else { 3039 ShouldNotReachHere(); 3040 } 3041 3042 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3043 __ bne_predict_not_taken(CCR0, Lretry); 3044 } else { 3045 __ bne( CCR0, Lretry); 3046 } 3047 3048 if (UseCompressedOops && data->is_oop()) { 3049 __ decode_heap_oop(dest->as_register()); 3050 } 3051 } 3052 3053 3054 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3055 Register obj = op->obj()->as_register(); 3056 Register tmp = op->tmp()->as_pointer_register(); 3057 LIR_Address* mdo_addr = op->mdp()->as_address_ptr(); 3058 ciKlass* exact_klass = op->exact_klass(); 3059 intptr_t current_klass = op->current_klass(); 3060 bool not_null = op->not_null(); 3061 bool no_conflict = op->no_conflict(); 3062 3063 Label Lupdate, Ldo_update, Ldone; 3064 3065 bool do_null = !not_null; 3066 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3067 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3068 3069 assert(do_null || do_update, "why are we here?"); 3070 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3071 3072 __ verify_oop(obj, FILE_AND_LINE); 3073 3074 if (do_null) { 3075 if (!TypeEntries::was_null_seen(current_klass)) { 3076 __ cmpdi(CCR0, obj, 0); 3077 __ bne(CCR0, Lupdate); 3078 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3079 __ ori(R0, R0, TypeEntries::null_seen); 3080 if (do_update) { 3081 __ b(Ldo_update); 3082 } else { 3083 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3084 } 3085 } else { 3086 if (do_update) { 3087 __ cmpdi(CCR0, obj, 0); 3088 __ beq(CCR0, Ldone); 3089 } 3090 } 3091 #ifdef ASSERT 3092 } else { 3093 __ cmpdi(CCR0, obj, 0); 3094 __ bne(CCR0, Lupdate); 3095 __ stop("unexpected null obj"); 3096 #endif 3097 } 3098 3099 __ bind(Lupdate); 3100 if (do_update) { 3101 Label Lnext; 3102 const Register klass = R29_TOC; // kill and reload 3103 bool klass_reg_used = false; 3104 #ifdef ASSERT 3105 if (exact_klass != NULL) { 3106 Label ok; 3107 klass_reg_used = true; 3108 __ load_klass(klass, obj); 3109 metadata2reg(exact_klass->constant_encoding(), R0); 3110 __ cmpd(CCR0, klass, R0); 3111 __ beq(CCR0, ok); 3112 __ stop("exact klass and actual klass differ"); 3113 __ bind(ok); 3114 } 3115 #endif 3116 3117 if (!no_conflict) { 3118 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3119 klass_reg_used = true; 3120 if (exact_klass != NULL) { 3121 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3122 metadata2reg(exact_klass->constant_encoding(), klass); 3123 } else { 3124 __ load_klass(klass, obj); 3125 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj 3126 } 3127 3128 // Like InterpreterMacroAssembler::profile_obj_type 3129 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask)); 3130 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask); 3131 __ cmpd(CCR1, R0, klass); 3132 // Klass seen before, nothing to do (regardless of unknown bit). 3133 //beq(CCR1, do_nothing); 3134 3135 __ andi_(R0, klass, TypeEntries::type_unknown); 3136 // Already unknown. Nothing to do anymore. 3137 //bne(CCR0, do_nothing); 3138 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne 3139 __ beq(CCR0, Lnext); 3140 3141 if (TypeEntries::is_type_none(current_klass)) { 3142 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask)); 3143 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3144 __ beq(CCR0, Ldo_update); // First time here. Set profile type. 3145 } 3146 3147 } else { 3148 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3149 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3150 3151 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3152 __ andi_(R0, tmp, TypeEntries::type_unknown); 3153 // Already unknown. Nothing to do anymore. 3154 __ bne(CCR0, Lnext); 3155 } 3156 3157 // Different than before. Cannot keep accurate profile. 3158 __ ori(R0, tmp, TypeEntries::type_unknown); 3159 } else { 3160 // There's a single possible klass at this profile point 3161 assert(exact_klass != NULL, "should be"); 3162 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3163 3164 if (TypeEntries::is_type_none(current_klass)) { 3165 klass_reg_used = true; 3166 metadata2reg(exact_klass->constant_encoding(), klass); 3167 3168 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask)); 3169 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask); 3170 __ cmpd(CCR1, R0, klass); 3171 // Klass seen before, nothing to do (regardless of unknown bit). 3172 __ beq(CCR1, Lnext); 3173 #ifdef ASSERT 3174 { 3175 Label ok; 3176 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask)); 3177 __ beq(CCR0, ok); // First time here. 3178 3179 __ stop("unexpected profiling mismatch"); 3180 __ bind(ok); 3181 } 3182 #endif 3183 // First time here. Set profile type. 3184 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3185 } else { 3186 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3187 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3188 3189 // Already unknown. Nothing to do anymore. 3190 __ andi_(R0, tmp, TypeEntries::type_unknown); 3191 __ bne(CCR0, Lnext); 3192 3193 // Different than before. Cannot keep accurate profile. 3194 __ ori(R0, tmp, TypeEntries::type_unknown); 3195 } 3196 } 3197 3198 __ bind(Ldo_update); 3199 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3200 3201 __ bind(Lnext); 3202 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit 3203 } 3204 __ bind(Ldone); 3205 } 3206 3207 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) { 3208 Unimplemented(); 3209 } 3210 3211 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3212 assert(op->crc()->is_single_cpu(), "crc must be register"); 3213 assert(op->val()->is_single_cpu(), "byte value must be register"); 3214 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3215 Register crc = op->crc()->as_register(); 3216 Register val = op->val()->as_register(); 3217 Register res = op->result_opr()->as_register(); 3218 3219 assert_different_registers(val, crc, res); 3220 3221 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0); 3222 __ kernel_crc32_singleByteReg(crc, val, res, true); 3223 __ mr(res, crc); 3224 } 3225 3226 #undef __