1 /*
2 * Copyright (c) 2002, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2026 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
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24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/accessDecorators.hpp"
31 #include "utilities/macros.hpp"
32
33 // MacroAssembler extends Assembler by a few frequently used macros.
34
35 class ciTypeArray;
36 class OopMap;
37
38 class MacroAssembler: public Assembler {
39 public:
40 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
41
42 // Indicates whether and, if so, which registers must be preserved when calling runtime code.
43 enum PreservationLevel {
44 PRESERVATION_NONE,
45 PRESERVATION_FRAME_LR,
46 PRESERVATION_FRAME_LR_GP_REGS,
47 PRESERVATION_FRAME_LR_GP_FP_REGS
48 };
49
50 //
51 // Optimized instruction emitters
52 //
53
54 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; }
55 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); }
56
57 // load d = *[a+si31]
58 // Emits several instructions if the offset is not encodable in one instruction.
59 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop);
60 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop);
61 inline static bool is_ld_largeoffset(address a);
62 inline static int get_ld_largeoffset_offset(address a);
63
64 inline void round_to(Register r, int modulus);
65
66 // Load/store with type given by parameter.
67 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed);
68 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes);
69
70 // Move register if destination register and target register are different
71 inline void mr_if_needed(Register rd, Register rs, bool allow_invalid = false);
72 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs);
73
74 // Memory barriers.
75 inline void membar(int bits);
76 inline void release();
77 inline void acquire();
78 inline void fence();
79
80 // nop padding
81 void align(int modulus, int max = 252, int rem = 0);
82
83 // Align prefix opcode to make sure it's not on the last word of a
84 // 64-byte block.
85 //
86 // Note: do not call align_prefix() in a .ad file (e.g. ppc.ad). Instead
87 // add ins_alignment(2) to the instruct definition and implement the
88 // compute_padding() method of the instruct node to use
89 // compute_prefix_padding(). See loadConI32Node::compute_padding() in
90 // ppc.ad for an example.
91 void align_prefix();
92
93 //
94 // Constants, loading constants, TOC support
95 //
96
97 // Address of the global TOC.
98 inline static address global_toc();
99 // Offset of given address to the global TOC.
100 inline static int offset_to_global_toc(const address addr);
101
102 // Address of TOC of the current method.
103 inline address method_toc();
104 // Offset of given address to TOC of the current method.
105 inline int offset_to_method_toc(const address addr);
106
107 // Global TOC.
108 void calculate_address_from_global_toc(Register dst, address addr,
109 bool hi16 = true, bool lo16 = true,
110 bool add_relocation = true, bool emit_dummy_addr = false,
111 bool add_addr_to_reloc = true);
112 void calculate_address_from_global_toc(Register dst, Label& addr,
113 bool hi16 = true, bool lo16 = true,
114 bool add_relocation = true, bool emit_dummy_addr = false) {
115 calculate_address_from_global_toc(dst, target(addr), hi16, lo16, add_relocation, emit_dummy_addr, false);
116 }
117 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) {
118 calculate_address_from_global_toc(dst, addr, true, false);
119 };
120 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) {
121 calculate_address_from_global_toc(dst, addr, false, true);
122 };
123
124 inline static bool is_calculate_address_from_global_toc_at(address a, address bound);
125 // Returns address of first instruction in sequence.
126 static address patch_calculate_address_from_global_toc_at(address a, address bound, address addr);
127 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr);
128
129 #ifdef _LP64
130 // Patch narrow oop constant.
131 inline static bool is_set_narrow_oop(address a, address bound);
132 // Returns address of first instruction in sequence.
133 static address patch_set_narrow_oop(address a, address bound, narrowOop data);
134 static narrowOop get_narrow_oop(address a, address bound);
135 #endif
136
137 inline static bool is_load_const_at(address a);
138
139 // Emits an oop const to the constant pool, loads the constant, and
140 // sets a relocation info with address current_pc.
141 // Returns true if successful.
142 bool load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc, bool fixed_size = false);
143
144 static bool is_load_const_from_method_toc_at(address a);
145 static int get_offset_of_load_const_from_method_toc_at(address a);
146
147 // Get the 64 bit constant from a `load_const' sequence.
148 static long get_const(address load_const);
149
150 // Patch the 64 bit constant of a `load_const' sequence. This is a
151 // low level procedure. It neither flushes the instruction cache nor
152 // is it atomic.
153 static void patch_const(address load_const, long x);
154
155 // Metadata in code that we have to keep track of.
156 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
157 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
158 // Oops used directly in compiled code are stored in the constant pool,
159 // and loaded from there.
160 // Allocate new entry for oop in constant pool. Generate relocation.
161 AddressLiteral allocate_oop_address(jobject obj);
162 // Find oop obj in constant pool. Return relocation with it's index.
163 AddressLiteral constant_oop_address(jobject obj);
164
165 // Find oop in constant pool and emit instructions to load it.
166 // Uses constant_oop_address.
167 inline void set_oop_constant(jobject obj, Register d);
168 // Same as load_address.
169 inline void set_oop (AddressLiteral obj_addr, Register d);
170
171 //
172 // branch, jump
173 //
174 // set dst to -1, 0, +1 as follows: if CR0bi is "greater than", dst is set to 1,
175 // if CR0bi is "equal", dst is set to 0, otherwise it's set to -1.
176 void inline set_cmp3(Register dst);
177 // set dst to (treat_unordered_like_less ? -1 : +1)
178 void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
179 // Branch-free implementation to convert !=0 to 1.
180 void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
181 // Convert between half precision float encoded into a short and a float in a FloatRegister.
182 void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
183 void inline hf2f(FloatRegister dst, Register src);
184
185 inline void pd_patch_instruction(address branch, address target, const char* file, int line);
186 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
187
188 // Conditional far branch for destinations encodable in 24+2 bits.
189 // Same interface as bc, e.g. no inverse boint-field.
190 enum {
191 bc_far_optimize_not = 0,
192 bc_far_optimize_on_relocate = 1
193 };
194 // optimize: flag for telling the conditional far branch to optimize
195 // itself when relocated.
196 void bc_far(int boint, int biint, Label& dest, int optimize);
197 void bc_far_optimized(int boint, int biint, Label& dest); // 1 or 2 instructions
198 // Relocation of conditional far branches.
199 static bool is_bc_far_at(address instruction_addr);
200 static address get_dest_of_bc_far_at(address instruction_addr);
201 static void set_dest_of_bc_far_at(address instruction_addr, address dest);
202 private:
203 static bool inline is_bc_far_variant1_at(address instruction_addr);
204 static bool inline is_bc_far_variant2_at(address instruction_addr);
205 static bool inline is_bc_far_variant3_at(address instruction_addr);
206 public:
207
208 // Convenience bc_far versions.
209 inline void blt_far(ConditionRegister crx, Label& L, int optimize);
210 inline void bgt_far(ConditionRegister crx, Label& L, int optimize);
211 inline void beq_far(ConditionRegister crx, Label& L, int optimize);
212 inline void bso_far(ConditionRegister crx, Label& L, int optimize);
213 inline void bge_far(ConditionRegister crx, Label& L, int optimize);
214 inline void ble_far(ConditionRegister crx, Label& L, int optimize);
215 inline void bne_far(ConditionRegister crx, Label& L, int optimize);
216 inline void bns_far(ConditionRegister crx, Label& L, int optimize);
217
218 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump.
219 private:
220 enum {
221 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/),
222 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord,
223 bxx64_patchable_ret_addr_offset = bxx64_patchable_size
224 };
225 void bxx64_patchable(address target, relocInfo::relocType rt, bool link);
226 static bool is_bxx64_patchable_at( address instruction_addr, bool link);
227 // Does the instruction use a pc-relative encoding of the destination?
228 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link);
229 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link);
230 // Load destination relative to global toc.
231 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link);
232 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link);
233 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link);
234 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link);
235
236 public:
237 // call
238 enum {
239 bl64_patchable_instruction_count = bxx64_patchable_instruction_count,
240 bl64_patchable_size = bxx64_patchable_size,
241 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset
242 };
243 inline void bl64_patchable(address target, relocInfo::relocType rt) {
244 bxx64_patchable(target, rt, /*link=*/true);
245 }
246 inline static bool is_bl64_patchable_at(address instruction_addr) {
247 return is_bxx64_patchable_at(instruction_addr, /*link=*/true);
248 }
249 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) {
250 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true);
251 }
252 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) {
253 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true);
254 }
255 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) {
256 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true);
257 }
258 // jump
259 enum {
260 b64_patchable_instruction_count = bxx64_patchable_instruction_count,
261 b64_patchable_size = bxx64_patchable_size,
262 };
263 inline void b64_patchable(address target, relocInfo::relocType rt) {
264 bxx64_patchable(target, rt, /*link=*/false);
265 }
266 inline static bool is_b64_patchable_at(address instruction_addr) {
267 return is_bxx64_patchable_at(instruction_addr, /*link=*/false);
268 }
269 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) {
270 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false);
271 }
272 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) {
273 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false);
274 }
275 inline static address get_dest_of_b64_patchable_at(address instruction_addr) {
276 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false);
277 }
278
279 //
280 // Support for frame handling
281 //
282
283 // some ABI-related functions
284
285 // Clobbers all volatile, (non-floating-point) general-purpose registers for debugging purposes.
286 // This is especially useful for making calls to the JRT in places in which this hasn't been done before;
287 // e.g. with the introduction of LRBs (load reference barriers) for concurrent garbage collection.
288 void clobber_volatile_gprs(Register excluded_register = noreg) NOT_DEBUG_RETURN;
289 // Load bad values into registers that are nonvolatile according to the ABI except R16_thread and R29_TOC.
290 // This is done after vthread preemption and before vthread resume.
291 void clobber_nonvolatile_registers() NOT_DEBUG_RETURN;
292 void clobber_carg_stack_slots(Register tmp);
293
294 int save_nonvolatile_registers_size(bool include_fp_regs, bool include_vector_regs) {
295 int size = (32 - 14) * 8; // GP regs
296 if (include_fp_regs) size += (32 - 14) * 8;
297 if (include_vector_regs) size += (32 - 20) * 16;
298 return size;
299 }
300 void save_nonvolatile_registers( Register dst_base, int offset, bool include_fp_regs, bool include_vector_regs);
301 void restore_nonvolatile_registers(Register src_base, int offset, bool include_fp_regs, bool include_vector_regs);
302
303 enum {
304 num_volatile_gp_regs = 11,
305 num_volatile_fp_regs = 14,
306 num_volatile_regs = num_volatile_gp_regs + num_volatile_fp_regs
307 };
308
309 void save_volatile_gprs( Register dst_base, int offset,
310 bool include_fp_regs = true, bool include_R3_RET_reg = true);
311 void restore_volatile_gprs(Register src_base, int offset,
312 bool include_fp_regs = true, bool include_R3_RET_reg = true);
313 void save_LR(Register tmp);
314 void restore_LR(Register tmp);
315 void save_LR_CR(Register tmp); // tmp contains LR on return.
316 void restore_LR_CR(Register tmp);
317
318 // Get current PC using bl-next-instruction trick.
319 address get_PC_trash_LR(Register result);
320
321 // Resize current frame either relatively wrt to current SP or absolute.
322 void resize_frame(Register offset, Register tmp);
323 void resize_frame(int offset, Register tmp);
324 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2);
325
326 // Push a frame of size bytes.
327 void push_frame(Register bytes, Register tmp);
328
329 // Push a frame of size `bytes'. No abi space provided.
330 void push_frame(unsigned int bytes, Register tmp);
331
332 // Push a frame of size `bytes' plus native_abi_reg_args on top.
333 void push_frame_reg_args(unsigned int bytes, Register tmp);
334
335 // pop current C frame
336 void pop_frame();
337
338 //
339 // Calls
340 //
341
342 private:
343 address _last_calls_return_pc;
344
345 #if defined(ABI_ELFv2)
346 // Generic version of a call to C function.
347 // Updates and returns _last_calls_return_pc.
348 address branch_to(Register function_entry, bool and_link);
349 #else
350 // Generic version of a call to C function via a function descriptor
351 // with variable support for C calling conventions (TOC, ENV, etc.).
352 // updates and returns _last_calls_return_pc.
353 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
354 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee);
355 #endif
356
357 public:
358
359 // Get the pc where the last call will return to. returns _last_calls_return_pc.
360 inline address last_calls_return_pc();
361
362 #if defined(ABI_ELFv2)
363 // Call a C function via a function descriptor and use full C
364 // calling conventions. Updates and returns _last_calls_return_pc.
365 address call_c(Register function_entry);
366 // For tail calls: only branch, don't link, so callee returns to caller of this function.
367 address call_c_and_return_to_caller(Register function_entry);
368 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none);
369 #else
370 // Call a C function via a function descriptor and use full C
371 // calling conventions. Updates and returns _last_calls_return_pc.
372 address call_c(Register function_descriptor);
373 // For tail calls: only branch, don't link, so callee returns to caller of this function.
374 address call_c_and_return_to_caller(Register function_descriptor);
375 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt);
376 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none) {
377 return call_c((const FunctionDescriptor*)function_entry, rt);
378 }
379 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt,
380 Register toc);
381 #endif
382
383 static int ic_check_size();
384 int ic_check(int end_alignment);
385
386 protected:
387
388 // It is imperative that all calls into the VM are handled via the
389 // call_VM macros. They make sure that the stack linkage is setup
390 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
391 // while call_VM_leaf's correspond to LEAF entry points.
392 //
393 // This is the base routine called by the different versions of
394 // call_VM. The interpreter may customize this version by overriding
395 // it for its purposes (e.g., to save/restore additional registers
396 // when doing a VM call).
397 //
398 // If no last_java_sp is specified (noreg) then SP will be used instead.
399 virtual void call_VM_base(
400 // where an oop-result ends up if any; use noreg otherwise
401 Register oop_result,
402 // to set up last_Java_frame in stubs; use noreg otherwise
403 Register last_java_sp,
404 // the entry point
405 address entry_point,
406 // flag which indicates if exception should be checked
407 bool check_exception = true,
408 Label* last_java_pc = nullptr
409 );
410
411 // Support for VM calls. This is the base routine called by the
412 // different versions of call_VM_leaf. The interpreter may customize
413 // this version by overriding it for its purposes (e.g., to
414 // save/restore additional registers when doing a VM call).
415 void call_VM_leaf_base(address entry_point);
416
417 public:
418 // Call into the VM.
419 // Passes the thread pointer (in R3_ARG1) as a prepended argument.
420 // Makes sure oop return values are visible to the GC.
421 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true, Label* last_java_pc = nullptr);
422 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
423 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
424 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true);
425 void call_VM_leaf(address entry_point);
426 void call_VM_leaf(address entry_point, Register arg_1);
427 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
428 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
429
430 // Call a stub function via a function descriptor, but don't save
431 // TOC before call, don't setup TOC and ENV for call, and don't
432 // restore TOC after call. Updates and returns _last_calls_return_pc.
433 inline address call_stub(Register function_entry);
434 inline void call_stub_and_return_to(Register function_entry, Register return_pc);
435
436 void post_call_nop();
437 static bool is_post_call_nop(int instr_bits) {
438 const uint32_t nineth_bit = opp_u_field(1, 9, 9);
439 const uint32_t opcode_mask = 0b111110 << OPCODE_SHIFT;
440 const uint32_t pcn_mask = opcode_mask | nineth_bit;
441 return (instr_bits & pcn_mask) == (Assembler::CMPLI_OPCODE | nineth_bit);
442 }
443
444 //
445 // Java utilities
446 //
447
448 // Read from the polling page, its address is already in a register.
449 inline void load_from_polling_page(Register polling_page_address, int offset = 0);
450 // Check whether instruction is a read access to the polling page
451 // which was emitted by load_from_polling_page(..).
452 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be nullptr*/,
453 address* polling_address_ptr = nullptr);
454
455 // Support for null-checks
456 //
457 // Generates code that causes a null OS exception if the content of reg is null.
458 // If the accessed location is M[reg + offset] and the offset is known, provide the
459 // offset. No explicit code generation is needed if the offset is within a certain
460 // range (0 <= offset <= page_size).
461
462 // Stack overflow checking
463 void bang_stack_with_offset(int offset);
464
465 // If instruction is a stack bang of the form ld, stdu, or
466 // stdux, return the banged address. Otherwise, return 0.
467 static address get_stack_bang_address(int instruction, void* ucontext);
468
469 // Check for reserved stack access in method being exited. If the reserved
470 // stack area was accessed, protect it again and throw StackOverflowError.
471 void reserved_stack_check(Register return_pc);
472
473 // Atomics
474 // CmpxchgX sets condition register to cmpX(current, compare).
475 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
476 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
477 static inline bool cmpxchgx_hint_acquire_lock() { return true; }
478 // The stxcx will probably not be succeeded by a releasing store.
479 static inline bool cmpxchgx_hint_release_lock() { return false; }
480 static inline bool cmpxchgx_hint_atomic_update() { return false; }
481
482 // Cmpxchg semantics
483 enum {
484 MemBarNone = 0,
485 MemBarRel = 1,
486 MemBarAcq = 2,
487 MemBarFenceAfter = 4 // use powers of 2
488 };
489 private:
490 // Helper functions for word/sub-word atomics.
491 void atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value,
492 Register addr_base, Register tmp1, Register tmp2, Register tmp3,
493 bool cmpxchgx_hint, bool is_add, int size);
494 void cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value,
495 RegisterOrConstant compare_value, Register exchange_value,
496 Register addr_base,Label &retry, Label &failed, bool cmpxchgx_hint, int size);
497 void cmpxchg_generic(ConditionRegister flag, Register dest_current_value,
498 RegisterOrConstant compare_value, Register exchange_value,
499 Register addr_base, int semantics, bool cmpxchgx_hint, Register int_flag_success,
500 Label* failed_ext, bool contention_hint, bool weak, int size);
501 public:
502 // Temps and addr_base are killed if processor does not support Power 8 instructions.
503 // Result will be sign extended.
504 void getandsetb(Register dest_current_value, Register exchange_value, Register addr_base,
505 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
506 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 1);
507 }
508 // Temps and addr_base are killed if processor does not support Power 8 instructions.
509 // Result will be sign extended.
510 void getandseth(Register dest_current_value, Register exchange_value, Register addr_base,
511 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
512 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 2);
513 }
514 void getandsetw(Register dest_current_value, Register exchange_value, Register addr_base,
515 bool cmpxchgx_hint) {
516 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, noreg, noreg, noreg, cmpxchgx_hint, false, 4);
517 }
518 void getandsetd(Register dest_current_value, Register exchange_value, Register addr_base,
519 bool cmpxchgx_hint);
520 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
521 // Result will be sign extended.
522 void getandaddb(Register dest_current_value, Register inc_value, Register addr_base,
523 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
524 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 1);
525 }
526 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
527 // Result will be sign extended.
528 void getandaddh(Register dest_current_value, Register inc_value, Register addr_base,
529 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
530 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 2);
531 }
532 void getandaddw(Register dest_current_value, Register inc_value, Register addr_base,
533 Register tmp1, bool cmpxchgx_hint) {
534 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, noreg, noreg, cmpxchgx_hint, true, 4);
535 }
536 void getandaddd(Register dest_current_value, Register exchange_value, Register addr_base,
537 Register tmp, bool cmpxchgx_hint);
538 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
539 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
540 void cmpxchgb(ConditionRegister flag, Register dest_current_value,
541 RegisterOrConstant compare_value, Register exchange_value,
542 Register addr_base, int semantics, bool cmpxchgx_hint = false,
543 Register int_flag_success = noreg, Label* failed = nullptr,
544 bool contention_hint = false, bool weak = false) {
545 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, semantics,
546 cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 1);
547 }
548 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
549 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
550 void cmpxchgh(ConditionRegister flag, Register dest_current_value,
551 RegisterOrConstant compare_value, Register exchange_value,
552 Register addr_base, int semantics, bool cmpxchgx_hint = false,
553 Register int_flag_success = noreg, Label* failed = nullptr,
554 bool contention_hint = false, bool weak = false) {
555 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
556 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 2);
557 }
558 void cmpxchgw(ConditionRegister flag, Register dest_current_value,
559 RegisterOrConstant compare_value, Register exchange_value,
560 Register addr_base,
561 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
562 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
563 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
564 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 4);
565 }
566 void cmpxchgd(ConditionRegister flag, Register dest_current_value,
567 RegisterOrConstant compare_value, Register exchange_value,
568 Register addr_base,
569 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
570 Label* failed = nullptr, bool contention_hint = false, bool weak = false);
571
572 // interface method calling
573 void lookup_interface_method(Register recv_klass,
574 Register intf_klass,
575 RegisterOrConstant itable_index,
576 Register method_result,
577 Register temp_reg, Register temp2_reg,
578 Label& no_such_interface,
579 bool return_method = true);
580
581 // virtual method calling
582 void lookup_virtual_method(Register recv_klass,
583 RegisterOrConstant vtable_index,
584 Register method_result);
585
586 // Test sub_klass against super_klass, with fast and slow paths.
587
588 // The fast path produces a tri-state answer: yes / no / maybe-slow.
589 // One of the three labels can be null, meaning take the fall-through.
590 // If super_check_offset is -1, the value is loaded up from super_klass.
591 // No registers are killed, except temp_reg and temp2_reg.
592 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
593 void check_klass_subtype_fast_path(Register sub_klass,
594 Register super_klass,
595 Register temp1_reg,
596 Register temp2_reg,
597 Label* L_success,
598 Label* L_failure,
599 Label* L_slow_path = nullptr, // default fall through
600 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
601
602 // The rest of the type check; must be wired to a corresponding fast path.
603 // It does not repeat the fast path logic, so don't use it standalone.
604 // The temp_reg can be noreg, if no temps are available.
605 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
606 // Updates the sub's secondary super cache as necessary.
607 void check_klass_subtype_slow_path_linear(Register sub_klass,
608 Register super_klass,
609 Register temp1_reg,
610 Register temp2_reg,
611 Label* L_success = nullptr,
612 Register result_reg = noreg);
613
614 void check_klass_subtype_slow_path_table(Register sub_klass,
615 Register super_klass,
616 Register temp1_reg,
617 Register temp2_reg,
618 Label* L_success = nullptr,
619 Register result_reg = noreg);
620
621 void check_klass_subtype_slow_path(Register sub_klass,
622 Register super_klass,
623 Register temp1_reg,
624 Register temp2_reg,
625 Label* L_success = nullptr,
626 Register result_reg = noreg);
627
628 void lookup_secondary_supers_table_var(Register sub_klass,
629 Register r_super_klass,
630 Register temp1,
631 Register temp2,
632 Register temp3,
633 Register temp4,
634 Register result);
635
636 // If r is valid, return r.
637 // If r is invalid, remove a register r2 from available_regs, add r2
638 // to regs_to_push, then return r2.
639 Register allocate_if_noreg(const Register r,
640 RegSetIterator<Register> &available_regs,
641 RegSet ®s_to_push);
642
643 // Frameless register spills (negative offset from SP)
644 void push_set(RegSet set);
645 void pop_set(RegSet set);
646
647 // Simplified, combined version, good for typical uses.
648 // Falls through on failure.
649 void check_klass_subtype(Register sub_klass,
650 Register super_klass,
651 Register temp1_reg,
652 Register temp2_reg,
653 Label& L_success);
654
655 void repne_scan(Register addr, Register value, Register count, Register scratch);
656
657 // As above, but with a constant super_klass.
658 // The result is in Register result, not the condition codes.
659 void lookup_secondary_supers_table_const(Register r_sub_klass,
660 Register r_super_klass,
661 Register temp1,
662 Register temp2,
663 Register temp3,
664 Register temp4,
665 Register result,
666 u1 super_klass_slot);
667
668 void verify_secondary_supers_table(Register r_sub_klass,
669 Register r_super_klass,
670 Register result,
671 Register temp1,
672 Register temp2,
673 Register temp3);
674
675 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
676 Register r_array_base,
677 Register r_array_index,
678 Register r_bitmap,
679 Register result,
680 Register temp1);
681
682 void clinit_barrier(Register klass,
683 Register thread,
684 Label* L_fast_path = nullptr,
685 Label* L_slow_path = nullptr);
686
687 // Method handle support (JSR 292).
688 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0);
689
690 void push_cont_fastpath();
691 void pop_cont_fastpath();
692 void atomically_flip_locked_state(bool is_unlock, Register obj, Register tmp, Label& failed, int semantics);
693 void fast_lock(Register box, Register obj, Register t1, Register t2, Label& slow);
694 void fast_unlock(Register obj, Register t1, Label& slow);
695
696 // allocation (for C1)
697 void tlab_allocate(
698 Register obj, // result: pointer to object after successful allocation
699 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
700 int con_size_in_bytes, // object size in bytes if known at compile time
701 Register t1, // temp register
702 Label& slow_case // continuation point if fast allocation fails
703 );
704
705 enum { trampoline_stub_size = 6 * 4 };
706 address emit_trampoline_stub(int destination_toc_offset, int insts_call_instruction_offset, Register Rtoc = noreg);
707
708 void compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
709 Register tmp1, Register tmp2, Register tmp3);
710
711 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
712 Register tmp1, Register tmp2, Register tmp3);
713
714 // Check if safepoint requested and if so branch
715 void safepoint_poll(Label& slow_path, Register temp, bool at_return, bool in_nmethod);
716 void jump_to_polling_page_return_handler_blob(int safepoint_offset, bool fixed_size = false);
717
718 void resolve_jobject(Register value, Register tmp1, Register tmp2,
719 MacroAssembler::PreservationLevel preservation_level);
720 void resolve_global_jobject(Register value, Register tmp1, Register tmp2,
721 MacroAssembler::PreservationLevel preservation_level);
722
723 // Support for managing the JavaThread pointer (i.e.; the reference to
724 // thread-local information).
725
726 // Support for last Java frame (but use call_VM instead where possible):
727 // access R16_thread->last_Java_sp.
728 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
729 void reset_last_Java_frame(bool check_last_java_sp = true);
730 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, Label* jpc = nullptr);
731
732 // Read vm result from thread: oop_result = R16_thread->result;
733 void get_vm_result_oop(Register oop_result);
734 void get_vm_result_metadata(Register metadata_result);
735
736 static bool needs_explicit_null_check(intptr_t offset);
737 static bool uses_implicit_null_check(void* address);
738
739 // Trap-instruction-based checks.
740 // Range checks can be distinguished from zero checks as they check 32 bit,
741 // zero checks all 64 bits (tw, td).
742 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual);
743 static bool is_trap_null_check(int x) {
744 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) ||
745 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0);
746 }
747
748 inline void trap_ic_miss_check(Register a, Register b);
749 static bool is_trap_ic_miss_check(int x) {
750 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/);
751 }
752
753 // Implicit or explicit null check, jumps to static address exception_entry.
754 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry);
755 inline void null_check(Register a, int offset, Label *Lis_null); // implicit only if Lis_null not provided
756
757 // Access heap oop, handle encoding and GC barriers.
758 // Some GC barriers call C so use needs_frame = true if an extra frame is needed at the current call site.
759 inline void access_store_at(BasicType type, DecoratorSet decorators,
760 Register base, RegisterOrConstant ind_or_offs, Register val,
761 Register tmp1, Register tmp2, Register tmp3,
762 MacroAssembler::PreservationLevel preservation_level);
763 inline void access_load_at(BasicType type, DecoratorSet decorators,
764 Register base, RegisterOrConstant ind_or_offs, Register dst,
765 Register tmp1, Register tmp2,
766 MacroAssembler::PreservationLevel preservation_level, Label *L_handle_null = nullptr);
767
768 public:
769 // Specify tmp1 for better code in certain compressed oops cases. Specify Label to bail out on null oop.
770 // tmp1, tmp2 and needs_frame are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
771 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
772 Register tmp1, Register tmp2,
773 MacroAssembler::PreservationLevel preservation_level,
774 DecoratorSet decorators = 0, Label *L_handle_null = nullptr);
775
776 inline void store_heap_oop(Register d, RegisterOrConstant offs, Register s1,
777 Register tmp1, Register tmp2, Register tmp3,
778 MacroAssembler::PreservationLevel preservation_level, DecoratorSet decorators = 0);
779
780 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong.
781 // src == d allowed.
782 inline Register encode_heap_oop_not_null(Register d, Register src = noreg);
783 inline Register decode_heap_oop_not_null(Register d, Register src = noreg);
784
785 // Null allowed.
786 inline Register encode_heap_oop(Register d, Register src); // Prefer null check in GC barrier!
787 inline void decode_heap_oop(Register d);
788
789 // Load/Store klass oop from klass field. Compress.
790 void load_klass_no_decode(Register dst, Register src);
791 void load_klass(Register dst, Register src);
792 void load_narrow_klass_compact(Register dst, Register src);
793 void cmp_klass(ConditionRegister dst, Register obj, Register klass, Register tmp, Register tmp2);
794 void cmp_klasses_from_objects(ConditionRegister dst, Register obj1, Register obj2, Register tmp1, Register tmp2);
795 void load_klass_check_null(Register dst, Register src, Label* is_null = nullptr);
796 void store_klass(Register dst_oop, Register klass, Register tmp = R0);
797 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified.
798
799 void resolve_oop_handle(Register result, Register tmp1, Register tmp2,
800 MacroAssembler::PreservationLevel preservation_level);
801 void resolve_weak_handle(Register result, Register tmp1, Register tmp2,
802 MacroAssembler::PreservationLevel preservation_level);
803 void load_method_holder(Register holder, Register method);
804
805 static int instr_size_for_load_klass();
806 void decode_klass_not_null(Register dst, Register src = noreg);
807 Register encode_klass_not_null(Register dst, Register src = noreg);
808
809 // SIGTRAP-based range checks for arrays.
810 inline void trap_range_check_l(Register a, Register b);
811 inline void trap_range_check_l(Register a, int si16);
812 static bool is_trap_range_check_l(int x) {
813 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
814 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) );
815 }
816 inline void trap_range_check_le(Register a, int si16);
817 static bool is_trap_range_check_le(int x) {
818 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/);
819 }
820 inline void trap_range_check_g(Register a, int si16);
821 static bool is_trap_range_check_g(int x) {
822 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/);
823 }
824 inline void trap_range_check_ge(Register a, Register b);
825 inline void trap_range_check_ge(Register a, int si16);
826 static bool is_trap_range_check_ge(int x) {
827 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
828 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) );
829 }
830 static bool is_trap_range_check(int x) {
831 return is_trap_range_check_l(x) || is_trap_range_check_le(x) ||
832 is_trap_range_check_g(x) || is_trap_range_check_ge(x);
833 }
834
835 void clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp = R0, int offset = 0);
836 void clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp = R0);
837 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0, long const_cnt = -1);
838
839 // Emitters for BigInteger.multiplyToLen intrinsic.
840 inline void multiply64(Register dest_hi, Register dest_lo,
841 Register x, Register y);
842 void add2_with_carry(Register dest_hi, Register dest_lo,
843 Register src1, Register src2);
844 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
845 Register y, Register y_idx, Register z,
846 Register carry, Register product_high, Register product,
847 Register idx, Register kdx, Register tmp);
848 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
849 Register yz_idx, Register idx, Register carry,
850 Register product_high, Register product, Register tmp,
851 int offset);
852 void multiply_128_x_128_loop(Register x_xstart,
853 Register y, Register z,
854 Register yz_idx, Register idx, Register carry,
855 Register product_high, Register product,
856 Register carry2, Register tmp);
857 void muladd(Register out, Register in, Register offset, Register len, Register k,
858 Register tmp1, Register tmp2, Register carry);
859 void multiply_to_len(Register x, Register xlen,
860 Register y, Register ylen,
861 Register z,
862 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
863 Register tmp6, Register tmp7, Register tmp8, Register tmp9, Register tmp10,
864 Register tmp11, Register tmp12, Register tmp13);
865
866 // Emitters for CRC32 calculation.
867 // A note on invertCRC:
868 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
869 // CRC32 holds it's current crc value in the externally visible representation.
870 // CRC32C holds it's current crc value in internal format, ready for updating.
871 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
872 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
873 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
874 void load_reverse_32(Register dst, Register src);
875 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3);
876 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp);
877 void update_byte_crc32(Register crc, Register val, Register table);
878 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
879 Register data, bool loopAlignment);
880 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
881 Register t0, Register t1, Register t2, Register t3,
882 Register tc0, Register tc1, Register tc2, Register tc3);
883 void kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants,
884 Register t0, Register t1, Register t2, Register t3, Register t4,
885 Register t5, Register t6, bool invertCRC);
886 void kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants,
887 Register t0, Register t1, Register t2, Register t3, Register t4,
888 Register t5, Register t6);
889 // Version which internally decides what to use.
890 void crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2,
891 Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c);
892
893 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
894 bool invertCRC);
895
896 // SHA-2 auxiliary functions and public interfaces
897 private:
898 void sha256_deque(const VectorRegister src,
899 const VectorRegister dst1, const VectorRegister dst2, const VectorRegister dst3);
900 void sha256_load_h_vec(const VectorRegister a, const VectorRegister e, const Register hptr);
901 void sha256_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
902 void sha256_load_w_plus_k_vec(const Register buf_in, const VectorRegister* ws,
903 const int total_ws, const Register k, const VectorRegister* kpws,
904 const int total_kpws);
905 void sha256_calc_4w(const VectorRegister w0, const VectorRegister w1,
906 const VectorRegister w2, const VectorRegister w3, const VectorRegister kpw0,
907 const VectorRegister kpw1, const VectorRegister kpw2, const VectorRegister kpw3,
908 const Register j, const Register k);
909 void sha256_update_sha_state(const VectorRegister a, const VectorRegister b,
910 const VectorRegister c, const VectorRegister d, const VectorRegister e,
911 const VectorRegister f, const VectorRegister g, const VectorRegister h,
912 const Register hptr);
913
914 void sha512_load_w_vec(const Register buf_in, const VectorRegister* ws, const int total_ws);
915 void sha512_update_sha_state(const Register state, const VectorRegister* hs, const int total_hs);
916 void sha512_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
917 void sha512_load_h_vec(const Register state, const VectorRegister* hs, const int total_hs);
918 void sha512_calc_2w(const VectorRegister w0, const VectorRegister w1,
919 const VectorRegister w2, const VectorRegister w3,
920 const VectorRegister w4, const VectorRegister w5,
921 const VectorRegister w6, const VectorRegister w7,
922 const VectorRegister kpw0, const VectorRegister kpw1, const Register j,
923 const VectorRegister vRb, const Register k);
924
925 public:
926 void sha256(bool multi_block);
927 void sha512(bool multi_block);
928
929 void cache_wb(Address line);
930 void cache_wbsync(bool is_presync);
931
932 //
933 // Debugging
934 //
935
936 // assert on cr0
937 enum AsmAssertCond {
938 eq,
939 ne,
940 ge,
941 gt,
942 lt,
943 le
944 };
945 void asm_assert(AsmAssertCond cond, const char* msg) PRODUCT_RETURN;
946 void asm_assert_eq(const char* msg) { asm_assert(eq, msg); }
947 void asm_assert_ne(const char* msg) { asm_assert(ne, msg); }
948
949 private:
950 void asm_assert_mems_zero(AsmAssertCond cond, int size, int mem_offset, Register mem_base,
951 const char* msg) NOT_DEBUG_RETURN;
952
953 public:
954
955 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg) {
956 asm_assert_mems_zero(eq, 8, mem_offset, mem_base, msg);
957 }
958 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg) {
959 asm_assert_mems_zero(ne, 8, mem_offset, mem_base, msg);
960 }
961
962 // Calls verify_oop. If UseCompressedOops is on, decodes the oop.
963 // Preserves reg.
964 void verify_coop(Register reg, const char*);
965 // Emit code to verify that reg contains a valid oop if +VerifyOops is set.
966 void verify_oop(Register reg, const char* s = "broken oop");
967 void verify_oop_addr(RegisterOrConstant offs, Register base, const char* s = "contains broken oop");
968
969 // TODO: verify method and klass metadata (compare against vptr?)
970 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
971 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
972
973 // Convenience method returning function entry. For the ELFv1 case
974 // creates function descriptor at the current address and returns
975 // the pointer to it. For the ELFv2 case returns the current address.
976 inline address function_entry();
977
978 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
979 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
980
981 private:
982 void stop(int type, const char* msg);
983
984 public:
985 enum {
986 stop_stop = 0,
987 stop_untested = 1,
988 stop_unimplemented = 2,
989 stop_shouldnotreachhere = 3,
990 stop_msg_present = -0x8000
991 };
992
993 // Prints msg, dumps registers and stops execution.
994 void stop (const char* msg = nullptr) { stop(stop_stop, msg); }
995 void untested (const char* msg = nullptr) { stop(stop_untested, msg); }
996 void unimplemented (const char* msg = nullptr) { stop(stop_unimplemented, msg); }
997 void should_not_reach_here(const char* msg = nullptr) { stop(stop_shouldnotreachhere, msg); }
998
999 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN;
1000 };
1001
1002 #endif // CPU_PPC_MACROASSEMBLER_PPC_HPP