1 /*
2 * Copyright (c) 2002, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2026 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
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24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/accessDecorators.hpp"
31 #include "utilities/macros.hpp"
32
33 // MacroAssembler extends Assembler by a few frequently used macros.
34
35 class ciTypeArray;
36 class OopMap;
37
38 class MacroAssembler: public Assembler {
39 public:
40 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
41
42 // Indicates whether and, if so, which registers must be preserved when calling runtime code.
43 enum PreservationLevel {
44 PRESERVATION_NONE,
45 PRESERVATION_FRAME_LR,
46 PRESERVATION_FRAME_LR_GP_REGS,
47 PRESERVATION_FRAME_LR_GP_FP_REGS
48 };
49
50 //
51 // Optimized instruction emitters
52 //
53
54 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; }
55 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); }
56
57 // load d = *[a+si31]
58 // Emits several instructions if the offset is not encodable in one instruction.
59 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop);
60 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop);
61 inline static bool is_ld_largeoffset(address a);
62 inline static int get_ld_largeoffset_offset(address a);
63
64 inline void round_to(Register r, int modulus);
65
66 // Load/store with type given by parameter.
67 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed);
68 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes);
69
70 // Move register if destination register and target register are different
71 inline void mr_if_needed(Register rd, Register rs, bool allow_invalid = false);
72 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs);
73
74 // Memory barriers.
75 inline void membar(int bits);
76 inline void release();
77 inline void acquire();
78 inline void fence();
79
80 // nop padding
81 void align(int modulus, int max = 252, int rem = 0);
82
83 // Align prefix opcode to make sure it's not on the last word of a
84 // 64-byte block.
85 //
86 // Note: do not call align_prefix() in a .ad file (e.g. ppc.ad). Instead
87 // add ins_alignment(2) to the instruct definition and implement the
88 // compute_padding() method of the instruct node to use
89 // compute_prefix_padding(). See loadConI32Node::compute_padding() in
90 // ppc.ad for an example.
91 void align_prefix();
92
93 //
94 // Constants, loading constants, TOC support
95 //
96
97 // Address of the global TOC.
98 inline static address global_toc();
99 // Offset of given address to the global TOC.
100 inline static int offset_to_global_toc(const address addr);
101
102 // Address of TOC of the current method.
103 inline address method_toc();
104 // Offset of given address to TOC of the current method.
105 inline int offset_to_method_toc(const address addr);
106
107 // Global TOC.
108 void calculate_address_from_global_toc(Register dst, address addr,
109 bool hi16 = true, bool lo16 = true,
110 bool add_relocation = true, bool emit_dummy_addr = false,
111 bool add_addr_to_reloc = true);
112 void calculate_address_from_global_toc(Register dst, Label& addr,
113 bool hi16 = true, bool lo16 = true,
114 bool add_relocation = true, bool emit_dummy_addr = false) {
115 calculate_address_from_global_toc(dst, target(addr), hi16, lo16, add_relocation, emit_dummy_addr, false);
116 }
117 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) {
118 calculate_address_from_global_toc(dst, addr, true, false);
119 };
120 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) {
121 calculate_address_from_global_toc(dst, addr, false, true);
122 };
123
124 inline static bool is_calculate_address_from_global_toc_at(address a, address bound);
125 // Returns address of first instruction in sequence.
126 static address patch_calculate_address_from_global_toc_at(address a, address bound, address addr);
127 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr);
128
129 #ifdef _LP64
130 // Patch narrow oop constant.
131 inline static bool is_set_narrow_oop(address a, address bound);
132 // Returns address of first instruction in sequence.
133 static address patch_set_narrow_oop(address a, address bound, narrowOop data);
134 static narrowOop get_narrow_oop(address a, address bound);
135 #endif
136
137 inline static bool is_load_const_at(address a);
138
139 // Emits an oop const to the constant pool, loads the constant, and
140 // sets a relocation info with address current_pc.
141 // Returns true if successful.
142 bool load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc, bool fixed_size = false);
143
144 static bool is_load_const_from_method_toc_at(address a);
145 static int get_offset_of_load_const_from_method_toc_at(address a);
146
147 // Get the 64 bit constant from a `load_const' sequence.
148 static long get_const(address load_const);
149
150 // Patch the 64 bit constant of a `load_const' sequence. This is a
151 // low level procedure. It neither flushes the instruction cache nor
152 // is it atomic.
153 static void patch_const(address load_const, long x);
154
155 // Metadata in code that we have to keep track of.
156 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
157 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
158 // Oops used directly in compiled code are stored in the constant pool,
159 // and loaded from there.
160 // Allocate new entry for oop in constant pool. Generate relocation.
161 AddressLiteral allocate_oop_address(jobject obj);
162 // Find oop obj in constant pool. Return relocation with it's index.
163 AddressLiteral constant_oop_address(jobject obj);
164
165 // Find oop in constant pool and emit instructions to load it.
166 // Uses constant_oop_address.
167 inline void set_oop_constant(jobject obj, Register d);
168 // Same as load_address.
169 inline void set_oop (AddressLiteral obj_addr, Register d);
170
171 //
172 // branch, jump
173 //
174 // set dst to -1, 0, +1 as follows: if CR0bi is "greater than", dst is set to 1,
175 // if CR0bi is "equal", dst is set to 0, otherwise it's set to -1.
176 void inline set_cmp3(Register dst);
177 // set dst to (treat_unordered_like_less ? -1 : +1)
178 void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
179 // Branch-free implementation to convert !=0 to 1.
180 void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
181 // Convert between half precision float encoded into a short and a float in a FloatRegister.
182 void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
183 void inline hf2f(FloatRegister dst, Register src);
184
185 inline void pd_patch_instruction(address branch, address target, const char* file, int line);
186 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
187
188 // Conditional far branch for destinations encodable in 24+2 bits.
189 // Same interface as bc, e.g. no inverse boint-field.
190 enum {
191 bc_far_optimize_not = 0,
192 bc_far_optimize_on_relocate = 1
193 };
194 // optimize: flag for telling the conditional far branch to optimize
195 // itself when relocated.
196 void bc_far(int boint, int biint, Label& dest, int optimize);
197 void bc_far_optimized(int boint, int biint, Label& dest); // 1 or 2 instructions
198 // Relocation of conditional far branches.
199 static bool is_bc_far_at(address instruction_addr);
200 static address get_dest_of_bc_far_at(address instruction_addr);
201 static void set_dest_of_bc_far_at(address instruction_addr, address dest);
202 private:
203 static bool inline is_bc_far_variant1_at(address instruction_addr);
204 static bool inline is_bc_far_variant2_at(address instruction_addr);
205 static bool inline is_bc_far_variant3_at(address instruction_addr);
206 public:
207
208 // Convenience bc_far versions.
209 inline void blt_far(ConditionRegister crx, Label& L, int optimize);
210 inline void bgt_far(ConditionRegister crx, Label& L, int optimize);
211 inline void beq_far(ConditionRegister crx, Label& L, int optimize);
212 inline void bso_far(ConditionRegister crx, Label& L, int optimize);
213 inline void bge_far(ConditionRegister crx, Label& L, int optimize);
214 inline void ble_far(ConditionRegister crx, Label& L, int optimize);
215 inline void bne_far(ConditionRegister crx, Label& L, int optimize);
216 inline void bns_far(ConditionRegister crx, Label& L, int optimize);
217
218 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump.
219 private:
220 enum {
221 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/),
222 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord,
223 bxx64_patchable_ret_addr_offset = bxx64_patchable_size
224 };
225 void bxx64_patchable(address target, relocInfo::relocType rt, bool link);
226 static bool is_bxx64_patchable_at( address instruction_addr, bool link);
227 // Does the instruction use a pc-relative encoding of the destination?
228 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link);
229 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link);
230 // Load destination relative to global toc.
231 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link);
232 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link);
233 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link);
234 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link);
235
236 public:
237 // call
238 enum {
239 bl64_patchable_instruction_count = bxx64_patchable_instruction_count,
240 bl64_patchable_size = bxx64_patchable_size,
241 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset
242 };
243 inline void bl64_patchable(address target, relocInfo::relocType rt) {
244 bxx64_patchable(target, rt, /*link=*/true);
245 }
246 inline static bool is_bl64_patchable_at(address instruction_addr) {
247 return is_bxx64_patchable_at(instruction_addr, /*link=*/true);
248 }
249 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) {
250 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true);
251 }
252 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) {
253 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true);
254 }
255 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) {
256 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true);
257 }
258 // jump
259 enum {
260 b64_patchable_instruction_count = bxx64_patchable_instruction_count,
261 b64_patchable_size = bxx64_patchable_size,
262 };
263 inline void b64_patchable(address target, relocInfo::relocType rt) {
264 bxx64_patchable(target, rt, /*link=*/false);
265 }
266 inline static bool is_b64_patchable_at(address instruction_addr) {
267 return is_bxx64_patchable_at(instruction_addr, /*link=*/false);
268 }
269 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) {
270 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false);
271 }
272 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) {
273 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false);
274 }
275 inline static address get_dest_of_b64_patchable_at(address instruction_addr) {
276 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false);
277 }
278
279 //
280 // Support for frame handling
281 //
282
283 // some ABI-related functions
284
285 // Clobbers all volatile, (non-floating-point) general-purpose registers for debugging purposes.
286 // This is especially useful for making calls to the JRT in places in which this hasn't been done before;
287 // e.g. with the introduction of LRBs (load reference barriers) for concurrent garbage collection.
288 void clobber_volatile_gprs(Register excluded_register = noreg) NOT_DEBUG_RETURN;
289 // Load bad values into registers that are nonvolatile according to the ABI except R16_thread and R29_TOC.
290 // This is done after vthread preemption and before vthread resume.
291 void clobber_nonvolatile_registers() NOT_DEBUG_RETURN;
292 void clobber_carg_stack_slots(Register tmp);
293
294 int save_nonvolatile_registers_size(bool include_fp_regs, bool include_vector_regs) {
295 int size = (32 - 14) * 8; // GP regs
296 if (include_fp_regs) size += (32 - 14) * 8;
297 if (include_vector_regs) size += (32 - 20) * 16;
298 return size;
299 }
300 void save_nonvolatile_registers( Register dst_base, int offset, bool include_fp_regs, bool include_vector_regs);
301 void restore_nonvolatile_registers(Register src_base, int offset, bool include_fp_regs, bool include_vector_regs);
302
303 enum {
304 num_volatile_gp_regs = 11,
305 num_volatile_fp_regs = 14,
306 num_volatile_regs = num_volatile_gp_regs + num_volatile_fp_regs
307 };
308
309 void save_volatile_gprs( Register dst_base, int offset,
310 bool include_fp_regs = true, bool include_R3_RET_reg = true);
311 void restore_volatile_gprs(Register src_base, int offset,
312 bool include_fp_regs = true, bool include_R3_RET_reg = true);
313 void save_LR(Register tmp);
314 void restore_LR(Register tmp);
315 void save_LR_CR(Register tmp); // tmp contains LR on return.
316 void restore_LR_CR(Register tmp);
317
318 // Get current PC using bl-next-instruction trick.
319 address get_PC_trash_LR(Register result);
320
321 // Resize current frame either relatively wrt to current SP or absolute.
322 void resize_frame(Register offset, Register tmp);
323 void resize_frame(int offset, Register tmp);
324 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2);
325
326 // Push a frame of size bytes.
327 void push_frame(Register bytes, Register tmp);
328
329 // Push a frame of size `bytes'. No abi space provided.
330 void push_frame(unsigned int bytes, Register tmp);
331
332 // Push a frame of size `bytes' plus native_abi_reg_args on top.
333 void push_frame_reg_args(unsigned int bytes, Register tmp);
334
335 // pop current C frame
336 void pop_frame();
337
338 //
339 // Calls
340 //
341
342 private:
343 address _last_calls_return_pc;
344
345 #if defined(ABI_ELFv2)
346 // Generic version of a call to C function.
347 // Updates and returns _last_calls_return_pc.
348 address branch_to(Register function_entry, bool and_link);
349 #else
350 // Generic version of a call to C function via a function descriptor
351 // with variable support for C calling conventions (TOC, ENV, etc.).
352 // updates and returns _last_calls_return_pc.
353 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
354 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee);
355 #endif
356
357 public:
358
359 // Get the pc where the last call will return to. returns _last_calls_return_pc.
360 inline address last_calls_return_pc();
361
362 #if defined(ABI_ELFv2)
363 // Call a C function via a function descriptor and use full C
364 // calling conventions. Updates and returns _last_calls_return_pc.
365 address call_c(Register function_entry);
366 // For tail calls: only branch, don't link, so callee returns to caller of this function.
367 address call_c_and_return_to_caller(Register function_entry);
368 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none);
369 #else
370 // Call a C function via a function descriptor and use full C
371 // calling conventions. Updates and returns _last_calls_return_pc.
372 address call_c(Register function_descriptor);
373 // For tail calls: only branch, don't link, so callee returns to caller of this function.
374 address call_c_and_return_to_caller(Register function_descriptor);
375 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt);
376 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none) {
377 return call_c((const FunctionDescriptor*)function_entry, rt);
378 }
379 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt,
380 Register toc);
381 #endif
382
383 // CompiledIC call
384 bool ic_call(Register Rmethod_toc,
385 address target,
386 jint method_index = 0,
387 bool scratch_emit = false,
388 bool fixed_size = false);
389 static int ic_check_size();
390 int ic_check(int end_alignment);
391
392 enum { trampoline_stub_size = 6 * 4 };
393 address trampoline_call(AddressLiteral target,
394 Register Rmethod_toc = noreg,
395 bool scratch_emit = false);
396
397 protected:
398
399 // It is imperative that all calls into the VM are handled via the
400 // call_VM macros. They make sure that the stack linkage is setup
401 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
402 // while call_VM_leaf's correspond to LEAF entry points.
403 //
404 // This is the base routine called by the different versions of
405 // call_VM. The interpreter may customize this version by overriding
406 // it for its purposes (e.g., to save/restore additional registers
407 // when doing a VM call).
408 //
409 // If no last_java_sp is specified (noreg) then SP will be used instead.
410 virtual void call_VM_base(
411 // where an oop-result ends up if any; use noreg otherwise
412 Register oop_result,
413 // to set up last_Java_frame in stubs; use noreg otherwise
414 Register last_java_sp,
415 // the entry point
416 address entry_point,
417 // flag which indicates if exception should be checked
418 bool check_exception = true,
419 Label* last_java_pc = nullptr
420 );
421
422 // Support for VM calls. This is the base routine called by the
423 // different versions of call_VM_leaf. The interpreter may customize
424 // this version by overriding it for its purposes (e.g., to
425 // save/restore additional registers when doing a VM call).
426 void call_VM_leaf_base(address entry_point);
427
428 public:
429 // Call into the VM.
430 // Passes the thread pointer (in R3_ARG1) as a prepended argument.
431 // Makes sure oop return values are visible to the GC.
432 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true, Label* last_java_pc = nullptr);
433 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
434 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
435 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true);
436 void call_VM_leaf(address entry_point);
437 void call_VM_leaf(address entry_point, Register arg_1);
438 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
439 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
440
441 // Call a stub function via a function descriptor, but don't save
442 // TOC before call, don't setup TOC and ENV for call, and don't
443 // restore TOC after call. Updates and returns _last_calls_return_pc.
444 inline address call_stub(Register function_entry);
445 inline void call_stub_and_return_to(Register function_entry, Register return_pc);
446
447 void post_call_nop();
448 static bool is_post_call_nop(int instr_bits) {
449 const uint32_t nineth_bit = opp_u_field(1, 9, 9);
450 const uint32_t opcode_mask = 0b111110 << OPCODE_SHIFT;
451 const uint32_t pcn_mask = opcode_mask | nineth_bit;
452 return (instr_bits & pcn_mask) == (Assembler::CMPLI_OPCODE | nineth_bit);
453 }
454
455 //
456 // Java utilities
457 //
458
459 // Read from the polling page, its address is already in a register.
460 inline void load_from_polling_page(Register polling_page_address, int offset = 0);
461 // Check whether instruction is a read access to the polling page
462 // which was emitted by load_from_polling_page(..).
463 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be nullptr*/,
464 address* polling_address_ptr = nullptr);
465
466 // Support for null-checks
467 //
468 // Generates code that causes a null OS exception if the content of reg is null.
469 // If the accessed location is M[reg + offset] and the offset is known, provide the
470 // offset. No explicit code generation is needed if the offset is within a certain
471 // range (0 <= offset <= page_size).
472
473 // Stack overflow checking
474 void bang_stack_with_offset(int offset);
475
476 // If instruction is a stack bang of the form ld, stdu, or
477 // stdux, return the banged address. Otherwise, return 0.
478 static address get_stack_bang_address(int instruction, void* ucontext);
479
480 // Check for reserved stack access in method being exited. If the reserved
481 // stack area was accessed, protect it again and throw StackOverflowError.
482 void reserved_stack_check(Register return_pc);
483
484 // Atomics
485 // CmpxchgX sets condition register to cmpX(current, compare).
486 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
487 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
488 static inline bool cmpxchgx_hint_acquire_lock() { return true; }
489 // The stxcx will probably not be succeeded by a releasing store.
490 static inline bool cmpxchgx_hint_release_lock() { return false; }
491 static inline bool cmpxchgx_hint_atomic_update() { return false; }
492
493 // Cmpxchg semantics
494 enum {
495 MemBarNone = 0,
496 MemBarRel = 1,
497 MemBarAcq = 2,
498 MemBarFenceAfter = 4 // use powers of 2
499 };
500 private:
501 // Helper functions for word/sub-word atomics.
502 void atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value,
503 Register addr_base, Register tmp1, Register tmp2, Register tmp3,
504 bool cmpxchgx_hint, bool is_add, int size);
505 void cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value,
506 RegisterOrConstant compare_value, Register exchange_value,
507 Register addr_base,Label &retry, Label &failed, bool cmpxchgx_hint, int size);
508 void cmpxchg_generic(ConditionRegister flag, Register dest_current_value,
509 RegisterOrConstant compare_value, Register exchange_value,
510 Register addr_base, int semantics, bool cmpxchgx_hint, Register int_flag_success,
511 Label* failed_ext, bool contention_hint, bool weak, int size);
512 public:
513 // Temps and addr_base are killed if processor does not support Power 8 instructions.
514 // Result will be sign extended.
515 void getandsetb(Register dest_current_value, Register exchange_value, Register addr_base,
516 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
517 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 1);
518 }
519 // Temps and addr_base are killed if processor does not support Power 8 instructions.
520 // Result will be sign extended.
521 void getandseth(Register dest_current_value, Register exchange_value, Register addr_base,
522 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
523 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 2);
524 }
525 void getandsetw(Register dest_current_value, Register exchange_value, Register addr_base,
526 bool cmpxchgx_hint) {
527 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, noreg, noreg, noreg, cmpxchgx_hint, false, 4);
528 }
529 void getandsetd(Register dest_current_value, Register exchange_value, Register addr_base,
530 bool cmpxchgx_hint);
531 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
532 // Result will be sign extended.
533 void getandaddb(Register dest_current_value, Register inc_value, Register addr_base,
534 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
535 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 1);
536 }
537 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
538 // Result will be sign extended.
539 void getandaddh(Register dest_current_value, Register inc_value, Register addr_base,
540 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
541 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 2);
542 }
543 void getandaddw(Register dest_current_value, Register inc_value, Register addr_base,
544 Register tmp1, bool cmpxchgx_hint) {
545 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, noreg, noreg, cmpxchgx_hint, true, 4);
546 }
547 void getandaddd(Register dest_current_value, Register exchange_value, Register addr_base,
548 Register tmp, bool cmpxchgx_hint);
549 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
550 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
551 void cmpxchgb(ConditionRegister flag, Register dest_current_value,
552 RegisterOrConstant compare_value, Register exchange_value,
553 Register addr_base, int semantics, bool cmpxchgx_hint = false,
554 Register int_flag_success = noreg, Label* failed = nullptr,
555 bool contention_hint = false, bool weak = false) {
556 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, semantics,
557 cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 1);
558 }
559 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
560 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
561 void cmpxchgh(ConditionRegister flag, Register dest_current_value,
562 RegisterOrConstant compare_value, Register exchange_value,
563 Register addr_base, int semantics, bool cmpxchgx_hint = false,
564 Register int_flag_success = noreg, Label* failed = nullptr,
565 bool contention_hint = false, bool weak = false) {
566 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
567 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 2);
568 }
569 void cmpxchgw(ConditionRegister flag, Register dest_current_value,
570 RegisterOrConstant compare_value, Register exchange_value,
571 Register addr_base,
572 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
573 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
574 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
575 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 4);
576 }
577 void cmpxchgd(ConditionRegister flag, Register dest_current_value,
578 RegisterOrConstant compare_value, Register exchange_value,
579 Register addr_base,
580 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
581 Label* failed = nullptr, bool contention_hint = false, bool weak = false);
582
583 // interface method calling
584 void lookup_interface_method(Register recv_klass,
585 Register intf_klass,
586 RegisterOrConstant itable_index,
587 Register method_result,
588 Register temp_reg, Register temp2_reg,
589 Label& no_such_interface,
590 bool return_method = true);
591
592 // virtual method calling
593 void lookup_virtual_method(Register recv_klass,
594 RegisterOrConstant vtable_index,
595 Register method_result);
596
597 // Test sub_klass against super_klass, with fast and slow paths.
598
599 // The fast path produces a tri-state answer: yes / no / maybe-slow.
600 // One of the three labels can be null, meaning take the fall-through.
601 // If super_check_offset is -1, the value is loaded up from super_klass.
602 // No registers are killed, except temp_reg and temp2_reg.
603 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
604 void check_klass_subtype_fast_path(Register sub_klass,
605 Register super_klass,
606 Register temp1_reg,
607 Register temp2_reg,
608 Label* L_success,
609 Label* L_failure,
610 Label* L_slow_path = nullptr, // default fall through
611 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
612
613 // The rest of the type check; must be wired to a corresponding fast path.
614 // It does not repeat the fast path logic, so don't use it standalone.
615 // The temp_reg can be noreg, if no temps are available.
616 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
617 // Updates the sub's secondary super cache as necessary.
618 void check_klass_subtype_slow_path_linear(Register sub_klass,
619 Register super_klass,
620 Register temp1_reg,
621 Register temp2_reg,
622 Label* L_success = nullptr,
623 Register result_reg = noreg);
624
625 void check_klass_subtype_slow_path_table(Register sub_klass,
626 Register super_klass,
627 Register temp1_reg,
628 Register temp2_reg,
629 Label* L_success = nullptr,
630 Register result_reg = noreg);
631
632 void check_klass_subtype_slow_path(Register sub_klass,
633 Register super_klass,
634 Register temp1_reg,
635 Register temp2_reg,
636 Label* L_success = nullptr,
637 Register result_reg = noreg);
638
639 void lookup_secondary_supers_table_var(Register sub_klass,
640 Register r_super_klass,
641 Register temp1,
642 Register temp2,
643 Register temp3,
644 Register temp4,
645 Register result);
646
647 // If r is valid, return r.
648 // If r is invalid, remove a register r2 from available_regs, add r2
649 // to regs_to_push, then return r2.
650 Register allocate_if_noreg(const Register r,
651 RegSetIterator<Register> &available_regs,
652 RegSet ®s_to_push);
653
654 // Frameless register spills (negative offset from SP)
655 void push_set(RegSet set);
656 void pop_set(RegSet set);
657
658 // Simplified, combined version, good for typical uses.
659 // Falls through on failure.
660 void check_klass_subtype(Register sub_klass,
661 Register super_klass,
662 Register temp1_reg,
663 Register temp2_reg,
664 Label& L_success);
665
666 void repne_scan(Register addr, Register value, Register count, Register scratch);
667
668 // As above, but with a constant super_klass.
669 // The result is in Register result, not the condition codes.
670 void lookup_secondary_supers_table_const(Register r_sub_klass,
671 Register r_super_klass,
672 Register temp1,
673 Register temp2,
674 Register temp3,
675 Register temp4,
676 Register result,
677 u1 super_klass_slot);
678
679 void verify_secondary_supers_table(Register r_sub_klass,
680 Register r_super_klass,
681 Register result,
682 Register temp1,
683 Register temp2,
684 Register temp3);
685
686 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
687 Register r_array_base,
688 Register r_array_index,
689 Register r_bitmap,
690 Register result,
691 Register temp1);
692
693 void clinit_barrier(Register klass,
694 Register thread,
695 Label* L_fast_path = nullptr,
696 Label* L_slow_path = nullptr);
697
698 // Method handle support (JSR 292).
699 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0);
700
701 void push_cont_fastpath();
702 void pop_cont_fastpath();
703 void atomically_flip_locked_state(bool is_unlock, Register obj, Register tmp, Label& failed, int semantics);
704 void fast_lock(Register box, Register obj, Register t1, Register t2, Label& slow);
705 void fast_unlock(Register obj, Register t1, Label& slow);
706
707 // allocation (for C1)
708 void tlab_allocate(
709 Register obj, // result: pointer to object after successful allocation
710 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
711 int con_size_in_bytes, // object size in bytes if known at compile time
712 Register t1, // temp register
713 Label& slow_case // continuation point if fast allocation fails
714 );
715
716 void compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
717 Register tmp1, Register tmp2, Register tmp3);
718
719 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
720 Register tmp1, Register tmp2, Register tmp3);
721
722 // Check if safepoint requested and if so branch
723 void safepoint_poll(Label& slow_path, Register temp, bool at_return, bool in_nmethod);
724 void jump_to_polling_page_return_handler_blob(int safepoint_offset, bool fixed_size = false);
725
726 void resolve_jobject(Register value, Register tmp1, Register tmp2,
727 MacroAssembler::PreservationLevel preservation_level);
728 void resolve_global_jobject(Register value, Register tmp1, Register tmp2,
729 MacroAssembler::PreservationLevel preservation_level);
730
731 // Support for managing the JavaThread pointer (i.e.; the reference to
732 // thread-local information).
733
734 // Support for last Java frame (but use call_VM instead where possible):
735 // access R16_thread->last_Java_sp.
736 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
737 void reset_last_Java_frame(bool check_last_java_sp = true);
738 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, Label* jpc = nullptr);
739
740 // Read vm result from thread: oop_result = R16_thread->result;
741 void get_vm_result_oop(Register oop_result);
742 void get_vm_result_metadata(Register metadata_result);
743
744 static bool needs_explicit_null_check(intptr_t offset);
745 static bool uses_implicit_null_check(void* address);
746
747 // Trap-instruction-based checks.
748 // Range checks can be distinguished from zero checks as they check 32 bit,
749 // zero checks all 64 bits (tw, td).
750 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual);
751 static bool is_trap_null_check(int x) {
752 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) ||
753 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0);
754 }
755
756 inline void trap_ic_miss_check(Register a, Register b);
757 static bool is_trap_ic_miss_check(int x) {
758 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/);
759 }
760
761 // Implicit or explicit null check, jumps to static address exception_entry.
762 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry);
763 inline void null_check(Register a, int offset, Label *Lis_null); // implicit only if Lis_null not provided
764
765 // Access heap oop, handle encoding and GC barriers.
766 // Some GC barriers call C so use needs_frame = true if an extra frame is needed at the current call site.
767 inline void access_store_at(BasicType type, DecoratorSet decorators,
768 Register base, RegisterOrConstant ind_or_offs, Register val,
769 Register tmp1, Register tmp2, Register tmp3,
770 MacroAssembler::PreservationLevel preservation_level);
771 inline void access_load_at(BasicType type, DecoratorSet decorators,
772 Register base, RegisterOrConstant ind_or_offs, Register dst,
773 Register tmp1, Register tmp2,
774 MacroAssembler::PreservationLevel preservation_level, Label *L_handle_null = nullptr);
775
776 public:
777 // Specify tmp1 for better code in certain compressed oops cases. Specify Label to bail out on null oop.
778 // tmp1, tmp2 and needs_frame are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
779 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
780 Register tmp1, Register tmp2,
781 MacroAssembler::PreservationLevel preservation_level,
782 DecoratorSet decorators = 0, Label *L_handle_null = nullptr);
783
784 inline void store_heap_oop(Register d, RegisterOrConstant offs, Register s1,
785 Register tmp1, Register tmp2, Register tmp3,
786 MacroAssembler::PreservationLevel preservation_level, DecoratorSet decorators = 0);
787
788 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong.
789 // src == d allowed.
790 inline Register encode_heap_oop_not_null(Register d, Register src = noreg);
791 inline Register decode_heap_oop_not_null(Register d, Register src = noreg);
792
793 // Null allowed.
794 inline Register encode_heap_oop(Register d, Register src); // Prefer null check in GC barrier!
795 inline void decode_heap_oop(Register d);
796
797 // Load/Store klass oop from klass field. Compress.
798 void load_klass_no_decode(Register dst, Register src);
799 void load_klass(Register dst, Register src);
800 void load_narrow_klass_compact(Register dst, Register src);
801 void cmp_klass(ConditionRegister dst, Register obj, Register klass, Register tmp, Register tmp2);
802 void cmp_klasses_from_objects(ConditionRegister dst, Register obj1, Register obj2, Register tmp1, Register tmp2);
803 void load_klass_check_null(Register dst, Register src, Label* is_null = nullptr);
804 void store_klass(Register dst_oop, Register klass, Register tmp = R0);
805 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified.
806
807 void resolve_oop_handle(Register result, Register tmp1, Register tmp2,
808 MacroAssembler::PreservationLevel preservation_level);
809 void resolve_weak_handle(Register result, Register tmp1, Register tmp2,
810 MacroAssembler::PreservationLevel preservation_level);
811 void load_method_holder(Register holder, Register method);
812
813 void decode_klass_not_null(Register dst, Register src = noreg);
814 Register encode_klass_not_null(Register dst, Register src = noreg);
815
816 // SIGTRAP-based range checks for arrays.
817 inline void trap_range_check_l(Register a, Register b);
818 inline void trap_range_check_l(Register a, int si16);
819 static bool is_trap_range_check_l(int x) {
820 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
821 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) );
822 }
823 inline void trap_range_check_le(Register a, int si16);
824 static bool is_trap_range_check_le(int x) {
825 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/);
826 }
827 inline void trap_range_check_g(Register a, int si16);
828 static bool is_trap_range_check_g(int x) {
829 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/);
830 }
831 inline void trap_range_check_ge(Register a, Register b);
832 inline void trap_range_check_ge(Register a, int si16);
833 static bool is_trap_range_check_ge(int x) {
834 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
835 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) );
836 }
837 static bool is_trap_range_check(int x) {
838 return is_trap_range_check_l(x) || is_trap_range_check_le(x) ||
839 is_trap_range_check_g(x) || is_trap_range_check_ge(x);
840 }
841
842 void clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp = R0, int offset = 0);
843 void clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp = R0);
844 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0, long const_cnt = -1);
845
846 // Emitters for BigInteger.multiplyToLen intrinsic.
847 inline void multiply64(Register dest_hi, Register dest_lo,
848 Register x, Register y);
849 void add2_with_carry(Register dest_hi, Register dest_lo,
850 Register src1, Register src2);
851 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
852 Register y, Register y_idx, Register z,
853 Register carry, Register product_high, Register product,
854 Register idx, Register kdx, Register tmp);
855 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
856 Register yz_idx, Register idx, Register carry,
857 Register product_high, Register product, Register tmp,
858 int offset);
859 void multiply_128_x_128_loop(Register x_xstart,
860 Register y, Register z,
861 Register yz_idx, Register idx, Register carry,
862 Register product_high, Register product,
863 Register carry2, Register tmp);
864 void muladd(Register out, Register in, Register offset, Register len, Register k,
865 Register tmp1, Register tmp2, Register carry);
866 void multiply_to_len(Register x, Register xlen,
867 Register y, Register ylen,
868 Register z,
869 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
870 Register tmp6, Register tmp7, Register tmp8, Register tmp9, Register tmp10,
871 Register tmp11, Register tmp12, Register tmp13);
872
873 // non-atomic 64-bit memory increment by simm16
874 void increment_mem64(Register base, RegisterOrConstant ind_or_offs, int val, Register tmp);
875
876 // Bytecode profiling (tmp2 = noreg is allowed, but then recv is killed)
877 void profile_receiver_type(Register recv, Register mdp, int mdp_offset, Register tmp1, Register tmp2);
878
879 // Emitters for CRC32 calculation.
880 // A note on invertCRC:
881 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
882 // CRC32 holds it's current crc value in the externally visible representation.
883 // CRC32C holds it's current crc value in internal format, ready for updating.
884 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
885 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
886 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
887 void load_reverse_32(Register dst, Register src);
888 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3);
889 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp);
890 void update_byte_crc32(Register crc, Register val, Register table);
891 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
892 Register data, bool loopAlignment);
893 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
894 Register t0, Register t1, Register t2, Register t3,
895 Register tc0, Register tc1, Register tc2, Register tc3);
896 void kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants,
897 Register t0, Register t1, Register t2, Register t3, Register t4,
898 Register t5, Register t6, bool invertCRC);
899 void kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants,
900 Register t0, Register t1, Register t2, Register t3, Register t4,
901 Register t5, Register t6);
902 // Version which internally decides what to use.
903 void crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2,
904 Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c);
905
906 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
907 bool invertCRC);
908
909 // SHA-2 auxiliary functions and public interfaces
910 private:
911 void sha256_deque(const VectorRegister src,
912 const VectorRegister dst1, const VectorRegister dst2, const VectorRegister dst3);
913 void sha256_load_h_vec(const VectorRegister a, const VectorRegister e, const Register hptr);
914 void sha256_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
915 void sha256_load_w_plus_k_vec(const Register buf_in, const VectorRegister* ws,
916 const int total_ws, const Register k, const VectorRegister* kpws,
917 const int total_kpws);
918 void sha256_calc_4w(const VectorRegister w0, const VectorRegister w1,
919 const VectorRegister w2, const VectorRegister w3, const VectorRegister kpw0,
920 const VectorRegister kpw1, const VectorRegister kpw2, const VectorRegister kpw3,
921 const Register j, const Register k);
922 void sha256_update_sha_state(const VectorRegister a, const VectorRegister b,
923 const VectorRegister c, const VectorRegister d, const VectorRegister e,
924 const VectorRegister f, const VectorRegister g, const VectorRegister h,
925 const Register hptr);
926
927 void sha512_load_w_vec(const Register buf_in, const VectorRegister* ws, const int total_ws);
928 void sha512_update_sha_state(const Register state, const VectorRegister* hs, const int total_hs);
929 void sha512_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
930 void sha512_load_h_vec(const Register state, const VectorRegister* hs, const int total_hs);
931 void sha512_calc_2w(const VectorRegister w0, const VectorRegister w1,
932 const VectorRegister w2, const VectorRegister w3,
933 const VectorRegister w4, const VectorRegister w5,
934 const VectorRegister w6, const VectorRegister w7,
935 const VectorRegister kpw0, const VectorRegister kpw1, const Register j,
936 const VectorRegister vRb, const Register k);
937
938 public:
939 void sha256(bool multi_block);
940 void sha512(bool multi_block);
941
942 void cache_wb(Address line);
943 void cache_wbsync(bool is_presync);
944
945 //
946 // Debugging
947 //
948
949 // assert on cr0
950 enum AsmAssertCond {
951 eq,
952 ne,
953 ge,
954 gt,
955 lt,
956 le
957 };
958 void asm_assert(AsmAssertCond cond, const char* msg) PRODUCT_RETURN;
959 void asm_assert_eq(const char* msg) { asm_assert(eq, msg); }
960 void asm_assert_ne(const char* msg) { asm_assert(ne, msg); }
961
962 private:
963 void asm_assert_mems_zero(AsmAssertCond cond, int size, int mem_offset, Register mem_base,
964 const char* msg) NOT_DEBUG_RETURN;
965
966 public:
967
968 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg) {
969 asm_assert_mems_zero(eq, 8, mem_offset, mem_base, msg);
970 }
971 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg) {
972 asm_assert_mems_zero(ne, 8, mem_offset, mem_base, msg);
973 }
974
975 // Calls verify_oop. If UseCompressedOops is on, decodes the oop.
976 // Preserves reg.
977 void verify_coop(Register reg, const char*);
978 // Emit code to verify that reg contains a valid oop if +VerifyOops is set.
979 void verify_oop(Register reg, const char* s = "broken oop");
980 void verify_oop_addr(RegisterOrConstant offs, Register base, const char* s = "contains broken oop");
981
982 // TODO: verify method and klass metadata (compare against vptr?)
983 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
984 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
985
986 // Convenience method returning function entry. For the ELFv1 case
987 // creates function descriptor at the current address and returns
988 // the pointer to it. For the ELFv2 case returns the current address.
989 inline address function_entry();
990
991 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
992 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
993
994 private:
995 void stop(int type, const char* msg);
996
997 public:
998 enum {
999 stop_stop = 0,
1000 stop_untested = 1,
1001 stop_unimplemented = 2,
1002 stop_shouldnotreachhere = 3,
1003 stop_msg_present = -0x8000
1004 };
1005
1006 // Prints msg, dumps registers and stops execution.
1007 void stop (const char* msg = nullptr) { stop(stop_stop, msg); }
1008 void untested (const char* msg = nullptr) { stop(stop_untested, msg); }
1009 void unimplemented (const char* msg = nullptr) { stop(stop_unimplemented, msg); }
1010 void should_not_reach_here(const char* msg = nullptr) { stop(stop_shouldnotreachhere, msg); }
1011
1012 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN;
1013 };
1014
1015 #endif // CPU_PPC_MACROASSEMBLER_PPC_HPP