1 /*
2 * Copyright (c) 2002, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2026 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/accessDecorators.hpp"
31 #include "utilities/macros.hpp"
32
33 // MacroAssembler extends Assembler by a few frequently used macros.
34
35 class ciTypeArray;
36 class OopMap;
37 class ciInlineKlass;
38 class SigEntry;
39 class VMRegPair;
40
41 class MacroAssembler: public Assembler {
42 public:
43 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
44
45 // Indicates whether and, if so, which registers must be preserved when calling runtime code.
46 enum PreservationLevel {
47 PRESERVATION_NONE,
48 PRESERVATION_FRAME_LR,
49 PRESERVATION_FRAME_LR_GP_REGS,
50 PRESERVATION_FRAME_LR_GP_FP_REGS
51 };
52
53 //
54 // Optimized instruction emitters
55 //
56
57 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; }
58 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); }
59
60 // load d = *[a+si31]
61 // Emits several instructions if the offset is not encodable in one instruction.
62 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop);
63 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop);
64 inline static bool is_ld_largeoffset(address a);
65 inline static int get_ld_largeoffset_offset(address a);
66
67 inline void round_to(Register r, int modulus);
68
69 // Load/store with type given by parameter.
70 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed);
71 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes);
72
73 // Move register if destination register and target register are different
74 inline void mr_if_needed(Register rd, Register rs, bool allow_invalid = false);
75 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs);
76
77 // Memory barriers.
78 inline void membar(int bits);
79 inline void release();
80 inline void acquire();
81 inline void fence();
82
83 // nop padding
84 void align(int modulus, int max = 252, int rem = 0);
85
86 // Align prefix opcode to make sure it's not on the last word of a
87 // 64-byte block.
88 //
89 // Note: do not call align_prefix() in a .ad file (e.g. ppc.ad). Instead
90 // add ins_alignment(2) to the instruct definition and implement the
91 // compute_padding() method of the instruct node to use
92 // compute_prefix_padding(). See loadConI32Node::compute_padding() in
93 // ppc.ad for an example.
94 void align_prefix();
95
96 //
97 // Constants, loading constants, TOC support
98 //
99
100 // Address of the global TOC.
101 inline static address global_toc();
102 // Offset of given address to the global TOC.
103 inline static int offset_to_global_toc(const address addr);
104
105 // Address of TOC of the current method.
106 inline address method_toc();
107 // Offset of given address to TOC of the current method.
108 inline int offset_to_method_toc(const address addr);
109
110 // Global TOC.
111 void calculate_address_from_global_toc(Register dst, address addr,
112 bool hi16 = true, bool lo16 = true,
113 bool add_relocation = true, bool emit_dummy_addr = false,
114 bool add_addr_to_reloc = true);
115 void calculate_address_from_global_toc(Register dst, Label& addr,
116 bool hi16 = true, bool lo16 = true,
117 bool add_relocation = true, bool emit_dummy_addr = false) {
118 calculate_address_from_global_toc(dst, target(addr), hi16, lo16, add_relocation, emit_dummy_addr, false);
119 }
120 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) {
121 calculate_address_from_global_toc(dst, addr, true, false);
122 };
123 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) {
124 calculate_address_from_global_toc(dst, addr, false, true);
125 };
126
127 inline static bool is_calculate_address_from_global_toc_at(address a, address bound);
128 // Returns address of first instruction in sequence.
129 static address patch_calculate_address_from_global_toc_at(address a, address bound, address addr);
130 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr);
131
132 #ifdef _LP64
133 // Patch narrow oop constant.
134 inline static bool is_set_narrow_oop(address a, address bound);
135 // Returns address of first instruction in sequence.
136 static address patch_set_narrow_oop(address a, address bound, narrowOop data);
137 static narrowOop get_narrow_oop(address a, address bound);
138 #endif
139
140 inline static bool is_load_const_at(address a);
141
142 // Emits an oop const to the constant pool, loads the constant, and
143 // sets a relocation info with address current_pc.
144 // Returns true if successful.
145 bool load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc, bool fixed_size = false);
146
147 static bool is_load_const_from_method_toc_at(address a);
148 static int get_offset_of_load_const_from_method_toc_at(address a);
149
150 // Get the 64 bit constant from a `load_const' sequence.
151 static long get_const(address load_const);
152
153 // Patch the 64 bit constant of a `load_const' sequence. This is a
154 // low level procedure. It neither flushes the instruction cache nor
155 // is it atomic.
156 static void patch_const(address load_const, long x);
157
158 // Metadata in code that we have to keep track of.
159 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
160 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
161 // Oops used directly in compiled code are stored in the constant pool,
162 // and loaded from there.
163 // Allocate new entry for oop in constant pool. Generate relocation.
164 AddressLiteral allocate_oop_address(jobject obj);
165 // Find oop obj in constant pool. Return relocation with it's index.
166 AddressLiteral constant_oop_address(jobject obj);
167
168 // Find oop in constant pool and emit instructions to load it.
169 // Uses constant_oop_address.
170 inline void set_oop_constant(jobject obj, Register d);
171 // Same as load_address.
172 inline void set_oop (AddressLiteral obj_addr, Register d);
173
174 //
175 // branch, jump
176 //
177 // set dst to -1, 0, +1 as follows: if CR0bi is "greater than", dst is set to 1,
178 // if CR0bi is "equal", dst is set to 0, otherwise it's set to -1.
179 void inline set_cmp3(Register dst);
180 // set dst to (treat_unordered_like_less ? -1 : +1)
181 void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
182 // Branch-free implementation to convert !=0 to 1.
183 void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
184 // Convert between half precision float encoded into a short and a float in a FloatRegister.
185 void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
186 void inline hf2f(FloatRegister dst, Register src);
187
188 inline void pd_patch_instruction(address branch, address target, const char* file, int line);
189 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
190
191 // Conditional far branch for destinations encodable in 24+2 bits.
192 // Same interface as bc, e.g. no inverse boint-field.
193 enum {
194 bc_far_optimize_not = 0,
195 bc_far_optimize_on_relocate = 1
196 };
197 // optimize: flag for telling the conditional far branch to optimize
198 // itself when relocated.
199 void bc_far(int boint, int biint, Label& dest, int optimize);
200 void bc_far_optimized(int boint, int biint, Label& dest); // 1 or 2 instructions
201 // Relocation of conditional far branches.
202 static bool is_bc_far_at(address instruction_addr);
203 static address get_dest_of_bc_far_at(address instruction_addr);
204 static void set_dest_of_bc_far_at(address instruction_addr, address dest);
205 private:
206 static bool inline is_bc_far_variant1_at(address instruction_addr);
207 static bool inline is_bc_far_variant2_at(address instruction_addr);
208 static bool inline is_bc_far_variant3_at(address instruction_addr);
209 public:
210
211 // Convenience bc_far versions.
212 inline void blt_far(ConditionRegister crx, Label& L, int optimize);
213 inline void bgt_far(ConditionRegister crx, Label& L, int optimize);
214 inline void beq_far(ConditionRegister crx, Label& L, int optimize);
215 inline void bso_far(ConditionRegister crx, Label& L, int optimize);
216 inline void bge_far(ConditionRegister crx, Label& L, int optimize);
217 inline void ble_far(ConditionRegister crx, Label& L, int optimize);
218 inline void bne_far(ConditionRegister crx, Label& L, int optimize);
219 inline void bns_far(ConditionRegister crx, Label& L, int optimize);
220
221 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump.
222 private:
223 enum {
224 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/),
225 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord,
226 bxx64_patchable_ret_addr_offset = bxx64_patchable_size
227 };
228 void bxx64_patchable(address target, relocInfo::relocType rt, bool link);
229 static bool is_bxx64_patchable_at( address instruction_addr, bool link);
230 // Does the instruction use a pc-relative encoding of the destination?
231 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link);
232 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link);
233 // Load destination relative to global toc.
234 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link);
235 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link);
236 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link);
237 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link);
238
239 public:
240 // call
241 enum {
242 bl64_patchable_instruction_count = bxx64_patchable_instruction_count,
243 bl64_patchable_size = bxx64_patchable_size,
244 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset
245 };
246 inline void bl64_patchable(address target, relocInfo::relocType rt) {
247 bxx64_patchable(target, rt, /*link=*/true);
248 }
249 inline static bool is_bl64_patchable_at(address instruction_addr) {
250 return is_bxx64_patchable_at(instruction_addr, /*link=*/true);
251 }
252 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) {
253 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true);
254 }
255 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) {
256 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true);
257 }
258 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) {
259 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true);
260 }
261 // jump
262 enum {
263 b64_patchable_instruction_count = bxx64_patchable_instruction_count,
264 b64_patchable_size = bxx64_patchable_size,
265 };
266 inline void b64_patchable(address target, relocInfo::relocType rt) {
267 bxx64_patchable(target, rt, /*link=*/false);
268 }
269 inline static bool is_b64_patchable_at(address instruction_addr) {
270 return is_bxx64_patchable_at(instruction_addr, /*link=*/false);
271 }
272 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) {
273 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false);
274 }
275 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) {
276 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false);
277 }
278 inline static address get_dest_of_b64_patchable_at(address instruction_addr) {
279 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false);
280 }
281
282 //
283 // Support for frame handling
284 //
285
286 // some ABI-related functions
287
288 // Clobbers all volatile, (non-floating-point) general-purpose registers for debugging purposes.
289 // This is especially useful for making calls to the JRT in places in which this hasn't been done before;
290 // e.g. with the introduction of LRBs (load reference barriers) for concurrent garbage collection.
291 void clobber_volatile_gprs(Register excluded_register = noreg) NOT_DEBUG_RETURN;
292 // Load bad values into registers that are nonvolatile according to the ABI except R16_thread and R29_TOC.
293 // This is done after vthread preemption and before vthread resume.
294 void clobber_nonvolatile_registers() NOT_DEBUG_RETURN;
295 void clobber_carg_stack_slots(Register tmp);
296
297 int save_nonvolatile_registers_size(bool include_fp_regs, bool include_vector_regs) {
298 int size = (32 - 14) * 8; // GP regs
299 if (include_fp_regs) size += (32 - 14) * 8;
300 if (include_vector_regs) size += (32 - 20) * 16;
301 return size;
302 }
303 void save_nonvolatile_registers( Register dst_base, int offset, bool include_fp_regs, bool include_vector_regs);
304 void restore_nonvolatile_registers(Register src_base, int offset, bool include_fp_regs, bool include_vector_regs);
305
306 enum {
307 num_volatile_gp_regs = 11,
308 num_volatile_fp_regs = 14,
309 num_volatile_regs = num_volatile_gp_regs + num_volatile_fp_regs
310 };
311
312 void save_volatile_gprs( Register dst_base, int offset,
313 bool include_fp_regs = true, bool include_R3_RET_reg = true);
314 void restore_volatile_gprs(Register src_base, int offset,
315 bool include_fp_regs = true, bool include_R3_RET_reg = true);
316 void save_LR(Register tmp);
317 void restore_LR(Register tmp);
318 void save_LR_CR(Register tmp); // tmp contains LR on return.
319 void restore_LR_CR(Register tmp);
320
321 // Get current PC using bl-next-instruction trick.
322 address get_PC_trash_LR(Register result);
323
324 // Resize current frame either relatively wrt to current SP or absolute.
325 void resize_frame(Register offset, Register tmp);
326 void resize_frame(int offset, Register tmp);
327 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2);
328
329 // Push a frame of size bytes.
330 void push_frame(Register bytes, Register tmp);
331
332 // Push a frame of size `bytes'. No abi space provided.
333 void push_frame(unsigned int bytes, Register tmp);
334
335 // Push a frame of size `bytes' plus native_abi_reg_args on top.
336 void push_frame_reg_args(unsigned int bytes, Register tmp);
337
338 // pop current C frame
339 void pop_frame();
340
341 //
342 // Calls
343 //
344
345 private:
346 address _last_calls_return_pc;
347
348 #if defined(ABI_ELFv2)
349 // Generic version of a call to C function.
350 // Updates and returns _last_calls_return_pc.
351 address branch_to(Register function_entry, bool and_link);
352 #else
353 // Generic version of a call to C function via a function descriptor
354 // with variable support for C calling conventions (TOC, ENV, etc.).
355 // updates and returns _last_calls_return_pc.
356 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
357 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee);
358 #endif
359
360 public:
361
362 // Get the pc where the last call will return to. returns _last_calls_return_pc.
363 inline address last_calls_return_pc();
364
365 #if defined(ABI_ELFv2)
366 // Call a C function via a function descriptor and use full C
367 // calling conventions. Updates and returns _last_calls_return_pc.
368 address call_c(Register function_entry);
369 // For tail calls: only branch, don't link, so callee returns to caller of this function.
370 address call_c_and_return_to_caller(Register function_entry);
371 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none);
372 #else
373 // Call a C function via a function descriptor and use full C
374 // calling conventions. Updates and returns _last_calls_return_pc.
375 address call_c(Register function_descriptor);
376 // For tail calls: only branch, don't link, so callee returns to caller of this function.
377 address call_c_and_return_to_caller(Register function_descriptor);
378 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt);
379 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none) {
380 return call_c((const FunctionDescriptor*)function_entry, rt);
381 }
382 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt,
383 Register toc);
384 #endif
385
386 // CompiledIC call
387 bool ic_call(Register Rmethod_toc,
388 address target,
389 jint method_index = 0,
390 bool scratch_emit = false,
391 bool fixed_size = false);
392 static int ic_check_size();
393 int ic_check(int end_alignment);
394
395 enum { trampoline_stub_size = 6 * 4 };
396 address trampoline_call(AddressLiteral target,
397 Register Rmethod_toc = noreg,
398 bool scratch_emit = false);
399
400 protected:
401
402 // It is imperative that all calls into the VM are handled via the
403 // call_VM macros. They make sure that the stack linkage is setup
404 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
405 // while call_VM_leaf's correspond to LEAF entry points.
406 //
407 // This is the base routine called by the different versions of
408 // call_VM. The interpreter may customize this version by overriding
409 // it for its purposes (e.g., to save/restore additional registers
410 // when doing a VM call).
411 //
412 // If no last_java_sp is specified (noreg) then SP will be used instead.
413 virtual void call_VM_base(
414 // where an oop-result ends up if any; use noreg otherwise
415 Register oop_result,
416 // to set up last_Java_frame in stubs; use noreg otherwise
417 Register last_java_sp,
418 // the entry point
419 address entry_point,
420 // flag which indicates if exception should be checked
421 bool check_exception = true,
422 Label* last_java_pc = nullptr
423 );
424
425 // Support for VM calls. This is the base routine called by the
426 // different versions of call_VM_leaf. The interpreter may customize
427 // this version by overriding it for its purposes (e.g., to
428 // save/restore additional registers when doing a VM call).
429 void call_VM_leaf_base(address entry_point);
430
431 public:
432 // Call into the VM.
433 // Passes the thread pointer (in R3_ARG1) as a prepended argument.
434 // Makes sure oop return values are visible to the GC.
435 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true, Label* last_java_pc = nullptr);
436 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
437 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
438 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true);
439 void call_VM_leaf(address entry_point);
440 void call_VM_leaf(address entry_point, Register arg_1);
441 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
442 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
443
444 // Call a stub function via a function descriptor, but don't save
445 // TOC before call, don't setup TOC and ENV for call, and don't
446 // restore TOC after call. Updates and returns _last_calls_return_pc.
447 inline address call_stub(Register function_entry);
448 inline void call_stub_and_return_to(Register function_entry, Register return_pc);
449
450 void post_call_nop();
451 static bool is_post_call_nop(int instr_bits) {
452 const uint32_t nineth_bit = opp_u_field(1, 9, 9);
453 const uint32_t opcode_mask = 0b111110 << OPCODE_SHIFT;
454 const uint32_t pcn_mask = opcode_mask | nineth_bit;
455 return (instr_bits & pcn_mask) == (Assembler::CMPLI_OPCODE | nineth_bit);
456 }
457
458 //
459 // Java utilities
460 //
461
462 // Read from the polling page, its address is already in a register.
463 inline void load_from_polling_page(Register polling_page_address, int offset = 0);
464 // Check whether instruction is a read access to the polling page
465 // which was emitted by load_from_polling_page(..).
466 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be nullptr*/,
467 address* polling_address_ptr = nullptr);
468
469 // Support for null-checks
470 //
471 // Generates code that causes a null OS exception if the content of reg is null.
472 // If the accessed location is M[reg + offset] and the offset is known, provide the
473 // offset. No explicit code generation is needed if the offset is within a certain
474 // range (0 <= offset <= page_size).
475
476 // Stack overflow checking
477 void bang_stack_with_offset(int offset);
478
479 // If instruction is a stack bang of the form ld, stdu, or
480 // stdux, return the banged address. Otherwise, return 0.
481 static address get_stack_bang_address(int instruction, void* ucontext);
482
483 // Check for reserved stack access in method being exited. If the reserved
484 // stack area was accessed, protect it again and throw StackOverflowError.
485 void reserved_stack_check(Register return_pc);
486
487 // Atomics
488 // CmpxchgX sets condition register to cmpX(current, compare).
489 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
490 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
491 static inline bool cmpxchgx_hint_acquire_lock() { return true; }
492 // The stxcx will probably not be succeeded by a releasing store.
493 static inline bool cmpxchgx_hint_release_lock() { return false; }
494 static inline bool cmpxchgx_hint_atomic_update() { return false; }
495
496 // Cmpxchg semantics
497 enum {
498 MemBarNone = 0,
499 MemBarRel = 1,
500 MemBarAcq = 2,
501 MemBarFenceAfter = 4 // use powers of 2
502 };
503 private:
504 // Helper functions for word/sub-word atomics.
505 void atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value,
506 Register addr_base, Register tmp1, Register tmp2, Register tmp3,
507 bool cmpxchgx_hint, bool is_add, int size);
508 void cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value,
509 RegisterOrConstant compare_value, Register exchange_value,
510 Register addr_base,Label &retry, Label &failed, bool cmpxchgx_hint, int size);
511 void cmpxchg_generic(ConditionRegister flag, Register dest_current_value,
512 RegisterOrConstant compare_value, Register exchange_value,
513 Register addr_base, int semantics, bool cmpxchgx_hint, Register int_flag_success,
514 Label* failed_ext, bool contention_hint, bool weak, int size);
515 public:
516 // Temps and addr_base are killed if processor does not support Power 8 instructions.
517 // Result will be sign extended.
518 void getandsetb(Register dest_current_value, Register exchange_value, Register addr_base,
519 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
520 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 1);
521 }
522 // Temps and addr_base are killed if processor does not support Power 8 instructions.
523 // Result will be sign extended.
524 void getandseth(Register dest_current_value, Register exchange_value, Register addr_base,
525 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
526 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 2);
527 }
528 void getandsetw(Register dest_current_value, Register exchange_value, Register addr_base,
529 bool cmpxchgx_hint) {
530 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, noreg, noreg, noreg, cmpxchgx_hint, false, 4);
531 }
532 void getandsetd(Register dest_current_value, Register exchange_value, Register addr_base,
533 bool cmpxchgx_hint);
534 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
535 // Result will be sign extended.
536 void getandaddb(Register dest_current_value, Register inc_value, Register addr_base,
537 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
538 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 1);
539 }
540 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
541 // Result will be sign extended.
542 void getandaddh(Register dest_current_value, Register inc_value, Register addr_base,
543 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
544 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 2);
545 }
546 void getandaddw(Register dest_current_value, Register inc_value, Register addr_base,
547 Register tmp1, bool cmpxchgx_hint) {
548 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, noreg, noreg, cmpxchgx_hint, true, 4);
549 }
550 void getandaddd(Register dest_current_value, Register exchange_value, Register addr_base,
551 Register tmp, bool cmpxchgx_hint);
552 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
553 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
554 void cmpxchgb(ConditionRegister flag, Register dest_current_value,
555 RegisterOrConstant compare_value, Register exchange_value,
556 Register addr_base, int semantics, bool cmpxchgx_hint = false,
557 Register int_flag_success = noreg, Label* failed = nullptr,
558 bool contention_hint = false, bool weak = false) {
559 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, semantics,
560 cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 1);
561 }
562 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
563 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
564 void cmpxchgh(ConditionRegister flag, Register dest_current_value,
565 RegisterOrConstant compare_value, Register exchange_value,
566 Register addr_base, int semantics, bool cmpxchgx_hint = false,
567 Register int_flag_success = noreg, Label* failed = nullptr,
568 bool contention_hint = false, bool weak = false) {
569 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
570 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 2);
571 }
572 void cmpxchgw(ConditionRegister flag, Register dest_current_value,
573 RegisterOrConstant compare_value, Register exchange_value,
574 Register addr_base,
575 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
576 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
577 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
578 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 4);
579 }
580 void cmpxchgd(ConditionRegister flag, Register dest_current_value,
581 RegisterOrConstant compare_value, Register exchange_value,
582 Register addr_base,
583 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
584 Label* failed = nullptr, bool contention_hint = false, bool weak = false);
585
586 // interface method calling
587 void lookup_interface_method(Register recv_klass,
588 Register intf_klass,
589 RegisterOrConstant itable_index,
590 Register method_result,
591 Register temp_reg, Register temp2_reg,
592 Label& no_such_interface,
593 bool return_method = true);
594
595 // virtual method calling
596 void lookup_virtual_method(Register recv_klass,
597 RegisterOrConstant vtable_index,
598 Register method_result);
599
600 // Test sub_klass against super_klass, with fast and slow paths.
601
602 // The fast path produces a tri-state answer: yes / no / maybe-slow.
603 // One of the three labels can be null, meaning take the fall-through.
604 // If super_check_offset is -1, the value is loaded up from super_klass.
605 // No registers are killed, except temp_reg and temp2_reg.
606 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
607 void check_klass_subtype_fast_path(Register sub_klass,
608 Register super_klass,
609 Register temp1_reg,
610 Register temp2_reg,
611 Label* L_success,
612 Label* L_failure,
613 Label* L_slow_path = nullptr, // default fall through
614 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
615
616 // The rest of the type check; must be wired to a corresponding fast path.
617 // It does not repeat the fast path logic, so don't use it standalone.
618 // The temp_reg can be noreg, if no temps are available.
619 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
620 // Updates the sub's secondary super cache as necessary.
621 void check_klass_subtype_slow_path_linear(Register sub_klass,
622 Register super_klass,
623 Register temp1_reg,
624 Register temp2_reg,
625 Label* L_success = nullptr,
626 Register result_reg = noreg);
627
628 void check_klass_subtype_slow_path_table(Register sub_klass,
629 Register super_klass,
630 Register temp1_reg,
631 Register temp2_reg,
632 Label* L_success = nullptr,
633 Register result_reg = noreg);
634
635 void check_klass_subtype_slow_path(Register sub_klass,
636 Register super_klass,
637 Register temp1_reg,
638 Register temp2_reg,
639 Label* L_success = nullptr,
640 Register result_reg = noreg);
641
642 void lookup_secondary_supers_table_var(Register sub_klass,
643 Register r_super_klass,
644 Register temp1,
645 Register temp2,
646 Register temp3,
647 Register temp4,
648 Register result);
649
650 // If r is valid, return r.
651 // If r is invalid, remove a register r2 from available_regs, add r2
652 // to regs_to_push, then return r2.
653 Register allocate_if_noreg(const Register r,
654 RegSetIterator<Register> &available_regs,
655 RegSet ®s_to_push);
656
657 // Frameless register spills (negative offset from SP)
658 void push_set(RegSet set);
659 void pop_set(RegSet set);
660
661 // Simplified, combined version, good for typical uses.
662 // Falls through on failure.
663 void check_klass_subtype(Register sub_klass,
664 Register super_klass,
665 Register temp1_reg,
666 Register temp2_reg,
667 Label& L_success);
668
669 void repne_scan(Register addr, Register value, Register count, Register scratch);
670
671 // As above, but with a constant super_klass.
672 // The result is in Register result, not the condition codes.
673 void lookup_secondary_supers_table_const(Register r_sub_klass,
674 Register r_super_klass,
675 Register temp1,
676 Register temp2,
677 Register temp3,
678 Register temp4,
679 Register result,
680 u1 super_klass_slot);
681
682 void verify_secondary_supers_table(Register r_sub_klass,
683 Register r_super_klass,
684 Register result,
685 Register temp1,
686 Register temp2,
687 Register temp3);
688
689 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
690 Register r_array_base,
691 Register r_array_index,
692 Register r_bitmap,
693 Register result,
694 Register temp1);
695
696 void clinit_barrier(Register klass,
697 Register thread,
698 Label* L_fast_path = nullptr,
699 Label* L_slow_path = nullptr);
700
701 // Method handle support (JSR 292).
702 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0);
703
704 void push_cont_fastpath();
705 void pop_cont_fastpath();
706 void atomically_flip_locked_state(bool is_unlock, Register obj, Register tmp, Label& failed, int semantics);
707 void fast_lock(Register box, Register obj, Register t1, Register t2, Label& slow);
708 void fast_unlock(Register obj, Register t1, Label& slow);
709
710 // allocation (for C1)
711 void tlab_allocate(
712 Register obj, // result: pointer to object after successful allocation
713 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
714 int con_size_in_bytes, // object size in bytes if known at compile time
715 Register t1, // temp register
716 Label& slow_case // continuation point if fast allocation fails
717 );
718
719 void compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
720 Register tmp1, Register tmp2, Register tmp3);
721
722 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
723 Register tmp1, Register tmp2, Register tmp3);
724
725 // Check if safepoint requested and if so branch
726 void safepoint_poll(Label& slow_path, Register temp, bool at_return, bool in_nmethod);
727 void jump_to_polling_page_return_handler_blob(int safepoint_offset, bool fixed_size = false);
728
729 void resolve_jobject(Register value, Register tmp1, Register tmp2,
730 MacroAssembler::PreservationLevel preservation_level);
731 void resolve_global_jobject(Register value, Register tmp1, Register tmp2,
732 MacroAssembler::PreservationLevel preservation_level);
733
734 // Support for managing the JavaThread pointer (i.e.; the reference to
735 // thread-local information).
736
737 // Support for last Java frame (but use call_VM instead where possible):
738 // access R16_thread->last_Java_sp.
739 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
740 void reset_last_Java_frame(bool check_last_java_sp = true);
741 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, Label* jpc = nullptr);
742
743 // Read vm result from thread: oop_result = R16_thread->result;
744 void get_vm_result_oop(Register oop_result);
745 void get_vm_result_metadata(Register metadata_result);
746
747 static bool needs_explicit_null_check(intptr_t offset);
748 static bool uses_implicit_null_check(void* address);
749
750 // Trap-instruction-based checks.
751 // Range checks can be distinguished from zero checks as they check 32 bit,
752 // zero checks all 64 bits (tw, td).
753 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual);
754 static bool is_trap_null_check(int x) {
755 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) ||
756 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0);
757 }
758
759 inline void trap_ic_miss_check(Register a, Register b);
760 static bool is_trap_ic_miss_check(int x) {
761 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/);
762 }
763
764 // Implicit or explicit null check, jumps to static address exception_entry.
765 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry);
766 inline void null_check(Register a, int offset, Label *Lis_null); // implicit only if Lis_null not provided
767
768 // Access heap oop, handle encoding and GC barriers.
769 // Some GC barriers call C so use needs_frame = true if an extra frame is needed at the current call site.
770 inline void access_store_at(BasicType type, DecoratorSet decorators,
771 Register base, RegisterOrConstant ind_or_offs, Register val,
772 Register tmp1, Register tmp2, Register tmp3,
773 MacroAssembler::PreservationLevel preservation_level);
774 inline void access_load_at(BasicType type, DecoratorSet decorators,
775 Register base, RegisterOrConstant ind_or_offs, Register dst,
776 Register tmp1, Register tmp2,
777 MacroAssembler::PreservationLevel preservation_level, Label *L_handle_null = nullptr);
778
779 public:
780 // Specify tmp1 for better code in certain compressed oops cases. Specify Label to bail out on null oop.
781 // tmp1, tmp2 and needs_frame are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
782 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
783 Register tmp1, Register tmp2,
784 MacroAssembler::PreservationLevel preservation_level,
785 DecoratorSet decorators = 0, Label *L_handle_null = nullptr);
786
787 inline void store_heap_oop(Register d, RegisterOrConstant offs, Register s1,
788 Register tmp1, Register tmp2, Register tmp3,
789 MacroAssembler::PreservationLevel preservation_level, DecoratorSet decorators = 0);
790
791 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong.
792 // src == d allowed.
793 inline Register encode_heap_oop_not_null(Register d, Register src = noreg);
794 inline Register decode_heap_oop_not_null(Register d, Register src = noreg);
795
796 // Null allowed.
797 inline Register encode_heap_oop(Register d, Register src); // Prefer null check in GC barrier!
798 inline void decode_heap_oop(Register d);
799
800 // Load/Store klass oop from klass field. Compress.
801 void load_klass_no_decode(Register dst, Register src);
802 void load_klass(Register dst, Register src);
803 void load_narrow_klass_compact(Register dst, Register src);
804 void cmp_klass(ConditionRegister dst, Register obj, Register klass, Register tmp, Register tmp2);
805 void cmp_klasses_from_objects(ConditionRegister dst, Register obj1, Register obj2, Register tmp1, Register tmp2);
806 void load_klass_check_null(Register dst, Register src, Label* is_null = nullptr);
807 void store_klass(Register dst_oop, Register klass, Register tmp = R0);
808 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified.
809
810 void resolve_oop_handle(Register result, Register tmp1, Register tmp2,
811 MacroAssembler::PreservationLevel preservation_level);
812 void resolve_weak_handle(Register result, Register tmp1, Register tmp2,
813 MacroAssembler::PreservationLevel preservation_level);
814 void load_method_holder(Register holder, Register method);
815
816 void decode_klass_not_null(Register dst, Register src = noreg);
817 Register encode_klass_not_null(Register dst, Register src = noreg);
818
819 // SIGTRAP-based range checks for arrays.
820 inline void trap_range_check_l(Register a, Register b);
821 inline void trap_range_check_l(Register a, int si16);
822 static bool is_trap_range_check_l(int x) {
823 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
824 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) );
825 }
826 inline void trap_range_check_le(Register a, int si16);
827 static bool is_trap_range_check_le(int x) {
828 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/);
829 }
830 inline void trap_range_check_g(Register a, int si16);
831 static bool is_trap_range_check_g(int x) {
832 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/);
833 }
834 inline void trap_range_check_ge(Register a, Register b);
835 inline void trap_range_check_ge(Register a, int si16);
836 static bool is_trap_range_check_ge(int x) {
837 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
838 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) );
839 }
840 static bool is_trap_range_check(int x) {
841 return is_trap_range_check_l(x) || is_trap_range_check_le(x) ||
842 is_trap_range_check_g(x) || is_trap_range_check_ge(x);
843 }
844
845 void clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp = R0, int offset = 0);
846 void clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp = R0);
847 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0, long const_cnt = -1);
848
849 // Emitters for BigInteger.multiplyToLen intrinsic.
850 inline void multiply64(Register dest_hi, Register dest_lo,
851 Register x, Register y);
852 void add2_with_carry(Register dest_hi, Register dest_lo,
853 Register src1, Register src2);
854 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
855 Register y, Register y_idx, Register z,
856 Register carry, Register product_high, Register product,
857 Register idx, Register kdx, Register tmp);
858 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
859 Register yz_idx, Register idx, Register carry,
860 Register product_high, Register product, Register tmp,
861 int offset);
862 void multiply_128_x_128_loop(Register x_xstart,
863 Register y, Register z,
864 Register yz_idx, Register idx, Register carry,
865 Register product_high, Register product,
866 Register carry2, Register tmp);
867 void muladd(Register out, Register in, Register offset, Register len, Register k,
868 Register tmp1, Register tmp2, Register carry);
869 void multiply_to_len(Register x, Register xlen,
870 Register y, Register ylen,
871 Register z,
872 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
873 Register tmp6, Register tmp7, Register tmp8, Register tmp9, Register tmp10,
874 Register tmp11, Register tmp12, Register tmp13);
875
876 // non-atomic 64-bit memory increment by simm16
877 void increment_mem64(Register base, RegisterOrConstant ind_or_offs, int val, Register tmp);
878
879 // Bytecode profiling (tmp2 = noreg is allowed, but then recv is killed)
880 void profile_receiver_type(Register recv, Register mdp, int mdp_offset, Register tmp1, Register tmp2);
881
882 // Emitters for CRC32 calculation.
883 // A note on invertCRC:
884 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
885 // CRC32 holds it's current crc value in the externally visible representation.
886 // CRC32C holds it's current crc value in internal format, ready for updating.
887 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
888 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
889 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
890 void load_reverse_32(Register dst, Register src);
891 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3);
892 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp);
893 void update_byte_crc32(Register crc, Register val, Register table);
894 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
895 Register data, bool loopAlignment);
896 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
897 Register t0, Register t1, Register t2, Register t3,
898 Register tc0, Register tc1, Register tc2, Register tc3);
899 void kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants,
900 Register t0, Register t1, Register t2, Register t3, Register t4,
901 Register t5, Register t6, bool invertCRC);
902 void kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants,
903 Register t0, Register t1, Register t2, Register t3, Register t4,
904 Register t5, Register t6);
905 // Version which internally decides what to use.
906 void crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2,
907 Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c);
908
909 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
910 bool invertCRC);
911
912 // SHA-2 auxiliary functions and public interfaces
913 private:
914 void sha256_deque(const VectorRegister src,
915 const VectorRegister dst1, const VectorRegister dst2, const VectorRegister dst3);
916 void sha256_load_h_vec(const VectorRegister a, const VectorRegister e, const Register hptr);
917 void sha256_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
918 void sha256_load_w_plus_k_vec(const Register buf_in, const VectorRegister* ws,
919 const int total_ws, const Register k, const VectorRegister* kpws,
920 const int total_kpws);
921 void sha256_calc_4w(const VectorRegister w0, const VectorRegister w1,
922 const VectorRegister w2, const VectorRegister w3, const VectorRegister kpw0,
923 const VectorRegister kpw1, const VectorRegister kpw2, const VectorRegister kpw3,
924 const Register j, const Register k);
925 void sha256_update_sha_state(const VectorRegister a, const VectorRegister b,
926 const VectorRegister c, const VectorRegister d, const VectorRegister e,
927 const VectorRegister f, const VectorRegister g, const VectorRegister h,
928 const Register hptr);
929
930 void sha512_load_w_vec(const Register buf_in, const VectorRegister* ws, const int total_ws);
931 void sha512_update_sha_state(const Register state, const VectorRegister* hs, const int total_hs);
932 void sha512_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
933 void sha512_load_h_vec(const Register state, const VectorRegister* hs, const int total_hs);
934 void sha512_calc_2w(const VectorRegister w0, const VectorRegister w1,
935 const VectorRegister w2, const VectorRegister w3,
936 const VectorRegister w4, const VectorRegister w5,
937 const VectorRegister w6, const VectorRegister w7,
938 const VectorRegister kpw0, const VectorRegister kpw1, const Register j,
939 const VectorRegister vRb, const Register k);
940
941 public:
942 void sha256(bool multi_block);
943 void sha512(bool multi_block);
944
945 void cache_wb(Address line);
946 void cache_wbsync(bool is_presync);
947
948 //
949 // Debugging
950 //
951
952 // assert on cr0
953 enum AsmAssertCond {
954 eq,
955 ne,
956 ge,
957 gt,
958 lt,
959 le
960 };
961 void asm_assert(AsmAssertCond cond, const char* msg) PRODUCT_RETURN;
962 void asm_assert_eq(const char* msg) { asm_assert(eq, msg); }
963 void asm_assert_ne(const char* msg) { asm_assert(ne, msg); }
964
965 private:
966 void asm_assert_mems_zero(AsmAssertCond cond, int size, int mem_offset, Register mem_base,
967 const char* msg) NOT_DEBUG_RETURN;
968
969 public:
970
971 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg) {
972 asm_assert_mems_zero(eq, 8, mem_offset, mem_base, msg);
973 }
974 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg) {
975 asm_assert_mems_zero(ne, 8, mem_offset, mem_base, msg);
976 }
977
978 // Calls verify_oop. If UseCompressedOops is on, decodes the oop.
979 // Preserves reg.
980 void verify_coop(Register reg, const char*);
981 // Emit code to verify that reg contains a valid oop if +VerifyOops is set.
982 void verify_oop(Register reg, const char* s = "broken oop");
983 void verify_oop_addr(RegisterOrConstant offs, Register base, const char* s = "contains broken oop");
984
985 // TODO: verify method and klass metadata (compare against vptr?)
986 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
987 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
988
989 // Convenience method returning function entry. For the ELFv1 case
990 // creates function descriptor at the current address and returns
991 // the pointer to it. For the ELFv2 case returns the current address.
992 inline address function_entry();
993
994 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
995 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
996
997 private:
998 void stop(int type, const char* msg);
999
1000 public:
1001 enum {
1002 stop_stop = 0,
1003 stop_untested = 1,
1004 stop_unimplemented = 2,
1005 stop_shouldnotreachhere = 3,
1006 stop_msg_present = -0x8000
1007 };
1008
1009 // Prints msg, dumps registers and stops execution.
1010 void stop (const char* msg = nullptr) { stop(stop_stop, msg); }
1011 void untested (const char* msg = nullptr) { stop(stop_untested, msg); }
1012 void unimplemented (const char* msg = nullptr) { stop(stop_unimplemented, msg); }
1013 void should_not_reach_here(const char* msg = nullptr) { stop(stop_shouldnotreachhere, msg); }
1014
1015 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN;
1016
1017 // Inline type specific methods
1018 #include "asm/macroAssembler_common.hpp"
1019 };
1020
1021 #endif // CPU_PPC_MACROASSEMBLER_PPC_HPP