1 /*
2 * Copyright (c) 2002, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2026 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/accessDecorators.hpp"
31 #include "runtime/signature.hpp"
32 #include "utilities/macros.hpp"
33
34 // MacroAssembler extends Assembler by a few frequently used macros.
35
36 class ciTypeArray;
37 class OopMap;
38 class ciInlineKlass;
39 class SigEntry;
40 class VMRegPair;
41
42 class MacroAssembler: public Assembler {
43 public:
44 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
45
46 // Indicates whether and, if so, which registers must be preserved when calling runtime code.
47 enum PreservationLevel {
48 PRESERVATION_NONE,
49 PRESERVATION_FRAME_LR,
50 PRESERVATION_FRAME_LR_GP_REGS,
51 PRESERVATION_FRAME_LR_GP_FP_REGS
52 };
53
54 //
55 // Optimized instruction emitters
56 //
57
58 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; }
59 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); }
60
61 // load d = *[a+si31]
62 // Emits several instructions if the offset is not encodable in one instruction.
63 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop);
64 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop);
65 inline static bool is_ld_largeoffset(address a);
66 inline static int get_ld_largeoffset_offset(address a);
67
68 inline void round_to(Register r, int modulus);
69
70 // Load/store with type given by parameter.
71 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed);
72 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes);
73
74 // Move register if destination register and target register are different
75 inline void mr_if_needed(Register rd, Register rs, bool allow_invalid = false);
76 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs);
77
78 // Memory barriers.
79 inline void membar(int bits);
80 inline void release();
81 inline void acquire();
82 inline void fence();
83
84 // nop padding
85 void align(int modulus, int max = 252, int rem = 0);
86
87 // Align prefix opcode to make sure it's not on the last word of a
88 // 64-byte block.
89 //
90 // Note: do not call align_prefix() in a .ad file (e.g. ppc.ad). Instead
91 // add ins_alignment(2) to the instruct definition and implement the
92 // compute_padding() method of the instruct node to use
93 // compute_prefix_padding(). See loadConI32Node::compute_padding() in
94 // ppc.ad for an example.
95 void align_prefix();
96
97 //
98 // Constants, loading constants, TOC support
99 //
100
101 // Address of the global TOC.
102 inline static address global_toc();
103 // Offset of given address to the global TOC.
104 inline static int offset_to_global_toc(const address addr);
105
106 // Address of TOC of the current method.
107 inline address method_toc();
108 // Offset of given address to TOC of the current method.
109 inline int offset_to_method_toc(const address addr);
110
111 // Global TOC.
112 void calculate_address_from_global_toc(Register dst, address addr,
113 bool hi16 = true, bool lo16 = true,
114 bool add_relocation = true, bool emit_dummy_addr = false,
115 bool add_addr_to_reloc = true);
116 void calculate_address_from_global_toc(Register dst, Label& addr,
117 bool hi16 = true, bool lo16 = true,
118 bool add_relocation = true, bool emit_dummy_addr = false) {
119 calculate_address_from_global_toc(dst, target(addr), hi16, lo16, add_relocation, emit_dummy_addr, false);
120 }
121 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) {
122 calculate_address_from_global_toc(dst, addr, true, false);
123 };
124 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) {
125 calculate_address_from_global_toc(dst, addr, false, true);
126 };
127
128 inline static bool is_calculate_address_from_global_toc_at(address a, address bound);
129 // Returns address of first instruction in sequence.
130 static address patch_calculate_address_from_global_toc_at(address a, address bound, address addr);
131 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr);
132
133 #ifdef _LP64
134 // Patch narrow oop constant.
135 inline static bool is_set_narrow_oop(address a, address bound);
136 // Returns address of first instruction in sequence.
137 static address patch_set_narrow_oop(address a, address bound, narrowOop data);
138 static narrowOop get_narrow_oop(address a, address bound);
139 #endif
140
141 inline static bool is_load_const_at(address a);
142
143 // Emits an oop const to the constant pool, loads the constant, and
144 // sets a relocation info with address current_pc.
145 // Returns true if successful.
146 bool load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc, bool fixed_size = false);
147
148 static bool is_load_const_from_method_toc_at(address a);
149 static int get_offset_of_load_const_from_method_toc_at(address a);
150
151 // Get the 64 bit constant from a `load_const' sequence.
152 static long get_const(address load_const);
153
154 // Patch the 64 bit constant of a `load_const' sequence. This is a
155 // low level procedure. It neither flushes the instruction cache nor
156 // is it atomic.
157 static void patch_const(address load_const, long x);
158
159 // Metadata in code that we have to keep track of.
160 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
161 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
162 // Oops used directly in compiled code are stored in the constant pool,
163 // and loaded from there.
164 // Allocate new entry for oop in constant pool. Generate relocation.
165 AddressLiteral allocate_oop_address(jobject obj);
166 // Find oop obj in constant pool. Return relocation with it's index.
167 AddressLiteral constant_oop_address(jobject obj);
168
169 // Find oop in constant pool and emit instructions to load it.
170 // Uses constant_oop_address.
171 inline void set_oop_constant(jobject obj, Register d);
172 // Same as load_address.
173 inline void set_oop (AddressLiteral obj_addr, Register d);
174
175 //
176 // branch, jump
177 //
178 // set dst to -1, 0, +1 as follows: if CR0bi is "greater than", dst is set to 1,
179 // if CR0bi is "equal", dst is set to 0, otherwise it's set to -1.
180 void inline set_cmp3(Register dst);
181 // set dst to (treat_unordered_like_less ? -1 : +1)
182 void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
183 // Branch-free implementation to convert !=0 to 1.
184 void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
185 // Convert between half precision float encoded into a short and a float in a FloatRegister.
186 void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
187 void inline hf2f(FloatRegister dst, Register src);
188
189 inline void pd_patch_instruction(address branch, address target, const char* file, int line);
190 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
191
192 // Conditional far branch for destinations encodable in 24+2 bits.
193 // Same interface as bc, e.g. no inverse boint-field.
194 enum {
195 bc_far_optimize_not = 0,
196 bc_far_optimize_on_relocate = 1
197 };
198 // optimize: flag for telling the conditional far branch to optimize
199 // itself when relocated.
200 void bc_far(int boint, int biint, Label& dest, int optimize);
201 void bc_far_optimized(int boint, int biint, Label& dest); // 1 or 2 instructions
202 // Relocation of conditional far branches.
203 static bool is_bc_far_at(address instruction_addr);
204 static address get_dest_of_bc_far_at(address instruction_addr);
205 static void set_dest_of_bc_far_at(address instruction_addr, address dest);
206 private:
207 static bool inline is_bc_far_variant1_at(address instruction_addr);
208 static bool inline is_bc_far_variant2_at(address instruction_addr);
209 static bool inline is_bc_far_variant3_at(address instruction_addr);
210 public:
211
212 // Convenience bc_far versions.
213 inline void blt_far(ConditionRegister crx, Label& L, int optimize);
214 inline void bgt_far(ConditionRegister crx, Label& L, int optimize);
215 inline void beq_far(ConditionRegister crx, Label& L, int optimize);
216 inline void bso_far(ConditionRegister crx, Label& L, int optimize);
217 inline void bge_far(ConditionRegister crx, Label& L, int optimize);
218 inline void ble_far(ConditionRegister crx, Label& L, int optimize);
219 inline void bne_far(ConditionRegister crx, Label& L, int optimize);
220 inline void bns_far(ConditionRegister crx, Label& L, int optimize);
221
222 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump.
223 private:
224 enum {
225 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/),
226 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord,
227 bxx64_patchable_ret_addr_offset = bxx64_patchable_size
228 };
229 void bxx64_patchable(address target, relocInfo::relocType rt, bool link);
230 static bool is_bxx64_patchable_at( address instruction_addr, bool link);
231 // Does the instruction use a pc-relative encoding of the destination?
232 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link);
233 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link);
234 // Load destination relative to global toc.
235 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link);
236 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link);
237 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link);
238 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link);
239
240 public:
241 // call
242 enum {
243 bl64_patchable_instruction_count = bxx64_patchable_instruction_count,
244 bl64_patchable_size = bxx64_patchable_size,
245 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset
246 };
247 inline void bl64_patchable(address target, relocInfo::relocType rt) {
248 bxx64_patchable(target, rt, /*link=*/true);
249 }
250 inline static bool is_bl64_patchable_at(address instruction_addr) {
251 return is_bxx64_patchable_at(instruction_addr, /*link=*/true);
252 }
253 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) {
254 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true);
255 }
256 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) {
257 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true);
258 }
259 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) {
260 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true);
261 }
262 // jump
263 enum {
264 b64_patchable_instruction_count = bxx64_patchable_instruction_count,
265 b64_patchable_size = bxx64_patchable_size,
266 };
267 inline void b64_patchable(address target, relocInfo::relocType rt) {
268 bxx64_patchable(target, rt, /*link=*/false);
269 }
270 inline static bool is_b64_patchable_at(address instruction_addr) {
271 return is_bxx64_patchable_at(instruction_addr, /*link=*/false);
272 }
273 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) {
274 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false);
275 }
276 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) {
277 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false);
278 }
279 inline static address get_dest_of_b64_patchable_at(address instruction_addr) {
280 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false);
281 }
282
283 //
284 // Support for frame handling
285 //
286
287 // some ABI-related functions
288
289 // Clobbers all volatile, (non-floating-point) general-purpose registers for debugging purposes.
290 // This is especially useful for making calls to the JRT in places in which this hasn't been done before;
291 // e.g. with the introduction of LRBs (load reference barriers) for concurrent garbage collection.
292 void clobber_volatile_gprs(Register excluded_register = noreg) NOT_DEBUG_RETURN;
293 // Load bad values into registers that are nonvolatile according to the ABI except R16_thread and R29_TOC.
294 // This is done after vthread preemption and before vthread resume.
295 void clobber_nonvolatile_registers() NOT_DEBUG_RETURN;
296 void clobber_carg_stack_slots(Register tmp);
297
298 int save_nonvolatile_registers_size(bool include_fp_regs, bool include_vector_regs) {
299 int size = (32 - 14) * 8; // GP regs
300 if (include_fp_regs) size += (32 - 14) * 8;
301 if (include_vector_regs) size += (32 - 20) * 16;
302 return size;
303 }
304 void save_nonvolatile_registers( Register dst_base, int offset, bool include_fp_regs, bool include_vector_regs);
305 void restore_nonvolatile_registers(Register src_base, int offset, bool include_fp_regs, bool include_vector_regs);
306
307 enum {
308 num_volatile_gp_regs = 11,
309 num_volatile_fp_regs = 14,
310 num_volatile_regs = num_volatile_gp_regs + num_volatile_fp_regs
311 };
312
313 void save_volatile_gprs( Register dst_base, int offset,
314 bool include_fp_regs = true, bool include_R3_RET_reg = true);
315 void restore_volatile_gprs(Register src_base, int offset,
316 bool include_fp_regs = true, bool include_R3_RET_reg = true);
317 void save_LR(Register tmp);
318 void restore_LR(Register tmp);
319 void save_LR_CR(Register tmp); // tmp contains LR on return.
320 void restore_LR_CR(Register tmp);
321
322 // Get current PC using bl-next-instruction trick.
323 address get_PC_trash_LR(Register result);
324
325 // Resize current frame either relatively wrt to current SP or absolute.
326 void resize_frame(Register offset, Register tmp);
327 void resize_frame(int offset, Register tmp);
328 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2);
329
330 // Push a frame of size bytes.
331 void push_frame(Register bytes, Register tmp);
332
333 // Push a frame of size `bytes'. No abi space provided.
334 void push_frame(unsigned int bytes, Register tmp);
335
336 // Push a frame of size `bytes' plus native_abi_reg_args on top.
337 void push_frame_reg_args(unsigned int bytes, Register tmp);
338
339 // pop current C frame
340 void pop_frame();
341
342 //
343 // Calls
344 //
345
346 private:
347 address _last_calls_return_pc;
348
349 #if defined(ABI_ELFv2)
350 // Generic version of a call to C function.
351 // Updates and returns _last_calls_return_pc.
352 address branch_to(Register function_entry, bool and_link);
353 #else
354 // Generic version of a call to C function via a function descriptor
355 // with variable support for C calling conventions (TOC, ENV, etc.).
356 // updates and returns _last_calls_return_pc.
357 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
358 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee);
359 #endif
360
361 public:
362
363 // Get the pc where the last call will return to. returns _last_calls_return_pc.
364 inline address last_calls_return_pc();
365
366 #if defined(ABI_ELFv2)
367 // Call a C function via a function descriptor and use full C
368 // calling conventions. Updates and returns _last_calls_return_pc.
369 address call_c(Register function_entry);
370 // For tail calls: only branch, don't link, so callee returns to caller of this function.
371 address call_c_and_return_to_caller(Register function_entry);
372 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none);
373 #else
374 // Call a C function via a function descriptor and use full C
375 // calling conventions. Updates and returns _last_calls_return_pc.
376 address call_c(Register function_descriptor);
377 // For tail calls: only branch, don't link, so callee returns to caller of this function.
378 address call_c_and_return_to_caller(Register function_descriptor);
379 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt);
380 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none) {
381 return call_c((const FunctionDescriptor*)function_entry, rt);
382 }
383 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt,
384 Register toc);
385 #endif
386
387 // CompiledIC call
388 bool ic_call(Register Rmethod_toc,
389 address target,
390 jint method_index = 0,
391 bool scratch_emit = false,
392 bool fixed_size = false);
393 static int ic_check_size();
394 int ic_check(int end_alignment);
395
396 enum { trampoline_stub_size = 6 * 4 };
397 address trampoline_call(AddressLiteral target,
398 Register Rmethod_toc = noreg,
399 bool scratch_emit = false);
400
401 // Inline type specific methods
402 #include "asm/macroAssembler_common.hpp"
403
404 void save_stack_increment(int sp_inc, int frame_size);
405
406 protected:
407
408 // It is imperative that all calls into the VM are handled via the
409 // call_VM macros. They make sure that the stack linkage is setup
410 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
411 // while call_VM_leaf's correspond to LEAF entry points.
412 //
413 // This is the base routine called by the different versions of
414 // call_VM. The interpreter may customize this version by overriding
415 // it for its purposes (e.g., to save/restore additional registers
416 // when doing a VM call).
417 //
418 // If no last_java_sp is specified (noreg) then SP will be used instead.
419 virtual void call_VM_base(
420 // where an oop-result ends up if any; use noreg otherwise
421 Register oop_result,
422 // to set up last_Java_frame in stubs; use noreg otherwise
423 Register last_java_sp,
424 // the entry point
425 address entry_point,
426 // flag which indicates if exception should be checked
427 bool check_exception = true,
428 Label* last_java_pc = nullptr
429 );
430
431 // Support for VM calls. This is the base routine called by the
432 // different versions of call_VM_leaf. The interpreter may customize
433 // this version by overriding it for its purposes (e.g., to
434 // save/restore additional registers when doing a VM call).
435 void call_VM_leaf_base(address entry_point);
436
437 public:
438 // Call into the VM.
439 // Passes the thread pointer (in R3_ARG1) as a prepended argument.
440 // Makes sure oop return values are visible to the GC.
441 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true, Label* last_java_pc = nullptr);
442 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
443 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
444 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true);
445 void call_VM_leaf(address entry_point);
446 void call_VM_leaf(address entry_point, Register arg_1);
447 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
448 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
449
450 // Call a stub function via a function descriptor, but don't save
451 // TOC before call, don't setup TOC and ENV for call, and don't
452 // restore TOC after call. Updates and returns _last_calls_return_pc.
453 inline address call_stub(Register function_entry);
454 inline void call_stub_and_return_to(Register function_entry, Register return_pc);
455
456 void post_call_nop();
457 static bool is_post_call_nop(int instr_bits) {
458 const uint32_t nineth_bit = opp_u_field(1, 9, 9);
459 const uint32_t opcode_mask = 0b111110 << OPCODE_SHIFT;
460 const uint32_t pcn_mask = opcode_mask | nineth_bit;
461 return (instr_bits & pcn_mask) == (Assembler::CMPLI_OPCODE | nineth_bit);
462 }
463
464 //
465 // Java utilities
466 //
467
468 // Read from the polling page, its address is already in a register.
469 inline void load_from_polling_page(Register polling_page_address, int offset = 0);
470 // Check whether instruction is a read access to the polling page
471 // which was emitted by load_from_polling_page(..).
472 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be nullptr*/,
473 address* polling_address_ptr = nullptr);
474
475 // Support for null-checks
476 //
477 // Generates code that causes a null OS exception if the content of reg is null.
478 // If the accessed location is M[reg + offset] and the offset is known, provide the
479 // offset. No explicit code generation is needed if the offset is within a certain
480 // range (0 <= offset <= page_size).
481
482 // Stack overflow checking
483 void bang_stack_with_offset(int offset);
484
485 // If instruction is a stack bang of the form ld, stdu, or
486 // stdux, return the banged address. Otherwise, return 0.
487 static address get_stack_bang_address(int instruction, void* ucontext);
488
489 // Check for reserved stack access in method being exited. If the reserved
490 // stack area was accessed, protect it again and throw StackOverflowError.
491 void reserved_stack_check(Register return_pc);
492
493 // Atomics
494 // CmpxchgX sets condition register to cmpX(current, compare).
495 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
496 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
497 static inline bool cmpxchgx_hint_acquire_lock() { return true; }
498 // The stxcx will probably not be succeeded by a releasing store.
499 static inline bool cmpxchgx_hint_release_lock() { return false; }
500 static inline bool cmpxchgx_hint_atomic_update() { return false; }
501
502 // Cmpxchg semantics
503 enum {
504 MemBarNone = 0,
505 MemBarRel = 1,
506 MemBarAcq = 2,
507 MemBarFenceAfter = 4 // use powers of 2
508 };
509 private:
510 // Helper functions for word/sub-word atomics.
511 void atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value,
512 Register addr_base, Register tmp1, Register tmp2, Register tmp3,
513 bool cmpxchgx_hint, bool is_add, int size);
514 void cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value,
515 RegisterOrConstant compare_value, Register exchange_value,
516 Register addr_base,Label &retry, Label &failed, bool cmpxchgx_hint, int size);
517 void cmpxchg_generic(ConditionRegister flag, Register dest_current_value,
518 RegisterOrConstant compare_value, Register exchange_value,
519 Register addr_base, int semantics, bool cmpxchgx_hint, Register int_flag_success,
520 Label* failed_ext, bool contention_hint, bool weak, int size);
521 public:
522 // Temps and addr_base are killed if processor does not support Power 8 instructions.
523 // Result will be sign extended.
524 void getandsetb(Register dest_current_value, Register exchange_value, Register addr_base,
525 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
526 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 1);
527 }
528 // Temps and addr_base are killed if processor does not support Power 8 instructions.
529 // Result will be sign extended.
530 void getandseth(Register dest_current_value, Register exchange_value, Register addr_base,
531 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
532 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 2);
533 }
534 void getandsetw(Register dest_current_value, Register exchange_value, Register addr_base,
535 bool cmpxchgx_hint) {
536 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, noreg, noreg, noreg, cmpxchgx_hint, false, 4);
537 }
538 void getandsetd(Register dest_current_value, Register exchange_value, Register addr_base,
539 bool cmpxchgx_hint);
540 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
541 // Result will be sign extended.
542 void getandaddb(Register dest_current_value, Register inc_value, Register addr_base,
543 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
544 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 1);
545 }
546 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
547 // Result will be sign extended.
548 void getandaddh(Register dest_current_value, Register inc_value, Register addr_base,
549 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
550 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 2);
551 }
552 void getandaddw(Register dest_current_value, Register inc_value, Register addr_base,
553 Register tmp1, bool cmpxchgx_hint) {
554 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, noreg, noreg, cmpxchgx_hint, true, 4);
555 }
556 void getandaddd(Register dest_current_value, Register exchange_value, Register addr_base,
557 Register tmp, bool cmpxchgx_hint);
558 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
559 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
560 void cmpxchgb(ConditionRegister flag, Register dest_current_value,
561 RegisterOrConstant compare_value, Register exchange_value,
562 Register addr_base, int semantics, bool cmpxchgx_hint = false,
563 Register int_flag_success = noreg, Label* failed = nullptr,
564 bool contention_hint = false, bool weak = false) {
565 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, semantics,
566 cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 1);
567 }
568 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
569 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
570 void cmpxchgh(ConditionRegister flag, Register dest_current_value,
571 RegisterOrConstant compare_value, Register exchange_value,
572 Register addr_base, int semantics, bool cmpxchgx_hint = false,
573 Register int_flag_success = noreg, Label* failed = nullptr,
574 bool contention_hint = false, bool weak = false) {
575 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
576 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 2);
577 }
578 void cmpxchgw(ConditionRegister flag, Register dest_current_value,
579 RegisterOrConstant compare_value, Register exchange_value,
580 Register addr_base,
581 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
582 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
583 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base,
584 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 4);
585 }
586 void cmpxchgd(ConditionRegister flag, Register dest_current_value,
587 RegisterOrConstant compare_value, Register exchange_value,
588 Register addr_base,
589 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
590 Label* failed = nullptr, bool contention_hint = false, bool weak = false);
591
592 // interface method calling
593 void lookup_interface_method(Register recv_klass,
594 Register intf_klass,
595 RegisterOrConstant itable_index,
596 Register method_result,
597 Register temp_reg, Register temp2_reg,
598 Label& no_such_interface,
599 bool return_method = true);
600
601 // virtual method calling
602 void lookup_virtual_method(Register recv_klass,
603 RegisterOrConstant vtable_index,
604 Register method_result);
605
606 // Test sub_klass against super_klass, with fast and slow paths.
607
608 // The fast path produces a tri-state answer: yes / no / maybe-slow.
609 // One of the three labels can be null, meaning take the fall-through.
610 // If super_check_offset is -1, the value is loaded up from super_klass.
611 // No registers are killed, except temp_reg and temp2_reg.
612 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
613 void check_klass_subtype_fast_path(Register sub_klass,
614 Register super_klass,
615 Register temp1_reg,
616 Register temp2_reg,
617 Label* L_success,
618 Label* L_failure,
619 Label* L_slow_path = nullptr, // default fall through
620 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
621
622 // The rest of the type check; must be wired to a corresponding fast path.
623 // It does not repeat the fast path logic, so don't use it standalone.
624 // The temp_reg can be noreg, if no temps are available.
625 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
626 // Updates the sub's secondary super cache as necessary.
627 void check_klass_subtype_slow_path_linear(Register sub_klass,
628 Register super_klass,
629 Register temp1_reg,
630 Register temp2_reg,
631 Label* L_success = nullptr,
632 Register result_reg = noreg);
633
634 void check_klass_subtype_slow_path_table(Register sub_klass,
635 Register super_klass,
636 Register temp1_reg,
637 Register temp2_reg,
638 Label* L_success = nullptr,
639 Register result_reg = noreg);
640
641 void check_klass_subtype_slow_path(Register sub_klass,
642 Register super_klass,
643 Register temp1_reg,
644 Register temp2_reg,
645 Label* L_success = nullptr,
646 Register result_reg = noreg);
647
648 void lookup_secondary_supers_table_var(Register sub_klass,
649 Register r_super_klass,
650 Register temp1,
651 Register temp2,
652 Register temp3,
653 Register temp4,
654 Register result);
655
656 // If r is valid, return r.
657 // If r is invalid, remove a register r2 from available_regs, add r2
658 // to regs_to_push, then return r2.
659 Register allocate_if_noreg(const Register r,
660 RegSetIterator<Register> &available_regs,
661 RegSet ®s_to_push);
662
663 // Frameless register spills (negative offset from SP)
664 void push_set(RegSet set);
665 void pop_set(RegSet set);
666
667 // Simplified, combined version, good for typical uses.
668 // Falls through on failure.
669 void check_klass_subtype(Register sub_klass,
670 Register super_klass,
671 Register temp1_reg,
672 Register temp2_reg,
673 Label& L_success);
674
675 void repne_scan(Register addr, Register value, Register count, Register scratch);
676
677 // As above, but with a constant super_klass.
678 // The result is in Register result, not the condition codes.
679 void lookup_secondary_supers_table_const(Register r_sub_klass,
680 Register r_super_klass,
681 Register temp1,
682 Register temp2,
683 Register temp3,
684 Register temp4,
685 Register result,
686 u1 super_klass_slot);
687
688 void verify_secondary_supers_table(Register r_sub_klass,
689 Register r_super_klass,
690 Register result,
691 Register temp1,
692 Register temp2,
693 Register temp3);
694
695 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
696 Register r_array_base,
697 Register r_array_index,
698 Register r_bitmap,
699 Register result,
700 Register temp1);
701
702 void clinit_barrier(Register klass,
703 Register thread,
704 Label* L_fast_path = nullptr,
705 Label* L_slow_path = nullptr);
706
707 // Method handle support (JSR 292).
708 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0);
709
710 void push_cont_fastpath();
711 void pop_cont_fastpath();
712 void atomically_flip_locked_state(bool is_unlock, Register obj, Register tmp, Label& failed, int semantics);
713 void fast_lock(Register box, Register obj, Register t1, Register t2, Label& slow);
714 void fast_unlock(Register obj, Register t1, Label& slow);
715
716 // allocation (for C1)
717 void tlab_allocate(
718 Register obj, // result: pointer to object after successful allocation
719 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
720 int con_size_in_bytes, // object size in bytes if known at compile time
721 Register t1, // temp register
722 Label& slow_case // continuation point if fast allocation fails
723 );
724
725 void compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
726 Register tmp1, Register tmp2, Register tmp3);
727
728 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
729 Register tmp1, Register tmp2, Register tmp3);
730
731 // Check if safepoint requested and if so branch
732 void safepoint_poll(Label& slow_path, Register temp, bool at_return, bool in_nmethod);
733 void jump_to_polling_page_return_handler_blob(int safepoint_offset, bool fixed_size = false);
734
735 void resolve_jobject(Register value, Register tmp1, Register tmp2,
736 MacroAssembler::PreservationLevel preservation_level);
737 void resolve_global_jobject(Register value, Register tmp1, Register tmp2,
738 MacroAssembler::PreservationLevel preservation_level);
739
740 // Support for managing the JavaThread pointer (i.e.; the reference to
741 // thread-local information).
742
743 // Support for last Java frame (but use call_VM instead where possible):
744 // access R16_thread->last_Java_sp.
745 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
746 void reset_last_Java_frame(bool check_last_java_sp = true);
747 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, Label* jpc = nullptr);
748
749 // Read vm result from thread: oop_result = R16_thread->result;
750 void get_vm_result_oop(Register oop_result);
751 void get_vm_result_metadata(Register metadata_result);
752
753 static bool needs_explicit_null_check(intptr_t offset);
754 static bool uses_implicit_null_check(void* address);
755
756 // Trap-instruction-based checks.
757 // Range checks can be distinguished from zero checks as they check 32 bit,
758 // zero checks all 64 bits (tw, td).
759 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual);
760 static bool is_trap_null_check(int x) {
761 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) ||
762 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0);
763 }
764
765 inline void trap_ic_miss_check(Register a, Register b);
766 static bool is_trap_ic_miss_check(int x) {
767 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/);
768 }
769
770 // Implicit or explicit null check, jumps to static address exception_entry.
771 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry);
772 inline void null_check(Register a, int offset, Label *Lis_null); // implicit only if Lis_null not provided
773
774 // Access heap oop, handle encoding and GC barriers.
775 // Some GC barriers call C so use needs_frame = true if an extra frame is needed at the current call site.
776 inline void access_store_at(BasicType type, DecoratorSet decorators,
777 Register base, RegisterOrConstant ind_or_offs, Register val,
778 Register tmp1, Register tmp2, Register tmp3,
779 MacroAssembler::PreservationLevel preservation_level);
780 inline void access_load_at(BasicType type, DecoratorSet decorators,
781 Register base, RegisterOrConstant ind_or_offs, Register dst,
782 Register tmp1, Register tmp2,
783 MacroAssembler::PreservationLevel preservation_level, Label *L_handle_null = nullptr);
784
785 public:
786 // Specify tmp1 for better code in certain compressed oops cases. Specify Label to bail out on null oop.
787 // tmp1, tmp2 and needs_frame are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
788 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
789 Register tmp1, Register tmp2,
790 MacroAssembler::PreservationLevel preservation_level,
791 DecoratorSet decorators = 0, Label *L_handle_null = nullptr);
792
793 inline void store_heap_oop(Register d, RegisterOrConstant offs, Register s1,
794 Register tmp1, Register tmp2, Register tmp3,
795 MacroAssembler::PreservationLevel preservation_level, DecoratorSet decorators = 0);
796
797 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong.
798 // src == d allowed.
799 inline Register encode_heap_oop_not_null(Register d, Register src = noreg);
800 inline Register decode_heap_oop_not_null(Register d, Register src = noreg);
801
802 // Null allowed.
803 inline Register encode_heap_oop(Register d, Register src); // Prefer null check in GC barrier!
804 inline void decode_heap_oop(Register d);
805
806 // Load/Store klass oop from klass field. Compress.
807 void load_klass_no_decode(Register dst, Register src);
808 void load_klass(Register dst, Register src);
809 void load_narrow_klass_compact(Register dst, Register src);
810 void cmp_klass(ConditionRegister dst, Register obj, Register klass, Register tmp, Register tmp2);
811 void cmp_klasses_from_objects(ConditionRegister dst, Register obj1, Register obj2, Register tmp1, Register tmp2);
812 void load_klass_check_null(Register dst, Register src, Label* is_null = nullptr);
813 void store_klass(Register dst_oop, Register klass, Register tmp = R0);
814 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified.
815
816 void resolve_oop_handle(Register result, Register tmp1, Register tmp2,
817 MacroAssembler::PreservationLevel preservation_level);
818 void resolve_weak_handle(Register result, Register tmp1, Register tmp2,
819 MacroAssembler::PreservationLevel preservation_level);
820 void load_method_holder(Register holder, Register method);
821
822 void decode_klass_not_null(Register dst, Register src = noreg);
823 Register encode_klass_not_null(Register dst, Register src = noreg);
824
825 // markWord tests, kills markWord reg
826 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
827
828 // inlineKlass queries, kills temp_reg
829 void test_oop_is_not_inline_type(Register object, Label& not_inline_type, bool can_be_null = true);
830
831 void test_field_is_null_free_inline_type(Register flags, Label& is_null_free);
832 void test_field_is_not_null_free_inline_type(Register flags, Label& not_null_free);
833 void test_field_is_flat(Register flags, Label& is_flat);
834
835 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
836 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label, bool maybe_far = false);
837 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array, bool maybe_far = false);
838 void test_non_flat_array_oop(Register oop, Register temp_reg, Label& is_non_flat_array);
839 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array, bool maybe_far = false);
840 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label& is_non_null_free_array);
841
842 // Check array klass layout helper for flat or null-free arrays...
843 void test_flat_array_layout(Register lh, Label& is_flat_array);
844
845 void load_metadata(Register dst, Register src);
846
847 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
848
849 void load_prototype_header(Register dst, Register src);
850
851 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
852
853 // inline type data payload offsets...
854 void payload_offset(Register inline_klass, Register offset);
855 void payload_address(Register oop, Register data, Register inline_klass, Register t1);
856
857 // SIGTRAP-based range checks for arrays.
858 inline void trap_range_check_l(Register a, Register b);
859 inline void trap_range_check_l(Register a, int si16);
860 static bool is_trap_range_check_l(int x) {
861 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
862 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) );
863 }
864 inline void trap_range_check_le(Register a, int si16);
865 static bool is_trap_range_check_le(int x) {
866 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/);
867 }
868 inline void trap_range_check_g(Register a, int si16);
869 static bool is_trap_range_check_g(int x) {
870 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/);
871 }
872 inline void trap_range_check_ge(Register a, Register b);
873 inline void trap_range_check_ge(Register a, int si16);
874 static bool is_trap_range_check_ge(int x) {
875 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
876 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) );
877 }
878 static bool is_trap_range_check(int x) {
879 return is_trap_range_check_l(x) || is_trap_range_check_le(x) ||
880 is_trap_range_check_g(x) || is_trap_range_check_ge(x);
881 }
882
883 void clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp = R0, int offset = 0);
884 void clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp = R0);
885 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0, long const_cnt = -1);
886 void fill_words(Register base, Register cnt, Register value);
887
888 // Emitters for BigInteger.multiplyToLen intrinsic.
889 inline void multiply64(Register dest_hi, Register dest_lo,
890 Register x, Register y);
891 void add2_with_carry(Register dest_hi, Register dest_lo,
892 Register src1, Register src2);
893 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
894 Register y, Register y_idx, Register z,
895 Register carry, Register product_high, Register product,
896 Register idx, Register kdx, Register tmp);
897 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
898 Register yz_idx, Register idx, Register carry,
899 Register product_high, Register product, Register tmp,
900 int offset);
901 void multiply_128_x_128_loop(Register x_xstart,
902 Register y, Register z,
903 Register yz_idx, Register idx, Register carry,
904 Register product_high, Register product,
905 Register carry2, Register tmp);
906 void muladd(Register out, Register in, Register offset, Register len, Register k,
907 Register tmp1, Register tmp2, Register carry);
908 void multiply_to_len(Register x, Register xlen,
909 Register y, Register ylen,
910 Register z,
911 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
912 Register tmp6, Register tmp7, Register tmp8, Register tmp9, Register tmp10,
913 Register tmp11, Register tmp12, Register tmp13);
914
915 // non-atomic 64-bit memory increment by simm16
916 void increment_mem64(Register base, RegisterOrConstant ind_or_offs, int val, Register tmp);
917
918 // Bytecode profiling (tmp2 = noreg is allowed, but then recv is killed)
919 void profile_receiver_type(Register recv, Register mdp, int mdp_offset, Register tmp1, Register tmp2);
920
921 // Emitters for CRC32 calculation.
922 // A note on invertCRC:
923 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
924 // CRC32 holds it's current crc value in the externally visible representation.
925 // CRC32C holds it's current crc value in internal format, ready for updating.
926 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
927 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
928 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
929 void load_reverse_32(Register dst, Register src);
930 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3);
931 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp);
932 void update_byte_crc32(Register crc, Register val, Register table);
933 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
934 Register data, bool loopAlignment);
935 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
936 Register t0, Register t1, Register t2, Register t3,
937 Register tc0, Register tc1, Register tc2, Register tc3);
938 void kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants,
939 Register t0, Register t1, Register t2, Register t3, Register t4,
940 Register t5, Register t6, bool invertCRC);
941 void kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants,
942 Register t0, Register t1, Register t2, Register t3, Register t4,
943 Register t5, Register t6);
944 // Version which internally decides what to use.
945 void crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2,
946 Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c);
947
948 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
949 bool invertCRC);
950
951 // SHA-2 auxiliary functions and public interfaces
952 private:
953 void sha256_deque(const VectorRegister src,
954 const VectorRegister dst1, const VectorRegister dst2, const VectorRegister dst3);
955 void sha256_load_h_vec(const VectorRegister a, const VectorRegister e, const Register hptr);
956 void sha256_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
957 void sha256_load_w_plus_k_vec(const Register buf_in, const VectorRegister* ws,
958 const int total_ws, const Register k, const VectorRegister* kpws,
959 const int total_kpws);
960 void sha256_calc_4w(const VectorRegister w0, const VectorRegister w1,
961 const VectorRegister w2, const VectorRegister w3, const VectorRegister kpw0,
962 const VectorRegister kpw1, const VectorRegister kpw2, const VectorRegister kpw3,
963 const Register j, const Register k);
964 void sha256_update_sha_state(const VectorRegister a, const VectorRegister b,
965 const VectorRegister c, const VectorRegister d, const VectorRegister e,
966 const VectorRegister f, const VectorRegister g, const VectorRegister h,
967 const Register hptr);
968
969 void sha512_load_w_vec(const Register buf_in, const VectorRegister* ws, const int total_ws);
970 void sha512_update_sha_state(const Register state, const VectorRegister* hs, const int total_hs);
971 void sha512_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
972 void sha512_load_h_vec(const Register state, const VectorRegister* hs, const int total_hs);
973 void sha512_calc_2w(const VectorRegister w0, const VectorRegister w1,
974 const VectorRegister w2, const VectorRegister w3,
975 const VectorRegister w4, const VectorRegister w5,
976 const VectorRegister w6, const VectorRegister w7,
977 const VectorRegister kpw0, const VectorRegister kpw1, const Register j,
978 const VectorRegister vRb, const Register k);
979
980 public:
981 void sha256(bool multi_block);
982 void sha512(bool multi_block);
983
984 void cache_wb(Address line);
985 void cache_wbsync(bool is_presync);
986
987 //
988 // Debugging
989 //
990
991 // assert on cr0
992 enum AsmAssertCond {
993 eq,
994 ne,
995 ge,
996 gt,
997 lt,
998 le
999 };
1000 void asm_assert(AsmAssertCond cond, const char* msg) PRODUCT_RETURN;
1001 void asm_assert_eq(const char* msg) { asm_assert(eq, msg); }
1002 void asm_assert_ne(const char* msg) { asm_assert(ne, msg); }
1003
1004 private:
1005 void asm_assert_mems_zero(AsmAssertCond cond, int size, int mem_offset, Register mem_base,
1006 const char* msg) NOT_DEBUG_RETURN;
1007
1008 public:
1009
1010 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg) {
1011 asm_assert_mems_zero(eq, 8, mem_offset, mem_base, msg);
1012 }
1013 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg) {
1014 asm_assert_mems_zero(ne, 8, mem_offset, mem_base, msg);
1015 }
1016
1017 // Calls verify_oop. If UseCompressedOops is on, decodes the oop.
1018 // Preserves reg.
1019 void verify_coop(Register reg, const char*);
1020 // Emit code to verify that reg contains a valid oop if +VerifyOops is set.
1021 void verify_oop(Register reg, const char* s = "broken oop");
1022 void verify_oop_addr(RegisterOrConstant offs, Register base, const char* s = "contains broken oop");
1023
1024 // TODO: verify method and klass metadata (compare against vptr?)
1025 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1026 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
1027
1028 // Convenience method returning function entry. For the ELFv1 case
1029 // creates function descriptor at the current address and returns
1030 // the pointer to it. For the ELFv2 case returns the current address.
1031 inline address function_entry();
1032
1033 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1034 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1035
1036 private:
1037 void stop(int type, const char* msg);
1038
1039 public:
1040 enum {
1041 stop_stop = 0,
1042 stop_untested = 1,
1043 stop_unimplemented = 2,
1044 stop_shouldnotreachhere = 3,
1045 stop_msg_present = -0x8000
1046 };
1047
1048 // Prints msg, dumps registers and stops execution.
1049 void stop (const char* msg = nullptr) { stop(stop_stop, msg); }
1050 void untested (const char* msg = nullptr) { stop(stop_untested, msg); }
1051 void unimplemented (const char* msg = nullptr) { stop(stop_unimplemented, msg); }
1052 void should_not_reach_here(const char* msg = nullptr) { stop(stop_shouldnotreachhere, msg); }
1053
1054 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN;
1055
1056 // Inline type specific methods
1057 #include "asm/macroAssembler_common.hpp"
1058 };
1059
1060 #endif // CPU_PPC_MACROASSEMBLER_PPC_HPP