1 //
2 // Copyright (c) 2011, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2012, 2026 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CR0(SOC, SOC, Op_RegFlags, 0, CR0->as_VMReg()); // v
240 reg_def CR1(SOC, SOC, Op_RegFlags, 1, CR1->as_VMReg()); // v
241 reg_def CR2(SOC, SOC, Op_RegFlags, 2, CR2->as_VMReg()); // nv
242 reg_def CR3(SOC, SOC, Op_RegFlags, 3, CR3->as_VMReg()); // nv
243 reg_def CR4(SOC, SOC, Op_RegFlags, 4, CR4->as_VMReg()); // nv
244 reg_def CR5(SOC, SOC, Op_RegFlags, 5, CR5->as_VMReg()); // v
245 reg_def CR6(SOC, SOC, Op_RegFlags, 6, CR6->as_VMReg()); // v
246 reg_def CR7(SOC, SOC, Op_RegFlags, 7, CR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257 // ----------------------------
258 // Vector Registers
259 // ----------------------------
260
261 reg_def VR0 (SOC, SOC, Op_RegF, 0, VR0->as_VMReg() );
262 reg_def VR0_H(SOC, SOC, Op_RegF, 0, VR0->as_VMReg()->next() );
263 reg_def VR0_J(SOC, SOC, Op_RegF, 0, VR0->as_VMReg()->next(2));
264 reg_def VR0_K(SOC, SOC, Op_RegF, 0, VR0->as_VMReg()->next(3));
265
266 reg_def VR1 (SOC, SOC, Op_RegF, 1, VR1->as_VMReg() );
267 reg_def VR1_H(SOC, SOC, Op_RegF, 1, VR1->as_VMReg()->next() );
268 reg_def VR1_J(SOC, SOC, Op_RegF, 1, VR1->as_VMReg()->next(2));
269 reg_def VR1_K(SOC, SOC, Op_RegF, 1, VR1->as_VMReg()->next(3));
270
271 reg_def VR2 (SOC, SOC, Op_RegF, 2, VR2->as_VMReg() );
272 reg_def VR2_H(SOC, SOC, Op_RegF, 2, VR2->as_VMReg()->next() );
273 reg_def VR2_J(SOC, SOC, Op_RegF, 2, VR2->as_VMReg()->next(2));
274 reg_def VR2_K(SOC, SOC, Op_RegF, 2, VR2->as_VMReg()->next(3));
275
276 reg_def VR3 (SOC, SOC, Op_RegF, 3, VR3->as_VMReg() );
277 reg_def VR3_H(SOC, SOC, Op_RegF, 3, VR3->as_VMReg()->next() );
278 reg_def VR3_J(SOC, SOC, Op_RegF, 3, VR3->as_VMReg()->next(2));
279 reg_def VR3_K(SOC, SOC, Op_RegF, 3, VR3->as_VMReg()->next(3));
280
281 reg_def VR4 (SOC, SOC, Op_RegF, 4, VR4->as_VMReg() );
282 reg_def VR4_H(SOC, SOC, Op_RegF, 4, VR4->as_VMReg()->next() );
283 reg_def VR4_J(SOC, SOC, Op_RegF, 4, VR4->as_VMReg()->next(2));
284 reg_def VR4_K(SOC, SOC, Op_RegF, 4, VR4->as_VMReg()->next(3));
285
286 reg_def VR5 (SOC, SOC, Op_RegF, 5, VR5->as_VMReg() );
287 reg_def VR5_H(SOC, SOC, Op_RegF, 5, VR5->as_VMReg()->next() );
288 reg_def VR5_J(SOC, SOC, Op_RegF, 5, VR5->as_VMReg()->next(2));
289 reg_def VR5_K(SOC, SOC, Op_RegF, 5, VR5->as_VMReg()->next(3));
290
291 reg_def VR6 (SOC, SOC, Op_RegF, 6, VR6->as_VMReg() );
292 reg_def VR6_H(SOC, SOC, Op_RegF, 6, VR6->as_VMReg()->next() );
293 reg_def VR6_J(SOC, SOC, Op_RegF, 6, VR6->as_VMReg()->next(2));
294 reg_def VR6_K(SOC, SOC, Op_RegF, 6, VR6->as_VMReg()->next(3));
295
296 reg_def VR7 (SOC, SOC, Op_RegF, 7, VR7->as_VMReg() );
297 reg_def VR7_H(SOC, SOC, Op_RegF, 7, VR7->as_VMReg()->next() );
298 reg_def VR7_J(SOC, SOC, Op_RegF, 7, VR7->as_VMReg()->next(2));
299 reg_def VR7_K(SOC, SOC, Op_RegF, 7, VR7->as_VMReg()->next(3));
300
301 reg_def VR8 (SOC, SOC, Op_RegF, 8, VR8->as_VMReg() );
302 reg_def VR8_H(SOC, SOC, Op_RegF, 8, VR8->as_VMReg()->next() );
303 reg_def VR8_J(SOC, SOC, Op_RegF, 8, VR8->as_VMReg()->next(2));
304 reg_def VR8_K(SOC, SOC, Op_RegF, 8, VR8->as_VMReg()->next(3));
305
306 reg_def VR9 (SOC, SOC, Op_RegF, 9, VR9->as_VMReg() );
307 reg_def VR9_H(SOC, SOC, Op_RegF, 9, VR9->as_VMReg()->next() );
308 reg_def VR9_J(SOC, SOC, Op_RegF, 9, VR9->as_VMReg()->next(2));
309 reg_def VR9_K(SOC, SOC, Op_RegF, 9, VR9->as_VMReg()->next(3));
310
311 reg_def VR10 (SOC, SOC, Op_RegF, 10, VR10->as_VMReg() );
312 reg_def VR10_H(SOC, SOC, Op_RegF, 10, VR10->as_VMReg()->next() );
313 reg_def VR10_J(SOC, SOC, Op_RegF, 10, VR10->as_VMReg()->next(2));
314 reg_def VR10_K(SOC, SOC, Op_RegF, 10, VR10->as_VMReg()->next(3));
315
316 reg_def VR11 (SOC, SOC, Op_RegF, 11, VR11->as_VMReg() );
317 reg_def VR11_H(SOC, SOC, Op_RegF, 11, VR11->as_VMReg()->next() );
318 reg_def VR11_J(SOC, SOC, Op_RegF, 11, VR11->as_VMReg()->next(2));
319 reg_def VR11_K(SOC, SOC, Op_RegF, 11, VR11->as_VMReg()->next(3));
320
321 reg_def VR12 (SOC, SOC, Op_RegF, 12, VR12->as_VMReg() );
322 reg_def VR12_H(SOC, SOC, Op_RegF, 12, VR12->as_VMReg()->next() );
323 reg_def VR12_J(SOC, SOC, Op_RegF, 12, VR12->as_VMReg()->next(2));
324 reg_def VR12_K(SOC, SOC, Op_RegF, 12, VR12->as_VMReg()->next(3));
325
326 reg_def VR13 (SOC, SOC, Op_RegF, 13, VR13->as_VMReg() );
327 reg_def VR13_H(SOC, SOC, Op_RegF, 13, VR13->as_VMReg()->next() );
328 reg_def VR13_J(SOC, SOC, Op_RegF, 13, VR13->as_VMReg()->next(2));
329 reg_def VR13_K(SOC, SOC, Op_RegF, 13, VR13->as_VMReg()->next(3));
330
331 reg_def VR14 (SOC, SOC, Op_RegF, 14, VR14->as_VMReg() );
332 reg_def VR14_H(SOC, SOC, Op_RegF, 14, VR14->as_VMReg()->next() );
333 reg_def VR14_J(SOC, SOC, Op_RegF, 14, VR14->as_VMReg()->next(2));
334 reg_def VR14_K(SOC, SOC, Op_RegF, 14, VR14->as_VMReg()->next(3));
335
336 reg_def VR15 (SOC, SOC, Op_RegF, 15, VR15->as_VMReg() );
337 reg_def VR15_H(SOC, SOC, Op_RegF, 15, VR15->as_VMReg()->next() );
338 reg_def VR15_J(SOC, SOC, Op_RegF, 15, VR15->as_VMReg()->next(2));
339 reg_def VR15_K(SOC, SOC, Op_RegF, 15, VR15->as_VMReg()->next(3));
340
341 reg_def VR16 (SOC, SOC, Op_RegF, 16, VR16->as_VMReg() );
342 reg_def VR16_H(SOC, SOC, Op_RegF, 16, VR16->as_VMReg()->next() );
343 reg_def VR16_J(SOC, SOC, Op_RegF, 16, VR16->as_VMReg()->next(2));
344 reg_def VR16_K(SOC, SOC, Op_RegF, 16, VR16->as_VMReg()->next(3));
345
346 reg_def VR17 (SOC, SOC, Op_RegF, 17, VR17->as_VMReg() );
347 reg_def VR17_H(SOC, SOC, Op_RegF, 17, VR17->as_VMReg()->next() );
348 reg_def VR17_J(SOC, SOC, Op_RegF, 17, VR17->as_VMReg()->next(2));
349 reg_def VR17_K(SOC, SOC, Op_RegF, 17, VR17->as_VMReg()->next(3));
350
351 reg_def VR18 (SOC, SOC, Op_RegF, 18, VR18->as_VMReg() );
352 reg_def VR18_H(SOC, SOC, Op_RegF, 18, VR18->as_VMReg()->next() );
353 reg_def VR18_J(SOC, SOC, Op_RegF, 18, VR18->as_VMReg()->next(2));
354 reg_def VR18_K(SOC, SOC, Op_RegF, 18, VR18->as_VMReg()->next(3));
355
356 reg_def VR19 (SOC, SOC, Op_RegF, 19, VR19->as_VMReg() );
357 reg_def VR19_H(SOC, SOC, Op_RegF, 19, VR19->as_VMReg()->next() );
358 reg_def VR19_J(SOC, SOC, Op_RegF, 19, VR19->as_VMReg()->next(2));
359 reg_def VR19_K(SOC, SOC, Op_RegF, 19, VR19->as_VMReg()->next(3));
360
361 reg_def VR20 (SOC, SOE, Op_RegF, 20, VR20->as_VMReg() );
362 reg_def VR20_H(SOC, SOE, Op_RegF, 20, VR20->as_VMReg()->next() );
363 reg_def VR20_J(SOC, SOE, Op_RegF, 20, VR20->as_VMReg()->next(2));
364 reg_def VR20_K(SOC, SOE, Op_RegF, 20, VR20->as_VMReg()->next(3));
365
366 reg_def VR21 (SOC, SOE, Op_RegF, 21, VR21->as_VMReg() );
367 reg_def VR21_H(SOC, SOE, Op_RegF, 21, VR21->as_VMReg()->next() );
368 reg_def VR21_J(SOC, SOE, Op_RegF, 21, VR21->as_VMReg()->next(2));
369 reg_def VR21_K(SOC, SOE, Op_RegF, 21, VR21->as_VMReg()->next(3));
370
371 reg_def VR22 (SOC, SOE, Op_RegF, 22, VR22->as_VMReg() );
372 reg_def VR22_H(SOC, SOE, Op_RegF, 22, VR22->as_VMReg()->next() );
373 reg_def VR22_J(SOC, SOE, Op_RegF, 22, VR22->as_VMReg()->next(2));
374 reg_def VR22_K(SOC, SOE, Op_RegF, 22, VR22->as_VMReg()->next(3));
375
376 reg_def VR23 (SOC, SOE, Op_RegF, 23, VR23->as_VMReg() );
377 reg_def VR23_H(SOC, SOE, Op_RegF, 23, VR23->as_VMReg()->next() );
378 reg_def VR23_J(SOC, SOE, Op_RegF, 23, VR23->as_VMReg()->next(2));
379 reg_def VR23_K(SOC, SOE, Op_RegF, 23, VR23->as_VMReg()->next(3));
380
381 reg_def VR24 (SOC, SOE, Op_RegF, 24, VR24->as_VMReg() );
382 reg_def VR24_H(SOC, SOE, Op_RegF, 24, VR24->as_VMReg()->next() );
383 reg_def VR24_J(SOC, SOE, Op_RegF, 24, VR24->as_VMReg()->next(2));
384 reg_def VR24_K(SOC, SOE, Op_RegF, 24, VR24->as_VMReg()->next(3));
385
386 reg_def VR25 (SOC, SOE, Op_RegF, 25, VR25->as_VMReg() );
387 reg_def VR25_H(SOC, SOE, Op_RegF, 25, VR25->as_VMReg()->next() );
388 reg_def VR25_J(SOC, SOE, Op_RegF, 25, VR25->as_VMReg()->next(2));
389 reg_def VR25_K(SOC, SOE, Op_RegF, 25, VR25->as_VMReg()->next(3));
390
391 reg_def VR26 (SOC, SOE, Op_RegF, 26, VR26->as_VMReg() );
392 reg_def VR26_H(SOC, SOE, Op_RegF, 26, VR26->as_VMReg()->next() );
393 reg_def VR26_J(SOC, SOE, Op_RegF, 26, VR26->as_VMReg()->next(2));
394 reg_def VR26_K(SOC, SOE, Op_RegF, 26, VR26->as_VMReg()->next(3));
395
396 reg_def VR27 (SOC, SOE, Op_RegF, 27, VR27->as_VMReg() );
397 reg_def VR27_H(SOC, SOE, Op_RegF, 27, VR27->as_VMReg()->next() );
398 reg_def VR27_J(SOC, SOE, Op_RegF, 27, VR27->as_VMReg()->next(2));
399 reg_def VR27_K(SOC, SOE, Op_RegF, 27, VR27->as_VMReg()->next(3));
400
401 reg_def VR28 (SOC, SOE, Op_RegF, 28, VR28->as_VMReg() );
402 reg_def VR28_H(SOC, SOE, Op_RegF, 28, VR28->as_VMReg()->next() );
403 reg_def VR28_J(SOC, SOE, Op_RegF, 28, VR28->as_VMReg()->next(2));
404 reg_def VR28_K(SOC, SOE, Op_RegF, 28, VR28->as_VMReg()->next(3));
405
406 reg_def VR29 (SOC, SOE, Op_RegF, 29, VR29->as_VMReg() );
407 reg_def VR29_H(SOC, SOE, Op_RegF, 29, VR29->as_VMReg()->next() );
408 reg_def VR29_J(SOC, SOE, Op_RegF, 29, VR29->as_VMReg()->next(2));
409 reg_def VR29_K(SOC, SOE, Op_RegF, 29, VR29->as_VMReg()->next(3));
410
411 reg_def VR30 (SOC, SOE, Op_RegF, 30, VR30->as_VMReg() );
412 reg_def VR30_H(SOC, SOE, Op_RegF, 30, VR30->as_VMReg()->next() );
413 reg_def VR30_J(SOC, SOE, Op_RegF, 30, VR30->as_VMReg()->next(2));
414 reg_def VR30_K(SOC, SOE, Op_RegF, 30, VR30->as_VMReg()->next(3));
415
416 reg_def VR31 (SOC, SOE, Op_RegF, 31, VR31->as_VMReg() );
417 reg_def VR31_H(SOC, SOE, Op_RegF, 31, VR31->as_VMReg()->next() );
418 reg_def VR31_J(SOC, SOE, Op_RegF, 31, VR31->as_VMReg()->next(2));
419 reg_def VR31_K(SOC, SOE, Op_RegF, 31, VR31->as_VMReg()->next(3));
420
421 // ----------------------------
422 // Specify priority of register selection within phases of register
423 // allocation. Highest priority is first. A useful heuristic is to
424 // give registers a low priority when they are required by machine
425 // instructions, like EAX and EDX on I486, and choose no-save registers
426 // before save-on-call, & save-on-call before save-on-entry. Registers
427 // which participate in fixed calling sequences should come last.
428 // Registers which are used as pairs must fall on an even boundary.
429
430 // It's worth about 1% on SPEC geomean to get this right.
431
432 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
433 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
434 // R3_num. Therefore, R3_num may not be (and in reality is not)
435 // the same as R3->encoding()! Furthermore, we cannot make any
436 // assumptions on ordering, e.g. R3_num may be less than R2_num.
437 // Additionally, the function
438 // static enum RC rc_class(OptoReg::Name reg )
439 // maps a given <register>_num value to its chunk type (except for flags)
440 // and its current implementation relies on chunk0 and chunk1 having a
441 // size of 64 each.
442
443 // If you change this allocation class, please have a look at the
444 // default values for the parameters RoundRobinIntegerRegIntervalStart
445 // and RoundRobinFloatRegIntervalStart
446
447 alloc_class chunk0 (
448 // Chunk0 contains *all* 64 integer registers halves.
449
450 // "non-volatile" registers
451 R14, R14_H,
452 R15, R15_H,
453 R17, R17_H,
454 R18, R18_H,
455 R19, R19_H,
456 R20, R20_H,
457 R21, R21_H,
458 R22, R22_H,
459 R23, R23_H,
460 R24, R24_H,
461 R25, R25_H,
462 R26, R26_H,
463 R27, R27_H,
464 R28, R28_H,
465 R29, R29_H,
466 R30, R30_H,
467 R31, R31_H,
468
469 // scratch/special registers
470 R11, R11_H,
471 R12, R12_H,
472
473 // argument registers
474 R10, R10_H,
475 R9, R9_H,
476 R8, R8_H,
477 R7, R7_H,
478 R6, R6_H,
479 R5, R5_H,
480 R4, R4_H,
481 R3, R3_H,
482
483 // special registers, not available for allocation
484 R16, R16_H, // R16_thread
485 R13, R13_H, // system thread id
486 R2, R2_H, // may be used for TOC
487 R1, R1_H, // SP
488 R0, R0_H // R0 (scratch)
489 );
490
491 // If you change this allocation class, please have a look at the
492 // default values for the parameters RoundRobinIntegerRegIntervalStart
493 // and RoundRobinFloatRegIntervalStart
494
495 alloc_class chunk1 (
496 // Chunk1 contains *all* 64 floating-point registers halves.
497
498 // scratch register
499 F0, F0_H,
500
501 // argument registers
502 F13, F13_H,
503 F12, F12_H,
504 F11, F11_H,
505 F10, F10_H,
506 F9, F9_H,
507 F8, F8_H,
508 F7, F7_H,
509 F6, F6_H,
510 F5, F5_H,
511 F4, F4_H,
512 F3, F3_H,
513 F2, F2_H,
514 F1, F1_H,
515
516 // non-volatile registers
517 F14, F14_H,
518 F15, F15_H,
519 F16, F16_H,
520 F17, F17_H,
521 F18, F18_H,
522 F19, F19_H,
523 F20, F20_H,
524 F21, F21_H,
525 F22, F22_H,
526 F23, F23_H,
527 F24, F24_H,
528 F25, F25_H,
529 F26, F26_H,
530 F27, F27_H,
531 F28, F28_H,
532 F29, F29_H,
533 F30, F30_H,
534 F31, F31_H
535 );
536
537 alloc_class chunk2 (
538 VR0 , VR0_H , VR0_J , VR0_K ,
539 VR1 , VR1_H , VR1_J , VR1_K ,
540 VR2 , VR2_H , VR2_J , VR2_K ,
541 VR3 , VR3_H , VR3_J , VR3_K ,
542 VR4 , VR4_H , VR4_J , VR4_K ,
543 VR5 , VR5_H , VR5_J , VR5_K ,
544 VR6 , VR6_H , VR6_J , VR6_K ,
545 VR7 , VR7_H , VR7_J , VR7_K ,
546 VR8 , VR8_H , VR8_J , VR8_K ,
547 VR9 , VR9_H , VR9_J , VR9_K ,
548 VR10, VR10_H, VR10_J, VR10_K,
549 VR11, VR11_H, VR11_J, VR11_K,
550 VR12, VR12_H, VR12_J, VR12_K,
551 VR13, VR13_H, VR13_J, VR13_K,
552 VR14, VR14_H, VR14_J, VR14_K,
553 VR15, VR15_H, VR15_J, VR15_K,
554 VR16, VR16_H, VR16_J, VR16_K,
555 VR17, VR17_H, VR17_J, VR17_K,
556 VR18, VR18_H, VR18_J, VR18_K,
557 VR19, VR19_H, VR19_J, VR19_K,
558 VR20, VR20_H, VR20_J, VR20_K,
559 VR21, VR21_H, VR21_J, VR21_K,
560 VR22, VR22_H, VR22_J, VR22_K,
561 VR23, VR23_H, VR23_J, VR23_K,
562 VR24, VR24_H, VR24_J, VR24_K,
563 VR25, VR25_H, VR25_J, VR25_K,
564 VR26, VR26_H, VR26_J, VR26_K,
565 VR27, VR27_H, VR27_J, VR27_K,
566 VR28, VR28_H, VR28_J, VR28_K,
567 VR29, VR29_H, VR29_J, VR29_K,
568 VR30, VR30_H, VR30_J, VR30_K,
569 VR31, VR31_H, VR31_J, VR31_K
570 );
571
572 alloc_class chunk3 (
573 // Chunk2 contains *all* 8 condition code registers.
574 CR0,
575 CR1,
576 CR2,
577 CR3,
578 CR4,
579 CR5,
580 CR6,
581 CR7
582 );
583
584 alloc_class chunk4 (
585 // special registers
586 // These registers are not allocated, but used for nodes generated by postalloc expand.
587 SR_XER,
588 SR_LR,
589 SR_CTR,
590 SR_VRSAVE,
591 SR_SPEFSCR,
592 SR_PPR
593 );
594
595 //-------Architecture Description Register Classes-----------------------
596
597 // Several register classes are automatically defined based upon
598 // information in this architecture description.
599
600 // 1) reg_class inline_cache_reg ( as defined in frame section )
601 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
602 //
603
604 // ----------------------------
605 // 32 Bit Register Classes
606 // ----------------------------
607
608 // We specify registers twice, once as read/write, and once read-only.
609 // We use the read-only registers for source operands. With this, we
610 // can include preset read only registers in this class, as a hard-coded
611 // '0'-register. (We used to simulate this on ppc.)
612
613 // 32 bit registers that can be read and written i.e. these registers
614 // can be dest (or src) of normal instructions.
615 reg_class bits32_reg_rw(
616 /*R0*/ // R0
617 /*R1*/ // SP
618 R2, // TOC
619 R3,
620 R4,
621 R5,
622 R6,
623 R7,
624 R8,
625 R9,
626 R10,
627 R11,
628 R12,
629 /*R13*/ // system thread id
630 R14,
631 R15,
632 /*R16*/ // R16_thread
633 R17,
634 R18,
635 R19,
636 R20,
637 R21,
638 R22,
639 R23,
640 R24,
641 R25,
642 R26,
643 R27,
644 R28,
645 /*R29,*/ // global TOC
646 R30,
647 R31
648 );
649
650 // 32 bit registers that can only be read i.e. these registers can
651 // only be src of all instructions.
652 reg_class bits32_reg_ro(
653 /*R0*/ // R0
654 /*R1*/ // SP
655 R2 // TOC
656 R3,
657 R4,
658 R5,
659 R6,
660 R7,
661 R8,
662 R9,
663 R10,
664 R11,
665 R12,
666 /*R13*/ // system thread id
667 R14,
668 R15,
669 /*R16*/ // R16_thread
670 R17,
671 R18,
672 R19,
673 R20,
674 R21,
675 R22,
676 R23,
677 R24,
678 R25,
679 R26,
680 R27,
681 R28,
682 /*R29,*/
683 R30,
684 R31
685 );
686
687 reg_class rscratch1_bits32_reg(R11);
688 reg_class rscratch2_bits32_reg(R12);
689 reg_class rarg1_bits32_reg(R3);
690 reg_class rarg2_bits32_reg(R4);
691 reg_class rarg3_bits32_reg(R5);
692 reg_class rarg4_bits32_reg(R6);
693
694 // ----------------------------
695 // 64 Bit Register Classes
696 // ----------------------------
697 // 64-bit build means 64-bit pointers means hi/lo pairs
698
699 reg_class rscratch1_bits64_reg(R11_H, R11);
700 reg_class rscratch2_bits64_reg(R12_H, R12);
701 reg_class rarg1_bits64_reg(R3_H, R3);
702 reg_class rarg2_bits64_reg(R4_H, R4);
703 reg_class rarg3_bits64_reg(R5_H, R5);
704 reg_class rarg4_bits64_reg(R6_H, R6);
705 reg_class rarg5_bits64_reg(R7_H, R7);
706 reg_class rarg6_bits64_reg(R8_H, R8);
707 // Thread register, 'written' by tlsLoadP, see there.
708 reg_class thread_bits64_reg(R16_H, R16);
709
710 reg_class r19_bits64_reg(R19_H, R19);
711
712 // 64 bit registers that can be read and written i.e. these registers
713 // can be dest (or src) of normal instructions.
714 reg_class bits64_reg_rw(
715 /*R0_H, R0*/ // R0
716 /*R1_H, R1*/ // SP
717 R2_H, R2, // TOC
718 R3_H, R3,
719 R4_H, R4,
720 R5_H, R5,
721 R6_H, R6,
722 R7_H, R7,
723 R8_H, R8,
724 R9_H, R9,
725 R10_H, R10,
726 R11_H, R11,
727 R12_H, R12,
728 /*R13_H, R13*/ // system thread id
729 R14_H, R14,
730 R15_H, R15,
731 /*R16_H, R16*/ // R16_thread
732 R17_H, R17,
733 R18_H, R18,
734 R19_H, R19,
735 R20_H, R20,
736 R21_H, R21,
737 R22_H, R22,
738 R23_H, R23,
739 R24_H, R24,
740 R25_H, R25,
741 R26_H, R26,
742 R27_H, R27,
743 R28_H, R28,
744 /*R29_H, R29,*/
745 R30_H, R30,
746 R31_H, R31
747 );
748
749 // 64 bit registers used excluding r2, r11 and r12
750 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
751 // r2, r11 and r12 internally.
752 reg_class bits64_reg_leaf_call(
753 /*R0_H, R0*/ // R0
754 /*R1_H, R1*/ // SP
755 /*R2_H, R2*/ // TOC
756 R3_H, R3,
757 R4_H, R4,
758 R5_H, R5,
759 R6_H, R6,
760 R7_H, R7,
761 R8_H, R8,
762 R9_H, R9,
763 R10_H, R10,
764 /*R11_H, R11*/
765 /*R12_H, R12*/
766 /*R13_H, R13*/ // system thread id
767 R14_H, R14,
768 R15_H, R15,
769 /*R16_H, R16*/ // R16_thread
770 R17_H, R17,
771 R18_H, R18,
772 R19_H, R19,
773 R20_H, R20,
774 R21_H, R21,
775 R22_H, R22,
776 R23_H, R23,
777 R24_H, R24,
778 R25_H, R25,
779 R26_H, R26,
780 R27_H, R27,
781 R28_H, R28,
782 /*R29_H, R29,*/
783 R30_H, R30,
784 R31_H, R31
785 );
786
787 // Used to hold the TOC to avoid collisions with expanded DynamicCall
788 // which uses r19 as inline cache internally and expanded LeafCall which uses
789 // r2, r11 and r12 internally.
790 reg_class bits64_constant_table_base(
791 /*R0_H, R0*/ // R0
792 /*R1_H, R1*/ // SP
793 /*R2_H, R2*/ // TOC
794 R3_H, R3,
795 R4_H, R4,
796 R5_H, R5,
797 R6_H, R6,
798 R7_H, R7,
799 R8_H, R8,
800 R9_H, R9,
801 R10_H, R10,
802 /*R11_H, R11*/
803 /*R12_H, R12*/
804 /*R13_H, R13*/ // system thread id
805 R14_H, R14,
806 R15_H, R15,
807 /*R16_H, R16*/ // R16_thread
808 R17_H, R17,
809 R18_H, R18,
810 /*R19_H, R19*/
811 R20_H, R20,
812 R21_H, R21,
813 R22_H, R22,
814 R23_H, R23,
815 R24_H, R24,
816 R25_H, R25,
817 R26_H, R26,
818 R27_H, R27,
819 R28_H, R28,
820 /*R29_H, R29,*/
821 R30_H, R30,
822 R31_H, R31
823 );
824
825 // 64 bit registers that can only be read i.e. these registers can
826 // only be src of all instructions.
827 reg_class bits64_reg_ro(
828 /*R0_H, R0*/ // R0
829 R1_H, R1,
830 R2_H, R2, // TOC
831 R3_H, R3,
832 R4_H, R4,
833 R5_H, R5,
834 R6_H, R6,
835 R7_H, R7,
836 R8_H, R8,
837 R9_H, R9,
838 R10_H, R10,
839 R11_H, R11,
840 R12_H, R12,
841 /*R13_H, R13*/ // system thread id
842 R14_H, R14,
843 R15_H, R15,
844 R16_H, R16, // R16_thread
845 R17_H, R17,
846 R18_H, R18,
847 R19_H, R19,
848 R20_H, R20,
849 R21_H, R21,
850 R22_H, R22,
851 R23_H, R23,
852 R24_H, R24,
853 R25_H, R25,
854 R26_H, R26,
855 R27_H, R27,
856 R28_H, R28,
857 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
858 R30_H, R30,
859 R31_H, R31
860 );
861
862
863 // ----------------------------
864 // Special Class for Condition Code Flags Register
865
866 reg_class int_flags(
867 /*CR0*/ // scratch
868 /*CR1*/ // scratch
869 /*CR2*/ // nv!
870 /*CR3*/ // nv!
871 /*CR4*/ // nv!
872 CR5,
873 CR6,
874 CR7
875 );
876
877 reg_class int_flags_ro(
878 CR0,
879 CR1,
880 CR2,
881 CR3,
882 CR4,
883 CR5,
884 CR6,
885 CR7
886 );
887
888 reg_class int_flags_CR0(CR0);
889 reg_class int_flags_CR1(CR1);
890 reg_class int_flags_CR6(CR6);
891 reg_class ctr_reg(SR_CTR);
892
893 // ----------------------------
894 // Float Register Classes
895 // ----------------------------
896
897 reg_class flt_reg(
898 F0,
899 F1,
900 F2,
901 F3,
902 F4,
903 F5,
904 F6,
905 F7,
906 F8,
907 F9,
908 F10,
909 F11,
910 F12,
911 F13,
912 F14, // nv!
913 F15, // nv!
914 F16, // nv!
915 F17, // nv!
916 F18, // nv!
917 F19, // nv!
918 F20, // nv!
919 F21, // nv!
920 F22, // nv!
921 F23, // nv!
922 F24, // nv!
923 F25, // nv!
924 F26, // nv!
925 F27, // nv!
926 F28, // nv!
927 F29, // nv!
928 F30, // nv!
929 F31 // nv!
930 );
931
932 // Double precision float registers have virtual `high halves' that
933 // are needed by the allocator.
934 reg_class dbl_reg(
935 F0, F0_H,
936 F1, F1_H,
937 F2, F2_H,
938 F3, F3_H,
939 F4, F4_H,
940 F5, F5_H,
941 F6, F6_H,
942 F7, F7_H,
943 F8, F8_H,
944 F9, F9_H,
945 F10, F10_H,
946 F11, F11_H,
947 F12, F12_H,
948 F13, F13_H,
949 F14, F14_H, // nv!
950 F15, F15_H, // nv!
951 F16, F16_H, // nv!
952 F17, F17_H, // nv!
953 F18, F18_H, // nv!
954 F19, F19_H, // nv!
955 F20, F20_H, // nv!
956 F21, F21_H, // nv!
957 F22, F22_H, // nv!
958 F23, F23_H, // nv!
959 F24, F24_H, // nv!
960 F25, F25_H, // nv!
961 F26, F26_H, // nv!
962 F27, F27_H, // nv!
963 F28, F28_H, // nv!
964 F29, F29_H, // nv!
965 F30, F30_H, // nv!
966 F31, F31_H // nv!
967 );
968
969 // ----------------------------
970 // Vector-Scalar Register Class
971 // ----------------------------
972
973 reg_class v_reg(
974 VR0 , VR0_H , VR0_J , VR0_K ,
975 VR1 , VR1_H , VR1_J , VR1_K ,
976 VR2 , VR2_H , VR2_J , VR2_K ,
977 VR3 , VR3_H , VR3_J , VR3_K ,
978 VR4 , VR4_H , VR4_J , VR4_K ,
979 VR5 , VR5_H , VR5_J , VR5_K ,
980 VR6 , VR6_H , VR6_J , VR6_K ,
981 VR7 , VR7_H , VR7_J , VR7_K ,
982 VR8 , VR8_H , VR8_J , VR8_K ,
983 VR9 , VR9_H , VR9_J , VR9_K ,
984 VR10, VR10_H, VR10_J, VR10_K,
985 VR11, VR11_H, VR11_J, VR11_K,
986 VR12, VR12_H, VR12_J, VR12_K,
987 VR13, VR13_H, VR13_J, VR13_K,
988 VR14, VR14_H, VR14_J, VR14_K,
989 VR15, VR15_H, VR15_J, VR15_K,
990 VR16, VR16_H, VR16_J, VR16_K,
991 VR17, VR17_H, VR17_J, VR17_K,
992 VR18, VR18_H, VR18_J, VR18_K,
993 VR19, VR19_H, VR19_J, VR19_K,
994 VR20, VR20_H, VR20_J, VR20_K,
995 VR21, VR21_H, VR21_J, VR21_K,
996 VR22, VR22_H, VR22_J, VR22_K,
997 VR23, VR23_H, VR23_J, VR23_K,
998 VR24, VR24_H, VR24_J, VR24_K,
999 VR25, VR25_H, VR25_J, VR25_K,
1000 VR26, VR26_H, VR26_J, VR26_K,
1001 VR27, VR27_H, VR27_J, VR27_K,
1002 VR28, VR28_H, VR28_J, VR28_K,
1003 VR29, VR29_H, VR29_J, VR29_K,
1004 VR30, VR30_H, VR30_J, VR30_K,
1005 VR31, VR31_H, VR31_J, VR31_K
1006 );
1007
1008 %}
1009
1010 //----------DEFINITION BLOCK---------------------------------------------------
1011 // Define name --> value mappings to inform the ADLC of an integer valued name
1012 // Current support includes integer values in the range [0, 0x7FFFFFFF]
1013 // Format:
1014 // int_def <name> ( <int_value>, <expression>);
1015 // Generated Code in ad_<arch>.hpp
1016 // #define <name> (<expression>)
1017 // // value == <int_value>
1018 // Generated code in ad_<arch>.cpp adlc_verification()
1019 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
1020 //
1021 definitions %{
1022 // The default cost (of an ALU instruction).
1023 int_def DEFAULT_COST_LOW ( 30, 30);
1024 int_def DEFAULT_COST ( 100, 100);
1025 int_def HUGE_COST (1000000, 1000000);
1026
1027 // Memory refs
1028 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
1029 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
1030
1031 // Branches are even more expensive.
1032 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
1033 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
1034 %}
1035
1036
1037 //----------SOURCE BLOCK-------------------------------------------------------
1038 // This is a block of C++ code which provides values, functions, and
1039 // definitions necessary in the rest of the architecture description.
1040 source_hpp %{
1041 // Header information of the source block.
1042 // Method declarations/definitions which are used outside
1043 // the ad-scope can conveniently be defined here.
1044 //
1045 // To keep related declarations/definitions/uses close together,
1046 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1047
1048 #include "opto/convertnode.hpp"
1049
1050 // Returns true if Node n is followed by a MemBar node that
1051 // will do an acquire. If so, this node must not do the acquire
1052 // operation.
1053 bool followed_by_acquire(const Node *n);
1054 %}
1055
1056 source %{
1057
1058 #include "opto/c2_CodeStubs.hpp"
1059 #include "oops/klass.inline.hpp"
1060
1061 void PhaseOutput::pd_perform_mach_node_analysis() {
1062 }
1063
1064 int MachNode::pd_alignment_required() const {
1065 return 1;
1066 }
1067
1068 int MachNode::compute_padding(int current_offset) const {
1069 return 0;
1070 }
1071
1072 // Should the matcher clone input 'm' of node 'n'?
1073 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
1074 if (is_encode_and_store_pattern(n, m)) {
1075 mstack.push(m, Visit);
1076 return true;
1077 }
1078 return false;
1079 }
1080
1081 // Should the Matcher clone shifts on addressing modes, expecting them
1082 // to be subsumed into complex addressing expressions or compute them
1083 // into registers?
1084 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1085 return clone_base_plus_offset_address(m, mstack, address_visited);
1086 }
1087
1088 // Optimize load-acquire.
1089 //
1090 // Check if acquire is unnecessary due to following operation that does
1091 // acquire anyways.
1092 // Walk the pattern:
1093 //
1094 // n: Load.acq
1095 // |
1096 // MemBarAcquire
1097 // | |
1098 // Proj(ctrl) Proj(mem)
1099 // | |
1100 // MemBarRelease/Volatile
1101 //
1102 bool followed_by_acquire(const Node *load) {
1103 assert(load->is_Load(), "So far implemented only for loads.");
1104
1105 // Find MemBarAcquire.
1106 const Node *mba = nullptr;
1107 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
1108 const Node *out = load->fast_out(i);
1109 if (out->Opcode() == Op_MemBarAcquire) {
1110 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
1111 mba = out;
1112 break;
1113 }
1114 }
1115 if (!mba) return false;
1116
1117 // Find following MemBar node.
1118 //
1119 // The following node must be reachable by control AND memory
1120 // edge to assure no other operations are in between the two nodes.
1121 //
1122 // So first get the Proj node, mem_proj, to use it to iterate forward.
1123 Node *mem_proj = nullptr;
1124 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
1125 mem_proj = mba->fast_out(i); // Runs out of bounds and asserts if Proj not found.
1126 assert(mem_proj->is_Proj(), "only projections here");
1127 ProjNode *proj = mem_proj->as_Proj();
1128 if (proj->_con == TypeFunc::Memory &&
1129 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
1130 break;
1131 }
1132 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
1133
1134 // Search MemBar behind Proj. If there are other memory operations
1135 // behind the Proj we lost.
1136 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
1137 Node *x = mem_proj->fast_out(j);
1138 // Proj might have an edge to a store or load node which precedes the membar.
1139 if (x->is_Mem()) return false;
1140
1141 // On PPC64 release and volatile are implemented by an instruction
1142 // that also has acquire semantics. I.e. there is no need for an
1143 // acquire before these.
1144 int xop = x->Opcode();
1145 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
1146 // Make sure we're not missing Call/Phi/MergeMem by checking
1147 // control edges. The control edge must directly lead back
1148 // to the MemBarAcquire
1149 Node *ctrl_proj = x->in(0);
1150 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
1151 return true;
1152 }
1153 }
1154 }
1155
1156 return false;
1157 }
1158
1159 #define __ masm->
1160
1161 // Tertiary op of a LoadP or StoreP encoding.
1162 #define REGP_OP true
1163
1164 // ****************************************************************************
1165
1166 // REQUIRED FUNCTIONALITY
1167
1168 // !!!!! Special hack to get all type of calls to specify the byte offset
1169 // from the start of the call to the point where the return address
1170 // will point.
1171
1172 // PPC port: Removed use of lazy constant construct.
1173
1174 int MachCallStaticJavaNode::ret_addr_offset() const {
1175 // It's only a single branch-and-link instruction.
1176 return 4;
1177 }
1178
1179 int MachCallDynamicJavaNode::ret_addr_offset() const {
1180 return 12;
1181 }
1182
1183 int MachCallRuntimeNode::ret_addr_offset() const {
1184 if (rule() == CallRuntimeDirect_rule) {
1185 // CallRuntimeDirectNode uses call_c.
1186 #if defined(ABI_ELFv2)
1187 return 28;
1188 #else
1189 return 40;
1190 #endif
1191 }
1192 assert(rule() == CallLeafDirect_rule, "unexpected node with rule %u", rule());
1193 // CallLeafDirectNode uses bl.
1194 return 4;
1195 }
1196
1197 //=============================================================================
1198
1199 // condition code conversions
1200
1201 static int cc_to_boint(int cc) {
1202 return Assembler::bcondCRbiIs0 | (cc & 8);
1203 }
1204
1205 static int cc_to_inverse_boint(int cc) {
1206 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1207 }
1208
1209 static int cc_to_biint(int cc, int flags_reg) {
1210 return (flags_reg << 2) | (cc & 3);
1211 }
1212
1213 //=============================================================================
1214
1215 // Compute padding required for nodes which need alignment. The padding
1216 // is the number of bytes (not instructions) which will be inserted before
1217 // the instruction. The padding must match the size of a NOP instruction.
1218
1219 // Add nop if a prefixed (two-word) instruction is going to cross a 64-byte boundary.
1220 // (See Section 1.6 of Power ISA Version 3.1)
1221 static int compute_prefix_padding(int current_offset) {
1222 assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
1223 "Code buffer must be aligned to a multiple of 64 bytes");
1224 if (is_aligned(current_offset + BytesPerInstWord, 64)) {
1225 return BytesPerInstWord;
1226 }
1227 return 0;
1228 }
1229
1230 int loadConI32Node::compute_padding(int current_offset) const {
1231 return compute_prefix_padding(current_offset);
1232 }
1233
1234 int loadConL34Node::compute_padding(int current_offset) const {
1235 return compute_prefix_padding(current_offset);
1236 }
1237
1238 int addI_reg_imm32Node::compute_padding(int current_offset) const {
1239 return compute_prefix_padding(current_offset);
1240 }
1241
1242 int addL_reg_imm34Node::compute_padding(int current_offset) const {
1243 return compute_prefix_padding(current_offset);
1244 }
1245
1246 int addP_reg_imm34Node::compute_padding(int current_offset) const {
1247 return compute_prefix_padding(current_offset);
1248 }
1249
1250 int cmprb_Whitespace_reg_reg_prefixedNode::compute_padding(int current_offset) const {
1251 return compute_prefix_padding(current_offset);
1252 }
1253
1254
1255 //=============================================================================
1256
1257 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1258 void emit_break(C2_MacroAssembler *masm) {
1259 __ illtrap();
1260 }
1261
1262 #ifndef PRODUCT
1263 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1264 st->print("BREAKPOINT");
1265 }
1266 #endif
1267
1268 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1269 emit_break(masm);
1270 }
1271
1272 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1273 return MachNode::size(ra_);
1274 }
1275
1276 //=============================================================================
1277
1278 void emit_nop(C2_MacroAssembler *masm) {
1279 __ nop();
1280 }
1281
1282 static inline void emit_long(C2_MacroAssembler *masm, int value) {
1283 *((int*)(__ pc())) = value;
1284 __ set_inst_end(__ pc() + BytesPerInstWord);
1285 }
1286
1287 //=============================================================================
1288
1289 %} // interrupt source
1290
1291 source_hpp %{ // Header information of the source block.
1292
1293 //--------------------------------------------------------------
1294 //---< Used for optimization in Compile::Shorten_branches >---
1295 //--------------------------------------------------------------
1296
1297 class C2_MacroAssembler;
1298
1299 class CallStubImpl {
1300
1301 public:
1302
1303 // Size of call trampoline stub.
1304 // This doesn't need to be accurate to the byte, but it
1305 // must be larger than or equal to the real size of the stub.
1306 static uint size_call_trampoline() {
1307 return MacroAssembler::trampoline_stub_size;
1308 }
1309
1310 // number of relocations needed by a call trampoline stub
1311 static uint reloc_call_trampoline() {
1312 return 5;
1313 }
1314
1315 };
1316
1317 %} // end source_hpp
1318
1319 source %{
1320
1321 // Factory for creating loadConL* nodes for large/small constant pool.
1322
1323 static inline jlong replicate_immF(float con) {
1324 // Replicate float con 2 times and pack into vector.
1325 int val = *((int*)&con);
1326 jlong lval = val;
1327 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1328 return lval;
1329 }
1330
1331 //=============================================================================
1332
1333 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1334 int ConstantTable::calculate_table_base_offset() const {
1335 return 0; // absolute addressing, no offset
1336 }
1337
1338 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1339 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1340 iRegLdstOper *op_dst = new iRegLdstOper();
1341 MachNode *m1 = new loadToc_hiNode();
1342 MachNode *m2 = new loadToc_loNode();
1343
1344 m1->add_req(nullptr);
1345 m2->add_req(nullptr, m1);
1346 m1->_opnds[0] = op_dst;
1347 m2->_opnds[0] = op_dst;
1348 m2->_opnds[1] = op_dst;
1349 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1350 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1351 nodes->push(m1);
1352 nodes->push(m2);
1353 }
1354
1355 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1356 // Is postalloc expanded.
1357 ShouldNotReachHere();
1358 }
1359
1360 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1361 return 0;
1362 }
1363
1364 #ifndef PRODUCT
1365 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1366 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1367 }
1368 #endif
1369
1370 //=============================================================================
1371
1372 #ifndef PRODUCT
1373 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1374 Compile* C = ra_->C;
1375 const long framesize = C->output()->frame_slots() << LogBytesPerInt;
1376
1377 st->print("PROLOG\n\t");
1378 if (C->output()->need_stack_bang(framesize)) {
1379 st->print("stack_overflow_check\n\t");
1380 }
1381
1382 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1383 st->print("save return pc\n\t");
1384 st->print("push frame %ld\n\t", -framesize);
1385 }
1386
1387 if (C->stub_function() == nullptr) {
1388 st->print("nmethod entry barrier\n\t");
1389 }
1390 }
1391 #endif
1392
1393 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1394 Compile* C = ra_->C;
1395
1396 const long framesize = C->output()->frame_size_in_bytes();
1397 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1398
1399 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1400
1401 const Register return_pc = R20; // Must match return_addr() in frame section.
1402 const Register callers_sp = R21;
1403 const Register push_frame_temp = R22;
1404 const Register toc_temp = R23;
1405 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1406
1407 if (!method_is_frameless) {
1408 // Get return pc.
1409 __ mflr(return_pc);
1410 }
1411
1412 if (C->clinit_barrier_on_entry()) {
1413 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1414
1415 Label L_skip_barrier;
1416 Register klass = toc_temp;
1417
1418 // Notify OOP recorder (don't need the relocation)
1419 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
1420 __ load_const_optimized(klass, md.value(), R0);
1421 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
1422
1423 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
1424 __ mtctr(klass);
1425 __ bctr();
1426
1427 __ bind(L_skip_barrier);
1428 }
1429
1430 // Calls to C2R adapters often do not accept exceptional returns.
1431 // We require that their callers must bang for them. But be
1432 // careful, because some VM calls (such as call site linkage) can
1433 // use several kilobytes of stack. But the stack safety zone should
1434 // account for that. See bugs 4446381, 4468289, 4497237.
1435
1436 int bangsize = C->output()->bang_size_in_bytes();
1437 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1438 if (C->output()->need_stack_bang(bangsize)) {
1439 // Unfortunately we cannot use the function provided in
1440 // assembler.cpp as we have to emulate the pipes. So I had to
1441 // insert the code of generate_stack_overflow_check(), see
1442 // assembler.cpp for some illuminative comments.
1443 const int page_size = os::vm_page_size();
1444 int bang_end = StackOverflow::stack_shadow_zone_size();
1445
1446 // This is how far the previous frame's stack banging extended.
1447 const int bang_end_safe = bang_end;
1448
1449 if (bangsize > page_size) {
1450 bang_end += bangsize;
1451 }
1452
1453 int bang_offset = bang_end_safe;
1454
1455 while (bang_offset <= bang_end) {
1456 // Need at least one stack bang at end of shadow zone.
1457
1458 // Again I had to copy code, this time from assembler_ppc.cpp,
1459 // bang_stack_with_offset - see there for comments.
1460
1461 // Stack grows down, caller passes positive offset.
1462 assert(bang_offset > 0, "must bang with positive offset");
1463
1464 long stdoffset = -bang_offset;
1465
1466 if (Assembler::is_simm(stdoffset, 16)) {
1467 // Signed 16 bit offset, a simple std is ok.
1468 if (UseLoadInstructionsForStackBangingPPC64) {
1469 __ ld(R0, (int)(signed short)stdoffset, R1_SP);
1470 } else {
1471 __ std(R0, (int)(signed short)stdoffset, R1_SP);
1472 }
1473 } else if (Assembler::is_simm(stdoffset, 31)) {
1474 // Use largeoffset calculations for addis & ld/std.
1475 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1476 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1477
1478 Register tmp = R11;
1479 __ addis(tmp, R1_SP, hi);
1480 if (UseLoadInstructionsForStackBangingPPC64) {
1481 __ ld(R0, lo, tmp);
1482 } else {
1483 __ std(R0, lo, tmp);
1484 }
1485 } else {
1486 ShouldNotReachHere();
1487 }
1488
1489 bang_offset += page_size;
1490 }
1491 // R11 trashed
1492 } // C->output()->need_stack_bang(framesize)
1493
1494 unsigned int bytes = (unsigned int)framesize;
1495 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1496 ciMethod *currMethod = C->method();
1497
1498 if (!method_is_frameless) {
1499 // Get callers sp.
1500 __ mr(callers_sp, R1_SP);
1501
1502 // Push method's frame, modifies SP.
1503 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1504 // The ABI is already accounted for in 'framesize' via the
1505 // 'out_preserve' area.
1506 Register tmp = push_frame_temp;
1507 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1508 if (Assembler::is_simm(-offset, 16)) {
1509 __ stdu(R1_SP, -offset, R1_SP);
1510 } else {
1511 long x = -offset;
1512 // Had to insert load_const(tmp, -offset).
1513 __ lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1514 __ ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1515 __ sldi(tmp, tmp, 32);
1516 __ oris(tmp, tmp, (x & 0xffff0000) >> 16);
1517 __ ori( tmp, tmp, (x & 0x0000ffff));
1518
1519 __ stdux(R1_SP, R1_SP, tmp);
1520 }
1521 }
1522 #if 0 // TODO: PPC port
1523 // For testing large constant pools, emit a lot of constants to constant pool.
1524 // "Randomize" const_size.
1525 if (ConstantsALot) {
1526 const int num_consts = const_size();
1527 for (int i = 0; i < num_consts; i++) {
1528 __ long_constant(0xB0B5B00BBABE);
1529 }
1530 }
1531 #endif
1532 if (!method_is_frameless) {
1533 // Save return pc.
1534 __ std(return_pc, _abi0(lr), callers_sp);
1535 }
1536
1537 if (C->stub_function() == nullptr) {
1538 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1539 bs->nmethod_entry_barrier(masm, push_frame_temp);
1540 }
1541
1542 C->output()->set_frame_complete(__ offset());
1543 }
1544
1545 int MachPrologNode::reloc() const {
1546 // Return number of relocatable values contained in this instruction.
1547 return 1; // 1 reloc entry for load_const(toc).
1548 }
1549
1550 //=============================================================================
1551
1552 #ifndef PRODUCT
1553 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1554 Compile* C = ra_->C;
1555
1556 st->print("EPILOG\n\t");
1557 st->print("restore return pc\n\t");
1558 st->print("pop frame\n\t");
1559
1560 if (do_polling() && C->is_method_compilation()) {
1561 st->print("safepoint poll\n\t");
1562 }
1563 }
1564 #endif
1565
1566 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1567 Compile* C = ra_->C;
1568
1569 const long framesize = ((long)C->output()->frame_slots()) << LogBytesPerInt;
1570 assert(framesize >= 0, "negative frame-size?");
1571
1572 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1573 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1574 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1575 const Register temp = R12;
1576
1577 if (!method_is_frameless) {
1578 // Restore return pc relative to callers' sp.
1579 __ ld(return_pc, ((int)framesize) + _abi0(lr), R1_SP);
1580 // Move return pc to LR.
1581 __ mtlr(return_pc);
1582 // Pop frame (fixed frame-size).
1583 __ addi(R1_SP, R1_SP, (int)framesize);
1584 }
1585
1586 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1587 __ reserved_stack_check(return_pc);
1588 }
1589
1590 if (method_needs_polling) {
1591 Label dummy_label;
1592 Label* code_stub = &dummy_label;
1593 if (!UseSIGTRAP && !C->output()->in_scratch_emit_size()) {
1594 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1595 C->output()->add_stub(stub);
1596 code_stub = &stub->entry();
1597 __ relocate(relocInfo::poll_return_type);
1598 }
1599 __ safepoint_poll(*code_stub, temp, true /* at_return */, true /* in_nmethod */);
1600 }
1601 }
1602
1603 int MachEpilogNode::reloc() const {
1604 // Return number of relocatable values contained in this instruction.
1605 return 1; // 1 for load_from_polling_page.
1606 }
1607
1608 const Pipeline * MachEpilogNode::pipeline() const {
1609 return MachNode::pipeline_class();
1610 }
1611
1612 // =============================================================================
1613
1614 // Figure out which register class each belongs in: rc_int, rc_float, rc_vec or
1615 // rc_stack.
1616 enum RC { rc_bad, rc_int, rc_float, rc_vec, rc_stack };
1617
1618 static enum RC rc_class(OptoReg::Name reg) {
1619 // Return the register class for the given register. The given register
1620 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1621 // enumeration in adGlobals_ppc.hpp.
1622
1623 if (reg == OptoReg::Bad) return rc_bad;
1624
1625 // We have 64 integer register halves, starting at index 0.
1626 STATIC_ASSERT((int)ConcreteRegisterImpl::max_gpr == (int)MachRegisterNumbers::F0_num);
1627 if (reg < ConcreteRegisterImpl::max_gpr) return rc_int;
1628
1629 // We have 64 floating-point register halves, starting at index 64.
1630 STATIC_ASSERT((int)ConcreteRegisterImpl::max_fpr == (int)MachRegisterNumbers::VR0_num);
1631 if (reg < ConcreteRegisterImpl::max_fpr) return rc_float;
1632
1633 // We have 64 vector-scalar registers, starting at index 128.
1634 STATIC_ASSERT((int)ConcreteRegisterImpl::max_vr == (int)MachRegisterNumbers::CR0_num);
1635 if (reg < ConcreteRegisterImpl::max_vr) return rc_vec;
1636
1637 // Condition and special purpose registers are not allocated. We only accept stack from here.
1638 assert(OptoReg::is_stack(reg), "what else is it?");
1639 return rc_stack;
1640 }
1641
1642 static int ld_st_helper(C2_MacroAssembler *masm, const char *op_str, uint opcode, int reg, int offset,
1643 bool do_print, Compile* C, outputStream *st) {
1644
1645 assert(opcode == Assembler::LD_OPCODE ||
1646 opcode == Assembler::STD_OPCODE ||
1647 opcode == Assembler::LWZ_OPCODE ||
1648 opcode == Assembler::STW_OPCODE ||
1649 opcode == Assembler::LFD_OPCODE ||
1650 opcode == Assembler::STFD_OPCODE ||
1651 opcode == Assembler::LFS_OPCODE ||
1652 opcode == Assembler::STFS_OPCODE,
1653 "opcode not supported");
1654
1655 if (masm) {
1656 int d =
1657 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1658 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1659 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1660 emit_long(masm, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1661 }
1662 #ifndef PRODUCT
1663 else if (do_print) {
1664 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1665 op_str,
1666 Matcher::regName[reg],
1667 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1668 }
1669 #endif
1670 return 4; // size
1671 }
1672
1673 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1674 Compile* C = ra_->C;
1675
1676 // Get registers to move.
1677 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1678 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1679 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1680 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1681
1682 enum RC src_hi_rc = rc_class(src_hi);
1683 enum RC src_lo_rc = rc_class(src_lo);
1684 enum RC dst_hi_rc = rc_class(dst_hi);
1685 enum RC dst_lo_rc = rc_class(dst_lo);
1686
1687 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1688 if (src_hi != OptoReg::Bad)
1689 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1690 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1691 "expected aligned-adjacent pairs");
1692 // Generate spill code!
1693 int size = 0;
1694
1695 if (src_lo == dst_lo && src_hi == dst_hi)
1696 return size; // Self copy, no move.
1697
1698 if (bottom_type()->isa_vect() != nullptr && ideal_reg() == Op_VecX) {
1699 int src_offset = ra_->reg2offset(src_lo);
1700 int dst_offset = ra_->reg2offset(dst_lo);
1701 DEBUG_ONLY(int algm = MIN2(RegMask::num_registers(ideal_reg()), (int)Matcher::stack_alignment_in_slots()) * VMRegImpl::stack_slot_size);
1702 assert((src_lo_rc != rc_stack) || is_aligned(src_offset, algm), "unaligned vector spill sp offset %d (src)", src_offset);
1703 assert((dst_lo_rc != rc_stack) || is_aligned(dst_offset, algm), "unaligned vector spill sp offset %d (dst)", dst_offset);
1704 // Memory->Memory Spill.
1705 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1706 if (masm) {
1707 __ ld(R0, src_offset, R1_SP);
1708 __ std(R0, dst_offset, R1_SP);
1709 __ ld(R0, src_offset+8, R1_SP);
1710 __ std(R0, dst_offset+8, R1_SP);
1711 }
1712 size += 16;
1713 #ifndef PRODUCT
1714 if (st != nullptr) {
1715 st->print("%-7s [R1_SP + #%d] -> [R1_SP + #%d] \t// vector spill copy", "SPILL", src_offset, dst_offset);
1716 }
1717 #endif // !PRODUCT
1718 }
1719 // VectorRegister->Memory Spill.
1720 else if (src_lo_rc == rc_vec && dst_lo_rc == rc_stack) {
1721 VectorSRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]).to_vsr();
1722 if (masm) {
1723 __ stxv(Rsrc, dst_offset, R1_SP); // matches storeV16
1724 }
1725 size += 4;
1726 #ifndef PRODUCT
1727 if (st != nullptr) {
1728 st->print("%-7s %s, [R1_SP + #%d] \t// vector spill copy", "STXV", Matcher::regName[src_lo], dst_offset);
1729 }
1730 #endif // !PRODUCT
1731 }
1732 // Memory->VectorRegister Spill.
1733 else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vec) {
1734 VectorSRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]).to_vsr();
1735 if (masm) {
1736 __ lxv(Rdst, src_offset, R1_SP);
1737 }
1738 size += 4;
1739 #ifndef PRODUCT
1740 if (st != nullptr) {
1741 st->print("%-7s %s, [R1_SP + #%d] \t// vector spill copy", "LXV", Matcher::regName[dst_lo], src_offset);
1742 }
1743 #endif // !PRODUCT
1744 }
1745 // VectorRegister->VectorRegister.
1746 else if (src_lo_rc == rc_vec && dst_lo_rc == rc_vec) {
1747 VectorSRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]).to_vsr();
1748 VectorSRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]).to_vsr();
1749 if (masm) {
1750 __ xxlor(Rdst, Rsrc, Rsrc);
1751 }
1752 size += 4;
1753 #ifndef PRODUCT
1754 if (st != nullptr) {
1755 st->print("%-7s %s, %s, %s\t// vector spill copy",
1756 "XXLOR", Matcher::regName[dst_lo], Matcher::regName[src_lo], Matcher::regName[src_lo]);
1757 }
1758 #endif // !PRODUCT
1759 }
1760 else {
1761 ShouldNotReachHere(); // No VR spill.
1762 }
1763 return size;
1764 }
1765
1766 // --------------------------------------
1767 // Memory->Memory Spill. Use R0 to hold the value.
1768 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1769 int src_offset = ra_->reg2offset(src_lo);
1770 int dst_offset = ra_->reg2offset(dst_lo);
1771 if (src_hi != OptoReg::Bad) {
1772 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1773 "expected same type of move for high parts");
1774 size += ld_st_helper(masm, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1775 if (!masm && !do_size) st->print("\n\t");
1776 size += ld_st_helper(masm, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1777 } else {
1778 size += ld_st_helper(masm, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1779 if (!masm && !do_size) st->print("\n\t");
1780 size += ld_st_helper(masm, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1781 }
1782 return size;
1783 }
1784
1785 // --------------------------------------
1786 // Check for float->int copy; requires a trip through memory.
1787 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1788 Unimplemented();
1789 }
1790
1791 // --------------------------------------
1792 // Check for integer reg-reg copy.
1793 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1794 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1795 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1796 size = (Rsrc != Rdst) ? 4 : 0;
1797
1798 if (masm) {
1799 if (size) {
1800 __ mr(Rdst, Rsrc);
1801 }
1802 }
1803 #ifndef PRODUCT
1804 else if (!do_size) {
1805 if (size) {
1806 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1807 } else {
1808 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1809 }
1810 }
1811 #endif
1812 return size;
1813 }
1814
1815 // Check for integer store.
1816 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1817 int dst_offset = ra_->reg2offset(dst_lo);
1818 if (src_hi != OptoReg::Bad) {
1819 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1820 "expected same type of move for high parts");
1821 size += ld_st_helper(masm, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1822 } else {
1823 size += ld_st_helper(masm, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1824 }
1825 return size;
1826 }
1827
1828 // Check for integer load.
1829 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1830 int src_offset = ra_->reg2offset(src_lo);
1831 if (src_hi != OptoReg::Bad) {
1832 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1833 "expected same type of move for high parts");
1834 size += ld_st_helper(masm, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1835 } else {
1836 size += ld_st_helper(masm, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1837 }
1838 return size;
1839 }
1840
1841 // Check for float reg-reg copy.
1842 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1843 if (masm) {
1844 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1845 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1846 __ fmr(Rdst, Rsrc);
1847 }
1848 #ifndef PRODUCT
1849 else if (!do_size) {
1850 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1851 }
1852 #endif
1853 return 4;
1854 }
1855
1856 // Check for float store.
1857 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1858 int dst_offset = ra_->reg2offset(dst_lo);
1859 if (src_hi != OptoReg::Bad) {
1860 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1861 "expected same type of move for high parts");
1862 size += ld_st_helper(masm, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1863 } else {
1864 size += ld_st_helper(masm, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1865 }
1866 return size;
1867 }
1868
1869 // Check for float load.
1870 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1871 int src_offset = ra_->reg2offset(src_lo);
1872 if (src_hi != OptoReg::Bad) {
1873 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1874 "expected same type of move for high parts");
1875 size += ld_st_helper(masm, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1876 } else {
1877 size += ld_st_helper(masm, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1878 }
1879 return size;
1880 }
1881
1882 // --------------------------------------------------------------------
1883 // Check for hi bits still needing moving. Only happens for misaligned
1884 // arguments to native calls.
1885 if (src_hi == dst_hi)
1886 return size; // Self copy; no move.
1887
1888 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1889 ShouldNotReachHere(); // Unimplemented
1890 return 0;
1891 }
1892
1893 #ifndef PRODUCT
1894 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1895 if (!ra_)
1896 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1897 else
1898 implementation(nullptr, ra_, false, st);
1899 }
1900 #endif
1901
1902 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1903 implementation(masm, ra_, false, nullptr);
1904 }
1905
1906 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1907 return implementation(nullptr, ra_, true, nullptr);
1908 }
1909
1910 #ifndef PRODUCT
1911 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1912 st->print("NOP \t// %d nops to pad for loops or prefixed instructions.", _count);
1913 }
1914 #endif
1915
1916 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *) const {
1917 // _count contains the number of nops needed for padding.
1918 for (int i = 0; i < _count; i++) {
1919 __ nop();
1920 }
1921 }
1922
1923 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1924 return _count * 4;
1925 }
1926
1927 #ifndef PRODUCT
1928 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1929 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1930 char reg_str[128];
1931 ra_->dump_register(this, reg_str, sizeof(reg_str));
1932 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1933 }
1934 #endif
1935
1936 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1937 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1938 int reg = ra_->get_encode(this);
1939
1940 if (Assembler::is_simm(offset, 16)) {
1941 __ addi(as_Register(reg), R1, offset);
1942 } else {
1943 ShouldNotReachHere();
1944 }
1945 }
1946
1947 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1948 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1949 return 4;
1950 }
1951
1952 #ifndef PRODUCT
1953 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1954 {
1955 Unimplemented();
1956 }
1957 #endif
1958
1959 void MachVEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc* ra_) const
1960 {
1961 Unimplemented();
1962 }
1963
1964 #ifndef PRODUCT
1965 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1966 st->print_cr("---- MachUEPNode ----");
1967 st->print_cr("...");
1968 }
1969 #endif
1970
1971 void MachUEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1972 // This is the unverified entry point.
1973 __ ic_check(CodeEntryAlignment);
1974 // Argument is valid and klass is as expected, continue.
1975 }
1976
1977 //=============================================================================
1978
1979 %} // interrupt source
1980
1981 source_hpp %{ // Header information of the source block.
1982
1983 class HandlerImpl {
1984
1985 public:
1986
1987 static int emit_deopt_handler(C2_MacroAssembler* masm);
1988
1989 static uint size_deopt_handler() {
1990 // The deopt_handler is a bl64_patchable.
1991 return MacroAssembler::bl64_patchable_size + BytesPerInstWord;
1992 }
1993
1994 };
1995
1996 class Node::PD {
1997 public:
1998 enum NodeFlags {
1999 _last_flag = Node::_last_flag
2000 };
2001 };
2002
2003 %} // end source_hpp
2004
2005 source %{
2006
2007 // The deopt_handler is like the exception handler, but it calls to
2008 // the deoptimization blob instead of jumping to the exception blob.
2009 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm) {
2010 address base = __ start_a_stub(size_deopt_handler());
2011 if (base == nullptr) {
2012 ciEnv::current()->record_failure("CodeCache is full");
2013 return 0; // CodeBuffer::expand failed
2014 }
2015
2016 int offset = __ offset();
2017
2018 Label start;
2019 __ bind(start);
2020
2021 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2022 relocInfo::runtime_call_type);
2023
2024 int entry_offset = __ offset();
2025
2026 __ b(start);
2027
2028 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2029 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
2030 "out of bounds read in post-call NOP check");
2031 __ end_a_stub();
2032
2033 return entry_offset;
2034 }
2035
2036 //=============================================================================
2037
2038 // Use a frame slots bias for frameless methods if accessing the stack.
2039 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2040 if (as_Register(reg_enc) == R1_SP) {
2041 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2042 }
2043 return 0;
2044 }
2045
2046 bool Matcher::match_rule_supported(int opcode) {
2047 if (!has_match_rule(opcode)) {
2048 return false; // no match rule present
2049 }
2050
2051 switch (opcode) {
2052 case Op_CountLeadingZerosI:
2053 case Op_CountLeadingZerosL:
2054 return UseCountLeadingZerosInstructionsPPC64;
2055 case Op_CountTrailingZerosI:
2056 case Op_CountTrailingZerosL:
2057 return (UseCountLeadingZerosInstructionsPPC64 || UseCountTrailingZerosInstructionsPPC64);
2058 case Op_PopCountI:
2059 case Op_PopCountL:
2060 return UsePopCountInstruction;
2061 case Op_ConvF2HF:
2062 case Op_ConvHF2F:
2063 return VM_Version::supports_float16();
2064 case Op_AddVB:
2065 case Op_AddVS:
2066 case Op_AddVI:
2067 case Op_AddVF:
2068 case Op_AddVD:
2069 case Op_SubVB:
2070 case Op_SubVS:
2071 case Op_SubVI:
2072 case Op_SubVF:
2073 case Op_SubVD:
2074 case Op_MulVS:
2075 case Op_MulVF:
2076 case Op_MulVD:
2077 case Op_DivVF:
2078 case Op_DivVD:
2079 case Op_AbsVF:
2080 case Op_AbsVD:
2081 case Op_NegVI:
2082 case Op_NegVF:
2083 case Op_NegVD:
2084 case Op_SqrtVF:
2085 case Op_SqrtVD:
2086 case Op_AddVL:
2087 case Op_SubVL:
2088 case Op_MulVI:
2089 case Op_RoundDoubleModeV:
2090 case Op_MinV:
2091 case Op_MaxV:
2092 case Op_UMinV:
2093 case Op_UMaxV:
2094 case Op_AndV:
2095 case Op_OrV:
2096 case Op_XorV:
2097 case Op_AddReductionVI:
2098 case Op_MulReductionVI:
2099 case Op_AndReductionV:
2100 case Op_OrReductionV:
2101 case Op_XorReductionV:
2102 case Op_MinReductionV:
2103 case Op_MaxReductionV:
2104 return SuperwordUseVSX;
2105 case Op_PopCountVI:
2106 case Op_PopCountVL:
2107 return (SuperwordUseVSX && UsePopCountInstruction);
2108 case Op_CountLeadingZerosV:
2109 return SuperwordUseVSX && UseCountLeadingZerosInstructionsPPC64;
2110 case Op_CountTrailingZerosV:
2111 return SuperwordUseVSX && UseCountTrailingZerosInstructionsPPC64;
2112 case Op_FmaF:
2113 case Op_FmaD:
2114 return UseFMA;
2115 case Op_FmaVF:
2116 case Op_FmaVD:
2117 return (SuperwordUseVSX && UseFMA);
2118
2119 case Op_MinF:
2120 case Op_MaxF:
2121 case Op_MinD:
2122 case Op_MaxD:
2123 return (PowerArchitecturePPC64 >= 9);
2124
2125 case Op_Digit:
2126 return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isDigit);
2127 case Op_LowerCase:
2128 return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isLowerCase);
2129 case Op_UpperCase:
2130 return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isUpperCase);
2131 case Op_Whitespace:
2132 return vmIntrinsics::is_intrinsic_available(vmIntrinsics::_isWhitespace);
2133
2134 case Op_CacheWB:
2135 case Op_CacheWBPreSync:
2136 case Op_CacheWBPostSync:
2137 return VM_Version::supports_data_cache_line_flush();
2138
2139 case Op_OnSpinWait:
2140 return VM_Version::supports_on_spin_wait();
2141 }
2142
2143 return true; // Per default match rules are supported.
2144 }
2145
2146 bool Matcher::match_rule_supported_auto_vectorization(int opcode, int vlen, BasicType bt) {
2147 return match_rule_supported_vector(opcode, vlen, bt);
2148 }
2149
2150 bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
2151 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
2152 return false;
2153 }
2154 // Special cases
2155 switch (opcode) {
2156 // Reductions only support INT at the moment.
2157 case Op_AddReductionVI:
2158 case Op_MulReductionVI:
2159 case Op_AndReductionV:
2160 case Op_OrReductionV:
2161 case Op_XorReductionV:
2162 case Op_MinReductionV:
2163 case Op_MaxReductionV:
2164 return bt == T_INT;
2165 // MaxV, MinV need types == INT || LONG.
2166 case Op_MaxV:
2167 case Op_MinV:
2168 case Op_UMinV:
2169 case Op_UMaxV:
2170 return bt == T_INT || bt == T_LONG;
2171 case Op_NegVI:
2172 return bt == T_INT;
2173 }
2174 return true; // Per default match rules are supported.
2175 }
2176
2177 bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
2178 return false;
2179 }
2180
2181 bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
2182 return false;
2183 }
2184
2185 bool Matcher::vector_rearrange_requires_load_shuffle(BasicType elem_bt, int vlen) {
2186 return false;
2187 }
2188
2189 bool Matcher::mask_op_prefers_predicate(int opcode, const TypeVect* vt) {
2190 return false;
2191 }
2192
2193 const RegMask* Matcher::predicate_reg_mask(void) {
2194 return nullptr;
2195 }
2196
2197 // Vector calling convention not yet implemented.
2198 bool Matcher::supports_vector_calling_convention(void) {
2199 return false;
2200 }
2201
2202 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
2203 Unimplemented();
2204 return OptoRegPair(0, 0);
2205 }
2206
2207 // Vector width in bytes.
2208 int Matcher::vector_width_in_bytes(BasicType bt) {
2209 if (SuperwordUseVSX) {
2210 assert(MaxVectorSize == 16,
2211 "SuperwordUseVSX requires MaxVectorSize 16, got " INT64_FORMAT, (int64_t)MaxVectorSize);
2212 return 16;
2213 } else {
2214 assert(MaxVectorSize == 8,
2215 "expected MaxVectorSize 8, got " INT64_FORMAT, (int64_t)MaxVectorSize);
2216 return 8;
2217 }
2218 }
2219
2220 // Vector ideal reg.
2221 uint Matcher::vector_ideal_reg(int size) {
2222 if (SuperwordUseVSX) {
2223 assert(MaxVectorSize == 16 && size == 16,
2224 "SuperwordUseVSX requires MaxVectorSize 16 and size 16, got MaxVectorSize=" INT64_FORMAT ", size=%d",
2225 (int64_t)MaxVectorSize, size);
2226 return Op_VecX;
2227 } else {
2228 assert(MaxVectorSize == 8 && size == 8,
2229 "expected MaxVectorSize 8 and size 8, got MaxVectorSize=" INT64_FORMAT ", size=%d",
2230 (int64_t)MaxVectorSize, size);
2231 return Op_RegL;
2232 }
2233 }
2234
2235 // Limits on vector size (number of elements) loaded into vector.
2236 int Matcher::max_vector_size(const BasicType bt) {
2237 assert(is_java_primitive(bt), "only primitive type vectors");
2238 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2239 }
2240
2241 int Matcher::min_vector_size(const BasicType bt) {
2242 return max_vector_size(bt); // Same as max.
2243 }
2244
2245 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2246 return Matcher::max_vector_size(bt);
2247 }
2248
2249 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2250 return -1;
2251 }
2252
2253 // RETURNS: whether this branch offset is short enough that a short
2254 // branch can be used.
2255 //
2256 // If the platform does not provide any short branch variants, then
2257 // this method should return `false' for offset 0.
2258 //
2259 // `Compile::Fill_buffer' will decide on basis of this information
2260 // whether to do the pass `Compile::Shorten_branches' at all.
2261 //
2262 // And `Compile::Shorten_branches' will decide on basis of this
2263 // information whether to replace particular branch sites by short
2264 // ones.
2265 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2266 // Is the offset within the range of a ppc64 pc relative branch?
2267 bool b;
2268
2269 const int safety_zone = 3 * BytesPerInstWord;
2270 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2271 29 - 16 + 1 + 2);
2272 return b;
2273 }
2274
2275 /* TODO: PPC port
2276 // Make a new machine dependent decode node (with its operands).
2277 MachTypeNode *Matcher::make_decode_node() {
2278 assert(CompressedOops::base() == nullptr && CompressedOops::shift() == 0,
2279 "This method is only implemented for unscaled cOops mode so far");
2280 MachTypeNode *decode = new decodeN_unscaledNode();
2281 decode->set_opnd_array(0, new iRegPdstOper());
2282 decode->set_opnd_array(1, new iRegNsrcOper());
2283 return decode;
2284 }
2285 */
2286
2287 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2288 ShouldNotReachHere(); // generic vector operands not supported
2289 return nullptr;
2290 }
2291
2292 bool Matcher::is_reg2reg_move(MachNode* m) {
2293 ShouldNotReachHere(); // generic vector operands not supported
2294 return false;
2295 }
2296
2297 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2298 return false;
2299 }
2300
2301 bool Matcher::is_generic_vector(MachOper* opnd) {
2302 ShouldNotReachHere(); // generic vector operands not supported
2303 return false;
2304 }
2305
2306 #ifdef ASSERT
2307 // Return whether or not this register is ever used as an argument.
2308 bool Matcher::can_be_java_arg(int reg) {
2309 // We must include the virtual halves in order to get STDs and LDs
2310 // instead of STWs and LWs in the trampoline stubs.
2311
2312 if ( reg == R3_num || reg == R3_H_num
2313 || reg == R4_num || reg == R4_H_num
2314 || reg == R5_num || reg == R5_H_num
2315 || reg == R6_num || reg == R6_H_num
2316 || reg == R7_num || reg == R7_H_num
2317 || reg == R8_num || reg == R8_H_num
2318 || reg == R9_num || reg == R9_H_num
2319 || reg == R10_num || reg == R10_H_num)
2320 return true;
2321
2322 if ( reg == F1_num || reg == F1_H_num
2323 || reg == F2_num || reg == F2_H_num
2324 || reg == F3_num || reg == F3_H_num
2325 || reg == F4_num || reg == F4_H_num
2326 || reg == F5_num || reg == F5_H_num
2327 || reg == F6_num || reg == F6_H_num
2328 || reg == F7_num || reg == F7_H_num
2329 || reg == F8_num || reg == F8_H_num
2330 || reg == F9_num || reg == F9_H_num
2331 || reg == F10_num || reg == F10_H_num
2332 || reg == F11_num || reg == F11_H_num
2333 || reg == F12_num || reg == F12_H_num
2334 || reg == F13_num || reg == F13_H_num)
2335 return true;
2336
2337 return false;
2338 }
2339 #endif
2340
2341 uint Matcher::int_pressure_limit()
2342 {
2343 return (INTPRESSURE == -1) ? 26 : INTPRESSURE;
2344 }
2345
2346 uint Matcher::float_pressure_limit()
2347 {
2348 return (FLOATPRESSURE == -1) ? 28 : FLOATPRESSURE;
2349 }
2350
2351 // Register for the first projection of an int pair
2352 const RegMask& Matcher::firstI_proj_mask() {
2353 ShouldNotReachHere();
2354 return RegMask::EMPTY;
2355 }
2356
2357 // Register for the second projection of an int pair
2358 const RegMask& Matcher::secondI_proj_mask() {
2359 ShouldNotReachHere();
2360 return RegMask::EMPTY;
2361 }
2362
2363 // Register for the first projection of a long pair
2364 const RegMask& Matcher::firstL_proj_mask() {
2365 ShouldNotReachHere();
2366 return RegMask::EMPTY;
2367 }
2368
2369 // Register for the second projection of a long pair
2370 const RegMask& Matcher::secondL_proj_mask() {
2371 ShouldNotReachHere();
2372 return RegMask::EMPTY;
2373 }
2374
2375 %}
2376
2377 //----------ENCODING BLOCK-----------------------------------------------------
2378 // This block specifies the encoding classes used by the compiler to output
2379 // byte streams. Encoding classes are parameterized macros used by
2380 // Machine Instruction Nodes in order to generate the bit encoding of the
2381 // instruction. Operands specify their base encoding interface with the
2382 // interface keyword. There are currently supported four interfaces,
2383 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2384 // operand to generate a function which returns its register number when
2385 // queried. CONST_INTER causes an operand to generate a function which
2386 // returns the value of the constant when queried. MEMORY_INTER causes an
2387 // operand to generate four functions which return the Base Register, the
2388 // Index Register, the Scale Value, and the Offset Value of the operand when
2389 // queried. COND_INTER causes an operand to generate six functions which
2390 // return the encoding code (ie - encoding bits for the instruction)
2391 // associated with each basic boolean condition for a conditional instruction.
2392 //
2393 // Instructions specify two basic values for encoding. Again, a function
2394 // is available to check if the constant displacement is an oop. They use the
2395 // ins_encode keyword to specify their encoding classes (which must be
2396 // a sequence of enc_class names, and their parameters, specified in
2397 // the encoding block), and they use the
2398 // opcode keyword to specify, in order, their primary, secondary, and
2399 // tertiary opcode. Only the opcode sections which a particular instruction
2400 // needs for encoding need to be specified.
2401 encode %{
2402 enc_class enc_unimplemented %{
2403 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2404 %}
2405
2406 enc_class enc_untested %{
2407 #ifdef ASSERT
2408 __ untested("Untested mach node encoding in AD file.");
2409 #else
2410 #endif
2411 %}
2412
2413 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2414 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2415 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2416 %}
2417
2418 // Load acquire.
2419 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2420 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2421 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2422 __ twi_0($dst$$Register);
2423 __ isync();
2424 %}
2425
2426 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2427 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2428 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2429 %}
2430
2431 // Load acquire.
2432 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2433 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2434 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2435 __ twi_0($dst$$Register);
2436 __ isync();
2437 %}
2438
2439 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2440 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2441 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2442 %}
2443
2444 // Load acquire.
2445 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2446 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2447 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2448 __ twi_0($dst$$Register);
2449 __ isync();
2450 %}
2451
2452 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2453 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2454 // Operand 'ds' requires 4-alignment.
2455 assert((Idisp & 0x3) == 0, "unaligned offset");
2456 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2457 %}
2458
2459 // Load acquire.
2460 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2461 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2462 // Operand 'ds' requires 4-alignment.
2463 assert((Idisp & 0x3) == 0, "unaligned offset");
2464 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2465 __ twi_0($dst$$Register);
2466 __ isync();
2467 %}
2468
2469 enc_class enc_lfd(RegF dst, memory mem) %{
2470 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2471 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2472 %}
2473
2474 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2475 int toc_offset = 0;
2476
2477 address const_toc_addr;
2478 // Create a non-oop constant, no relocation needed.
2479 // If it is an IC, it has a virtual_call_Relocation.
2480 const_toc_addr = __ long_constant((jlong)$src$$constant);
2481 if (const_toc_addr == nullptr) {
2482 ciEnv::current()->record_out_of_memory_failure();
2483 return;
2484 }
2485
2486 // Get the constant's TOC offset.
2487 toc_offset = __ offset_to_method_toc(const_toc_addr);
2488
2489 // Keep the current instruction offset in mind.
2490 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2491
2492 __ ld($dst$$Register, toc_offset, $toc$$Register);
2493 %}
2494
2495 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2496 if (!ra_->C->output()->in_scratch_emit_size()) {
2497 address const_toc_addr;
2498 // Create a non-oop constant, no relocation needed.
2499 // If it is an IC, it has a virtual_call_Relocation.
2500 const_toc_addr = __ long_constant((jlong)$src$$constant);
2501 if (const_toc_addr == nullptr) {
2502 ciEnv::current()->record_out_of_memory_failure();
2503 return;
2504 }
2505
2506 // Get the constant's TOC offset.
2507 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2508 // Store the toc offset of the constant.
2509 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2510
2511 // Also keep the current instruction offset in mind.
2512 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2513 }
2514
2515 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2516 %}
2517
2518 %} // encode
2519
2520 source %{
2521
2522 typedef struct {
2523 loadConL_hiNode *_large_hi;
2524 loadConL_loNode *_large_lo;
2525 loadConLNode *_small;
2526 MachNode *_last;
2527 } loadConLNodesTuple;
2528
2529 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2530 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2531 loadConLNodesTuple nodes;
2532
2533 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2534 if (large_constant_pool) {
2535 // Create new nodes.
2536 loadConL_hiNode *m1 = new loadConL_hiNode();
2537 loadConL_loNode *m2 = new loadConL_loNode();
2538
2539 // inputs for new nodes
2540 m1->add_req(nullptr, toc);
2541 m2->add_req(nullptr, m1);
2542
2543 // operands for new nodes
2544 m1->_opnds[0] = new iRegLdstOper(); // dst
2545 m1->_opnds[1] = immSrc; // src
2546 m1->_opnds[2] = new iRegLdstOper(); // toc
2547 m2->_opnds[0] = new iRegLdstOper(); // dst
2548 m2->_opnds[1] = immSrc; // src
2549 m2->_opnds[2] = new iRegLdstOper(); // base
2550
2551 // Initialize ins_attrib TOC fields.
2552 m1->_const_toc_offset = -1;
2553 m2->_const_toc_offset_hi_node = m1;
2554
2555 // Initialize ins_attrib instruction offset.
2556 m1->_cbuf_insts_offset = -1;
2557
2558 // register allocation for new nodes
2559 ra_->set_pair(m1->_idx, reg_second, reg_first);
2560 ra_->set_pair(m2->_idx, reg_second, reg_first);
2561
2562 // Create result.
2563 nodes._large_hi = m1;
2564 nodes._large_lo = m2;
2565 nodes._small = nullptr;
2566 nodes._last = nodes._large_lo;
2567 assert(m2->bottom_type()->isa_long(), "must be long");
2568 } else {
2569 loadConLNode *m2 = new loadConLNode();
2570
2571 // inputs for new nodes
2572 m2->add_req(nullptr, toc);
2573
2574 // operands for new nodes
2575 m2->_opnds[0] = new iRegLdstOper(); // dst
2576 m2->_opnds[1] = immSrc; // src
2577 m2->_opnds[2] = new iRegLdstOper(); // toc
2578
2579 // Initialize ins_attrib instruction offset.
2580 m2->_cbuf_insts_offset = -1;
2581
2582 // register allocation for new nodes
2583 ra_->set_pair(m2->_idx, reg_second, reg_first);
2584
2585 // Create result.
2586 nodes._large_hi = nullptr;
2587 nodes._large_lo = nullptr;
2588 nodes._small = m2;
2589 nodes._last = nodes._small;
2590 assert(m2->bottom_type()->isa_long(), "must be long");
2591 }
2592
2593 return nodes;
2594 }
2595
2596 typedef struct {
2597 loadConL_hiNode *_large_hi;
2598 loadConL_loNode *_large_lo;
2599 mtvsrdNode *_moved;
2600 xxspltdNode *_replicated;
2601 loadConLNode *_small;
2602 MachNode *_last;
2603 } loadConLReplicatedNodesTuple;
2604
2605 loadConLReplicatedNodesTuple loadConLReplicatedNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2606 vecXOper *dst, immI_0Oper *zero,
2607 OptoReg::Name reg_second, OptoReg::Name reg_first,
2608 OptoReg::Name reg_vec_second, OptoReg::Name reg_vec_first) {
2609 loadConLReplicatedNodesTuple nodes;
2610
2611 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2612 if (large_constant_pool) {
2613 // Create new nodes.
2614 loadConL_hiNode *m1 = new loadConL_hiNode();
2615 loadConL_loNode *m2 = new loadConL_loNode();
2616 mtvsrdNode *m3 = new mtvsrdNode();
2617 xxspltdNode *m4 = new xxspltdNode();
2618
2619 // inputs for new nodes
2620 m1->add_req(nullptr, toc);
2621 m2->add_req(nullptr, m1);
2622 m3->add_req(nullptr, m2);
2623 m4->add_req(nullptr, m3);
2624
2625 // operands for new nodes
2626 m1->_opnds[0] = new iRegLdstOper(); // dst
2627 m1->_opnds[1] = immSrc; // src
2628 m1->_opnds[2] = new iRegLdstOper(); // toc
2629
2630 m2->_opnds[0] = new iRegLdstOper(); // dst
2631 m2->_opnds[1] = immSrc; // src
2632 m2->_opnds[2] = new iRegLdstOper(); // base
2633
2634 m3->_opnds[0] = new vecXOper(); // dst
2635 m3->_opnds[1] = new iRegLdstOper(); // src
2636
2637 m4->_opnds[0] = new vecXOper(); // dst
2638 m4->_opnds[1] = new vecXOper(); // src
2639 m4->_opnds[2] = zero;
2640
2641 // Initialize ins_attrib TOC fields.
2642 m1->_const_toc_offset = -1;
2643 m2->_const_toc_offset_hi_node = m1;
2644
2645 // Initialize ins_attrib instruction offset.
2646 m1->_cbuf_insts_offset = -1;
2647
2648 // register allocation for new nodes
2649 ra_->set_pair(m1->_idx, reg_second, reg_first);
2650 ra_->set_pair(m2->_idx, reg_second, reg_first);
2651 ra_->set1(m3->_idx, reg_second);
2652 ra_->set2(m3->_idx, reg_vec_first);
2653 ra_->set_pair(m4->_idx, reg_vec_second, reg_vec_first);
2654
2655 // Create result.
2656 nodes._large_hi = m1;
2657 nodes._large_lo = m2;
2658 nodes._moved = m3;
2659 nodes._replicated = m4;
2660 nodes._small = nullptr;
2661 nodes._last = nodes._replicated;
2662 assert(m2->bottom_type()->isa_long(), "must be long");
2663 } else {
2664 loadConLNode *m2 = new loadConLNode();
2665 mtvsrdNode *m3 = new mtvsrdNode();
2666 xxspltdNode *m4 = new xxspltdNode();
2667
2668 // inputs for new nodes
2669 m2->add_req(nullptr, toc);
2670
2671 // operands for new nodes
2672 m2->_opnds[0] = new iRegLdstOper(); // dst
2673 m2->_opnds[1] = immSrc; // src
2674 m2->_opnds[2] = new iRegLdstOper(); // toc
2675
2676 m3->_opnds[0] = new vecXOper(); // dst
2677 m3->_opnds[1] = new iRegLdstOper(); // src
2678
2679 m4->_opnds[0] = new vecXOper(); // dst
2680 m4->_opnds[1] = new vecXOper(); // src
2681 m4->_opnds[2] = zero;
2682
2683 // Initialize ins_attrib instruction offset.
2684 m2->_cbuf_insts_offset = -1;
2685 ra_->set1(m3->_idx, reg_second);
2686 ra_->set2(m3->_idx, reg_vec_first);
2687 ra_->set_pair(m4->_idx, reg_vec_second, reg_vec_first);
2688
2689 // register allocation for new nodes
2690 ra_->set_pair(m2->_idx, reg_second, reg_first);
2691
2692 // Create result.
2693 nodes._large_hi = nullptr;
2694 nodes._large_lo = nullptr;
2695 nodes._small = m2;
2696 nodes._moved = m3;
2697 nodes._replicated = m4;
2698 nodes._last = nodes._replicated;
2699 assert(m2->bottom_type()->isa_long(), "must be long");
2700 }
2701
2702 return nodes;
2703 }
2704
2705 %} // source
2706
2707 encode %{
2708 // Postalloc expand emitter for loading a long constant from the method's TOC.
2709 // Enc_class needed as consttanttablebase is not supported by postalloc
2710 // expand.
2711 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2712 // Create new nodes.
2713 loadConLNodesTuple loadConLNodes =
2714 loadConLNodesTuple_create(ra_, n_toc, op_src,
2715 ra_->get_reg_second(this), ra_->get_reg_first(this));
2716
2717 // Push new nodes.
2718 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2719 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2720
2721 // some asserts
2722 assert(nodes->length() >= 1, "must have created at least 1 node");
2723 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2724 %}
2725
2726 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2727 int toc_offset = 0;
2728
2729 intptr_t val = $src$$constant;
2730 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2731 address const_toc_addr;
2732 RelocationHolder r; // Initializes type to none.
2733 if (constant_reloc == relocInfo::oop_type) {
2734 // Create an oop constant and a corresponding relocation.
2735 AddressLiteral a = __ constant_oop_address((jobject)val);
2736 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2737 r = a.rspec();
2738 } else if (constant_reloc == relocInfo::metadata_type) {
2739 // Notify OOP recorder (don't need the relocation)
2740 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2741 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2742 } else {
2743 // Create a non-oop constant, no relocation needed.
2744 const_toc_addr = __ long_constant((jlong)$src$$constant);
2745 }
2746
2747 if (const_toc_addr == nullptr) {
2748 ciEnv::current()->record_out_of_memory_failure();
2749 return;
2750 }
2751 __ relocate(r); // If set above.
2752 // Get the constant's TOC offset.
2753 toc_offset = __ offset_to_method_toc(const_toc_addr);
2754
2755 __ ld($dst$$Register, toc_offset, $toc$$Register);
2756 %}
2757
2758 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2759 if (!ra_->C->output()->in_scratch_emit_size()) {
2760 intptr_t val = $src$$constant;
2761 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2762 address const_toc_addr;
2763 RelocationHolder r; // Initializes type to none.
2764 if (constant_reloc == relocInfo::oop_type) {
2765 // Create an oop constant and a corresponding relocation.
2766 AddressLiteral a = __ constant_oop_address((jobject)val);
2767 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2768 r = a.rspec();
2769 } else if (constant_reloc == relocInfo::metadata_type) {
2770 // Notify OOP recorder (don't need the relocation)
2771 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2772 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2773 } else { // non-oop pointers, e.g. card mark base, heap top
2774 // Create a non-oop constant, no relocation needed.
2775 const_toc_addr = __ long_constant((jlong)$src$$constant);
2776 }
2777
2778 if (const_toc_addr == nullptr) {
2779 ciEnv::current()->record_out_of_memory_failure();
2780 return;
2781 }
2782 __ relocate(r); // If set above.
2783 // Get the constant's TOC offset.
2784 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2785 // Store the toc offset of the constant.
2786 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2787 }
2788
2789 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2790 %}
2791
2792 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2793 // Enc_class needed as consttanttablebase is not supported by postalloc
2794 // expand.
2795 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2796 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2797 if (large_constant_pool) {
2798 // Create new nodes.
2799 loadConP_hiNode *m1 = new loadConP_hiNode();
2800 loadConP_loNode *m2 = new loadConP_loNode();
2801
2802 // If this is an oop, both m1 and m2 must be consider oops so postalloc scheduling does not
2803 // put a safepoint between them
2804 m1->_bottom_type = bottom_type();
2805 m2->_bottom_type = bottom_type();
2806
2807 // inputs for new nodes
2808 m1->add_req(nullptr, n_toc);
2809 m2->add_req(nullptr, m1);
2810
2811 // operands for new nodes
2812 m1->_opnds[0] = new iRegPdstOper(); // dst
2813 m1->_opnds[1] = op_src; // src
2814 m1->_opnds[2] = new iRegLdstOper(); // toc
2815
2816 m2->_opnds[0] = new iRegPdstOper(); // dst
2817 m2->_opnds[1] = op_src; // src
2818 m2->_opnds[2] = new iRegLdstOper(); // base
2819
2820 // Initialize ins_attrib TOC fields.
2821 m1->_const_toc_offset = -1;
2822 m2->_const_toc_offset_hi_node = m1;
2823
2824 // Register allocation for new nodes.
2825 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2826 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2827
2828 nodes->push(m1);
2829 nodes->push(m2);
2830 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2831 } else {
2832 loadConPNode *m2 = new loadConPNode();
2833
2834 // inputs for new nodes
2835 m2->add_req(nullptr, n_toc);
2836
2837 // operands for new nodes
2838 m2->_opnds[0] = new iRegPdstOper(); // dst
2839 m2->_opnds[1] = op_src; // src
2840 m2->_opnds[2] = new iRegLdstOper(); // toc
2841
2842 // Register allocation for new nodes.
2843 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2844
2845 nodes->push(m2);
2846 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2847 }
2848 %}
2849
2850 // Enc_class needed as consttanttablebase is not supported by postalloc
2851 // expand.
2852 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2853 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2854
2855 MachNode *m2;
2856 if (large_constant_pool) {
2857 m2 = new loadConFCompNode();
2858 } else {
2859 m2 = new loadConFNode();
2860 }
2861 // inputs for new nodes
2862 m2->add_req(nullptr, n_toc);
2863
2864 // operands for new nodes
2865 m2->_opnds[0] = op_dst;
2866 m2->_opnds[1] = op_src;
2867 m2->_opnds[2] = new iRegLdstOper(); // constanttablebase
2868
2869 // register allocation for new nodes
2870 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2871 nodes->push(m2);
2872 %}
2873
2874 // Enc_class needed as consttanttablebase is not supported by postalloc
2875 // expand.
2876 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2877 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2878
2879 MachNode *m2;
2880 if (large_constant_pool) {
2881 m2 = new loadConDCompNode();
2882 } else {
2883 m2 = new loadConDNode();
2884 }
2885 // inputs for new nodes
2886 m2->add_req(nullptr, n_toc);
2887
2888 // operands for new nodes
2889 m2->_opnds[0] = op_dst;
2890 m2->_opnds[1] = op_src;
2891 m2->_opnds[2] = new iRegLdstOper(); // constanttablebase
2892
2893 // register allocation for new nodes
2894 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2895 nodes->push(m2);
2896 %}
2897
2898 enc_class enc_stw(iRegIsrc src, memory mem) %{
2899 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2900 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2901 %}
2902
2903 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2904 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2905 // Operand 'ds' requires 4-alignment.
2906 assert((Idisp & 0x3) == 0, "unaligned offset");
2907 __ std($src$$Register, Idisp, $mem$$base$$Register);
2908 %}
2909
2910 enc_class enc_stfs(RegF src, memory mem) %{
2911 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2912 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2913 %}
2914
2915 enc_class enc_stfd(RegF src, memory mem) %{
2916 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2917 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2918 %}
2919
2920 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2921 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2922 encodeP_subNode *n_sub_base = new encodeP_subNode();
2923 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2924 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2925
2926 n_compare->add_req(n_region, n_src);
2927 n_compare->_opnds[0] = op_crx;
2928 n_compare->_opnds[1] = op_src;
2929 n_compare->_opnds[2] = new immL16Oper(0);
2930
2931 n_sub_base->add_req(n_region, n_src);
2932 n_sub_base->_opnds[0] = op_dst;
2933 n_sub_base->_opnds[1] = op_src;
2934 n_sub_base->_bottom_type = _bottom_type;
2935
2936 n_shift->add_req(n_region, n_sub_base);
2937 n_shift->_opnds[0] = op_dst;
2938 n_shift->_opnds[1] = op_dst;
2939 n_shift->_bottom_type = _bottom_type;
2940
2941 n_cond_set->add_req(n_region, n_compare, n_shift);
2942 n_cond_set->_opnds[0] = op_dst;
2943 n_cond_set->_opnds[1] = op_crx;
2944 n_cond_set->_opnds[2] = op_dst;
2945 n_cond_set->_bottom_type = _bottom_type;
2946
2947 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2948 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2949 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2950 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2951
2952 nodes->push(n_compare);
2953 nodes->push(n_sub_base);
2954 nodes->push(n_shift);
2955 nodes->push(n_cond_set);
2956
2957 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2958 %}
2959
2960 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2961
2962 encodeP_subNode *n1 = new encodeP_subNode();
2963 n1->add_req(n_region, n_src);
2964 n1->_opnds[0] = op_dst;
2965 n1->_opnds[1] = op_src;
2966 n1->_bottom_type = _bottom_type;
2967
2968 encodeP_shiftNode *n2 = new encodeP_shiftNode();
2969 n2->add_req(n_region, n1);
2970 n2->_opnds[0] = op_dst;
2971 n2->_opnds[1] = op_dst;
2972 n2->_bottom_type = _bottom_type;
2973 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2974 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2975
2976 nodes->push(n1);
2977 nodes->push(n2);
2978 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2979 %}
2980
2981 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2982 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
2983 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
2984
2985 n_compare->add_req(n_region, n_src);
2986 n_compare->_opnds[0] = op_crx;
2987 n_compare->_opnds[1] = op_src;
2988 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2989
2990 n_shift->add_req(n_region, n_src);
2991 n_shift->_opnds[0] = op_dst;
2992 n_shift->_opnds[1] = op_src;
2993 n_shift->_bottom_type = _bottom_type;
2994
2995 decodeN_addNode *n_add_base = new decodeN_addNode();
2996 n_add_base->add_req(n_region, n_shift);
2997 n_add_base->_opnds[0] = op_dst;
2998 n_add_base->_opnds[1] = op_dst;
2999 n_add_base->_bottom_type = _bottom_type;
3000
3001 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
3002 n_cond_set->add_req(n_region, n_compare, n_add_base);
3003 n_cond_set->_opnds[0] = op_dst;
3004 n_cond_set->_opnds[1] = op_crx;
3005 n_cond_set->_opnds[2] = op_dst;
3006 n_cond_set->_bottom_type = _bottom_type;
3007
3008 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3009 ra_->set_oop(n_cond_set, true);
3010
3011 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3012 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3013 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3014 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3015
3016 nodes->push(n_compare);
3017 nodes->push(n_shift);
3018 nodes->push(n_add_base);
3019 nodes->push(n_cond_set);
3020
3021 %}
3022
3023 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3024 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3025 n1->add_req(n_region, n_src);
3026 n1->_opnds[0] = op_dst;
3027 n1->_opnds[1] = op_src;
3028 n1->_bottom_type = _bottom_type;
3029
3030 decodeN_addNode *n2 = new decodeN_addNode();
3031 n2->add_req(n_region, n1);
3032 n2->_opnds[0] = op_dst;
3033 n2->_opnds[1] = op_dst;
3034 n2->_bottom_type = _bottom_type;
3035 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3036 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3037
3038 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3039 ra_->set_oop(n2, true);
3040
3041 nodes->push(n1);
3042 nodes->push(n2);
3043 %}
3044
3045
3046 // This enc_class is needed so that scheduler gets proper
3047 // input mapping for latency computation.
3048 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3049 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3050 %}
3051
3052 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3053 Label done;
3054 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3055 __ li($dst$$Register, $zero$$constant);
3056 __ beq($crx$$CondRegister, done);
3057 __ li($dst$$Register, $notzero$$constant);
3058 __ bind(done);
3059 %}
3060
3061 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3062 Label done;
3063 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064 __ li($dst$$Register, $zero$$constant);
3065 __ beq($crx$$CondRegister, done);
3066 __ li($dst$$Register, $notzero$$constant);
3067 __ bind(done);
3068 %}
3069
3070 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3072 Label done;
3073 __ bso($crx$$CondRegister, done);
3074 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3075 __ bind(done);
3076 %}
3077
3078 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3079 Label d; // dummy
3080 __ bind(d);
3081 Label* p = ($lbl$$label);
3082 // `p' is `nullptr' when this encoding class is used only to
3083 // determine the size of the encoded instruction.
3084 Label& l = (nullptr == p)? d : *(p);
3085 int cc = $cmp$$cmpcode;
3086 int flags_reg = $crx$$reg;
3087 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3088 int bhint = Assembler::bhintNoHint;
3089
3090 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3091 if (_prob <= PROB_NEVER) {
3092 bhint = Assembler::bhintIsNotTaken;
3093 } else if (_prob >= PROB_ALWAYS) {
3094 bhint = Assembler::bhintIsTaken;
3095 }
3096 }
3097
3098 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3099 cc_to_biint(cc, flags_reg),
3100 l);
3101 %}
3102
3103 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3104 // The scheduler doesn't know about branch shortening, so we set the opcode
3105 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3106 Label d; // dummy
3107 __ bind(d);
3108 Label* p = ($lbl$$label);
3109 // `p' is `nullptr' when this encoding class is used only to
3110 // determine the size of the encoded instruction.
3111 Label& l = (nullptr == p)? d : *(p);
3112 int cc = $cmp$$cmpcode;
3113 int flags_reg = $crx$$reg;
3114 int bhint = Assembler::bhintNoHint;
3115
3116 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3117 if (_prob <= PROB_NEVER) {
3118 bhint = Assembler::bhintIsNotTaken;
3119 } else if (_prob >= PROB_ALWAYS) {
3120 bhint = Assembler::bhintIsTaken;
3121 }
3122 }
3123
3124 // Tell the conditional far branch to optimize itself when being relocated.
3125 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3126 cc_to_biint(cc, flags_reg),
3127 l,
3128 MacroAssembler::bc_far_optimize_on_relocate);
3129 %}
3130
3131 // Postalloc expand emitter for loading a replicatef float constant from
3132 // the method's TOC.
3133 // Enc_class needed as consttanttablebase is not supported by postalloc
3134 // expand.
3135 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3136 // Create new nodes.
3137
3138 // Make an operand with the bit pattern to load as float.
3139 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3140
3141 loadConLNodesTuple loadConLNodes =
3142 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3143 ra_->get_reg_second(this), ra_->get_reg_first(this));
3144
3145 // Push new nodes.
3146 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3147 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3148
3149 assert(nodes->length() >= 1, "must have created at least 1 node");
3150 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3151 %}
3152
3153 enc_class postalloc_expand_load_replF_constant_vsx(vecX dst, immF src, iRegLdst toc, iRegLdst tmp) %{
3154 // Create new nodes.
3155
3156 // Make an operand with the bit pattern to load as float.
3157 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3158 immI_0Oper *op_zero = new immI_0Oper(0);
3159
3160 loadConLReplicatedNodesTuple loadConLNodes =
3161 loadConLReplicatedNodesTuple_create(C, ra_, n_toc, op_repl, op_dst, op_zero,
3162 ra_->get_reg_second(n_tmp), ra_->get_reg_first(n_tmp),
3163 ra_->get_reg_second(this), ra_->get_reg_first(this));
3164
3165 // Push new nodes.
3166 if (loadConLNodes._large_hi) { nodes->push(loadConLNodes._large_hi); }
3167 if (loadConLNodes._large_lo) { nodes->push(loadConLNodes._large_lo); }
3168 if (loadConLNodes._moved) { nodes->push(loadConLNodes._moved); }
3169 if (loadConLNodes._last) { nodes->push(loadConLNodes._last); }
3170
3171 assert(nodes->length() >= 1, "must have created at least 1 node");
3172 %}
3173
3174 // This enc_class is needed so that scheduler gets proper
3175 // input mapping for latency computation.
3176 enc_class enc_poll(immI dst, iRegLdst poll) %{
3177 // Fake operand dst needed for PPC scheduler.
3178 assert($dst$$constant == 0x0, "dst must be 0x0");
3179
3180 // Mark the code position where the load from the safepoint
3181 // polling page was emitted as relocInfo::poll_type.
3182 __ relocate(relocInfo::poll_type);
3183 __ load_from_polling_page($poll$$Register);
3184 %}
3185
3186 // A Java static call or a runtime call.
3187 //
3188 // Branch-and-link relative to a trampoline.
3189 // The trampoline loads the target address and does a long branch to there.
3190 // In case we call java, the trampoline branches to a interpreter_stub
3191 // which loads the inline cache and the real call target from the constant pool.
3192 //
3193 // This basically looks like this:
3194 //
3195 // >>>> consts -+ -+
3196 // | |- offset1
3197 // [call target1] | <-+
3198 // [IC cache] |- offset2
3199 // [call target2] <--+
3200 //
3201 // <<<< consts
3202 // >>>> insts
3203 //
3204 // bl offset16 -+ -+ ??? // How many bits available?
3205 // | |
3206 // <<<< insts | |
3207 // >>>> stubs | |
3208 // | |- trampoline_stub_Reloc
3209 // trampoline stub: | <-+
3210 // r2 = toc |
3211 // r2 = [r2 + offset1] | // Load call target1 from const section
3212 // mtctr r2 |
3213 // bctr |- static_stub_Reloc
3214 // comp_to_interp_stub: <---+
3215 // r1 = toc
3216 // ICreg = [r1 + IC_offset] // Load IC from const section
3217 // r1 = [r1 + offset2] // Load call target2 from const section
3218 // mtctr r1
3219 // bctr
3220 //
3221 // <<<< stubs
3222 //
3223 // The call instruction in the code either
3224 // - Branches directly to a compiled method if the offset is encodable in instruction.
3225 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3226 // - Branches to the compiled_to_interp stub if the target is interpreted.
3227 //
3228 // Further there are three relocations from the loads to the constants in
3229 // the constant section.
3230 //
3231 // Usage of r1 and r2 in the stubs allows to distinguish them.
3232 enc_class enc_java_static_call(method meth) %{
3233 address entry_point = (address)$meth$$method;
3234 address call_pc;
3235
3236 if (!_method) {
3237 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3238 call_pc = __ trampoline_call(AddressLiteral(entry_point, relocInfo::runtime_call_type));
3239 if (call_pc == nullptr) {
3240 ciEnv::current()->record_failure("CodeCache is full");
3241 return;
3242 }
3243 } else {
3244 int method_index = resolved_method_index(masm);
3245 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3246 : static_call_Relocation::spec(method_index);
3247 call_pc = __ trampoline_call(AddressLiteral(entry_point, rspec));
3248 if (call_pc == nullptr) {
3249 ciEnv::current()->record_failure("CodeCache is full");
3250 return;
3251 }
3252
3253 // Emit stub for static call
3254 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call_pc);
3255 if (stub == nullptr) {
3256 ciEnv::current()->record_failure("CodeCache is full");
3257 return;
3258 }
3259 }
3260 __ post_call_nop();
3261 %}
3262
3263 // Compound version of call dynamic
3264 // Toc is only passed so that it can be used in ins_encode statement.
3265 // In the code we have to use $constanttablebase.
3266 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3267 int start_offset = __ offset();
3268 int method_index = resolved_method_index(masm);
3269 bool scratch_emit = ra_ == nullptr;
3270 Register Rtoc = scratch_emit ? R2_TOC : $constanttablebase;
3271 bool success = __ ic_call(Rtoc, (address)$meth$$method, method_index, scratch_emit, true /*fixed_size*/);
3272 if (!success) {
3273 ciEnv::current()->record_failure("CodeCache is full");
3274 return;
3275 }
3276 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3277 "Fix constant in ret_addr_offset(), expected %d", __ offset() - start_offset);
3278 __ post_call_nop();
3279 %}
3280
3281 // a runtime call
3282 enc_class enc_java_to_runtime_call (method meth) %{
3283 const address start_pc = __ pc();
3284
3285 #if defined(ABI_ELFv2)
3286 address entry= !($meth$$method) ? nullptr : (address)$meth$$method;
3287 __ call_c(entry, relocInfo::runtime_call_type);
3288 __ post_call_nop();
3289 #else
3290 // The function we're going to call.
3291 FunctionDescriptor fdtemp;
3292 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3293
3294 Register Rtoc = R12_scratch2;
3295 // Calculate the method's TOC.
3296 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3297 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3298 // pool entries; call_c_using_toc will optimize the call.
3299 bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3300 if (!success) {
3301 ciEnv::current()->record_out_of_memory_failure();
3302 return;
3303 }
3304 __ post_call_nop();
3305 #endif
3306
3307 // Check the ret_addr_offset.
3308 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3309 "Fix constant in ret_addr_offset()");
3310 %}
3311
3312 // Move to ctr for leaf call.
3313 // This enc_class is needed so that scheduler gets proper
3314 // input mapping for latency computation.
3315 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3316 __ mtctr($src$$Register);
3317 %}
3318
3319 // Postalloc expand emitter for runtime leaf calls.
3320 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3321 loadConLNodesTuple loadConLNodes_Entry;
3322 #if defined(ABI_ELFv2)
3323 jlong entry_address = (jlong) this->entry_point();
3324 assert(entry_address, "need address here");
3325 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3326 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3327 #else
3328 // Get the struct that describes the function we are about to call.
3329 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3330 assert(fd, "need fd here");
3331 jlong entry_address = (jlong) fd->entry();
3332 // new nodes
3333 loadConLNodesTuple loadConLNodes_Env;
3334 loadConLNodesTuple loadConLNodes_Toc;
3335
3336 // Create nodes and operands for loading the entry point.
3337 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3338 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3339
3340
3341 // Create nodes and operands for loading the env pointer.
3342 if (fd->env() != nullptr) {
3343 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3344 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3345 } else {
3346 loadConLNodes_Env._large_hi = nullptr;
3347 loadConLNodes_Env._large_lo = nullptr;
3348 loadConLNodes_Env._small = nullptr;
3349 loadConLNodes_Env._last = new loadConL16Node();
3350 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3351 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3352 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3353 }
3354
3355 // Create nodes and operands for loading the Toc point.
3356 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3357 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3358 #endif // ABI_ELFv2
3359 // mtctr node
3360 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3361
3362 assert(loadConLNodes_Entry._last != nullptr, "entry must exist");
3363 mtctr->add_req(nullptr, loadConLNodes_Entry._last);
3364
3365 mtctr->_opnds[0] = new iRegLdstOper();
3366 mtctr->_opnds[1] = new iRegLdstOper();
3367
3368 // call node
3369 MachCallLeafNode *call = new CallLeafDirectNode();
3370
3371 call->_opnds[0] = _opnds[0];
3372 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3373
3374 // Make the new call node look like the old one.
3375 call->_name = _name;
3376 call->_tf = _tf;
3377 call->_entry_point = _entry_point;
3378 call->_cnt = _cnt;
3379 call->_guaranteed_safepoint = false;
3380 call->_oop_map = _oop_map;
3381 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3382 call->_jvms = nullptr;
3383 call->_jvmadj = _jvmadj;
3384 call->_in_rms = _in_rms;
3385 call->_nesting = _nesting;
3386
3387 // New call needs all inputs of old call.
3388 // Req...
3389 for (uint i = 0; i < req(); ++i) {
3390 if (i != mach_constant_base_node_input()) {
3391 call->add_req(in(i));
3392 }
3393 }
3394
3395 // These must be reqired edges, as the registers are live up to
3396 // the call. Else the constants are handled as kills.
3397 call->add_req(mtctr);
3398 #if !defined(ABI_ELFv2)
3399 call->add_req(loadConLNodes_Env._last);
3400 call->add_req(loadConLNodes_Toc._last);
3401 #endif
3402
3403 // ...as well as prec
3404 for (uint i = req(); i < len(); ++i) {
3405 call->add_prec(in(i));
3406 }
3407
3408 // registers
3409 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3410
3411 // Insert the new nodes.
3412 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3413 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3414 #if !defined(ABI_ELFv2)
3415 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3416 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3417 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3418 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3419 #endif
3420 nodes->push(mtctr);
3421 nodes->push(call);
3422 %}
3423 %}
3424
3425 //----------FRAME--------------------------------------------------------------
3426 // Definition of frame structure and management information.
3427
3428 frame %{
3429 // These two registers define part of the calling convention between
3430 // compiled code and the interpreter.
3431
3432 // Inline Cache Register or method for I2C.
3433 inline_cache_reg(R19); // R19_method
3434
3435 // Optional: name the operand used by cisc-spilling to access
3436 // [stack_pointer + offset].
3437 cisc_spilling_operand_name(indOffset);
3438
3439 // Number of stack slots consumed by a Monitor enter.
3440 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3441
3442 // Compiled code's Frame Pointer.
3443 frame_pointer(R1); // R1_SP
3444
3445 stack_alignment(frame::alignment_in_bytes);
3446
3447 // Number of outgoing stack slots killed above the
3448 // out_preserve_stack_slots for calls to C. Supports the var-args
3449 // backing area for register parms.
3450 //
3451 varargs_C_out_slots_killed(((frame::native_abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3452
3453 // The after-PROLOG location of the return address. Location of
3454 // return address specifies a type (REG or STACK) and a number
3455 // representing the register number (i.e. - use a register name) or
3456 // stack slot.
3457 //
3458 // A: Link register is stored in stack slot ...
3459 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3460 // J: Therefore, we make sure that the link register is also in R11_scratch1
3461 // at the end of the prolog.
3462 // B: We use R20, now.
3463 //return_addr(REG R20);
3464
3465 // G: After reading the comments made by all the luminaries on their
3466 // failure to tell the compiler where the return address really is,
3467 // I hardly dare to try myself. However, I'm convinced it's in slot
3468 // 4 what apparently works and saves us some spills.
3469 return_addr(STACK 4);
3470
3471 // Location of compiled Java return values. Same as C
3472 return_value %{
3473 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3474 (ideal_reg == Op_RegN && CompressedOops::base() == nullptr && CompressedOops::shift() == 0),
3475 "only return normal values");
3476 // enum names from opcodes.hpp
3477 static int typeToRegLo[Op_RegL+1] = {
3478 0, // Op_Node
3479 0, // Op_Set
3480 R3_num, // Op_RegN
3481 R3_num, // Op_RegI
3482 R3_num, // Op_RegP
3483 F1_num, // Op_RegF
3484 F1_num, // Op_RegD
3485 R3_num, // Op_RegL
3486 };
3487
3488 static int typeToRegHi[Op_RegL+1] = {
3489 0, // Op_Node
3490 0, // Op_Set
3491 OptoReg::Bad, // Op_RegN
3492 OptoReg::Bad, // Op_RegI
3493 R3_H_num, // Op_RegP
3494 OptoReg::Bad, // Op_RegF
3495 F1_H_num, // Op_RegD
3496 R3_H_num // Op_RegL
3497 };
3498
3499 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3500 %}
3501 %}
3502
3503
3504 //----------ATTRIBUTES---------------------------------------------------------
3505
3506 //----------Operand Attributes-------------------------------------------------
3507 op_attrib op_cost(1); // Required cost attribute.
3508
3509 //----------Instruction Attributes---------------------------------------------
3510
3511 // Cost attribute. required.
3512 ins_attrib ins_cost(DEFAULT_COST);
3513
3514 // Is this instruction a non-matching short branch variant of some
3515 // long branch? Not required.
3516 ins_attrib ins_short_branch(0);
3517
3518 ins_attrib ins_is_TrapBasedCheckNode(true);
3519
3520 // Number of constants.
3521 // This instruction uses the given number of constants
3522 // (optional attribute).
3523 // This is needed to determine in time whether the constant pool will
3524 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3525 // is determined. It's also used to compute the constant pool size
3526 // in Output().
3527 ins_attrib ins_num_consts(0);
3528
3529 // Required alignment attribute (must be a power of 2) specifies the
3530 // alignment that some part of the instruction (not necessarily the
3531 // start) requires. If > 1, a compute_padding() function must be
3532 // provided for the instruction.
3533 ins_attrib ins_alignment(1);
3534
3535 // Enforce/prohibit rematerializations.
3536 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3537 // then rematerialization of that instruction is prohibited and the
3538 // instruction's value will be spilled if necessary.
3539 // Causes that MachNode::rematerialize() returns false.
3540 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3541 // then rematerialization should be enforced and a copy of the instruction
3542 // should be inserted if possible; rematerialization is not guaranteed.
3543 // Note: this may result in rematerializations in front of every use.
3544 // Causes that MachNode::rematerialize() can return true.
3545 // (optional attribute)
3546 ins_attrib ins_cannot_rematerialize(false);
3547 ins_attrib ins_should_rematerialize(false);
3548
3549 // Instruction is a nop.
3550 ins_attrib ins_is_nop(false);
3551
3552 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3553 ins_attrib ins_use_mach_if_fast_lock_node(false);
3554
3555 // Field for the toc offset of a constant.
3556 //
3557 // This is needed if the toc offset is not encodable as an immediate in
3558 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3559 // added to the toc, and from this a load with immediate is performed.
3560 // With postalloc expand, we get two nodes that require the same offset
3561 // but which don't know about each other. The offset is only known
3562 // when the constant is added to the constant pool during emitting.
3563 // It is generated in the 'hi'-node adding the upper bits, and saved
3564 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3565 // the offset from there when it gets encoded.
3566 ins_attrib ins_field_const_toc_offset(0);
3567 ins_attrib ins_field_const_toc_offset_hi_node(0);
3568
3569 // A field that can hold the instructions offset in the code buffer.
3570 // Set in the nodes emitter.
3571 ins_attrib ins_field_cbuf_insts_offset(-1);
3572
3573 // Fields for referencing a call's load-IC-node.
3574 // If the toc offset can not be encoded as an immediate in a load, we
3575 // use two nodes.
3576 ins_attrib ins_field_load_ic_hi_node(0);
3577 ins_attrib ins_field_load_ic_node(0);
3578
3579 // Whether this node is expanded during code emission into a sequence of
3580 // instructions and the first instruction can perform an implicit null check.
3581 ins_attrib ins_is_late_expanded_null_check_candidate(false);
3582
3583 //----------OPERANDS-----------------------------------------------------------
3584 // Operand definitions must precede instruction definitions for correct
3585 // parsing in the ADLC because operands constitute user defined types
3586 // which are used in instruction definitions.
3587 //
3588 // Formats are generated automatically for constants and base registers.
3589
3590 operand vecX() %{
3591 constraint(ALLOC_IN_RC(v_reg));
3592 match(VecX);
3593
3594 format %{ %}
3595 interface(REG_INTER);
3596 %}
3597
3598 //----------Simple Operands----------------------------------------------------
3599 // Immediate Operands
3600
3601 // Integer Immediate: 32-bit
3602 operand immI() %{
3603 match(ConI);
3604 op_cost(40);
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3609 operand immI8() %{
3610 predicate(Assembler::is_simm(n->get_int(), 8));
3611 op_cost(0);
3612 match(ConI);
3613 format %{ %}
3614 interface(CONST_INTER);
3615 %}
3616
3617 // Integer Immediate: 16-bit
3618 operand immI16() %{
3619 predicate(Assembler::is_simm(n->get_int(), 16));
3620 op_cost(0);
3621 match(ConI);
3622 format %{ %}
3623 interface(CONST_INTER);
3624 %}
3625
3626 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
3627 operand immIhi16() %{
3628 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
3629 match(ConI);
3630 op_cost(0);
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3634
3635 // Integer Immediate: 32-bit immediate for prefixed addi and load/store.
3636 operand immI32() %{
3637 predicate(PowerArchitecturePPC64 >= 10);
3638 op_cost(0);
3639 match(ConI);
3640 format %{ %}
3641 interface(CONST_INTER);
3642 %}
3643
3644 operand immInegpow2() %{
3645 predicate(is_power_of_2(-(juint)(n->get_int())));
3646 match(ConI);
3647 op_cost(0);
3648 format %{ %}
3649 interface(CONST_INTER);
3650 %}
3651
3652 operand immIpow2minus1() %{
3653 predicate(is_power_of_2((juint)(n->get_int()) + 1u));
3654 match(ConI);
3655 op_cost(0);
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 operand immIpowerOf2() %{
3661 predicate(is_power_of_2((juint)(n->get_int())));
3662 match(ConI);
3663 op_cost(0);
3664 format %{ %}
3665 interface(CONST_INTER);
3666 %}
3667
3668 // Unsigned Integer Immediate: the values 0-31
3669 operand uimmI5() %{
3670 predicate(Assembler::is_uimm(n->get_int(), 5));
3671 match(ConI);
3672 op_cost(0);
3673 format %{ %}
3674 interface(CONST_INTER);
3675 %}
3676
3677 // Unsigned Integer Immediate: 6-bit
3678 operand uimmI6() %{
3679 predicate(Assembler::is_uimm(n->get_int(), 6));
3680 match(ConI);
3681 op_cost(0);
3682 format %{ %}
3683 interface(CONST_INTER);
3684 %}
3685
3686 // Unsigned Integer Immediate: 6-bit int, greater than 32
3687 operand uimmI6_ge32() %{
3688 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
3689 match(ConI);
3690 op_cost(0);
3691 format %{ %}
3692 interface(CONST_INTER);
3693 %}
3694
3695 // Unsigned Integer Immediate: 15-bit
3696 operand uimmI15() %{
3697 predicate(Assembler::is_uimm(n->get_int(), 15));
3698 match(ConI);
3699 op_cost(0);
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3703
3704 // Unsigned Integer Immediate: 16-bit
3705 operand uimmI16() %{
3706 predicate(Assembler::is_uimm(n->get_int(), 16));
3707 match(ConI);
3708 op_cost(0);
3709 format %{ %}
3710 interface(CONST_INTER);
3711 %}
3712
3713 // constant 'int 0'.
3714 operand immI_0() %{
3715 predicate(n->get_int() == 0);
3716 match(ConI);
3717 op_cost(0);
3718 format %{ %}
3719 interface(CONST_INTER);
3720 %}
3721
3722 // constant 'int 1'.
3723 operand immI_1() %{
3724 predicate(n->get_int() == 1);
3725 match(ConI);
3726 op_cost(0);
3727 format %{ %}
3728 interface(CONST_INTER);
3729 %}
3730
3731 // constant 'int -1'.
3732 operand immI_minus1() %{
3733 predicate(n->get_int() == -1);
3734 match(ConI);
3735 op_cost(0);
3736 format %{ %}
3737 interface(CONST_INTER);
3738 %}
3739
3740 // int value 16.
3741 operand immI_16() %{
3742 predicate(n->get_int() == 16);
3743 match(ConI);
3744 op_cost(0);
3745 format %{ %}
3746 interface(CONST_INTER);
3747 %}
3748
3749 // int value 24.
3750 operand immI_24() %{
3751 predicate(n->get_int() == 24);
3752 match(ConI);
3753 op_cost(0);
3754 format %{ %}
3755 interface(CONST_INTER);
3756 %}
3757
3758 // Compressed oops constants
3759 // Pointer Immediate
3760 operand immN() %{
3761 match(ConN);
3762
3763 op_cost(10);
3764 format %{ %}
3765 interface(CONST_INTER);
3766 %}
3767
3768 // nullptr Pointer Immediate
3769 operand immN_0() %{
3770 predicate(n->get_narrowcon() == 0);
3771 match(ConN);
3772
3773 op_cost(0);
3774 format %{ %}
3775 interface(CONST_INTER);
3776 %}
3777
3778 // Compressed klass constants
3779 operand immNKlass() %{
3780 match(ConNKlass);
3781
3782 op_cost(0);
3783 format %{ %}
3784 interface(CONST_INTER);
3785 %}
3786
3787 // This operand can be used to avoid matching of an instruct
3788 // with chain rule.
3789 operand immNKlass_NM() %{
3790 match(ConNKlass);
3791 predicate(false);
3792 op_cost(0);
3793 format %{ %}
3794 interface(CONST_INTER);
3795 %}
3796
3797 // Pointer Immediate: 64-bit
3798 operand immP() %{
3799 match(ConP);
3800 op_cost(0);
3801 format %{ %}
3802 interface(CONST_INTER);
3803 %}
3804
3805 // Operand to avoid match of loadConP.
3806 // This operand can be used to avoid matching of an instruct
3807 // with chain rule.
3808 operand immP_NM() %{
3809 match(ConP);
3810 predicate(false);
3811 op_cost(0);
3812 format %{ %}
3813 interface(CONST_INTER);
3814 %}
3815
3816 // constant 'pointer 0'.
3817 operand immP_0() %{
3818 predicate(n->get_ptr() == 0);
3819 match(ConP);
3820 op_cost(0);
3821 format %{ %}
3822 interface(CONST_INTER);
3823 %}
3824
3825 // pointer 0x0 or 0x1
3826 operand immP_0or1() %{
3827 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
3828 match(ConP);
3829 op_cost(0);
3830 format %{ %}
3831 interface(CONST_INTER);
3832 %}
3833
3834 operand immL() %{
3835 match(ConL);
3836 op_cost(40);
3837 format %{ %}
3838 interface(CONST_INTER);
3839 %}
3840
3841 operand immLmax30() %{
3842 predicate((n->get_long() <= 30));
3843 match(ConL);
3844 op_cost(0);
3845 format %{ %}
3846 interface(CONST_INTER);
3847 %}
3848
3849 // Long Immediate: 16-bit
3850 operand immL16() %{
3851 predicate(Assembler::is_simm(n->get_long(), 16));
3852 match(ConL);
3853 op_cost(0);
3854 format %{ %}
3855 interface(CONST_INTER);
3856 %}
3857
3858 // Long Immediate: 16-bit, 4-aligned
3859 operand immL16Alg4() %{
3860 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
3861 match(ConL);
3862 op_cost(0);
3863 format %{ %}
3864 interface(CONST_INTER);
3865 %}
3866
3867 // Long Immediate: 16-bit, 16-aligned
3868 operand immL16Alg16() %{
3869 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0xf) == 0));
3870 match(ConL);
3871 op_cost(0);
3872 format %{ %}
3873 interface(CONST_INTER);
3874 %}
3875
3876 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
3877 operand immL32hi16() %{
3878 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
3879 match(ConL);
3880 op_cost(0);
3881 format %{ %}
3882 interface(CONST_INTER);
3883 %}
3884
3885 // Long Immediate: 32-bit
3886 operand immL32() %{
3887 predicate(Assembler::is_simm(n->get_long(), 32));
3888 match(ConL);
3889 op_cost(0);
3890 format %{ %}
3891 interface(CONST_INTER);
3892 %}
3893
3894 // Long Immediate: 34-bit, immediate field in prefixed addi and load/store.
3895 operand immL34() %{
3896 predicate(PowerArchitecturePPC64 >= 10 && Assembler::is_simm(n->get_long(), 34));
3897 match(ConL);
3898 op_cost(0);
3899 format %{ %}
3900 interface(CONST_INTER);
3901 %}
3902
3903 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
3904 operand immLhighest16() %{
3905 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
3906 match(ConL);
3907 op_cost(0);
3908 format %{ %}
3909 interface(CONST_INTER);
3910 %}
3911
3912 operand immLnegpow2() %{
3913 predicate(is_power_of_2(-(julong)(n->get_long())));
3914 match(ConL);
3915 op_cost(0);
3916 format %{ %}
3917 interface(CONST_INTER);
3918 %}
3919
3920 operand immLpow2minus1() %{
3921 predicate(is_power_of_2((julong)(n->get_long()) + 1ull));
3922 match(ConL);
3923 op_cost(0);
3924 format %{ %}
3925 interface(CONST_INTER);
3926 %}
3927
3928 // constant 'long 0'.
3929 operand immL_0() %{
3930 predicate(n->get_long() == 0L);
3931 match(ConL);
3932 op_cost(0);
3933 format %{ %}
3934 interface(CONST_INTER);
3935 %}
3936
3937 // constat ' long -1'.
3938 operand immL_minus1() %{
3939 predicate(n->get_long() == -1L);
3940 match(ConL);
3941 op_cost(0);
3942 format %{ %}
3943 interface(CONST_INTER);
3944 %}
3945
3946 // Long Immediate: low 32-bit mask
3947 operand immL_32bits() %{
3948 predicate(n->get_long() == 0xFFFFFFFFL);
3949 match(ConL);
3950 op_cost(0);
3951 format %{ %}
3952 interface(CONST_INTER);
3953 %}
3954
3955 // Unsigned Long Immediate: 16-bit
3956 operand uimmL16() %{
3957 predicate(Assembler::is_uimm(n->get_long(), 16));
3958 match(ConL);
3959 op_cost(0);
3960 format %{ %}
3961 interface(CONST_INTER);
3962 %}
3963
3964 // Float Immediate
3965 operand immF() %{
3966 match(ConF);
3967 op_cost(40);
3968 format %{ %}
3969 interface(CONST_INTER);
3970 %}
3971
3972 // Float Immediate: +0.0f.
3973 operand immF_0() %{
3974 predicate(jint_cast(n->getf()) == 0);
3975 match(ConF);
3976
3977 op_cost(0);
3978 format %{ %}
3979 interface(CONST_INTER);
3980 %}
3981
3982 // Double Immediate
3983 operand immD() %{
3984 match(ConD);
3985 op_cost(40);
3986 format %{ %}
3987 interface(CONST_INTER);
3988 %}
3989
3990 // Double Immediate: +0.0d.
3991 operand immD_0() %{
3992 predicate(jlong_cast(n->getd()) == 0);
3993 match(ConD);
3994
3995 op_cost(0);
3996 format %{ %}
3997 interface(CONST_INTER);
3998 %}
3999
4000 // Integer Register Operands
4001 // Integer Destination Register
4002 // See definition of reg_class bits32_reg_rw.
4003 operand iRegIdst() %{
4004 constraint(ALLOC_IN_RC(bits32_reg_rw));
4005 match(RegI);
4006 match(rscratch1RegI);
4007 match(rscratch2RegI);
4008 match(rarg1RegI);
4009 match(rarg2RegI);
4010 match(rarg3RegI);
4011 match(rarg4RegI);
4012 format %{ %}
4013 interface(REG_INTER);
4014 %}
4015
4016 // Integer Source Register
4017 // See definition of reg_class bits32_reg_ro.
4018 operand iRegIsrc() %{
4019 constraint(ALLOC_IN_RC(bits32_reg_ro));
4020 match(RegI);
4021 match(rscratch1RegI);
4022 match(rscratch2RegI);
4023 match(rarg1RegI);
4024 match(rarg2RegI);
4025 match(rarg3RegI);
4026 match(rarg4RegI);
4027 format %{ %}
4028 interface(REG_INTER);
4029 %}
4030
4031 operand rscratch1RegI() %{
4032 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4033 match(iRegIdst);
4034 format %{ %}
4035 interface(REG_INTER);
4036 %}
4037
4038 operand rscratch2RegI() %{
4039 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4040 match(iRegIdst);
4041 format %{ %}
4042 interface(REG_INTER);
4043 %}
4044
4045 operand rarg1RegI() %{
4046 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4047 match(iRegIdst);
4048 format %{ %}
4049 interface(REG_INTER);
4050 %}
4051
4052 operand rarg2RegI() %{
4053 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4054 match(iRegIdst);
4055 format %{ %}
4056 interface(REG_INTER);
4057 %}
4058
4059 operand rarg3RegI() %{
4060 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4061 match(iRegIdst);
4062 format %{ %}
4063 interface(REG_INTER);
4064 %}
4065
4066 operand rarg4RegI() %{
4067 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4068 match(iRegIdst);
4069 format %{ %}
4070 interface(REG_INTER);
4071 %}
4072
4073 operand rarg1RegL() %{
4074 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4075 match(iRegLdst);
4076 format %{ %}
4077 interface(REG_INTER);
4078 %}
4079
4080 // Pointer Destination Register
4081 // See definition of reg_class bits64_reg_rw.
4082 operand iRegPdst() %{
4083 constraint(ALLOC_IN_RC(bits64_reg_rw));
4084 match(RegP);
4085 match(rscratch1RegP);
4086 match(rscratch2RegP);
4087 match(rarg1RegP);
4088 match(rarg2RegP);
4089 match(rarg3RegP);
4090 match(rarg4RegP);
4091 format %{ %}
4092 interface(REG_INTER);
4093 %}
4094
4095 // Pointer Destination Register
4096 // Operand not using r11 and r12 (killed in epilog).
4097 operand iRegPdstNoScratch() %{
4098 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4099 match(RegP);
4100 match(rarg1RegP);
4101 match(rarg2RegP);
4102 match(rarg3RegP);
4103 match(rarg4RegP);
4104 format %{ %}
4105 interface(REG_INTER);
4106 %}
4107
4108 // Pointer Source Register
4109 // See definition of reg_class bits64_reg_ro.
4110 operand iRegPsrc() %{
4111 constraint(ALLOC_IN_RC(bits64_reg_ro));
4112 match(RegP);
4113 match(iRegPdst);
4114 match(rscratch1RegP);
4115 match(rscratch2RegP);
4116 match(rarg1RegP);
4117 match(rarg2RegP);
4118 match(rarg3RegP);
4119 match(rarg4RegP);
4120 match(rarg5RegP);
4121 match(rarg6RegP);
4122 match(threadRegP);
4123 format %{ %}
4124 interface(REG_INTER);
4125 %}
4126
4127 // Thread operand.
4128 operand threadRegP() %{
4129 constraint(ALLOC_IN_RC(thread_bits64_reg));
4130 match(iRegPdst);
4131 format %{ "R16" %}
4132 interface(REG_INTER);
4133 %}
4134
4135 operand rscratch1RegP() %{
4136 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4137 match(iRegPdst);
4138 format %{ "R11" %}
4139 interface(REG_INTER);
4140 %}
4141
4142 operand rscratch2RegP() %{
4143 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4144 match(iRegPdst);
4145 format %{ %}
4146 interface(REG_INTER);
4147 %}
4148
4149 operand rarg1RegP() %{
4150 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4151 match(iRegPdst);
4152 format %{ %}
4153 interface(REG_INTER);
4154 %}
4155
4156 operand rarg2RegP() %{
4157 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4158 match(iRegPdst);
4159 format %{ %}
4160 interface(REG_INTER);
4161 %}
4162
4163 operand rarg3RegP() %{
4164 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4165 match(iRegPdst);
4166 format %{ %}
4167 interface(REG_INTER);
4168 %}
4169
4170 operand rarg4RegP() %{
4171 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4172 match(iRegPdst);
4173 format %{ %}
4174 interface(REG_INTER);
4175 %}
4176
4177 operand rarg5RegP() %{
4178 constraint(ALLOC_IN_RC(rarg5_bits64_reg));
4179 match(iRegPdst);
4180 format %{ %}
4181 interface(REG_INTER);
4182 %}
4183
4184 operand rarg6RegP() %{
4185 constraint(ALLOC_IN_RC(rarg6_bits64_reg));
4186 match(iRegPdst);
4187 format %{ %}
4188 interface(REG_INTER);
4189 %}
4190
4191 operand iRegNsrc() %{
4192 constraint(ALLOC_IN_RC(bits32_reg_ro));
4193 match(RegN);
4194 match(iRegNdst);
4195
4196 format %{ %}
4197 interface(REG_INTER);
4198 %}
4199
4200 operand iRegNdst() %{
4201 constraint(ALLOC_IN_RC(bits32_reg_rw));
4202 match(RegN);
4203
4204 format %{ %}
4205 interface(REG_INTER);
4206 %}
4207
4208 // Long Destination Register
4209 // See definition of reg_class bits64_reg_rw.
4210 operand iRegLdst() %{
4211 constraint(ALLOC_IN_RC(bits64_reg_rw));
4212 match(RegL);
4213 match(rscratch1RegL);
4214 match(rscratch2RegL);
4215 format %{ %}
4216 interface(REG_INTER);
4217 %}
4218
4219 // Long Source Register
4220 // See definition of reg_class bits64_reg_ro.
4221 operand iRegLsrc() %{
4222 constraint(ALLOC_IN_RC(bits64_reg_ro));
4223 match(RegL);
4224 match(iRegLdst);
4225 match(rscratch1RegL);
4226 match(rscratch2RegL);
4227 format %{ %}
4228 interface(REG_INTER);
4229 %}
4230
4231 // Special operand for ConvL2I.
4232 operand iRegL2Isrc(iRegLsrc reg) %{
4233 constraint(ALLOC_IN_RC(bits64_reg_ro));
4234 match(ConvL2I reg);
4235 format %{ "ConvL2I($reg)" %}
4236 interface(REG_INTER)
4237 %}
4238
4239 operand rscratch1RegL() %{
4240 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4241 match(RegL);
4242 format %{ %}
4243 interface(REG_INTER);
4244 %}
4245
4246 operand rscratch2RegL() %{
4247 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4248 match(RegL);
4249 format %{ %}
4250 interface(REG_INTER);
4251 %}
4252
4253 // Condition Code Flag Registers
4254 operand flagsReg() %{
4255 constraint(ALLOC_IN_RC(int_flags));
4256 match(RegFlags);
4257 format %{ %}
4258 interface(REG_INTER);
4259 %}
4260
4261 operand flagsRegSrc() %{
4262 constraint(ALLOC_IN_RC(int_flags_ro));
4263 match(RegFlags);
4264 match(flagsReg);
4265 match(flagsRegCR0);
4266 format %{ %}
4267 interface(REG_INTER);
4268 %}
4269
4270 // Condition Code Flag Register CR0
4271 operand flagsRegCR0() %{
4272 constraint(ALLOC_IN_RC(int_flags_CR0));
4273 match(RegFlags);
4274 format %{ "CR0" %}
4275 interface(REG_INTER);
4276 %}
4277
4278 operand flagsRegCR1() %{
4279 constraint(ALLOC_IN_RC(int_flags_CR1));
4280 match(RegFlags);
4281 format %{ "CR1" %}
4282 interface(REG_INTER);
4283 %}
4284
4285 operand flagsRegCR6() %{
4286 constraint(ALLOC_IN_RC(int_flags_CR6));
4287 match(RegFlags);
4288 format %{ "CR6" %}
4289 interface(REG_INTER);
4290 %}
4291
4292 operand regCTR() %{
4293 constraint(ALLOC_IN_RC(ctr_reg));
4294 // RegFlags should work. Introducing a RegSpecial type would cause a
4295 // lot of changes.
4296 match(RegFlags);
4297 format %{"SR_CTR" %}
4298 interface(REG_INTER);
4299 %}
4300
4301 operand regD() %{
4302 constraint(ALLOC_IN_RC(dbl_reg));
4303 match(RegD);
4304 format %{ %}
4305 interface(REG_INTER);
4306 %}
4307
4308 operand regF() %{
4309 constraint(ALLOC_IN_RC(flt_reg));
4310 match(RegF);
4311 format %{ %}
4312 interface(REG_INTER);
4313 %}
4314
4315 // Special Registers
4316
4317 // Method Register
4318 operand inline_cache_regP(iRegPdst reg) %{
4319 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4320 match(reg);
4321 format %{ %}
4322 interface(REG_INTER);
4323 %}
4324
4325 // Operands to remove register moves in unscaled mode.
4326 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4327 operand iRegP2N(iRegPsrc reg) %{
4328 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& CompressedOops::shift() == 0);
4329 constraint(ALLOC_IN_RC(bits64_reg_ro));
4330 match(EncodeP reg);
4331 format %{ "$reg" %}
4332 interface(REG_INTER)
4333 %}
4334
4335 operand iRegN2P(iRegNsrc reg) %{
4336 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4337 constraint(ALLOC_IN_RC(bits32_reg_ro));
4338 match(DecodeN reg);
4339 format %{ "$reg" %}
4340 interface(REG_INTER)
4341 %}
4342
4343 operand iRegN2P_klass(iRegNsrc reg) %{
4344 predicate(CompressedKlassPointers::base() == nullptr && CompressedKlassPointers::shift() == 0);
4345 constraint(ALLOC_IN_RC(bits32_reg_ro));
4346 match(DecodeNKlass reg);
4347 format %{ "$reg" %}
4348 interface(REG_INTER)
4349 %}
4350
4351 //----------Complex Operands---------------------------------------------------
4352 // Indirect Memory Reference
4353 operand indirect(iRegPsrc reg) %{
4354 constraint(ALLOC_IN_RC(bits64_reg_ro));
4355 match(reg);
4356 op_cost(100);
4357 format %{ "[$reg]" %}
4358 interface(MEMORY_INTER) %{
4359 base($reg);
4360 index(0x0);
4361 scale(0x0);
4362 disp(0x0);
4363 %}
4364 %}
4365
4366 // Indirect with Offset
4367 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4368 constraint(ALLOC_IN_RC(bits64_reg_ro));
4369 match(AddP reg offset);
4370 op_cost(100);
4371 format %{ "[$reg + $offset]" %}
4372 interface(MEMORY_INTER) %{
4373 base($reg);
4374 index(0x0);
4375 scale(0x0);
4376 disp($offset);
4377 %}
4378 %}
4379
4380 // Indirect with 4-aligned Offset
4381 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4382 constraint(ALLOC_IN_RC(bits64_reg_ro));
4383 match(AddP reg offset);
4384 op_cost(100);
4385 format %{ "[$reg + $offset]" %}
4386 interface(MEMORY_INTER) %{
4387 base($reg);
4388 index(0x0);
4389 scale(0x0);
4390 disp($offset);
4391 %}
4392 %}
4393
4394 // Indirect with 16-aligned Offset
4395 operand indOffset16Alg16(iRegPsrc reg, immL16Alg16 offset) %{
4396 constraint(ALLOC_IN_RC(bits64_reg_ro));
4397 match(AddP reg offset);
4398 op_cost(100);
4399 format %{ "[$reg + $offset]" %}
4400 interface(MEMORY_INTER) %{
4401 base($reg);
4402 index(0x0);
4403 scale(0x0);
4404 disp($offset);
4405 %}
4406 %}
4407
4408 //----------Complex Operands for Compressed OOPs-------------------------------
4409 // Compressed OOPs with narrow_oop_shift == 0.
4410
4411 // Indirect Memory Reference, compressed OOP
4412 operand indirectNarrow(iRegNsrc reg) %{
4413 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4414 constraint(ALLOC_IN_RC(bits64_reg_ro));
4415 match(DecodeN reg);
4416 op_cost(100);
4417 format %{ "[$reg]" %}
4418 interface(MEMORY_INTER) %{
4419 base($reg);
4420 index(0x0);
4421 scale(0x0);
4422 disp(0x0);
4423 %}
4424 %}
4425
4426 operand indirectNarrow_klass(iRegNsrc reg) %{
4427 predicate(CompressedKlassPointers::base() == nullptr && CompressedKlassPointers::shift() == 0);
4428 constraint(ALLOC_IN_RC(bits64_reg_ro));
4429 match(DecodeNKlass reg);
4430 op_cost(100);
4431 format %{ "[$reg]" %}
4432 interface(MEMORY_INTER) %{
4433 base($reg);
4434 index(0x0);
4435 scale(0x0);
4436 disp(0x0);
4437 %}
4438 %}
4439
4440 // Indirect with Offset, compressed OOP
4441 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4442 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4443 constraint(ALLOC_IN_RC(bits64_reg_ro));
4444 match(AddP (DecodeN reg) offset);
4445 op_cost(100);
4446 format %{ "[$reg + $offset]" %}
4447 interface(MEMORY_INTER) %{
4448 base($reg);
4449 index(0x0);
4450 scale(0x0);
4451 disp($offset);
4452 %}
4453 %}
4454
4455 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4456 predicate(CompressedKlassPointers::base() == nullptr && CompressedKlassPointers::shift() == 0);
4457 constraint(ALLOC_IN_RC(bits64_reg_ro));
4458 match(AddP (DecodeNKlass reg) offset);
4459 op_cost(100);
4460 format %{ "[$reg + $offset]" %}
4461 interface(MEMORY_INTER) %{
4462 base($reg);
4463 index(0x0);
4464 scale(0x0);
4465 disp($offset);
4466 %}
4467 %}
4468
4469 // Indirect with 4-aligned Offset, compressed OOP
4470 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4471 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4472 constraint(ALLOC_IN_RC(bits64_reg_ro));
4473 match(AddP (DecodeN reg) offset);
4474 op_cost(100);
4475 format %{ "[$reg + $offset]" %}
4476 interface(MEMORY_INTER) %{
4477 base($reg);
4478 index(0x0);
4479 scale(0x0);
4480 disp($offset);
4481 %}
4482 %}
4483
4484 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4485 predicate(CompressedKlassPointers::base() == nullptr && CompressedKlassPointers::shift() == 0);
4486 constraint(ALLOC_IN_RC(bits64_reg_ro));
4487 match(AddP (DecodeNKlass reg) offset);
4488 op_cost(100);
4489 format %{ "[$reg + $offset]" %}
4490 interface(MEMORY_INTER) %{
4491 base($reg);
4492 index(0x0);
4493 scale(0x0);
4494 disp($offset);
4495 %}
4496 %}
4497
4498 //----------Special Memory Operands--------------------------------------------
4499 // Stack Slot Operand
4500 //
4501 // This operand is used for loading and storing temporary values on
4502 // the stack where a match requires a value to flow through memory.
4503 operand stackSlotI(sRegI reg) %{
4504 constraint(ALLOC_IN_RC(stack_slots));
4505 op_cost(100);
4506 //match(RegI);
4507 format %{ "[sp+$reg]" %}
4508 interface(MEMORY_INTER) %{
4509 base(0x1); // R1_SP
4510 index(0x0);
4511 scale(0x0);
4512 disp($reg); // Stack Offset
4513 %}
4514 %}
4515
4516 operand stackSlotL(sRegL reg) %{
4517 constraint(ALLOC_IN_RC(stack_slots));
4518 op_cost(100);
4519 //match(RegL);
4520 format %{ "[sp+$reg]" %}
4521 interface(MEMORY_INTER) %{
4522 base(0x1); // R1_SP
4523 index(0x0);
4524 scale(0x0);
4525 disp($reg); // Stack Offset
4526 %}
4527 %}
4528
4529 operand stackSlotP(sRegP reg) %{
4530 constraint(ALLOC_IN_RC(stack_slots));
4531 op_cost(100);
4532 //match(RegP);
4533 format %{ "[sp+$reg]" %}
4534 interface(MEMORY_INTER) %{
4535 base(0x1); // R1_SP
4536 index(0x0);
4537 scale(0x0);
4538 disp($reg); // Stack Offset
4539 %}
4540 %}
4541
4542 operand stackSlotF(sRegF reg) %{
4543 constraint(ALLOC_IN_RC(stack_slots));
4544 op_cost(100);
4545 //match(RegF);
4546 format %{ "[sp+$reg]" %}
4547 interface(MEMORY_INTER) %{
4548 base(0x1); // R1_SP
4549 index(0x0);
4550 scale(0x0);
4551 disp($reg); // Stack Offset
4552 %}
4553 %}
4554
4555 operand stackSlotD(sRegD reg) %{
4556 constraint(ALLOC_IN_RC(stack_slots));
4557 op_cost(100);
4558 //match(RegD);
4559 format %{ "[sp+$reg]" %}
4560 interface(MEMORY_INTER) %{
4561 base(0x1); // R1_SP
4562 index(0x0);
4563 scale(0x0);
4564 disp($reg); // Stack Offset
4565 %}
4566 %}
4567
4568 // Operands for expressing Control Flow
4569 // NOTE: Label is a predefined operand which should not be redefined in
4570 // the AD file. It is generically handled within the ADLC.
4571
4572 //----------Conditional Branch Operands----------------------------------------
4573 // Comparison Op
4574 //
4575 // This is the operation of the comparison, and is limited to the
4576 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4577 // (!=).
4578 //
4579 // Other attributes of the comparison, such as unsignedness, are specified
4580 // by the comparison instruction that sets a condition code flags register.
4581 // That result is represented by a flags operand whose subtype is appropriate
4582 // to the unsignedness (etc.) of the comparison.
4583 //
4584 // Later, the instruction which matches both the Comparison Op (a Bool) and
4585 // the flags (produced by the Cmp) specifies the coding of the comparison op
4586 // by matching a specific subtype of Bool operand below.
4587
4588 // When used for floating point comparisons: unordered same as less.
4589 operand cmpOp() %{
4590 match(Bool);
4591 format %{ "" %}
4592 interface(COND_INTER) %{
4593 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4594 // BO & BI
4595 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4596 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4597 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4598 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4599 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4600 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4601 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4602 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4603 %}
4604 %}
4605
4606 //----------OPERAND CLASSES----------------------------------------------------
4607 // Operand Classes are groups of operands that are used to simplify
4608 // instruction definitions by not requiring the AD writer to specify
4609 // separate instructions for every form of operand when the
4610 // instruction accepts multiple operand types with the same basic
4611 // encoding and format. The classic case of this is memory operands.
4612 // Indirect is not included since its use is limited to Compare & Swap.
4613
4614 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4615 // Memory operand where offsets are 4-aligned. Required for ld, std.
4616 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4617 opclass memoryAlg16(indirect, indOffset16Alg16);
4618 opclass indirectMemory(indirect, indirectNarrow);
4619
4620 // Special opclass for I and ConvL2I.
4621 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4622
4623 // Operand classes to match encode and decode. iRegN_P2N is only used
4624 // for storeN. I have never seen an encode node elsewhere.
4625 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4626 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4627
4628 //----------PIPELINE-----------------------------------------------------------
4629
4630 pipeline %{
4631
4632 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4633 // J. Res. & Dev., No. 1, Jan. 2002.
4634
4635 //----------ATTRIBUTES---------------------------------------------------------
4636 attributes %{
4637
4638 // Power4 instructions are of fixed length.
4639 fixed_size_instructions;
4640
4641 // TODO: if `bundle' means number of instructions fetched
4642 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4643 // max instructions issued per cycle, this is 5.
4644 max_instructions_per_bundle = 8;
4645
4646 // A Power4 instruction is 4 bytes long.
4647 instruction_unit_size = 4;
4648
4649 // The Power4 processor fetches 64 bytes...
4650 instruction_fetch_unit_size = 64;
4651
4652 // ...in one line
4653 instruction_fetch_units = 1
4654 %}
4655
4656 //----------RESOURCES----------------------------------------------------------
4657 // Resources are the functional units available to the machine
4658 resources(
4659 PPC_BR, // branch unit
4660 PPC_CR, // condition unit
4661 PPC_FX1, // integer arithmetic unit 1
4662 PPC_FX2, // integer arithmetic unit 2
4663 PPC_LDST1, // load/store unit 1
4664 PPC_LDST2, // load/store unit 2
4665 PPC_FP1, // float arithmetic unit 1
4666 PPC_FP2, // float arithmetic unit 2
4667 PPC_LDST = PPC_LDST1 | PPC_LDST2,
4668 PPC_FX = PPC_FX1 | PPC_FX2,
4669 PPC_FP = PPC_FP1 | PPC_FP2
4670 );
4671
4672 //----------PIPELINE DESCRIPTION-----------------------------------------------
4673 // Pipeline Description specifies the stages in the machine's pipeline
4674 pipe_desc(
4675 // Power4 longest pipeline path
4676 PPC_IF, // instruction fetch
4677 PPC_IC,
4678 //PPC_BP, // branch prediction
4679 PPC_D0, // decode
4680 PPC_D1, // decode
4681 PPC_D2, // decode
4682 PPC_D3, // decode
4683 PPC_Xfer1,
4684 PPC_GD, // group definition
4685 PPC_MP, // map
4686 PPC_ISS, // issue
4687 PPC_RF, // resource fetch
4688 PPC_EX1, // execute (all units)
4689 PPC_EX2, // execute (FP, LDST)
4690 PPC_EX3, // execute (FP, LDST)
4691 PPC_EX4, // execute (FP)
4692 PPC_EX5, // execute (FP)
4693 PPC_EX6, // execute (FP)
4694 PPC_WB, // write back
4695 PPC_Xfer2,
4696 PPC_CP
4697 );
4698
4699 //----------PIPELINE CLASSES---------------------------------------------------
4700 // Pipeline Classes describe the stages in which input and output are
4701 // referenced by the hardware pipeline.
4702
4703 // Simple pipeline classes.
4704
4705 // Default pipeline class.
4706 pipe_class pipe_class_default() %{
4707 single_instruction;
4708 fixed_latency(2);
4709 %}
4710
4711 // Pipeline class for empty instructions.
4712 pipe_class pipe_class_empty() %{
4713 single_instruction;
4714 fixed_latency(0);
4715 %}
4716
4717 // Pipeline class for compares.
4718 pipe_class pipe_class_compare() %{
4719 single_instruction;
4720 fixed_latency(16);
4721 %}
4722
4723 // Pipeline class for traps.
4724 pipe_class pipe_class_trap() %{
4725 single_instruction;
4726 fixed_latency(100);
4727 %}
4728
4729 // Pipeline class for memory operations.
4730 pipe_class pipe_class_memory() %{
4731 single_instruction;
4732 fixed_latency(16);
4733 %}
4734
4735 // Pipeline class for call.
4736 pipe_class pipe_class_call() %{
4737 single_instruction;
4738 fixed_latency(100);
4739 %}
4740
4741 // Define the class for the Nop node.
4742 define %{
4743 MachNop = pipe_class_default;
4744 %}
4745
4746 %}
4747
4748 //----------INSTRUCTIONS-------------------------------------------------------
4749
4750 // Naming of instructions:
4751 // opA_operB / opA_operB_operC:
4752 // Operation 'op' with one or two source operands 'oper'. Result
4753 // type is A, source operand types are B and C.
4754 // Iff A == B == C, B and C are left out.
4755 //
4756 // The instructions are ordered according to the following scheme:
4757 // - loads
4758 // - load constants
4759 // - prefetch
4760 // - store
4761 // - encode/decode
4762 // - membar
4763 // - conditional moves
4764 // - compare & swap
4765 // - arithmetic and logic operations
4766 // * int: Add, Sub, Mul, Div, Mod
4767 // * int: lShift, arShift, urShift, rot
4768 // * float: Add, Sub, Mul, Div
4769 // * and, or, xor ...
4770 // - register moves: float <-> int, reg <-> stack, repl
4771 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
4772 // - conv (low level type cast requiring bit changes (sign extend etc)
4773 // - compares, range & zero checks.
4774 // - branches
4775 // - complex operations, intrinsics, min, max, replicate
4776 // - lock
4777 // - Calls
4778 //
4779 // If there are similar instructions with different types they are sorted:
4780 // int before float
4781 // small before big
4782 // signed before unsigned
4783 // e.g., loadS before loadUS before loadI before loadF.
4784
4785
4786 //----------Load/Store Instructions--------------------------------------------
4787
4788 //----------Load Instructions--------------------------------------------------
4789
4790 // Converts byte to int.
4791 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
4792 // reuses the 'amount' operand, but adlc expects that operand specification
4793 // and operands in match rule are equivalent.
4794 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
4795 effect(DEF dst, USE src);
4796 format %{ "EXTSB $dst, $src \t// byte->int" %}
4797 size(4);
4798 ins_encode %{
4799 __ extsb($dst$$Register, $src$$Register);
4800 %}
4801 ins_pipe(pipe_class_default);
4802 %}
4803
4804 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
4805 // match-rule, false predicate
4806 match(Set dst (LoadB mem));
4807 predicate(false);
4808
4809 format %{ "LBZ $dst, $mem" %}
4810 size(4);
4811 ins_encode( enc_lbz(dst, mem) );
4812 ins_pipe(pipe_class_memory);
4813 %}
4814
4815 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
4816 // match-rule, false predicate
4817 match(Set dst (LoadB mem));
4818 predicate(false);
4819
4820 format %{ "LBZ $dst, $mem\n\t"
4821 "TWI $dst\n\t"
4822 "ISYNC" %}
4823 size(12);
4824 ins_encode( enc_lbz_ac(dst, mem) );
4825 ins_pipe(pipe_class_memory);
4826 %}
4827
4828 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
4829 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
4830 match(Set dst (LoadB mem));
4831 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
4832 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
4833 expand %{
4834 iRegIdst tmp;
4835 loadUB_indirect(tmp, mem);
4836 convB2I_reg_2(dst, tmp);
4837 %}
4838 %}
4839
4840 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
4841 match(Set dst (LoadB mem));
4842 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
4843 expand %{
4844 iRegIdst tmp;
4845 loadUB_indirect_ac(tmp, mem);
4846 convB2I_reg_2(dst, tmp);
4847 %}
4848 %}
4849
4850 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
4851 // match-rule, false predicate
4852 match(Set dst (LoadB mem));
4853 predicate(false);
4854
4855 format %{ "LBZ $dst, $mem" %}
4856 size(4);
4857 ins_encode( enc_lbz(dst, mem) );
4858 ins_pipe(pipe_class_memory);
4859 %}
4860
4861 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
4862 // match-rule, false predicate
4863 match(Set dst (LoadB mem));
4864 predicate(false);
4865
4866 format %{ "LBZ $dst, $mem\n\t"
4867 "TWI $dst\n\t"
4868 "ISYNC" %}
4869 size(12);
4870 ins_encode( enc_lbz_ac(dst, mem) );
4871 ins_pipe(pipe_class_memory);
4872 %}
4873
4874 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
4875 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
4876 match(Set dst (LoadB mem));
4877 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
4878 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
4879
4880 expand %{
4881 iRegIdst tmp;
4882 loadUB_indOffset16(tmp, mem);
4883 convB2I_reg_2(dst, tmp);
4884 %}
4885 %}
4886
4887 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
4888 match(Set dst (LoadB mem));
4889 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
4890
4891 expand %{
4892 iRegIdst tmp;
4893 loadUB_indOffset16_ac(tmp, mem);
4894 convB2I_reg_2(dst, tmp);
4895 %}
4896 %}
4897
4898 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4899 instruct loadUB(iRegIdst dst, memory mem) %{
4900 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
4901 match(Set dst (LoadUB mem));
4902 ins_cost(MEMORY_REF_COST);
4903
4904 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
4905 size(4);
4906 ins_encode( enc_lbz(dst, mem) );
4907 ins_pipe(pipe_class_memory);
4908 %}
4909
4910 // Load Unsigned Byte (8bit UNsigned) acquire.
4911 instruct loadUB_ac(iRegIdst dst, memory mem) %{
4912 match(Set dst (LoadUB mem));
4913 ins_cost(3*MEMORY_REF_COST);
4914
4915 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
4916 "TWI $dst\n\t"
4917 "ISYNC" %}
4918 size(12);
4919 ins_encode( enc_lbz_ac(dst, mem) );
4920 ins_pipe(pipe_class_memory);
4921 %}
4922
4923 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4924 instruct loadUB2L(iRegLdst dst, memory mem) %{
4925 match(Set dst (ConvI2L (LoadUB mem)));
4926 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
4927 ins_cost(MEMORY_REF_COST);
4928
4929 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
4930 size(4);
4931 ins_encode( enc_lbz(dst, mem) );
4932 ins_pipe(pipe_class_memory);
4933 %}
4934
4935 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
4936 match(Set dst (ConvI2L (LoadUB mem)));
4937 ins_cost(3*MEMORY_REF_COST);
4938
4939 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
4940 "TWI $dst\n\t"
4941 "ISYNC" %}
4942 size(12);
4943 ins_encode( enc_lbz_ac(dst, mem) );
4944 ins_pipe(pipe_class_memory);
4945 %}
4946
4947 // Load Short (16bit signed)
4948 instruct loadS(iRegIdst dst, memory mem) %{
4949 match(Set dst (LoadS mem));
4950 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
4951 ins_cost(MEMORY_REF_COST);
4952
4953 format %{ "LHA $dst, $mem" %}
4954 size(4);
4955 ins_encode %{
4956 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
4957 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
4958 %}
4959 ins_pipe(pipe_class_memory);
4960 %}
4961
4962 // Load Short (16bit signed) acquire.
4963 instruct loadS_ac(iRegIdst dst, memory mem) %{
4964 match(Set dst (LoadS mem));
4965 ins_cost(3*MEMORY_REF_COST);
4966
4967 format %{ "LHA $dst, $mem\t acquire\n\t"
4968 "TWI $dst\n\t"
4969 "ISYNC" %}
4970 size(12);
4971 ins_encode %{
4972 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
4973 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
4974 __ twi_0($dst$$Register);
4975 __ isync();
4976 %}
4977 ins_pipe(pipe_class_memory);
4978 %}
4979
4980 // Load Char (16bit unsigned)
4981 instruct loadUS(iRegIdst dst, memory mem) %{
4982 match(Set dst (LoadUS mem));
4983 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
4984 ins_cost(MEMORY_REF_COST);
4985
4986 format %{ "LHZ $dst, $mem" %}
4987 size(4);
4988 ins_encode( enc_lhz(dst, mem) );
4989 ins_pipe(pipe_class_memory);
4990 %}
4991
4992 // Load Char (16bit unsigned) acquire.
4993 instruct loadUS_ac(iRegIdst dst, memory mem) %{
4994 match(Set dst (LoadUS mem));
4995 ins_cost(3*MEMORY_REF_COST);
4996
4997 format %{ "LHZ $dst, $mem \t// acquire\n\t"
4998 "TWI $dst\n\t"
4999 "ISYNC" %}
5000 size(12);
5001 ins_encode( enc_lhz_ac(dst, mem) );
5002 ins_pipe(pipe_class_memory);
5003 %}
5004
5005 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5006 instruct loadUS2L(iRegLdst dst, memory mem) %{
5007 match(Set dst (ConvI2L (LoadUS mem)));
5008 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5009 ins_cost(MEMORY_REF_COST);
5010
5011 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5012 size(4);
5013 ins_encode( enc_lhz(dst, mem) );
5014 ins_pipe(pipe_class_memory);
5015 %}
5016
5017 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5018 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5019 match(Set dst (ConvI2L (LoadUS mem)));
5020 ins_cost(3*MEMORY_REF_COST);
5021
5022 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5023 "TWI $dst\n\t"
5024 "ISYNC" %}
5025 size(12);
5026 ins_encode( enc_lhz_ac(dst, mem) );
5027 ins_pipe(pipe_class_memory);
5028 %}
5029
5030 // Load Integer.
5031 instruct loadI(iRegIdst dst, memory mem) %{
5032 match(Set dst (LoadI mem));
5033 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5034 ins_cost(MEMORY_REF_COST);
5035
5036 format %{ "LWZ $dst, $mem" %}
5037 size(4);
5038 ins_encode( enc_lwz(dst, mem) );
5039 ins_pipe(pipe_class_memory);
5040 %}
5041
5042 // Load Integer acquire.
5043 instruct loadI_ac(iRegIdst dst, memory mem) %{
5044 match(Set dst (LoadI mem));
5045 ins_cost(3*MEMORY_REF_COST);
5046
5047 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5048 "TWI $dst\n\t"
5049 "ISYNC" %}
5050 size(12);
5051 ins_encode( enc_lwz_ac(dst, mem) );
5052 ins_pipe(pipe_class_memory);
5053 %}
5054
5055 // Match loading integer and casting it to unsigned int in
5056 // long register.
5057 // LoadI + ConvI2L + AndL 0xffffffff.
5058 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5059 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5060 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5061 ins_cost(MEMORY_REF_COST);
5062
5063 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5064 size(4);
5065 ins_encode( enc_lwz(dst, mem) );
5066 ins_pipe(pipe_class_memory);
5067 %}
5068
5069 // Match loading integer and casting it to long.
5070 instruct loadI2L(iRegLdst dst, memoryAlg4 mem) %{
5071 match(Set dst (ConvI2L (LoadI mem)));
5072 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5073 ins_cost(MEMORY_REF_COST);
5074
5075 format %{ "LWA $dst, $mem \t// loadI2L" %}
5076 size(4);
5077 ins_encode %{
5078 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5079 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5080 %}
5081 ins_pipe(pipe_class_memory);
5082 %}
5083
5084 // Match loading integer and casting it to long - acquire.
5085 instruct loadI2L_ac(iRegLdst dst, memoryAlg4 mem) %{
5086 match(Set dst (ConvI2L (LoadI mem)));
5087 ins_cost(3*MEMORY_REF_COST);
5088
5089 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5090 "TWI $dst\n\t"
5091 "ISYNC" %}
5092 size(12);
5093 ins_encode %{
5094 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5095 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5096 __ twi_0($dst$$Register);
5097 __ isync();
5098 %}
5099 ins_pipe(pipe_class_memory);
5100 %}
5101
5102 // Load Long - aligned
5103 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5104 match(Set dst (LoadL mem));
5105 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5106 ins_cost(MEMORY_REF_COST);
5107
5108 format %{ "LD $dst, $mem \t// long" %}
5109 size(4);
5110 ins_encode( enc_ld(dst, mem) );
5111 ins_pipe(pipe_class_memory);
5112 %}
5113
5114 // Load Long - aligned acquire.
5115 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5116 match(Set dst (LoadL mem));
5117 ins_cost(3*MEMORY_REF_COST);
5118
5119 format %{ "LD $dst, $mem \t// long acquire\n\t"
5120 "TWI $dst\n\t"
5121 "ISYNC" %}
5122 size(12);
5123 ins_encode( enc_ld_ac(dst, mem) );
5124 ins_pipe(pipe_class_memory);
5125 %}
5126
5127 // Load Long - UNaligned
5128 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5129 match(Set dst (LoadL_unaligned mem));
5130 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5131 ins_cost(MEMORY_REF_COST);
5132
5133 format %{ "LD $dst, $mem \t// unaligned long" %}
5134 size(4);
5135 ins_encode( enc_ld(dst, mem) );
5136 ins_pipe(pipe_class_memory);
5137 %}
5138
5139 // Load nodes for superwords
5140
5141 // Load Aligned Packed Byte
5142 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5143 predicate(n->as_LoadVector()->memory_size() == 8);
5144 match(Set dst (LoadVector mem));
5145 ins_cost(MEMORY_REF_COST);
5146
5147 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5148 size(4);
5149 ins_encode( enc_ld(dst, mem) );
5150 ins_pipe(pipe_class_memory);
5151 %}
5152
5153
5154 instruct loadV16(vecX dst, memoryAlg16 mem) %{
5155 predicate(n->as_LoadVector()->memory_size() == 16);
5156 match(Set dst (LoadVector mem));
5157 ins_cost(MEMORY_REF_COST);
5158
5159 format %{ "LXV $dst, $mem \t// load 16-byte Vector" %}
5160 size(4);
5161 ins_encode %{
5162 __ lxv($dst$$VectorRegister.to_vsr(), $mem$$disp, $mem$$Register);
5163 %}
5164 ins_pipe(pipe_class_default);
5165 %}
5166
5167 // Load Range, range = array length (=jint)
5168 instruct loadRange(iRegIdst dst, memory mem) %{
5169 match(Set dst (LoadRange mem));
5170 ins_cost(MEMORY_REF_COST);
5171
5172 format %{ "LWZ $dst, $mem \t// range" %}
5173 size(4);
5174 ins_encode( enc_lwz(dst, mem) );
5175 ins_pipe(pipe_class_memory);
5176 %}
5177
5178 // Load Compressed Pointer
5179 instruct loadN(iRegNdst dst, memory mem) %{
5180 match(Set dst (LoadN mem));
5181 predicate((n->as_Load()->is_unordered() || followed_by_acquire(n)) && n->as_Load()->barrier_data() == 0);
5182 ins_cost(MEMORY_REF_COST);
5183
5184 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5185 size(4);
5186 ins_encode( enc_lwz(dst, mem) );
5187 ins_pipe(pipe_class_memory);
5188 %}
5189
5190 // Load Compressed Pointer acquire.
5191 instruct loadN_ac(iRegNdst dst, memory mem) %{
5192 match(Set dst (LoadN mem));
5193 predicate(n->as_Load()->barrier_data() == 0);
5194 ins_cost(3*MEMORY_REF_COST);
5195
5196 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5197 "TWI $dst\n\t"
5198 "ISYNC" %}
5199 size(12);
5200 ins_encode( enc_lwz_ac(dst, mem) );
5201 ins_pipe(pipe_class_memory);
5202 %}
5203
5204 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5205 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5206 match(Set dst (DecodeN (LoadN mem)));
5207 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && CompressedOops::shift() == 0 && _kids[0]->_leaf->as_Load()->barrier_data() == 0);
5208 ins_cost(MEMORY_REF_COST);
5209
5210 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5211 size(4);
5212 ins_encode( enc_lwz(dst, mem) );
5213 ins_pipe(pipe_class_memory);
5214 %}
5215
5216 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5217 match(Set dst (DecodeNKlass (LoadNKlass mem)));
5218 predicate(CompressedKlassPointers::base() == nullptr && CompressedKlassPointers::shift() == 0 &&
5219 _kids[0]->_leaf->as_Load()->is_unordered());
5220 ins_cost(MEMORY_REF_COST);
5221
5222 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5223 size(4);
5224 ins_encode( enc_lwz(dst, mem) );
5225 ins_pipe(pipe_class_memory);
5226 %}
5227
5228 // Load Pointer
5229 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5230 match(Set dst (LoadP mem));
5231 predicate((n->as_Load()->is_unordered() || followed_by_acquire(n)) && n->as_Load()->barrier_data() == 0);
5232 ins_cost(MEMORY_REF_COST);
5233
5234 format %{ "LD $dst, $mem \t// ptr" %}
5235 size(4);
5236 ins_encode( enc_ld(dst, mem) );
5237 ins_pipe(pipe_class_memory);
5238 %}
5239
5240 // Load Pointer acquire.
5241 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5242 match(Set dst (LoadP mem));
5243 ins_cost(3*MEMORY_REF_COST);
5244
5245 predicate(n->as_Load()->barrier_data() == 0);
5246
5247 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5248 "TWI $dst\n\t"
5249 "ISYNC" %}
5250 size(12);
5251 ins_encode( enc_ld_ac(dst, mem) );
5252 ins_pipe(pipe_class_memory);
5253 %}
5254
5255 // LoadP + CastP2L
5256 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5257 match(Set dst (CastP2X (LoadP mem)));
5258 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && _kids[0]->_leaf->as_Load()->barrier_data() == 0);
5259 ins_cost(MEMORY_REF_COST);
5260
5261 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5262 size(4);
5263 ins_encode( enc_ld(dst, mem) );
5264 ins_pipe(pipe_class_memory);
5265 %}
5266
5267 // Load compressed klass pointer.
5268 instruct loadNKlass(iRegNdst dst, memory mem) %{
5269 match(Set dst (LoadNKlass mem));
5270 predicate(!UseCompactObjectHeaders);
5271 ins_cost(MEMORY_REF_COST);
5272
5273 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5274 size(4);
5275 ins_encode( enc_lwz(dst, mem) );
5276 ins_pipe(pipe_class_memory);
5277 %}
5278
5279 instruct loadNKlassCompactHeaders(iRegNdst dst, memory mem) %{
5280 match(Set dst (LoadNKlass mem));
5281 predicate(UseCompactObjectHeaders);
5282 ins_cost(MEMORY_REF_COST);
5283
5284 format %{ "load_narrow_klass_compact $dst, $mem \t// compressed class ptr" %}
5285 size(8);
5286 ins_encode %{
5287 assert($mem$$index$$Register == R0, "must not have indexed address: %s[%s]", $mem$$base$$Register.name(), $mem$$index$$Register.name());
5288 __ load_narrow_klass_compact_c2($dst$$Register, $mem$$base$$Register, $mem$$disp);
5289 %}
5290 ins_pipe(pipe_class_memory);
5291 %}
5292
5293 // Load Klass Pointer
5294 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5295 match(Set dst (LoadKlass mem));
5296 ins_cost(MEMORY_REF_COST);
5297
5298 format %{ "LD $dst, $mem \t// klass ptr" %}
5299 size(4);
5300 ins_encode( enc_ld(dst, mem) );
5301 ins_pipe(pipe_class_memory);
5302 %}
5303
5304 // Load Float
5305 instruct loadF(regF dst, memory mem) %{
5306 match(Set dst (LoadF mem));
5307 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5308 ins_cost(MEMORY_REF_COST);
5309
5310 format %{ "LFS $dst, $mem" %}
5311 size(4);
5312 ins_encode %{
5313 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5314 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5315 %}
5316 ins_pipe(pipe_class_memory);
5317 %}
5318
5319 // Load Float acquire.
5320 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5321 match(Set dst (LoadF mem));
5322 effect(TEMP cr0);
5323 ins_cost(3*MEMORY_REF_COST);
5324
5325 format %{ "LFS $dst, $mem \t// acquire\n\t"
5326 "FCMPU cr0, $dst, $dst\n\t"
5327 "BNE cr0, next\n"
5328 "next:\n\t"
5329 "ISYNC" %}
5330 size(16);
5331 ins_encode %{
5332 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5333 Label next;
5334 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5335 __ fcmpu(CR0, $dst$$FloatRegister, $dst$$FloatRegister);
5336 __ bne(CR0, next);
5337 __ bind(next);
5338 __ isync();
5339 %}
5340 ins_pipe(pipe_class_memory);
5341 %}
5342
5343 // Load Double - aligned
5344 instruct loadD(regD dst, memory mem) %{
5345 match(Set dst (LoadD mem));
5346 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5347 ins_cost(MEMORY_REF_COST);
5348
5349 format %{ "LFD $dst, $mem" %}
5350 size(4);
5351 ins_encode( enc_lfd(dst, mem) );
5352 ins_pipe(pipe_class_memory);
5353 %}
5354
5355 // Load Double - aligned acquire.
5356 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5357 match(Set dst (LoadD mem));
5358 effect(TEMP cr0);
5359 ins_cost(3*MEMORY_REF_COST);
5360
5361 format %{ "LFD $dst, $mem \t// acquire\n\t"
5362 "FCMPU cr0, $dst, $dst\n\t"
5363 "BNE cr0, next\n"
5364 "next:\n\t"
5365 "ISYNC" %}
5366 size(16);
5367 ins_encode %{
5368 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5369 Label next;
5370 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5371 __ fcmpu(CR0, $dst$$FloatRegister, $dst$$FloatRegister);
5372 __ bne(CR0, next);
5373 __ bind(next);
5374 __ isync();
5375 %}
5376 ins_pipe(pipe_class_memory);
5377 %}
5378
5379 // Load Double - UNaligned
5380 instruct loadD_unaligned(regD dst, memory mem) %{
5381 match(Set dst (LoadD_unaligned mem));
5382 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5383 ins_cost(MEMORY_REF_COST);
5384
5385 format %{ "LFD $dst, $mem" %}
5386 size(4);
5387 ins_encode( enc_lfd(dst, mem) );
5388 ins_pipe(pipe_class_memory);
5389 %}
5390
5391 //----------Constants--------------------------------------------------------
5392
5393 // Load MachConstantTableBase: add hi offset to global toc.
5394 // TODO: Handle hidden register r29 in bundler!
5395 instruct loadToc_hi(iRegLdst dst) %{
5396 effect(DEF dst);
5397 ins_cost(DEFAULT_COST);
5398
5399 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5400 size(4);
5401 ins_encode %{
5402 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5403 %}
5404 ins_pipe(pipe_class_default);
5405 %}
5406
5407 // Load MachConstantTableBase: add lo offset to global toc.
5408 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5409 effect(DEF dst, USE src);
5410 ins_cost(DEFAULT_COST);
5411
5412 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5413 size(4);
5414 ins_encode %{
5415 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5416 %}
5417 ins_pipe(pipe_class_default);
5418 %}
5419
5420 // Load 16-bit integer constant 0xssss????
5421 instruct loadConI16(iRegIdst dst, immI16 src) %{
5422 match(Set dst src);
5423
5424 format %{ "LI $dst, $src" %}
5425 size(4);
5426 ins_encode %{
5427 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5428 %}
5429 ins_pipe(pipe_class_default);
5430 %}
5431
5432 // Load integer constant 0x????0000
5433 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5434 match(Set dst src);
5435 ins_cost(DEFAULT_COST);
5436
5437 format %{ "LIS $dst, $src.hi" %}
5438 size(4);
5439 ins_encode %{
5440 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5441 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5442 %}
5443 ins_pipe(pipe_class_default);
5444 %}
5445
5446 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5447 // and sign extended), this adds the low 16 bits.
5448 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5449 // no match-rule, false predicate
5450 effect(DEF dst, USE src1, USE src2);
5451 predicate(false);
5452
5453 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5454 size(4);
5455 ins_encode %{
5456 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5457 %}
5458 ins_pipe(pipe_class_default);
5459 %}
5460
5461 instruct loadConI32(iRegIdst dst, immI32 src) %{
5462 match(Set dst src);
5463 // This macro is valid only in Power 10 and up, but adding the following predicate here
5464 // caused a build error, so we comment it out for now.
5465 // predicate(PowerArchitecturePPC64 >= 10);
5466 ins_cost(DEFAULT_COST+1);
5467
5468 format %{ "PLI $dst, $src" %}
5469 size(8);
5470 ins_encode %{
5471 assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
5472 __ pli($dst$$Register, $src$$constant);
5473 %}
5474 ins_pipe(pipe_class_default);
5475 ins_alignment(2);
5476 %}
5477
5478 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5479 match(Set dst src);
5480 ins_cost(DEFAULT_COST*2);
5481
5482 expand %{
5483 // Would like to use $src$$constant.
5484 immI16 srcLo %{ _opnds[1]->constant() %}
5485 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5486 immIhi16 srcHi %{ _opnds[1]->constant() %}
5487 iRegIdst tmpI;
5488 loadConIhi16(tmpI, srcHi);
5489 loadConI32_lo16(dst, tmpI, srcLo);
5490 %}
5491 %}
5492
5493 // No constant pool entries required.
5494 instruct loadConL16(iRegLdst dst, immL16 src) %{
5495 match(Set dst src);
5496
5497 format %{ "LI $dst, $src \t// long" %}
5498 size(4);
5499 ins_encode %{
5500 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5501 %}
5502 ins_pipe(pipe_class_default);
5503 %}
5504
5505 // Load long constant 0xssssssss????0000
5506 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5507 match(Set dst src);
5508 ins_cost(DEFAULT_COST);
5509
5510 format %{ "LIS $dst, $src.hi \t// long" %}
5511 size(4);
5512 ins_encode %{
5513 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5514 %}
5515 ins_pipe(pipe_class_default);
5516 %}
5517
5518 // To load a 32 bit constant: merge lower 16 bits into already loaded
5519 // high 16 bits.
5520 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5521 // no match-rule, false predicate
5522 effect(DEF dst, USE src1, USE src2);
5523 predicate(false);
5524
5525 format %{ "ORI $dst, $src1, $src2.lo" %}
5526 size(4);
5527 ins_encode %{
5528 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5529 %}
5530 ins_pipe(pipe_class_default);
5531 %}
5532
5533 // Load 32-bit long constant
5534 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5535 match(Set dst src);
5536 ins_cost(DEFAULT_COST*2);
5537
5538 expand %{
5539 // Would like to use $src$$constant.
5540 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5541 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5542 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5543 iRegLdst tmpL;
5544 loadConL32hi16(tmpL, srcHi);
5545 loadConL32_lo16(dst, tmpL, srcLo);
5546 %}
5547 %}
5548
5549 // Load 34-bit long constant using prefixed addi. No constant pool entries required.
5550 instruct loadConL34(iRegLdst dst, immL34 src) %{
5551 match(Set dst src);
5552 // This macro is valid only in Power 10 and up, but adding the following predicate here
5553 // caused a build error, so we comment it out for now.
5554 // predicate(PowerArchitecturePPC64 >= 10);
5555 ins_cost(DEFAULT_COST+1);
5556
5557 format %{ "PLI $dst, $src \t// long" %}
5558 size(8);
5559 ins_encode %{
5560 assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
5561 __ pli($dst$$Register, $src$$constant);
5562 %}
5563 ins_pipe(pipe_class_default);
5564 ins_alignment(2);
5565 %}
5566
5567 // Load long constant 0x????000000000000.
5568 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5569 match(Set dst src);
5570 ins_cost(DEFAULT_COST);
5571
5572 expand %{
5573 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5574 immI shift32 %{ 32 %}
5575 iRegLdst tmpL;
5576 loadConL32hi16(tmpL, srcHi);
5577 lshiftL_regL_immI(dst, tmpL, shift32);
5578 %}
5579 %}
5580
5581 // Expand node for constant pool load: small offset.
5582 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5583 effect(DEF dst, USE src, USE toc);
5584 ins_cost(MEMORY_REF_COST);
5585
5586 ins_num_consts(1);
5587 // Needed so that CallDynamicJavaDirect can compute the address of this
5588 // instruction for relocation.
5589 ins_field_cbuf_insts_offset(int);
5590
5591 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5592 size(4);
5593 ins_encode( enc_load_long_constL(dst, src, toc) );
5594 ins_pipe(pipe_class_memory);
5595 %}
5596
5597 // Expand node for constant pool load: large offset.
5598 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5599 effect(DEF dst, USE src, USE toc);
5600 predicate(false);
5601
5602 ins_num_consts(1);
5603 ins_field_const_toc_offset(int);
5604 // Needed so that CallDynamicJavaDirect can compute the address of this
5605 // instruction for relocation.
5606 ins_field_cbuf_insts_offset(int);
5607
5608 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5609 size(4);
5610 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5611 ins_pipe(pipe_class_default);
5612 %}
5613
5614 // Expand node for constant pool load: large offset.
5615 // No constant pool entries required.
5616 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5617 effect(DEF dst, USE src, USE base);
5618 predicate(false);
5619
5620 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5621
5622 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5623 size(4);
5624 ins_encode %{
5625 int offset = ra_->C->output()->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5626 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5627 %}
5628 ins_pipe(pipe_class_memory);
5629 %}
5630
5631 // Load long constant from constant table. Expand in case of
5632 // offset > 16 bit is needed.
5633 // Adlc adds toc node MachConstantTableBase.
5634 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5635 match(Set dst src);
5636 ins_cost(MEMORY_REF_COST);
5637
5638 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5639 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5640 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5641 %}
5642
5643 // Load nullptr as compressed oop.
5644 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5645 match(Set dst src);
5646 ins_cost(DEFAULT_COST);
5647
5648 format %{ "LI $dst, $src \t// compressed ptr" %}
5649 size(4);
5650 ins_encode %{
5651 __ li($dst$$Register, 0);
5652 %}
5653 ins_pipe(pipe_class_default);
5654 %}
5655
5656 // Load hi part of compressed oop constant.
5657 instruct loadConN_hi(iRegNdst dst, immN src) %{
5658 effect(DEF dst, USE src);
5659 ins_cost(DEFAULT_COST);
5660
5661 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5662 size(4);
5663 ins_encode %{
5664 __ lis($dst$$Register, 0); // Will get patched.
5665 %}
5666 ins_pipe(pipe_class_default);
5667 %}
5668
5669 // Add lo part of compressed oop constant to already loaded hi part.
5670 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5671 effect(DEF dst, USE src1, USE src2);
5672 ins_cost(DEFAULT_COST);
5673
5674 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5675 size(4);
5676 ins_encode %{
5677 AddressLiteral addrlit = __ constant_oop_address((jobject)$src2$$constant);
5678 __ relocate(addrlit.rspec(), /*compressed format*/ 1);
5679 __ ori($dst$$Register, $src1$$Register, 0); // Will get patched.
5680 %}
5681 ins_pipe(pipe_class_default);
5682 %}
5683
5684 instruct rldicl(iRegLdst dst, iRegLsrc src, immI16 shift, immI16 mask_begin) %{
5685 effect(DEF dst, USE src, USE shift, USE mask_begin);
5686
5687 size(4);
5688 ins_encode %{
5689 __ rldicl($dst$$Register, $src$$Register, $shift$$constant, $mask_begin$$constant);
5690 %}
5691 ins_pipe(pipe_class_default);
5692 %}
5693
5694 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5695 // leaving the upper 32 bits with sign-extension bits.
5696 // This clears these bits: dst = src & 0xFFFFFFFF.
5697 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5698 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5699 effect(DEF dst, USE src);
5700 predicate(false);
5701
5702 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5703 size(4);
5704 ins_encode %{
5705 __ clrldi($dst$$Register, $src$$Register, 0x20);
5706 %}
5707 ins_pipe(pipe_class_default);
5708 %}
5709
5710 // Optimize DecodeN for disjoint base.
5711 // Load base of compressed oops into a register
5712 instruct loadBase(iRegLdst dst) %{
5713 effect(DEF dst);
5714
5715 format %{ "LoadConst $dst, heapbase" %}
5716 ins_encode %{
5717 __ load_const_optimized($dst$$Register, CompressedOops::base(), R0);
5718 %}
5719 ins_pipe(pipe_class_default);
5720 %}
5721
5722 // Loading ConN must be postalloc expanded so that edges between
5723 // the nodes are safe. They may not interfere with a safepoint.
5724 // GL TODO: This needs three instructions: better put this into the constant pool.
5725 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5726 match(Set dst src);
5727 ins_cost(DEFAULT_COST*2);
5728
5729 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
5730 postalloc_expand %{
5731 MachNode *m1 = new loadConN_hiNode();
5732 MachNode *m2 = new loadConN_loNode();
5733 MachNode *m3 = new clearMs32bNode();
5734 m1->_bottom_type = bottom_type();
5735 m2->_bottom_type = bottom_type();
5736 m3->_bottom_type = bottom_type();
5737 m1->add_req(nullptr);
5738 m2->add_req(nullptr, m1);
5739 m3->add_req(nullptr, m2);
5740 m1->_opnds[0] = op_dst;
5741 m1->_opnds[1] = op_src;
5742 m2->_opnds[0] = op_dst;
5743 m2->_opnds[1] = op_dst;
5744 m2->_opnds[2] = op_src;
5745 m3->_opnds[0] = op_dst;
5746 m3->_opnds[1] = op_dst;
5747 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5748 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5749 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5750 nodes->push(m1);
5751 nodes->push(m2);
5752 nodes->push(m3);
5753 %}
5754 %}
5755
5756 // We have seen a safepoint between the hi and lo parts, and this node was handled
5757 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
5758 // not a narrow oop.
5759 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
5760 match(Set dst src);
5761 effect(DEF dst, USE src);
5762 ins_cost(DEFAULT_COST);
5763
5764 format %{ "LIS $dst, $src \t// narrow klass hi" %}
5765 size(4);
5766 ins_encode %{
5767 intptr_t Csrc = CompressedKlassPointers::encode((Klass *)$src$$constant);
5768 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
5769 %}
5770 ins_pipe(pipe_class_default);
5771 %}
5772
5773 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
5774 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
5775 match(Set dst src1);
5776 effect(TEMP src2);
5777 ins_cost(DEFAULT_COST);
5778
5779 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
5780 size(4);
5781 ins_encode %{
5782 __ clrldi($dst$$Register, $src2$$Register, 0x20);
5783 %}
5784 ins_pipe(pipe_class_default);
5785 %}
5786
5787 // This needs a match rule so that build_oop_map knows this is
5788 // not a narrow oop.
5789 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
5790 match(Set dst src1);
5791 effect(TEMP src2);
5792 ins_cost(DEFAULT_COST);
5793
5794 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
5795 size(4);
5796 ins_encode %{
5797 // Notify OOP recorder (don't need the relocation)
5798 AddressLiteral md = __ constant_metadata_address((Klass*)$src1$$constant);
5799 intptr_t Csrc = CompressedKlassPointers::encode((Klass*)md.value());
5800 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
5801 %}
5802 ins_pipe(pipe_class_default);
5803 %}
5804
5805 // Loading ConNKlass must be postalloc expanded so that edges between
5806 // the nodes are safe. They may not interfere with a safepoint.
5807 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
5808 match(Set dst src);
5809 ins_cost(DEFAULT_COST*2);
5810
5811 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
5812 postalloc_expand %{
5813 // Load high bits into register. Sign extended.
5814 MachNode *m1 = new loadConNKlass_hiNode();
5815 m1->_bottom_type = bottom_type();
5816 m1->add_req(nullptr);
5817 m1->_opnds[0] = op_dst;
5818 m1->_opnds[1] = op_src;
5819 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5820 nodes->push(m1);
5821
5822 MachNode *m2 = m1;
5823 if (!Assembler::is_uimm((jlong)CompressedKlassPointers::encode((Klass *)op_src->constant()), 31)) {
5824 // Value might be 1-extended. Mask out these bits.
5825 m2 = new loadConNKlass_maskNode();
5826 m2->_bottom_type = bottom_type();
5827 m2->add_req(nullptr, m1);
5828 m2->_opnds[0] = op_dst;
5829 m2->_opnds[1] = op_src;
5830 m2->_opnds[2] = op_dst;
5831 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5832 nodes->push(m2);
5833 }
5834
5835 MachNode *m3 = new loadConNKlass_loNode();
5836 m3->_bottom_type = bottom_type();
5837 m3->add_req(nullptr, m2);
5838 m3->_opnds[0] = op_dst;
5839 m3->_opnds[1] = op_src;
5840 m3->_opnds[2] = op_dst;
5841 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5842 nodes->push(m3);
5843 %}
5844 %}
5845
5846 // 0x1 is used in object initialization (initial object header).
5847 // No constant pool entries required.
5848 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
5849 match(Set dst src);
5850
5851 format %{ "LI $dst, $src \t// ptr" %}
5852 size(4);
5853 ins_encode %{
5854 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5855 %}
5856 ins_pipe(pipe_class_default);
5857 %}
5858
5859 // Expand node for constant pool load: small offset.
5860 // The match rule is needed to generate the correct bottom_type(),
5861 // however this node should never match. The use of predicate is not
5862 // possible since ADLC forbids predicates for chain rules. The higher
5863 // costs do not prevent matching in this case. For that reason the
5864 // operand immP_NM with predicate(false) is used.
5865 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
5866 match(Set dst src);
5867 effect(TEMP toc);
5868
5869 ins_num_consts(1);
5870
5871 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
5872 size(4);
5873 ins_encode( enc_load_long_constP(dst, src, toc) );
5874 ins_pipe(pipe_class_memory);
5875 %}
5876
5877 // Expand node for constant pool load: large offset.
5878 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
5879 effect(DEF dst, USE src, USE toc);
5880 predicate(false);
5881
5882 ins_num_consts(1);
5883 ins_field_const_toc_offset(int);
5884
5885 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
5886 size(4);
5887 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
5888 ins_pipe(pipe_class_default);
5889 %}
5890
5891 // Expand node for constant pool load: large offset.
5892 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
5893 match(Set dst src);
5894 effect(TEMP base);
5895
5896 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
5897
5898 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
5899 size(4);
5900 ins_encode %{
5901 int offset = ra_->C->output()->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5902 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5903 %}
5904 ins_pipe(pipe_class_memory);
5905 %}
5906
5907 // Load pointer constant from constant table. Expand in case an
5908 // offset > 16 bit is needed.
5909 // Adlc adds toc node MachConstantTableBase.
5910 instruct loadConP_Ex(iRegPdst dst, immP src) %{
5911 match(Set dst src);
5912 ins_cost(MEMORY_REF_COST);
5913
5914 // This rule does not use "expand" because then
5915 // the result type is not known to be an Oop. An ADLC
5916 // enhancement will be needed to make that work - not worth it!
5917
5918 // If this instruction rematerializes, it prolongs the live range
5919 // of the toc node, causing illegal graphs.
5920 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
5921 ins_cannot_rematerialize(true);
5922
5923 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
5924 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
5925 %}
5926
5927 // Expand node for constant pool load: small offset.
5928 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
5929 effect(DEF dst, USE src, USE toc);
5930 ins_cost(MEMORY_REF_COST);
5931
5932 ins_num_consts(1);
5933
5934 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
5935 size(4);
5936 ins_encode %{
5937 address float_address = __ float_constant($src$$constant);
5938 if (float_address == nullptr) {
5939 ciEnv::current()->record_out_of_memory_failure();
5940 return;
5941 }
5942 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
5943 %}
5944 ins_pipe(pipe_class_memory);
5945 %}
5946
5947 // Expand node for constant pool load: large offset.
5948 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
5949 effect(DEF dst, USE src, USE toc);
5950 ins_cost(MEMORY_REF_COST);
5951
5952 ins_num_consts(1);
5953
5954 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
5955 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
5956 "ADDIS $toc, $toc, -offset_hi"%}
5957 size(12);
5958 ins_encode %{
5959 FloatRegister Rdst = $dst$$FloatRegister;
5960 Register Rtoc = $toc$$Register;
5961 address float_address = __ float_constant($src$$constant);
5962 if (float_address == nullptr) {
5963 ciEnv::current()->record_out_of_memory_failure();
5964 return;
5965 }
5966 int offset = __ offset_to_method_toc(float_address);
5967 int hi = (offset + (1<<15))>>16;
5968 int lo = offset - hi * (1<<16);
5969
5970 __ addis(Rtoc, Rtoc, hi);
5971 __ lfs(Rdst, lo, Rtoc);
5972 __ addis(Rtoc, Rtoc, -hi);
5973 %}
5974 ins_pipe(pipe_class_memory);
5975 %}
5976
5977 // Adlc adds toc node MachConstantTableBase.
5978 instruct loadConF_Ex(regF dst, immF src) %{
5979 match(Set dst src);
5980 ins_cost(MEMORY_REF_COST);
5981
5982 // See loadConP.
5983 ins_cannot_rematerialize(true);
5984
5985 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
5986 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
5987 %}
5988
5989 // Expand node for constant pool load: small offset.
5990 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
5991 effect(DEF dst, USE src, USE toc);
5992 ins_cost(MEMORY_REF_COST);
5993
5994 ins_num_consts(1);
5995
5996 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
5997 size(4);
5998 ins_encode %{
5999 address float_address = __ double_constant($src$$constant);
6000 if (float_address == nullptr) {
6001 ciEnv::current()->record_out_of_memory_failure();
6002 return;
6003 }
6004 int offset = __ offset_to_method_toc(float_address);
6005 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6006 %}
6007 ins_pipe(pipe_class_memory);
6008 %}
6009
6010 // Expand node for constant pool load: large offset.
6011 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6012 effect(DEF dst, USE src, USE toc);
6013 ins_cost(MEMORY_REF_COST);
6014
6015 ins_num_consts(1);
6016
6017 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6018 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6019 "ADDIS $toc, $toc, -offset_hi" %}
6020 size(12);
6021 ins_encode %{
6022 FloatRegister Rdst = $dst$$FloatRegister;
6023 Register Rtoc = $toc$$Register;
6024 address float_address = __ double_constant($src$$constant);
6025 if (float_address == nullptr) {
6026 ciEnv::current()->record_out_of_memory_failure();
6027 return;
6028 }
6029 int offset = __ offset_to_method_toc(float_address);
6030 int hi = (offset + (1<<15))>>16;
6031 int lo = offset - hi * (1<<16);
6032
6033 __ addis(Rtoc, Rtoc, hi);
6034 __ lfd(Rdst, lo, Rtoc);
6035 __ addis(Rtoc, Rtoc, -hi);
6036 %}
6037 ins_pipe(pipe_class_memory);
6038 %}
6039
6040 // Adlc adds toc node MachConstantTableBase.
6041 instruct loadConD_Ex(regD dst, immD src) %{
6042 match(Set dst src);
6043 ins_cost(MEMORY_REF_COST);
6044
6045 // See loadConP.
6046 ins_cannot_rematerialize(true);
6047
6048 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6049 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6050 %}
6051
6052 // Prefetch instructions.
6053 // Must be safe to execute with invalid address (cannot fault).
6054
6055 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6056 match(PrefetchAllocation (AddP mem src));
6057 ins_cost(MEMORY_REF_COST);
6058
6059 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6060 size(4);
6061 ins_encode %{
6062 __ dcbtst($src$$Register, $mem$$base$$Register);
6063 %}
6064 ins_pipe(pipe_class_memory);
6065 %}
6066
6067 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6068 match(PrefetchAllocation mem);
6069 ins_cost(MEMORY_REF_COST);
6070
6071 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6072 size(4);
6073 ins_encode %{
6074 __ dcbtst($mem$$base$$Register);
6075 %}
6076 ins_pipe(pipe_class_memory);
6077 %}
6078
6079 //----------Store Instructions-------------------------------------------------
6080
6081 // Store Byte
6082 instruct storeB(memory mem, iRegIsrc src) %{
6083 match(Set mem (StoreB mem src));
6084 ins_cost(MEMORY_REF_COST);
6085
6086 format %{ "STB $src, $mem \t// byte" %}
6087 size(4);
6088 ins_encode %{
6089 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6090 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6091 %}
6092 ins_pipe(pipe_class_memory);
6093 %}
6094
6095 // Store Char/Short
6096 instruct storeC(memory mem, iRegIsrc src) %{
6097 match(Set mem (StoreC mem src));
6098 ins_cost(MEMORY_REF_COST);
6099
6100 format %{ "STH $src, $mem \t// short" %}
6101 size(4);
6102 ins_encode %{
6103 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6104 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6105 %}
6106 ins_pipe(pipe_class_memory);
6107 %}
6108
6109 // Store Integer
6110 instruct storeI(memory mem, iRegIsrc src) %{
6111 match(Set mem (StoreI mem src));
6112 ins_cost(MEMORY_REF_COST);
6113
6114 format %{ "STW $src, $mem" %}
6115 size(4);
6116 ins_encode( enc_stw(src, mem) );
6117 ins_pipe(pipe_class_memory);
6118 %}
6119
6120 // ConvL2I + StoreI.
6121 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6122 match(Set mem (StoreI mem (ConvL2I src)));
6123 ins_cost(MEMORY_REF_COST);
6124
6125 format %{ "STW l2i($src), $mem" %}
6126 size(4);
6127 ins_encode( enc_stw(src, mem) );
6128 ins_pipe(pipe_class_memory);
6129 %}
6130
6131 // Store Long
6132 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6133 match(Set mem (StoreL mem src));
6134 ins_cost(MEMORY_REF_COST);
6135
6136 format %{ "STD $src, $mem \t// long" %}
6137 size(4);
6138 ins_encode( enc_std(src, mem) );
6139 ins_pipe(pipe_class_memory);
6140 %}
6141
6142 // Store super word nodes.
6143
6144 // Store Aligned Packed Byte long register to memory
6145 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6146 predicate(n->as_StoreVector()->memory_size() == 8);
6147 match(Set mem (StoreVector mem src));
6148 ins_cost(MEMORY_REF_COST);
6149
6150 format %{ "STD $mem, $src \t// packed8B" %}
6151 size(4);
6152 ins_encode( enc_std(src, mem) );
6153 ins_pipe(pipe_class_memory);
6154 %}
6155
6156
6157 instruct storeV16(memoryAlg16 mem, vecX src) %{
6158 predicate(n->as_StoreVector()->memory_size() == 16);
6159 match(Set mem (StoreVector mem src));
6160 ins_cost(MEMORY_REF_COST);
6161
6162 format %{ "STXV $mem, $src \t// store 16-byte Vector" %}
6163 size(4);
6164 ins_encode %{
6165 __ stxv($src$$VectorRegister.to_vsr(), $mem$$disp, $mem$$Register);
6166 %}
6167 ins_pipe(pipe_class_default);
6168 %}
6169
6170 // Reinterpret: only one vector size used: either L or X
6171 instruct reinterpretL(iRegLdst dst) %{
6172 match(Set dst (VectorReinterpret dst));
6173 ins_cost(0);
6174 format %{ "reinterpret $dst" %}
6175 size(0);
6176 ins_encode( /*empty*/ );
6177 ins_pipe(pipe_class_empty);
6178 %}
6179
6180 instruct reinterpretX(vecX dst) %{
6181 match(Set dst (VectorReinterpret dst));
6182 ins_cost(0);
6183 format %{ "reinterpret $dst" %}
6184 size(0);
6185 ins_encode( /*empty*/ );
6186 ins_pipe(pipe_class_empty);
6187 %}
6188
6189 // Store Compressed Oop
6190 instruct storeN(memory dst, iRegN_P2N src) %{
6191 match(Set dst (StoreN dst src));
6192 predicate(n->as_Store()->barrier_data() == 0);
6193 ins_cost(MEMORY_REF_COST);
6194
6195 format %{ "STW $src, $dst \t// compressed oop" %}
6196 size(4);
6197 ins_encode( enc_stw(src, dst) );
6198 ins_pipe(pipe_class_memory);
6199 %}
6200
6201 // Store Compressed KLass
6202 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6203 match(Set dst (StoreNKlass dst src));
6204 ins_cost(MEMORY_REF_COST);
6205
6206 format %{ "STW $src, $dst \t// compressed klass" %}
6207 size(4);
6208 ins_encode( enc_stw(src, dst) );
6209 ins_pipe(pipe_class_memory);
6210 %}
6211
6212 // Store Pointer
6213 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6214 match(Set dst (StoreP dst src));
6215 predicate(n->as_Store()->barrier_data() == 0);
6216 ins_cost(MEMORY_REF_COST);
6217
6218 format %{ "STD $src, $dst \t// ptr" %}
6219 size(4);
6220 ins_encode( enc_std(src, dst) );
6221 ins_pipe(pipe_class_memory);
6222 %}
6223
6224 // Store Float
6225 instruct storeF(memory mem, regF src) %{
6226 match(Set mem (StoreF mem src));
6227 ins_cost(MEMORY_REF_COST);
6228
6229 format %{ "STFS $src, $mem" %}
6230 size(4);
6231 ins_encode( enc_stfs(src, mem) );
6232 ins_pipe(pipe_class_memory);
6233 %}
6234
6235 // Store Double
6236 instruct storeD(memory mem, regD src) %{
6237 match(Set mem (StoreD mem src));
6238 ins_cost(MEMORY_REF_COST);
6239
6240 format %{ "STFD $src, $mem" %}
6241 size(4);
6242 ins_encode( enc_stfd(src, mem) );
6243 ins_pipe(pipe_class_memory);
6244 %}
6245
6246 // Convert oop pointer into compressed form.
6247
6248 // Nodes for postalloc expand.
6249
6250 // Shift node for expand.
6251 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6252 // The match rule is needed to make it a 'MachTypeNode'!
6253 match(Set dst (EncodeP src));
6254 predicate(false);
6255
6256 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6257 size(4);
6258 ins_encode %{
6259 __ srdi($dst$$Register, $src$$Register, CompressedOops::shift() & 0x3f);
6260 %}
6261 ins_pipe(pipe_class_default);
6262 %}
6263
6264 // Add node for expand.
6265 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6266 // The match rule is needed to make it a 'MachTypeNode'!
6267 match(Set dst (EncodeP src));
6268 predicate(false);
6269
6270 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6271 ins_encode %{
6272 __ sub_const_optimized($dst$$Register, $src$$Register, CompressedOops::base(), R0);
6273 %}
6274 ins_pipe(pipe_class_default);
6275 %}
6276
6277 // Conditional sub base.
6278 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6279 // The match rule is needed to make it a 'MachTypeNode'!
6280 match(Set dst (EncodeP (Binary crx src1)));
6281 predicate(false);
6282
6283 format %{ "BEQ $crx, done\n\t"
6284 "SUB $dst, $src1, heapbase \t// encode: subtract base if != nullptr\n"
6285 "done:" %}
6286 ins_encode %{
6287 Label done;
6288 __ beq($crx$$CondRegister, done);
6289 __ sub_const_optimized($dst$$Register, $src1$$Register, CompressedOops::base(), R0);
6290 __ bind(done);
6291 %}
6292 ins_pipe(pipe_class_default);
6293 %}
6294
6295 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6296 // The match rule is needed to make it a 'MachTypeNode'!
6297 match(Set dst (EncodeP (Binary crx src1)));
6298 predicate(false);
6299
6300 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6301 size(4);
6302 ins_encode %{
6303 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6304 %}
6305 ins_pipe(pipe_class_default);
6306 %}
6307
6308 // Disjoint narrow oop base.
6309 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6310 match(Set dst (EncodeP src));
6311 predicate(CompressedOops::base_disjoint());
6312
6313 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6314 size(4);
6315 ins_encode %{
6316 __ rldicl($dst$$Register, $src$$Register, 64-CompressedOops::shift(), 32);
6317 %}
6318 ins_pipe(pipe_class_default);
6319 %}
6320
6321 // shift != 0, base != 0
6322 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6323 match(Set dst (EncodeP src));
6324 effect(TEMP crx);
6325 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6326 CompressedOops::shift() != 0 &&
6327 CompressedOops::base_overlaps());
6328
6329 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6330 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6331 %}
6332
6333 // shift != 0, base != 0
6334 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6335 match(Set dst (EncodeP src));
6336 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6337 CompressedOops::shift() != 0 &&
6338 CompressedOops::base_overlaps());
6339
6340 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6341 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6342 %}
6343
6344 // shift != 0, base == 0
6345 // TODO: This is the same as encodeP_shift. Merge!
6346 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6347 match(Set dst (EncodeP src));
6348 predicate(CompressedOops::shift() != 0 &&
6349 CompressedOops::base() == nullptr);
6350
6351 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != nullptr" %}
6352 size(4);
6353 ins_encode %{
6354 __ srdi($dst$$Register, $src$$Register, CompressedOops::shift() & 0x3f);
6355 %}
6356 ins_pipe(pipe_class_default);
6357 %}
6358
6359 // Compressed OOPs with narrow_oop_shift == 0.
6360 // shift == 0, base == 0
6361 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6362 match(Set dst (EncodeP src));
6363 predicate(CompressedOops::shift() == 0);
6364
6365 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6366 // variable size, 0 or 4.
6367 ins_encode %{
6368 __ mr_if_needed($dst$$Register, $src$$Register);
6369 %}
6370 ins_pipe(pipe_class_default);
6371 %}
6372
6373 // Decode nodes.
6374
6375 // Shift node for expand.
6376 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6377 // The match rule is needed to make it a 'MachTypeNode'!
6378 match(Set dst (DecodeN src));
6379 predicate(false);
6380
6381 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6382 size(4);
6383 ins_encode %{
6384 __ sldi($dst$$Register, $src$$Register, CompressedOops::shift());
6385 %}
6386 ins_pipe(pipe_class_default);
6387 %}
6388
6389 // Add node for expand.
6390 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6391 // The match rule is needed to make it a 'MachTypeNode'!
6392 match(Set dst (DecodeN src));
6393 predicate(false);
6394
6395 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %}
6396 ins_encode %{
6397 __ add_const_optimized($dst$$Register, $src$$Register, CompressedOops::base(), R0);
6398 %}
6399 ins_pipe(pipe_class_default);
6400 %}
6401
6402 // conditianal add base for expand
6403 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6404 // The match rule is needed to make it a 'MachTypeNode'!
6405 // NOTICE that the rule is nonsense - we just have to make sure that:
6406 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6407 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6408 match(Set dst (DecodeN (Binary crx src)));
6409 predicate(false);
6410
6411 format %{ "BEQ $crx, done\n\t"
6412 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != nullptr\n"
6413 "done:" %}
6414 ins_encode %{
6415 Label done;
6416 __ beq($crx$$CondRegister, done);
6417 __ add_const_optimized($dst$$Register, $src$$Register, CompressedOops::base(), R0);
6418 __ bind(done);
6419 %}
6420 ins_pipe(pipe_class_default);
6421 %}
6422
6423 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6424 // The match rule is needed to make it a 'MachTypeNode'!
6425 // NOTICE that the rule is nonsense - we just have to make sure that:
6426 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6427 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6428 match(Set dst (DecodeN (Binary crx src1)));
6429 predicate(false);
6430
6431 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6432 size(4);
6433 ins_encode %{
6434 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6435 %}
6436 ins_pipe(pipe_class_default);
6437 %}
6438
6439 // shift != 0, base != 0
6440 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6441 match(Set dst (DecodeN src));
6442 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6443 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6444 CompressedOops::shift() != 0 &&
6445 CompressedOops::base() != nullptr);
6446 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6447 effect(TEMP crx);
6448
6449 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6450 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6451 %}
6452
6453 // shift != 0, base == 0
6454 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6455 match(Set dst (DecodeN src));
6456 predicate(CompressedOops::shift() != 0 &&
6457 CompressedOops::base() == nullptr);
6458
6459 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6460 size(4);
6461 ins_encode %{
6462 __ sldi($dst$$Register, $src$$Register, CompressedOops::shift());
6463 %}
6464 ins_pipe(pipe_class_default);
6465 %}
6466
6467 // Optimize DecodeN for disjoint base.
6468 // Shift narrow oop and or it into register that already contains the heap base.
6469 // Base == dst must hold, and is assured by construction in postaloc_expand.
6470 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6471 match(Set dst (DecodeN src));
6472 effect(TEMP base);
6473 predicate(false);
6474
6475 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6476 size(4);
6477 ins_encode %{
6478 __ rldimi($dst$$Register, $src$$Register, CompressedOops::shift(), 32-CompressedOops::shift());
6479 %}
6480 ins_pipe(pipe_class_default);
6481 %}
6482
6483 // Optimize DecodeN for disjoint base.
6484 // This node requires only one cycle on the critical path.
6485 // We must postalloc_expand as we can not express use_def effects where
6486 // the used register is L and the def'ed register P.
6487 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6488 match(Set dst (DecodeN src));
6489 effect(TEMP_DEF dst);
6490 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6491 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6492 CompressedOops::base_disjoint());
6493 ins_cost(DEFAULT_COST);
6494
6495 format %{ "MOV $dst, heapbase \t\n"
6496 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6497 postalloc_expand %{
6498 loadBaseNode *n1 = new loadBaseNode();
6499 n1->add_req(nullptr);
6500 n1->_opnds[0] = op_dst;
6501
6502 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6503 n2->add_req(n_region, n_src, n1);
6504 n2->_opnds[0] = op_dst;
6505 n2->_opnds[1] = op_src;
6506 n2->_opnds[2] = op_dst;
6507 n2->_bottom_type = _bottom_type;
6508
6509 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6510 ra_->set_oop(n2, true);
6511
6512 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6513 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6514
6515 nodes->push(n1);
6516 nodes->push(n2);
6517 %}
6518 %}
6519
6520 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6521 match(Set dst (DecodeN src));
6522 effect(TEMP_DEF dst, TEMP crx);
6523 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6524 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6525 CompressedOops::base_disjoint());
6526 ins_cost(3 * DEFAULT_COST);
6527
6528 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6529 postalloc_expand %{
6530 loadBaseNode *n1 = new loadBaseNode();
6531 n1->add_req(nullptr);
6532 n1->_opnds[0] = op_dst;
6533
6534 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6535 n_compare->add_req(n_region, n_src);
6536 n_compare->_opnds[0] = op_crx;
6537 n_compare->_opnds[1] = op_src;
6538 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6539
6540 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6541 n2->add_req(n_region, n_src, n1);
6542 n2->_opnds[0] = op_dst;
6543 n2->_opnds[1] = op_src;
6544 n2->_opnds[2] = op_dst;
6545 n2->_bottom_type = _bottom_type;
6546
6547 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6548 n_cond_set->add_req(n_region, n_compare, n2);
6549 n_cond_set->_opnds[0] = op_dst;
6550 n_cond_set->_opnds[1] = op_crx;
6551 n_cond_set->_opnds[2] = op_dst;
6552 n_cond_set->_bottom_type = _bottom_type;
6553
6554 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6555 ra_->set_oop(n_cond_set, true);
6556
6557 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6558 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6559 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6560 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6561
6562 nodes->push(n1);
6563 nodes->push(n_compare);
6564 nodes->push(n2);
6565 nodes->push(n_cond_set);
6566 %}
6567 %}
6568
6569 // src != 0, shift != 0, base != 0
6570 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6571 match(Set dst (DecodeN src));
6572 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6573 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6574 CompressedOops::shift() != 0 &&
6575 CompressedOops::base() != nullptr);
6576 ins_cost(2 * DEFAULT_COST);
6577
6578 format %{ "DecodeN $dst, $src \t// $src != nullptr, postalloc expanded" %}
6579 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6580 %}
6581
6582 // Compressed OOPs with narrow_oop_shift == 0.
6583 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6584 match(Set dst (DecodeN src));
6585 predicate(CompressedOops::shift() == 0);
6586 ins_cost(DEFAULT_COST);
6587
6588 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6589 // variable size, 0 or 4.
6590 ins_encode %{
6591 __ mr_if_needed($dst$$Register, $src$$Register);
6592 %}
6593 ins_pipe(pipe_class_default);
6594 %}
6595
6596 // Convert compressed oop into int for vectors alignment masking.
6597 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6598 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6599 predicate(CompressedOops::shift() == 0);
6600 ins_cost(DEFAULT_COST);
6601
6602 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6603 // variable size, 0 or 4.
6604 ins_encode %{
6605 __ mr_if_needed($dst$$Register, $src$$Register);
6606 %}
6607 ins_pipe(pipe_class_default);
6608 %}
6609
6610 // Convert klass pointer into compressed form.
6611
6612 // Disjoint narrow oop base.
6613 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
6614 match(Set dst (EncodePKlass src));
6615 predicate(false /* TODO: PPC port CompressedKlassPointers::base_disjoint()*/);
6616
6617 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6618 size(4);
6619 ins_encode %{
6620 __ rldicl($dst$$Register, $src$$Register, 64-CompressedKlassPointers::shift(), 32);
6621 %}
6622 ins_pipe(pipe_class_default);
6623 %}
6624
6625 // shift != 0, base != 0
6626 instruct encodePKlass_not_null(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6627 match(Set dst (EncodePKlass (Binary base src)));
6628 predicate(false);
6629
6630 format %{ "EncodePKlass $dst = ($src - $base) >> 3\t// $src != nullptr" %}
6631 size(8);
6632 ins_encode %{
6633 __ subf($dst$$Register, $base$$Register, $src$$Register);
6634 __ srdi($dst$$Register, $dst$$Register, CompressedKlassPointers::shift());
6635 %}
6636 ins_pipe(pipe_class_default);
6637 %}
6638
6639 // shift != 0, base != 0
6640 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6641 match(Set dst (EncodePKlass src));
6642 //predicate(CompressedKlassPointers::shift() != 0 &&
6643 // true /* TODO: PPC port CompressedKlassPointers::base_overlaps()*/);
6644
6645 ins_cost(DEFAULT_COST*2); // Don't count constant.
6646 expand %{
6647 immL baseImm %{ (jlong)(intptr_t)CompressedKlassPointers::base() %}
6648 iRegLdst base;
6649 loadConL_Ex(base, baseImm);
6650 encodePKlass_not_null(dst, base, src);
6651 %}
6652 %}
6653
6654 // Decode nodes.
6655
6656 // src != 0, shift != 0, base != 0
6657 instruct decodeNKlass_notNull(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
6658 match(Set dst (DecodeNKlass (Binary base src)));
6659 predicate(false);
6660
6661 format %{ "DecodeNKlass $dst = ($base + $src) << 3\t// $src != nullptr, base pre-shifted" %}
6662 size(8);
6663 ins_encode %{
6664 __ add($dst$$Register, $base$$Register, $src$$Register);
6665 __ sldi($dst$$Register, $dst$$Register, CompressedKlassPointers::shift());
6666 %}
6667 ins_pipe(pipe_class_default);
6668 %}
6669
6670 // src != 0, shift != 0, base != 0
6671 instruct decodeNKlass_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6672 match(Set dst (DecodeNKlass src));
6673 // predicate(CompressedKlassPointers::shift() != 0 &&
6674 // CompressedKlassPointers::base() != 0);
6675
6676 ins_cost(DEFAULT_COST*2); // Don't count constant.
6677 expand %{
6678 // We add first, then we shift. Like this, we can get along with one register less.
6679 // But we have to load the base pre-shifted.
6680 immL baseImm %{ (jlong)((intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift()) %}
6681 iRegLdst base;
6682 loadConL_Ex(base, baseImm);
6683 decodeNKlass_notNull(dst, base, src);
6684 %}
6685 %}
6686
6687 //----------MemBar Instructions-----------------------------------------------
6688 // Memory barrier flavors
6689
6690 instruct membar_acquire() %{
6691 match(LoadFence);
6692 ins_cost(4*MEMORY_REF_COST);
6693
6694 format %{ "MEMBAR-acquire" %}
6695 size(4);
6696 ins_encode %{
6697 __ acquire();
6698 %}
6699 ins_pipe(pipe_class_default);
6700 %}
6701
6702 instruct unnecessary_membar_acquire() %{
6703 match(MemBarAcquire);
6704 ins_cost(0);
6705
6706 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
6707 size(0);
6708 ins_encode( /*empty*/ );
6709 ins_pipe(pipe_class_default);
6710 %}
6711
6712 instruct membar_acquire_lock() %{
6713 match(MemBarAcquireLock);
6714 ins_cost(0);
6715
6716 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
6717 size(0);
6718 ins_encode( /*empty*/ );
6719 ins_pipe(pipe_class_default);
6720 %}
6721
6722 instruct membar_release() %{
6723 match(MemBarRelease);
6724 match(StoreFence);
6725 ins_cost(4*MEMORY_REF_COST);
6726
6727 format %{ "MEMBAR-release" %}
6728 size(4);
6729 ins_encode %{
6730 __ release();
6731 %}
6732 ins_pipe(pipe_class_default);
6733 %}
6734
6735 instruct membar_storestore() %{
6736 match(MemBarStoreStore);
6737 match(StoreStoreFence);
6738 ins_cost(4*MEMORY_REF_COST);
6739
6740 format %{ "MEMBAR-store-store" %}
6741 size(4);
6742 ins_encode %{
6743 __ membar(Assembler::StoreStore);
6744 %}
6745 ins_pipe(pipe_class_default);
6746 %}
6747
6748 instruct membar_release_lock() %{
6749 match(MemBarReleaseLock);
6750 ins_cost(0);
6751
6752 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
6753 size(0);
6754 ins_encode( /*empty*/ );
6755 ins_pipe(pipe_class_default);
6756 %}
6757
6758 instruct membar_storeload() %{
6759 match(MemBarStoreLoad);
6760 ins_cost(4*MEMORY_REF_COST);
6761
6762 format %{ "MEMBAR-store-load" %}
6763 size(4);
6764 ins_encode %{
6765 __ fence();
6766 %}
6767 ins_pipe(pipe_class_default);
6768 %}
6769
6770 instruct membar_volatile() %{
6771 match(MemBarVolatile);
6772 ins_cost(4*MEMORY_REF_COST);
6773
6774 format %{ "MEMBAR-volatile" %}
6775 size(4);
6776 ins_encode %{
6777 __ fence();
6778 %}
6779 ins_pipe(pipe_class_default);
6780 %}
6781
6782 // This optimization is wrong on PPC. The following pattern is not supported:
6783 // MemBarVolatile
6784 // ^ ^
6785 // | |
6786 // CtrlProj MemProj
6787 // ^ ^
6788 // | |
6789 // | Load
6790 // |
6791 // MemBarVolatile
6792 //
6793 // The first MemBarVolatile could get optimized out! According to
6794 // Vladimir, this pattern can not occur on Oracle platforms.
6795 // However, it does occur on PPC64 (because of membars in
6796 // inline_unsafe_load_store).
6797 //
6798 // Add this node again if we found a good solution for inline_unsafe_load_store().
6799 // Don't forget to look at the implementation of post_store_load_barrier again,
6800 // we did other fixes in that method.
6801 //instruct unnecessary_membar_volatile() %{
6802 // match(MemBarVolatile);
6803 // predicate(Matcher::post_store_load_barrier(n));
6804 // ins_cost(0);
6805 //
6806 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
6807 // size(0);
6808 // ins_encode( /*empty*/ );
6809 // ins_pipe(pipe_class_default);
6810 //%}
6811
6812 instruct membar_full() %{
6813 match(MemBarFull);
6814 ins_cost(4*MEMORY_REF_COST);
6815
6816 format %{ "MEMBAR-full" %}
6817 size(4);
6818 ins_encode %{
6819 __ fence();
6820 %}
6821 ins_pipe(pipe_class_default);
6822 %}
6823
6824 instruct membar_CPUOrder() %{
6825 match(MemBarCPUOrder);
6826 ins_cost(0);
6827
6828 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
6829 size(0);
6830 ins_encode( /*empty*/ );
6831 ins_pipe(pipe_class_default);
6832 %}
6833
6834 instruct onspinwait() %{
6835 match(OnSpinWait);
6836 ins_cost(DEFAULT_COST);
6837
6838 format %{ "OnSpinWait (smt_prio_low ; smt_prio_medium)" %}
6839 size(8);
6840 ins_encode %{
6841 __ block_comment("spin_wait {");
6842 __ smt_prio_low();
6843 __ smt_prio_medium();
6844 __ block_comment("}");
6845 %}
6846 ins_pipe(pipe_class_default);
6847 %}
6848
6849 //----------Conditional Move---------------------------------------------------
6850
6851 // Cmove using isel.
6852 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
6853 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
6854 ins_cost(DEFAULT_COST);
6855
6856 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
6857 size(4);
6858 ins_encode %{
6859 int cc = $cmp$$cmpcode;
6860 __ isel($dst$$Register, $crx$$CondRegister,
6861 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
6862 %}
6863 ins_pipe(pipe_class_default);
6864 %}
6865
6866 // Cmove using isel.
6867 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
6868 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
6869 ins_cost(DEFAULT_COST);
6870
6871 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
6872 size(4);
6873 ins_encode %{
6874 int cc = $cmp$$cmpcode;
6875 __ isel($dst$$Register, $crx$$CondRegister,
6876 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
6877 %}
6878 ins_pipe(pipe_class_default);
6879 %}
6880
6881 // Cmove using isel.
6882 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
6883 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
6884 ins_cost(DEFAULT_COST);
6885
6886 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
6887 size(4);
6888 ins_encode %{
6889 int cc = $cmp$$cmpcode;
6890 __ isel($dst$$Register, $crx$$CondRegister,
6891 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
6892 %}
6893 ins_pipe(pipe_class_default);
6894 %}
6895
6896 // Cmove using isel.
6897 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
6898 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
6899 ins_cost(DEFAULT_COST);
6900
6901 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
6902 size(4);
6903 ins_encode %{
6904 int cc = $cmp$$cmpcode;
6905 __ isel($dst$$Register, $crx$$CondRegister,
6906 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
6907 %}
6908 ins_pipe(pipe_class_default);
6909 %}
6910
6911 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
6912 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
6913 ins_cost(DEFAULT_COST+BRANCH_COST);
6914
6915 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
6916 size(8);
6917 ins_encode %{
6918 Label done;
6919 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
6920 // Branch if not (cmp crx).
6921 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
6922 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
6923 __ bind(done);
6924 %}
6925 ins_pipe(pipe_class_default);
6926 %}
6927
6928 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
6929 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
6930 ins_cost(DEFAULT_COST+BRANCH_COST);
6931
6932 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
6933 size(8);
6934 ins_encode %{
6935 Label done;
6936 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
6937 // Branch if not (cmp crx).
6938 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
6939 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
6940 __ bind(done);
6941 %}
6942 ins_pipe(pipe_class_default);
6943 %}
6944
6945 instruct cmovF_cmpF(cmpOp cop, regF op1, regF op2, regF dst, regF false_result, regF true_result, regD tmp) %{
6946 match(Set dst (CMoveF (Binary cop (CmpF op1 op2)) (Binary false_result true_result)));
6947 predicate(PowerArchitecturePPC64 >= 9);
6948 effect(TEMP tmp);
6949 ins_cost(2*DEFAULT_COST);
6950 format %{ "cmovF_cmpF $dst = ($op1 $cop $op2) ? $true_result : $false_result\n\t" %}
6951 size(8);
6952 ins_encode %{
6953 __ cmovF($cop$$cmpcode, $dst$$FloatRegister->to_vsr(),
6954 $op1$$FloatRegister->to_vsr(), $op2$$FloatRegister->to_vsr(),
6955 $true_result$$FloatRegister->to_vsr(), $false_result$$FloatRegister->to_vsr(),
6956 $tmp$$FloatRegister->to_vsr());
6957 %}
6958 ins_pipe(pipe_class_default);
6959 %}
6960
6961 instruct cmovF_cmpD(cmpOp cop, regD op1, regD op2, regF dst, regF false_result, regF true_result, regD tmp) %{
6962 match(Set dst (CMoveF (Binary cop (CmpD op1 op2)) (Binary false_result true_result)));
6963 predicate(PowerArchitecturePPC64 >= 9);
6964 effect(TEMP tmp);
6965 ins_cost(2*DEFAULT_COST);
6966 format %{ "cmovF_cmpD $dst = ($op1 $cop $op2) ? $true_result : $false_result\n\t" %}
6967 size(8);
6968 ins_encode %{
6969 __ cmovF($cop$$cmpcode, $dst$$FloatRegister->to_vsr(),
6970 $op1$$FloatRegister->to_vsr(), $op2$$FloatRegister->to_vsr(),
6971 $true_result$$FloatRegister->to_vsr(), $false_result$$FloatRegister->to_vsr(),
6972 $tmp$$FloatRegister->to_vsr());
6973 %}
6974 ins_pipe(pipe_class_default);
6975 %}
6976
6977 instruct cmovD_cmpD(cmpOp cop, regD op1, regD op2, regD dst, regD false_result, regD true_result, regD tmp) %{
6978 match(Set dst (CMoveD (Binary cop (CmpD op1 op2)) (Binary false_result true_result)));
6979 predicate(PowerArchitecturePPC64 >= 9);
6980 effect(TEMP tmp);
6981 ins_cost(2*DEFAULT_COST);
6982 format %{ "cmovD_cmpD $dst = ($op1 $cop $op2) ? $true_result : $false_result\n\t" %}
6983 size(8);
6984 ins_encode %{
6985 __ cmovF($cop$$cmpcode, $dst$$FloatRegister->to_vsr(),
6986 $op1$$FloatRegister->to_vsr(), $op2$$FloatRegister->to_vsr(),
6987 $true_result$$FloatRegister->to_vsr(), $false_result$$FloatRegister->to_vsr(),
6988 $tmp$$FloatRegister->to_vsr());
6989 %}
6990 ins_pipe(pipe_class_default);
6991 %}
6992
6993 instruct cmovD_cmpF(cmpOp cop, regF op1, regF op2, regD dst, regD false_result, regD true_result, regD tmp) %{
6994 match(Set dst (CMoveD (Binary cop (CmpF op1 op2)) (Binary false_result true_result)));
6995 predicate(PowerArchitecturePPC64 >= 9);
6996 effect(TEMP tmp);
6997 ins_cost(2*DEFAULT_COST);
6998 format %{ "cmovD_cmpF $dst = ($op1 $cop $op2) ? $true_result : $false_result\n\t" %}
6999 size(8);
7000 ins_encode %{
7001 __ cmovF($cop$$cmpcode, $dst$$FloatRegister->to_vsr(),
7002 $op1$$FloatRegister->to_vsr(), $op2$$FloatRegister->to_vsr(),
7003 $true_result$$FloatRegister->to_vsr(), $false_result$$FloatRegister->to_vsr(),
7004 $tmp$$FloatRegister->to_vsr());
7005 %}
7006 ins_pipe(pipe_class_default);
7007 %}
7008
7009 //----------Compare-And-Swap---------------------------------------------------
7010
7011 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7012 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7013 // matched.
7014
7015 // Strong versions:
7016
7017 instruct compareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7018 match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7019 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7020 format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7021 ins_encode %{
7022 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7023 __ cmpxchgb(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7024 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7025 $res$$Register, nullptr, true);
7026 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7027 __ isync();
7028 } else {
7029 __ sync();
7030 }
7031 %}
7032 ins_pipe(pipe_class_default);
7033 %}
7034
7035 instruct compareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7036 match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7037 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7038 format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7039 ins_encode %{
7040 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7041 __ cmpxchgh(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7042 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7043 $res$$Register, nullptr, true);
7044 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7045 __ isync();
7046 } else {
7047 __ sync();
7048 }
7049 %}
7050 ins_pipe(pipe_class_default);
7051 %}
7052
7053 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7054 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7055 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7056 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7057 ins_encode %{
7058 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7059 __ cmpxchgw(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7060 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7061 $res$$Register, nullptr, true);
7062 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7063 __ isync();
7064 } else {
7065 __ sync();
7066 }
7067 %}
7068 ins_pipe(pipe_class_default);
7069 %}
7070
7071 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7072 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7073 predicate(n->as_LoadStore()->barrier_data() == 0);
7074 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7075 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7076 ins_encode %{
7077 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7078 __ cmpxchgw(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7079 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7080 $res$$Register, nullptr, true);
7081 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7082 __ isync();
7083 } else {
7084 __ sync();
7085 }
7086 %}
7087 ins_pipe(pipe_class_default);
7088 %}
7089
7090 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7091 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7092 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7093 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7094 ins_encode %{
7095 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7096 __ cmpxchgd(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7097 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7098 $res$$Register, nullptr, true);
7099 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7100 __ isync();
7101 } else {
7102 __ sync();
7103 }
7104 %}
7105 ins_pipe(pipe_class_default);
7106 %}
7107
7108 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7109 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7110 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7111 predicate(n->as_LoadStore()->barrier_data() == 0);
7112 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7113 ins_encode %{
7114 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7115 __ cmpxchgd(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7116 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7117 $res$$Register, nullptr, true);
7118 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7119 __ isync();
7120 } else {
7121 __ sync();
7122 }
7123 %}
7124 ins_pipe(pipe_class_default);
7125 %}
7126
7127 // Weak versions:
7128
7129 instruct weakCompareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7130 match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7131 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7132 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7133 format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7134 ins_encode %{
7135 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7136 __ cmpxchgb(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7137 MacroAssembler::MemBarNone,
7138 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7139 %}
7140 ins_pipe(pipe_class_default);
7141 %}
7142
7143 instruct weakCompareAndSwapB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7144 match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7145 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) );
7146 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7147 format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
7148 ins_encode %{
7149 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7150 __ cmpxchgb(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7151 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7152 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7153 %}
7154 ins_pipe(pipe_class_default);
7155 %}
7156
7157 instruct weakCompareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7158 match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7159 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7160 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7161 format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7162 ins_encode %{
7163 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7164 __ cmpxchgh(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7165 MacroAssembler::MemBarNone,
7166 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7167 %}
7168 ins_pipe(pipe_class_default);
7169 %}
7170
7171 instruct weakCompareAndSwapS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7172 match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7173 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst));
7174 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7175 format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
7176 ins_encode %{
7177 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7178 __ cmpxchgh(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7179 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7180 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7181 %}
7182 ins_pipe(pipe_class_default);
7183 %}
7184
7185 instruct weakCompareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7186 match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
7187 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7188 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7189 format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7190 ins_encode %{
7191 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7192 __ cmpxchgw(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7193 MacroAssembler::MemBarNone,
7194 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7195 %}
7196 ins_pipe(pipe_class_default);
7197 %}
7198
7199 instruct weakCompareAndSwapI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7200 match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
7201 predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7202 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7203 format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
7204 ins_encode %{
7205 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7206 // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7207 // value is never passed to caller.
7208 __ cmpxchgw(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7209 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7210 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7211 %}
7212 ins_pipe(pipe_class_default);
7213 %}
7214
7215 instruct weakCompareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7216 match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
7217 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && n->as_LoadStore()->barrier_data() == 0);
7218 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7219 format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7220 ins_encode %{
7221 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7222 __ cmpxchgw(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7223 MacroAssembler::MemBarNone,
7224 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7225 %}
7226 ins_pipe(pipe_class_default);
7227 %}
7228
7229 instruct weakCompareAndSwapN_acq_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7230 match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
7231 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && n->as_LoadStore()->barrier_data() == 0);
7232 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7233 format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
7234 ins_encode %{
7235 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7236 // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7237 // value is never passed to caller.
7238 __ cmpxchgw(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7239 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7240 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7241 %}
7242 ins_pipe(pipe_class_default);
7243 %}
7244
7245 instruct weakCompareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7246 match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
7247 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7248 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7249 format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7250 ins_encode %{
7251 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7252 // value is never passed to caller.
7253 __ cmpxchgd(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7254 MacroAssembler::MemBarNone,
7255 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7256 %}
7257 ins_pipe(pipe_class_default);
7258 %}
7259
7260 instruct weakCompareAndSwapL_acq_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7261 match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
7262 predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7263 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7264 format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool" %}
7265 ins_encode %{
7266 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7267 // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7268 // value is never passed to caller.
7269 __ cmpxchgd(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7270 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7271 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7272 %}
7273 ins_pipe(pipe_class_default);
7274 %}
7275
7276 instruct weakCompareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7277 match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
7278 predicate((((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst) && n->as_LoadStore()->barrier_data() == 0);
7279 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7280 format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7281 ins_encode %{
7282 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7283 __ cmpxchgd(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7284 MacroAssembler::MemBarNone,
7285 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7286 %}
7287 ins_pipe(pipe_class_default);
7288 %}
7289
7290 instruct weakCompareAndSwapP_acq_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7291 match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
7292 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && n->as_LoadStore()->barrier_data() == 0);
7293 effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7294 format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7295 ins_encode %{
7296 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7297 // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7298 // value is never passed to caller.
7299 __ cmpxchgd(CR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7300 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7301 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, nullptr, true, /*weak*/ true);
7302 %}
7303 ins_pipe(pipe_class_default);
7304 %}
7305
7306 // CompareAndExchange
7307
7308 instruct compareAndExchangeB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7309 match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7310 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7311 effect(TEMP_DEF res, TEMP cr0);
7312 format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
7313 ins_encode %{
7314 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7315 __ cmpxchgb(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7316 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7317 noreg, nullptr, true);
7318 %}
7319 ins_pipe(pipe_class_default);
7320 %}
7321
7322 instruct compareAndExchangeB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7323 match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7324 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst));
7325 effect(TEMP_DEF res, TEMP cr0);
7326 format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
7327 ins_encode %{
7328 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7329 __ cmpxchgb(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7330 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7331 noreg, nullptr, true);
7332 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7333 __ isync();
7334 } else {
7335 // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7336 __ sync();
7337 }
7338 %}
7339 ins_pipe(pipe_class_default);
7340 %}
7341
7342
7343 instruct compareAndExchangeS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7344 match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7345 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7346 effect(TEMP_DEF res, TEMP cr0);
7347 format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
7348 ins_encode %{
7349 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7350 __ cmpxchgh(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7351 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7352 noreg, nullptr, true);
7353 %}
7354 ins_pipe(pipe_class_default);
7355 %}
7356
7357 instruct compareAndExchangeS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7358 match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7359 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst));
7360 effect(TEMP_DEF res, TEMP cr0);
7361 format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
7362 ins_encode %{
7363 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7364 __ cmpxchgh(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7365 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7366 noreg, nullptr, true);
7367 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7368 __ isync();
7369 } else {
7370 // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7371 __ sync();
7372 }
7373 %}
7374 ins_pipe(pipe_class_default);
7375 %}
7376
7377 instruct compareAndExchangeI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7378 match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
7379 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7380 effect(TEMP_DEF res, TEMP cr0);
7381 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as int" %}
7382 ins_encode %{
7383 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7384 __ cmpxchgw(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7385 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7386 noreg, nullptr, true);
7387 %}
7388 ins_pipe(pipe_class_default);
7389 %}
7390
7391 instruct compareAndExchangeI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7392 match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
7393 predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7394 effect(TEMP_DEF res, TEMP cr0);
7395 format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as int" %}
7396 ins_encode %{
7397 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7398 __ cmpxchgw(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7399 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7400 noreg, nullptr, true);
7401 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7402 __ isync();
7403 } else {
7404 // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7405 __ sync();
7406 }
7407 %}
7408 ins_pipe(pipe_class_default);
7409 %}
7410
7411 instruct compareAndExchangeN_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7412 match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
7413 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && n->as_LoadStore()->barrier_data() == 0);
7414 effect(TEMP_DEF res, TEMP cr0);
7415 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as narrow oop" %}
7416 ins_encode %{
7417 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7418 __ cmpxchgw(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7419 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7420 noreg, nullptr, true);
7421 %}
7422 ins_pipe(pipe_class_default);
7423 %}
7424
7425 instruct compareAndExchangeN_acq_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7426 match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
7427 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && n->as_LoadStore()->barrier_data() == 0);
7428 effect(TEMP_DEF res, TEMP cr0);
7429 format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as narrow oop" %}
7430 ins_encode %{
7431 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7432 __ cmpxchgw(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7433 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7434 noreg, nullptr, true);
7435 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7436 __ isync();
7437 } else {
7438 // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7439 __ sync();
7440 }
7441 %}
7442 ins_pipe(pipe_class_default);
7443 %}
7444
7445 instruct compareAndExchangeL_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7446 match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
7447 predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7448 effect(TEMP_DEF res, TEMP cr0);
7449 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as long" %}
7450 ins_encode %{
7451 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7452 __ cmpxchgd(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7453 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7454 noreg, nullptr, true);
7455 %}
7456 ins_pipe(pipe_class_default);
7457 %}
7458
7459 instruct compareAndExchangeL_acq_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7460 match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
7461 predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7462 effect(TEMP_DEF res, TEMP cr0);
7463 format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as long" %}
7464 ins_encode %{
7465 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7466 __ cmpxchgd(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7467 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7468 noreg, nullptr, true);
7469 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7470 __ isync();
7471 } else {
7472 // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7473 __ sync();
7474 }
7475 %}
7476 ins_pipe(pipe_class_default);
7477 %}
7478
7479 instruct compareAndExchangeP_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7480 match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
7481 predicate((((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst)
7482 && n->as_LoadStore()->barrier_data() == 0);
7483 effect(TEMP_DEF res, TEMP cr0);
7484 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
7485 ins_encode %{
7486 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7487 __ cmpxchgd(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7488 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7489 noreg, nullptr, true);
7490 %}
7491 ins_pipe(pipe_class_default);
7492 %}
7493
7494 instruct compareAndExchangeP_acq_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7495 match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
7496 predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst)
7497 && n->as_LoadStore()->barrier_data() == 0);
7498 effect(TEMP_DEF res, TEMP cr0);
7499 format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
7500 ins_encode %{
7501 // CmpxchgX sets CR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7502 __ cmpxchgd(CR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7503 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7504 noreg, nullptr, true);
7505 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7506 __ isync();
7507 } else {
7508 // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7509 __ sync();
7510 }
7511 %}
7512 ins_pipe(pipe_class_default);
7513 %}
7514
7515 // Special RMW
7516
7517 instruct getAndAddB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7518 match(Set res (GetAndAddB mem_ptr src));
7519 effect(TEMP_DEF res, TEMP cr0);
7520 format %{ "GetAndAddB $res, $mem_ptr, $src" %}
7521 ins_encode %{
7522 __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
7523 R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
7524 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7525 __ isync();
7526 } else {
7527 __ sync();
7528 }
7529 %}
7530 ins_pipe(pipe_class_default);
7531 %}
7532
7533 instruct getAndAddS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7534 match(Set res (GetAndAddS mem_ptr src));
7535 effect(TEMP_DEF res, TEMP cr0);
7536 format %{ "GetAndAddS $res, $mem_ptr, $src" %}
7537 ins_encode %{
7538 __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
7539 R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
7540 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7541 __ isync();
7542 } else {
7543 __ sync();
7544 }
7545 %}
7546 ins_pipe(pipe_class_default);
7547 %}
7548
7549
7550 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7551 match(Set res (GetAndAddI mem_ptr src));
7552 effect(TEMP_DEF res, TEMP cr0);
7553 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7554 ins_encode %{
7555 __ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
7556 R0, MacroAssembler::cmpxchgx_hint_atomic_update());
7557 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7558 __ isync();
7559 } else {
7560 __ sync();
7561 }
7562 %}
7563 ins_pipe(pipe_class_default);
7564 %}
7565
7566 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7567 match(Set res (GetAndAddL mem_ptr src));
7568 effect(TEMP_DEF res, TEMP cr0);
7569 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7570 ins_encode %{
7571 __ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
7572 R0, MacroAssembler::cmpxchgx_hint_atomic_update());
7573 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7574 __ isync();
7575 } else {
7576 __ sync();
7577 }
7578 %}
7579 ins_pipe(pipe_class_default);
7580 %}
7581
7582 instruct getAndSetB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7583 match(Set res (GetAndSetB mem_ptr src));
7584 effect(TEMP_DEF res, TEMP cr0);
7585 format %{ "GetAndSetB $res, $mem_ptr, $src" %}
7586 ins_encode %{
7587 __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
7588 noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
7589 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7590 __ isync();
7591 } else {
7592 __ sync();
7593 }
7594 %}
7595 ins_pipe(pipe_class_default);
7596 %}
7597
7598 instruct getAndSetS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7599 match(Set res (GetAndSetS mem_ptr src));
7600 effect(TEMP_DEF res, TEMP cr0);
7601 format %{ "GetAndSetS $res, $mem_ptr, $src" %}
7602 ins_encode %{
7603 __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
7604 noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
7605 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7606 __ isync();
7607 } else {
7608 __ sync();
7609 }
7610 %}
7611 ins_pipe(pipe_class_default);
7612 %}
7613
7614
7615 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7616 match(Set res (GetAndSetI mem_ptr src));
7617 effect(TEMP_DEF res, TEMP cr0);
7618 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7619 ins_encode %{
7620 __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
7621 MacroAssembler::cmpxchgx_hint_atomic_update());
7622 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7623 __ isync();
7624 } else {
7625 __ sync();
7626 }
7627 %}
7628 ins_pipe(pipe_class_default);
7629 %}
7630
7631 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7632 match(Set res (GetAndSetL mem_ptr src));
7633 effect(TEMP_DEF res, TEMP cr0);
7634 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7635 ins_encode %{
7636 __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
7637 MacroAssembler::cmpxchgx_hint_atomic_update());
7638 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7639 __ isync();
7640 } else {
7641 __ sync();
7642 }
7643 %}
7644 ins_pipe(pipe_class_default);
7645 %}
7646
7647 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7648 match(Set res (GetAndSetP mem_ptr src));
7649 predicate(n->as_LoadStore()->barrier_data() == 0);
7650 effect(TEMP_DEF res, TEMP cr0);
7651 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7652 ins_encode %{
7653 __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
7654 MacroAssembler::cmpxchgx_hint_atomic_update());
7655 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7656 __ isync();
7657 } else {
7658 __ sync();
7659 }
7660 %}
7661 ins_pipe(pipe_class_default);
7662 %}
7663
7664 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7665 match(Set res (GetAndSetN mem_ptr src));
7666 predicate(n->as_LoadStore()->barrier_data() == 0);
7667 effect(TEMP_DEF res, TEMP cr0);
7668 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7669 ins_encode %{
7670 __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
7671 MacroAssembler::cmpxchgx_hint_atomic_update());
7672 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7673 __ isync();
7674 } else {
7675 __ sync();
7676 }
7677 %}
7678 ins_pipe(pipe_class_default);
7679 %}
7680
7681 //----------Arithmetic Instructions--------------------------------------------
7682 // Addition Instructions
7683
7684 // Register Addition
7685 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7686 match(Set dst (AddI src1 src2));
7687 format %{ "ADD $dst, $src1, $src2" %}
7688 size(4);
7689 ins_encode %{
7690 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7691 %}
7692 ins_pipe(pipe_class_default);
7693 %}
7694
7695 // Expand does not work with above instruct. (??)
7696 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7697 // no match-rule
7698 effect(DEF dst, USE src1, USE src2);
7699 format %{ "ADD $dst, $src1, $src2" %}
7700 size(4);
7701 ins_encode %{
7702 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7703 %}
7704 ins_pipe(pipe_class_default);
7705 %}
7706
7707 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7708 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7709 ins_cost(DEFAULT_COST*3);
7710
7711 expand %{
7712 // FIXME: we should do this in the ideal world.
7713 iRegIdst tmp1;
7714 iRegIdst tmp2;
7715 addI_reg_reg(tmp1, src1, src2);
7716 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7717 addI_reg_reg(dst, tmp1, tmp2);
7718 %}
7719 %}
7720
7721 // Immediate Addition
7722 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7723 match(Set dst (AddI src1 src2));
7724 format %{ "ADDI $dst, $src1, $src2" %}
7725 size(4);
7726 ins_encode %{
7727 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7728 %}
7729 ins_pipe(pipe_class_default);
7730 %}
7731
7732 // Immediate Addition with 16-bit shifted operand
7733 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7734 match(Set dst (AddI src1 src2));
7735 format %{ "ADDIS $dst, $src1, $src2" %}
7736 size(4);
7737 ins_encode %{
7738 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7739 %}
7740 ins_pipe(pipe_class_default);
7741 %}
7742
7743 // Immediate Addition using prefixed addi
7744 instruct addI_reg_imm32(iRegIdst dst, iRegIsrc src1, immI32 src2) %{
7745 match(Set dst (AddI src1 src2));
7746 predicate(PowerArchitecturePPC64 >= 10);
7747 ins_cost(DEFAULT_COST+1);
7748 format %{ "PADDI $dst, $src1, $src2" %}
7749 size(8);
7750 ins_encode %{
7751 assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
7752 __ paddi($dst$$Register, $src1$$Register, $src2$$constant);
7753 %}
7754 ins_pipe(pipe_class_default);
7755 ins_alignment(2);
7756 %}
7757
7758 // Long Addition
7759 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7760 match(Set dst (AddL src1 src2));
7761 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7762 size(4);
7763 ins_encode %{
7764 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7765 %}
7766 ins_pipe(pipe_class_default);
7767 %}
7768
7769 // Expand does not work with above instruct. (??)
7770 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7771 // no match-rule
7772 effect(DEF dst, USE src1, USE src2);
7773 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7774 size(4);
7775 ins_encode %{
7776 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7777 %}
7778 ins_pipe(pipe_class_default);
7779 %}
7780
7781 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7782 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7783 ins_cost(DEFAULT_COST*3);
7784
7785 expand %{
7786 // FIXME: we should do this in the ideal world.
7787 iRegLdst tmp1;
7788 iRegLdst tmp2;
7789 addL_reg_reg(tmp1, src1, src2);
7790 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7791 addL_reg_reg(dst, tmp1, tmp2);
7792 %}
7793 %}
7794
7795 // AddL + ConvL2I.
7796 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7797 match(Set dst (ConvL2I (AddL src1 src2)));
7798
7799 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7800 size(4);
7801 ins_encode %{
7802 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7803 %}
7804 ins_pipe(pipe_class_default);
7805 %}
7806
7807 // No constant pool entries required.
7808 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7809 match(Set dst (AddL src1 src2));
7810
7811 format %{ "ADDI $dst, $src1, $src2" %}
7812 size(4);
7813 ins_encode %{
7814 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7815 %}
7816 ins_pipe(pipe_class_default);
7817 %}
7818
7819 // Long Immediate Addition with 16-bit shifted operand.
7820 // No constant pool entries required.
7821 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7822 match(Set dst (AddL src1 src2));
7823
7824 format %{ "ADDIS $dst, $src1, $src2" %}
7825 size(4);
7826 ins_encode %{
7827 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7828 %}
7829 ins_pipe(pipe_class_default);
7830 %}
7831
7832 // Long Immediate Addition using prefixed addi
7833 // No constant pool entries required.
7834 instruct addL_reg_imm34(iRegLdst dst, iRegLsrc src1, immL34 src2) %{
7835 match(Set dst (AddL src1 src2));
7836 predicate(PowerArchitecturePPC64 >= 10);
7837 ins_cost(DEFAULT_COST+1);
7838
7839 format %{ "PADDI $dst, $src1, $src2" %}
7840 size(8);
7841 ins_encode %{
7842 assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
7843 __ paddi($dst$$Register, $src1$$Register, $src2$$constant);
7844 %}
7845 ins_pipe(pipe_class_default);
7846 ins_alignment(2);
7847 %}
7848
7849 // Pointer Register Addition
7850 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7851 match(Set dst (AddP src1 src2));
7852 format %{ "ADD $dst, $src1, $src2" %}
7853 size(4);
7854 ins_encode %{
7855 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7856 %}
7857 ins_pipe(pipe_class_default);
7858 %}
7859
7860 // Pointer Immediate Addition
7861 // No constant pool entries required.
7862 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7863 match(Set dst (AddP src1 src2));
7864
7865 format %{ "ADDI $dst, $src1, $src2" %}
7866 size(4);
7867 ins_encode %{
7868 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7869 %}
7870 ins_pipe(pipe_class_default);
7871 %}
7872
7873 // Pointer Immediate Addition with 16-bit shifted operand.
7874 // No constant pool entries required.
7875 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7876 match(Set dst (AddP src1 src2));
7877
7878 format %{ "ADDIS $dst, $src1, $src2" %}
7879 size(4);
7880 ins_encode %{
7881 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7882 %}
7883 ins_pipe(pipe_class_default);
7884 %}
7885
7886 // Pointer Immediate Addition using prefixed addi
7887 // No constant pool entries required.
7888 instruct addP_reg_imm34(iRegPdst dst, iRegP_N2P src1, immL34 src2) %{
7889 match(Set dst (AddP src1 src2));
7890 predicate(PowerArchitecturePPC64 >= 10);
7891 ins_cost(DEFAULT_COST+1);
7892
7893 format %{ "PADDI $dst, $src1, $src2" %}
7894 size(8);
7895 ins_encode %{
7896 assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
7897 __ paddi($dst$$Register, $src1$$Register, $src2$$constant);
7898 %}
7899 ins_pipe(pipe_class_default);
7900 ins_alignment(2);
7901 %}
7902
7903 //---------------------
7904 // Subtraction Instructions
7905
7906 // Register Subtraction
7907 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7908 match(Set dst (SubI src1 src2));
7909 format %{ "SUBF $dst, $src2, $src1" %}
7910 size(4);
7911 ins_encode %{
7912 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7913 %}
7914 ins_pipe(pipe_class_default);
7915 %}
7916
7917 // Immediate Subtraction
7918 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7919 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7920
7921 // SubI from constant (using subfic).
7922 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7923 match(Set dst (SubI src1 src2));
7924 format %{ "SUBI $dst, $src1, $src2" %}
7925
7926 size(4);
7927 ins_encode %{
7928 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7929 %}
7930 ins_pipe(pipe_class_default);
7931 %}
7932
7933 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7934 // positive integers and 0xF...F for negative ones.
7935 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7936 // no match-rule, false predicate
7937 effect(DEF dst, USE src);
7938 predicate(false);
7939
7940 format %{ "SRAWI $dst, $src, #31" %}
7941 size(4);
7942 ins_encode %{
7943 __ srawi($dst$$Register, $src$$Register, 0x1f);
7944 %}
7945 ins_pipe(pipe_class_default);
7946 %}
7947
7948 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7949 match(Set dst (AbsI src));
7950 ins_cost(DEFAULT_COST*3);
7951
7952 expand %{
7953 iRegIdst tmp1;
7954 iRegIdst tmp2;
7955 signmask32I_regI(tmp1, src);
7956 xorI_reg_reg(tmp2, tmp1, src);
7957 subI_reg_reg(dst, tmp2, tmp1);
7958 %}
7959 %}
7960
7961 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7962 match(Set dst (SubI zero src2));
7963 format %{ "NEG $dst, $src2" %}
7964 size(4);
7965 ins_encode %{
7966 __ neg($dst$$Register, $src2$$Register);
7967 %}
7968 ins_pipe(pipe_class_default);
7969 %}
7970
7971 // Long subtraction
7972 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7973 match(Set dst (SubL src1 src2));
7974 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7975 size(4);
7976 ins_encode %{
7977 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7978 %}
7979 ins_pipe(pipe_class_default);
7980 %}
7981
7982 // SubL + convL2I.
7983 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7984 match(Set dst (ConvL2I (SubL src1 src2)));
7985
7986 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7987 size(4);
7988 ins_encode %{
7989 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7990 %}
7991 ins_pipe(pipe_class_default);
7992 %}
7993
7994 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7995 // positive longs and 0xF...F for negative ones.
7996 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7997 // no match-rule, false predicate
7998 effect(DEF dst, USE src);
7999 predicate(false);
8000
8001 format %{ "SRADI $dst, $src, #63" %}
8002 size(4);
8003 ins_encode %{
8004 __ sradi($dst$$Register, $src$$Register, 0x3f);
8005 %}
8006 ins_pipe(pipe_class_default);
8007 %}
8008
8009 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8010 // positive longs and 0xF...F for negative ones.
8011 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8012 // no match-rule, false predicate
8013 effect(DEF dst, USE src);
8014 predicate(false);
8015
8016 format %{ "SRADI $dst, $src, #63" %}
8017 size(4);
8018 ins_encode %{
8019 __ sradi($dst$$Register, $src$$Register, 0x3f);
8020 %}
8021 ins_pipe(pipe_class_default);
8022 %}
8023
8024 instruct absL_reg_Ex(iRegLdst dst, iRegLsrc src) %{
8025 match(Set dst (AbsL src));
8026 ins_cost(DEFAULT_COST*3);
8027
8028 expand %{
8029 iRegLdst tmp1;
8030 iRegLdst tmp2;
8031 signmask64L_regL(tmp1, src);
8032 xorL_reg_reg(tmp2, tmp1, src);
8033 subL_reg_reg(dst, tmp2, tmp1);
8034 %}
8035 %}
8036
8037 // Long negation
8038 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8039 match(Set dst (SubL zero src2));
8040 format %{ "NEG $dst, $src2 \t// long" %}
8041 size(4);
8042 ins_encode %{
8043 __ neg($dst$$Register, $src2$$Register);
8044 %}
8045 ins_pipe(pipe_class_default);
8046 %}
8047
8048 // NegL + ConvL2I.
8049 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8050 match(Set dst (ConvL2I (SubL zero src2)));
8051
8052 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8053 size(4);
8054 ins_encode %{
8055 __ neg($dst$$Register, $src2$$Register);
8056 %}
8057 ins_pipe(pipe_class_default);
8058 %}
8059
8060 // Multiplication Instructions
8061 // Integer Multiplication
8062
8063 // Register Multiplication
8064 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8065 match(Set dst (MulI src1 src2));
8066 ins_cost(DEFAULT_COST);
8067
8068 format %{ "MULLW $dst, $src1, $src2" %}
8069 size(4);
8070 ins_encode %{
8071 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8072 %}
8073 ins_pipe(pipe_class_default);
8074 %}
8075
8076 // Immediate Multiplication
8077 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8078 match(Set dst (MulI src1 src2));
8079 ins_cost(DEFAULT_COST);
8080
8081 format %{ "MULLI $dst, $src1, $src2" %}
8082 size(4);
8083 ins_encode %{
8084 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8085 %}
8086 ins_pipe(pipe_class_default);
8087 %}
8088
8089 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8090 match(Set dst (MulL src1 src2));
8091 ins_cost(DEFAULT_COST);
8092
8093 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8094 size(4);
8095 ins_encode %{
8096 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8097 %}
8098 ins_pipe(pipe_class_default);
8099 %}
8100
8101 // Multiply high for optimized long division by constant.
8102 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8103 match(Set dst (MulHiL src1 src2));
8104 ins_cost(DEFAULT_COST);
8105
8106 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8107 size(4);
8108 ins_encode %{
8109 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8110 %}
8111 ins_pipe(pipe_class_default);
8112 %}
8113
8114 instruct uMulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8115 match(Set dst (UMulHiL src1 src2));
8116 ins_cost(DEFAULT_COST);
8117
8118 format %{ "MULHDU $dst $src1, $src2 \t// unsigned long" %}
8119 size(4);
8120 ins_encode %{
8121 __ mulhdu($dst$$Register, $src1$$Register, $src2$$Register);
8122 %}
8123 ins_pipe(pipe_class_default);
8124 %}
8125
8126 // Immediate Multiplication
8127 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8128 match(Set dst (MulL src1 src2));
8129 ins_cost(DEFAULT_COST);
8130
8131 format %{ "MULLI $dst, $src1, $src2" %}
8132 size(4);
8133 ins_encode %{
8134 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8135 %}
8136 ins_pipe(pipe_class_default);
8137 %}
8138
8139 // Integer Division with Immediate -1: Negate.
8140 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8141 match(Set dst (DivI src1 src2));
8142 ins_cost(DEFAULT_COST);
8143
8144 format %{ "NEG $dst, $src1 \t// /-1" %}
8145 size(4);
8146 ins_encode %{
8147 __ neg($dst$$Register, $src1$$Register);
8148 %}
8149 ins_pipe(pipe_class_default);
8150 %}
8151
8152 // Integer Division with constant, but not -1.
8153 // We should be able to improve this by checking the type of src2.
8154 // It might well be that src2 is known to be positive.
8155 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8156 match(Set dst (DivI src1 src2));
8157 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8158 ins_cost(2*DEFAULT_COST);
8159
8160 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8161 size(4);
8162 ins_encode %{
8163 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8164 %}
8165 ins_pipe(pipe_class_default);
8166 %}
8167
8168 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8169 effect(USE_DEF dst, USE src1, USE crx);
8170 predicate(false);
8171
8172 format %{ "CMOVE $dst, neg($src1), $crx" %}
8173 size(8);
8174 ins_encode %{
8175 Label done;
8176 __ bne($crx$$CondRegister, done);
8177 __ neg($dst$$Register, $src1$$Register);
8178 __ bind(done);
8179 %}
8180 ins_pipe(pipe_class_default);
8181 %}
8182
8183 // Integer Division with Registers not containing constants.
8184 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8185 match(Set dst (DivI src1 src2));
8186 ins_cost(10*DEFAULT_COST);
8187
8188 expand %{
8189 immI16 imm %{ (int)-1 %}
8190 flagsReg tmp1;
8191 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8192 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8193 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8194 %}
8195 %}
8196
8197 // Long Division with Immediate -1: Negate.
8198 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8199 match(Set dst (DivL src1 src2));
8200 ins_cost(DEFAULT_COST);
8201
8202 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8203 size(4);
8204 ins_encode %{
8205 __ neg($dst$$Register, $src1$$Register);
8206 %}
8207 ins_pipe(pipe_class_default);
8208 %}
8209
8210 // Long Division with constant, but not -1.
8211 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8212 match(Set dst (DivL src1 src2));
8213 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8214 ins_cost(2*DEFAULT_COST);
8215
8216 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8217 size(4);
8218 ins_encode %{
8219 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8220 %}
8221 ins_pipe(pipe_class_default);
8222 %}
8223
8224 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8225 effect(USE_DEF dst, USE src1, USE crx);
8226 predicate(false);
8227
8228 format %{ "CMOVE $dst, neg($src1), $crx" %}
8229 size(8);
8230 ins_encode %{
8231 Label done;
8232 __ bne($crx$$CondRegister, done);
8233 __ neg($dst$$Register, $src1$$Register);
8234 __ bind(done);
8235 %}
8236 ins_pipe(pipe_class_default);
8237 %}
8238
8239 // Long Division with Registers not containing constants.
8240 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8241 match(Set dst (DivL src1 src2));
8242 ins_cost(10*DEFAULT_COST);
8243
8244 expand %{
8245 immL16 imm %{ (int)-1 %}
8246 flagsReg tmp1;
8247 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8248 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8249 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8250 %}
8251 %}
8252
8253 // Integer Remainder with registers.
8254 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8255 match(Set dst (ModI src1 src2));
8256 ins_cost(10*DEFAULT_COST);
8257
8258 expand %{
8259 immI16 imm %{ (int)-1 %}
8260 flagsReg tmp1;
8261 iRegIdst tmp2;
8262 iRegIdst tmp3;
8263 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8264 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8265 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8266 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8267 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8268 %}
8269 %}
8270
8271 // Long Remainder with registers
8272 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8273 match(Set dst (ModL src1 src2));
8274 ins_cost(10*DEFAULT_COST);
8275
8276 expand %{
8277 immL16 imm %{ (int)-1 %}
8278 flagsReg tmp1;
8279 iRegLdst tmp2;
8280 iRegLdst tmp3;
8281 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8282 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8283 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8284 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8285 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8286 %}
8287 %}
8288
8289 instruct udivI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8290 match(Set dst (UDivI src1 src2));
8291 format %{ "DIVWU $dst, $src1, $src2" %}
8292 size(4);
8293 ins_encode %{
8294 __ divwu($dst$$Register, $src1$$Register, $src2$$Register);
8295 %}
8296 ins_pipe(pipe_class_default);
8297 %}
8298
8299 instruct umodI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8300 match(Set dst (UModI src1 src2));
8301 expand %{
8302 iRegIdst tmp1;
8303 iRegIdst tmp2;
8304 udivI_reg_reg(tmp1, src1, src2);
8305 // Compute lower 32 bit result using signed instructions as suggested by ISA.
8306 // Upper 32 bit will contain garbage.
8307 mulI_reg_reg(tmp2, src2, tmp1);
8308 subI_reg_reg(dst, src1, tmp2);
8309 %}
8310 %}
8311
8312 instruct udivL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8313 match(Set dst (UDivL src1 src2));
8314 format %{ "DIVDU $dst, $src1, $src2" %}
8315 size(4);
8316 ins_encode %{
8317 __ divdu($dst$$Register, $src1$$Register, $src2$$Register);
8318 %}
8319 ins_pipe(pipe_class_default);
8320 %}
8321
8322 instruct umodL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8323 match(Set dst (UModL src1 src2));
8324 expand %{
8325 iRegLdst tmp1;
8326 iRegLdst tmp2;
8327 udivL_reg_reg(tmp1, src1, src2);
8328 mulL_reg_reg(tmp2, src2, tmp1);
8329 subL_reg_reg(dst, src1, tmp2);
8330 %}
8331 %}
8332
8333 // Integer Shift Instructions
8334
8335 // Register Shift Left
8336
8337 // Clear all but the lowest #mask bits.
8338 // Used to normalize shift amounts in registers.
8339 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8340 // no match-rule, false predicate
8341 effect(DEF dst, USE src, USE mask);
8342 predicate(false);
8343
8344 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8345 size(4);
8346 ins_encode %{
8347 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8348 %}
8349 ins_pipe(pipe_class_default);
8350 %}
8351
8352 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8353 // no match-rule, false predicate
8354 effect(DEF dst, USE src1, USE src2);
8355 predicate(false);
8356
8357 format %{ "SLW $dst, $src1, $src2" %}
8358 size(4);
8359 ins_encode %{
8360 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8361 %}
8362 ins_pipe(pipe_class_default);
8363 %}
8364
8365 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8366 match(Set dst (LShiftI src1 src2));
8367 ins_cost(DEFAULT_COST*2);
8368 expand %{
8369 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8370 iRegIdst tmpI;
8371 maskI_reg_imm(tmpI, src2, mask);
8372 lShiftI_reg_reg(dst, src1, tmpI);
8373 %}
8374 %}
8375
8376 // Register Shift Left Immediate
8377 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8378 match(Set dst (LShiftI src1 src2));
8379
8380 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8381 size(4);
8382 ins_encode %{
8383 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8384 %}
8385 ins_pipe(pipe_class_default);
8386 %}
8387
8388 // AndI with negpow2-constant + LShiftI
8389 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8390 match(Set dst (LShiftI (AndI src1 src2) src3));
8391 predicate(UseRotateAndMaskInstructionsPPC64);
8392
8393 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8394 size(4);
8395 ins_encode %{
8396 long src3 = $src3$$constant;
8397 long maskbits = src3 + log2i_exact(-(juint)$src2$$constant);
8398 if (maskbits >= 32) {
8399 __ li($dst$$Register, 0); // addi
8400 } else {
8401 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8402 }
8403 %}
8404 ins_pipe(pipe_class_default);
8405 %}
8406
8407 // RShiftI + AndI with negpow2-constant + LShiftI
8408 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8409 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8410 predicate(UseRotateAndMaskInstructionsPPC64);
8411
8412 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8413 size(4);
8414 ins_encode %{
8415 long src3 = $src3$$constant;
8416 long maskbits = src3 + log2i_exact(-(juint)$src2$$constant);
8417 if (maskbits >= 32) {
8418 __ li($dst$$Register, 0); // addi
8419 } else {
8420 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8421 }
8422 %}
8423 ins_pipe(pipe_class_default);
8424 %}
8425
8426 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8427 // no match-rule, false predicate
8428 effect(DEF dst, USE src1, USE src2);
8429 predicate(false);
8430
8431 format %{ "SLD $dst, $src1, $src2" %}
8432 size(4);
8433 ins_encode %{
8434 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8435 %}
8436 ins_pipe(pipe_class_default);
8437 %}
8438
8439 // Register Shift Left
8440 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8441 match(Set dst (LShiftL src1 src2));
8442 ins_cost(DEFAULT_COST*2);
8443 expand %{
8444 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8445 iRegIdst tmpI;
8446 maskI_reg_imm(tmpI, src2, mask);
8447 lShiftL_regL_regI(dst, src1, tmpI);
8448 %}
8449 %}
8450
8451 // Register Shift Left Immediate
8452 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8453 match(Set dst (LShiftL src1 src2));
8454 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8455 size(4);
8456 ins_encode %{
8457 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8458 %}
8459 ins_pipe(pipe_class_default);
8460 %}
8461
8462 // If we shift more than 32 bits, we need not convert I2L.
8463 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8464 match(Set dst (LShiftL (ConvI2L src1) src2));
8465 ins_cost(DEFAULT_COST);
8466
8467 size(4);
8468 format %{ "SLDI $dst, i2l($src1), $src2" %}
8469 ins_encode %{
8470 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8471 %}
8472 ins_pipe(pipe_class_default);
8473 %}
8474
8475 // Shift a postivie int to the left.
8476 // Clrlsldi clears the upper 32 bits and shifts.
8477 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8478 match(Set dst (LShiftL (ConvI2L src1) src2));
8479 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8480
8481 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8482 size(4);
8483 ins_encode %{
8484 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8485 %}
8486 ins_pipe(pipe_class_default);
8487 %}
8488
8489 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8490 // no match-rule, false predicate
8491 effect(DEF dst, USE src1, USE src2);
8492 predicate(false);
8493
8494 format %{ "SRAW $dst, $src1, $src2" %}
8495 size(4);
8496 ins_encode %{
8497 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8498 %}
8499 ins_pipe(pipe_class_default);
8500 %}
8501
8502 // Register Arithmetic Shift Right
8503 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8504 match(Set dst (RShiftI src1 src2));
8505 ins_cost(DEFAULT_COST*2);
8506 expand %{
8507 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8508 iRegIdst tmpI;
8509 maskI_reg_imm(tmpI, src2, mask);
8510 arShiftI_reg_reg(dst, src1, tmpI);
8511 %}
8512 %}
8513
8514 // Register Arithmetic Shift Right Immediate
8515 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8516 match(Set dst (RShiftI src1 src2));
8517
8518 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8519 size(4);
8520 ins_encode %{
8521 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8522 %}
8523 ins_pipe(pipe_class_default);
8524 %}
8525
8526 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8527 // no match-rule, false predicate
8528 effect(DEF dst, USE src1, USE src2);
8529 predicate(false);
8530
8531 format %{ "SRAD $dst, $src1, $src2" %}
8532 size(4);
8533 ins_encode %{
8534 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8535 %}
8536 ins_pipe(pipe_class_default);
8537 %}
8538
8539 // Register Shift Right Arithmetic Long
8540 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8541 match(Set dst (RShiftL src1 src2));
8542 ins_cost(DEFAULT_COST*2);
8543
8544 expand %{
8545 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8546 iRegIdst tmpI;
8547 maskI_reg_imm(tmpI, src2, mask);
8548 arShiftL_regL_regI(dst, src1, tmpI);
8549 %}
8550 %}
8551
8552 // Register Shift Right Immediate
8553 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8554 match(Set dst (RShiftL src1 src2));
8555
8556 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8557 size(4);
8558 ins_encode %{
8559 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8560 %}
8561 ins_pipe(pipe_class_default);
8562 %}
8563
8564 // RShiftL + ConvL2I
8565 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8566 match(Set dst (ConvL2I (RShiftL src1 src2)));
8567
8568 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8569 size(4);
8570 ins_encode %{
8571 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8572 %}
8573 ins_pipe(pipe_class_default);
8574 %}
8575
8576 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8577 // no match-rule, false predicate
8578 effect(DEF dst, USE src1, USE src2);
8579 predicate(false);
8580
8581 format %{ "SRW $dst, $src1, $src2" %}
8582 size(4);
8583 ins_encode %{
8584 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8585 %}
8586 ins_pipe(pipe_class_default);
8587 %}
8588
8589 // Register Shift Right
8590 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8591 match(Set dst (URShiftI src1 src2));
8592 ins_cost(DEFAULT_COST*2);
8593
8594 expand %{
8595 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8596 iRegIdst tmpI;
8597 maskI_reg_imm(tmpI, src2, mask);
8598 urShiftI_reg_reg(dst, src1, tmpI);
8599 %}
8600 %}
8601
8602 // Register Shift Right Immediate
8603 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8604 match(Set dst (URShiftI src1 src2));
8605
8606 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8607 size(4);
8608 ins_encode %{
8609 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8610 %}
8611 ins_pipe(pipe_class_default);
8612 %}
8613
8614 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8615 // no match-rule, false predicate
8616 effect(DEF dst, USE src1, USE src2);
8617 predicate(false);
8618
8619 format %{ "SRD $dst, $src1, $src2" %}
8620 size(4);
8621 ins_encode %{
8622 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8623 %}
8624 ins_pipe(pipe_class_default);
8625 %}
8626
8627 // Register Shift Right
8628 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8629 match(Set dst (URShiftL src1 src2));
8630 ins_cost(DEFAULT_COST*2);
8631
8632 expand %{
8633 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8634 iRegIdst tmpI;
8635 maskI_reg_imm(tmpI, src2, mask);
8636 urShiftL_regL_regI(dst, src1, tmpI);
8637 %}
8638 %}
8639
8640 // Register Shift Right Immediate
8641 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8642 match(Set dst (URShiftL src1 src2));
8643
8644 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8645 size(4);
8646 ins_encode %{
8647 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8648 %}
8649 ins_pipe(pipe_class_default);
8650 %}
8651
8652 // URShiftL + ConvL2I.
8653 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8654 match(Set dst (ConvL2I (URShiftL src1 src2)));
8655
8656 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8657 size(4);
8658 ins_encode %{
8659 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8660 %}
8661 ins_pipe(pipe_class_default);
8662 %}
8663
8664 // Register Shift Right Immediate with a CastP2X
8665 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8666 match(Set dst (URShiftL (CastP2X src1) src2));
8667
8668 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8669 size(4);
8670 ins_encode %{
8671 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8672 %}
8673 ins_pipe(pipe_class_default);
8674 %}
8675
8676 // Bitfield Extract: URShiftI + AndI
8677 instruct andI_urShiftI_regI_immI_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immI src2, immIpow2minus1 src3) %{
8678 match(Set dst (AndI (URShiftI src1 src2) src3));
8679
8680 format %{ "EXTRDI $dst, $src1, shift=$src2, mask=$src3 \t// int bitfield extract" %}
8681 size(4);
8682 ins_encode %{
8683 int rshift = ($src2$$constant) & 0x1f;
8684 int length = log2i_exact((juint)$src3$$constant + 1u);
8685 if (rshift + length > 32) {
8686 // if necessary, adjust mask to omit rotated bits.
8687 length = 32 - rshift;
8688 }
8689 __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
8690 %}
8691 ins_pipe(pipe_class_default);
8692 %}
8693
8694 // Bitfield Extract: URShiftL + AndL
8695 instruct andL_urShiftL_regL_immI_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immI src2, immLpow2minus1 src3) %{
8696 match(Set dst (AndL (URShiftL src1 src2) src3));
8697
8698 format %{ "EXTRDI $dst, $src1, shift=$src2, mask=$src3 \t// long bitfield extract" %}
8699 size(4);
8700 ins_encode %{
8701 int rshift = ($src2$$constant) & 0x3f;
8702 int length = log2i_exact((julong)$src3$$constant + 1ull);
8703 if (rshift + length > 64) {
8704 // if necessary, adjust mask to omit rotated bits.
8705 length = 64 - rshift;
8706 }
8707 __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
8708 %}
8709 ins_pipe(pipe_class_default);
8710 %}
8711
8712 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8713 match(Set dst (ConvL2I (ConvI2L src)));
8714
8715 format %{ "EXTSW $dst, $src \t// int->int" %}
8716 size(4);
8717 ins_encode %{
8718 __ extsw($dst$$Register, $src$$Register);
8719 %}
8720 ins_pipe(pipe_class_default);
8721 %}
8722
8723 //----------Rotate Instructions------------------------------------------------
8724
8725 // Rotate Left by 8-bit immediate
8726 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8727 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8728 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8729
8730 format %{ "ROTLWI $dst, $src, $lshift" %}
8731 size(4);
8732 ins_encode %{
8733 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8734 %}
8735 ins_pipe(pipe_class_default);
8736 %}
8737
8738 // Rotate Right by 8-bit immediate
8739 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8740 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8741 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8742
8743 format %{ "ROTRWI $dst, $rshift" %}
8744 size(4);
8745 ins_encode %{
8746 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8747 %}
8748 ins_pipe(pipe_class_default);
8749 %}
8750
8751 //----------Floating Point Arithmetic Instructions-----------------------------
8752
8753 // Add float single precision
8754 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8755 match(Set dst (AddF src1 src2));
8756
8757 format %{ "FADDS $dst, $src1, $src2" %}
8758 size(4);
8759 ins_encode %{
8760 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8761 %}
8762 ins_pipe(pipe_class_default);
8763 %}
8764
8765 // Add float double precision
8766 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8767 match(Set dst (AddD src1 src2));
8768
8769 format %{ "FADD $dst, $src1, $src2" %}
8770 size(4);
8771 ins_encode %{
8772 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8773 %}
8774 ins_pipe(pipe_class_default);
8775 %}
8776
8777 // Sub float single precision
8778 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8779 match(Set dst (SubF src1 src2));
8780
8781 format %{ "FSUBS $dst, $src1, $src2" %}
8782 size(4);
8783 ins_encode %{
8784 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8785 %}
8786 ins_pipe(pipe_class_default);
8787 %}
8788
8789 // Sub float double precision
8790 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8791 match(Set dst (SubD src1 src2));
8792 format %{ "FSUB $dst, $src1, $src2" %}
8793 size(4);
8794 ins_encode %{
8795 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8796 %}
8797 ins_pipe(pipe_class_default);
8798 %}
8799
8800 // Mul float single precision
8801 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8802 match(Set dst (MulF src1 src2));
8803 format %{ "FMULS $dst, $src1, $src2" %}
8804 size(4);
8805 ins_encode %{
8806 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8807 %}
8808 ins_pipe(pipe_class_default);
8809 %}
8810
8811 // Mul float double precision
8812 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8813 match(Set dst (MulD src1 src2));
8814 format %{ "FMUL $dst, $src1, $src2" %}
8815 size(4);
8816 ins_encode %{
8817 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8818 %}
8819 ins_pipe(pipe_class_default);
8820 %}
8821
8822 // Div float single precision
8823 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8824 match(Set dst (DivF src1 src2));
8825 format %{ "FDIVS $dst, $src1, $src2" %}
8826 size(4);
8827 ins_encode %{
8828 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8829 %}
8830 ins_pipe(pipe_class_default);
8831 %}
8832
8833 // Div float double precision
8834 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8835 match(Set dst (DivD src1 src2));
8836 format %{ "FDIV $dst, $src1, $src2" %}
8837 size(4);
8838 ins_encode %{
8839 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8840 %}
8841 ins_pipe(pipe_class_default);
8842 %}
8843
8844 // Absolute float single precision
8845 instruct absF_reg(regF dst, regF src) %{
8846 match(Set dst (AbsF src));
8847 format %{ "FABS $dst, $src \t// float" %}
8848 size(4);
8849 ins_encode %{
8850 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8851 %}
8852 ins_pipe(pipe_class_default);
8853 %}
8854
8855 // Absolute float double precision
8856 instruct absD_reg(regD dst, regD src) %{
8857 match(Set dst (AbsD src));
8858 format %{ "FABS $dst, $src \t// double" %}
8859 size(4);
8860 ins_encode %{
8861 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8862 %}
8863 ins_pipe(pipe_class_default);
8864 %}
8865
8866 instruct negF_reg(regF dst, regF src) %{
8867 match(Set dst (NegF src));
8868 format %{ "FNEG $dst, $src \t// float" %}
8869 size(4);
8870 ins_encode %{
8871 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8872 %}
8873 ins_pipe(pipe_class_default);
8874 %}
8875
8876 instruct negD_reg(regD dst, regD src) %{
8877 match(Set dst (NegD src));
8878 format %{ "FNEG $dst, $src \t// double" %}
8879 size(4);
8880 ins_encode %{
8881 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8882 %}
8883 ins_pipe(pipe_class_default);
8884 %}
8885
8886 // AbsF + NegF.
8887 instruct negF_absF_reg(regF dst, regF src) %{
8888 match(Set dst (NegF (AbsF src)));
8889 format %{ "FNABS $dst, $src \t// float" %}
8890 size(4);
8891 ins_encode %{
8892 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8893 %}
8894 ins_pipe(pipe_class_default);
8895 %}
8896
8897 // AbsD + NegD.
8898 instruct negD_absD_reg(regD dst, regD src) %{
8899 match(Set dst (NegD (AbsD src)));
8900 format %{ "FNABS $dst, $src \t// double" %}
8901 size(4);
8902 ins_encode %{
8903 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8904 %}
8905 ins_pipe(pipe_class_default);
8906 %}
8907
8908 // Sqrt float double precision
8909 instruct sqrtD_reg(regD dst, regD src) %{
8910 match(Set dst (SqrtD src));
8911 format %{ "FSQRT $dst, $src" %}
8912 size(4);
8913 ins_encode %{
8914 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8915 %}
8916 ins_pipe(pipe_class_default);
8917 %}
8918
8919 // Single-precision sqrt.
8920 instruct sqrtF_reg(regF dst, regF src) %{
8921 match(Set dst (SqrtF src));
8922 ins_cost(DEFAULT_COST);
8923
8924 format %{ "FSQRTS $dst, $src" %}
8925 size(4);
8926 ins_encode %{
8927 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8928 %}
8929 ins_pipe(pipe_class_default);
8930 %}
8931
8932
8933 // Multiply-Accumulate
8934 // src1 * src2 + src3
8935 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
8936 match(Set dst (FmaF src3 (Binary src1 src2)));
8937
8938 format %{ "FMADDS $dst, $src1, $src2, $src3" %}
8939 size(4);
8940 ins_encode %{
8941 assert(UseFMA, "Needs FMA instructions support.");
8942 __ fmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8943 %}
8944 ins_pipe(pipe_class_default);
8945 %}
8946
8947 // src1 * src2 + src3
8948 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
8949 match(Set dst (FmaD src3 (Binary src1 src2)));
8950
8951 format %{ "FMADD $dst, $src1, $src2, $src3" %}
8952 size(4);
8953 ins_encode %{
8954 assert(UseFMA, "Needs FMA instructions support.");
8955 __ fmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8956 %}
8957 ins_pipe(pipe_class_default);
8958 %}
8959
8960 // src1 * (-src2) + src3 = -(src1*src2-src3)
8961 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
8962 instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
8963 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
8964
8965 format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
8966 size(4);
8967 ins_encode %{
8968 assert(UseFMA, "Needs FMA instructions support.");
8969 __ fnmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8970 %}
8971 ins_pipe(pipe_class_default);
8972 %}
8973
8974 // src1 * (-src2) + src3 = -(src1*src2-src3)
8975 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
8976 instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
8977 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
8978
8979 format %{ "FNMSUB $dst, $src1, $src2, $src3" %}
8980 size(4);
8981 ins_encode %{
8982 assert(UseFMA, "Needs FMA instructions support.");
8983 __ fnmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8984 %}
8985 ins_pipe(pipe_class_default);
8986 %}
8987
8988 // src1 * (-src2) - src3 = -(src1*src2+src3)
8989 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
8990 instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
8991 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
8992
8993 format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
8994 size(4);
8995 ins_encode %{
8996 assert(UseFMA, "Needs FMA instructions support.");
8997 __ fnmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8998 %}
8999 ins_pipe(pipe_class_default);
9000 %}
9001
9002 // src1 * (-src2) - src3 = -(src1*src2+src3)
9003 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
9004 instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9005 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
9006
9007 format %{ "FNMADD $dst, $src1, $src2, $src3" %}
9008 size(4);
9009 ins_encode %{
9010 assert(UseFMA, "Needs FMA instructions support.");
9011 __ fnmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9012 %}
9013 ins_pipe(pipe_class_default);
9014 %}
9015
9016 // src1 * src2 - src3
9017 instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9018 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
9019
9020 format %{ "FMSUBS $dst, $src1, $src2, $src3" %}
9021 size(4);
9022 ins_encode %{
9023 assert(UseFMA, "Needs FMA instructions support.");
9024 __ fmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9025 %}
9026 ins_pipe(pipe_class_default);
9027 %}
9028
9029 // src1 * src2 - src3
9030 instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9031 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
9032
9033 format %{ "FMSUB $dst, $src1, $src2, $src3" %}
9034 size(4);
9035 ins_encode %{
9036 assert(UseFMA, "Needs FMA instructions support.");
9037 __ fmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9038 %}
9039 ins_pipe(pipe_class_default);
9040 %}
9041
9042
9043 //----------Logical Instructions-----------------------------------------------
9044
9045 // And Instructions
9046
9047 // Register And
9048 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9049 match(Set dst (AndI src1 src2));
9050 format %{ "AND $dst, $src1, $src2" %}
9051 size(4);
9052 ins_encode %{
9053 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9054 %}
9055 ins_pipe(pipe_class_default);
9056 %}
9057
9058 instruct andI_reg_immI(iRegIdst dst, iRegIsrc src1, immI src2, flagsRegCR0 cr0) %{
9059 match(Set dst (AndI src1 src2));
9060 predicate(Assembler::andi_supports((juint)(n->in(2)->get_int())));
9061 effect(KILL cr0);
9062 format %{ "ANDI $dst, $src1, $src2" %}
9063 size(4);
9064 ins_encode %{
9065 __ andi($dst$$Register, $src1$$Register, (juint)$src2$$constant); // optimized version
9066 %}
9067 ins_pipe(pipe_class_default);
9068 %}
9069
9070 // Register And Long
9071 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9072 match(Set dst (AndL src1 src2));
9073 ins_cost(DEFAULT_COST);
9074
9075 format %{ "AND $dst, $src1, $src2 \t// long" %}
9076 size(4);
9077 ins_encode %{
9078 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9079 %}
9080 ins_pipe(pipe_class_default);
9081 %}
9082
9083 instruct andL_reg_immL(iRegLdst dst, iRegLsrc src1, immL src2, flagsRegCR0 cr0) %{
9084 match(Set dst (AndL src1 src2));
9085 predicate(Assembler::andi_supports(n->in(2)->get_long()));
9086 effect(KILL cr0);
9087 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
9088 size(4);
9089 ins_encode %{
9090 __ andi($dst$$Register, $src1$$Register, $src2$$constant); // optimized version
9091 %}
9092 ins_pipe(pipe_class_default);
9093 %}
9094
9095 // AndL + ConvL2I.
9096 instruct convL2I_andL_reg_immL(iRegIdst dst, iRegLsrc src1, immL src2, flagsRegCR0 cr0) %{
9097 match(Set dst (ConvL2I (AndL src1 src2)));
9098 predicate(Assembler::andi_supports(n->in(1)->in(2)->get_long()));
9099 effect(KILL cr0);
9100 format %{ "ANDI $dst, $src1, $src2 \t// long + l2i" %}
9101 size(4);
9102 ins_encode %{
9103 __ andi($dst$$Register, $src1$$Register, $src2$$constant); // optimized version
9104 %}
9105 ins_pipe(pipe_class_default);
9106 %}
9107
9108 // Or Instructions
9109
9110 // Register Or
9111 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9112 match(Set dst (OrI src1 src2));
9113 format %{ "OR $dst, $src1, $src2" %}
9114 size(4);
9115 ins_encode %{
9116 __ orr($dst$$Register, $src1$$Register, $src2$$Register);
9117 %}
9118 ins_pipe(pipe_class_default);
9119 %}
9120
9121 // Expand does not work with above instruct. (??)
9122 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9123 // no match-rule
9124 effect(DEF dst, USE src1, USE src2);
9125 format %{ "OR $dst, $src1, $src2" %}
9126 size(4);
9127 ins_encode %{
9128 __ orr($dst$$Register, $src1$$Register, $src2$$Register);
9129 %}
9130 ins_pipe(pipe_class_default);
9131 %}
9132
9133 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9134 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9135 ins_cost(DEFAULT_COST*3);
9136
9137 expand %{
9138 // FIXME: we should do this in the ideal world.
9139 iRegIdst tmp1;
9140 iRegIdst tmp2;
9141 orI_reg_reg(tmp1, src1, src2);
9142 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9143 orI_reg_reg(dst, tmp1, tmp2);
9144 %}
9145 %}
9146
9147 // Immediate Or
9148 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9149 match(Set dst (OrI src1 src2));
9150 format %{ "ORI $dst, $src1, $src2" %}
9151 size(4);
9152 ins_encode %{
9153 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9154 %}
9155 ins_pipe(pipe_class_default);
9156 %}
9157
9158 // Register Or Long
9159 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9160 match(Set dst (OrL src1 src2));
9161 ins_cost(DEFAULT_COST);
9162
9163 size(4);
9164 format %{ "OR $dst, $src1, $src2 \t// long" %}
9165 ins_encode %{
9166 __ orr($dst$$Register, $src1$$Register, $src2$$Register);
9167 %}
9168 ins_pipe(pipe_class_default);
9169 %}
9170
9171 // OrL + ConvL2I.
9172 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9173 match(Set dst (ConvL2I (OrL src1 src2)));
9174 ins_cost(DEFAULT_COST);
9175
9176 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9177 size(4);
9178 ins_encode %{
9179 __ orr($dst$$Register, $src1$$Register, $src2$$Register);
9180 %}
9181 ins_pipe(pipe_class_default);
9182 %}
9183
9184 // Immediate Or long
9185 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9186 match(Set dst (OrL src1 con));
9187 ins_cost(DEFAULT_COST);
9188
9189 format %{ "ORI $dst, $src1, $con \t// long" %}
9190 size(4);
9191 ins_encode %{
9192 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9193 %}
9194 ins_pipe(pipe_class_default);
9195 %}
9196
9197 // Xor Instructions
9198
9199 // Register Xor
9200 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9201 match(Set dst (XorI src1 src2));
9202 format %{ "XOR $dst, $src1, $src2" %}
9203 size(4);
9204 ins_encode %{
9205 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9206 %}
9207 ins_pipe(pipe_class_default);
9208 %}
9209
9210 // Expand does not work with above instruct. (??)
9211 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9212 // no match-rule
9213 effect(DEF dst, USE src1, USE src2);
9214 format %{ "XOR $dst, $src1, $src2" %}
9215 size(4);
9216 ins_encode %{
9217 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9218 %}
9219 ins_pipe(pipe_class_default);
9220 %}
9221
9222 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9223 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9224 ins_cost(DEFAULT_COST*3);
9225
9226 expand %{
9227 // FIXME: we should do this in the ideal world.
9228 iRegIdst tmp1;
9229 iRegIdst tmp2;
9230 xorI_reg_reg(tmp1, src1, src2);
9231 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9232 xorI_reg_reg(dst, tmp1, tmp2);
9233 %}
9234 %}
9235
9236 // Immediate Xor
9237 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9238 match(Set dst (XorI src1 src2));
9239 format %{ "XORI $dst, $src1, $src2" %}
9240 size(4);
9241 ins_encode %{
9242 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9243 %}
9244 ins_pipe(pipe_class_default);
9245 %}
9246
9247 // Register Xor Long
9248 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9249 match(Set dst (XorL src1 src2));
9250 ins_cost(DEFAULT_COST);
9251
9252 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9253 size(4);
9254 ins_encode %{
9255 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9256 %}
9257 ins_pipe(pipe_class_default);
9258 %}
9259
9260 // XorL + ConvL2I.
9261 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9262 match(Set dst (ConvL2I (XorL src1 src2)));
9263 ins_cost(DEFAULT_COST);
9264
9265 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9266 size(4);
9267 ins_encode %{
9268 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9269 %}
9270 ins_pipe(pipe_class_default);
9271 %}
9272
9273 // Immediate Xor Long
9274 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9275 match(Set dst (XorL src1 src2));
9276 ins_cost(DEFAULT_COST);
9277
9278 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9279 size(4);
9280 ins_encode %{
9281 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9282 %}
9283 ins_pipe(pipe_class_default);
9284 %}
9285
9286 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9287 match(Set dst (XorI src1 src2));
9288 ins_cost(DEFAULT_COST);
9289
9290 format %{ "NOT $dst, $src1 ($src2)" %}
9291 size(4);
9292 ins_encode %{
9293 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9294 %}
9295 ins_pipe(pipe_class_default);
9296 %}
9297
9298 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9299 match(Set dst (XorL src1 src2));
9300 ins_cost(DEFAULT_COST);
9301
9302 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9303 size(4);
9304 ins_encode %{
9305 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9306 %}
9307 ins_pipe(pipe_class_default);
9308 %}
9309
9310 // And-complement
9311 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9312 match(Set dst (AndI (XorI src1 src2) src3));
9313 ins_cost(DEFAULT_COST);
9314
9315 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9316 size(4);
9317 ins_encode( enc_andc(dst, src3, src1) );
9318 ins_pipe(pipe_class_default);
9319 %}
9320
9321 // And-complement
9322 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9323 // no match-rule, false predicate
9324 effect(DEF dst, USE src1, USE src2);
9325 predicate(false);
9326
9327 format %{ "ANDC $dst, $src1, $src2" %}
9328 size(4);
9329 ins_encode %{
9330 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9331 %}
9332 ins_pipe(pipe_class_default);
9333 %}
9334
9335 //----------Moves between int/long and float/double----------------------------
9336 //
9337 // The following rules move values from int/long registers/stack-locations
9338 // to float/double registers/stack-locations and vice versa, without doing any
9339 // conversions. These rules are used to implement the bit-conversion methods
9340 // of java.lang.Float etc., e.g.
9341 // int floatToIntBits(float value)
9342 // float intBitsToFloat(int bits)
9343
9344 instruct moveL2D_reg(regD dst, iRegLsrc src) %{
9345 match(Set dst (MoveL2D src));
9346
9347 format %{ "MTFPRD $dst, $src" %}
9348 size(4);
9349 ins_encode %{
9350 __ mtfprd($dst$$FloatRegister, $src$$Register);
9351 %}
9352 ins_pipe(pipe_class_default);
9353 %}
9354
9355 instruct moveI2D_reg(regD dst, iRegIsrc src) %{
9356 // no match-rule, false predicate
9357 effect(DEF dst, USE src);
9358 predicate(false);
9359
9360 format %{ "MTFPRWA $dst, $src" %}
9361 size(4);
9362 ins_encode %{
9363 __ mtfprwa($dst$$FloatRegister, $src$$Register);
9364 %}
9365 ins_pipe(pipe_class_default);
9366 %}
9367
9368 //---------- Chain stack slots between similar types --------
9369
9370 // These are needed so that the rules below can match.
9371
9372 // Load integer from stack slot
9373 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9374 match(Set dst src);
9375 ins_cost(MEMORY_REF_COST);
9376
9377 format %{ "LWZ $dst, $src" %}
9378 size(4);
9379 ins_encode( enc_lwz(dst, src) );
9380 ins_pipe(pipe_class_memory);
9381 %}
9382
9383 // Store integer to stack slot
9384 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9385 match(Set dst src);
9386 ins_cost(MEMORY_REF_COST);
9387
9388 format %{ "STW $src, $dst \t// stk" %}
9389 size(4);
9390 ins_encode( enc_stw(src, dst) ); // rs=rt
9391 ins_pipe(pipe_class_memory);
9392 %}
9393
9394 // Load long from stack slot
9395 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9396 match(Set dst src);
9397 ins_cost(MEMORY_REF_COST);
9398
9399 format %{ "LD $dst, $src \t// long" %}
9400 size(4);
9401 ins_encode( enc_ld(dst, src) );
9402 ins_pipe(pipe_class_memory);
9403 %}
9404
9405 // Store long to stack slot
9406 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9407 match(Set dst src);
9408 ins_cost(MEMORY_REF_COST);
9409
9410 format %{ "STD $src, $dst \t// long" %}
9411 size(4);
9412 ins_encode( enc_std(src, dst) ); // rs=rt
9413 ins_pipe(pipe_class_memory);
9414 %}
9415
9416 //----------Moves between int and float
9417
9418 // Move float value from float stack-location to integer register.
9419 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9420 match(Set dst (MoveF2I src));
9421 ins_cost(MEMORY_REF_COST);
9422
9423 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9424 size(4);
9425 ins_encode( enc_lwz(dst, src) );
9426 ins_pipe(pipe_class_memory);
9427 %}
9428
9429 // Move float value from float register to integer stack-location.
9430 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9431 match(Set dst (MoveF2I src));
9432 ins_cost(MEMORY_REF_COST);
9433
9434 format %{ "STFS $src, $dst \t// MoveF2I" %}
9435 size(4);
9436 ins_encode( enc_stfs(src, dst) );
9437 ins_pipe(pipe_class_memory);
9438 %}
9439
9440 // Move integer value from integer stack-location to float register.
9441 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9442 match(Set dst (MoveI2F src));
9443 ins_cost(MEMORY_REF_COST);
9444
9445 format %{ "LFS $dst, $src \t// MoveI2F" %}
9446 size(4);
9447 ins_encode %{
9448 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9449 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9450 %}
9451 ins_pipe(pipe_class_memory);
9452 %}
9453
9454 // Move integer value from integer register to float stack-location.
9455 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9456 match(Set dst (MoveI2F src));
9457 ins_cost(MEMORY_REF_COST);
9458
9459 format %{ "STW $src, $dst \t// MoveI2F" %}
9460 size(4);
9461 ins_encode( enc_stw(src, dst) );
9462 ins_pipe(pipe_class_memory);
9463 %}
9464
9465
9466 //----------Moves between long and double
9467
9468 // Move double value from double stack-location to long register.
9469 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9470 match(Set dst (MoveD2L src));
9471 ins_cost(MEMORY_REF_COST);
9472 size(4);
9473 format %{ "LD $dst, $src \t// MoveD2L" %}
9474 ins_encode( enc_ld(dst, src) );
9475 ins_pipe(pipe_class_memory);
9476 %}
9477
9478 // Move double value from double register to long stack-location.
9479 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9480 match(Set dst (MoveD2L src));
9481 effect(DEF dst, USE src);
9482 ins_cost(MEMORY_REF_COST);
9483
9484 format %{ "STFD $src, $dst \t// MoveD2L" %}
9485 size(4);
9486 ins_encode( enc_stfd(src, dst) );
9487 ins_pipe(pipe_class_memory);
9488 %}
9489
9490
9491 //----------Register Move Instructions-----------------------------------------
9492
9493 // Replicate for Superword
9494
9495 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9496 predicate(false);
9497 effect(DEF dst, USE src);
9498
9499 format %{ "MR $dst, $src \t// replicate " %}
9500 // variable size, 0 or 4.
9501 ins_encode %{
9502 __ mr_if_needed($dst$$Register, $src$$Register);
9503 %}
9504 ins_pipe(pipe_class_default);
9505 %}
9506
9507 //----------Cast instructions (Java-level type cast)---------------------------
9508
9509 // Cast Long to Pointer for unsafe natives.
9510 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9511 match(Set dst (CastX2P src));
9512
9513 format %{ "MR $dst, $src \t// Long->Ptr" %}
9514 // variable size, 0 or 4.
9515 ins_encode %{
9516 __ mr_if_needed($dst$$Register, $src$$Register);
9517 %}
9518 ins_pipe(pipe_class_default);
9519 %}
9520
9521 // Cast Pointer to Long for unsafe natives.
9522 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9523 match(Set dst (CastP2X src));
9524
9525 format %{ "MR $dst, $src \t// Ptr->Long" %}
9526 // variable size, 0 or 4.
9527 ins_encode %{
9528 __ mr_if_needed($dst$$Register, $src$$Register);
9529 %}
9530 ins_pipe(pipe_class_default);
9531 %}
9532
9533 instruct castN2X(iRegLdst dst, iRegNsrc src) %{
9534 match(Set dst (CastP2X src));
9535
9536 format %{ "MR $dst, $src \t// Ptr->Long" %}
9537 // variable size, 0 or 4.
9538 ins_encode %{
9539 __ mr_if_needed($dst$$Register, $src$$Register);
9540 %}
9541 ins_pipe(pipe_class_default);
9542 %}
9543
9544 instruct castPP(iRegPdst dst) %{
9545 match(Set dst (CastPP dst));
9546 format %{ " -- \t// castPP of $dst" %}
9547 size(0);
9548 ins_encode( /*empty*/ );
9549 ins_pipe(pipe_class_default);
9550 %}
9551
9552 instruct castII(iRegIdst dst) %{
9553 match(Set dst (CastII dst));
9554 format %{ " -- \t// castII of $dst" %}
9555 size(0);
9556 ins_encode( /*empty*/ );
9557 ins_pipe(pipe_class_default);
9558 %}
9559
9560 instruct castLL(iRegLdst dst) %{
9561 match(Set dst (CastLL dst));
9562 format %{ " -- \t// castLL of $dst" %}
9563 size(0);
9564 ins_encode( /*empty*/ );
9565 ins_pipe(pipe_class_default);
9566 %}
9567
9568 instruct castFF(regF dst) %{
9569 match(Set dst (CastFF dst));
9570 format %{ " -- \t// castFF of $dst" %}
9571 size(0);
9572 ins_encode( /*empty*/ );
9573 ins_pipe(pipe_class_default);
9574 %}
9575
9576 instruct castDD(regD dst) %{
9577 match(Set dst (CastDD dst));
9578 format %{ " -- \t// castDD of $dst" %}
9579 size(0);
9580 ins_encode( /*empty*/ );
9581 ins_pipe(pipe_class_default);
9582 %}
9583
9584 instruct castVV8(iRegLdst dst) %{
9585 match(Set dst (CastVV dst));
9586 format %{ " -- \t// castVV of $dst" %}
9587 size(0);
9588 ins_encode( /*empty*/ );
9589 ins_pipe(pipe_class_default);
9590 %}
9591
9592 instruct castVV16(vecX dst) %{
9593 match(Set dst (CastVV dst));
9594 format %{ " -- \t// castVV of $dst" %}
9595 size(0);
9596 ins_encode( /*empty*/ );
9597 ins_pipe(pipe_class_default);
9598 %}
9599
9600 instruct checkCastPP(iRegPdst dst) %{
9601 match(Set dst (CheckCastPP dst));
9602 format %{ " -- \t// checkcastPP of $dst" %}
9603 size(0);
9604 ins_encode( /*empty*/ );
9605 ins_pipe(pipe_class_default);
9606 %}
9607
9608 //----------Convert instructions-----------------------------------------------
9609
9610 // Convert to boolean.
9611
9612 // int_to_bool(src) : { 1 if src != 0
9613 // { 0 else
9614 //
9615 // strategy:
9616 // 1) Count leading zeros of 32 bit-value src,
9617 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9618 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9619 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9620
9621 // convI2Bool
9622 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9623 match(Set dst (Conv2B src));
9624 predicate(UseCountLeadingZerosInstructionsPPC64);
9625 ins_cost(DEFAULT_COST);
9626
9627 expand %{
9628 immI shiftAmount %{ 0x5 %}
9629 uimmI16 mask %{ 0x1 %}
9630 iRegIdst tmp1;
9631 iRegIdst tmp2;
9632 countLeadingZerosI(tmp1, src);
9633 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9634 xorI_reg_uimm16(dst, tmp2, mask);
9635 %}
9636 %}
9637
9638 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9639 match(Set dst (Conv2B src));
9640 effect(TEMP crx);
9641 predicate(!UseCountLeadingZerosInstructionsPPC64);
9642 ins_cost(DEFAULT_COST);
9643
9644 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9645 "LI $dst, #0\n\t"
9646 "BEQ $crx, done\n\t"
9647 "LI $dst, #1\n"
9648 "done:" %}
9649 size(16);
9650 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9651 ins_pipe(pipe_class_compare);
9652 %}
9653
9654 // ConvI2B + XorI
9655 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9656 match(Set dst (XorI (Conv2B src) mask));
9657 predicate(UseCountLeadingZerosInstructionsPPC64);
9658 ins_cost(DEFAULT_COST);
9659
9660 expand %{
9661 immI shiftAmount %{ 0x5 %}
9662 iRegIdst tmp1;
9663 countLeadingZerosI(tmp1, src);
9664 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9665 %}
9666 %}
9667
9668 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9669 match(Set dst (XorI (Conv2B src) mask));
9670 effect(TEMP crx);
9671 predicate(!UseCountLeadingZerosInstructionsPPC64);
9672 ins_cost(DEFAULT_COST);
9673
9674 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9675 "LI $dst, #1\n\t"
9676 "BEQ $crx, done\n\t"
9677 "LI $dst, #0\n"
9678 "done:" %}
9679 size(16);
9680 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9681 ins_pipe(pipe_class_compare);
9682 %}
9683
9684 // AndI 0b0..010..0 + ConvI2B
9685 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9686 match(Set dst (Conv2B (AndI src mask)));
9687 predicate(UseRotateAndMaskInstructionsPPC64);
9688 ins_cost(DEFAULT_COST);
9689
9690 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9691 size(4);
9692 ins_encode %{
9693 __ rlwinm($dst$$Register, $src$$Register, 32 - log2i_exact((juint)($mask$$constant)), 31, 31);
9694 %}
9695 ins_pipe(pipe_class_default);
9696 %}
9697
9698 // Convert pointer to boolean.
9699 //
9700 // ptr_to_bool(src) : { 1 if src != 0
9701 // { 0 else
9702 //
9703 // strategy:
9704 // 1) Count leading zeros of 64 bit-value src,
9705 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9706 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9707 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9708
9709 // ConvP2B
9710 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9711 match(Set dst (Conv2B src));
9712 predicate(UseCountLeadingZerosInstructionsPPC64);
9713 ins_cost(DEFAULT_COST);
9714
9715 expand %{
9716 immI shiftAmount %{ 0x6 %}
9717 uimmI16 mask %{ 0x1 %}
9718 iRegIdst tmp1;
9719 iRegIdst tmp2;
9720 countLeadingZerosP(tmp1, src);
9721 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9722 xorI_reg_uimm16(dst, tmp2, mask);
9723 %}
9724 %}
9725
9726 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9727 match(Set dst (Conv2B src));
9728 effect(TEMP crx);
9729 predicate(!UseCountLeadingZerosInstructionsPPC64);
9730 ins_cost(DEFAULT_COST);
9731
9732 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9733 "LI $dst, #0\n\t"
9734 "BEQ $crx, done\n\t"
9735 "LI $dst, #1\n"
9736 "done:" %}
9737 size(16);
9738 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9739 ins_pipe(pipe_class_compare);
9740 %}
9741
9742 // ConvP2B + XorI
9743 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9744 match(Set dst (XorI (Conv2B src) mask));
9745 predicate(UseCountLeadingZerosInstructionsPPC64);
9746 ins_cost(DEFAULT_COST);
9747
9748 expand %{
9749 immI shiftAmount %{ 0x6 %}
9750 iRegIdst tmp1;
9751 countLeadingZerosP(tmp1, src);
9752 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9753 %}
9754 %}
9755
9756 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9757 match(Set dst (XorI (Conv2B src) mask));
9758 effect(TEMP crx);
9759 predicate(!UseCountLeadingZerosInstructionsPPC64);
9760 ins_cost(DEFAULT_COST);
9761
9762 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9763 "LI $dst, #1\n\t"
9764 "BEQ $crx, done\n\t"
9765 "LI $dst, #0\n"
9766 "done:" %}
9767 size(16);
9768 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9769 ins_pipe(pipe_class_compare);
9770 %}
9771
9772 // if src1 < src2, return -1 else return 0
9773 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9774 match(Set dst (CmpLTMask src1 src2));
9775 ins_cost(DEFAULT_COST*4);
9776
9777 expand %{
9778 iRegLdst src1s;
9779 iRegLdst src2s;
9780 iRegLdst diff;
9781 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9782 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9783 subL_reg_reg(diff, src1s, src2s);
9784 // Need to consider >=33 bit result, therefore we need signmaskL.
9785 signmask64I_regL(dst, diff);
9786 %}
9787 %}
9788
9789 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9790 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9791 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9792 size(4);
9793 ins_encode %{
9794 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9795 %}
9796 ins_pipe(pipe_class_default);
9797 %}
9798
9799 //----------Arithmetic Conversion Instructions---------------------------------
9800
9801 // Convert to Byte -- nop
9802 // Convert to Short -- nop
9803
9804 // Convert to Int
9805
9806 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9807 match(Set dst (RShiftI (LShiftI src amount) amount));
9808 format %{ "EXTSB $dst, $src \t// byte->int" %}
9809 size(4);
9810 ins_encode %{
9811 __ extsb($dst$$Register, $src$$Register);
9812 %}
9813 ins_pipe(pipe_class_default);
9814 %}
9815
9816 instruct extsh(iRegIdst dst, iRegIsrc src) %{
9817 effect(DEF dst, USE src);
9818
9819 size(4);
9820 ins_encode %{
9821 __ extsh($dst$$Register, $src$$Register);
9822 %}
9823 ins_pipe(pipe_class_default);
9824 %}
9825
9826 // LShiftI 16 + RShiftI 16 converts short to int.
9827 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9828 match(Set dst (RShiftI (LShiftI src amount) amount));
9829 format %{ "EXTSH $dst, $src \t// short->int" %}
9830 size(4);
9831 ins_encode %{
9832 __ extsh($dst$$Register, $src$$Register);
9833 %}
9834 ins_pipe(pipe_class_default);
9835 %}
9836
9837 // ConvL2I + ConvI2L: Sign extend int in long register.
9838 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9839 match(Set dst (ConvI2L (ConvL2I src)));
9840
9841 format %{ "EXTSW $dst, $src \t// long->long" %}
9842 size(4);
9843 ins_encode %{
9844 __ extsw($dst$$Register, $src$$Register);
9845 %}
9846 ins_pipe(pipe_class_default);
9847 %}
9848
9849 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9850 match(Set dst (ConvL2I src));
9851 format %{ "MR $dst, $src \t// long->int" %}
9852 // variable size, 0 or 4
9853 ins_encode %{
9854 __ mr_if_needed($dst$$Register, $src$$Register);
9855 %}
9856 ins_pipe(pipe_class_default);
9857 %}
9858
9859 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9860 // no match-rule, false predicate
9861 effect(DEF dst, USE crx, USE src);
9862 predicate(false);
9863
9864 format %{ "CMOVI $crx, $dst, $src" %}
9865 size(8);
9866 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9867 ins_pipe(pipe_class_default);
9868 %}
9869
9870 instruct cmovI_bso_reg_con0(iRegIdst dst, flagsRegSrc crx, regD src) %{
9871 // no match-rule, false predicate
9872 effect(DEF dst, USE crx, USE src);
9873 predicate(false);
9874
9875 format %{ "CMOVI $dst, $crx, $src, 0 \t// set to 0 if unordered" %}
9876 size(12);
9877 ins_encode %{
9878 Label done;
9879 __ li($dst$$Register, 0);
9880 __ bso($crx$$CondRegister, done);
9881 __ mffprd($dst$$Register, $src$$FloatRegister);
9882 __ bind(done);
9883 %}
9884 ins_pipe(pipe_class_default);
9885 %}
9886
9887 instruct convD2IRaw_regD(regD dst, regD src) %{
9888 // no match-rule, false predicate
9889 effect(DEF dst, USE src);
9890 predicate(false);
9891
9892 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9893 size(4);
9894 ins_encode %{
9895 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9896 %}
9897 ins_pipe(pipe_class_default);
9898 %}
9899
9900 // Double to Int conversion, NaN is mapped to 0. Special version for Power8.
9901 instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
9902 match(Set dst (ConvD2I src));
9903 ins_cost(DEFAULT_COST);
9904
9905 expand %{
9906 regD tmpD;
9907 flagsReg crx;
9908 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9909 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9910 cmovI_bso_reg_con0(dst, crx, tmpD); // Cmove based on NaN check.
9911 %}
9912 %}
9913
9914 instruct convF2IRaw_regF(regF dst, regF src) %{
9915 // no match-rule, false predicate
9916 effect(DEF dst, USE src);
9917 predicate(false);
9918
9919 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9920 size(4);
9921 ins_encode %{
9922 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9923 %}
9924 ins_pipe(pipe_class_default);
9925 %}
9926
9927
9928 // Float to Int conversion, NaN is mapped to 0. Special version for Power8.
9929 instruct convF2I_regF_mffprd_ExEx(iRegIdst dst, regF src) %{
9930 match(Set dst (ConvF2I src));
9931 ins_cost(DEFAULT_COST);
9932
9933 expand %{
9934 regF tmpF;
9935 flagsReg crx;
9936 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9937 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9938 cmovI_bso_reg_con0(dst, crx, tmpF); // Cmove based on NaN check.
9939 %}
9940 %}
9941
9942 // Convert to Long
9943
9944 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9945 match(Set dst (ConvI2L src));
9946 format %{ "EXTSW $dst, $src \t// int->long" %}
9947 size(4);
9948 ins_encode %{
9949 __ extsw($dst$$Register, $src$$Register);
9950 %}
9951 ins_pipe(pipe_class_default);
9952 %}
9953
9954 // Zero-extend: convert unsigned int to long (convUI2L).
9955 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9956 match(Set dst (AndL (ConvI2L src) mask));
9957 ins_cost(DEFAULT_COST);
9958
9959 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9960 size(4);
9961 ins_encode %{
9962 __ clrldi($dst$$Register, $src$$Register, 32);
9963 %}
9964 ins_pipe(pipe_class_default);
9965 %}
9966
9967 // Zero-extend: convert unsigned int to long in long register.
9968 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9969 match(Set dst (AndL src mask));
9970 ins_cost(DEFAULT_COST);
9971
9972 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9973 size(4);
9974 ins_encode %{
9975 __ clrldi($dst$$Register, $src$$Register, 32);
9976 %}
9977 ins_pipe(pipe_class_default);
9978 %}
9979
9980 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9981 // no match-rule, false predicate
9982 effect(DEF dst, USE crx, USE src);
9983 predicate(false);
9984
9985 format %{ "CMOVL $crx, $dst, $src" %}
9986 size(8);
9987 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9988 ins_pipe(pipe_class_default);
9989 %}
9990
9991 instruct cmovL_bso_reg_con0(iRegLdst dst, flagsRegSrc crx, regD src) %{
9992 // no match-rule, false predicate
9993 effect(DEF dst, USE crx, USE src);
9994 predicate(false);
9995
9996 format %{ "CMOVL $dst, $crx, $src, 0 \t// set to 0 if unordered" %}
9997 size(12);
9998 ins_encode %{
9999 Label done;
10000 __ li($dst$$Register, 0);
10001 __ bso($crx$$CondRegister, done);
10002 __ mffprd($dst$$Register, $src$$FloatRegister);
10003 __ bind(done);
10004 %}
10005 ins_pipe(pipe_class_default);
10006 %}
10007
10008 instruct convF2LRaw_regF(regF dst, regF src) %{
10009 // no match-rule, false predicate
10010 effect(DEF dst, USE src);
10011 predicate(false);
10012
10013 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
10014 size(4);
10015 ins_encode %{
10016 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10017 %}
10018 ins_pipe(pipe_class_default);
10019 %}
10020
10021 // Float to Long conversion, NaN is mapped to 0. Special version for Power8.
10022 instruct convF2L_reg_mffprd_ExEx(iRegLdst dst, regF src) %{
10023 match(Set dst (ConvF2L src));
10024 ins_cost(DEFAULT_COST);
10025
10026 expand %{
10027 regF tmpF;
10028 flagsReg crx;
10029 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10030 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
10031 cmovL_bso_reg_con0(dst, crx, tmpF); // Cmove based on NaN check.
10032 %}
10033 %}
10034
10035 instruct convD2LRaw_regD(regD dst, regD src) %{
10036 // no match-rule, false predicate
10037 effect(DEF dst, USE src);
10038 predicate(false);
10039
10040 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10041 size(4);
10042 ins_encode %{
10043 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10044 %}
10045 ins_pipe(pipe_class_default);
10046 %}
10047
10048 // Double to Long conversion, NaN is mapped to 0. Special version for Power8.
10049 instruct convD2L_reg_mffprd_ExEx(iRegLdst dst, regD src) %{
10050 match(Set dst (ConvD2L src));
10051 ins_cost(DEFAULT_COST);
10052
10053 expand %{
10054 regD tmpD;
10055 flagsReg crx;
10056 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10057 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10058 cmovL_bso_reg_con0(dst, crx, tmpD); // Cmove based on NaN check.
10059 %}
10060 %}
10061
10062 // Convert to Float
10063
10064 // Placed here as needed in expand.
10065 instruct convL2DRaw_regD(regD dst, regD src) %{
10066 // no match-rule, false predicate
10067 effect(DEF dst, USE src);
10068 predicate(false);
10069
10070 format %{ "FCFID $dst, $src \t// convL2D" %}
10071 size(4);
10072 ins_encode %{
10073 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10074 %}
10075 ins_pipe(pipe_class_default);
10076 %}
10077
10078 // Placed here as needed in expand.
10079 instruct convD2F_reg(regF dst, regD src) %{
10080 match(Set dst (ConvD2F src));
10081 format %{ "FRSP $dst, $src \t// convD2F" %}
10082 size(4);
10083 ins_encode %{
10084 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10085 %}
10086 ins_pipe(pipe_class_default);
10087 %}
10088
10089 instruct convL2FRaw_regF(regF dst, regD src) %{
10090 // no match-rule, false predicate
10091 effect(DEF dst, USE src);
10092 predicate(false);
10093
10094 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10095 size(4);
10096 ins_encode %{
10097 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10098 %}
10099 ins_pipe(pipe_class_default);
10100 %}
10101
10102
10103 // Integer to Float conversion. Special version for Power8.
10104 instruct convI2F_ireg_mtfprd_Ex(regF dst, iRegIsrc src) %{
10105 match(Set dst (ConvI2F src));
10106 ins_cost(DEFAULT_COST);
10107
10108 expand %{
10109 regD tmpD;
10110 moveI2D_reg(tmpD, src);
10111 convL2FRaw_regF(dst, tmpD); // Convert to float.
10112 %}
10113 %}
10114
10115
10116 // L2F to avoid runtime call. Special version for Power8.
10117 instruct convL2F_ireg_mtfprd_Ex(regF dst, iRegLsrc src) %{
10118 match(Set dst (ConvL2F src));
10119 ins_cost(DEFAULT_COST);
10120
10121 expand %{
10122 regD tmpD;
10123 moveL2D_reg(tmpD, src);
10124 convL2FRaw_regF(dst, tmpD); // Convert to float.
10125 %}
10126 %}
10127
10128 // Moved up as used in expand.
10129 //instruct convD2F_reg(regF dst, regD src) %{%}
10130
10131 // Convert to Double
10132
10133
10134 // Integer to Double conversion. Special version for Power8.
10135 instruct convI2D_reg_mtfprd_Ex(regD dst, iRegIsrc src) %{
10136 match(Set dst (ConvI2D src));
10137 ins_cost(DEFAULT_COST);
10138
10139 expand %{
10140 regD tmpD;
10141 moveI2D_reg(tmpD, src);
10142 convL2DRaw_regD(dst, tmpD); // Convert to double.
10143 %}
10144 %}
10145
10146
10147 // Long to Double conversion. Special version for Power8.
10148 instruct convL2D_reg_mtfprd_Ex(regD dst, iRegLsrc src) %{
10149 match(Set dst (ConvL2D src));
10150 ins_cost(DEFAULT_COST);
10151
10152 expand %{
10153 regD tmpD;
10154 moveL2D_reg(tmpD, src);
10155 convL2DRaw_regD(dst, tmpD); // Convert to double.
10156 %}
10157 %}
10158
10159 instruct convF2D_reg(regD dst, regF src) %{
10160 match(Set dst (ConvF2D src));
10161 format %{ "FMR $dst, $src \t// float->double" %}
10162 // variable size, 0 or 4
10163 ins_encode %{
10164 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10165 %}
10166 ins_pipe(pipe_class_default);
10167 %}
10168
10169 instruct convF2HF_reg_reg(iRegIdst dst, regF src, regF tmp) %{
10170 match(Set dst (ConvF2HF src));
10171 effect(TEMP tmp);
10172 ins_cost(3 * DEFAULT_COST);
10173 size(12);
10174 format %{ "XSCVDPHP $tmp, $src\t# convert to half precision\n\t"
10175 "MFFPRD $dst, $tmp\t# move result from $tmp to $dst\n\t"
10176 "EXTSH $dst, $dst\t# make it a proper short"
10177 %}
10178 ins_encode %{
10179 __ f2hf($dst$$Register, $src$$FloatRegister, $tmp$$FloatRegister);
10180 %}
10181 ins_pipe(pipe_class_default);
10182 %}
10183
10184 instruct convHF2F_reg_reg(regF dst, iRegIsrc src) %{
10185 match(Set dst (ConvHF2F src));
10186 ins_cost(2 * DEFAULT_COST);
10187 size(8);
10188 format %{ "MTFPRD $dst, $src\t# move source from $src to $dst\n\t"
10189 "XSCVHPDP $dst, $dst\t# convert from half precision"
10190 %}
10191 ins_encode %{
10192 __ hf2f($dst$$FloatRegister, $src$$Register);
10193 %}
10194 ins_pipe(pipe_class_default);
10195 %}
10196
10197 //----------Control Flow Instructions------------------------------------------
10198 // Compare Instructions
10199
10200 // Compare Integers
10201 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10202 match(Set crx (CmpI src1 src2));
10203 size(4);
10204 format %{ "CMPW $crx, $src1, $src2" %}
10205 ins_encode %{
10206 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10207 %}
10208 ins_pipe(pipe_class_compare);
10209 %}
10210
10211 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10212 match(Set crx (CmpI src1 src2));
10213 format %{ "CMPWI $crx, $src1, $src2" %}
10214 size(4);
10215 ins_encode %{
10216 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10217 %}
10218 ins_pipe(pipe_class_compare);
10219 %}
10220
10221 // (src1 & src2) == 0?
10222 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10223 match(Set cr0 (CmpI (AndI src1 src2) zero));
10224 // r0 is killed
10225 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10226 size(4);
10227 ins_encode %{
10228 __ andi_(R0, $src1$$Register, $src2$$constant);
10229 %}
10230 ins_pipe(pipe_class_compare);
10231 %}
10232
10233 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10234 match(Set crx (CmpL src1 src2));
10235 format %{ "CMPD $crx, $src1, $src2" %}
10236 size(4);
10237 ins_encode %{
10238 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10239 %}
10240 ins_pipe(pipe_class_compare);
10241 %}
10242
10243 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10244 match(Set crx (CmpL src1 src2));
10245 format %{ "CMPDI $crx, $src1, $src2" %}
10246 size(4);
10247 ins_encode %{
10248 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10249 %}
10250 ins_pipe(pipe_class_compare);
10251 %}
10252
10253 // Added CmpUL for LoopPredicate.
10254 instruct cmpUL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10255 match(Set crx (CmpUL src1 src2));
10256 format %{ "CMPLD $crx, $src1, $src2" %}
10257 size(4);
10258 ins_encode %{
10259 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10260 %}
10261 ins_pipe(pipe_class_compare);
10262 %}
10263
10264 instruct cmpUL_reg_imm16(flagsReg crx, iRegLsrc src1, uimmL16 src2) %{
10265 match(Set crx (CmpUL src1 src2));
10266 format %{ "CMPLDI $crx, $src1, $src2" %}
10267 size(4);
10268 ins_encode %{
10269 __ cmpldi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10270 %}
10271 ins_pipe(pipe_class_compare);
10272 %}
10273
10274 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10275 match(Set cr0 (CmpL (AndL src1 src2) zero));
10276 // r0 is killed
10277 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10278 size(4);
10279 ins_encode %{
10280 __ and_(R0, $src1$$Register, $src2$$Register);
10281 %}
10282 ins_pipe(pipe_class_compare);
10283 %}
10284
10285 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10286 match(Set cr0 (CmpL (AndL src1 src2) zero));
10287 // r0 is killed
10288 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10289 size(4);
10290 ins_encode %{
10291 __ andi_(R0, $src1$$Register, $src2$$constant);
10292 %}
10293 ins_pipe(pipe_class_compare);
10294 %}
10295
10296 // Manifest a CmpL3 result in an integer register.
10297 instruct cmpL3_reg_reg(iRegIdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
10298 match(Set dst (CmpL3 src1 src2));
10299 effect(KILL cr0);
10300 ins_cost(DEFAULT_COST * 5);
10301 size((VM_Version::has_brw() ? 16 : 20));
10302
10303 format %{ "cmpL3_reg_reg $dst, $src1, $src2" %}
10304
10305 ins_encode %{
10306 __ cmpd(CR0, $src1$$Register, $src2$$Register);
10307 __ set_cmp3($dst$$Register);
10308 %}
10309 ins_pipe(pipe_class_default);
10310 %}
10311
10312 instruct cmpU3_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
10313 match(Set dst (CmpU3 src1 src2));
10314 effect(KILL cr0);
10315 ins_cost(DEFAULT_COST * 5);
10316 size((VM_Version::has_brw() ? 16 : 20));
10317
10318 format %{ "cmpU3_reg_reg $dst, $src1, $src2" %}
10319
10320 ins_encode %{
10321 __ cmplw(CR0, $src1$$Register, $src2$$Register);
10322 __ set_cmp3($dst$$Register);
10323 %}
10324 ins_pipe(pipe_class_default);
10325 %}
10326
10327 instruct cmpUL3_reg_reg(iRegIdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
10328 match(Set dst (CmpUL3 src1 src2));
10329 effect(KILL cr0);
10330 ins_cost(DEFAULT_COST * 5);
10331 size((VM_Version::has_brw() ? 16 : 20));
10332
10333 format %{ "cmpUL3_reg_reg $dst, $src1, $src2" %}
10334
10335 ins_encode %{
10336 __ cmpld(CR0, $src1$$Register, $src2$$Register);
10337 __ set_cmp3($dst$$Register);
10338 %}
10339 ins_pipe(pipe_class_default);
10340 %}
10341
10342 // Implicit range checks.
10343 // A range check in the ideal world has one of the following shapes:
10344 // - (If le (CmpU length index)), (IfTrue throw exception)
10345 // - (If lt (CmpU index length)), (IfFalse throw exception)
10346 //
10347 // Match range check 'If le (CmpU length index)'.
10348 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10349 match(If cmp (CmpU src_length index));
10350 effect(USE labl);
10351 predicate(TrapBasedRangeChecks &&
10352 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10353 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10354 (Matcher::branches_to_uncommon_trap(_leaf)));
10355
10356 ins_is_TrapBasedCheckNode(true);
10357
10358 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10359 size(4);
10360 ins_encode %{
10361 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10362 __ trap_range_check_le($src_length$$Register, $index$$constant);
10363 } else {
10364 // Both successors are uncommon traps, probability is 0.
10365 // Node got flipped during fixup flow.
10366 assert($cmp$$cmpcode == 0x9, "must be greater");
10367 __ trap_range_check_g($src_length$$Register, $index$$constant);
10368 }
10369 %}
10370 ins_pipe(pipe_class_trap);
10371 %}
10372
10373 // Match range check 'If lt (CmpU index length)'.
10374 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10375 match(If cmp (CmpU src_index src_length));
10376 effect(USE labl);
10377 predicate(TrapBasedRangeChecks &&
10378 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10379 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10380 (Matcher::branches_to_uncommon_trap(_leaf)));
10381
10382 ins_is_TrapBasedCheckNode(true);
10383
10384 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10385 size(4);
10386 ins_encode %{
10387 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10388 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10389 } else {
10390 // Both successors are uncommon traps, probability is 0.
10391 // Node got flipped during fixup flow.
10392 assert($cmp$$cmpcode == 0x8, "must be less");
10393 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10394 }
10395 %}
10396 ins_pipe(pipe_class_trap);
10397 %}
10398
10399 // Match range check 'If lt (CmpU index length)'.
10400 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10401 match(If cmp (CmpU src_index length));
10402 effect(USE labl);
10403 predicate(TrapBasedRangeChecks &&
10404 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10405 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10406 (Matcher::branches_to_uncommon_trap(_leaf)));
10407
10408 ins_is_TrapBasedCheckNode(true);
10409
10410 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10411 size(4);
10412 ins_encode %{
10413 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10414 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10415 } else {
10416 // Both successors are uncommon traps, probability is 0.
10417 // Node got flipped during fixup flow.
10418 assert($cmp$$cmpcode == 0x8, "must be less");
10419 __ trap_range_check_l($src_index$$Register, $length$$constant);
10420 }
10421 %}
10422 ins_pipe(pipe_class_trap);
10423 %}
10424
10425 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10426 match(Set crx (CmpU src1 src2));
10427 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10428 size(4);
10429 ins_encode %{
10430 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10431 %}
10432 ins_pipe(pipe_class_compare);
10433 %}
10434
10435 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10436 match(Set crx (CmpU src1 src2));
10437 size(4);
10438 format %{ "CMPLWI $crx, $src1, $src2" %}
10439 ins_encode %{
10440 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10441 %}
10442 ins_pipe(pipe_class_compare);
10443 %}
10444
10445 // Implicit zero checks (more implicit null checks).
10446 // No constant pool entries required.
10447 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10448 match(If cmp (CmpN value zero));
10449 effect(USE labl);
10450 predicate(TrapBasedNullChecks &&
10451 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10452 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10453 Matcher::branches_to_uncommon_trap(_leaf));
10454 ins_cost(1);
10455
10456 ins_is_TrapBasedCheckNode(true);
10457
10458 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10459 size(4);
10460 ins_encode %{
10461 if ($cmp$$cmpcode == 0xA) {
10462 __ trap_null_check($value$$Register);
10463 } else {
10464 // Both successors are uncommon traps, probability is 0.
10465 // Node got flipped during fixup flow.
10466 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10467 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10468 }
10469 %}
10470 ins_pipe(pipe_class_trap);
10471 %}
10472
10473 // Compare narrow oops.
10474 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10475 match(Set crx (CmpN src1 src2));
10476
10477 size(4);
10478 ins_cost(2);
10479 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10480 ins_encode %{
10481 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10482 %}
10483 ins_pipe(pipe_class_compare);
10484 %}
10485
10486 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10487 match(Set crx (CmpN src1 src2));
10488 // Make this more expensive than zeroCheckN_iReg_imm0.
10489 ins_cost(2);
10490
10491 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10492 size(4);
10493 ins_encode %{
10494 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10495 %}
10496 ins_pipe(pipe_class_compare);
10497 %}
10498
10499 // Implicit zero checks (more implicit null checks).
10500 // No constant pool entries required.
10501 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10502 match(If cmp (CmpP value zero));
10503 effect(USE labl);
10504 predicate(TrapBasedNullChecks &&
10505 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10506 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10507 Matcher::branches_to_uncommon_trap(_leaf));
10508 ins_cost(1); // Should not be cheaper than zeroCheckN.
10509
10510 ins_is_TrapBasedCheckNode(true);
10511
10512 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10513 size(4);
10514 ins_encode %{
10515 if ($cmp$$cmpcode == 0xA) {
10516 __ trap_null_check($value$$Register);
10517 } else {
10518 // Both successors are uncommon traps, probability is 0.
10519 // Node got flipped during fixup flow.
10520 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10521 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10522 }
10523 %}
10524 ins_pipe(pipe_class_trap);
10525 %}
10526
10527 // Compare Pointers
10528 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10529 match(Set crx (CmpP src1 src2));
10530 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10531 size(4);
10532 ins_encode %{
10533 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10534 %}
10535 ins_pipe(pipe_class_compare);
10536 %}
10537
10538 instruct cmpP_reg_null(flagsReg crx, iRegP_N2P src1, immP_0or1 src2) %{
10539 match(Set crx (CmpP src1 src2));
10540 format %{ "CMPLDI $crx, $src1, $src2 \t// ptr" %}
10541 size(4);
10542 ins_encode %{
10543 __ cmpldi($crx$$CondRegister, $src1$$Register, (int)((short)($src2$$constant & 0xFFFF)));
10544 %}
10545 ins_pipe(pipe_class_compare);
10546 %}
10547
10548 // Used in postalloc expand.
10549 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10550 // This match rule prevents reordering of node before a safepoint.
10551 // This only makes sense if this instructions is used exclusively
10552 // for the expansion of EncodeP!
10553 match(Set crx (CmpP src1 src2));
10554 predicate(false);
10555
10556 format %{ "CMPDI $crx, $src1, $src2" %}
10557 size(4);
10558 ins_encode %{
10559 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10560 %}
10561 ins_pipe(pipe_class_compare);
10562 %}
10563
10564 //----------Float Compares----------------------------------------------------
10565
10566 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10567 // Needs matchrule, see cmpDUnordered.
10568 match(Set crx (CmpF src1 src2));
10569 // no match-rule, false predicate
10570 predicate(false);
10571
10572 format %{ "cmpFUrd $crx, $src1, $src2" %}
10573 size(4);
10574 ins_encode %{
10575 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10576 %}
10577 ins_pipe(pipe_class_default);
10578 %}
10579
10580 // Compare floating, generate condition code.
10581 instruct cmpF_reg_reg(flagsReg crx, regF src1, regF src2) %{
10582 match(Set crx (CmpF src1 src2));
10583 ins_cost(DEFAULT_COST+BRANCH_COST);
10584
10585 format %{ "CMPF $crx, $src1, $src2" %}
10586 size(16);
10587 ins_encode %{
10588 Label done;
10589 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10590 __ bns($crx$$CondRegister, done);
10591 __ li(R0, 0);
10592 __ cmpwi($crx$$CondRegister, R0, 1);
10593 __ bind(done);
10594 %}
10595 ins_pipe(pipe_class_default);
10596 %}
10597
10598 // Compare float, generate -1,0,1
10599 instruct cmpF3_reg_reg(iRegIdst dst, regF src1, regF src2, flagsRegCR0 cr0) %{
10600 match(Set dst (CmpF3 src1 src2));
10601 effect(KILL cr0);
10602 ins_cost(DEFAULT_COST * 6);
10603 size((VM_Version::has_brw() ? 20 : 24));
10604
10605 format %{ "cmpF3_reg_reg $dst, $src1, $src2" %}
10606
10607 ins_encode %{
10608 __ fcmpu(CR0, $src1$$FloatRegister, $src2$$FloatRegister);
10609 __ set_cmpu3($dst$$Register, true); // C2 requires unordered to get treated like less
10610 %}
10611 ins_pipe(pipe_class_default);
10612 %}
10613
10614 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10615 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10616 // node right before the conditional move using it.
10617 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10618 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10619 // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10620 // conditional move was supposed to be spilled.
10621 match(Set crx (CmpD src1 src2));
10622 // False predicate, shall not be matched.
10623 predicate(false);
10624
10625 format %{ "cmpFUrd $crx, $src1, $src2" %}
10626 size(4);
10627 ins_encode %{
10628 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10629 %}
10630 ins_pipe(pipe_class_default);
10631 %}
10632
10633 instruct cmpD_reg_reg(flagsReg crx, regD src1, regD src2) %{
10634 match(Set crx (CmpD src1 src2));
10635 ins_cost(DEFAULT_COST+BRANCH_COST);
10636
10637 format %{ "CMPD $crx, $src1, $src2" %}
10638 size(16);
10639 ins_encode %{
10640 Label done;
10641 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10642 __ bns($crx$$CondRegister, done);
10643 __ li(R0, 0);
10644 __ cmpwi($crx$$CondRegister, R0, 1);
10645 __ bind(done);
10646 %}
10647 ins_pipe(pipe_class_default);
10648 %}
10649
10650 // Compare double, generate -1,0,1
10651 instruct cmpD3_reg_reg(iRegIdst dst, regD src1, regD src2, flagsRegCR0 cr0) %{
10652 match(Set dst (CmpD3 src1 src2));
10653 effect(KILL cr0);
10654 ins_cost(DEFAULT_COST * 6);
10655 size((VM_Version::has_brw() ? 20 : 24));
10656
10657 format %{ "cmpD3_reg_reg $dst, $src1, $src2" %}
10658
10659 ins_encode %{
10660 __ fcmpu(CR0, $src1$$FloatRegister, $src2$$FloatRegister);
10661 __ set_cmpu3($dst$$Register, true); // C2 requires unordered to get treated like less
10662 %}
10663 ins_pipe(pipe_class_default);
10664 %}
10665
10666 // Compare char
10667 instruct cmprb_Digit_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
10668 match(Set dst (Digit src1));
10669 effect(TEMP src2, TEMP crx);
10670 ins_cost(3 * DEFAULT_COST);
10671
10672 format %{ "LI $src2, 0x3930\n\t"
10673 "CMPRB $crx, 0, $src1, $src2\n\t"
10674 "SETB $dst, $crx" %}
10675 size(12);
10676 ins_encode %{
10677 // 0x30: 0, 0x39: 9
10678 __ li($src2$$Register, 0x3930);
10679 // compare src1 with ranges 0x30 to 0x39
10680 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
10681 __ setb($dst$$Register, $crx$$CondRegister);
10682 %}
10683 ins_pipe(pipe_class_default);
10684 %}
10685
10686 instruct cmprb_LowerCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
10687 match(Set dst (LowerCase src1));
10688 effect(TEMP src2, TEMP crx);
10689 ins_cost(12 * DEFAULT_COST);
10690
10691 format %{ "LI $src2, 0x7A61\n\t"
10692 "CMPRB $crx, 0, $src1, $src2\n\t"
10693 "BGT $crx, done\n\t"
10694 "LIS $src2, (signed short)0xF6DF\n\t"
10695 "ORI $src2, $src2, 0xFFF8\n\t"
10696 "CMPRB $crx, 1, $src1, $src2\n\t"
10697 "BGT $crx, done\n\t"
10698 "LIS $src2, (signed short)0xAAB5\n\t"
10699 "ORI $src2, $src2, 0xBABA\n\t"
10700 "INSRDI $src2, $src2, 32, 0\n\t"
10701 "CMPEQB $crx, 1, $src1, $src2\n"
10702 "done:\n\t"
10703 "SETB $dst, $crx" %}
10704
10705 size(48);
10706 ins_encode %{
10707 Label done;
10708 // 0x61: a, 0x7A: z
10709 __ li($src2$$Register, 0x7A61);
10710 // compare src1 with ranges 0x61 to 0x7A
10711 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
10712 __ bgt($crx$$CondRegister, done);
10713
10714 // 0xDF: sharp s, 0xFF: y with diaeresis, 0xF7 is not the lower case
10715 __ lis($src2$$Register, (signed short)0xF6DF);
10716 __ ori($src2$$Register, $src2$$Register, 0xFFF8);
10717 // compare src1 with ranges 0xDF to 0xF6 and 0xF8 to 0xFF
10718 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
10719 __ bgt($crx$$CondRegister, done);
10720
10721 // 0xAA: feminine ordinal indicator
10722 // 0xB5: micro sign
10723 // 0xBA: masculine ordinal indicator
10724 __ lis($src2$$Register, (signed short)0xAAB5);
10725 __ ori($src2$$Register, $src2$$Register, 0xBABA);
10726 __ insrdi($src2$$Register, $src2$$Register, 32, 0);
10727 // compare src1 with 0xAA, 0xB5, and 0xBA
10728 __ cmpeqb($crx$$CondRegister, $src1$$Register, $src2$$Register);
10729
10730 __ bind(done);
10731 __ setb($dst$$Register, $crx$$CondRegister);
10732 %}
10733 ins_pipe(pipe_class_default);
10734 %}
10735
10736 instruct cmprb_UpperCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
10737 match(Set dst (UpperCase src1));
10738 effect(TEMP src2, TEMP crx);
10739 ins_cost(7 * DEFAULT_COST);
10740
10741 format %{ "LI $src2, 0x5A41\n\t"
10742 "CMPRB $crx, 0, $src1, $src2\n\t"
10743 "BGT $crx, done\n\t"
10744 "LIS $src2, (signed short)0xD6C0\n\t"
10745 "ORI $src2, $src2, 0xDED8\n\t"
10746 "CMPRB $crx, 1, $src1, $src2\n"
10747 "done:\n\t"
10748 "SETB $dst, $crx" %}
10749
10750 size(28);
10751 ins_encode %{
10752 Label done;
10753 // 0x41: A, 0x5A: Z
10754 __ li($src2$$Register, 0x5A41);
10755 // compare src1 with a range 0x41 to 0x5A
10756 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
10757 __ bgt($crx$$CondRegister, done);
10758
10759 // 0xC0: a with grave, 0xDE: thorn, 0xD7 is not the upper case
10760 __ lis($src2$$Register, (signed short)0xD6C0);
10761 __ ori($src2$$Register, $src2$$Register, 0xDED8);
10762 // compare src1 with ranges 0xC0 to 0xD6 and 0xD8 to 0xDE
10763 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
10764
10765 __ bind(done);
10766 __ setb($dst$$Register, $crx$$CondRegister);
10767 %}
10768 ins_pipe(pipe_class_default);
10769 %}
10770
10771 instruct cmprb_Whitespace_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
10772 match(Set dst (Whitespace src1));
10773 predicate(PowerArchitecturePPC64 <= 9);
10774 effect(TEMP src2, TEMP crx);
10775 ins_cost(4 * DEFAULT_COST);
10776
10777 format %{ "LI $src2, 0x0D09\n\t"
10778 "ADDIS $src2, 0x201C\n\t"
10779 "CMPRB $crx, 1, $src1, $src2\n\t"
10780 "SETB $dst, $crx" %}
10781 size(16);
10782 ins_encode %{
10783 // 0x09 to 0x0D, 0x1C to 0x20
10784 __ li($src2$$Register, 0x0D09);
10785 __ addis($src2$$Register, $src2$$Register, 0x0201C);
10786 // compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
10787 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
10788 __ setb($dst$$Register, $crx$$CondRegister);
10789 %}
10790 ins_pipe(pipe_class_default);
10791 %}
10792
10793 // Power 10 version, using prefixed addi to load 32-bit constant
10794 instruct cmprb_Whitespace_reg_reg_prefixed(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
10795 match(Set dst (Whitespace src1));
10796 predicate(PowerArchitecturePPC64 >= 10);
10797 effect(TEMP src2, TEMP crx);
10798 ins_cost(3 * DEFAULT_COST);
10799
10800 format %{ "PLI $src2, 0x201C0D09\n\t"
10801 "CMPRB $crx, 1, $src1, $src2\n\t"
10802 "SETB $dst, $crx" %}
10803 size(16);
10804 ins_encode %{
10805 // 0x09 to 0x0D, 0x1C to 0x20
10806 assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
10807 __ pli($src2$$Register, 0x201C0D09);
10808 // compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
10809 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
10810 __ setb($dst$$Register, $crx$$CondRegister);
10811 %}
10812 ins_pipe(pipe_class_default);
10813 ins_alignment(2);
10814 %}
10815
10816 //----------Branches---------------------------------------------------------
10817 // Jump
10818
10819 // Direct Branch.
10820 instruct branch(label labl) %{
10821 match(Goto);
10822 effect(USE labl);
10823 ins_cost(BRANCH_COST);
10824
10825 format %{ "B $labl" %}
10826 size(4);
10827 ins_encode %{
10828 Label d; // dummy
10829 __ bind(d);
10830 Label* p = $labl$$label;
10831 // `p' is `nullptr' when this encoding class is used only to
10832 // determine the size of the encoded instruction.
10833 Label& l = (nullptr == p)? d : *(p);
10834 __ b(l);
10835 %}
10836 ins_pipe(pipe_class_default);
10837 %}
10838
10839 // Conditional Near Branch
10840 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10841 // Same match rule as `branchConFar'.
10842 match(If cmp crx);
10843 effect(USE lbl);
10844 ins_cost(BRANCH_COST);
10845
10846 // If set to 1 this indicates that the current instruction is a
10847 // short variant of a long branch. This avoids using this
10848 // instruction in first-pass matching. It will then only be used in
10849 // the `Shorten_branches' pass.
10850 ins_short_branch(1);
10851
10852 format %{ "B$cmp $crx, $lbl" %}
10853 size(4);
10854 ins_encode( enc_bc(crx, cmp, lbl) );
10855 ins_pipe(pipe_class_default);
10856 %}
10857
10858 // This is for cases when the ppc64 `bc' instruction does not
10859 // reach far enough. So we emit a far branch here, which is more
10860 // expensive.
10861 //
10862 // Conditional Far Branch
10863 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10864 // Same match rule as `branchCon'.
10865 match(If cmp crx);
10866 effect(USE crx, USE lbl);
10867 // Higher cost than `branchCon'.
10868 ins_cost(5*BRANCH_COST);
10869
10870 // This is not a short variant of a branch, but the long variant.
10871 ins_short_branch(0);
10872
10873 format %{ "B_FAR$cmp $crx, $lbl" %}
10874 size(8);
10875 ins_encode( enc_bc_far(crx, cmp, lbl) );
10876 ins_pipe(pipe_class_default);
10877 %}
10878
10879 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10880 match(CountedLoopEnd cmp crx);
10881 effect(USE labl);
10882 ins_cost(BRANCH_COST);
10883
10884 // short variant.
10885 ins_short_branch(1);
10886
10887 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10888 size(4);
10889 ins_encode( enc_bc(crx, cmp, labl) );
10890 ins_pipe(pipe_class_default);
10891 %}
10892
10893 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10894 match(CountedLoopEnd cmp crx);
10895 effect(USE labl);
10896 ins_cost(BRANCH_COST);
10897
10898 // Long variant.
10899 ins_short_branch(0);
10900
10901 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10902 size(8);
10903 ins_encode( enc_bc_far(crx, cmp, labl) );
10904 ins_pipe(pipe_class_default);
10905 %}
10906
10907 // ============================================================================
10908 // Java runtime operations, intrinsics and other complex operations.
10909
10910 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10911 // array for an instance of the superklass. Set a hidden internal cache on a
10912 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10913 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10914 //
10915 // GL TODO: Improve this.
10916 // - result should not be a TEMP
10917 // - Add match rule as on sparc avoiding additional Cmp.
10918 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10919 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10920 match(Set result (PartialSubtypeCheck subklass superklass));
10921 predicate(!UseSecondarySupersTable);
10922 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10923 ins_cost(DEFAULT_COST*10);
10924
10925 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10926 ins_encode %{
10927 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10928 $tmp_klass$$Register, nullptr, $result$$Register);
10929 %}
10930 ins_pipe(pipe_class_default);
10931 %}
10932
10933 // Two versions of partialSubtypeCheck, both used when we need to
10934 // search for a super class in the secondary supers array. The first
10935 // is used when we don't know _a priori_ the class being searched
10936 // for. The second, far more common, is used when we do know: this is
10937 // used for instanceof, checkcast, and any case where C2 can determine
10938 // it by constant propagation.
10939 instruct partialSubtypeCheckVarSuper(iRegPsrc sub, iRegPsrc super, iRegPdst result,
10940 iRegPdst tempR1, iRegPdst tempR2, iRegPdst tempR3, iRegPdst tempR4,
10941 flagsRegCR0 cr0, regCTR ctr)
10942 %{
10943 match(Set result (PartialSubtypeCheck sub super));
10944 predicate(UseSecondarySupersTable);
10945 effect(KILL cr0, KILL ctr, TEMP_DEF result, TEMP tempR1, TEMP tempR2, TEMP tempR3, TEMP tempR4);
10946
10947 ins_cost(DEFAULT_COST * 10); // slightly larger than the next version
10948 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10949 ins_encode %{
10950 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register,
10951 $tempR1$$Register, $tempR2$$Register, $tempR3$$Register, $tempR4$$Register,
10952 $result$$Register);
10953 %}
10954 ins_pipe(pipe_class_memory);
10955 %}
10956
10957 instruct partialSubtypeCheckConstSuper(rarg3RegP sub, rarg2RegP super_reg, immP super_con, rarg6RegP result,
10958 rarg1RegP tempR1, rarg5RegP tempR2, rarg4RegP tempR3, rscratch1RegP tempR4,
10959 flagsRegCR0 cr0, regCTR ctr)
10960 %{
10961 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10962 predicate(UseSecondarySupersTable);
10963 effect(KILL cr0, KILL ctr, TEMP tempR1, TEMP tempR2, TEMP tempR3, TEMP tempR4);
10964
10965 ins_cost(DEFAULT_COST*8); // smaller than the other version
10966 format %{ "partialSubtypeCheck $result, $sub, $super_reg" %}
10967
10968 ins_encode %{
10969 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10970 if (InlineSecondarySupersTest) {
10971 __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register,
10972 $tempR1$$Register, $tempR2$$Register, $tempR3$$Register, $tempR4$$Register,
10973 $result$$Register, super_klass_slot);
10974 } else {
10975 address stub = StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot);
10976 Register r_stub_addr = $tempR1$$Register;
10977 __ add_const_optimized(r_stub_addr, R29_TOC, MacroAssembler::offset_to_global_toc(stub), R0);
10978 __ mtctr(r_stub_addr);
10979 __ bctrl();
10980 }
10981 %}
10982
10983 ins_pipe(pipe_class_memory);
10984 %}
10985
10986 // inlined locking and unlocking
10987
10988 instruct cmpFastLock(flagsRegCR0 crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
10989 predicate(!UseObjectMonitorTable);
10990 match(Set crx (FastLock oop box));
10991 effect(TEMP tmp1, TEMP tmp2);
10992
10993 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2" %}
10994 ins_encode %{
10995 __ fast_lock($crx$$CondRegister, $oop$$Register, $box$$Register,
10996 $tmp1$$Register, $tmp2$$Register, noreg /*tmp3*/);
10997 // If locking was successful, crx should indicate 'EQ'.
10998 // The compiler generates a branch to the runtime call to
10999 // _complete_monitor_locking_Java for the case where crx is 'NE'.
11000 %}
11001 ins_pipe(pipe_class_compare);
11002 %}
11003
11004 instruct cmpFastLockMonitorTable(flagsRegCR0 crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, flagsRegCR1 cr1) %{
11005 predicate(UseObjectMonitorTable);
11006 match(Set crx (FastLock oop box));
11007 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr1);
11008
11009 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
11010 ins_encode %{
11011 __ fast_lock($crx$$CondRegister, $oop$$Register, $box$$Register,
11012 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11013 // If locking was successful, crx should indicate 'EQ'.
11014 // The compiler generates a branch to the runtime call to
11015 // _complete_monitor_locking_Java for the case where crx is 'NE'.
11016 %}
11017 ins_pipe(pipe_class_compare);
11018 %}
11019
11020 instruct cmpFastUnlock(flagsRegCR0 crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
11021 match(Set crx (FastUnlock oop box));
11022 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11023
11024 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
11025 ins_encode %{
11026 __ fast_unlock($crx$$CondRegister, $oop$$Register, $box$$Register,
11027 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11028 // If unlocking was successful, crx should indicate 'EQ'.
11029 // The compiler generates a branch to the runtime call to
11030 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11031 %}
11032 ins_pipe(pipe_class_compare);
11033 %}
11034
11035 // Align address.
11036 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11037 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11038
11039 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
11040 size(4);
11041 ins_encode %{
11042 __ clrrdi($dst$$Register, $src$$Register, log2i_exact(-(julong)$mask$$constant));
11043 %}
11044 ins_pipe(pipe_class_default);
11045 %}
11046
11047 // Array size computation.
11048 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11049 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11050
11051 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11052 size(4);
11053 ins_encode %{
11054 __ subf($dst$$Register, $start$$Register, $end$$Register);
11055 %}
11056 ins_pipe(pipe_class_default);
11057 %}
11058
11059 // Clear-array with constant short array length. The versions below can use dcbz with cnt > 30.
11060 instruct inlineCallClearArrayShort(immLmax30 cnt, rarg2RegP base, immL_0 zero, Universe dummy, regCTR ctr) %{
11061 match(Set dummy (ClearArray (Binary cnt base) zero));
11062 effect(USE_KILL base, KILL ctr);
11063 ins_cost(2 * MEMORY_REF_COST);
11064
11065 format %{ "ClearArray $cnt, $base" %}
11066 ins_encode %{
11067 __ clear_memory_constlen($base$$Register, $cnt$$constant, R0); // kills base, R0
11068 %}
11069 ins_pipe(pipe_class_default);
11070 %}
11071
11072 // Clear-array with constant large array length.
11073 instruct inlineCallClearArrayLarge(immL cnt, rarg2RegP base, immL_0 zero, Universe dummy, iRegLdst tmp, regCTR ctr) %{
11074 match(Set dummy (ClearArray (Binary cnt base) zero));
11075 effect(USE_KILL base, TEMP tmp, KILL ctr);
11076 ins_cost(3 * MEMORY_REF_COST);
11077
11078 format %{ "ClearArray $cnt, $base \t// KILL $tmp" %}
11079 ins_encode %{
11080 __ clear_memory_doubleword($base$$Register, $tmp$$Register, R0, $cnt$$constant); // kills base, R0
11081 %}
11082 ins_pipe(pipe_class_default);
11083 %}
11084
11085 // Clear-array with dynamic array length.
11086 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, immL_0 zero, Universe dummy, regCTR ctr) %{
11087 match(Set dummy (ClearArray (Binary cnt base) zero));
11088 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11089 ins_cost(4 * MEMORY_REF_COST);
11090
11091 format %{ "ClearArray $cnt, $base" %}
11092 ins_encode %{
11093 __ clear_memory_doubleword($base$$Register, $cnt$$Register, R0); // kills cnt, base, R0
11094 %}
11095 ins_pipe(pipe_class_default);
11096 %}
11097
11098 // Clear-array with dynamic array length and non-zero value.
11099 instruct inlineCallClearArrayWordCopy(rarg1RegL cnt, rarg2RegP base, iRegLdst val, Universe dummy, regCTR ctr) %{
11100 predicate(((ClearArrayNode*)n)->word_copy_only());
11101 match(Set dummy (ClearArray (Binary cnt base) val));
11102 effect(USE_KILL base, KILL ctr);
11103 ins_cost(8 * MEMORY_REF_COST);
11104
11105 format %{ "ClearArray $cnt, $base, $val" %}
11106 ins_encode %{
11107 __ fill_words($base$$Register, $cnt$$Register, $val$$Register);
11108 %}
11109 ins_pipe(pipe_class_default);
11110 %}
11111
11112 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11113 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11114 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11115 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11116 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11117 ins_cost(300);
11118 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11119 ins_encode %{
11120 __ string_compare($str1$$Register, $str2$$Register,
11121 $cnt1$$Register, $cnt2$$Register,
11122 $tmp$$Register,
11123 $result$$Register, StrIntrinsicNode::LL);
11124 %}
11125 ins_pipe(pipe_class_default);
11126 %}
11127
11128 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11129 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11130 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11131 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11132 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11133 ins_cost(300);
11134 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11135 ins_encode %{
11136 __ string_compare($str1$$Register, $str2$$Register,
11137 $cnt1$$Register, $cnt2$$Register,
11138 $tmp$$Register,
11139 $result$$Register, StrIntrinsicNode::UU);
11140 %}
11141 ins_pipe(pipe_class_default);
11142 %}
11143
11144 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11145 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11146 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11147 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11148 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11149 ins_cost(300);
11150 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11151 ins_encode %{
11152 __ string_compare($str1$$Register, $str2$$Register,
11153 $cnt1$$Register, $cnt2$$Register,
11154 $tmp$$Register,
11155 $result$$Register, StrIntrinsicNode::LU);
11156 %}
11157 ins_pipe(pipe_class_default);
11158 %}
11159
11160 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11161 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11162 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11163 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11164 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11165 ins_cost(300);
11166 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11167 ins_encode %{
11168 __ string_compare($str2$$Register, $str1$$Register,
11169 $cnt2$$Register, $cnt1$$Register,
11170 $tmp$$Register,
11171 $result$$Register, StrIntrinsicNode::UL);
11172 %}
11173 ins_pipe(pipe_class_default);
11174 %}
11175
11176 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
11177 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11178 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11179 match(Set result (StrEquals (Binary str1 str2) cnt));
11180 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
11181 ins_cost(300);
11182 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
11183 ins_encode %{
11184 __ array_equals(false, $str1$$Register, $str2$$Register,
11185 $cnt$$Register, $tmp$$Register,
11186 $result$$Register, true /* byte */);
11187 %}
11188 ins_pipe(pipe_class_default);
11189 %}
11190
11191 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
11192 iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11193 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11194 match(Set result (AryEq ary1 ary2));
11195 effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
11196 ins_cost(300);
11197 format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
11198 ins_encode %{
11199 __ array_equals(true, $ary1$$Register, $ary2$$Register,
11200 $tmp1$$Register, $tmp2$$Register,
11201 $result$$Register, true /* byte */);
11202 %}
11203 ins_pipe(pipe_class_default);
11204 %}
11205
11206 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
11207 iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11208 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11209 match(Set result (AryEq ary1 ary2));
11210 effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
11211 ins_cost(300);
11212 format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
11213 ins_encode %{
11214 __ array_equals(true, $ary1$$Register, $ary2$$Register,
11215 $tmp1$$Register, $tmp2$$Register,
11216 $result$$Register, false /* byte */);
11217 %}
11218 ins_pipe(pipe_class_default);
11219 %}
11220
11221 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11222 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11223 iRegIdst tmp1, iRegIdst tmp2,
11224 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11225 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11226 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11227 // Required for EA: check if it is still a type_array.
11228 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11229 ins_cost(150);
11230
11231 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11232 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11233
11234 ins_encode %{
11235 immPOper *needleOper = (immPOper *)$needleImm;
11236 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11237 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11238 jchar chr;
11239 #ifdef VM_LITTLE_ENDIAN
11240 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11241 ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11242 #else
11243 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11244 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11245 #endif
11246 __ string_indexof_char($result$$Register,
11247 $haystack$$Register, $haycnt$$Register,
11248 R0, chr,
11249 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11250 %}
11251 ins_pipe(pipe_class_compare);
11252 %}
11253
11254 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11255 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11256 iRegIdst tmp1, iRegIdst tmp2,
11257 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11258 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11259 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11260 // Required for EA: check if it is still a type_array.
11261 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11262 ins_cost(150);
11263
11264 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11265 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11266
11267 ins_encode %{
11268 immPOper *needleOper = (immPOper *)$needleImm;
11269 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11270 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11271 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11272 __ string_indexof_char($result$$Register,
11273 $haystack$$Register, $haycnt$$Register,
11274 R0, chr,
11275 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11276 %}
11277 ins_pipe(pipe_class_compare);
11278 %}
11279
11280 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11281 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11282 iRegIdst tmp1, iRegIdst tmp2,
11283 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11284 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11285 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11286 // Required for EA: check if it is still a type_array.
11287 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11288 ins_cost(150);
11289
11290 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11291 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11292
11293 ins_encode %{
11294 immPOper *needleOper = (immPOper *)$needleImm;
11295 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11296 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11297 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11298 __ string_indexof_char($result$$Register,
11299 $haystack$$Register, $haycnt$$Register,
11300 R0, chr,
11301 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11302 %}
11303 ins_pipe(pipe_class_compare);
11304 %}
11305
11306 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11307 rscratch2RegP needle, immI_1 needlecntImm,
11308 iRegIdst tmp1, iRegIdst tmp2,
11309 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11310 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11311 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11312 // Required for EA: check if it is still a type_array.
11313 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
11314 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11315 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11316 ins_cost(180);
11317
11318 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11319 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11320 ins_encode %{
11321 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11322 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11323 guarantee(needle_values, "sanity");
11324 jchar chr;
11325 #ifdef VM_LITTLE_ENDIAN
11326 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11327 ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11328 #else
11329 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11330 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11331 #endif
11332 __ string_indexof_char($result$$Register,
11333 $haystack$$Register, $haycnt$$Register,
11334 R0, chr,
11335 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11336 %}
11337 ins_pipe(pipe_class_compare);
11338 %}
11339
11340 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11341 rscratch2RegP needle, immI_1 needlecntImm,
11342 iRegIdst tmp1, iRegIdst tmp2,
11343 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11344 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11345 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11346 // Required for EA: check if it is still a type_array.
11347 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
11348 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11349 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11350 ins_cost(180);
11351
11352 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11353 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11354 ins_encode %{
11355 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11356 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11357 guarantee(needle_values, "sanity");
11358 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11359 __ string_indexof_char($result$$Register,
11360 $haystack$$Register, $haycnt$$Register,
11361 R0, chr,
11362 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11363 %}
11364 ins_pipe(pipe_class_compare);
11365 %}
11366
11367 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11368 rscratch2RegP needle, immI_1 needlecntImm,
11369 iRegIdst tmp1, iRegIdst tmp2,
11370 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11371 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11372 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11373 // Required for EA: check if it is still a type_array.
11374 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
11375 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11376 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11377 ins_cost(180);
11378
11379 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11380 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11381 ins_encode %{
11382 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11383 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11384 guarantee(needle_values, "sanity");
11385 jchar chr = (jchar)needle_values->element_value(0).as_byte();
11386 __ string_indexof_char($result$$Register,
11387 $haystack$$Register, $haycnt$$Register,
11388 R0, chr,
11389 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11390 %}
11391 ins_pipe(pipe_class_compare);
11392 %}
11393
11394 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11395 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
11396 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11397 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
11398 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11399 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
11400 ins_cost(180);
11401
11402 format %{ "StringUTF16 IndexOfChar $haystack[0..$haycnt], $ch"
11403 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11404 ins_encode %{
11405 __ string_indexof_char($result$$Register,
11406 $haystack$$Register, $haycnt$$Register,
11407 $ch$$Register, 0 /* this is not used if the character is already in a register */,
11408 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11409 %}
11410 ins_pipe(pipe_class_compare);
11411 %}
11412
11413 instruct indexOfChar_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11414 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
11415 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11416 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
11417 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11418 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
11419 ins_cost(180);
11420
11421 format %{ "StringLatin1 IndexOfChar $haystack[0..$haycnt], $ch"
11422 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11423 ins_encode %{
11424 __ string_indexof_char($result$$Register,
11425 $haystack$$Register, $haycnt$$Register,
11426 $ch$$Register, 0 /* this is not used if the character is already in a register */,
11427 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11428 %}
11429 ins_pipe(pipe_class_compare);
11430 %}
11431
11432 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11433 iRegPsrc needle, uimmI15 needlecntImm,
11434 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11435 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11436 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11437 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11438 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11439 // Required for EA: check if it is still a type_array.
11440 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
11441 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11442 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11443 ins_cost(250);
11444
11445 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11446 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11447 ins_encode %{
11448 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11449 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11450
11451 __ string_indexof($result$$Register,
11452 $haystack$$Register, $haycnt$$Register,
11453 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11454 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
11455 %}
11456 ins_pipe(pipe_class_compare);
11457 %}
11458
11459 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11460 iRegPsrc needle, uimmI15 needlecntImm,
11461 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11462 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11463 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11464 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11465 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11466 // Required for EA: check if it is still a type_array.
11467 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
11468 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11469 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11470 ins_cost(250);
11471
11472 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11473 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11474 ins_encode %{
11475 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11476 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11477
11478 __ string_indexof($result$$Register,
11479 $haystack$$Register, $haycnt$$Register,
11480 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11481 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
11482 %}
11483 ins_pipe(pipe_class_compare);
11484 %}
11485
11486 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11487 iRegPsrc needle, uimmI15 needlecntImm,
11488 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11489 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11490 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11491 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11492 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11493 // Required for EA: check if it is still a type_array.
11494 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
11495 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11496 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11497 ins_cost(250);
11498
11499 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11500 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11501 ins_encode %{
11502 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11503 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11504
11505 __ string_indexof($result$$Register,
11506 $haystack$$Register, $haycnt$$Register,
11507 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11508 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
11509 %}
11510 ins_pipe(pipe_class_compare);
11511 %}
11512
11513 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11514 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11515 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11516 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11517 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11518 TEMP_DEF result,
11519 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11520 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11521 ins_cost(300);
11522
11523 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11524 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11525 ins_encode %{
11526 __ string_indexof($result$$Register,
11527 $haystack$$Register, $haycnt$$Register,
11528 $needle$$Register, nullptr, $needlecnt$$Register, 0, // needlecnt not constant.
11529 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
11530 %}
11531 ins_pipe(pipe_class_compare);
11532 %}
11533
11534 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11535 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11536 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11537 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11538 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11539 TEMP_DEF result,
11540 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11541 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11542 ins_cost(300);
11543
11544 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11545 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11546 ins_encode %{
11547 __ string_indexof($result$$Register,
11548 $haystack$$Register, $haycnt$$Register,
11549 $needle$$Register, nullptr, $needlecnt$$Register, 0, // needlecnt not constant.
11550 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
11551 %}
11552 ins_pipe(pipe_class_compare);
11553 %}
11554
11555 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11556 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11557 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11558 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11559 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11560 TEMP_DEF result,
11561 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11562 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11563 ins_cost(300);
11564
11565 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11566 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11567 ins_encode %{
11568 __ string_indexof($result$$Register,
11569 $haystack$$Register, $haycnt$$Register,
11570 $needle$$Register, nullptr, $needlecnt$$Register, 0, // needlecnt not constant.
11571 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
11572 %}
11573 ins_pipe(pipe_class_compare);
11574 %}
11575
11576 // char[] to byte[] compression
11577 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11578 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11579 match(Set result (StrCompressedCopy src (Binary dst len)));
11580 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11581 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11582 ins_cost(300);
11583 format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11584 ins_encode %{
11585 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register, $tmp2$$Register,
11586 $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, $result$$Register, false);
11587 %}
11588 ins_pipe(pipe_class_default);
11589 %}
11590
11591 // byte[] to char[] inflation
11592 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1,
11593 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11594 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11595 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11596 ins_cost(300);
11597 format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11598 ins_encode %{
11599 Label Ldone;
11600 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11601 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11602 __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11603 __ beq(CR0, Ldone);
11604 __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register);
11605 __ bind(Ldone);
11606 %}
11607 ins_pipe(pipe_class_default);
11608 %}
11609
11610 // StringCoding.java intrinsics
11611 instruct count_positives(iRegPsrc ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2,
11612 regCTR ctr, flagsRegCR0 cr0)
11613 %{
11614 match(Set result (CountPositives ary1 len));
11615 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0);
11616 ins_cost(300);
11617 format %{ "count positives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %}
11618 ins_encode %{
11619 __ count_positives($ary1$$Register, $len$$Register, $result$$Register,
11620 $tmp1$$Register, $tmp2$$Register);
11621 %}
11622 ins_pipe(pipe_class_default);
11623 %}
11624
11625 // encode char[] to byte[] in ISO_8859_1
11626 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11627 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11628 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
11629 match(Set result (EncodeISOArray src (Binary dst len)));
11630 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11631 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11632 ins_cost(300);
11633 format %{ "Encode iso array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11634 ins_encode %{
11635 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register, $tmp2$$Register,
11636 $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, $result$$Register, false);
11637 %}
11638 ins_pipe(pipe_class_default);
11639 %}
11640
11641 // encode char[] to byte[] in ASCII
11642 instruct encode_ascii_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11643 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11644 predicate(((EncodeISOArrayNode*)n)->is_ascii());
11645 match(Set result (EncodeISOArray src (Binary dst len)));
11646 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11647 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11648 ins_cost(300);
11649 format %{ "Encode ascii array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11650 ins_encode %{
11651 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register, $tmp2$$Register,
11652 $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, $result$$Register, true);
11653 %}
11654 ins_pipe(pipe_class_default);
11655 %}
11656
11657
11658 //---------- Min/Max Instructions ---------------------------------------------
11659
11660
11661 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
11662 match(Set dst (MinI src1 src2));
11663 effect(KILL cr0);
11664 ins_cost(DEFAULT_COST*2);
11665
11666 size(8);
11667 ins_encode %{
11668 __ cmpw(CR0, $src1$$Register, $src2$$Register);
11669 __ isel($dst$$Register, CR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register);
11670 %}
11671 ins_pipe(pipe_class_default);
11672 %}
11673
11674
11675 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
11676 match(Set dst (MaxI src1 src2));
11677 effect(KILL cr0);
11678 ins_cost(DEFAULT_COST*2);
11679
11680 size(8);
11681 ins_encode %{
11682 __ cmpw(CR0, $src1$$Register, $src2$$Register);
11683 __ isel($dst$$Register, CR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register);
11684 %}
11685 ins_pipe(pipe_class_default);
11686 %}
11687
11688 instruct minF(regF dst, regF src1, regF src2) %{
11689 match(Set dst (MinF src1 src2));
11690 predicate(PowerArchitecturePPC64 >= 9);
11691 ins_cost(DEFAULT_COST);
11692
11693 format %{ "XSMINJDP $dst, $src1, $src2\t// MinF" %}
11694 size(4);
11695 ins_encode %{
11696 __ xsminjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
11697 %}
11698 ins_pipe(pipe_class_default);
11699 %}
11700
11701 instruct minD(regD dst, regD src1, regD src2) %{
11702 match(Set dst (MinD src1 src2));
11703 predicate(PowerArchitecturePPC64 >= 9);
11704 ins_cost(DEFAULT_COST);
11705
11706 format %{ "XSMINJDP $dst, $src1, $src2\t// MinD" %}
11707 size(4);
11708 ins_encode %{
11709 __ xsminjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
11710 %}
11711 ins_pipe(pipe_class_default);
11712 %}
11713
11714 instruct maxF(regF dst, regF src1, regF src2) %{
11715 match(Set dst (MaxF src1 src2));
11716 predicate(PowerArchitecturePPC64 >= 9);
11717 ins_cost(DEFAULT_COST);
11718
11719 format %{ "XSMAXJDP $dst, $src1, $src2\t// MaxF" %}
11720 size(4);
11721 ins_encode %{
11722 __ xsmaxjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
11723 %}
11724 ins_pipe(pipe_class_default);
11725 %}
11726
11727 instruct maxD(regD dst, regD src1, regD src2) %{
11728 match(Set dst (MaxD src1 src2));
11729 predicate(PowerArchitecturePPC64 >= 9);
11730 ins_cost(DEFAULT_COST);
11731
11732 format %{ "XSMAXJDP $dst, $src1, $src2\t// MaxD" %}
11733 size(4);
11734 ins_encode %{
11735 __ xsmaxjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
11736 %}
11737 ins_pipe(pipe_class_default);
11738 %}
11739
11740 //---------- Population Count Instructions ------------------------------------
11741
11742 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11743 match(Set dst (PopCountI src));
11744 predicate(UsePopCountInstruction);
11745 ins_cost(DEFAULT_COST);
11746
11747 format %{ "POPCNTW $dst, $src" %}
11748 size(4);
11749 ins_encode %{
11750 __ popcntw($dst$$Register, $src$$Register);
11751 %}
11752 ins_pipe(pipe_class_default);
11753 %}
11754
11755 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11756 predicate(UsePopCountInstruction);
11757 match(Set dst (PopCountL src));
11758 ins_cost(DEFAULT_COST);
11759
11760 format %{ "POPCNTD $dst, $src" %}
11761 size(4);
11762 ins_encode %{
11763 __ popcntd($dst$$Register, $src$$Register);
11764 %}
11765 ins_pipe(pipe_class_default);
11766 %}
11767
11768 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11769 match(Set dst (CountLeadingZerosI src));
11770 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11771 ins_cost(DEFAULT_COST);
11772
11773 format %{ "CNTLZW $dst, $src" %}
11774 size(4);
11775 ins_encode %{
11776 __ cntlzw($dst$$Register, $src$$Register);
11777 %}
11778 ins_pipe(pipe_class_default);
11779 %}
11780
11781 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11782 match(Set dst (CountLeadingZerosL src));
11783 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11784 ins_cost(DEFAULT_COST);
11785
11786 format %{ "CNTLZD $dst, $src" %}
11787 size(4);
11788 ins_encode %{
11789 __ cntlzd($dst$$Register, $src$$Register);
11790 %}
11791 ins_pipe(pipe_class_default);
11792 %}
11793
11794 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11795 // no match-rule, false predicate
11796 effect(DEF dst, USE src);
11797 predicate(false);
11798
11799 format %{ "CNTLZD $dst, $src" %}
11800 size(4);
11801 ins_encode %{
11802 __ cntlzd($dst$$Register, $src$$Register);
11803 %}
11804 ins_pipe(pipe_class_default);
11805 %}
11806
11807 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11808 match(Set dst (CountTrailingZerosI src));
11809 predicate(UseCountLeadingZerosInstructionsPPC64 && !UseCountTrailingZerosInstructionsPPC64);
11810 ins_cost(DEFAULT_COST);
11811
11812 expand %{
11813 immI16 imm1 %{ (int)-1 %}
11814 immI16 imm2 %{ (int)32 %}
11815 immI_minus1 m1 %{ -1 %}
11816 iRegIdst tmpI1;
11817 iRegIdst tmpI2;
11818 iRegIdst tmpI3;
11819 addI_reg_imm16(tmpI1, src, imm1);
11820 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11821 countLeadingZerosI(tmpI3, tmpI2);
11822 subI_imm16_reg(dst, imm2, tmpI3);
11823 %}
11824 %}
11825
11826 instruct countTrailingZerosI_cnttzw(iRegIdst dst, iRegIsrc src) %{
11827 match(Set dst (CountTrailingZerosI src));
11828 predicate(UseCountTrailingZerosInstructionsPPC64);
11829 ins_cost(DEFAULT_COST);
11830
11831 format %{ "CNTTZW $dst, $src" %}
11832 size(4);
11833 ins_encode %{
11834 __ cnttzw($dst$$Register, $src$$Register);
11835 %}
11836 ins_pipe(pipe_class_default);
11837 %}
11838
11839 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11840 match(Set dst (CountTrailingZerosL src));
11841 predicate(UseCountLeadingZerosInstructionsPPC64 && !UseCountTrailingZerosInstructionsPPC64);
11842 ins_cost(DEFAULT_COST);
11843
11844 expand %{
11845 immL16 imm1 %{ (long)-1 %}
11846 immI16 imm2 %{ (int)64 %}
11847 iRegLdst tmpL1;
11848 iRegLdst tmpL2;
11849 iRegIdst tmpL3;
11850 addL_reg_imm16(tmpL1, src, imm1);
11851 andcL_reg_reg(tmpL2, tmpL1, src);
11852 countLeadingZerosL(tmpL3, tmpL2);
11853 subI_imm16_reg(dst, imm2, tmpL3);
11854 %}
11855 %}
11856
11857 instruct countTrailingZerosL_cnttzd(iRegIdst dst, iRegLsrc src) %{
11858 match(Set dst (CountTrailingZerosL src));
11859 predicate(UseCountTrailingZerosInstructionsPPC64);
11860 ins_cost(DEFAULT_COST);
11861
11862 format %{ "CNTTZD $dst, $src" %}
11863 size(4);
11864 ins_encode %{
11865 __ cnttzd($dst$$Register, $src$$Register);
11866 %}
11867 ins_pipe(pipe_class_default);
11868 %}
11869
11870 // Expand nodes for byte_reverse_int/ushort/short.
11871 instruct rlwinm(iRegIdst dst, iRegIsrc src, immI16 shift, immI16 mb, immI16 me) %{
11872 effect(DEF dst, USE src, USE shift, USE mb, USE me);
11873 predicate(false);
11874
11875 format %{ "RLWINM $dst, $src, $shift, $mb, $me" %}
11876 size(4);
11877 ins_encode %{
11878 __ rlwinm($dst$$Register, $src$$Register, $shift$$constant, $mb$$constant, $me$$constant);
11879 %}
11880 ins_pipe(pipe_class_default);
11881 %}
11882
11883 // Expand nodes for byte_reverse_int.
11884 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 n, immI16 b) %{
11885 effect(DEF dst, USE src, USE n, USE b);
11886 predicate(false);
11887
11888 format %{ "INSRWI $dst, $src, $n, $b" %}
11889 size(4);
11890 ins_encode %{
11891 __ insrwi($dst$$Register, $src$$Register, $n$$constant, $b$$constant);
11892 %}
11893 ins_pipe(pipe_class_default);
11894 %}
11895
11896 // As insrwi_a, but with USE_DEF.
11897 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 n, immI16 b) %{
11898 effect(USE_DEF dst, USE src, USE n, USE b);
11899 predicate(false);
11900
11901 format %{ "INSRWI $dst, $src, $n, $b" %}
11902 size(4);
11903 ins_encode %{
11904 __ insrwi($dst$$Register, $src$$Register, $n$$constant, $b$$constant);
11905 %}
11906 ins_pipe(pipe_class_default);
11907 %}
11908
11909 // Just slightly faster than java implementation.
11910 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11911 match(Set dst (ReverseBytesI src));
11912 predicate(!UseByteReverseInstructions);
11913 ins_cost(7*DEFAULT_COST);
11914
11915 expand %{
11916 immI16 imm24 %{ (int) 24 %}
11917 immI16 imm16 %{ (int) 16 %}
11918 immI16 imm8 %{ (int) 8 %}
11919 immI16 imm4 %{ (int) 4 %}
11920 immI16 imm0 %{ (int) 0 %}
11921 iRegLdst tmpI1;
11922 iRegLdst tmpI2;
11923 iRegLdst tmpI3;
11924
11925 urShiftI_reg_imm(tmpI1, src, imm24);
11926 insrwi_a(dst, tmpI1, imm8, imm24);
11927 urShiftI_reg_imm(tmpI2, src, imm16);
11928 insrwi(dst, tmpI2, imm16, imm8);
11929 urShiftI_reg_imm(tmpI3, src, imm8);
11930 insrwi(dst, tmpI3, imm8, imm8);
11931 insrwi(dst, src, imm8, imm0);
11932 %}
11933 %}
11934
11935 instruct bytes_reverse_int_vec(iRegIdst dst, iRegIsrc src, vecX tmpV) %{
11936 match(Set dst (ReverseBytesI src));
11937 predicate(UseVectorByteReverseInstructionsPPC64);
11938 effect(TEMP tmpV);
11939 ins_cost(DEFAULT_COST*3);
11940 size(12);
11941 format %{ "MTVSRWZ $tmpV, $src\n"
11942 "\tXXBRW $tmpV, $tmpV\n"
11943 "\tMFVSRWZ $dst, $tmpV" %}
11944
11945 ins_encode %{
11946 __ mtvsrwz($tmpV$$VectorRegister.to_vsr(), $src$$Register);
11947 __ xxbrw($tmpV$$VectorRegister.to_vsr(), $tmpV$$VectorRegister->to_vsr());
11948 __ mfvsrwz($dst$$Register, $tmpV$$VectorRegister->to_vsr());
11949 %}
11950 ins_pipe(pipe_class_default);
11951 %}
11952
11953 instruct bytes_reverse_int(iRegIdst dst, iRegIsrc src) %{
11954 match(Set dst (ReverseBytesI src));
11955 predicate(UseByteReverseInstructions);
11956 ins_cost(DEFAULT_COST);
11957 size(4);
11958
11959 format %{ "BRW $dst, $src" %}
11960
11961 ins_encode %{
11962 __ brw($dst$$Register, $src$$Register);
11963 %}
11964 ins_pipe(pipe_class_default);
11965 %}
11966
11967 instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{
11968 match(Set dst (ReverseBytesL src));
11969 predicate(!UseByteReverseInstructions);
11970 ins_cost(15*DEFAULT_COST);
11971
11972 expand %{
11973 immI16 imm56 %{ (int) 56 %}
11974 immI16 imm48 %{ (int) 48 %}
11975 immI16 imm40 %{ (int) 40 %}
11976 immI16 imm32 %{ (int) 32 %}
11977 immI16 imm24 %{ (int) 24 %}
11978 immI16 imm16 %{ (int) 16 %}
11979 immI16 imm8 %{ (int) 8 %}
11980 immI16 imm0 %{ (int) 0 %}
11981 iRegLdst tmpL1;
11982 iRegLdst tmpL2;
11983 iRegLdst tmpL3;
11984 iRegLdst tmpL4;
11985 iRegLdst tmpL5;
11986 iRegLdst tmpL6;
11987
11988 // src : |a|b|c|d|e|f|g|h|
11989 rldicl(tmpL1, src, imm8, imm24); // tmpL1 : | | | |e|f|g|h|a|
11990 rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |a| | | |e|
11991 rldicl(tmpL3, tmpL2, imm32, imm0); // tmpL3 : | | | |e| | | |a|
11992 rldicl(tmpL1, src, imm16, imm24); // tmpL1 : | | | |f|g|h|a|b|
11993 rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |b| | | |f|
11994 rldicl(tmpL4, tmpL2, imm40, imm0); // tmpL4 : | | |f| | | |b| |
11995 orL_reg_reg(tmpL5, tmpL3, tmpL4); // tmpL5 : | | |f|e| | |b|a|
11996 rldicl(tmpL1, src, imm24, imm24); // tmpL1 : | | | |g|h|a|b|c|
11997 rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |c| | | |g|
11998 rldicl(tmpL3, tmpL2, imm48, imm0); // tmpL3 : | |g| | | |c| | |
11999 rldicl(tmpL1, src, imm32, imm24); // tmpL1 : | | | |h|a|b|c|d|
12000 rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |d| | | |h|
12001 rldicl(tmpL4, tmpL2, imm56, imm0); // tmpL4 : |h| | | |d| | | |
12002 orL_reg_reg(tmpL6, tmpL3, tmpL4); // tmpL6 : |h|g| | |d|c| | |
12003 orL_reg_reg(dst, tmpL5, tmpL6); // dst : |h|g|f|e|d|c|b|a|
12004 %}
12005 %}
12006
12007 instruct bytes_reverse_long_vec(iRegLdst dst, iRegLsrc src, vecX tmpV) %{
12008 match(Set dst (ReverseBytesL src));
12009 predicate(UseVectorByteReverseInstructionsPPC64);
12010 effect(TEMP tmpV);
12011 ins_cost(DEFAULT_COST*3);
12012 size(12);
12013 format %{ "MTVSRD $tmpV, $src\n"
12014 "\tXXBRD $tmpV, $tmpV\n"
12015 "\tMFVSRD $dst, $tmpV" %}
12016
12017 ins_encode %{
12018 __ mtvsrd($tmpV$$VectorRegister->to_vsr(), $src$$Register);
12019 __ xxbrd($tmpV$$VectorRegister->to_vsr(), $tmpV$$VectorRegister->to_vsr());
12020 __ mfvsrd($dst$$Register, $tmpV$$VectorRegister->to_vsr());
12021 %}
12022 ins_pipe(pipe_class_default);
12023 %}
12024
12025 instruct bytes_reverse_long(iRegLdst dst, iRegLsrc src) %{
12026 match(Set dst (ReverseBytesL src));
12027 predicate(UseByteReverseInstructions);
12028 ins_cost(DEFAULT_COST);
12029 size(4);
12030
12031 format %{ "BRD $dst, $src" %}
12032
12033 ins_encode %{
12034 __ brd($dst$$Register, $src$$Register);
12035 %}
12036 ins_pipe(pipe_class_default);
12037 %}
12038
12039 // Need zero extend. Must not use brh only.
12040 instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{
12041 match(Set dst (ReverseBytesUS src));
12042 ins_cost(2*DEFAULT_COST);
12043
12044 expand %{
12045 immI16 imm31 %{ (int) 31 %}
12046 immI16 imm24 %{ (int) 24 %}
12047 immI16 imm16 %{ (int) 16 %}
12048 immI16 imm8 %{ (int) 8 %}
12049
12050 rlwinm(dst, src, imm24, imm24, imm31);
12051 insrwi(dst, src, imm8, imm16);
12052 %}
12053 %}
12054
12055 instruct bytes_reverse_short_Ex(iRegIdst dst, iRegIsrc src) %{
12056 match(Set dst (ReverseBytesS src));
12057 predicate(!UseByteReverseInstructions);
12058 ins_cost(3*DEFAULT_COST);
12059
12060 expand %{
12061 immI16 imm16 %{ (int) 16 %}
12062 immI16 imm8 %{ (int) 8 %}
12063 iRegLdst tmpI1;
12064
12065 urShiftI_reg_imm(tmpI1, src, imm8);
12066 insrwi(tmpI1, src, imm8, imm16);
12067 extsh(dst, tmpI1);
12068 %}
12069 %}
12070
12071 instruct bytes_reverse_short(iRegIdst dst, iRegIsrc src) %{
12072 match(Set dst (ReverseBytesS src));
12073 predicate(UseByteReverseInstructions);
12074 ins_cost(DEFAULT_COST);
12075 size(8);
12076
12077 format %{ "BRH $dst, $src\n\t"
12078 "EXTSH $dst, $dst" %}
12079
12080 ins_encode %{
12081 __ brh($dst$$Register, $src$$Register);
12082 __ extsh($dst$$Register, $dst$$Register);
12083 %}
12084 ins_pipe(pipe_class_default);
12085 %}
12086
12087 // Load Integer reversed byte order
12088 instruct loadI_reversed(iRegIdst dst, indirect mem) %{
12089 match(Set dst (ReverseBytesI (LoadI mem)));
12090 predicate(n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1)));
12091 ins_cost(MEMORY_REF_COST);
12092
12093 size(4);
12094 ins_encode %{
12095 __ lwbrx($dst$$Register, $mem$$Register);
12096 %}
12097 ins_pipe(pipe_class_default);
12098 %}
12099
12100 instruct loadI_reversed_acquire(iRegIdst dst, indirect mem) %{
12101 match(Set dst (ReverseBytesI (LoadI mem)));
12102 ins_cost(2 * MEMORY_REF_COST);
12103
12104 size(12);
12105 ins_encode %{
12106 __ lwbrx($dst$$Register, $mem$$Register);
12107 __ twi_0($dst$$Register);
12108 __ isync();
12109 %}
12110 ins_pipe(pipe_class_default);
12111 %}
12112
12113 // Load Long - aligned and reversed
12114 instruct loadL_reversed(iRegLdst dst, indirect mem) %{
12115 match(Set dst (ReverseBytesL (LoadL mem)));
12116 predicate((n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1))));
12117 ins_cost(MEMORY_REF_COST);
12118
12119 size(4);
12120 ins_encode %{
12121 __ ldbrx($dst$$Register, $mem$$Register);
12122 %}
12123 ins_pipe(pipe_class_default);
12124 %}
12125
12126 instruct loadL_reversed_acquire(iRegLdst dst, indirect mem) %{
12127 match(Set dst (ReverseBytesL (LoadL mem)));
12128 ins_cost(2 * MEMORY_REF_COST);
12129
12130 size(12);
12131 ins_encode %{
12132 __ ldbrx($dst$$Register, $mem$$Register);
12133 __ twi_0($dst$$Register);
12134 __ isync();
12135 %}
12136 ins_pipe(pipe_class_default);
12137 %}
12138
12139 // Load unsigned short / char reversed byte order
12140 instruct loadUS_reversed(iRegIdst dst, indirect mem) %{
12141 match(Set dst (ReverseBytesUS (LoadUS mem)));
12142 predicate(n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1)));
12143 ins_cost(MEMORY_REF_COST);
12144
12145 size(4);
12146 ins_encode %{
12147 __ lhbrx($dst$$Register, $mem$$Register);
12148 %}
12149 ins_pipe(pipe_class_default);
12150 %}
12151
12152 instruct loadUS_reversed_acquire(iRegIdst dst, indirect mem) %{
12153 match(Set dst (ReverseBytesUS (LoadUS mem)));
12154 ins_cost(2 * MEMORY_REF_COST);
12155
12156 size(12);
12157 ins_encode %{
12158 __ lhbrx($dst$$Register, $mem$$Register);
12159 __ twi_0($dst$$Register);
12160 __ isync();
12161 %}
12162 ins_pipe(pipe_class_default);
12163 %}
12164
12165 // Load short reversed byte order
12166 instruct loadS_reversed(iRegIdst dst, indirect mem) %{
12167 match(Set dst (ReverseBytesS (LoadS mem)));
12168 predicate(n->in(1)->as_Load()->is_unordered() || followed_by_acquire(n->in(1)));
12169 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
12170
12171 size(8);
12172 ins_encode %{
12173 __ lhbrx($dst$$Register, $mem$$Register);
12174 __ extsh($dst$$Register, $dst$$Register);
12175 %}
12176 ins_pipe(pipe_class_default);
12177 %}
12178
12179 instruct loadS_reversed_acquire(iRegIdst dst, indirect mem) %{
12180 match(Set dst (ReverseBytesS (LoadS mem)));
12181 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
12182
12183 size(16);
12184 ins_encode %{
12185 __ lhbrx($dst$$Register, $mem$$Register);
12186 __ twi_0($dst$$Register);
12187 __ extsh($dst$$Register, $dst$$Register);
12188 __ isync();
12189 %}
12190 ins_pipe(pipe_class_default);
12191 %}
12192
12193 // Store Integer reversed byte order
12194 instruct storeI_reversed(iRegIsrc src, indirect mem) %{
12195 match(Set mem (StoreI mem (ReverseBytesI src)));
12196 ins_cost(MEMORY_REF_COST);
12197
12198 size(4);
12199 ins_encode %{
12200 __ stwbrx($src$$Register, $mem$$Register);
12201 %}
12202 ins_pipe(pipe_class_default);
12203 %}
12204
12205 // Store Long reversed byte order
12206 instruct storeL_reversed(iRegLsrc src, indirect mem) %{
12207 match(Set mem (StoreL mem (ReverseBytesL src)));
12208 ins_cost(MEMORY_REF_COST);
12209
12210 size(4);
12211 ins_encode %{
12212 __ stdbrx($src$$Register, $mem$$Register);
12213 %}
12214 ins_pipe(pipe_class_default);
12215 %}
12216
12217 // Store unsigned short / char reversed byte order
12218 instruct storeUS_reversed(iRegIsrc src, indirect mem) %{
12219 match(Set mem (StoreC mem (ReverseBytesUS src)));
12220 ins_cost(MEMORY_REF_COST);
12221
12222 size(4);
12223 ins_encode %{
12224 __ sthbrx($src$$Register, $mem$$Register);
12225 %}
12226 ins_pipe(pipe_class_default);
12227 %}
12228
12229 // Store short reversed byte order
12230 instruct storeS_reversed(iRegIsrc src, indirect mem) %{
12231 match(Set mem (StoreC mem (ReverseBytesS src)));
12232 ins_cost(MEMORY_REF_COST);
12233
12234 size(4);
12235 ins_encode %{
12236 __ sthbrx($src$$Register, $mem$$Register);
12237 %}
12238 ins_pipe(pipe_class_default);
12239 %}
12240
12241 instruct mtvsrwz(vecX temp1, iRegIsrc src) %{
12242 effect(DEF temp1, USE src);
12243
12244 format %{ "MTVSRWZ $temp1, $src \t// Move to 16-byte register" %}
12245 size(4);
12246 ins_encode %{
12247 __ mtvsrwz($temp1$$VectorRegister->to_vsr(), $src$$Register);
12248 %}
12249 ins_pipe(pipe_class_default);
12250 %}
12251
12252 instruct xxspltw(vecX dst, vecX src, immI8 imm1) %{
12253 effect(DEF dst, USE src, USE imm1);
12254
12255 format %{ "XXSPLTW $dst, $src, $imm1 \t// Splat word" %}
12256 size(4);
12257 ins_encode %{
12258 __ xxspltw($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr(), $imm1$$constant);
12259 %}
12260 ins_pipe(pipe_class_default);
12261 %}
12262
12263 instruct xscvdpspn_regF(vecX dst, regF src) %{
12264 effect(DEF dst, USE src);
12265
12266 format %{ "XSCVDPSPN $dst, $src \t// Convert scalar single precision to vector single precision" %}
12267 size(4);
12268 ins_encode %{
12269 __ xscvdpspn($dst$$VectorRegister->to_vsr(), $src$$FloatRegister->to_vsr());
12270 %}
12271 ins_pipe(pipe_class_default);
12272 %}
12273
12274 //---------- Replicate Vector Instructions ------------------------------------
12275
12276 // Insrdi does replicate if src == dst.
12277 instruct repl32(iRegLdst dst) %{
12278 predicate(false);
12279 effect(USE_DEF dst);
12280
12281 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
12282 size(4);
12283 ins_encode %{
12284 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
12285 %}
12286 ins_pipe(pipe_class_default);
12287 %}
12288
12289 // Insrdi does replicate if src == dst.
12290 instruct repl48(iRegLdst dst) %{
12291 predicate(false);
12292 effect(USE_DEF dst);
12293
12294 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
12295 size(4);
12296 ins_encode %{
12297 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
12298 %}
12299 ins_pipe(pipe_class_default);
12300 %}
12301
12302 // Insrdi does replicate if src == dst.
12303 instruct repl56(iRegLdst dst) %{
12304 predicate(false);
12305 effect(USE_DEF dst);
12306
12307 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
12308 size(4);
12309 ins_encode %{
12310 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
12311 %}
12312 ins_pipe(pipe_class_default);
12313 %}
12314
12315 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12316 match(Set dst (Replicate src));
12317 predicate(n->as_Vector()->length() == 8 &&
12318 Matcher::vector_element_basic_type(n) == T_BYTE);
12319 expand %{
12320 moveReg(dst, src);
12321 repl56(dst);
12322 repl48(dst);
12323 repl32(dst);
12324 %}
12325 %}
12326
12327 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
12328 match(Set dst (Replicate zero));
12329 predicate(n->as_Vector()->length() == 8 &&
12330 Matcher::vector_element_basic_type(n) == T_BYTE);
12331 format %{ "LI $dst, #0 \t// replicate8B" %}
12332 size(4);
12333 ins_encode %{
12334 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12335 %}
12336 ins_pipe(pipe_class_default);
12337 %}
12338
12339 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
12340 match(Set dst (Replicate src));
12341 predicate(n->as_Vector()->length() == 8 &&
12342 Matcher::vector_element_basic_type(n) == T_BYTE);
12343 format %{ "LI $dst, #-1 \t// replicate8B" %}
12344 size(4);
12345 ins_encode %{
12346 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12347 %}
12348 ins_pipe(pipe_class_default);
12349 %}
12350
12351 instruct repl16B_reg_Ex(vecX dst, iRegIsrc src) %{
12352 match(Set dst (Replicate src));
12353 predicate(n->as_Vector()->length() == 16 &&
12354 Matcher::vector_element_basic_type(n) == T_BYTE);
12355
12356 expand %{
12357 iRegLdst tmpL;
12358 vecX tmpV;
12359 immI8 imm1 %{ (int) 1 %}
12360 moveReg(tmpL, src);
12361 repl56(tmpL);
12362 repl48(tmpL);
12363 mtvsrwz(tmpV, tmpL);
12364 xxspltw(dst, tmpV, imm1);
12365 %}
12366 %}
12367
12368 instruct repl16B_immI0(vecX dst, immI_0 zero) %{
12369 match(Set dst (Replicate zero));
12370 predicate(n->as_Vector()->length() == 16 &&
12371 Matcher::vector_element_basic_type(n) == T_BYTE);
12372
12373 format %{ "XXLXOR $dst, $zero \t// replicate16B" %}
12374 size(4);
12375 ins_encode %{
12376 __ xxlxor($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
12377 %}
12378 ins_pipe(pipe_class_default);
12379 %}
12380
12381 instruct repl16B_immIminus1(vecX dst, immI_minus1 src) %{
12382 match(Set dst (Replicate src));
12383 predicate(n->as_Vector()->length() == 16 &&
12384 Matcher::vector_element_basic_type(n) == T_BYTE);
12385
12386 format %{ "XXLEQV $dst, $src \t// replicate16B" %}
12387 size(4);
12388 ins_encode %{
12389 __ xxleqv($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
12390 %}
12391 ins_pipe(pipe_class_default);
12392 %}
12393
12394 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12395 match(Set dst (Replicate src));
12396 predicate(n->as_Vector()->length() == 4 &&
12397 Matcher::vector_element_basic_type(n) == T_SHORT);
12398 expand %{
12399 moveReg(dst, src);
12400 repl48(dst);
12401 repl32(dst);
12402 %}
12403 %}
12404
12405 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
12406 match(Set dst (Replicate zero));
12407 predicate(n->as_Vector()->length() == 4 &&
12408 Matcher::vector_element_basic_type(n) == T_SHORT);
12409 format %{ "LI $dst, #0 \t// replicate4S" %}
12410 size(4);
12411 ins_encode %{
12412 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12413 %}
12414 ins_pipe(pipe_class_default);
12415 %}
12416
12417 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
12418 match(Set dst (Replicate src));
12419 predicate(n->as_Vector()->length() == 4 &&
12420 Matcher::vector_element_basic_type(n) == T_SHORT);
12421 format %{ "LI $dst, -1 \t// replicate4S" %}
12422 size(4);
12423 ins_encode %{
12424 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12425 %}
12426 ins_pipe(pipe_class_default);
12427 %}
12428
12429 instruct repl8S_reg_Ex(vecX dst, iRegIsrc src) %{
12430 match(Set dst (Replicate src));
12431 predicate(n->as_Vector()->length() == 8 &&
12432 Matcher::vector_element_basic_type(n) == T_SHORT);
12433
12434 expand %{
12435 iRegLdst tmpL;
12436 vecX tmpV;
12437 immI8 zero %{ (int) 0 %}
12438 moveReg(tmpL, src);
12439 repl48(tmpL);
12440 repl32(tmpL);
12441 mtvsrd(tmpV, tmpL);
12442 xxpermdi(dst, tmpV, tmpV, zero);
12443 %}
12444 %}
12445
12446 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
12447 match(Set dst (Replicate zero));
12448 predicate(n->as_Vector()->length() == 8 &&
12449 Matcher::vector_element_basic_type(n) == T_SHORT);
12450
12451 format %{ "XXLXOR $dst, $zero \t// replicate8S" %}
12452 size(4);
12453 ins_encode %{
12454 __ xxlxor($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
12455 %}
12456 ins_pipe(pipe_class_default);
12457 %}
12458
12459 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
12460 match(Set dst (Replicate src));
12461 predicate(n->as_Vector()->length() == 8 &&
12462 Matcher::vector_element_basic_type(n) == T_SHORT);
12463
12464 format %{ "XXLEQV $dst, $src \t// replicate8S" %}
12465 size(4);
12466 ins_encode %{
12467 __ xxleqv($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
12468 %}
12469 ins_pipe(pipe_class_default);
12470 %}
12471
12472 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12473 match(Set dst (Replicate src));
12474 predicate(n->as_Vector()->length() == 2 &&
12475 Matcher::vector_element_basic_type(n) == T_INT);
12476 ins_cost(2 * DEFAULT_COST);
12477 expand %{
12478 moveReg(dst, src);
12479 repl32(dst);
12480 %}
12481 %}
12482
12483 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
12484 match(Set dst (Replicate zero));
12485 predicate(n->as_Vector()->length() == 2 &&
12486 Matcher::vector_element_basic_type(n) == T_INT);
12487 format %{ "LI $dst, #0 \t// replicate2I" %}
12488 size(4);
12489 ins_encode %{
12490 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12491 %}
12492 ins_pipe(pipe_class_default);
12493 %}
12494
12495 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
12496 match(Set dst (Replicate src));
12497 predicate(n->as_Vector()->length() == 2 &&
12498 Matcher::vector_element_basic_type(n) == T_INT);
12499 format %{ "LI $dst, -1 \t// replicate2I" %}
12500 size(4);
12501 ins_encode %{
12502 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12503 %}
12504 ins_pipe(pipe_class_default);
12505 %}
12506
12507 instruct repl4I_reg_Ex(vecX dst, iRegIsrc src) %{
12508 match(Set dst (Replicate src));
12509 predicate(n->as_Vector()->length() == 4 &&
12510 Matcher::vector_element_basic_type(n) == T_INT);
12511 ins_cost(2 * DEFAULT_COST);
12512
12513 expand %{
12514 iRegLdst tmpL;
12515 vecX tmpV;
12516 immI8 zero %{ (int) 0 %}
12517 moveReg(tmpL, src);
12518 repl32(tmpL);
12519 mtvsrd(tmpV, tmpL);
12520 xxpermdi(dst, tmpV, tmpV, zero);
12521 %}
12522 %}
12523
12524 instruct repl4I_immI0(vecX dst, immI_0 zero) %{
12525 match(Set dst (Replicate zero));
12526 predicate(n->as_Vector()->length() == 4 &&
12527 Matcher::vector_element_basic_type(n) == T_INT);
12528
12529 format %{ "XXLXOR $dst, $zero \t// replicate4I" %}
12530 size(4);
12531 ins_encode %{
12532 __ xxlxor($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
12533 %}
12534 ins_pipe(pipe_class_default);
12535 %}
12536
12537 instruct repl4I_immIminus1(vecX dst, immI_minus1 src) %{
12538 match(Set dst (Replicate src));
12539 predicate(n->as_Vector()->length() == 4 &&
12540 Matcher::vector_element_basic_type(n) == T_INT);
12541
12542 format %{ "XXLEQV $dst, $dst, $dst \t// replicate4I" %}
12543 size(4);
12544 ins_encode %{
12545 __ xxleqv($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
12546 %}
12547 ins_pipe(pipe_class_default);
12548 %}
12549
12550 // Move float to int register via stack, replicate.
12551 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
12552 match(Set dst (Replicate src));
12553 predicate(n->as_Vector()->length() == 2 &&
12554 Matcher::vector_element_basic_type(n) == T_FLOAT);
12555 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
12556 expand %{
12557 stackSlotL tmpS;
12558 iRegIdst tmpI;
12559 moveF2I_reg_stack(tmpS, src); // Move float to stack.
12560 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
12561 moveReg(dst, tmpI); // Move int to long reg.
12562 repl32(dst); // Replicate bitpattern.
12563 %}
12564 %}
12565
12566 // Replicate scalar constant to packed float values in Double register
12567 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
12568 match(Set dst (Replicate src));
12569 predicate(n->as_Vector()->length() == 2 &&
12570 Matcher::vector_element_basic_type(n) == T_FLOAT);
12571 ins_cost(5 * DEFAULT_COST);
12572
12573 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
12574 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
12575 %}
12576
12577 // Replicate scalar zero constant to packed float values in Double register
12578 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
12579 match(Set dst (Replicate zero));
12580 predicate(n->as_Vector()->length() == 2 &&
12581 Matcher::vector_element_basic_type(n) == T_FLOAT);
12582
12583 format %{ "LI $dst, #0 \t// replicate2F" %}
12584 size(4);
12585 ins_encode %{
12586 __ li($dst$$Register, 0x0);
12587 %}
12588 ins_pipe(pipe_class_default);
12589 %}
12590
12591
12592 //----------Vector Arithmetic Instructions--------------------------------------
12593
12594 // Vector Addition Instructions
12595
12596 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
12597 match(Set dst (AddVB src1 src2));
12598 predicate(n->as_Vector()->length() == 16);
12599 format %{ "VADDUBM $dst,$src1,$src2\t// add packed16B" %}
12600 size(4);
12601 ins_encode %{
12602 __ vaddubm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12603 %}
12604 ins_pipe(pipe_class_default);
12605 %}
12606
12607 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
12608 match(Set dst (AddVS src1 src2));
12609 predicate(n->as_Vector()->length() == 8);
12610 format %{ "VADDUHM $dst,$src1,$src2\t// add packed8S" %}
12611 size(4);
12612 ins_encode %{
12613 __ vadduhm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12614 %}
12615 ins_pipe(pipe_class_default);
12616 %}
12617
12618 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
12619 match(Set dst (AddVI src1 src2));
12620 predicate(n->as_Vector()->length() == 4);
12621 format %{ "VADDUWM $dst,$src1,$src2\t// add packed4I" %}
12622 size(4);
12623 ins_encode %{
12624 __ vadduwm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12625 %}
12626 ins_pipe(pipe_class_default);
12627 %}
12628
12629 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
12630 match(Set dst (AddVF src1 src2));
12631 predicate(n->as_Vector()->length() == 4);
12632 format %{ "VADDFP $dst,$src1,$src2\t// add packed4F" %}
12633 size(4);
12634 ins_encode %{
12635 __ vaddfp($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12636 %}
12637 ins_pipe(pipe_class_default);
12638 %}
12639
12640 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
12641 match(Set dst (AddVL src1 src2));
12642 predicate(n->as_Vector()->length() == 2);
12643 format %{ "VADDUDM $dst,$src1,$src2\t// add packed2L" %}
12644 size(4);
12645 ins_encode %{
12646 __ vaddudm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12647 %}
12648 ins_pipe(pipe_class_default);
12649 %}
12650
12651 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
12652 match(Set dst (AddVD src1 src2));
12653 predicate(n->as_Vector()->length() == 2);
12654 format %{ "XVADDDP $dst,$src1,$src2\t// add packed2D" %}
12655 size(4);
12656 ins_encode %{
12657 __ xvadddp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
12658 %}
12659 ins_pipe(pipe_class_default);
12660 %}
12661
12662 // Vector Subtraction Instructions
12663
12664 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
12665 match(Set dst (SubVB src1 src2));
12666 predicate(n->as_Vector()->length() == 16);
12667 format %{ "VSUBUBM $dst,$src1,$src2\t// sub packed16B" %}
12668 size(4);
12669 ins_encode %{
12670 __ vsububm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12671 %}
12672 ins_pipe(pipe_class_default);
12673 %}
12674
12675 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
12676 match(Set dst (SubVS src1 src2));
12677 predicate(n->as_Vector()->length() == 8);
12678 format %{ "VSUBUHM $dst,$src1,$src2\t// sub packed8S" %}
12679 size(4);
12680 ins_encode %{
12681 __ vsubuhm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12682 %}
12683 ins_pipe(pipe_class_default);
12684 %}
12685
12686 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
12687 match(Set dst (SubVI src1 src2));
12688 predicate(n->as_Vector()->length() == 4);
12689 format %{ "VSUBUWM $dst,$src1,$src2\t// sub packed4I" %}
12690 size(4);
12691 ins_encode %{
12692 __ vsubuwm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12693 %}
12694 ins_pipe(pipe_class_default);
12695 %}
12696
12697 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
12698 match(Set dst (SubVF src1 src2));
12699 predicate(n->as_Vector()->length() == 4);
12700 format %{ "VSUBFP $dst,$src1,$src2\t// sub packed4F" %}
12701 size(4);
12702 ins_encode %{
12703 __ vsubfp($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12704 %}
12705 ins_pipe(pipe_class_default);
12706 %}
12707
12708 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
12709 match(Set dst (SubVL src1 src2));
12710 predicate(n->as_Vector()->length() == 2);
12711 format %{ "VSUBUDM $dst,$src1,$src2\t// sub packed2L" %}
12712 size(4);
12713 ins_encode %{
12714 __ vsubudm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12715 %}
12716 ins_pipe(pipe_class_default);
12717 %}
12718
12719 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
12720 match(Set dst (SubVD src1 src2));
12721 predicate(n->as_Vector()->length() == 2);
12722 format %{ "XVSUBDP $dst,$src1,$src2\t// sub packed2D" %}
12723 size(4);
12724 ins_encode %{
12725 __ xvsubdp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
12726 %}
12727 ins_pipe(pipe_class_default);
12728 %}
12729
12730 // Vector Multiplication Instructions
12731
12732 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2, vecX tmp) %{
12733 match(Set dst (MulVS src1 src2));
12734 predicate(n->as_Vector()->length() == 8);
12735 effect(TEMP tmp);
12736 format %{ "VSPLTISH $tmp,0\t// mul packed8S" %}
12737 format %{ "VMLADDUHM $dst,$src1,$src2\t// mul packed8S" %}
12738 size(8);
12739 ins_encode %{
12740 __ vspltish($tmp$$VectorRegister, 0);
12741 __ vmladduhm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister, $tmp$$VectorRegister);
12742 %}
12743 ins_pipe(pipe_class_default);
12744 %}
12745
12746 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
12747 match(Set dst (MulVI src1 src2));
12748 predicate(n->as_Vector()->length() == 4);
12749 format %{ "VMULUWM $dst,$src1,$src2\t// mul packed4I" %}
12750 size(4);
12751 ins_encode %{
12752 __ vmuluwm($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12753 %}
12754 ins_pipe(pipe_class_default);
12755 %}
12756
12757 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
12758 match(Set dst (MulVF src1 src2));
12759 predicate(n->as_Vector()->length() == 4);
12760 format %{ "XVMULSP $dst,$src1,$src2\t// mul packed4F" %}
12761 size(4);
12762 ins_encode %{
12763 __ xvmulsp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
12764 %}
12765 ins_pipe(pipe_class_default);
12766 %}
12767
12768 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
12769 match(Set dst (MulVD src1 src2));
12770 predicate(n->as_Vector()->length() == 2);
12771 format %{ "XVMULDP $dst,$src1,$src2\t// mul packed2D" %}
12772 size(4);
12773 ins_encode %{
12774 __ xvmuldp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
12775 %}
12776 ins_pipe(pipe_class_default);
12777 %}
12778
12779 // Vector Division Instructions
12780
12781 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
12782 match(Set dst (DivVF src1 src2));
12783 predicate(n->as_Vector()->length() == 4);
12784 format %{ "XVDIVSP $dst,$src1,$src2\t// div packed4F" %}
12785 size(4);
12786 ins_encode %{
12787 __ xvdivsp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
12788 %}
12789 ins_pipe(pipe_class_default);
12790 %}
12791
12792 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
12793 match(Set dst (DivVD src1 src2));
12794 predicate(n->as_Vector()->length() == 2);
12795 format %{ "XVDIVDP $dst,$src1,$src2\t// div packed2D" %}
12796 size(4);
12797 ins_encode %{
12798 __ xvdivdp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
12799 %}
12800 ins_pipe(pipe_class_default);
12801 %}
12802
12803 // Vector Min / Max Instructions
12804
12805 instruct vmin_reg(vecX dst, vecX src1, vecX src2) %{
12806 match(Set dst (MinV src1 src2));
12807 format %{ "VMIN $dst,$src1,$src2\t// vector min" %}
12808 size(4);
12809 ins_encode %{
12810 BasicType bt = Matcher::vector_element_basic_type(this);
12811 switch (bt) {
12812 case T_INT:
12813 __ vminsw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12814 break;
12815 case T_LONG:
12816 __ vminsd($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12817 break;
12818 default:
12819 ShouldNotReachHere();
12820 }
12821 %}
12822 ins_pipe(pipe_class_default);
12823 %}
12824
12825 instruct vmax_reg(vecX dst, vecX src1, vecX src2) %{
12826 match(Set dst (MaxV src1 src2));
12827 format %{ "VMAX $dst,$src1,$src2\t// vector max" %}
12828 size(4);
12829 ins_encode %{
12830 BasicType bt = Matcher::vector_element_basic_type(this);
12831 switch (bt) {
12832 case T_INT:
12833 __ vmaxsw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12834 break;
12835 case T_LONG:
12836 __ vmaxsd($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12837 break;
12838 default:
12839 ShouldNotReachHere();
12840 }
12841 %}
12842 ins_pipe(pipe_class_default);
12843 %}
12844
12845 instruct vminu_reg(vecX dst, vecX src1, vecX src2) %{
12846 match(Set dst (UMinV src1 src2));
12847 format %{ "VMINU $dst,$src1,$src2\t// vector unsigned min" %}
12848 size(4);
12849 ins_encode %{
12850 BasicType bt = Matcher::vector_element_basic_type(this);
12851 switch (bt) {
12852 case T_INT:
12853 __ vminuw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12854 break;
12855 case T_LONG:
12856 __ vminud($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12857 break;
12858 default:
12859 ShouldNotReachHere();
12860 }
12861 %}
12862 ins_pipe(pipe_class_default);
12863 %}
12864
12865 instruct vmaxu_reg(vecX dst, vecX src1, vecX src2) %{
12866 match(Set dst (UMaxV src1 src2));
12867 format %{ "VMAXU $dst,$src1,$src2\t// vector unsigned max" %}
12868 size(4);
12869 ins_encode %{
12870 BasicType bt = Matcher::vector_element_basic_type(this);
12871 switch (bt) {
12872 case T_INT:
12873 __ vmaxuw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12874 break;
12875 case T_LONG:
12876 __ vmaxud($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12877 break;
12878 default:
12879 ShouldNotReachHere();
12880 }
12881 %}
12882 ins_pipe(pipe_class_default);
12883 %}
12884
12885 instruct vand(vecX dst, vecX src1, vecX src2) %{
12886 match(Set dst (AndV src1 src2));
12887 size(4);
12888 format %{ "VAND $dst,$src1,$src2\t// and vectors" %}
12889 ins_encode %{
12890 __ vand($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12891 %}
12892 ins_pipe(pipe_class_default);
12893 %}
12894
12895 instruct vor(vecX dst, vecX src1, vecX src2) %{
12896 match(Set dst (OrV src1 src2));
12897 size(4);
12898 format %{ "VOR $dst,$src1,$src2\t// or vectors" %}
12899 ins_encode %{
12900 __ vor($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12901 %}
12902 ins_pipe(pipe_class_default);
12903 %}
12904
12905 instruct vxor(vecX dst, vecX src1, vecX src2) %{
12906 match(Set dst (XorV src1 src2));
12907 size(4);
12908 format %{ "VXOR $dst,$src1,$src2\t// xor vectors" %}
12909 ins_encode %{
12910 __ vxor($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
12911 %}
12912 ins_pipe(pipe_class_default);
12913 %}
12914
12915 instruct reductionI_arith_logic(iRegIdst dst, iRegIsrc srcInt, vecX srcVec, vecX tmp1, vecX tmp2) %{
12916 predicate(Matcher::vector_element_basic_type(n->in(2)) == T_INT);
12917 match(Set dst (AddReductionVI srcInt srcVec));
12918 match(Set dst (MulReductionVI srcInt srcVec));
12919 match(Set dst (AndReductionV srcInt srcVec));
12920 match(Set dst ( OrReductionV srcInt srcVec));
12921 match(Set dst (XorReductionV srcInt srcVec));
12922 effect(TEMP tmp1, TEMP tmp2);
12923 ins_cost(DEFAULT_COST * 6);
12924 format %{ "REDUCEI_ARITH_LOGIC // $dst,$srcInt,$srcVec,$tmp1,$tmp2\t// reduce vector int add/mul/and/or/xor" %}
12925 size(24);
12926 ins_encode %{
12927 int opcode = this->ideal_Opcode();
12928 __ reduceI(opcode, $dst$$Register, $srcInt$$Register, $srcVec$$VectorRegister,
12929 $tmp1$$VectorRegister, $tmp2$$VectorRegister);
12930 %}
12931 ins_pipe(pipe_class_default);
12932 %}
12933
12934 instruct reductionI_min_max(iRegIdst dst, iRegIsrc srcInt, vecX srcVec, vecX tmp1, vecX tmp2, flagsRegCR0 cr0) %{
12935 predicate(Matcher::vector_element_basic_type(n->in(2)) == T_INT);
12936 match(Set dst (MinReductionV srcInt srcVec));
12937 match(Set dst (MaxReductionV srcInt srcVec));
12938 effect(TEMP tmp1, TEMP tmp2, KILL cr0);
12939 ins_cost(DEFAULT_COST * 7);
12940 format %{ "REDUCEI_MINMAX // $dst,$srcInt,$srcVec,$tmp1,$tmp2,cr0\t// reduce vector int min/max" %}
12941 size(28);
12942 ins_encode %{
12943 int opcode = this->ideal_Opcode();
12944 __ reduceI(opcode, $dst$$Register, $srcInt$$Register, $srcVec$$VectorRegister,
12945 $tmp1$$VectorRegister, $tmp2$$VectorRegister);
12946 %}
12947 ins_pipe(pipe_class_default);
12948 %}
12949
12950 // Vector Absolute Instructions
12951
12952 instruct vabs4F_reg(vecX dst, vecX src) %{
12953 match(Set dst (AbsVF src));
12954 predicate(n->as_Vector()->length() == 4);
12955 format %{ "XVABSSP $dst,$src\t// absolute packed4F" %}
12956 size(4);
12957 ins_encode %{
12958 __ xvabssp($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
12959 %}
12960 ins_pipe(pipe_class_default);
12961 %}
12962
12963 instruct vabs2D_reg(vecX dst, vecX src) %{
12964 match(Set dst (AbsVD src));
12965 predicate(n->as_Vector()->length() == 2);
12966 format %{ "XVABSDP $dst,$src\t// absolute packed2D" %}
12967 size(4);
12968 ins_encode %{
12969 __ xvabsdp($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
12970 %}
12971 ins_pipe(pipe_class_default);
12972 %}
12973
12974 // Round Instructions
12975 instruct roundD_reg(regD dst, regD src, immI8 rmode) %{
12976 match(Set dst (RoundDoubleMode src rmode));
12977 format %{ "RoundDoubleMode $src,$rmode" %}
12978 size(4);
12979 ins_encode %{
12980 switch ($rmode$$constant) {
12981 case RoundDoubleModeNode::rmode_rint:
12982 __ xvrdpic($dst$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr());
12983 break;
12984 case RoundDoubleModeNode::rmode_floor:
12985 __ frim($dst$$FloatRegister, $src$$FloatRegister);
12986 break;
12987 case RoundDoubleModeNode::rmode_ceil:
12988 __ frip($dst$$FloatRegister, $src$$FloatRegister);
12989 break;
12990 default:
12991 ShouldNotReachHere();
12992 }
12993 %}
12994 ins_pipe(pipe_class_default);
12995 %}
12996
12997 // Vector Round Instructions
12998 instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
12999 match(Set dst (RoundDoubleModeV src rmode));
13000 predicate(n->as_Vector()->length() == 2);
13001 format %{ "RoundDoubleModeV $src,$rmode" %}
13002 size(4);
13003 ins_encode %{
13004 switch ($rmode$$constant) {
13005 case RoundDoubleModeNode::rmode_rint:
13006 __ xvrdpic($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13007 break;
13008 case RoundDoubleModeNode::rmode_floor:
13009 __ xvrdpim($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13010 break;
13011 case RoundDoubleModeNode::rmode_ceil:
13012 __ xvrdpip($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13013 break;
13014 default:
13015 ShouldNotReachHere();
13016 }
13017 %}
13018 ins_pipe(pipe_class_default);
13019 %}
13020
13021 // Vector Negate Instructions
13022
13023 instruct vneg4F_reg(vecX dst, vecX src) %{
13024 match(Set dst (NegVF src));
13025 predicate(n->as_Vector()->length() == 4);
13026 format %{ "XVNEGSP $dst,$src\t// negate packed4F" %}
13027 size(4);
13028 ins_encode %{
13029 __ xvnegsp($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13030 %}
13031 ins_pipe(pipe_class_default);
13032 %}
13033
13034 instruct vneg2D_reg(vecX dst, vecX src) %{
13035 match(Set dst (NegVD src));
13036 predicate(n->as_Vector()->length() == 2);
13037 format %{ "XVNEGDP $dst,$src\t// negate packed2D" %}
13038 size(4);
13039 ins_encode %{
13040 __ xvnegdp($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13041 %}
13042 ins_pipe(pipe_class_default);
13043 %}
13044
13045 instruct vneg4I_reg(vecX dst, vecX src) %{
13046 match(Set dst (NegVI src));
13047 predicate(Matcher::vector_element_basic_type(n) == T_INT);
13048 format %{ "VNEGW $dst,$src\t// negate int vector" %}
13049 size(4);
13050 ins_encode %{
13051 __ vnegw($dst$$VectorRegister, $src$$VectorRegister);
13052 %}
13053 ins_pipe(pipe_class_default);
13054 %}
13055
13056 // Vector Square Root Instructions
13057
13058 instruct vsqrt4F_reg(vecX dst, vecX src) %{
13059 match(Set dst (SqrtVF src));
13060 predicate(n->as_Vector()->length() == 4);
13061 format %{ "XVSQRTSP $dst,$src\t// sqrt packed4F" %}
13062 size(4);
13063 ins_encode %{
13064 __ xvsqrtsp($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13065 %}
13066 ins_pipe(pipe_class_default);
13067 %}
13068
13069 instruct vsqrt2D_reg(vecX dst, vecX src) %{
13070 match(Set dst (SqrtVD src));
13071 predicate(n->as_Vector()->length() == 2);
13072 format %{ "XVSQRTDP $dst,$src\t// sqrt packed2D" %}
13073 size(4);
13074 ins_encode %{
13075 __ xvsqrtdp($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr());
13076 %}
13077 ins_pipe(pipe_class_default);
13078 %}
13079
13080 // Vector Population Count and Zeros Count Instructions
13081
13082 instruct vpopcnt_reg(vecX dst, vecX src) %{
13083 match(Set dst (PopCountVI src));
13084 match(Set dst (PopCountVL src));
13085 format %{ "VPOPCNT $dst,$src\t// pop count packed" %}
13086 size(4);
13087 ins_encode %{
13088 BasicType bt = Matcher::vector_element_basic_type(this);
13089 switch (bt) {
13090 case T_BYTE:
13091 __ vpopcntb($dst$$VectorRegister, $src$$VectorRegister);
13092 break;
13093 case T_SHORT:
13094 __ vpopcnth($dst$$VectorRegister, $src$$VectorRegister);
13095 break;
13096 case T_INT:
13097 __ vpopcntw($dst$$VectorRegister, $src$$VectorRegister);
13098 break;
13099 case T_LONG:
13100 __ vpopcntd($dst$$VectorRegister, $src$$VectorRegister);
13101 break;
13102 default:
13103 ShouldNotReachHere();
13104 }
13105 %}
13106 ins_pipe(pipe_class_default);
13107 %}
13108
13109 instruct vcount_leading_zeros_reg(vecX dst, vecX src) %{
13110 match(Set dst (CountLeadingZerosV src));
13111 format %{ "VCLZ $dst,$src\t// leading zeros count packed" %}
13112 size(4);
13113 ins_encode %{
13114 BasicType bt = Matcher::vector_element_basic_type(this);
13115 switch (bt) {
13116 case T_BYTE:
13117 __ vclzb($dst$$VectorRegister, $src$$VectorRegister);
13118 break;
13119 case T_SHORT:
13120 __ vclzh($dst$$VectorRegister, $src$$VectorRegister);
13121 break;
13122 case T_INT:
13123 __ vclzw($dst$$VectorRegister, $src$$VectorRegister);
13124 break;
13125 case T_LONG:
13126 __ vclzd($dst$$VectorRegister, $src$$VectorRegister);
13127 break;
13128 default:
13129 ShouldNotReachHere();
13130 }
13131 %}
13132 ins_pipe(pipe_class_default);
13133 %}
13134
13135 instruct vcount_trailing_zeros_reg(vecX dst, vecX src) %{
13136 match(Set dst (CountTrailingZerosV src));
13137 format %{ "VCTZ $dst,$src\t// trailing zeros count packed" %}
13138 size(4);
13139 ins_encode %{
13140 BasicType bt = Matcher::vector_element_basic_type(this);
13141 switch (bt) {
13142 case T_BYTE:
13143 __ vctzb($dst$$VectorRegister, $src$$VectorRegister);
13144 break;
13145 case T_SHORT:
13146 __ vctzh($dst$$VectorRegister, $src$$VectorRegister);
13147 break;
13148 case T_INT:
13149 __ vctzw($dst$$VectorRegister, $src$$VectorRegister);
13150 break;
13151 case T_LONG:
13152 __ vctzd($dst$$VectorRegister, $src$$VectorRegister);
13153 break;
13154 default:
13155 ShouldNotReachHere();
13156 }
13157 %}
13158 ins_pipe(pipe_class_default);
13159 %}
13160
13161 // --------------------------------- FMA --------------------------------------
13162 // src1 * src2 + dst
13163 instruct vfma4F(vecX dst, vecX src1, vecX src2) %{
13164 match(Set dst (FmaVF dst (Binary src1 src2)));
13165 predicate(n->as_Vector()->length() == 4);
13166
13167 format %{ "XVMADDASP $dst, $src1, $src2" %}
13168
13169 size(4);
13170 ins_encode %{
13171 assert(UseFMA, "Needs FMA instructions support.");
13172 __ xvmaddasp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
13173 %}
13174 ins_pipe(pipe_class_default);
13175 %}
13176
13177 // src1 * (-src2) + dst
13178 // "(-src1) * src2 + dst" has been idealized to "src2 * (-src1) + dst"
13179 instruct vfma4F_neg1(vecX dst, vecX src1, vecX src2) %{
13180 match(Set dst (FmaVF dst (Binary src1 (NegVF src2))));
13181 predicate(n->as_Vector()->length() == 4);
13182
13183 format %{ "XVNMSUBASP $dst, $src1, $src2" %}
13184
13185 size(4);
13186 ins_encode %{
13187 assert(UseFMA, "Needs FMA instructions support.");
13188 __ xvnmsubasp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
13189 %}
13190 ins_pipe(pipe_class_default);
13191 %}
13192
13193 // src1 * src2 - dst
13194 instruct vfma4F_neg2(vecX dst, vecX src1, vecX src2) %{
13195 match(Set dst (FmaVF (NegVF dst) (Binary src1 src2)));
13196 predicate(n->as_Vector()->length() == 4);
13197
13198 format %{ "XVMSUBASP $dst, $src1, $src2" %}
13199
13200 size(4);
13201 ins_encode %{
13202 assert(UseFMA, "Needs FMA instructions support.");
13203 __ xvmsubasp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
13204 %}
13205 ins_pipe(pipe_class_default);
13206 %}
13207
13208 // src1 * src2 + dst
13209 instruct vfma2D(vecX dst, vecX src1, vecX src2) %{
13210 match(Set dst (FmaVD dst (Binary src1 src2)));
13211 predicate(n->as_Vector()->length() == 2);
13212
13213 format %{ "XVMADDADP $dst, $src1, $src2" %}
13214
13215 size(4);
13216 ins_encode %{
13217 assert(UseFMA, "Needs FMA instructions support.");
13218 __ xvmaddadp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
13219 %}
13220 ins_pipe(pipe_class_default);
13221 %}
13222
13223 // src1 * (-src2) + dst
13224 // "(-src1) * src2 + dst" has been idealized to "src2 * (-src1) + dst"
13225 instruct vfma2D_neg1(vecX dst, vecX src1, vecX src2) %{
13226 match(Set dst (FmaVD dst (Binary src1 (NegVD src2))));
13227 predicate(n->as_Vector()->length() == 2);
13228
13229 format %{ "XVNMSUBADP $dst, $src1, $src2" %}
13230
13231 size(4);
13232 ins_encode %{
13233 assert(UseFMA, "Needs FMA instructions support.");
13234 __ xvnmsubadp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
13235 %}
13236 ins_pipe(pipe_class_default);
13237 %}
13238
13239 // src1 * src2 - dst
13240 instruct vfma2D_neg2(vecX dst, vecX src1, vecX src2) %{
13241 match(Set dst (FmaVD (NegVD dst) (Binary src1 src2)));
13242 predicate(n->as_Vector()->length() == 2);
13243
13244 format %{ "XVMSUBADP $dst, $src1, $src2" %}
13245
13246 size(4);
13247 ins_encode %{
13248 assert(UseFMA, "Needs FMA instructions support.");
13249 __ xvmsubadp($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr());
13250 %}
13251 ins_pipe(pipe_class_default);
13252 %}
13253
13254 //----------Overflow Math Instructions-----------------------------------------
13255
13256 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
13257 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
13258 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
13259
13260 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13261 match(Set cr0 (OverflowAddL op1 op2));
13262
13263 format %{ "ADD_ $op1, $op2\t# overflow check long" %}
13264 size(12);
13265 ins_encode %{
13266 __ li(R0, 0);
13267 __ mtxer(R0); // clear XER.SO
13268 __ addo_(R0, $op1$$Register, $op2$$Register);
13269 %}
13270 ins_pipe(pipe_class_default);
13271 %}
13272
13273 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13274 match(Set cr0 (OverflowSubL op1 op2));
13275
13276 format %{ "SUBFO_ R0, $op2, $op1\t# overflow check long" %}
13277 size(12);
13278 ins_encode %{
13279 __ li(R0, 0);
13280 __ mtxer(R0); // clear XER.SO
13281 __ subfo_(R0, $op2$$Register, $op1$$Register);
13282 %}
13283 ins_pipe(pipe_class_default);
13284 %}
13285
13286 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
13287 match(Set cr0 (OverflowSubL zero op2));
13288
13289 format %{ "NEGO_ R0, $op2\t# overflow check long" %}
13290 size(12);
13291 ins_encode %{
13292 __ li(R0, 0);
13293 __ mtxer(R0); // clear XER.SO
13294 __ nego_(R0, $op2$$Register);
13295 %}
13296 ins_pipe(pipe_class_default);
13297 %}
13298
13299 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13300 match(Set cr0 (OverflowMulL op1 op2));
13301
13302 format %{ "MULLDO_ R0, $op1, $op2\t# overflow check long" %}
13303 size(12);
13304 ins_encode %{
13305 __ li(R0, 0);
13306 __ mtxer(R0); // clear XER.SO
13307 __ mulldo_(R0, $op1$$Register, $op2$$Register);
13308 %}
13309 ins_pipe(pipe_class_default);
13310 %}
13311
13312 instruct repl4F_reg_Ex(vecX dst, regF src) %{
13313 match(Set dst (Replicate src));
13314 predicate(n->as_Vector()->length() == 4 &&
13315 Matcher::vector_element_basic_type(n) == T_FLOAT);
13316 ins_cost(DEFAULT_COST);
13317 expand %{
13318 vecX tmpV;
13319 immI8 zero %{ (int) 0 %}
13320
13321 xscvdpspn_regF(tmpV, src);
13322 xxspltw(dst, tmpV, zero);
13323 %}
13324 %}
13325
13326 instruct repl4F_immF_Ex(vecX dst, immF src, iRegLdst tmp) %{
13327 match(Set dst (Replicate src));
13328 predicate(n->as_Vector()->length() == 4 &&
13329 Matcher::vector_element_basic_type(n) == T_FLOAT);
13330 effect(TEMP tmp);
13331 ins_cost(10 * DEFAULT_COST);
13332
13333 postalloc_expand( postalloc_expand_load_replF_constant_vsx(dst, src, constanttablebase, tmp) );
13334 %}
13335
13336 instruct repl4F_immF0(vecX dst, immF_0 zero) %{
13337 match(Set dst (Replicate zero));
13338 predicate(n->as_Vector()->length() == 4 &&
13339 Matcher::vector_element_basic_type(n) == T_FLOAT);
13340
13341 format %{ "XXLXOR $dst, $zero \t// replicate4F" %}
13342 size(4);
13343 ins_encode %{
13344 __ xxlxor($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
13345 %}
13346 ins_pipe(pipe_class_default);
13347 %}
13348
13349 instruct repl2D_reg_Ex(vecX dst, regD src) %{
13350 match(Set dst (Replicate src));
13351 predicate(n->as_Vector()->length() == 2 &&
13352 Matcher::vector_element_basic_type(n) == T_DOUBLE);
13353
13354 format %{ "XXPERMDI $dst, $src, $src, 0 \t// Splat doubleword" %}
13355 size(4);
13356 ins_encode %{
13357 __ xxpermdi($dst$$VectorRegister->to_vsr(), $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0);
13358 %}
13359 ins_pipe(pipe_class_default);
13360 %}
13361
13362 instruct repl2D_immD0(vecX dst, immD_0 zero) %{
13363 match(Set dst (Replicate zero));
13364 predicate(n->as_Vector()->length() == 2 &&
13365 Matcher::vector_element_basic_type(n) == T_DOUBLE);
13366
13367 format %{ "XXLXOR $dst, $zero \t// replicate2D" %}
13368 size(4);
13369 ins_encode %{
13370 __ xxlxor($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
13371 %}
13372 ins_pipe(pipe_class_default);
13373 %}
13374
13375 instruct mtvsrd(vecX dst, iRegLsrc src) %{
13376 predicate(false);
13377 effect(DEF dst, USE src);
13378
13379 format %{ "MTVSRD $dst, $src \t// Move to 16-byte register" %}
13380 size(4);
13381 ins_encode %{
13382 __ mtvsrd($dst$$VectorRegister->to_vsr(), $src$$Register);
13383 %}
13384 ins_pipe(pipe_class_default);
13385 %}
13386
13387 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
13388 effect(DEF dst, USE src, USE zero);
13389
13390 format %{ "XXSPLATD $dst, $src, $zero \t// Splat doubleword" %}
13391 size(4);
13392 ins_encode %{
13393 __ xxpermdi($dst$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr(), $src$$VectorRegister->to_vsr(), $zero$$constant);
13394 %}
13395 ins_pipe(pipe_class_default);
13396 %}
13397
13398 instruct xxpermdi(vecX dst, vecX src1, vecX src2, immI8 zero) %{
13399 effect(DEF dst, USE src1, USE src2, USE zero);
13400
13401 format %{ "XXPERMDI $dst, $src1, $src2, $zero \t// Splat doubleword" %}
13402 size(4);
13403 ins_encode %{
13404 __ xxpermdi($dst$$VectorRegister->to_vsr(), $src1$$VectorRegister->to_vsr(), $src2$$VectorRegister->to_vsr(), $zero$$constant);
13405 %}
13406 ins_pipe(pipe_class_default);
13407 %}
13408
13409 instruct repl2L_reg_Ex(vecX dst, iRegLsrc src) %{
13410 predicate(Matcher::vector_element_basic_type(n) == T_LONG);
13411 match(Set dst (Replicate src));
13412 predicate(n->as_Vector()->length() == 2);
13413 expand %{
13414 vecX tmpV;
13415 immI8 zero %{ (int) 0 %}
13416 mtvsrd(tmpV, src);
13417 xxpermdi(dst, tmpV, tmpV, zero);
13418 %}
13419 %}
13420
13421 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
13422 match(Set dst (Replicate zero));
13423 predicate(n->as_Vector()->length() == 2 &&
13424 Matcher::vector_element_basic_type(n) == T_LONG);
13425
13426 format %{ "XXLXOR $dst, $zero \t// replicate2L" %}
13427 size(4);
13428 ins_encode %{
13429 __ xxlxor($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
13430 %}
13431 ins_pipe(pipe_class_default);
13432 %}
13433
13434 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
13435 match(Set dst (Replicate src));
13436 predicate(n->as_Vector()->length() == 2 &&
13437 Matcher::vector_element_basic_type(n) == T_LONG);
13438
13439 format %{ "XXLEQV $dst, $src \t// replicate2L" %}
13440 size(4);
13441 ins_encode %{
13442 __ xxleqv($dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr(), $dst$$VectorRegister->to_vsr());
13443 %}
13444 ins_pipe(pipe_class_default);
13445 %}
13446
13447 // ============================================================================
13448 // Safepoint Instruction
13449
13450 instruct safePoint_poll(iRegPdst poll) %{
13451 match(SafePoint poll);
13452
13453 // It caused problems to add the effect that r0 is killed, but this
13454 // effect no longer needs to be mentioned, since r0 is not contained
13455 // in a reg_class.
13456
13457 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
13458 size(4);
13459 ins_encode( enc_poll(0x0, poll) );
13460 ins_pipe(pipe_class_default);
13461 %}
13462
13463 // ============================================================================
13464 // Call Instructions
13465
13466 source %{
13467
13468 #include "runtime/continuation.hpp"
13469
13470 %}
13471
13472 // Call Java Static Instruction
13473
13474 instruct CallStaticJavaDirect(method meth) %{
13475 match(CallStaticJava);
13476 effect(USE meth);
13477 ins_cost(CALL_COST);
13478
13479 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
13480
13481 format %{ "CALL,static $meth \t// ==> " %}
13482 size((Continuations::enabled() ? 8 : 4));
13483 ins_encode( enc_java_static_call(meth) );
13484 ins_pipe(pipe_class_call);
13485 %}
13486
13487 // Call Java Dynamic Instruction
13488
13489 instruct CallDynamicJavaDirect(method meth) %{
13490 match(CallDynamicJava);
13491 effect(USE meth);
13492 ins_cost(CALL_COST);
13493
13494 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
13495 ins_num_consts(4);
13496
13497 format %{ "CALL,dynamic $meth \t// ==> " %}
13498 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
13499 ins_pipe(pipe_class_call);
13500 %}
13501
13502 // Call Runtime Instruction
13503
13504 instruct CallRuntimeDirect(method meth) %{
13505 match(CallRuntime);
13506 effect(USE meth);
13507 ins_cost(CALL_COST);
13508
13509 // Enc_java_to_runtime_call needs up to 3 constants: call target,
13510 // env for callee, C-toc.
13511 ins_num_consts(3);
13512
13513 format %{ "CALL,runtime" %}
13514 ins_encode( enc_java_to_runtime_call(meth) );
13515 ins_pipe(pipe_class_call);
13516 %}
13517
13518 // Call Leaf
13519
13520 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
13521 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
13522 effect(DEF dst, USE src);
13523
13524 ins_num_consts(1);
13525
13526 format %{ "MTCTR $src" %}
13527 size(4);
13528 ins_encode( enc_leaf_call_mtctr(src) );
13529 ins_pipe(pipe_class_default);
13530 %}
13531
13532 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
13533 instruct CallLeafDirect(method meth) %{
13534 match(CallLeaf); // To get the data all the data fields we need ...
13535 effect(USE meth);
13536 predicate(false); // but never match.
13537
13538 format %{ "BCTRL \t// leaf call $meth ==> " %}
13539 size((Continuations::enabled() ? 8 : 4));
13540 ins_encode %{
13541 __ bctrl();
13542 __ post_call_nop();
13543 %}
13544 ins_pipe(pipe_class_call);
13545 %}
13546
13547 // postalloc expand of CallLeafDirect.
13548 // Load address to call from TOC, then bl to it.
13549 instruct CallLeafDirect_Ex(method meth) %{
13550 match(CallLeaf);
13551 effect(USE meth);
13552 ins_cost(CALL_COST);
13553
13554 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
13555 // env for callee, C-toc.
13556 ins_num_consts(3);
13557
13558 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
13559 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
13560 %}
13561
13562 // Call runtime without safepoint - same as CallLeaf.
13563 // postalloc expand of CallLeafNoFPDirect.
13564 // Load address to call from TOC, then bl to it.
13565 instruct CallLeafNoFPDirect_Ex(method meth) %{
13566 match(CallLeafNoFP);
13567 effect(USE meth);
13568 ins_cost(CALL_COST);
13569
13570 // Enc_java_to_runtime_call needs up to 3 constants: call target,
13571 // env for callee, C-toc.
13572 ins_num_consts(3);
13573
13574 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
13575 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
13576 %}
13577
13578 // Tail Call; Jump from runtime stub to Java code.
13579 // Also known as an 'interprocedural jump'.
13580 // Target of jump will eventually return to caller.
13581 // TailJump below removes the return address.
13582 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_ptr) %{
13583 match(TailCall jump_target method_ptr);
13584 ins_cost(CALL_COST);
13585
13586 format %{ "MTCTR $jump_target \t// $method_ptr holds method\n\t"
13587 "BCTR \t// tail call" %}
13588 size(8);
13589 ins_encode %{
13590 __ mtctr($jump_target$$Register);
13591 __ bctr();
13592 %}
13593 ins_pipe(pipe_class_call);
13594 %}
13595
13596 // Return Instruction
13597 instruct Ret() %{
13598 match(Return);
13599 format %{ "BLR \t// branch to link register" %}
13600 size(4);
13601 ins_encode %{
13602 // LR is restored in MachEpilogNode. Just do the RET here.
13603 __ blr();
13604 %}
13605 ins_pipe(pipe_class_default);
13606 %}
13607
13608 // Tail Jump; remove the return address; jump to target.
13609 // TailCall above leaves the return address around.
13610 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
13611 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
13612 // "restore" before this instruction (in Epilogue), we need to materialize it
13613 // in %i0.
13614 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
13615 match(TailJump jump_target ex_oop);
13616 ins_cost(CALL_COST);
13617
13618 format %{ "LD R4_ARG2 = LR\n\t"
13619 "MTCTR $jump_target\n\t"
13620 "BCTR \t// TailJump, exception oop: $ex_oop" %}
13621 size(12);
13622 ins_encode %{
13623 __ ld(R4_ARG2/* issuing pc */, _abi0(lr), R1_SP);
13624 __ mtctr($jump_target$$Register);
13625 __ bctr();
13626 %}
13627 ins_pipe(pipe_class_call);
13628 %}
13629
13630 // Forward exception.
13631 instruct ForwardExceptionjmp()
13632 %{
13633 match(ForwardException);
13634 ins_cost(CALL_COST);
13635
13636 format %{ "JMP forward_exception_stub" %}
13637 ins_encode %{
13638 __ set_inst_mark();
13639 __ b64_patchable(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
13640 __ clear_inst_mark();
13641 %}
13642 ins_pipe(pipe_class_call);
13643 %}
13644
13645 // Create exception oop: created by stack-crawling runtime code.
13646 // Created exception is now available to this handler, and is setup
13647 // just prior to jumping to this handler. No code emitted.
13648 instruct CreateException(rarg1RegP ex_oop) %{
13649 match(Set ex_oop (CreateEx));
13650 ins_cost(0);
13651
13652 format %{ " -- \t// exception oop; no code emitted" %}
13653 size(0);
13654 ins_encode( /*empty*/ );
13655 ins_pipe(pipe_class_default);
13656 %}
13657
13658 // Rethrow exception: The exception oop will come in the first
13659 // argument position. Then JUMP (not call) to the rethrow stub code.
13660 instruct RethrowException() %{
13661 match(Rethrow);
13662 ins_cost(CALL_COST);
13663
13664 format %{ "JMP rethrow_stub" %}
13665 ins_encode %{
13666 __ set_inst_mark();
13667 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
13668 __ clear_inst_mark();
13669 %}
13670 ins_pipe(pipe_class_call);
13671 %}
13672
13673 // Die now.
13674 instruct ShouldNotReachHere() %{
13675 match(Halt);
13676 ins_cost(CALL_COST);
13677
13678 format %{ "ShouldNotReachHere" %}
13679 ins_encode %{
13680 if (is_reachable()) {
13681 const char* str = __ code_string(_halt_reason);
13682 __ stop(str);
13683 }
13684 %}
13685 ins_pipe(pipe_class_default);
13686 %}
13687
13688 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
13689 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
13690 // Get a DEF on threadRegP, no costs, no encoding, use
13691 // 'ins_should_rematerialize(true)' to avoid spilling.
13692 instruct tlsLoadP(threadRegP dst) %{
13693 match(Set dst (ThreadLocal));
13694 ins_cost(0);
13695
13696 ins_should_rematerialize(true);
13697
13698 format %{ " -- \t// $dst=Thread::current(), empty" %}
13699 size(0);
13700 ins_encode( /*empty*/ );
13701 ins_pipe(pipe_class_empty);
13702 %}
13703
13704 //---Some PPC specific nodes---------------------------------------------------
13705
13706 // Nop instructions
13707
13708 instruct fxNop() %{
13709 ins_cost(0);
13710
13711 ins_is_nop(true);
13712
13713 format %{ "fxNop" %}
13714 size(4);
13715 ins_encode %{
13716 __ nop();
13717 %}
13718 ins_pipe(pipe_class_default);
13719 %}
13720
13721 instruct fpNop0() %{
13722 ins_cost(0);
13723
13724 ins_is_nop(true);
13725
13726 format %{ "fpNop0" %}
13727 size(4);
13728 ins_encode %{
13729 __ fpnop0();
13730 %}
13731 ins_pipe(pipe_class_default);
13732 %}
13733
13734 instruct fpNop1() %{
13735 ins_cost(0);
13736
13737 ins_is_nop(true);
13738
13739 format %{ "fpNop1" %}
13740 size(4);
13741 ins_encode %{
13742 __ fpnop1();
13743 %}
13744 ins_pipe(pipe_class_default);
13745 %}
13746
13747 instruct brNop0() %{
13748 ins_cost(0);
13749 size(4);
13750 format %{ "brNop0" %}
13751 ins_encode %{
13752 __ brnop0();
13753 %}
13754 ins_is_nop(true);
13755 ins_pipe(pipe_class_default);
13756 %}
13757
13758 instruct brNop1() %{
13759 ins_cost(0);
13760
13761 ins_is_nop(true);
13762
13763 format %{ "brNop1" %}
13764 size(4);
13765 ins_encode %{
13766 __ brnop1();
13767 %}
13768 ins_pipe(pipe_class_default);
13769 %}
13770
13771 instruct brNop2() %{
13772 ins_cost(0);
13773
13774 ins_is_nop(true);
13775
13776 format %{ "brNop2" %}
13777 size(4);
13778 ins_encode %{
13779 __ brnop2();
13780 %}
13781 ins_pipe(pipe_class_default);
13782 %}
13783
13784 instruct cacheWB(indirect addr)
13785 %{
13786 match(CacheWB addr);
13787
13788 ins_cost(100);
13789 format %{ "cache writeback, address = $addr" %}
13790 ins_encode %{
13791 assert($addr->index_position() < 0, "should be");
13792 assert($addr$$disp == 0, "should be");
13793 __ cache_wb(Address($addr$$base$$Register));
13794 %}
13795 ins_pipe(pipe_class_default);
13796 %}
13797
13798 instruct cacheWBPreSync()
13799 %{
13800 match(CacheWBPreSync);
13801
13802 ins_cost(0);
13803 format %{ "cache writeback presync" %}
13804 ins_encode %{
13805 __ cache_wbsync(true);
13806 %}
13807 ins_pipe(pipe_class_default);
13808 %}
13809
13810 instruct cacheWBPostSync()
13811 %{
13812 match(CacheWBPostSync);
13813
13814 ins_cost(100);
13815 format %{ "cache writeback postsync" %}
13816 ins_encode %{
13817 __ cache_wbsync(false);
13818 %}
13819 ins_pipe(pipe_class_default);
13820 %}
13821
13822 //----------PEEPHOLE RULES-----------------------------------------------------
13823 // These must follow all instruction definitions as they use the names
13824 // defined in the instructions definitions.
13825 //
13826 // peepmatch ( root_instr_name [preceeding_instruction]* );
13827 //
13828 // peepconstraint %{
13829 // (instruction_number.operand_name relational_op instruction_number.operand_name
13830 // [, ...] );
13831 // // instruction numbers are zero-based using left to right order in peepmatch
13832 //
13833 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13834 // // provide an instruction_number.operand_name for each operand that appears
13835 // // in the replacement instruction's match rule
13836 //
13837 // ---------VM FLAGS---------------------------------------------------------
13838 //
13839 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13840 //
13841 // Each peephole rule is given an identifying number starting with zero and
13842 // increasing by one in the order seen by the parser. An individual peephole
13843 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13844 // on the command-line.
13845 //
13846 // ---------CURRENT LIMITATIONS----------------------------------------------
13847 //
13848 // Only match adjacent instructions in same basic block
13849 // Only equality constraints
13850 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13851 // Only one replacement instruction
13852 //
13853 // ---------EXAMPLE----------------------------------------------------------
13854 //
13855 // // pertinent parts of existing instructions in architecture description
13856 // instruct movI(eRegI dst, eRegI src) %{
13857 // match(Set dst (CopyI src));
13858 // %}
13859 //
13860 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13861 // match(Set dst (AddI dst src));
13862 // effect(KILL cr);
13863 // %}
13864 //
13865 // // Change (inc mov) to lea
13866 // peephole %{
13867 // // increment preceded by register-register move
13868 // peepmatch ( incI_eReg movI );
13869 // // require that the destination register of the increment
13870 // // match the destination register of the move
13871 // peepconstraint ( 0.dst == 1.dst );
13872 // // construct a replacement instruction that sets
13873 // // the destination to ( move's source register + one )
13874 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13875 // %}
13876 //
13877 // Implementation no longer uses movX instructions since
13878 // machine-independent system no longer uses CopyX nodes.
13879 //
13880 // peephole %{
13881 // peepmatch ( incI_eReg movI );
13882 // peepconstraint ( 0.dst == 1.dst );
13883 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13884 // %}
13885 //
13886 // peephole %{
13887 // peepmatch ( decI_eReg movI );
13888 // peepconstraint ( 0.dst == 1.dst );
13889 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13890 // %}
13891 //
13892 // peephole %{
13893 // peepmatch ( addI_eReg_imm movI );
13894 // peepconstraint ( 0.dst == 1.dst );
13895 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13896 // %}
13897 //
13898 // peephole %{
13899 // peepmatch ( addP_eReg_imm movP );
13900 // peepconstraint ( 0.dst == 1.dst );
13901 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13902 // %}
13903
13904 // // Change load of spilled value to only a spill
13905 // instruct storeI(memory mem, eRegI src) %{
13906 // match(Set mem (StoreI mem src));
13907 // %}
13908 //
13909 // instruct loadI(eRegI dst, memory mem) %{
13910 // match(Set dst (LoadI mem));
13911 // %}
13912 //
13913 peephole %{
13914 peepmatch ( loadI storeI );
13915 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13916 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13917 %}
13918
13919 peephole %{
13920 peepmatch ( loadL storeL );
13921 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13922 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
13923 %}
13924
13925 peephole %{
13926 peepmatch ( loadP storeP );
13927 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
13928 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
13929 %}
13930
13931 //----------SMARTSPILL RULES---------------------------------------------------
13932 // These must follow all instruction definitions as they use the names
13933 // defined in the instructions definitions.