1694 __ mr(R4_ARG2/*issuing_pc*/, return_pc);
1695
1696 // Return to exception handler.
1697 __ blr();
1698
1699 //=============================================================================
1700 // Counter overflow.
1701
1702 if (inc_counter) {
1703 // Handle invocation counter overflow.
1704 __ bind(invocation_counter_overflow);
1705
1706 generate_counter_overflow(continue_after_compile);
1707 }
1708
1709 return entry;
1710 }
1711
1712 // Generic interpreted method entry to (asm) interpreter.
1713 //
1714 address TemplateInterpreterGenerator::generate_normal_entry(bool synchronized) {
1715 bool inc_counter = UseCompiler || CountCompiledCalls;
1716 address entry = __ pc();
1717 // Generate the code to allocate the interpreter stack frame.
1718 Register Rsize_of_parameters = R4_ARG2, // Written by generate_fixed_frame.
1719 Rsize_of_locals = R5_ARG3; // Written by generate_fixed_frame.
1720
1721 // Does also a stack check to assure this frame fits on the stack.
1722 generate_fixed_frame(false, Rsize_of_parameters, Rsize_of_locals);
1723
1724 // --------------------------------------------------------------------------
1725 // Zero out non-parameter locals.
1726 // Note: *Always* zero out non-parameter locals as Sparc does. It's not
1727 // worth to ask the flag, just do it.
1728 Register Rslot_addr = R6_ARG4,
1729 Rnum = R7_ARG5;
1730 Label Lno_locals, Lzero_loop;
1731
1732 // Set up the zeroing loop.
1733 __ subf(Rnum, Rsize_of_parameters, Rsize_of_locals);
1734 __ subf(Rslot_addr, Rsize_of_parameters, R18_locals);
1789 // --------------------------------------------------------------------------
1790 // Locking of synchronized methods. Must happen AFTER invocation_counter
1791 // check and stack overflow check, so method is not locked if overflows.
1792 if (synchronized) {
1793 lock_method(R3_ARG1, R4_ARG2, R5_ARG3);
1794 }
1795 #ifdef ASSERT
1796 else {
1797 Label Lok;
1798 __ lhz(R0, in_bytes(Method::access_flags_offset()), R19_method);
1799 __ andi_(R0, R0, JVM_ACC_SYNCHRONIZED);
1800 __ asm_assert_eq("method needs synchronization");
1801 __ bind(Lok);
1802 }
1803 #endif // ASSERT
1804
1805 // --------------------------------------------------------------------------
1806 // JVMTI support
1807 __ notify_method_entry();
1808
1809 // --------------------------------------------------------------------------
1810 // Start executing instructions.
1811 __ dispatch_next(vtos);
1812
1813 // --------------------------------------------------------------------------
1814 if (inc_counter) {
1815 // Handle invocation counter overflow.
1816 __ bind(invocation_counter_overflow);
1817 generate_counter_overflow(continue_after_compile);
1818 }
1819 return entry;
1820 }
1821
1822 // CRC32 Intrinsics.
1823 //
1824 // Contract on scratch and work registers.
1825 // =======================================
1826 //
1827 // On ppc, the register set {R2..R12} is available in the interpreter as scratch/work registers.
1828 // You should, however, keep in mind that {R3_ARG1..R10_ARG8} is the C-ABI argument register set.
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1694 __ mr(R4_ARG2/*issuing_pc*/, return_pc);
1695
1696 // Return to exception handler.
1697 __ blr();
1698
1699 //=============================================================================
1700 // Counter overflow.
1701
1702 if (inc_counter) {
1703 // Handle invocation counter overflow.
1704 __ bind(invocation_counter_overflow);
1705
1706 generate_counter_overflow(continue_after_compile);
1707 }
1708
1709 return entry;
1710 }
1711
1712 // Generic interpreted method entry to (asm) interpreter.
1713 //
1714 address TemplateInterpreterGenerator::generate_normal_entry(bool synchronized, bool object_init) {
1715 bool inc_counter = UseCompiler || CountCompiledCalls;
1716 address entry = __ pc();
1717 // Generate the code to allocate the interpreter stack frame.
1718 Register Rsize_of_parameters = R4_ARG2, // Written by generate_fixed_frame.
1719 Rsize_of_locals = R5_ARG3; // Written by generate_fixed_frame.
1720
1721 // Does also a stack check to assure this frame fits on the stack.
1722 generate_fixed_frame(false, Rsize_of_parameters, Rsize_of_locals);
1723
1724 // --------------------------------------------------------------------------
1725 // Zero out non-parameter locals.
1726 // Note: *Always* zero out non-parameter locals as Sparc does. It's not
1727 // worth to ask the flag, just do it.
1728 Register Rslot_addr = R6_ARG4,
1729 Rnum = R7_ARG5;
1730 Label Lno_locals, Lzero_loop;
1731
1732 // Set up the zeroing loop.
1733 __ subf(Rnum, Rsize_of_parameters, Rsize_of_locals);
1734 __ subf(Rslot_addr, Rsize_of_parameters, R18_locals);
1789 // --------------------------------------------------------------------------
1790 // Locking of synchronized methods. Must happen AFTER invocation_counter
1791 // check and stack overflow check, so method is not locked if overflows.
1792 if (synchronized) {
1793 lock_method(R3_ARG1, R4_ARG2, R5_ARG3);
1794 }
1795 #ifdef ASSERT
1796 else {
1797 Label Lok;
1798 __ lhz(R0, in_bytes(Method::access_flags_offset()), R19_method);
1799 __ andi_(R0, R0, JVM_ACC_SYNCHRONIZED);
1800 __ asm_assert_eq("method needs synchronization");
1801 __ bind(Lok);
1802 }
1803 #endif // ASSERT
1804
1805 // --------------------------------------------------------------------------
1806 // JVMTI support
1807 __ notify_method_entry();
1808
1809 // --------------------------------------------------------------------------
1810 // Issue a StoreStore barrier on entry to Object_init if the
1811 // class has strict field fields. Be lazy, always do it.
1812 if (object_init) {
1813 __ membar(Assembler::StoreStore);
1814 }
1815
1816 // --------------------------------------------------------------------------
1817 // Start executing instructions.
1818 __ dispatch_next(vtos);
1819
1820 // --------------------------------------------------------------------------
1821 if (inc_counter) {
1822 // Handle invocation counter overflow.
1823 __ bind(invocation_counter_overflow);
1824 generate_counter_overflow(continue_after_compile);
1825 }
1826 return entry;
1827 }
1828
1829 // CRC32 Intrinsics.
1830 //
1831 // Contract on scratch and work registers.
1832 // =======================================
1833 //
1834 // On ppc, the register set {R2..R12} is available in the interpreter as scratch/work registers.
1835 // You should, however, keep in mind that {R3_ARG1..R10_ARG8} is the C-ABI argument register set.
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