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src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

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1714 
1715   __ bind(update);
1716 
1717   if (do_update) {
1718 #ifdef ASSERT
1719     if (exact_klass != nullptr) {
1720       check_exact_klass(tmp, exact_klass);
1721     }
1722 #endif
1723     if (!no_conflict) {
1724       check_conflict(exact_klass, current_klass, tmp, next, none, mdo_addr);
1725     } else {
1726       check_no_conflict(exact_klass, current_klass, tmp, mdo_addr, next);
1727     }
1728 
1729     __ bind(next);
1730   }
1731   COMMENT("} emit_profile_type");
1732 }
1733 




1734 void LIR_Assembler::align_backward_branch_target() { }
1735 
1736 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
1737   // tmp must be unused
1738   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
1739 
1740   if (left->is_single_cpu()) {
1741     assert(dest->is_single_cpu(), "expect single result reg");
1742     __ negw(dest->as_register(), left->as_register());
1743   } else if (left->is_double_cpu()) {
1744     assert(dest->is_double_cpu(), "expect double result reg");
1745     __ neg(dest->as_register_lo(), left->as_register_lo());
1746   } else if (left->is_single_fpu()) {
1747     assert(dest->is_single_fpu(), "expect single float result reg");
1748     __ fneg_s(dest->as_float_reg(), left->as_float_reg());
1749   } else {
1750     assert(left->is_double_fpu(), "expect double float operand reg");
1751     assert(dest->is_double_fpu(), "expect double float result reg");
1752     __ fneg_d(dest->as_double_reg(), left->as_double_reg());
1753   }

2137     case lir_logic_xor: __ xori(dst, left, right); break;
2138     default:            ShouldNotReachHere();
2139   }
2140 }
2141 
2142 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2143   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2144   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2145   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2146   __ sd(r, Address(sp, offset_from_rsp_in_bytes));
2147 }
2148 
2149 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2150   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2151   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2152   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2153   __ mv(t0, c);
2154   __ sd(t0, Address(sp, offset_from_rsp_in_bytes));
2155 }
2156 






















2157 #undef __

1714 
1715   __ bind(update);
1716 
1717   if (do_update) {
1718 #ifdef ASSERT
1719     if (exact_klass != nullptr) {
1720       check_exact_klass(tmp, exact_klass);
1721     }
1722 #endif
1723     if (!no_conflict) {
1724       check_conflict(exact_klass, current_klass, tmp, next, none, mdo_addr);
1725     } else {
1726       check_no_conflict(exact_klass, current_klass, tmp, mdo_addr, next);
1727     }
1728 
1729     __ bind(next);
1730   }
1731   COMMENT("} emit_profile_type");
1732 }
1733 
1734 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
1735   Unimplemented();
1736 }
1737 
1738 void LIR_Assembler::align_backward_branch_target() { }
1739 
1740 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
1741   // tmp must be unused
1742   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
1743 
1744   if (left->is_single_cpu()) {
1745     assert(dest->is_single_cpu(), "expect single result reg");
1746     __ negw(dest->as_register(), left->as_register());
1747   } else if (left->is_double_cpu()) {
1748     assert(dest->is_double_cpu(), "expect double result reg");
1749     __ neg(dest->as_register_lo(), left->as_register_lo());
1750   } else if (left->is_single_fpu()) {
1751     assert(dest->is_single_fpu(), "expect single float result reg");
1752     __ fneg_s(dest->as_float_reg(), left->as_float_reg());
1753   } else {
1754     assert(left->is_double_fpu(), "expect double float operand reg");
1755     assert(dest->is_double_fpu(), "expect double float result reg");
1756     __ fneg_d(dest->as_double_reg(), left->as_double_reg());
1757   }

2141     case lir_logic_xor: __ xori(dst, left, right); break;
2142     default:            ShouldNotReachHere();
2143   }
2144 }
2145 
2146 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2147   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2148   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2149   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2150   __ sd(r, Address(sp, offset_from_rsp_in_bytes));
2151 }
2152 
2153 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2154   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2155   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2156   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2157   __ mv(t0, c);
2158   __ sd(t0, Address(sp, offset_from_rsp_in_bytes));
2159 }
2160 
2161 // Valhalla support
2162 
2163 void LIR_Assembler::check_orig_pc() {
2164   Unimplemented();
2165 }
2166 
2167 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
2168   Unimplemented();
2169   return 0;
2170 }
2171 
2172 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
2173   Unimplemented();
2174 }
2175 
2176 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
2177   Unimplemented();
2178 }
2179 
2180 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
2181   Unimplemented();
2182 }
2183 #undef __
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