src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -1729,10 +1729,14 @@
      __ bind(next);
    }
    COMMENT("} emit_profile_type");
  }
  
+ void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
+   Unimplemented();
+ }
+ 
  void LIR_Assembler::align_backward_branch_target() { }
  
  void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
    // tmp must be unused
    assert(tmp->is_illegal(), "wasting a register if tmp is allocated");

@@ -2152,6 +2156,28 @@
    assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
    __ mv(t0, c);
    __ sd(t0, Address(sp, offset_from_rsp_in_bytes));
  }
  
+ // Valhalla support
+ 
+ void LIR_Assembler::check_orig_pc() {
+   Unimplemented();
+ }
+ 
+ int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
+   Unimplemented();
+   return 0;
+ }
+ 
+ void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
+   Unimplemented();
+ }
+ 
+ void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
+   Unimplemented();
+ }
+ 
+ void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
+   Unimplemented();
+ }
  #undef __