diff a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp
--- a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp
@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
  * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -110,10 +110,11 @@
 
   void logic_op_reg32(Register dst, Register left, Register right, LIR_Code code);
   void logic_op_reg(Register dst, Register left, Register right, LIR_Code code);
   void logic_op_imm(Register dst, Register left, int right, LIR_Code code);
 
+  void move(LIR_Opr src, LIR_Opr dst);
 public:
 
   void emit_cmove(LIR_Op4* op);
 
   void store_parameter(Register r, int offset_from_rsp_in_words);