src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

*** 43,10 ***
--- 43,33 ---
  #define STOP(error) block_comment(error); stop(error)
  #endif
  
  #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  
+ void C2_MacroAssembler::entry_barrier() {
+   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
+   // Dummy labels for just measuring the code size
+   Label dummy_slow_path;
+   Label dummy_continuation;
+   Label dummy_guard;
+   Label* slow_path = &dummy_slow_path;
+   Label* continuation = &dummy_continuation;
+   Label* guard = &dummy_guard;
+ 
+   if (!Compile::current()->output()->in_scratch_emit_size()) {
+     // Use real labels from actual stub when not emitting code for the purpose of measuring its size
+     C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
+     Compile::current()->output()->add_stub(stub);
+     slow_path = &stub->entry();
+     continuation = &stub->continuation();
+     guard = &stub->guard();
+   }
+ 
+   // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
+   bs->nmethod_entry_barrier(this, slow_path, continuation, guard);
+ }
+ 
  void C2_MacroAssembler::fast_lock(Register obj, Register box,
                                    Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
    // Flag register, zero for success; non-zero for failure.
    Register flag = t1;
  

*** 2350,11 ***
  
    // check whether it's a NaN or +/- Inf.
    mv(t0, 0x7c00);
    andr(tmp, src, t0);
    // jump to stub processing NaN and Inf cases.
!   beq(t0, tmp, stub->entry(), true);
  
    // non-NaN or non-Inf cases, just use built-in instructions.
    fmv_h_x(dst, src);
    fcvt_s_h(dst, dst);
  
--- 2373,11 ---
  
    // check whether it's a NaN or +/- Inf.
    mv(t0, 0x7c00);
    andr(tmp, src, t0);
    // jump to stub processing NaN and Inf cases.
!   beq(t0, tmp, stub->entry(), /* is_far */ true);
  
    // non-NaN or non-Inf cases, just use built-in instructions.
    fmv_h_x(dst, src);
    fcvt_s_h(dst, dst);
  

*** 2382,11 ***
  
    // check whether it's a NaN.
    // replace fclass with feq as performance optimization.
    feq_s(t0, src, src);
    // jump to stub processing NaN cases.
!   beqz(t0, stub->entry(), true);
  
    // non-NaN cases, just use built-in instructions.
    fcvt_h_s(ftmp, src);
    fmv_x_h(dst, ftmp);
  
--- 2405,11 ---
  
    // check whether it's a NaN.
    // replace fclass with feq as performance optimization.
    feq_s(t0, src, src);
    // jump to stub processing NaN cases.
!   beqz(t0, stub->entry(), /* is_far */ true);
  
    // non-NaN cases, just use built-in instructions.
    fcvt_h_s(ftmp, src);
    fmv_x_h(dst, ftmp);
  

*** 2443,11 ***
  
    // For non-NaN or non-Inf cases, just use built-in instructions.
    vfwcvt_f_f_v(dst, src);
  
    // jump to stub processing NaN and Inf cases if there is any of them in the vector-wide.
!   bnez(t0, stub->entry(), true);
  
    bind(stub->continuation());
  }
  
  static void float_to_float16_v_slow_path(C2_MacroAssembler& masm,
--- 2466,11 ---
  
    // For non-NaN or non-Inf cases, just use built-in instructions.
    vfwcvt_f_f_v(dst, src);
  
    // jump to stub processing NaN and Inf cases if there is any of them in the vector-wide.
!   bnez(t0, stub->entry(), /* is_far */ true);
  
    bind(stub->continuation());
  }
  
  static void float_to_float16_v_slow_path(C2_MacroAssembler& masm,

*** 2536,11 ***
  
    // For non-NaN cases, just use built-in instructions.
    vfncvt_f_f_w(dst, src);
  
    // jump to stub processing NaN cases.
!   bnez(t0, stub->entry(), true);
  
    bind(stub->continuation());
  }
  
  void C2_MacroAssembler::signum_fp_v(VectorRegister dst, VectorRegister one, BasicType bt, int vlen) {
--- 2559,11 ---
  
    // For non-NaN cases, just use built-in instructions.
    vfncvt_f_f_w(dst, src);
  
    // jump to stub processing NaN cases.
!   bnez(t0, stub->entry(), /* is_far */ true);
  
    bind(stub->continuation());
  }
  
  void C2_MacroAssembler::signum_fp_v(VectorRegister dst, VectorRegister one, BasicType bt, int vlen) {