1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_MACROASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
29
30 #include "asm/assembler.inline.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42
43 public:
44
45 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
46
47 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp_reg = t0);
48
49 // Alignment
50 int align(int modulus, int extra_offset = 0);
51
52 static inline void assert_alignment(address pc, int alignment = MacroAssembler::instruction_size) {
53 assert(is_aligned(pc, alignment), "bad alignment");
54 }
55
56 // nop
57 void post_call_nop();
58
59 // Stack frame creation/removal
60 // Note that SP must be updated to the right place before saving/restoring RA and FP
61 // because signal based thread suspend/resume could happen asynchronously.
62 void enter() {
63 subi(sp, sp, 2 * wordSize);
64 sd(ra, Address(sp, wordSize));
65 sd(fp, Address(sp));
66 addi(fp, sp, 2 * wordSize);
67 }
68
69 void leave() {
70 subi(sp, fp, 2 * wordSize);
71 ld(fp, Address(sp));
72 ld(ra, Address(sp, wordSize));
73 addi(sp, sp, 2 * wordSize);
74 }
75
76
77 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
78 // The pointer will be loaded into the thread register.
79 void get_thread(Register thread);
80
81 // Support for VM calls
82 //
83 // It is imperative that all calls into the VM are handled via the call_VM macros.
84 // They make sure that the stack linkage is setup correctly. call_VM's correspond
85 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
86
87 void call_VM(Register oop_result,
88 address entry_point,
89 bool check_exceptions = true);
90 void call_VM(Register oop_result,
91 address entry_point,
92 Register arg_1,
93 bool check_exceptions = true);
94 void call_VM(Register oop_result,
95 address entry_point,
96 Register arg_1, Register arg_2,
97 bool check_exceptions = true);
98 void call_VM(Register oop_result,
99 address entry_point,
100 Register arg_1, Register arg_2, Register arg_3,
101 bool check_exceptions = true);
102
103 // Overloadings with last_Java_sp
104 void call_VM(Register oop_result,
105 Register last_java_sp,
106 address entry_point,
107 int number_of_arguments = 0,
108 bool check_exceptions = true);
109 void call_VM(Register oop_result,
110 Register last_java_sp,
111 address entry_point,
112 Register arg_1,
113 bool check_exceptions = true);
114 void call_VM(Register oop_result,
115 Register last_java_sp,
116 address entry_point,
117 Register arg_1, Register arg_2,
118 bool check_exceptions = true);
119 void call_VM(Register oop_result,
120 Register last_java_sp,
121 address entry_point,
122 Register arg_1, Register arg_2, Register arg_3,
123 bool check_exceptions = true);
124
125 void get_vm_result_oop(Register oop_result, Register java_thread);
126 void get_vm_result_metadata(Register metadata_result, Register java_thread);
127
128 // These always tightly bind to MacroAssembler::call_VM_leaf_base
129 // bypassing the virtual implementation
130 void call_VM_leaf(address entry_point,
131 int number_of_arguments = 0);
132 void call_VM_leaf(address entry_point,
133 Register arg_0);
134 void call_VM_leaf(address entry_point,
135 Register arg_0, Register arg_1);
136 void call_VM_leaf(address entry_point,
137 Register arg_0, Register arg_1, Register arg_2);
138
139 // These always tightly bind to MacroAssembler::call_VM_base
140 // bypassing the virtual implementation
141 void super_call_VM_leaf(address entry_point, Register arg_0);
142 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1);
143 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2);
144 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3);
145
146 // last Java Frame (fills frame anchor)
147 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, Register tmp);
148 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, Register tmp);
149 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc);
150
151 // thread in the default location (xthread)
152 void reset_last_Java_frame(bool clear_fp);
153
154 virtual void call_VM_leaf_base(
155 address entry_point, // the entry point
156 int number_of_arguments, // the number of arguments to pop after the call
157 Label* retaddr = nullptr
158 );
159
160 virtual void call_VM_leaf_base(
161 address entry_point, // the entry point
162 int number_of_arguments, // the number of arguments to pop after the call
163 Label& retaddr) {
164 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
165 }
166
167 virtual void call_VM_base( // returns the register containing the thread upon return
168 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
169 Register java_thread, // the thread if computed before ; use noreg otherwise
170 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
171 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
172 address entry_point, // the entry point
173 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
174 bool check_exceptions // whether to check for pending exceptions after return
175 );
176
177 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions);
178
179 virtual void check_and_handle_earlyret(Register java_thread);
180 virtual void check_and_handle_popframe(Register java_thread);
181
182 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
183 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
184 void resolve_jobject(Register value, Register tmp1, Register tmp2);
185 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
186
187 void movoop(Register dst, jobject obj);
188 void mov_metadata(Register dst, Metadata* obj);
189 void bang_stack_size(Register size, Register tmp);
190 void set_narrow_oop(Register dst, jobject obj);
191 void set_narrow_klass(Register dst, Klass* k);
192
193 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
194 void access_load_at(BasicType type, DecoratorSet decorators, Register dst,
195 Address src, Register tmp1, Register tmp2);
196 void access_store_at(BasicType type, DecoratorSet decorators, Address dst,
197 Register val, Register tmp1, Register tmp2, Register tmp3);
198 void load_klass(Register dst, Register src, Register tmp = t0);
199 void load_narrow_klass_compact(Register dst, Register src);
200 void load_narrow_klass(Register dst, Register src);
201 void store_klass(Register dst, Register src, Register tmp = t0);
202 void cmp_klass_beq(Register obj, Register klass,
203 Register tmp1, Register tmp2,
204 Label &L, bool is_far = false);
205 void cmp_klass_bne(Register obj, Register klass,
206 Register tmp1, Register tmp2,
207 Label &L, bool is_far = false);
208
209 void encode_klass_not_null(Register r, Register tmp = t0);
210 void decode_klass_not_null(Register r, Register tmp = t0);
211 void encode_klass_not_null(Register dst, Register src, Register tmp);
212 void decode_klass_not_null(Register dst, Register src, Register tmp);
213 void decode_heap_oop_not_null(Register r);
214 void decode_heap_oop_not_null(Register dst, Register src);
215 void decode_heap_oop(Register d, Register s);
216 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
217 void encode_heap_oop_not_null(Register r);
218 void encode_heap_oop_not_null(Register dst, Register src);
219 void encode_heap_oop(Register d, Register s);
220 void encode_heap_oop(Register r) { encode_heap_oop(r, r); };
221 void load_heap_oop(Register dst, Address src, Register tmp1,
222 Register tmp2, DecoratorSet decorators = 0);
223 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
224 Register tmp2, DecoratorSet decorators = 0);
225 void store_heap_oop(Address dst, Register val, Register tmp1,
226 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
227
228 void store_klass_gap(Register dst, Register src);
229
230 // currently unimplemented
231 // Used for storing null. All other oop constants should be
232 // stored using routines that take a jobject.
233 void store_heap_oop_null(Address dst);
234
235 // This dummy is to prevent a call to store_heap_oop from
236 // converting a zero (linked null) into a Register by giving
237 // the compiler two choices it can't resolve
238
239 void store_heap_oop(Address dst, void* dummy);
240
241 // Support for null-checks
242 //
243 // Generates code that causes a null OS exception if the content of reg is null.
244 // If the accessed location is M[reg + offset] and the offset is known, provide the
245 // offset. No explicit code generateion is needed if the offset is within a certain
246 // range (0 <= offset <= page_size).
247
248 virtual void null_check(Register reg, int offset = -1);
249 static bool needs_explicit_null_check(intptr_t offset);
250 static bool uses_implicit_null_check(void* address);
251
252 // interface method calling
253 void lookup_interface_method(Register recv_klass,
254 Register intf_klass,
255 RegisterOrConstant itable_index,
256 Register method_result,
257 Register scan_tmp,
258 Label& no_such_interface,
259 bool return_method = true);
260
261 void lookup_interface_method_stub(Register recv_klass,
262 Register holder_klass,
263 Register resolved_klass,
264 Register method_result,
265 Register temp_reg,
266 Register temp_reg2,
267 int itable_index,
268 Label& L_no_such_interface);
269
270 // virtual method calling
271 // n.n. x86 allows RegisterOrConstant for vtable_index
272 void lookup_virtual_method(Register recv_klass,
273 RegisterOrConstant vtable_index,
274 Register method_result);
275
276 // Form an address from base + offset in Rd. Rd my or may not
277 // actually be used: you must use the Address that is returned. It
278 // is up to you to ensure that the shift provided matches the size
279 // of your data.
280 Address form_address(Register Rd, Register base, int64_t byte_offset);
281
282 // Sometimes we get misaligned loads and stores, usually from Unsafe
283 // accesses, and these can exceed the offset range.
284 Address legitimize_address(Register Rd, const Address &adr) {
285 if (adr.getMode() == Address::base_plus_offset) {
286 if (!is_simm12(adr.offset())) {
287 return form_address(Rd, adr.base(), adr.offset());
288 }
289 }
290 return adr;
291 }
292
293 // allocation
294 void tlab_allocate(
295 Register obj, // result: pointer to object after successful allocation
296 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
297 int con_size_in_bytes, // object size in bytes if known at compile time
298 Register tmp1, // temp register
299 Register tmp2, // temp register
300 Label& slow_case, // continuation point of fast allocation fails
301 bool is_far = false
302 );
303
304 // Test sub_klass against super_klass, with fast and slow paths.
305
306 // The fast path produces a tri-state answer: yes / no / maybe-slow.
307 // One of the three labels can be null, meaning take the fall-through.
308 // If super_check_offset is -1, the value is loaded up from super_klass.
309 // No registers are killed, except tmp_reg
310 void check_klass_subtype_fast_path(Register sub_klass,
311 Register super_klass,
312 Register tmp_reg,
313 Label* L_success,
314 Label* L_failure,
315 Label* L_slow_path,
316 Register super_check_offset = noreg);
317
318 // The reset of the type check; must be wired to a corresponding fast path.
319 // It does not repeat the fast path logic, so don't use it standalone.
320 // The tmp1_reg and tmp2_reg can be noreg, if no temps are available.
321 // Updates the sub's secondary super cache as necessary.
322 void check_klass_subtype_slow_path(Register sub_klass,
323 Register super_klass,
324 Register tmp1_reg,
325 Register tmp2_reg,
326 Label* L_success,
327 Label* L_failure,
328 bool set_cond_codes = false);
329
330 void check_klass_subtype_slow_path_linear(Register sub_klass,
331 Register super_klass,
332 Register tmp1_reg,
333 Register tmp2_reg,
334 Label* L_success,
335 Label* L_failure,
336 bool set_cond_codes = false);
337
338 void check_klass_subtype_slow_path_table(Register sub_klass,
339 Register super_klass,
340 Register tmp1_reg,
341 Register tmp2_reg,
342 Label* L_success,
343 Label* L_failure,
344 bool set_cond_codes = false);
345
346 // If r is valid, return r.
347 // If r is invalid, remove a register r2 from available_regs, add r2
348 // to regs_to_push, then return r2.
349 Register allocate_if_noreg(const Register r,
350 RegSetIterator<Register> &available_regs,
351 RegSet ®s_to_push);
352
353 // Secondary subtype checking
354 void lookup_secondary_supers_table_var(Register sub_klass,
355 Register r_super_klass,
356 Register result,
357 Register tmp1,
358 Register tmp2,
359 Register tmp3,
360 Register tmp4,
361 Label *L_success);
362
363 void population_count(Register dst, Register src, Register tmp1, Register tmp2);
364
365 // As above, but with a constant super_klass.
366 // The result is in Register result, not the condition codes.
367 bool lookup_secondary_supers_table_const(Register r_sub_klass,
368 Register r_super_klass,
369 Register result,
370 Register tmp1,
371 Register tmp2,
372 Register tmp3,
373 Register tmp4,
374 u1 super_klass_slot,
375 bool stub_is_near = false);
376
377 void verify_secondary_supers_table(Register r_sub_klass,
378 Register r_super_klass,
379 Register result,
380 Register tmp1,
381 Register tmp2,
382 Register tmp3);
383
384 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
385 Register r_array_base,
386 Register r_array_index,
387 Register r_bitmap,
388 Register result,
389 Register tmp,
390 bool is_stub = true);
391
392 void check_klass_subtype(Register sub_klass,
393 Register super_klass,
394 Register tmp_reg,
395 Label& L_success);
396
397 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
398
399 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
400
401 // only if +VerifyOops
402 void _verify_oop(Register reg, const char* s, const char* file, int line);
403 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
404
405 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
406 if (VerifyOops) {
407 _verify_oop(reg, s, file, line);
408 }
409 }
410 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
411 if (VerifyOops) {
412 _verify_oop_addr(reg, s, file, line);
413 }
414 }
415
416 void _verify_method_ptr(Register reg, const char* msg, const char* file, int line) {}
417 void _verify_klass_ptr(Register reg, const char* msg, const char* file, int line) {}
418
419 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
420 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
421 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
422 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
423 #define verify_klass_ptr(reg) _verify_method_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
424
425 // A more convenient access to fence for our purposes
426 // We used four bit to indicate the read and write bits in the predecessors and successors,
427 // and extended i for r, o for w if UseConservativeFence enabled.
428 enum Membar_mask_bits {
429 StoreStore = 0b0101, // (pred = w + succ = w)
430 LoadStore = 0b1001, // (pred = r + succ = w)
431 StoreLoad = 0b0110, // (pred = w + succ = r)
432 LoadLoad = 0b1010, // (pred = r + succ = r)
433 AnyAny = LoadStore | StoreLoad // (pred = rw + succ = rw)
434 };
435
436 void membar(uint32_t order_constraint);
437
438 private:
439
440 static void membar_mask_to_pred_succ(uint32_t order_constraint,
441 uint32_t& predecessor, uint32_t& successor) {
442 predecessor = (order_constraint >> 2) & 0x3;
443 successor = order_constraint & 0x3;
444
445 // extend rw -> iorw:
446 // 01(w) -> 0101(ow)
447 // 10(r) -> 1010(ir)
448 // 11(rw)-> 1111(iorw)
449 if (UseConservativeFence) {
450 predecessor |= predecessor << 2;
451 successor |= successor << 2;
452 }
453 }
454
455 static int pred_succ_to_membar_mask(uint32_t predecessor, uint32_t successor) {
456 return ((predecessor & 0x3) << 2) | (successor & 0x3);
457 }
458
459 public:
460
461 void cmodx_fence();
462
463 void pause() {
464 // Zihintpause
465 // PAUSE is encoded as a FENCE instruction with pred=W, succ=0, fm=0, rd=x0, and rs1=x0.
466 Assembler::fence(w, 0);
467 }
468
469 // prints msg, dumps registers and stops execution
470 void stop(const char* msg);
471
472 static void debug64(char* msg, int64_t pc, int64_t regs[]);
473
474 void unimplemented(const char* what = "");
475
476 void should_not_reach_here() { stop("should not reach here"); }
477
478 static address target_addr_for_insn(address insn_addr);
479
480 // Required platform-specific helpers for Label::patch_instructions.
481 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
482 static int pd_patch_instruction_size(address branch, address target);
483 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
484 pd_patch_instruction_size(branch, target);
485 }
486 static address pd_call_destination(address branch) {
487 return target_addr_for_insn(branch);
488 }
489
490 static int patch_oop(address insn_addr, address o);
491
492 static address get_target_of_li32(address insn_addr);
493 static int patch_imm_in_li32(address branch, int32_t target);
494
495 // Return whether code is emitted to a scratch blob.
496 virtual bool in_scratch_emit_size() {
497 return false;
498 }
499
500 address emit_reloc_call_address_stub(int insts_call_instruction_offset, address target);
501 static int max_reloc_call_address_stub_size();
502
503 void emit_static_call_stub();
504 static int static_call_stub_size();
505
506 // The following 4 methods return the offset of the appropriate move instruction
507
508 // Support for fast byte/short loading with zero extension (depending on particular CPU)
509 int load_unsigned_byte(Register dst, Address src);
510 int load_unsigned_short(Register dst, Address src);
511
512 // Support for fast byte/short loading with sign extension (depending on particular CPU)
513 int load_signed_byte(Register dst, Address src);
514 int load_signed_short(Register dst, Address src);
515
516 // Load and store values by size and signed-ness
517 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
518 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
519
520 // Misaligned loads, will use the best way, according to the AvoidUnalignedAccess flag
521 void load_short_misaligned(Register dst, Address src, Register tmp, bool is_signed, int granularity = 1);
522 void load_int_misaligned(Register dst, Address src, Register tmp, bool is_signed, int granularity = 1);
523 void load_long_misaligned(Register dst, Address src, Register tmp, int granularity = 1);
524
525 public:
526 // Standard pseudo instructions
527 inline void nop() {
528 addi(x0, x0, 0);
529 }
530
531 inline void mv(Register Rd, Register Rs) {
532 if (Rd != Rs) {
533 addi(Rd, Rs, 0);
534 }
535 }
536
537 inline void notr(Register Rd, Register Rs) {
538 if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
539 c_not(Rd);
540 } else {
541 xori(Rd, Rs, -1);
542 }
543 }
544
545 inline void neg(Register Rd, Register Rs) {
546 sub(Rd, x0, Rs);
547 }
548
549 inline void negw(Register Rd, Register Rs) {
550 subw(Rd, x0, Rs);
551 }
552
553 inline void sext_w(Register Rd, Register Rs) {
554 addiw(Rd, Rs, 0);
555 }
556
557 inline void zext_b(Register Rd, Register Rs) {
558 if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
559 c_zext_b(Rd);
560 } else {
561 andi(Rd, Rs, 0xFF);
562 }
563 }
564
565 inline void seqz(Register Rd, Register Rs) {
566 sltiu(Rd, Rs, 1);
567 }
568
569 inline void snez(Register Rd, Register Rs) {
570 sltu(Rd, x0, Rs);
571 }
572
573 inline void sltz(Register Rd, Register Rs) {
574 slt(Rd, Rs, x0);
575 }
576
577 inline void sgtz(Register Rd, Register Rs) {
578 slt(Rd, x0, Rs);
579 }
580
581 // Bit-manipulation extension pseudo instructions
582 // zero extend word
583 inline void zext_w(Register Rd, Register Rs) {
584 assert(UseZba, "must be");
585 if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
586 c_zext_w(Rd);
587 } else {
588 add_uw(Rd, Rs, zr);
589 }
590 }
591
592 // Floating-point data-processing pseudo instructions
593 inline void fmv_s(FloatRegister Rd, FloatRegister Rs) {
594 if (Rd != Rs) {
595 fsgnj_s(Rd, Rs, Rs);
596 }
597 }
598
599 inline void fabs_s(FloatRegister Rd, FloatRegister Rs) {
600 fsgnjx_s(Rd, Rs, Rs);
601 }
602
603 inline void fneg_s(FloatRegister Rd, FloatRegister Rs) {
604 fsgnjn_s(Rd, Rs, Rs);
605 }
606
607 inline void fmv_d(FloatRegister Rd, FloatRegister Rs) {
608 if (Rd != Rs) {
609 fsgnj_d(Rd, Rs, Rs);
610 }
611 }
612
613 inline void fabs_d(FloatRegister Rd, FloatRegister Rs) {
614 fsgnjx_d(Rd, Rs, Rs);
615 }
616
617 inline void fneg_d(FloatRegister Rd, FloatRegister Rs) {
618 fsgnjn_d(Rd, Rs, Rs);
619 }
620
621 // Control and status pseudo instructions
622 void csrr(Register Rd, unsigned csr); // read csr
623 void csrw(unsigned csr, Register Rs); // write csr
624 void csrs(unsigned csr, Register Rs); // set bits in csr
625 void csrc(unsigned csr, Register Rs); // clear bits in csr
626 void csrwi(unsigned csr, unsigned imm);
627 void csrsi(unsigned csr, unsigned imm);
628 void csrci(unsigned csr, unsigned imm);
629 void frcsr(Register Rd) { csrr(Rd, CSR_FCSR); }; // read float-point csr
630 void fscsr(Register Rd, Register Rs); // swap float-point csr
631 void fscsr(Register Rs); // write float-point csr
632 void frrm(Register Rd) { csrr(Rd, CSR_FRM); }; // read float-point rounding mode
633 void fsrm(Register Rd, Register Rs); // swap float-point rounding mode
634 void fsrm(Register Rs); // write float-point rounding mode
635 void fsrmi(Register Rd, unsigned imm);
636 void fsrmi(unsigned imm);
637 void frflags(Register Rd) { csrr(Rd, CSR_FFLAGS); }; // read float-point exception flags
638 void fsflags(Register Rd, Register Rs); // swap float-point exception flags
639 void fsflags(Register Rs); // write float-point exception flags
640 void fsflagsi(Register Rd, unsigned imm);
641 void fsflagsi(unsigned imm);
642 // Requires Zicntr
643 void rdinstret(Register Rd) { csrr(Rd, CSR_INSTRET); }; // read instruction-retired counter
644 void rdcycle(Register Rd) { csrr(Rd, CSR_CYCLE); }; // read cycle counter
645 void rdtime(Register Rd) { csrr(Rd, CSR_TIME); }; // read time
646
647 // Restore cpu control state after JNI call
648 void restore_cpu_control_state_after_jni(Register tmp);
649
650 // Control transfer pseudo instructions
651 void beqz(Register Rs, const address dest);
652 void bnez(Register Rs, const address dest);
653 void blez(Register Rs, const address dest);
654 void bgez(Register Rs, const address dest);
655 void bltz(Register Rs, const address dest);
656 void bgtz(Register Rs, const address dest);
657
658 void cmov_eq(Register cmp1, Register cmp2, Register dst, Register src);
659 void cmov_ne(Register cmp1, Register cmp2, Register dst, Register src);
660 void cmov_le(Register cmp1, Register cmp2, Register dst, Register src);
661 void cmov_leu(Register cmp1, Register cmp2, Register dst, Register src);
662 void cmov_ge(Register cmp1, Register cmp2, Register dst, Register src);
663 void cmov_geu(Register cmp1, Register cmp2, Register dst, Register src);
664 void cmov_lt(Register cmp1, Register cmp2, Register dst, Register src);
665 void cmov_ltu(Register cmp1, Register cmp2, Register dst, Register src);
666 void cmov_gt(Register cmp1, Register cmp2, Register dst, Register src);
667 void cmov_gtu(Register cmp1, Register cmp2, Register dst, Register src);
668
669 void cmov_cmp_fp_eq(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
670 void cmov_cmp_fp_ne(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
671 void cmov_cmp_fp_le(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
672 void cmov_cmp_fp_ge(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
673 void cmov_cmp_fp_lt(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
674 void cmov_cmp_fp_gt(FloatRegister cmp1, FloatRegister cmp2, Register dst, Register src, bool is_single);
675
676 void cmov_fp_eq(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
677 void cmov_fp_ne(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
678 void cmov_fp_le(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
679 void cmov_fp_leu(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
680 void cmov_fp_ge(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
681 void cmov_fp_geu(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
682 void cmov_fp_lt(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
683 void cmov_fp_ltu(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
684 void cmov_fp_gt(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
685 void cmov_fp_gtu(Register cmp1, Register cmp2, FloatRegister dst, FloatRegister src, bool is_single);
686
687 void cmov_fp_cmp_fp_eq(FloatRegister cmp1, FloatRegister cmp2, FloatRegister dst, FloatRegister src, bool cmp_single, bool cmov_single);
688 void cmov_fp_cmp_fp_ne(FloatRegister cmp1, FloatRegister cmp2, FloatRegister dst, FloatRegister src, bool cmp_single, bool cmov_single);
689 void cmov_fp_cmp_fp_le(FloatRegister cmp1, FloatRegister cmp2, FloatRegister dst, FloatRegister src, bool cmp_single, bool cmov_single);
690 void cmov_fp_cmp_fp_ge(FloatRegister cmp1, FloatRegister cmp2, FloatRegister dst, FloatRegister src, bool cmp_single, bool cmov_single);
691 void cmov_fp_cmp_fp_lt(FloatRegister cmp1, FloatRegister cmp2, FloatRegister dst, FloatRegister src, bool cmp_single, bool cmov_single);
692 void cmov_fp_cmp_fp_gt(FloatRegister cmp1, FloatRegister cmp2, FloatRegister dst, FloatRegister src, bool cmp_single, bool cmov_single);
693
694 public:
695 // We try to follow risc-v asm menomics.
696 // But as we don't layout a reachable GOT,
697 // we often need to resort to movptr, li <48imm>.
698 // https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc
699
700 // Hotspot only use the standard calling convention using x1/ra.
701 // The alternative calling convection using x5/t0 is not used.
702 // Using x5 as a temp causes the CPU to mispredict returns.
703
704 // JALR, return address stack updates:
705 // | rd is x1/x5 | rs1 is x1/x5 | rd=rs1 | RAS action
706 // | ----------- | ------------ | ------ |-------------
707 // | No | No | - | None
708 // | No | Yes | - | Pop
709 // | Yes | No | - | Push
710 // | Yes | Yes | No | Pop, then push
711 // | Yes | Yes | Yes | Push
712 //
713 // JAL, return address stack updates:
714 // | rd is x1/x5 | RAS action
715 // | ----------- | ----------
716 // | Yes | Push
717 // | No | None
718 //
719 // JUMPs uses Rd = x0/zero and Rs = x6/t1 or imm
720 // CALLS uses Rd = x1/ra and Rs = x6/t1 or imm (or x1/ra*)
721 // RETURNS uses Rd = x0/zero and Rs = x1/ra
722 // *use of x1/ra should not normally be used, special case only.
723
724 // jump: jal x0, offset
725 // For long reach uses temp register for:
726 // la + jr
727 void j(const address dest, Register temp = t1);
728 void j(const Address &dest, Register temp = t1);
729 void j(Label &l, Register temp = noreg);
730
731 // jump register: jalr x0, offset(rs)
732 void jr(Register Rd, int32_t offset = 0);
733
734 // call: la + jalr x1
735 void call(const address dest, Register temp = t1);
736
737 // jalr: jalr x1, offset(rs)
738 void jalr(Register Rs, int32_t offset = 0);
739
740 // Emit a runtime call. Only invalidates the tmp register which
741 // is used to keep the entry address for jalr/movptr.
742 // Uses call() for intra code cache, else movptr + jalr.
743 // Clobebrs t1
744 void rt_call(address dest, Register tmp = t1);
745
746 // ret: jalr x0, 0(x1)
747 inline void ret() {
748 Assembler::jalr(x0, x1, 0);
749 }
750
751 //label
752 void beqz(Register Rs, Label &l, bool is_far = false);
753 void bnez(Register Rs, Label &l, bool is_far = false);
754 void blez(Register Rs, Label &l, bool is_far = false);
755 void bgez(Register Rs, Label &l, bool is_far = false);
756 void bltz(Register Rs, Label &l, bool is_far = false);
757 void bgtz(Register Rs, Label &l, bool is_far = false);
758
759 void beq (Register Rs1, Register Rs2, Label &L, bool is_far = false);
760 void bne (Register Rs1, Register Rs2, Label &L, bool is_far = false);
761 void blt (Register Rs1, Register Rs2, Label &L, bool is_far = false);
762 void bge (Register Rs1, Register Rs2, Label &L, bool is_far = false);
763 void bltu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
764 void bgeu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
765
766 void bgt (Register Rs, Register Rt, const address dest);
767 void ble (Register Rs, Register Rt, const address dest);
768 void bgtu(Register Rs, Register Rt, const address dest);
769 void bleu(Register Rs, Register Rt, const address dest);
770
771 void bgt (Register Rs, Register Rt, Label &l, bool is_far = false);
772 void ble (Register Rs, Register Rt, Label &l, bool is_far = false);
773 void bgtu(Register Rs, Register Rt, Label &l, bool is_far = false);
774 void bleu(Register Rs, Register Rt, Label &l, bool is_far = false);
775
776 #define INSN_ENTRY_RELOC(result_type, header) \
777 result_type header { \
778 guarantee(rtype == relocInfo::internal_word_type, \
779 "only internal_word_type relocs make sense here"); \
780 relocate(InternalAddress(dest).rspec()); \
781 IncompressibleScope scope(this); /* relocations */
782
783 #define INSN(NAME) \
784 void NAME(Register Rs1, Register Rs2, const address dest) { \
785 assert_cond(dest != nullptr); \
786 int64_t offset = dest - pc(); \
787 guarantee(is_simm13(offset) && is_even(offset), \
788 "offset is invalid: is_simm_13: %s offset: " INT64_FORMAT, \
789 BOOL_TO_STR(is_simm13(offset)), offset); \
790 Assembler::NAME(Rs1, Rs2, offset); \
791 } \
792 INSN_ENTRY_RELOC(void, NAME(Register Rs1, Register Rs2, address dest, relocInfo::relocType rtype)) \
793 NAME(Rs1, Rs2, dest); \
794 }
795
796 INSN(beq);
797 INSN(bne);
798 INSN(bge);
799 INSN(bgeu);
800 INSN(blt);
801 INSN(bltu);
802
803 #undef INSN
804
805 #undef INSN_ENTRY_RELOC
806
807 void float_beq(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
808 void float_bne(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
809 void float_ble(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
810 void float_bge(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
811 void float_blt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
812 void float_bgt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
813
814 void double_beq(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
815 void double_bne(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
816 void double_ble(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
817 void double_bge(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
818 void double_blt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
819 void double_bgt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
820
821 private:
822 // The signed 20-bit upper imm can materialize at most negative 0xF...F80000000, two G.
823 // The following signed 12-bit imm can at max subtract 0x800, two K, from that previously loaded two G.
824 bool is_valid_32bit_offset(int64_t x) {
825 constexpr int64_t twoG = (2 * G);
826 constexpr int64_t twoK = (2 * K);
827 return x < (twoG - twoK) && x >= (-twoG - twoK);
828 }
829
830 // Ensure that the auipc can reach the destination at x from anywhere within
831 // the code cache so that if it is relocated we know it will still reach.
832 bool is_32bit_offset_from_codecache(int64_t x) {
833 int64_t low = (int64_t)CodeCache::low_bound();
834 int64_t high = (int64_t)CodeCache::high_bound();
835 return is_valid_32bit_offset(x - low) && is_valid_32bit_offset(x - high);
836 }
837
838 public:
839 // Stack push and pop individual 64 bit registers
840 void push_reg(Register Rs);
841 void pop_reg(Register Rd);
842
843 int push_reg(RegSet regset, Register stack);
844 int pop_reg(RegSet regset, Register stack);
845
846 int push_fp(FloatRegSet regset, Register stack);
847 int pop_fp(FloatRegSet regset, Register stack);
848
849 #ifdef COMPILER2
850 int push_v(VectorRegSet regset, Register stack);
851 int pop_v(VectorRegSet regset, Register stack);
852 #endif // COMPILER2
853
854 // Push and pop everything that might be clobbered by a native
855 // runtime call except t0 and t1. (They are always
856 // temporary registers, so we don't have to protect them.)
857 // Additional registers can be excluded in a passed RegSet.
858 void push_call_clobbered_registers_except(RegSet exclude);
859 void pop_call_clobbered_registers_except(RegSet exclude);
860
861 void push_call_clobbered_registers() {
862 push_call_clobbered_registers_except(RegSet());
863 }
864 void pop_call_clobbered_registers() {
865 pop_call_clobbered_registers_except(RegSet());
866 }
867
868 void push_CPU_state(bool save_vectors = false, int vector_size_in_bytes = 0);
869 void pop_CPU_state(bool restore_vectors = false, int vector_size_in_bytes = 0);
870
871 void push_cont_fastpath(Register java_thread = xthread);
872 void pop_cont_fastpath(Register java_thread = xthread);
873
874 // if heap base register is used - reinit it with the correct value
875 void reinit_heapbase();
876
877 void bind(Label& L) {
878 Assembler::bind(L);
879 // fences across basic blocks should not be merged
880 code()->clear_last_merge_candidate();
881 }
882
883 typedef void (MacroAssembler::* compare_and_branch_insn)(Register Rs1, Register Rs2, const address dest);
884 typedef void (MacroAssembler::* compare_and_branch_label_insn)(Register Rs1, Register Rs2, Label &L, bool is_far);
885 typedef void (MacroAssembler::* jal_jalr_insn)(Register Rt, address dest);
886
887 void wrap_label(Register r, Label &L, jal_jalr_insn insn);
888 void wrap_label(Register r1, Register r2, Label &L,
889 compare_and_branch_insn insn,
890 compare_and_branch_label_insn neg_insn, bool is_far = false);
891
892 void la(Register Rd, Label &label);
893 void la(Register Rd, const address addr);
894 void la(Register Rd, const address addr, int32_t &offset);
895 void la(Register Rd, const Address &adr);
896
897 void li16u(Register Rd, uint16_t imm);
898 void li32(Register Rd, int32_t imm);
899 void li (Register Rd, int64_t imm); // optimized load immediate
900
901 // mv
902 void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }
903 void mv(Register Rd, address addr, int32_t &offset) {
904 // Split address into a lower 12-bit sign-extended offset and the remainder,
905 // so that the offset could be encoded in jalr or load/store instruction.
906 offset = ((int32_t)(int64_t)addr << 20) >> 20;
907 li(Rd, (int64_t)addr - offset);
908 }
909
910 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
911 inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }
912
913 void mv(Register Rd, RegisterOrConstant src) {
914 if (src.is_register()) {
915 mv(Rd, src.as_register());
916 } else {
917 mv(Rd, src.as_constant());
918 }
919 }
920
921 // Generates a load of a 48-bit constant which can be
922 // patched to any 48-bit constant, i.e. address.
923 // If common case supply additional temp register
924 // to shorten the instruction sequence.
925 void movptr(Register Rd, const Address &addr, Register tmp = noreg);
926 void movptr(Register Rd, address addr, Register tmp = noreg);
927 void movptr(Register Rd, address addr, int32_t &offset, Register tmp = noreg);
928
929 private:
930 void movptr1(Register Rd, uintptr_t addr, int32_t &offset);
931 void movptr2(Register Rd, uintptr_t addr, int32_t &offset, Register tmp);
932 public:
933 // float imm move
934 static bool can_hf_imm_load(short imm);
935 static bool can_fp_imm_load(float imm);
936 static bool can_dp_imm_load(double imm);
937 void fli_h(FloatRegister Rd, short imm);
938 void fli_s(FloatRegister Rd, float imm);
939 void fli_d(FloatRegister Rd, double imm);
940
941 // arith
942 void add (Register Rd, Register Rn, int64_t increment, Register tmp = t0);
943 void sub (Register Rd, Register Rn, int64_t decrement, Register tmp = t0);
944 void addw(Register Rd, Register Rn, int64_t increment, Register tmp = t0);
945 void subw(Register Rd, Register Rn, int64_t decrement, Register tmp = t0);
946
947 void subi(Register Rd, Register Rn, int64_t decrement) {
948 assert(is_simm12(-decrement), "Must be");
949 addi(Rd, Rn, -decrement);
950 }
951
952 void subiw(Register Rd, Register Rn, int64_t decrement) {
953 assert(is_simm12(-decrement), "Must be");
954 addiw(Rd, Rn, -decrement);
955 }
956
957 #define INSN(NAME) \
958 inline void NAME(Register Rd, Register Rs1, Register Rs2) { \
959 Assembler::NAME(Rd, Rs1, Rs2); \
960 }
961
962 INSN(add);
963 INSN(addw);
964 INSN(sub);
965 INSN(subw);
966
967 #undef INSN
968
969 // logic
970 void andrw(Register Rd, Register Rs1, Register Rs2);
971 void orrw(Register Rd, Register Rs1, Register Rs2);
972 void xorrw(Register Rd, Register Rs1, Register Rs2);
973
974 // logic with negate
975 void andn(Register Rd, Register Rs1, Register Rs2);
976 void orn(Register Rd, Register Rs1, Register Rs2);
977
978 // reverse bytes
979 void revbw(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1); // reverse bytes in lower word, sign-extend
980 void revb(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1); // reverse bytes in doubleword
981
982 void ror(Register dst, Register src, Register shift, Register tmp = t0);
983 void ror(Register dst, Register src, uint32_t shift, Register tmp = t0);
984 void rolw(Register dst, Register src, uint32_t shift, Register tmp = t0);
985
986 void orptr(Address adr, RegisterOrConstant src, Register tmp1 = t0, Register tmp2 = t1);
987
988 // Load and Store Instructions
989 #define INSN_ENTRY_RELOC(result_type, header) \
990 result_type header { \
991 guarantee(rtype == relocInfo::internal_word_type, \
992 "only internal_word_type relocs make sense here"); \
993 relocate(InternalAddress(dest).rspec()); \
994 IncompressibleScope scope(this); /* relocations */
995
996 #define INSN(NAME) \
997 void NAME(Register Rd, address dest) { \
998 assert_cond(dest != nullptr); \
999 if (CodeCache::contains(dest)) { \
1000 int64_t distance = dest - pc(); \
1001 assert(is_valid_32bit_offset(distance), "Must be"); \
1002 auipc(Rd, (int32_t)distance + 0x800); \
1003 Assembler::NAME(Rd, Rd, ((int32_t)distance << 20) >> 20); \
1004 } else { \
1005 int32_t offset = 0; \
1006 movptr(Rd, dest, offset); \
1007 Assembler::NAME(Rd, Rd, offset); \
1008 } \
1009 } \
1010 INSN_ENTRY_RELOC(void, NAME(Register Rd, address dest, relocInfo::relocType rtype)) \
1011 NAME(Rd, dest); \
1012 } \
1013 void NAME(Register Rd, const Address &adr, Register temp = t0) { \
1014 switch (adr.getMode()) { \
1015 case Address::literal: { \
1016 relocate(adr.rspec(), [&] { \
1017 NAME(Rd, adr.target()); \
1018 }); \
1019 break; \
1020 } \
1021 case Address::base_plus_offset: { \
1022 if (is_simm12(adr.offset())) { \
1023 Assembler::NAME(Rd, adr.base(), adr.offset()); \
1024 } else { \
1025 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
1026 if (Rd == adr.base()) { \
1027 la(temp, Address(adr.base(), adr.offset() - offset)); \
1028 Assembler::NAME(Rd, temp, offset); \
1029 } else { \
1030 la(Rd, Address(adr.base(), adr.offset() - offset)); \
1031 Assembler::NAME(Rd, Rd, offset); \
1032 } \
1033 } \
1034 break; \
1035 } \
1036 default: \
1037 ShouldNotReachHere(); \
1038 } \
1039 } \
1040 void NAME(Register Rd, Label &L) { \
1041 wrap_label(Rd, L, &MacroAssembler::NAME); \
1042 }
1043
1044 INSN(lb);
1045 INSN(lbu);
1046 INSN(lh);
1047 INSN(lhu);
1048 INSN(lw);
1049 INSN(lwu);
1050 INSN(ld);
1051
1052 #undef INSN
1053
1054 #define INSN(NAME) \
1055 void NAME(FloatRegister Rd, address dest, Register temp = t0) { \
1056 assert_cond(dest != nullptr); \
1057 if (CodeCache::contains(dest)) { \
1058 int64_t distance = dest - pc(); \
1059 assert(is_valid_32bit_offset(distance), "Must be"); \
1060 auipc(temp, (int32_t)distance + 0x800); \
1061 Assembler::NAME(Rd, temp, ((int32_t)distance << 20) >> 20); \
1062 } else { \
1063 int32_t offset = 0; \
1064 movptr(temp, dest, offset); \
1065 Assembler::NAME(Rd, temp, offset); \
1066 } \
1067 } \
1068 INSN_ENTRY_RELOC(void, NAME(FloatRegister Rd, address dest, \
1069 relocInfo::relocType rtype, Register temp = t0)) \
1070 NAME(Rd, dest, temp); \
1071 } \
1072 void NAME(FloatRegister Rd, const Address &adr, Register temp = t0) { \
1073 switch (adr.getMode()) { \
1074 case Address::literal: { \
1075 relocate(adr.rspec(), [&] { \
1076 NAME(Rd, adr.target(), temp); \
1077 }); \
1078 break; \
1079 } \
1080 case Address::base_plus_offset: { \
1081 if (is_simm12(adr.offset())) { \
1082 Assembler::NAME(Rd, adr.base(), adr.offset()); \
1083 } else { \
1084 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
1085 la(temp, Address(adr.base(), adr.offset() - offset)); \
1086 Assembler::NAME(Rd, temp, offset); \
1087 } \
1088 break; \
1089 } \
1090 default: \
1091 ShouldNotReachHere(); \
1092 } \
1093 }
1094
1095 INSN(flh);
1096 INSN(flw);
1097 INSN(fld);
1098
1099 #undef INSN
1100
1101 #define INSN(NAME, REGISTER) \
1102 INSN_ENTRY_RELOC(void, NAME(REGISTER Rs, address dest, \
1103 relocInfo::relocType rtype, Register temp = t0)) \
1104 NAME(Rs, dest, temp); \
1105 }
1106
1107 INSN(sb, Register);
1108 INSN(sh, Register);
1109 INSN(sw, Register);
1110 INSN(sd, Register);
1111 INSN(fsw, FloatRegister);
1112 INSN(fsd, FloatRegister);
1113
1114 #undef INSN
1115
1116 #define INSN(NAME) \
1117 void NAME(Register Rs, address dest, Register temp = t0) { \
1118 assert_cond(dest != nullptr); \
1119 assert_different_registers(Rs, temp); \
1120 if (CodeCache::contains(dest)) { \
1121 int64_t distance = dest - pc(); \
1122 assert(is_valid_32bit_offset(distance), "Must be"); \
1123 auipc(temp, (int32_t)distance + 0x800); \
1124 Assembler::NAME(Rs, temp, ((int32_t)distance << 20) >> 20); \
1125 } else { \
1126 int32_t offset = 0; \
1127 movptr(temp, dest, offset); \
1128 Assembler::NAME(Rs, temp, offset); \
1129 } \
1130 } \
1131 void NAME(Register Rs, const Address &adr, Register temp = t0) { \
1132 switch (adr.getMode()) { \
1133 case Address::literal: { \
1134 assert_different_registers(Rs, temp); \
1135 relocate(adr.rspec(), [&] { \
1136 NAME(Rs, adr.target(), temp); \
1137 }); \
1138 break; \
1139 } \
1140 case Address::base_plus_offset: { \
1141 if (is_simm12(adr.offset())) { \
1142 Assembler::NAME(Rs, adr.base(), adr.offset()); \
1143 } else { \
1144 assert_different_registers(Rs, temp); \
1145 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
1146 la(temp, Address(adr.base(), adr.offset() - offset)); \
1147 Assembler::NAME(Rs, temp, offset); \
1148 } \
1149 break; \
1150 } \
1151 default: \
1152 ShouldNotReachHere(); \
1153 } \
1154 }
1155
1156 INSN(sb);
1157 INSN(sh);
1158 INSN(sw);
1159 INSN(sd);
1160
1161 #undef INSN
1162
1163 #define INSN(NAME) \
1164 void NAME(FloatRegister Rs, address dest, Register temp = t0) { \
1165 assert_cond(dest != nullptr); \
1166 if (CodeCache::contains(dest)) { \
1167 int64_t distance = dest - pc(); \
1168 assert(is_valid_32bit_offset(distance), "Must be"); \
1169 auipc(temp, (int32_t)distance + 0x800); \
1170 Assembler::NAME(Rs, temp, ((int32_t)distance << 20) >> 20); \
1171 } else { \
1172 int32_t offset = 0; \
1173 movptr(temp, dest, offset); \
1174 Assembler::NAME(Rs, temp, offset); \
1175 } \
1176 } \
1177 void NAME(FloatRegister Rs, const Address &adr, Register temp = t0) { \
1178 switch (adr.getMode()) { \
1179 case Address::literal: { \
1180 relocate(adr.rspec(), [&] { \
1181 NAME(Rs, adr.target(), temp); \
1182 }); \
1183 break; \
1184 } \
1185 case Address::base_plus_offset: { \
1186 if (is_simm12(adr.offset())) { \
1187 Assembler::NAME(Rs, adr.base(), adr.offset()); \
1188 } else { \
1189 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
1190 la(temp, Address(adr.base(), adr.offset() - offset)); \
1191 Assembler::NAME(Rs, temp, offset); \
1192 } \
1193 break; \
1194 } \
1195 default: \
1196 ShouldNotReachHere(); \
1197 } \
1198 }
1199
1200 INSN(fsw);
1201 INSN(fsd);
1202
1203 #undef INSN
1204
1205 #undef INSN_ENTRY_RELOC
1206
1207 void cmpxchg(Register addr, Register expected,
1208 Register new_val,
1209 Assembler::operand_size size,
1210 Assembler::Aqrl acquire, Assembler::Aqrl release,
1211 Register result, bool result_as_bool = false);
1212 void weak_cmpxchg(Register addr, Register expected,
1213 Register new_val,
1214 Assembler::operand_size size,
1215 Assembler::Aqrl acquire, Assembler::Aqrl release,
1216 Register result);
1217 void cmpxchg_narrow_value_helper(Register addr, Register expected, Register new_val,
1218 Assembler::operand_size size,
1219 Register shift, Register mask, Register aligned_addr);
1220 void cmpxchg_narrow_value(Register addr, Register expected,
1221 Register new_val,
1222 Assembler::operand_size size,
1223 Assembler::Aqrl acquire, Assembler::Aqrl release,
1224 Register result, bool result_as_bool,
1225 Register tmp1, Register tmp2, Register tmp3);
1226 void weak_cmpxchg_narrow_value(Register addr, Register expected,
1227 Register new_val,
1228 Assembler::operand_size size,
1229 Assembler::Aqrl acquire, Assembler::Aqrl release,
1230 Register result,
1231 Register tmp1, Register tmp2, Register tmp3);
1232
1233 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1234 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1235 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1236 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1237
1238 void atomic_xchg(Register prev, Register newv, Register addr);
1239 void atomic_xchgw(Register prev, Register newv, Register addr);
1240 void atomic_xchgal(Register prev, Register newv, Register addr);
1241 void atomic_xchgalw(Register prev, Register newv, Register addr);
1242 void atomic_xchgwu(Register prev, Register newv, Register addr);
1243 void atomic_xchgalwu(Register prev, Register newv, Register addr);
1244
1245 void atomic_cas(Register prev, Register newv, Register addr, Assembler::operand_size size,
1246 Assembler::Aqrl acquire = Assembler::relaxed, Assembler::Aqrl release = Assembler::relaxed);
1247
1248 // Emit a far call/jump. Only invalidates the tmp register which
1249 // is used to keep the entry address for jalr.
1250 // The address must be inside the code cache.
1251 // Supported entry.rspec():
1252 // - relocInfo::external_word_type
1253 // - relocInfo::runtime_call_type
1254 // - relocInfo::none
1255 // Clobbers t1 default.
1256 void far_call(const Address &entry, Register tmp = t1);
1257 void far_jump(const Address &entry, Register tmp = t1);
1258
1259 static int far_branch_size() {
1260 return 2 * MacroAssembler::instruction_size; // auipc + jalr, see far_call() & far_jump()
1261 }
1262
1263 void load_byte_map_base(Register reg);
1264
1265 void bang_stack_with_offset(int offset) {
1266 // stack grows down, caller passes positive offset
1267 assert(offset > 0, "must bang with negative offset");
1268 sub(t0, sp, offset);
1269 sd(zr, Address(t0));
1270 }
1271
1272 virtual void _call_Unimplemented(address call_site) {
1273 mv(t1, call_site);
1274 }
1275
1276 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
1277
1278 // Frame creation and destruction shared between JITs.
1279 void build_frame(int framesize);
1280 void remove_frame(int framesize);
1281
1282 void reserved_stack_check();
1283
1284 void get_polling_page(Register dest, relocInfo::relocType rtype);
1285 void read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype);
1286
1287 // RISCV64 OpenJDK uses three different types of calls:
1288 //
1289 // - far call: auipc reg, pc_relative_offset; jalr ra, reg, offset
1290 // The offset has the range [-(2G + 2K), 2G - 2K). Addresses out of the
1291 // range in the code cache requires indirect call.
1292 // If a jump is needed rather than a call, a far jump 'jalr x0, reg, offset'
1293 // can be used instead.
1294 // All instructions are embedded at a call site.
1295 //
1296 // - indirect call: movptr + jalr
1297 // This can reach anywhere in the address space, but it cannot be patched
1298 // while code is running, so it must only be modified at a safepoint.
1299 // This form of call is most suitable for targets at fixed addresses,
1300 // which will never be patched.
1301 //
1302 // - reloc call:
1303 // This too can reach anywhere in the address space but is only available
1304 // in C1/C2-generated code (nmethod).
1305 //
1306 // [Main code section]
1307 // auipc
1308 // ld <address_from_stub_section>
1309 // jalr
1310 //
1311 // [Stub section]
1312 // address stub:
1313 // <64-bit destination address>
1314 //
1315 // To change the destination we simply atomically store the new
1316 // address in the stub section.
1317 // There is a benign race in that the other thread might observe the old
1318 // 64-bit destination address before it observes the new address. That does
1319 // not matter because the destination method has been invalidated, so there
1320 // will be a trap at its start.
1321
1322 // Emit a reloc call and create a stub to hold the entry point address.
1323 // Supported entry.rspec():
1324 // - relocInfo::runtime_call_type
1325 // - relocInfo::opt_virtual_call_type
1326 // - relocInfo::static_call_type
1327 // - relocInfo::virtual_call_type
1328 //
1329 // Return: the call PC or nullptr if CodeCache is full.
1330 address reloc_call(Address entry, Register tmp = t1);
1331
1332 address ic_call(address entry, jint method_index = 0);
1333 static int ic_check_size();
1334 int ic_check(int end_alignment = MacroAssembler::instruction_size);
1335
1336 // Support for memory inc/dec
1337 // n.b. increment/decrement calls with an Address destination will
1338 // need to use a scratch register to load the value to be
1339 // incremented. increment/decrement calls which add or subtract a
1340 // constant value other than sign-extended 12-bit immediate will need
1341 // to use a 2nd scratch register to hold the constant. so, an address
1342 // increment/decrement may trash both t0 and t1.
1343
1344 void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1345 void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1346
1347 void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1348 void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1349
1350 void clinit_barrier(Register klass, Register tmp, Label* L_fast_path = nullptr, Label* L_slow_path = nullptr);
1351
1352 void load_method_holder_cld(Register result, Register method);
1353 void load_method_holder(Register holder, Register method);
1354
1355 void compute_index(Register str1, Register trailing_zeros, Register match_mask,
1356 Register result, Register char_tmp, Register tmp,
1357 bool haystack_isL);
1358 void compute_match_mask(Register src, Register pattern, Register match_mask,
1359 Register mask1, Register mask2);
1360
1361 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1362 void kernel_crc32(Register crc, Register buf, Register len,
1363 Register table0, Register table1, Register table2, Register table3,
1364 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register tmp6);
1365 void update_word_crc32(Register crc, Register v, Register tmp1, Register tmp2, Register tmp3,
1366 Register table0, Register table1, Register table2, Register table3,
1367 bool upper);
1368 void update_byte_crc32(Register crc, Register val, Register table);
1369
1370 #ifdef COMPILER2
1371 void vector_update_crc32(Register crc, Register buf, Register len,
1372 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
1373 Register table0, Register table3);
1374 void kernel_crc32_vclmul_fold(Register crc, Register buf, Register len,
1375 Register table0, Register table1, Register table2, Register table3,
1376 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1377 void crc32_vclmul_fold_to_16_bytes_vectorsize_32(VectorRegister vx, VectorRegister vy, VectorRegister vt,
1378 VectorRegister vtmp1, VectorRegister vtmp2, VectorRegister vtmp3, VectorRegister vtmp4);
1379 void kernel_crc32_vclmul_fold_vectorsize_32(Register crc, Register buf, Register len,
1380 Register vclmul_table, Register tmp1, Register tmp2);
1381 void crc32_vclmul_fold_16_bytes_vectorsize_16(VectorRegister vx, VectorRegister vt,
1382 VectorRegister vtmp1, VectorRegister vtmp2, VectorRegister vtmp3, VectorRegister vtmp4,
1383 Register buf, Register tmp, const int STEP);
1384 void crc32_vclmul_fold_16_bytes_vectorsize_16_2(VectorRegister vx, VectorRegister vy, VectorRegister vt,
1385 VectorRegister vtmp1, VectorRegister vtmp2, VectorRegister vtmp3, VectorRegister vtmp4,
1386 Register tmp);
1387 void crc32_vclmul_fold_16_bytes_vectorsize_16_3(VectorRegister vx, VectorRegister vy, VectorRegister vt,
1388 VectorRegister vtmp1, VectorRegister vtmp2, VectorRegister vtmp3, VectorRegister vtmp4,
1389 Register tmp);
1390 void kernel_crc32_vclmul_fold_vectorsize_16(Register crc, Register buf, Register len,
1391 Register vclmul_table, Register tmp1, Register tmp2);
1392
1393 void mul_add(Register out, Register in, Register offset,
1394 Register len, Register k, Register tmp);
1395 void wide_mul(Register prod_lo, Register prod_hi, Register n, Register m);
1396 void wide_madd(Register sum_lo, Register sum_hi, Register n,
1397 Register m, Register tmp1, Register tmp2);
1398 void cad(Register dst, Register src1, Register src2, Register carry);
1399 void cadc(Register dst, Register src1, Register src2, Register carry);
1400 void adc(Register dst, Register src1, Register src2, Register carry);
1401 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1402 Register src1, Register src2, Register carry);
1403 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1404 Register y, Register y_idx, Register z,
1405 Register carry, Register product,
1406 Register idx, Register kdx);
1407 void multiply_128_x_128_loop(Register y, Register z,
1408 Register carry, Register carry2,
1409 Register idx, Register jdx,
1410 Register yz_idx1, Register yz_idx2,
1411 Register tmp, Register tmp3, Register tmp4,
1412 Register tmp6, Register product_hi);
1413 void multiply_to_len(Register x, Register xlen, Register y, Register ylen,
1414 Register z, Register tmp0,
1415 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
1416 Register tmp5, Register tmp6, Register product_hi);
1417
1418 #endif // COMPILER2
1419
1420 void inflate_lo32(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);
1421 void inflate_hi32(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);
1422
1423 void ctzc_bits(Register Rd, Register Rs, bool isLL = false,
1424 Register tmp1 = t0, Register tmp2 = t1);
1425
1426 void zero_words(Register base, uint64_t cnt);
1427 address zero_words(Register ptr, Register cnt);
1428 void fill_words(Register base, Register cnt, Register value);
1429 void zero_memory(Register addr, Register len, Register tmp);
1430 void zero_dcache_blocks(Register base, Register cnt, Register tmp1, Register tmp2);
1431
1432 // shift left by shamt and add
1433 void shadd(Register Rd, Register Rs1, Register Rs2, Register tmp, int shamt);
1434
1435 // test single bit in Rs, result is set to Rd
1436 void test_bit(Register Rd, Register Rs, uint32_t bit_pos);
1437
1438 // Here the float instructions with safe deal with some exceptions.
1439 // e.g. convert from NaN, +Inf, -Inf to int, float, double
1440 // will trigger exception, we need to deal with these situations
1441 // to get correct results.
1442 void fcvt_w_s_safe(Register dst, FloatRegister src, Register tmp = t0);
1443 void fcvt_l_s_safe(Register dst, FloatRegister src, Register tmp = t0);
1444 void fcvt_w_d_safe(Register dst, FloatRegister src, Register tmp = t0);
1445 void fcvt_l_d_safe(Register dst, FloatRegister src, Register tmp = t0);
1446
1447 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1448 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1449
1450 // Helper routine processing the slow path of NaN when converting float to float16
1451 void float_to_float16_NaN(Register dst, FloatRegister src, Register tmp1, Register tmp2);
1452
1453 // vector load/store unit-stride instructions
1454 void vlex_v(VectorRegister vd, Register base, Assembler::SEW sew, VectorMask vm = unmasked) {
1455 switch (sew) {
1456 case Assembler::e64:
1457 vle64_v(vd, base, vm);
1458 break;
1459 case Assembler::e32:
1460 vle32_v(vd, base, vm);
1461 break;
1462 case Assembler::e16:
1463 vle16_v(vd, base, vm);
1464 break;
1465 case Assembler::e8: // fall through
1466 default:
1467 vle8_v(vd, base, vm);
1468 break;
1469 }
1470 }
1471
1472 void vsex_v(VectorRegister store_data, Register base, Assembler::SEW sew, VectorMask vm = unmasked) {
1473 switch (sew) {
1474 case Assembler::e64:
1475 vse64_v(store_data, base, vm);
1476 break;
1477 case Assembler::e32:
1478 vse32_v(store_data, base, vm);
1479 break;
1480 case Assembler::e16:
1481 vse16_v(store_data, base, vm);
1482 break;
1483 case Assembler::e8: // fall through
1484 default:
1485 vse8_v(store_data, base, vm);
1486 break;
1487 }
1488 }
1489
1490 // vector pseudo instructions
1491 // rotate vector register left with shift bits, 32-bit version
1492 inline void vrole32_vi(VectorRegister vd, uint32_t shift, VectorRegister tmp_vr) {
1493 vsrl_vi(tmp_vr, vd, 32 - shift);
1494 vsll_vi(vd, vd, shift);
1495 vor_vv(vd, vd, tmp_vr);
1496 }
1497
1498 inline void vl1r_v(VectorRegister vd, Register rs) {
1499 vl1re8_v(vd, rs);
1500 }
1501
1502 inline void vmnot_m(VectorRegister vd, VectorRegister vs) {
1503 vmnand_mm(vd, vs, vs);
1504 }
1505
1506 inline void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1507 vnsrl_wx(vd, vs, x0, vm);
1508 }
1509
1510 inline void vneg_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1511 vrsub_vx(vd, vs, x0, vm);
1512 }
1513
1514 inline void vfneg_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1515 vfsgnjn_vv(vd, vs, vs, vm);
1516 }
1517
1518 inline void vfabs_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1519 vfsgnjx_vv(vd, vs, vs, vm);
1520 }
1521
1522 inline void vmsgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1523 vmslt_vv(vd, vs1, vs2, vm);
1524 }
1525
1526 inline void vmsgtu_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1527 vmsltu_vv(vd, vs1, vs2, vm);
1528 }
1529
1530 inline void vmsge_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1531 vmsle_vv(vd, vs1, vs2, vm);
1532 }
1533
1534 inline void vmsgeu_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1535 vmsleu_vv(vd, vs1, vs2, vm);
1536 }
1537
1538 inline void vmfgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1539 vmflt_vv(vd, vs1, vs2, vm);
1540 }
1541
1542 inline void vmfge_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1543 vmfle_vv(vd, vs1, vs2, vm);
1544 }
1545
1546 inline void vmsltu_vi(VectorRegister Vd, VectorRegister Vs2, uint32_t imm, VectorMask vm = unmasked) {
1547 guarantee(imm >= 1 && imm <= 16, "imm is invalid");
1548 vmsleu_vi(Vd, Vs2, imm-1, vm);
1549 }
1550
1551 inline void vmsgeu_vi(VectorRegister Vd, VectorRegister Vs2, uint32_t imm, VectorMask vm = unmasked) {
1552 guarantee(imm >= 1 && imm <= 16, "imm is invalid");
1553 vmsgtu_vi(Vd, Vs2, imm-1, vm);
1554 }
1555
1556 // Copy mask register
1557 inline void vmmv_m(VectorRegister vd, VectorRegister vs) {
1558 vmand_mm(vd, vs, vs);
1559 }
1560
1561 // Clear mask register
1562 inline void vmclr_m(VectorRegister vd) {
1563 vmxor_mm(vd, vd, vd);
1564 }
1565
1566 // Set mask register
1567 inline void vmset_m(VectorRegister vd) {
1568 vmxnor_mm(vd, vd, vd);
1569 }
1570
1571 inline void vnot_v(VectorRegister Vd, VectorRegister Vs, VectorMask vm = unmasked) {
1572 vxor_vi(Vd, Vs, -1, vm);
1573 }
1574
1575 static const int zero_words_block_size;
1576
1577 void cast_primitive_type(BasicType type, Register Rt) {
1578 switch (type) {
1579 case T_BOOLEAN:
1580 sltu(Rt, zr, Rt);
1581 break;
1582 case T_CHAR :
1583 zext(Rt, Rt, 16);
1584 break;
1585 case T_BYTE :
1586 sext(Rt, Rt, 8);
1587 break;
1588 case T_SHORT :
1589 sext(Rt, Rt, 16);
1590 break;
1591 case T_INT :
1592 sext(Rt, Rt, 32);
1593 break;
1594 case T_LONG : /* nothing to do */ break;
1595 case T_VOID : /* nothing to do */ break;
1596 case T_FLOAT : /* nothing to do */ break;
1597 case T_DOUBLE : /* nothing to do */ break;
1598 default: ShouldNotReachHere();
1599 }
1600 }
1601
1602 // float cmp with unordered_result
1603 void float_compare(Register result, FloatRegister Rs1, FloatRegister Rs2, int unordered_result);
1604 void double_compare(Register result, FloatRegister Rs1, FloatRegister Rs2, int unordered_result);
1605
1606 // Zero/Sign-extend
1607 void zext(Register dst, Register src, int bits);
1608 void sext(Register dst, Register src, int bits);
1609
1610 private:
1611 void cmp_x2i(Register dst, Register src1, Register src2, Register tmp, bool is_signed = true);
1612
1613 public:
1614 // compare src1 and src2 and get -1/0/1 in dst.
1615 // if [src1 > src2], dst = 1;
1616 // if [src1 == src2], dst = 0;
1617 // if [src1 < src2], dst = -1;
1618 void cmp_l2i(Register dst, Register src1, Register src2, Register tmp = t0);
1619 void cmp_ul2i(Register dst, Register src1, Register src2, Register tmp = t0);
1620 void cmp_uw2i(Register dst, Register src1, Register src2, Register tmp = t0);
1621
1622 // support for argument shuffling
1623 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = t0);
1624 void float_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
1625 void long_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
1626 void double_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
1627 void object_move(OopMap* map,
1628 int oop_handle_offset,
1629 int framesize_in_slots,
1630 VMRegPair src,
1631 VMRegPair dst,
1632 bool is_receiver,
1633 int* receiver_offset);
1634
1635 #ifdef ASSERT
1636 // Template short-hand support to clean-up after a failed call to trampoline
1637 // call generation (see trampoline_call() below), when a set of Labels must
1638 // be reset (before returning).
1639 template<typename Label, typename... More>
1640 void reset_labels(Label& lbl, More&... more) {
1641 lbl.reset(); reset_labels(more...);
1642 }
1643 template<typename Label>
1644 void reset_labels(Label& lbl) {
1645 lbl.reset();
1646 }
1647 #endif
1648
1649 private:
1650
1651 void repne_scan(Register addr, Register value, Register count, Register tmp);
1652
1653 int bitset_to_regs(unsigned int bitset, unsigned char* regs);
1654 Address add_memory_helper(const Address dst, Register tmp);
1655
1656 void load_reserved(Register dst, Register addr, Assembler::operand_size size, Assembler::Aqrl acquire);
1657 void store_conditional(Register dst, Register new_val, Register addr, Assembler::operand_size size, Assembler::Aqrl release);
1658
1659 public:
1660 void fast_lock(Register basic_lock, Register obj, Register tmp1, Register tmp2, Register tmp3, Label& slow);
1661 void fast_unlock(Register obj, Register tmp1, Register tmp2, Register tmp3, Label& slow);
1662
1663 public:
1664 enum {
1665 // movptr
1666 movptr1_instruction_size = 6 * MacroAssembler::instruction_size, // lui, addi, slli, addi, slli, addi. See movptr1().
1667 movptr2_instruction_size = 5 * MacroAssembler::instruction_size, // lui, lui, slli, add, addi. See movptr2().
1668 load_pc_relative_instruction_size = 2 * MacroAssembler::instruction_size // auipc, ld
1669 };
1670
1671 static bool is_load_pc_relative_at(address branch);
1672 static bool is_li16u_at(address instr);
1673
1674 static bool is_jal_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b1101111; }
1675 static bool is_jalr_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b1100111 && extract_funct3(instr) == 0b000; }
1676 static bool is_branch_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b1100011; }
1677 static bool is_ld_at(address instr) { assert_cond(instr != nullptr); return is_load_at(instr) && extract_funct3(instr) == 0b011; }
1678 static bool is_load_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0000011; }
1679 static bool is_float_load_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0000111; }
1680 static bool is_auipc_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0010111; }
1681 static bool is_jump_at(address instr) { assert_cond(instr != nullptr); return is_branch_at(instr) || is_jal_at(instr) || is_jalr_at(instr); }
1682 static bool is_add_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0110011 && extract_funct3(instr) == 0b000; }
1683 static bool is_addi_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0010011 && extract_funct3(instr) == 0b000; }
1684 static bool is_addiw_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0011011 && extract_funct3(instr) == 0b000; }
1685 static bool is_addiw_to_zr_at(address instr){ assert_cond(instr != nullptr); return is_addiw_at(instr) && extract_rd(instr) == zr; }
1686 static bool is_lui_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0110111; }
1687 static bool is_lui_to_zr_at(address instr) { assert_cond(instr != nullptr); return is_lui_at(instr) && extract_rd(instr) == zr; }
1688
1689 static bool is_srli_at(address instr) {
1690 assert_cond(instr != nullptr);
1691 return extract_opcode(instr) == 0b0010011 &&
1692 extract_funct3(instr) == 0b101 &&
1693 Assembler::extract(((unsigned*)instr)[0], 31, 26) == 0b000000;
1694 }
1695
1696 static bool is_slli_shift_at(address instr, uint32_t shift) {
1697 assert_cond(instr != nullptr);
1698 return (extract_opcode(instr) == 0b0010011 && // opcode field
1699 extract_funct3(instr) == 0b001 && // funct3 field, select the type of operation
1700 Assembler::extract(Assembler::ld_instr(instr), 25, 20) == shift); // shamt field
1701 }
1702
1703 static bool is_movptr1_at(address instr);
1704 static bool is_movptr2_at(address instr);
1705
1706 static bool is_lwu_to_zr(address instr);
1707
1708 static Register extract_rs1(address instr);
1709 static Register extract_rs2(address instr);
1710 static Register extract_rd(address instr);
1711 static uint32_t extract_opcode(address instr);
1712 static uint32_t extract_funct3(address instr);
1713
1714 // the instruction sequence of movptr is as below:
1715 // lui
1716 // addi
1717 // slli
1718 // addi
1719 // slli
1720 // addi/jalr/load
1721 static bool check_movptr1_data_dependency(address instr) {
1722 address lui = instr;
1723 address addi1 = lui + MacroAssembler::instruction_size;
1724 address slli1 = addi1 + MacroAssembler::instruction_size;
1725 address addi2 = slli1 + MacroAssembler::instruction_size;
1726 address slli2 = addi2 + MacroAssembler::instruction_size;
1727 address last_instr = slli2 + MacroAssembler::instruction_size;
1728 return extract_rs1(addi1) == extract_rd(lui) &&
1729 extract_rs1(addi1) == extract_rd(addi1) &&
1730 extract_rs1(slli1) == extract_rd(addi1) &&
1731 extract_rs1(slli1) == extract_rd(slli1) &&
1732 extract_rs1(addi2) == extract_rd(slli1) &&
1733 extract_rs1(addi2) == extract_rd(addi2) &&
1734 extract_rs1(slli2) == extract_rd(addi2) &&
1735 extract_rs1(slli2) == extract_rd(slli2) &&
1736 extract_rs1(last_instr) == extract_rd(slli2);
1737 }
1738
1739 // the instruction sequence of movptr2 is as below:
1740 // lui
1741 // lui
1742 // slli
1743 // add
1744 // addi/jalr/load
1745 static bool check_movptr2_data_dependency(address instr) {
1746 address lui1 = instr;
1747 address lui2 = lui1 + MacroAssembler::instruction_size;
1748 address slli = lui2 + MacroAssembler::instruction_size;
1749 address add = slli + MacroAssembler::instruction_size;
1750 address last_instr = add + MacroAssembler::instruction_size;
1751 return extract_rd(add) == extract_rd(lui2) &&
1752 extract_rs1(add) == extract_rd(lui2) &&
1753 extract_rs2(add) == extract_rd(slli) &&
1754 extract_rs1(slli) == extract_rd(lui1) &&
1755 extract_rd(slli) == extract_rd(lui1) &&
1756 extract_rs1(last_instr) == extract_rd(add);
1757 }
1758
1759 // the instruction sequence of li16u is as below:
1760 // lui
1761 // srli
1762 static bool check_li16u_data_dependency(address instr) {
1763 address lui = instr;
1764 address srli = lui + MacroAssembler::instruction_size;
1765
1766 return extract_rs1(srli) == extract_rd(lui) &&
1767 extract_rs1(srli) == extract_rd(srli);
1768 }
1769
1770 // the instruction sequence of li32 is as below:
1771 // lui
1772 // addiw
1773 static bool check_li32_data_dependency(address instr) {
1774 address lui = instr;
1775 address addiw = lui + MacroAssembler::instruction_size;
1776
1777 return extract_rs1(addiw) == extract_rd(lui) &&
1778 extract_rs1(addiw) == extract_rd(addiw);
1779 }
1780
1781 // the instruction sequence of pc-relative is as below:
1782 // auipc
1783 // jalr/addi/load/float_load
1784 static bool check_pc_relative_data_dependency(address instr) {
1785 address auipc = instr;
1786 address last_instr = auipc + MacroAssembler::instruction_size;
1787
1788 return extract_rs1(last_instr) == extract_rd(auipc);
1789 }
1790
1791 // the instruction sequence of load_label is as below:
1792 // auipc
1793 // load
1794 static bool check_load_pc_relative_data_dependency(address instr) {
1795 address auipc = instr;
1796 address load = auipc + MacroAssembler::instruction_size;
1797
1798 return extract_rd(load) == extract_rd(auipc) &&
1799 extract_rs1(load) == extract_rd(load);
1800 }
1801
1802 static bool is_li32_at(address instr);
1803 static bool is_pc_relative_at(address branch);
1804
1805 static bool is_membar(address addr) {
1806 return (Bytes::get_native_u4(addr) & 0x7f) == 0b1111 && extract_funct3(addr) == 0;
1807 }
1808 static uint32_t get_membar_kind(address addr);
1809 static void set_membar_kind(address addr, uint32_t order_kind);
1810 };
1811
1812 #ifdef ASSERT
1813 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1814 #endif
1815
1816 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP