1 //
2 // Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_CompareAndSwapB:
1150 case Op_CompareAndSwapS:
1151 case Op_GetAndSetI:
1152 case Op_GetAndSetL:
1153 case Op_GetAndSetP:
1154 case Op_GetAndSetN:
1155 case Op_GetAndAddI:
1156 case Op_GetAndAddL:
1157 return true;
1158 case Op_CompareAndExchangeI:
1159 case Op_CompareAndExchangeN:
1160 case Op_CompareAndExchangeB:
1161 case Op_CompareAndExchangeS:
1162 case Op_CompareAndExchangeL:
1163 case Op_CompareAndExchangeP:
1164 case Op_WeakCompareAndSwapB:
1165 case Op_WeakCompareAndSwapS:
1166 case Op_WeakCompareAndSwapI:
1167 case Op_WeakCompareAndSwapL:
1168 case Op_WeakCompareAndSwapP:
1169 case Op_WeakCompareAndSwapN:
1170 return maybe_volatile;
1171 default:
1172 return false;
1173 }
1174 }
1175
1176 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1177
1178 // predicate controlling translation of CAS
1179 //
1180 // returns true if CAS needs to use an acquiring load otherwise false
1181 bool needs_acquiring_load_reserved(const Node *n)
1182 {
1183 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1184
1185 LoadStoreNode* ldst = n->as_LoadStore();
1186 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1187 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1188 } else {
1189 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1190 }
1191 // so we can just return true here
1192 return true;
1193 }
1194 #define __ masm->
1195
1196 // advance declarations for helper functions to convert register
1197 // indices to register objects
1198
1199 // the ad file has to provide implementations of certain methods
1200 // expected by the generic code
1201 //
1202 // REQUIRED FUNCTIONALITY
1203
1204 //=============================================================================
1205
1206 // !!!!! Special hack to get all types of calls to specify the byte offset
1207 // from the start of the call to the point where the return address
1208 // will point.
1209
1210 int MachCallStaticJavaNode::ret_addr_offset()
1211 {
1212 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1213 }
1214
1215 int MachCallDynamicJavaNode::ret_addr_offset()
1216 {
1217 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1218 }
1219
1220 int MachCallRuntimeNode::ret_addr_offset() {
1221 // For address inside the code cache the call will be:
1222 // auipc + jalr
1223 // For real runtime callouts it will be 8 instructions
1224 // see riscv_enc_java_to_runtime
1225 // la(t0, retaddr) -> auipc + addi
1226 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1227 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1228 // jalr(t1, offset) -> jalr
1229 if (CodeCache::contains(_entry_point)) {
1230 return 2 * NativeInstruction::instruction_size;
1231 } else if (_entry_point == nullptr) {
1232 // See CallLeafNoFPIndirect
1233 return 1 * NativeInstruction::instruction_size;
1234 } else {
1235 return 8 * NativeInstruction::instruction_size;
1236 }
1237 }
1238
1239 //
1240 // Compute padding required for nodes which need alignment
1241 //
1242
1243 // With RVC a call instruction may get 2-byte aligned.
1244 // The address of the call instruction needs to be 4-byte aligned to
1245 // ensure that it does not span a cache line so that it can be patched.
1246 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1247 {
1248 // to make sure the address of jal 4-byte aligned.
1249 return align_up(current_offset, alignment_required()) - current_offset;
1250 }
1251
1252 // With RVC a call instruction may get 2-byte aligned.
1253 // The address of the call instruction needs to be 4-byte aligned to
1254 // ensure that it does not span a cache line so that it can be patched.
1255 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1256 {
1257 // skip the movptr2 in MacroAssembler::ic_call():
1258 // lui, lui, slli, add, addi
1259 // Though movptr2() has already 4-byte aligned with or without RVC,
1260 // We need to prevent from further changes by explicitly calculating the size.
1261 current_offset += NativeMovConstReg::movptr2_instruction_size;
1262 // to make sure the address of jal 4-byte aligned.
1263 return align_up(current_offset, alignment_required()) - current_offset;
1264 }
1265
1266 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1267 {
1268 return align_up(current_offset, alignment_required()) - current_offset;
1269 }
1270
1271 int CallLeafDirectNode::compute_padding(int current_offset) const
1272 {
1273 return align_up(current_offset, alignment_required()) - current_offset;
1274 }
1275
1276 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1277 {
1278 return align_up(current_offset, alignment_required()) - current_offset;
1279 }
1280
1281 int CallLeafNoFPIndirectNode::compute_padding(int current_offset) const
1282 {
1283 return align_up(current_offset, alignment_required()) - current_offset;
1284 }
1285
1286 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1287 {
1288 return align_up(current_offset, alignment_required()) - current_offset;
1289 }
1290
1291 //=============================================================================
1292
1293 #ifndef PRODUCT
1294 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1295 assert_cond(st != nullptr);
1296 st->print("BREAKPOINT");
1297 }
1298 #endif
1299
1300 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1301 __ ebreak();
1302 }
1303
1304 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1305 return MachNode::size(ra_);
1306 }
1307
1308 //=============================================================================
1309
1310 #ifndef PRODUCT
1311 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1312 st->print("nop \t# %d bytes pad for loops and calls", _count);
1313 }
1314 #endif
1315
1316 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1317 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1318 for (int i = 0; i < _count; i++) {
1319 __ nop();
1320 }
1321 }
1322
1323 uint MachNopNode::size(PhaseRegAlloc*) const {
1324 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1325 }
1326
1327 //=============================================================================
1328 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1329
1330 int ConstantTable::calculate_table_base_offset() const {
1331 return 0; // absolute addressing, no offset
1332 }
1333
1334 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1335 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1336 ShouldNotReachHere();
1337 }
1338
1339 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1340 // Empty encoding
1341 }
1342
1343 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1344 return 0;
1345 }
1346
1347 #ifndef PRODUCT
1348 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1349 assert_cond(st != nullptr);
1350 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1351 }
1352 #endif
1353
1354 #ifndef PRODUCT
1355 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1356 assert_cond(st != nullptr && ra_ != nullptr);
1357 Compile* C = ra_->C;
1358
1359 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1360
1361 if (C->output()->need_stack_bang(framesize)) {
1362 st->print("# stack bang size=%d\n\t", framesize);
1363 }
1364
1365 st->print("sub sp, sp, #%d\n\t", framesize);
1366 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1367 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1368 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1369
1370 if (VerifyStackAtCalls) {
1371 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1372 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1373 }
1374
1375 if (C->stub_function() == nullptr) {
1376 st->print("ld t0, [guard]\n\t");
1377 st->print("membar LoadLoad\n\t");
1378 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1379 st->print("beq t0, t1, skip\n\t");
1380 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1381 st->print("j skip\n\t");
1382 st->print("guard: int\n\t");
1383 st->print("skip:\n\t");
1384 }
1385 }
1386 #endif
1387
1388 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1389 assert_cond(ra_ != nullptr);
1390 Compile* C = ra_->C;
1391
1392 __ verified_entry(C, 0);
1393
1394 if (VerifyStackAtCalls) {
1395 // n.b. frame size includes space for return pc and fp
1396 const long framesize = C->output()->frame_size_in_bytes();
1397 __ mv(t2, MAJIK_DWORD);
1398 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1399 }
1400
1401 if (C->stub_function() == nullptr) {
1402 __ entry_barrier();
1403 }
1404
1405 if (!Compile::current()->output()->in_scratch_emit_size()) {
1406 __ bind(*_verified_entry);
1407 }
1408
1409 C->output()->set_frame_complete(__ offset());
1410
1411 if (C->has_mach_constant_base_node()) {
1412 // NOTE: We set the table base offset here because users might be
1413 // emitted before MachConstantBaseNode.
1414 ConstantTable& constant_table = C->output()->constant_table();
1415 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1416 }
1417 }
1418
1419 int MachPrologNode::reloc() const
1420 {
1421 return 0;
1422 }
1423
1424 //=============================================================================
1425
1426 #ifndef PRODUCT
1427 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1428 assert_cond(st != nullptr && ra_ != nullptr);
1429 Compile* C = ra_->C;
1430 assert_cond(C != nullptr);
1431 int framesize = C->output()->frame_size_in_bytes();
1432
1433 st->print("# pop frame %d\n\t", framesize);
1434
1435 if (framesize == 0) {
1436 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1437 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1438 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1439 } else {
1440 st->print("add sp, sp, #%d\n\t", framesize);
1441 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1442 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1443 }
1444
1445 if (do_polling() && C->is_method_compilation()) {
1446 st->print("# test polling word\n\t");
1447 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1448 st->print("bgtu sp, t0, #slow_path");
1449 }
1450 }
1451 #endif
1452
1453 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1454 assert_cond(ra_ != nullptr);
1455 Compile* C = ra_->C;
1456 assert_cond(C != nullptr);
1457 int framesize = C->output()->frame_size_in_bytes();
1458
1459 __ remove_frame(framesize);
1460
1461 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1462 __ reserved_stack_check();
1463 }
1464
1465 if (do_polling() && C->is_method_compilation()) {
1466 Label dummy_label;
1467 Label* code_stub = &dummy_label;
1468 if (!C->output()->in_scratch_emit_size()) {
1469 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1470 C->output()->add_stub(stub);
1471 code_stub = &stub->entry();
1472 }
1473 __ relocate(relocInfo::poll_return_type);
1474 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1475 }
1476 }
1477
1478 int MachEpilogNode::reloc() const {
1479 // Return number of relocatable values contained in this instruction.
1480 return 1; // 1 for polling page.
1481 }
1482 const Pipeline * MachEpilogNode::pipeline() const {
1483 return MachNode::pipeline_class();
1484 }
1485
1486 //=============================================================================
1487
1488 // Figure out which register class each belongs in: rc_int, rc_float or
1489 // rc_stack.
1490 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1491
1492 static enum RC rc_class(OptoReg::Name reg) {
1493
1494 if (reg == OptoReg::Bad) {
1495 return rc_bad;
1496 }
1497
1498 // we have 30 int registers * 2 halves
1499 // (t0 and t1 are omitted)
1500 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1501 if (reg < slots_of_int_registers) {
1502 return rc_int;
1503 }
1504
1505 // we have 32 float register * 2 halves
1506 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1507 if (reg < slots_of_int_registers + slots_of_float_registers) {
1508 return rc_float;
1509 }
1510
1511 // we have 32 vector register * 4 halves
1512 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1513 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1514 return rc_vector;
1515 }
1516
1517 // Between vector regs & stack is the flags regs.
1518 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1519
1520 return rc_stack;
1521 }
1522
1523 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1524 assert_cond(ra_ != nullptr);
1525 Compile* C = ra_->C;
1526
1527 // Get registers to move.
1528 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1529 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1530 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1531 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1532
1533 enum RC src_hi_rc = rc_class(src_hi);
1534 enum RC src_lo_rc = rc_class(src_lo);
1535 enum RC dst_hi_rc = rc_class(dst_hi);
1536 enum RC dst_lo_rc = rc_class(dst_lo);
1537
1538 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1539
1540 if (src_hi != OptoReg::Bad && !bottom_type()->isa_pvectmask()) {
1541 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1542 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1543 "expected aligned-adjacent pairs");
1544 }
1545
1546 if (src_lo == dst_lo && src_hi == dst_hi) {
1547 return 0; // Self copy, no move.
1548 }
1549
1550 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1551 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1552 int src_offset = ra_->reg2offset(src_lo);
1553 int dst_offset = ra_->reg2offset(dst_lo);
1554
1555 if (bottom_type()->isa_vect() != nullptr) {
1556 uint ireg = ideal_reg();
1557 if (ireg == Op_VecA && masm) {
1558 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1559 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1560 // stack to stack
1561 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1562 vector_reg_size_in_bytes);
1563 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1564 // vpr to stack
1565 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1566 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1567 // stack to vpr
1568 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1569 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1570 // vpr to vpr
1571 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1572 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1573 } else {
1574 ShouldNotReachHere();
1575 }
1576 } else if (bottom_type()->isa_pvectmask() && masm) {
1577 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1578 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1579 // stack to stack
1580 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1581 vmask_size_in_bytes);
1582 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1583 // vmask to stack
1584 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1585 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1586 // stack to vmask
1587 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1588 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1589 // vmask to vmask
1590 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1591 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1592 } else {
1593 ShouldNotReachHere();
1594 }
1595 }
1596 } else if (masm != nullptr) {
1597 switch (src_lo_rc) {
1598 case rc_int:
1599 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1600 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1601 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1602 } else {
1603 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1604 }
1605 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1606 if (is64) {
1607 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1608 as_Register(Matcher::_regEncode[src_lo]));
1609 } else {
1610 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1611 as_Register(Matcher::_regEncode[src_lo]));
1612 }
1613 } else { // gpr --> stack spill
1614 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1615 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1616 }
1617 break;
1618 case rc_float:
1619 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1620 if (is64) {
1621 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1622 as_FloatRegister(Matcher::_regEncode[src_lo]));
1623 } else {
1624 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1625 as_FloatRegister(Matcher::_regEncode[src_lo]));
1626 }
1627 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1628 if (is64) {
1629 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1630 as_FloatRegister(Matcher::_regEncode[src_lo]));
1631 } else {
1632 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1633 as_FloatRegister(Matcher::_regEncode[src_lo]));
1634 }
1635 } else { // fpr --> stack spill
1636 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1637 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1638 is64, dst_offset);
1639 }
1640 break;
1641 case rc_stack:
1642 if (dst_lo_rc == rc_int) { // stack --> gpr load
1643 if (this->ideal_reg() == Op_RegI) {
1644 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1645 } else { // // zero extended for narrow oop or klass
1646 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1647 }
1648 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1649 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1650 is64, src_offset);
1651 } else { // stack --> stack copy
1652 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1653 if (this->ideal_reg() == Op_RegI) {
1654 __ unspill(t0, is64, src_offset);
1655 } else { // zero extended for narrow oop or klass
1656 __ unspillu(t0, is64, src_offset);
1657 }
1658 __ spill(t0, is64, dst_offset);
1659 }
1660 break;
1661 default:
1662 ShouldNotReachHere();
1663 }
1664 }
1665
1666 if (st != nullptr) {
1667 st->print("spill ");
1668 if (src_lo_rc == rc_stack) {
1669 st->print("[sp, #%d] -> ", src_offset);
1670 } else {
1671 st->print("%s -> ", Matcher::regName[src_lo]);
1672 }
1673 if (dst_lo_rc == rc_stack) {
1674 st->print("[sp, #%d]", dst_offset);
1675 } else {
1676 st->print("%s", Matcher::regName[dst_lo]);
1677 }
1678 if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
1679 int vsize = 0;
1680 if (ideal_reg() == Op_VecA) {
1681 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1682 } else {
1683 ShouldNotReachHere();
1684 }
1685 st->print("\t# vector spill size = %d", vsize);
1686 } else if (ideal_reg() == Op_RegVectMask) {
1687 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1688 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1689 st->print("\t# vmask spill size = %d", vsize);
1690 } else {
1691 st->print("\t# spill size = %d", is64 ? 64 : 32);
1692 }
1693 }
1694
1695 return 0;
1696 }
1697
1698 #ifndef PRODUCT
1699 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1700 if (ra_ == nullptr) {
1701 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1702 } else {
1703 implementation(nullptr, ra_, false, st);
1704 }
1705 }
1706 #endif
1707
1708 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1709 implementation(masm, ra_, false, nullptr);
1710 }
1711
1712 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1713 return MachNode::size(ra_);
1714 }
1715
1716 //=============================================================================
1717
1718 #ifndef PRODUCT
1719 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1720 assert_cond(ra_ != nullptr && st != nullptr);
1721 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1722 int reg = ra_->get_reg_first(this);
1723 st->print("add %s, sp, #%d\t# box lock",
1724 Matcher::regName[reg], offset);
1725 }
1726 #endif
1727
1728 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1729 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1730
1731 assert_cond(ra_ != nullptr);
1732 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1733 int reg = ra_->get_encode(this);
1734
1735 if (Assembler::is_simm12(offset)) {
1736 __ addi(as_Register(reg), sp, offset);
1737 } else {
1738 __ li32(t0, offset);
1739 __ add(as_Register(reg), sp, t0);
1740 }
1741 }
1742
1743 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1744 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1745 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1746
1747 if (Assembler::is_simm12(offset)) {
1748 return NativeInstruction::instruction_size;
1749 } else {
1750 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1751 }
1752 }
1753
1754 //=============================================================================
1755
1756 #ifndef PRODUCT
1757 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1758 {
1759 Unimplemented();
1760 }
1761 #endif
1762
1763 void MachVEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc* ra_) const
1764 {
1765 Unimplemented();
1766 }
1767
1768 //=============================================================================
1769
1770 #ifndef PRODUCT
1771 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1772 {
1773 assert_cond(st != nullptr);
1774 st->print_cr("# MachUEPNode");
1775 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1776 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1777 st->print_cr("\tbeq t1, t2, ic_hit");
1778 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1779 st->print_cr("\tic_hit:");
1780 }
1781 #endif
1782
1783 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1784 {
1785 // This is the unverified entry point.
1786 __ ic_check(CodeEntryAlignment);
1787
1788 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1789 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1790 }
1791
1792 // REQUIRED EMIT CODE
1793
1794 //=============================================================================
1795
1796 // Emit deopt handler code.
1797 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1798 {
1799 address base = __ start_a_stub(size_deopt_handler());
1800 if (base == nullptr) {
1801 ciEnv::current()->record_failure("CodeCache is full");
1802 return 0; // CodeBuffer::expand failed
1803 }
1804 int offset = __ offset();
1805
1806 Label start;
1807 __ bind(start);
1808
1809 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1810
1811 int entry_offset = __ offset();
1812 __ j(start);
1813
1814 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1815 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1816 "out of bounds read in post-call NOP check");
1817 __ end_a_stub();
1818 return entry_offset;
1819
1820 }
1821 // REQUIRED MATCHER CODE
1822
1823 //=============================================================================
1824
1825 bool Matcher::match_rule_supported(int opcode) {
1826 if (!has_match_rule(opcode)) {
1827 return false;
1828 }
1829
1830 switch (opcode) {
1831 case Op_OnSpinWait:
1832 return VM_Version::supports_on_spin_wait();
1833 case Op_CacheWB: // fall through
1834 case Op_CacheWBPreSync: // fall through
1835 case Op_CacheWBPostSync:
1836 if (!VM_Version::supports_data_cache_line_flush()) {
1837 return false;
1838 }
1839 break;
1840
1841 case Op_StrCompressedCopy: // fall through
1842 case Op_StrInflatedCopy: // fall through
1843 case Op_CountPositives: // fall through
1844 case Op_EncodeISOArray:
1845 return UseRVV;
1846
1847 case Op_PopCountI:
1848 case Op_PopCountL:
1849 return UsePopCountInstruction;
1850
1851 case Op_ReverseI:
1852 case Op_ReverseL:
1853 return UseZbkb;
1854
1855 case Op_ReverseBytesI:
1856 case Op_ReverseBytesL:
1857 case Op_ReverseBytesS:
1858 case Op_ReverseBytesUS:
1859 case Op_RotateRight:
1860 case Op_RotateLeft:
1861 case Op_CountLeadingZerosI:
1862 case Op_CountLeadingZerosL:
1863 case Op_CountTrailingZerosI:
1864 case Op_CountTrailingZerosL:
1865 return UseZbb;
1866
1867 case Op_FmaF:
1868 case Op_FmaD:
1869 return UseFMA;
1870
1871 case Op_ConvHF2F:
1872 case Op_ConvF2HF:
1873 return VM_Version::supports_float16_float_conversion();
1874 case Op_ReinterpretS2HF:
1875 case Op_ReinterpretHF2S:
1876 return UseZfh || UseZfhmin;
1877 case Op_AddHF:
1878 case Op_DivHF:
1879 case Op_FmaHF:
1880 case Op_MaxHF:
1881 case Op_MinHF:
1882 case Op_MulHF:
1883 case Op_SqrtHF:
1884 case Op_SubHF:
1885 return UseZfh;
1886
1887 case Op_CMoveP:
1888 case Op_CMoveN:
1889 return false;
1890 }
1891
1892 return true; // Per default match rules are supported.
1893 }
1894
1895 const RegMask* Matcher::predicate_reg_mask(void) {
1896 return &_VMASK_REG_mask;
1897 }
1898
1899 // Vector calling convention not yet implemented.
1900 bool Matcher::supports_vector_calling_convention(void) {
1901 return EnableVectorSupport;
1902 }
1903
1904 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1905 assert(EnableVectorSupport, "sanity");
1906 assert(ideal_reg == Op_VecA, "sanity");
1907 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1908 int lo = V8_num;
1909 int hi = V8_K_num;
1910 return OptoRegPair(hi, lo);
1911 }
1912
1913 // Is this branch offset short enough that a short branch can be used?
1914 //
1915 // NOTE: If the platform does not provide any short branch variants, then
1916 // this method should return false for offset 0.
1917 // |---label(L1)-----|
1918 // |-----------------|
1919 // |-----------------|----------eq: float-------------------
1920 // |-----------------| // far_cmpD_branch | cmpD_branch
1921 // |------- ---------| feq; | feq;
1922 // |-far_cmpD_branch-| beqz done; | bnez L;
1923 // |-----------------| j L; |
1924 // |-----------------| bind(done); |
1925 // |-----------------|--------------------------------------
1926 // |-----------------| // so shortBrSize = br_size - 4;
1927 // |-----------------| // so offs = offset - shortBrSize + 4;
1928 // |---label(L2)-----|
1929 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1930 // The passed offset is relative to address of the branch.
1931 int shortBrSize = br_size - 4;
1932 int offs = offset - shortBrSize + 4;
1933 return (-4096 <= offs && offs < 4096);
1934 }
1935
1936 // Vector width in bytes.
1937 int Matcher::vector_width_in_bytes(BasicType bt) {
1938 if (UseRVV) {
1939 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1940 // MaxVectorSize == VM_Version::_initial_vector_length
1941 int size = MaxVectorSize;
1942 // Minimum 2 values in vector
1943 if (size < 2 * type2aelembytes(bt)) size = 0;
1944 // But never < 4
1945 if (size < 4) size = 0;
1946 return size;
1947 }
1948 return 0;
1949 }
1950
1951 // Limits on vector size (number of elements) loaded into vector.
1952 int Matcher::max_vector_size(const BasicType bt) {
1953 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1954 }
1955
1956 int Matcher::min_vector_size(const BasicType bt) {
1957 int size;
1958 switch(bt) {
1959 case T_BOOLEAN:
1960 // Load/store a vector mask with only 2 elements for vector types
1961 // such as "2I/2F/2L/2D".
1962 size = 2;
1963 break;
1964 case T_BYTE:
1965 // Generate a "4B" vector, to support vector cast between "8B/16B"
1966 // and "4S/4I/4L/4F/4D".
1967 size = 4;
1968 break;
1969 case T_SHORT:
1970 // Generate a "2S" vector, to support vector cast between "4S/8S"
1971 // and "2I/2L/2F/2D".
1972 size = 2;
1973 break;
1974 default:
1975 // Limit the min vector length to 64-bit.
1976 size = 8 / type2aelembytes(bt);
1977 // The number of elements in a vector should be at least 2.
1978 size = MAX2(size, 2);
1979 }
1980
1981 int max_size = max_vector_size(bt);
1982 return MIN2(size, max_size);
1983 }
1984
1985 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
1986 return Matcher::max_vector_size(bt);
1987 }
1988
1989 // Vector ideal reg.
1990 uint Matcher::vector_ideal_reg(int len) {
1991 assert(MaxVectorSize >= len, "");
1992 if (UseRVV) {
1993 return Op_VecA;
1994 }
1995
1996 ShouldNotReachHere();
1997 return 0;
1998 }
1999
2000 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2001 return Matcher::max_vector_size(bt);
2002 }
2003
2004 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2005 ShouldNotReachHere(); // generic vector operands not supported
2006 return nullptr;
2007 }
2008
2009 bool Matcher::is_reg2reg_move(MachNode* m) {
2010 ShouldNotReachHere(); // generic vector operands not supported
2011 return false;
2012 }
2013
2014 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2015 return false;
2016 }
2017
2018 bool Matcher::is_generic_vector(MachOper* opnd) {
2019 ShouldNotReachHere(); // generic vector operands not supported
2020 return false;
2021 }
2022
2023 #ifdef ASSERT
2024 // Return whether or not this register is ever used as an argument.
2025 bool Matcher::can_be_java_arg(int reg)
2026 {
2027 return
2028 reg == R10_num || reg == R10_H_num ||
2029 reg == R11_num || reg == R11_H_num ||
2030 reg == R12_num || reg == R12_H_num ||
2031 reg == R13_num || reg == R13_H_num ||
2032 reg == R14_num || reg == R14_H_num ||
2033 reg == R15_num || reg == R15_H_num ||
2034 reg == R16_num || reg == R16_H_num ||
2035 reg == R17_num || reg == R17_H_num ||
2036 reg == F10_num || reg == F10_H_num ||
2037 reg == F11_num || reg == F11_H_num ||
2038 reg == F12_num || reg == F12_H_num ||
2039 reg == F13_num || reg == F13_H_num ||
2040 reg == F14_num || reg == F14_H_num ||
2041 reg == F15_num || reg == F15_H_num ||
2042 reg == F16_num || reg == F16_H_num ||
2043 reg == F17_num || reg == F17_H_num;
2044 }
2045 #endif
2046
2047 uint Matcher::int_pressure_limit()
2048 {
2049 // A derived pointer is live at CallNode and then is flagged by RA
2050 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2051 // derived pointers and lastly fail to spill after reaching maximum
2052 // number of iterations. Lowering the default pressure threshold to
2053 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2054 // a high register pressure area of the code so that split_DEF can
2055 // generate DefinitionSpillCopy for the derived pointer.
2056 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2057 if (!PreserveFramePointer) {
2058 // When PreserveFramePointer is off, frame pointer is allocatable,
2059 // but different from other SOC registers, it is excluded from
2060 // fatproj's mask because its save type is No-Save. Decrease 1 to
2061 // ensure high pressure at fatproj when PreserveFramePointer is off.
2062 // See check_pressure_at_fatproj().
2063 default_int_pressure_threshold--;
2064 }
2065 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2066 }
2067
2068 uint Matcher::float_pressure_limit()
2069 {
2070 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2071 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2072 }
2073
2074 const RegMask& Matcher::divI_proj_mask() {
2075 ShouldNotReachHere();
2076 return RegMask::EMPTY;
2077 }
2078
2079 // Register for MODI projection of divmodI.
2080 const RegMask& Matcher::modI_proj_mask() {
2081 ShouldNotReachHere();
2082 return RegMask::EMPTY;
2083 }
2084
2085 // Register for DIVL projection of divmodL.
2086 const RegMask& Matcher::divL_proj_mask() {
2087 ShouldNotReachHere();
2088 return RegMask::EMPTY;
2089 }
2090
2091 // Register for MODL projection of divmodL.
2092 const RegMask& Matcher::modL_proj_mask() {
2093 ShouldNotReachHere();
2094 return RegMask::EMPTY;
2095 }
2096
2097 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2098 assert_cond(addp != nullptr);
2099 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2100 Node* u = addp->fast_out(i);
2101 if (u != nullptr && u->is_Mem()) {
2102 int opsize = u->as_Mem()->memory_size();
2103 assert(opsize > 0, "unexpected memory operand size");
2104 if (u->as_Mem()->memory_size() != (1 << shift)) {
2105 return false;
2106 }
2107 }
2108 }
2109 return true;
2110 }
2111
2112 // Binary src (Replicate scalar/immediate)
2113 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2114 if (n == nullptr || m == nullptr) {
2115 return false;
2116 }
2117
2118 if (m->Opcode() != Op_Replicate) {
2119 return false;
2120 }
2121
2122 switch (n->Opcode()) {
2123 case Op_AndV:
2124 case Op_OrV:
2125 case Op_XorV:
2126 case Op_AddVB:
2127 case Op_AddVS:
2128 case Op_AddVI:
2129 case Op_AddVL:
2130 case Op_SubVB:
2131 case Op_SubVS:
2132 case Op_SubVI:
2133 case Op_SubVL:
2134 case Op_MulVB:
2135 case Op_MulVS:
2136 case Op_MulVI:
2137 case Op_MulVL: {
2138 return true;
2139 }
2140 default:
2141 return false;
2142 }
2143 }
2144
2145 // (XorV src (Replicate m1))
2146 // (XorVMask src (MaskAll m1))
2147 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2148 if (n != nullptr && m != nullptr) {
2149 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2150 VectorNode::is_all_ones_vector(m);
2151 }
2152 return false;
2153 }
2154
2155 // Should the Matcher clone input 'm' of node 'n'?
2156 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2157 assert_cond(m != nullptr);
2158 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2159 is_vector_bitwise_not_pattern(n, m) ||
2160 is_vector_scalar_bitwise_pattern(n, m) ||
2161 is_encode_and_store_pattern(n, m)) {
2162 mstack.push(m, Visit);
2163 return true;
2164 }
2165 return false;
2166 }
2167
2168 // Should the Matcher clone shifts on addressing modes, expecting them
2169 // to be subsumed into complex addressing expressions or compute them
2170 // into registers?
2171 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2172 return clone_base_plus_offset_address(m, mstack, address_visited);
2173 }
2174
2175 %}
2176
2177
2178
2179 //----------ENCODING BLOCK-----------------------------------------------------
2180 // This block specifies the encoding classes used by the compiler to
2181 // output byte streams. Encoding classes are parameterized macros
2182 // used by Machine Instruction Nodes in order to generate the bit
2183 // encoding of the instruction. Operands specify their base encoding
2184 // interface with the interface keyword. There are currently
2185 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2186 // COND_INTER. REG_INTER causes an operand to generate a function
2187 // which returns its register number when queried. CONST_INTER causes
2188 // an operand to generate a function which returns the value of the
2189 // constant when queried. MEMORY_INTER causes an operand to generate
2190 // four functions which return the Base Register, the Index Register,
2191 // the Scale Value, and the Offset Value of the operand when queried.
2192 // COND_INTER causes an operand to generate six functions which return
2193 // the encoding code (ie - encoding bits for the instruction)
2194 // associated with each basic boolean condition for a conditional
2195 // instruction.
2196 //
2197 // Instructions specify two basic values for encoding. Again, a
2198 // function is available to check if the constant displacement is an
2199 // oop. They use the ins_encode keyword to specify their encoding
2200 // classes (which must be a sequence of enc_class names, and their
2201 // parameters, specified in the encoding block), and they use the
2202 // opcode keyword to specify, in order, their primary, secondary, and
2203 // tertiary opcode. Only the opcode sections which a particular
2204 // instruction needs for encoding need to be specified.
2205 encode %{
2206 // BEGIN Non-volatile memory access
2207
2208 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2209 int64_t con = (int64_t)$src$$constant;
2210 Register dst_reg = as_Register($dst$$reg);
2211 __ mv(dst_reg, con);
2212 %}
2213
2214 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2215 Register dst_reg = as_Register($dst$$reg);
2216 address con = (address)$src$$constant;
2217 if (con == nullptr || con == (address)1) {
2218 ShouldNotReachHere();
2219 } else {
2220 relocInfo::relocType rtype = $src->constant_reloc();
2221 if (rtype == relocInfo::oop_type) {
2222 __ movoop(dst_reg, (jobject)con);
2223 } else if (rtype == relocInfo::metadata_type) {
2224 __ mov_metadata(dst_reg, (Metadata*)con);
2225 } else {
2226 assert(rtype == relocInfo::none || rtype == relocInfo::external_word_type, "unexpected reloc type");
2227 __ mv(dst_reg, $src$$constant);
2228 }
2229 }
2230 %}
2231
2232 enc_class riscv_enc_mov_p1(iRegP dst) %{
2233 Register dst_reg = as_Register($dst$$reg);
2234 __ mv(dst_reg, 1);
2235 %}
2236
2237 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2238 Register dst_reg = as_Register($dst$$reg);
2239 address con = (address)$src$$constant;
2240 if (con == nullptr) {
2241 ShouldNotReachHere();
2242 } else {
2243 relocInfo::relocType rtype = $src->constant_reloc();
2244 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2245 __ set_narrow_oop(dst_reg, (jobject)con);
2246 }
2247 %}
2248
2249 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2250 Register dst_reg = as_Register($dst$$reg);
2251 __ mv(dst_reg, zr);
2252 %}
2253
2254 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2255 Register dst_reg = as_Register($dst$$reg);
2256 address con = (address)$src$$constant;
2257 if (con == nullptr) {
2258 ShouldNotReachHere();
2259 } else {
2260 relocInfo::relocType rtype = $src->constant_reloc();
2261 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2262 __ set_narrow_klass(dst_reg, (Klass *)con);
2263 }
2264 %}
2265
2266 // compare and branch instruction encodings
2267
2268 enc_class riscv_enc_j(label lbl) %{
2269 Label* L = $lbl$$label;
2270 __ j(*L);
2271 %}
2272
2273 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2274 Label* L = $lbl$$label;
2275 switch ($cmp$$cmpcode) {
2276 case(BoolTest::ge):
2277 __ j(*L);
2278 break;
2279 case(BoolTest::lt):
2280 break;
2281 default:
2282 Unimplemented();
2283 }
2284 %}
2285
2286 // call instruction encodings
2287
2288 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2289 Register sub_reg = as_Register($sub$$reg);
2290 Register super_reg = as_Register($super$$reg);
2291 Register temp_reg = as_Register($temp$$reg);
2292 Register result_reg = as_Register($result$$reg);
2293 Register cr_reg = t1;
2294
2295 Label miss;
2296 Label done;
2297 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2298 nullptr, &miss, /*set_cond_codes*/ true);
2299 if ($primary) {
2300 __ mv(result_reg, zr);
2301 } else {
2302 __ mv(cr_reg, zr);
2303 __ j(done);
2304 }
2305
2306 __ bind(miss);
2307 if (!$primary) {
2308 __ mv(cr_reg, 1);
2309 }
2310
2311 __ bind(done);
2312 %}
2313
2314 enc_class riscv_enc_java_static_call(method meth) %{
2315 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2316
2317 address addr = (address)$meth$$method;
2318 address call = nullptr;
2319 assert_cond(addr != nullptr);
2320 if (!_method) {
2321 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2322 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2323 if (call == nullptr) {
2324 ciEnv::current()->record_failure("CodeCache is full");
2325 return;
2326 }
2327 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2328 // The NOP here is purely to ensure that eliding a call to
2329 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2330 __ nop();
2331 __ nop();
2332 __ nop();
2333 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2334 } else {
2335 int method_index = resolved_method_index(masm);
2336 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2337 : static_call_Relocation::spec(method_index);
2338 call = __ reloc_call(Address(addr, rspec));
2339 if (call == nullptr) {
2340 ciEnv::current()->record_failure("CodeCache is full");
2341 return;
2342 }
2343
2344 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2345 // Calls of the same statically bound method can share
2346 // a stub to the interpreter.
2347 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2348 } else {
2349 // Emit stub for static call
2350 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2351 if (stub == nullptr) {
2352 ciEnv::current()->record_failure("CodeCache is full");
2353 return;
2354 }
2355 }
2356 }
2357
2358 __ post_call_nop();
2359 %}
2360
2361 enc_class riscv_enc_java_dynamic_call(method meth) %{
2362 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2363 int method_index = resolved_method_index(masm);
2364 address call = __ ic_call((address)$meth$$method, method_index);
2365 if (call == nullptr) {
2366 ciEnv::current()->record_failure("CodeCache is full");
2367 return;
2368 }
2369
2370 __ post_call_nop();
2371 %}
2372
2373 enc_class riscv_enc_call_epilog() %{
2374 if (VerifyStackAtCalls) {
2375 // Check that stack depth is unchanged: find majik cookie on stack
2376 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2377 Label stack_ok;
2378 __ ld(t1, Address(sp, framesize));
2379 __ mv(t2, MAJIK_DWORD);
2380 __ beq(t2, t1, stack_ok);
2381 __ stop("MAJIK_DWORD not found");
2382 __ bind(stack_ok);
2383 }
2384 %}
2385
2386 enc_class riscv_enc_java_to_runtime(method meth) %{
2387 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2388
2389 // Some calls to generated routines (arraycopy code) are scheduled by C2
2390 // as runtime calls. if so we can call them using a far call (they will be
2391 // in the code cache, thus in a reachable segment) otherwise we have to use
2392 // a movptr+jalr pair which loads the absolute address into a register.
2393 address entry = (address)$meth$$method;
2394 if (CodeCache::contains(entry)) {
2395 __ far_call(Address(entry, relocInfo::runtime_call_type));
2396 __ post_call_nop();
2397 } else {
2398 Label retaddr;
2399 // Make the anchor frame walkable
2400 __ la(t0, retaddr);
2401 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2402 int32_t offset = 0;
2403 // No relocation needed
2404 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2405 __ jalr(t1, offset);
2406 __ bind(retaddr);
2407 __ post_call_nop();
2408 }
2409 %}
2410
2411 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2412 Register target_reg = as_Register($jump_target$$reg);
2413 __ jr(target_reg);
2414 %}
2415
2416 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2417 Register target_reg = as_Register($jump_target$$reg);
2418 // exception oop should be in x10
2419 // ret addr has been popped into ra
2420 // callee expects it in x13
2421 __ mv(x13, ra);
2422 __ jr(target_reg);
2423 %}
2424
2425 enc_class riscv_enc_rethrow() %{
2426 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2427 %}
2428
2429 enc_class riscv_enc_ret() %{
2430 __ ret();
2431 %}
2432
2433 %}
2434
2435 //----------FRAME--------------------------------------------------------------
2436 // Definition of frame structure and management information.
2437 //
2438 // S T A C K L A Y O U T Allocators stack-slot number
2439 // | (to get allocators register number
2440 // G Owned by | | v add OptoReg::stack0())
2441 // r CALLER | |
2442 // o | +--------+ pad to even-align allocators stack-slot
2443 // w V | pad0 | numbers; owned by CALLER
2444 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2445 // h ^ | in | 5
2446 // | | args | 4 Holes in incoming args owned by SELF
2447 // | | | | 3
2448 // | | +--------+
2449 // V | | old out| Empty on Intel, window on Sparc
2450 // | old |preserve| Must be even aligned.
2451 // | SP-+--------+----> Matcher::_old_SP, even aligned
2452 // | | in | 3 area for Intel ret address
2453 // Owned by |preserve| Empty on Sparc.
2454 // SELF +--------+
2455 // | | pad2 | 2 pad to align old SP
2456 // | +--------+ 1
2457 // | | locks | 0
2458 // | +--------+----> OptoReg::stack0(), even aligned
2459 // | | pad1 | 11 pad to align new SP
2460 // | +--------+
2461 // | | | 10
2462 // | | spills | 9 spills
2463 // V | | 8 (pad0 slot for callee)
2464 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2465 // ^ | out | 7
2466 // | | args | 6 Holes in outgoing args owned by CALLEE
2467 // Owned by +--------+
2468 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2469 // | new |preserve| Must be even-aligned.
2470 // | SP-+--------+----> Matcher::_new_SP, even aligned
2471 // | | |
2472 //
2473 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2474 // known from SELF's arguments and the Java calling convention.
2475 // Region 6-7 is determined per call site.
2476 // Note 2: If the calling convention leaves holes in the incoming argument
2477 // area, those holes are owned by SELF. Holes in the outgoing area
2478 // are owned by the CALLEE. Holes should not be necessary in the
2479 // incoming area, as the Java calling convention is completely under
2480 // the control of the AD file. Doubles can be sorted and packed to
2481 // avoid holes. Holes in the outgoing arguments may be necessary for
2482 // varargs C calling conventions.
2483 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2484 // even aligned with pad0 as needed.
2485 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2486 // (the latter is true on Intel but is it false on RISCV?)
2487 // region 6-11 is even aligned; it may be padded out more so that
2488 // the region from SP to FP meets the minimum stack alignment.
2489 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2490 // alignment. Region 11, pad1, may be dynamically extended so that
2491 // SP meets the minimum alignment.
2492
2493 frame %{
2494 // These three registers define part of the calling convention
2495 // between compiled code and the interpreter.
2496
2497 // Inline Cache Register or methodOop for I2C.
2498 inline_cache_reg(R31);
2499
2500 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2501 cisc_spilling_operand_name(indOffset);
2502
2503 // Number of stack slots consumed by locking an object
2504 // generate Compile::sync_stack_slots
2505 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2506 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2507
2508 // Compiled code's Frame Pointer
2509 frame_pointer(R2);
2510
2511 // Stack alignment requirement
2512 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2513
2514 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2515 // for calls to C. Supports the var-args backing area for register parms.
2516 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2517
2518 // The after-PROLOG location of the return address. Location of
2519 // return address specifies a type (REG or STACK) and a number
2520 // representing the register number (i.e. - use a register name) or
2521 // stack slot.
2522 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2523 // Otherwise, it is above the locks and verification slot and alignment word
2524 // TODO this may well be correct but need to check why that - 2 is there
2525 // ppc port uses 0 but we definitely need to allow for fixed_slots
2526 // which folds in the space used for monitors
2527 return_addr(STACK - 2 +
2528 align_up((Compile::current()->in_preserve_stack_slots() +
2529 Compile::current()->fixed_slots()),
2530 stack_alignment_in_slots()));
2531
2532 // Location of compiled Java return values. Same as C for now.
2533 return_value
2534 %{
2535 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2536 "only return normal values");
2537
2538 static const int lo[Op_RegL + 1] = { // enum name
2539 0, // Op_Node
2540 0, // Op_Set
2541 R10_num, // Op_RegN
2542 R10_num, // Op_RegI
2543 R10_num, // Op_RegP
2544 F10_num, // Op_RegF
2545 F10_num, // Op_RegD
2546 R10_num // Op_RegL
2547 };
2548
2549 static const int hi[Op_RegL + 1] = { // enum name
2550 0, // Op_Node
2551 0, // Op_Set
2552 OptoReg::Bad, // Op_RegN
2553 OptoReg::Bad, // Op_RegI
2554 R10_H_num, // Op_RegP
2555 OptoReg::Bad, // Op_RegF
2556 F10_H_num, // Op_RegD
2557 R10_H_num // Op_RegL
2558 };
2559
2560 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2561 %}
2562 %}
2563
2564 //----------ATTRIBUTES---------------------------------------------------------
2565 //----------Operand Attributes-------------------------------------------------
2566 op_attrib op_cost(1); // Required cost attribute
2567
2568 //----------Instruction Attributes---------------------------------------------
2569 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2570 ins_attrib ins_size(32); // Required size attribute (in bits)
2571 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2572 // a non-matching short branch variant
2573 // of some long branch?
2574 ins_attrib ins_alignment(4); // Required alignment attribute (must
2575 // be a power of 2) specifies the
2576 // alignment that some part of the
2577 // instruction (not necessarily the
2578 // start) requires. If > 1, a
2579 // compute_padding() function must be
2580 // provided for the instruction
2581
2582 // Whether this node is expanded during code emission into a sequence of
2583 // instructions and the first instruction can perform an implicit null check.
2584 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2585
2586 //----------OPERANDS-----------------------------------------------------------
2587 // Operand definitions must precede instruction definitions for correct parsing
2588 // in the ADLC because operands constitute user defined types which are used in
2589 // instruction definitions.
2590
2591 //----------Simple Operands----------------------------------------------------
2592
2593 // Integer operands 32 bit
2594 // 32 bit immediate
2595 operand immI()
2596 %{
2597 match(ConI);
2598
2599 op_cost(0);
2600 format %{ %}
2601 interface(CONST_INTER);
2602 %}
2603
2604 // 32 bit zero
2605 operand immI0()
2606 %{
2607 predicate(n->get_int() == 0);
2608 match(ConI);
2609
2610 op_cost(0);
2611 format %{ %}
2612 interface(CONST_INTER);
2613 %}
2614
2615 // 32 bit unit increment
2616 operand immI_1()
2617 %{
2618 predicate(n->get_int() == 1);
2619 match(ConI);
2620
2621 op_cost(0);
2622 format %{ %}
2623 interface(CONST_INTER);
2624 %}
2625
2626 // 32 bit unit decrement
2627 operand immI_M1()
2628 %{
2629 predicate(n->get_int() == -1);
2630 match(ConI);
2631
2632 op_cost(0);
2633 format %{ %}
2634 interface(CONST_INTER);
2635 %}
2636
2637 // Unsigned Integer Immediate: 6-bit int, greater than 32
2638 operand uimmI6_ge32() %{
2639 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2640 match(ConI);
2641 op_cost(0);
2642 format %{ %}
2643 interface(CONST_INTER);
2644 %}
2645
2646 operand immI_le_4()
2647 %{
2648 predicate(n->get_int() <= 4);
2649 match(ConI);
2650
2651 op_cost(0);
2652 format %{ %}
2653 interface(CONST_INTER);
2654 %}
2655
2656 operand immI_4()
2657 %{
2658 predicate(n->get_int() == 4);
2659 match(ConI);
2660
2661 op_cost(0);
2662 format %{ %}
2663 interface(CONST_INTER);
2664 %}
2665
2666 operand immI_16()
2667 %{
2668 predicate(n->get_int() == 16);
2669 match(ConI);
2670 op_cost(0);
2671 format %{ %}
2672 interface(CONST_INTER);
2673 %}
2674
2675 operand immI_24()
2676 %{
2677 predicate(n->get_int() == 24);
2678 match(ConI);
2679 op_cost(0);
2680 format %{ %}
2681 interface(CONST_INTER);
2682 %}
2683
2684 operand immI_31()
2685 %{
2686 predicate(n->get_int() == 31);
2687 match(ConI);
2688
2689 op_cost(0);
2690 format %{ %}
2691 interface(CONST_INTER);
2692 %}
2693
2694 operand immI_63()
2695 %{
2696 predicate(n->get_int() == 63);
2697 match(ConI);
2698
2699 op_cost(0);
2700 format %{ %}
2701 interface(CONST_INTER);
2702 %}
2703
2704 // 32 bit integer valid for add immediate
2705 operand immIAdd()
2706 %{
2707 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2708 match(ConI);
2709 op_cost(0);
2710 format %{ %}
2711 interface(CONST_INTER);
2712 %}
2713
2714 // 32 bit integer valid for sub immediate
2715 operand immISub()
2716 %{
2717 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2718 match(ConI);
2719 op_cost(0);
2720 format %{ %}
2721 interface(CONST_INTER);
2722 %}
2723
2724 // 5 bit signed value.
2725 operand immI5()
2726 %{
2727 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2728 match(ConI);
2729
2730 op_cost(0);
2731 format %{ %}
2732 interface(CONST_INTER);
2733 %}
2734
2735 // 5 bit signed value (simm5)
2736 operand immL5()
2737 %{
2738 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2739 match(ConL);
2740
2741 op_cost(0);
2742 format %{ %}
2743 interface(CONST_INTER);
2744 %}
2745
2746 // Integer operands 64 bit
2747 // 64 bit immediate
2748 operand immL()
2749 %{
2750 match(ConL);
2751
2752 op_cost(0);
2753 format %{ %}
2754 interface(CONST_INTER);
2755 %}
2756
2757 // 64 bit zero
2758 operand immL0()
2759 %{
2760 predicate(n->get_long() == 0);
2761 match(ConL);
2762
2763 op_cost(0);
2764 format %{ %}
2765 interface(CONST_INTER);
2766 %}
2767
2768 // Pointer operands
2769 // Pointer Immediate
2770 operand immP()
2771 %{
2772 match(ConP);
2773
2774 op_cost(0);
2775 format %{ %}
2776 interface(CONST_INTER);
2777 %}
2778
2779 // Null Pointer Immediate
2780 operand immP0()
2781 %{
2782 predicate(n->get_ptr() == 0);
2783 match(ConP);
2784
2785 op_cost(0);
2786 format %{ %}
2787 interface(CONST_INTER);
2788 %}
2789
2790 // Pointer Immediate One
2791 // this is used in object initialization (initial object header)
2792 operand immP_1()
2793 %{
2794 predicate(n->get_ptr() == 1);
2795 match(ConP);
2796
2797 op_cost(0);
2798 format %{ %}
2799 interface(CONST_INTER);
2800 %}
2801
2802 // Int Immediate: low 16-bit mask
2803 operand immI_16bits()
2804 %{
2805 predicate(n->get_int() == 0xFFFF);
2806 match(ConI);
2807 op_cost(0);
2808 format %{ %}
2809 interface(CONST_INTER);
2810 %}
2811
2812 operand immIpowerOf2() %{
2813 predicate(is_power_of_2((juint)(n->get_int())));
2814 match(ConI);
2815 op_cost(0);
2816 format %{ %}
2817 interface(CONST_INTER);
2818 %}
2819
2820 // Long Immediate: low 32-bit mask
2821 operand immL_32bits()
2822 %{
2823 predicate(n->get_long() == 0xFFFFFFFFL);
2824 match(ConL);
2825 op_cost(0);
2826 format %{ %}
2827 interface(CONST_INTER);
2828 %}
2829
2830 // 64 bit unit decrement
2831 operand immL_M1()
2832 %{
2833 predicate(n->get_long() == -1);
2834 match(ConL);
2835
2836 op_cost(0);
2837 format %{ %}
2838 interface(CONST_INTER);
2839 %}
2840
2841
2842 // 64 bit integer valid for add immediate
2843 operand immLAdd()
2844 %{
2845 predicate(Assembler::is_simm12(n->get_long()));
2846 match(ConL);
2847 op_cost(0);
2848 format %{ %}
2849 interface(CONST_INTER);
2850 %}
2851
2852 // 64 bit integer valid for sub immediate
2853 operand immLSub()
2854 %{
2855 predicate(Assembler::is_simm12(-(n->get_long())));
2856 match(ConL);
2857 op_cost(0);
2858 format %{ %}
2859 interface(CONST_INTER);
2860 %}
2861
2862 // Narrow pointer operands
2863 // Narrow Pointer Immediate
2864 operand immN()
2865 %{
2866 match(ConN);
2867
2868 op_cost(0);
2869 format %{ %}
2870 interface(CONST_INTER);
2871 %}
2872
2873 // Narrow Null Pointer Immediate
2874 operand immN0()
2875 %{
2876 predicate(n->get_narrowcon() == 0);
2877 match(ConN);
2878
2879 op_cost(0);
2880 format %{ %}
2881 interface(CONST_INTER);
2882 %}
2883
2884 operand immNKlass()
2885 %{
2886 match(ConNKlass);
2887
2888 op_cost(0);
2889 format %{ %}
2890 interface(CONST_INTER);
2891 %}
2892
2893 // Float and Double operands
2894 // Double Immediate
2895 operand immD()
2896 %{
2897 match(ConD);
2898 op_cost(0);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // Double Immediate: +0.0d
2904 operand immD0()
2905 %{
2906 predicate(jlong_cast(n->getd()) == 0);
2907 match(ConD);
2908
2909 op_cost(0);
2910 format %{ %}
2911 interface(CONST_INTER);
2912 %}
2913
2914 // Float Immediate
2915 operand immF()
2916 %{
2917 match(ConF);
2918 op_cost(0);
2919 format %{ %}
2920 interface(CONST_INTER);
2921 %}
2922
2923 // Float Immediate: +0.0f.
2924 operand immF0()
2925 %{
2926 predicate(jint_cast(n->getf()) == 0);
2927 match(ConF);
2928
2929 op_cost(0);
2930 format %{ %}
2931 interface(CONST_INTER);
2932 %}
2933
2934 // Half Float Immediate
2935 operand immH()
2936 %{
2937 match(ConH);
2938
2939 op_cost(0);
2940 format %{ %}
2941 interface(CONST_INTER);
2942 %}
2943
2944 // Half Float Immediate: +0.0f.
2945 operand immH0()
2946 %{
2947 predicate(jint_cast(n->geth()) == 0);
2948 match(ConH);
2949
2950 op_cost(0);
2951 format %{ %}
2952 interface(CONST_INTER);
2953 %}
2954
2955 operand immIOffset()
2956 %{
2957 predicate(Assembler::is_simm12(n->get_int()));
2958 match(ConI);
2959 op_cost(0);
2960 format %{ %}
2961 interface(CONST_INTER);
2962 %}
2963
2964 operand immLOffset()
2965 %{
2966 predicate(Assembler::is_simm12(n->get_long()));
2967 match(ConL);
2968 op_cost(0);
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 // Scale values
2974 operand immIScale()
2975 %{
2976 predicate(1 <= n->get_int() && (n->get_int() <= 3));
2977 match(ConI);
2978
2979 op_cost(0);
2980 format %{ %}
2981 interface(CONST_INTER);
2982 %}
2983
2984 // Integer 32 bit Register Operands
2985 operand iRegI()
2986 %{
2987 constraint(ALLOC_IN_RC(any_reg32));
2988 match(RegI);
2989 match(iRegINoSp);
2990 op_cost(0);
2991 format %{ %}
2992 interface(REG_INTER);
2993 %}
2994
2995 // Integer 32 bit Register not Special
2996 operand iRegINoSp()
2997 %{
2998 constraint(ALLOC_IN_RC(no_special_reg32));
2999 match(RegI);
3000 op_cost(0);
3001 format %{ %}
3002 interface(REG_INTER);
3003 %}
3004
3005 // Register R10 only
3006 operand iRegI_R10()
3007 %{
3008 constraint(ALLOC_IN_RC(int_r10_reg));
3009 match(RegI);
3010 match(iRegINoSp);
3011 op_cost(0);
3012 format %{ %}
3013 interface(REG_INTER);
3014 %}
3015
3016 // Register R12 only
3017 operand iRegI_R12()
3018 %{
3019 constraint(ALLOC_IN_RC(int_r12_reg));
3020 match(RegI);
3021 match(iRegINoSp);
3022 op_cost(0);
3023 format %{ %}
3024 interface(REG_INTER);
3025 %}
3026
3027 // Register R13 only
3028 operand iRegI_R13()
3029 %{
3030 constraint(ALLOC_IN_RC(int_r13_reg));
3031 match(RegI);
3032 match(iRegINoSp);
3033 op_cost(0);
3034 format %{ %}
3035 interface(REG_INTER);
3036 %}
3037
3038 // Register R14 only
3039 operand iRegI_R14()
3040 %{
3041 constraint(ALLOC_IN_RC(int_r14_reg));
3042 match(RegI);
3043 match(iRegINoSp);
3044 op_cost(0);
3045 format %{ %}
3046 interface(REG_INTER);
3047 %}
3048
3049 // Integer 64 bit Register Operands
3050 operand iRegL()
3051 %{
3052 constraint(ALLOC_IN_RC(any_reg));
3053 match(RegL);
3054 match(iRegLNoSp);
3055 op_cost(0);
3056 format %{ %}
3057 interface(REG_INTER);
3058 %}
3059
3060 // Integer 64 bit Register not Special
3061 operand iRegLNoSp()
3062 %{
3063 constraint(ALLOC_IN_RC(no_special_reg));
3064 match(RegL);
3065 match(iRegL_R10);
3066 format %{ %}
3067 interface(REG_INTER);
3068 %}
3069
3070 // Long 64 bit Register R29 only
3071 operand iRegL_R29()
3072 %{
3073 constraint(ALLOC_IN_RC(r29_reg));
3074 match(RegL);
3075 match(iRegLNoSp);
3076 op_cost(0);
3077 format %{ %}
3078 interface(REG_INTER);
3079 %}
3080
3081 // Long 64 bit Register R30 only
3082 operand iRegL_R30()
3083 %{
3084 constraint(ALLOC_IN_RC(r30_reg));
3085 match(RegL);
3086 match(iRegLNoSp);
3087 op_cost(0);
3088 format %{ %}
3089 interface(REG_INTER);
3090 %}
3091
3092 // Pointer Register Operands
3093 // Pointer Register
3094 operand iRegP()
3095 %{
3096 constraint(ALLOC_IN_RC(ptr_reg));
3097 match(RegP);
3098 match(iRegPNoSp);
3099 match(iRegP_R10);
3100 match(iRegP_R15);
3101 match(javaThread_RegP);
3102 op_cost(0);
3103 format %{ %}
3104 interface(REG_INTER);
3105 %}
3106
3107 // Pointer 64 bit Register not Special
3108 operand iRegPNoSp()
3109 %{
3110 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3111 match(RegP);
3112 op_cost(0);
3113 format %{ %}
3114 interface(REG_INTER);
3115 %}
3116
3117 // This operand is not allowed to use fp even if
3118 // fp is not used to hold the frame pointer.
3119 operand iRegPNoSpNoFp()
3120 %{
3121 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3122 match(RegP);
3123 match(iRegPNoSp);
3124 op_cost(0);
3125 format %{ %}
3126 interface(REG_INTER);
3127 %}
3128
3129 operand iRegP_R10()
3130 %{
3131 constraint(ALLOC_IN_RC(r10_reg));
3132 match(RegP);
3133 // match(iRegP);
3134 match(iRegPNoSp);
3135 op_cost(0);
3136 format %{ %}
3137 interface(REG_INTER);
3138 %}
3139
3140 // Pointer 64 bit Register R11 only
3141 operand iRegP_R11()
3142 %{
3143 constraint(ALLOC_IN_RC(r11_reg));
3144 match(RegP);
3145 match(iRegPNoSp);
3146 op_cost(0);
3147 format %{ %}
3148 interface(REG_INTER);
3149 %}
3150
3151 operand iRegP_R12()
3152 %{
3153 constraint(ALLOC_IN_RC(r12_reg));
3154 match(RegP);
3155 // match(iRegP);
3156 match(iRegPNoSp);
3157 op_cost(0);
3158 format %{ %}
3159 interface(REG_INTER);
3160 %}
3161
3162 // Pointer 64 bit Register R13 only
3163 operand iRegP_R13()
3164 %{
3165 constraint(ALLOC_IN_RC(r13_reg));
3166 match(RegP);
3167 match(iRegPNoSp);
3168 op_cost(0);
3169 format %{ %}
3170 interface(REG_INTER);
3171 %}
3172
3173 operand iRegP_R14()
3174 %{
3175 constraint(ALLOC_IN_RC(r14_reg));
3176 match(RegP);
3177 // match(iRegP);
3178 match(iRegPNoSp);
3179 op_cost(0);
3180 format %{ %}
3181 interface(REG_INTER);
3182 %}
3183
3184 operand iRegP_R15()
3185 %{
3186 constraint(ALLOC_IN_RC(r15_reg));
3187 match(RegP);
3188 // match(iRegP);
3189 match(iRegPNoSp);
3190 op_cost(0);
3191 format %{ %}
3192 interface(REG_INTER);
3193 %}
3194
3195 operand iRegP_R16()
3196 %{
3197 constraint(ALLOC_IN_RC(r16_reg));
3198 match(RegP);
3199 match(iRegPNoSp);
3200 op_cost(0);
3201 format %{ %}
3202 interface(REG_INTER);
3203 %}
3204
3205 // Pointer 64 bit Register R28 only
3206 operand iRegP_R28()
3207 %{
3208 constraint(ALLOC_IN_RC(r28_reg));
3209 match(RegP);
3210 match(iRegPNoSp);
3211 op_cost(0);
3212 format %{ %}
3213 interface(REG_INTER);
3214 %}
3215
3216 // Pointer 64 bit Register R30 only
3217 operand iRegP_R30()
3218 %{
3219 constraint(ALLOC_IN_RC(r30_reg));
3220 match(RegP);
3221 match(iRegPNoSp);
3222 op_cost(0);
3223 format %{ %}
3224 interface(REG_INTER);
3225 %}
3226
3227 // Pointer 64 bit Register R31 only
3228 operand iRegP_R31()
3229 %{
3230 constraint(ALLOC_IN_RC(r31_reg));
3231 match(RegP);
3232 match(iRegPNoSp);
3233 op_cost(0);
3234 format %{ %}
3235 interface(REG_INTER);
3236 %}
3237
3238 // Pointer Register Operands
3239 // Narrow Pointer Register
3240 operand iRegN()
3241 %{
3242 constraint(ALLOC_IN_RC(any_reg32));
3243 match(RegN);
3244 match(iRegNNoSp);
3245 op_cost(0);
3246 format %{ %}
3247 interface(REG_INTER);
3248 %}
3249
3250 // Integer 64 bit Register not Special
3251 operand iRegNNoSp()
3252 %{
3253 constraint(ALLOC_IN_RC(no_special_reg32));
3254 match(RegN);
3255 op_cost(0);
3256 format %{ %}
3257 interface(REG_INTER);
3258 %}
3259
3260 // Long 64 bit Register R10 only
3261 operand iRegL_R10()
3262 %{
3263 constraint(ALLOC_IN_RC(r10_reg));
3264 match(RegL);
3265 match(iRegLNoSp);
3266 op_cost(0);
3267 format %{ %}
3268 interface(REG_INTER);
3269 %}
3270
3271 // Float Register
3272 // Float register operands
3273 operand fRegF()
3274 %{
3275 constraint(ALLOC_IN_RC(float_reg));
3276 match(RegF);
3277
3278 op_cost(0);
3279 format %{ %}
3280 interface(REG_INTER);
3281 %}
3282
3283 // Double Register
3284 // Double register operands
3285 operand fRegD()
3286 %{
3287 constraint(ALLOC_IN_RC(double_reg));
3288 match(RegD);
3289
3290 op_cost(0);
3291 format %{ %}
3292 interface(REG_INTER);
3293 %}
3294
3295 // Generic vector class. This will be used for
3296 // all vector operands.
3297 operand vReg()
3298 %{
3299 constraint(ALLOC_IN_RC(vectora_reg));
3300 match(VecA);
3301 op_cost(0);
3302 format %{ %}
3303 interface(REG_INTER);
3304 %}
3305
3306 operand vReg_V1()
3307 %{
3308 constraint(ALLOC_IN_RC(v1_reg));
3309 match(VecA);
3310 match(vReg);
3311 op_cost(0);
3312 format %{ %}
3313 interface(REG_INTER);
3314 %}
3315
3316 operand vReg_V2()
3317 %{
3318 constraint(ALLOC_IN_RC(v2_reg));
3319 match(VecA);
3320 match(vReg);
3321 op_cost(0);
3322 format %{ %}
3323 interface(REG_INTER);
3324 %}
3325
3326 operand vReg_V3()
3327 %{
3328 constraint(ALLOC_IN_RC(v3_reg));
3329 match(VecA);
3330 match(vReg);
3331 op_cost(0);
3332 format %{ %}
3333 interface(REG_INTER);
3334 %}
3335
3336 operand vReg_V4()
3337 %{
3338 constraint(ALLOC_IN_RC(v4_reg));
3339 match(VecA);
3340 match(vReg);
3341 op_cost(0);
3342 format %{ %}
3343 interface(REG_INTER);
3344 %}
3345
3346 operand vReg_V5()
3347 %{
3348 constraint(ALLOC_IN_RC(v5_reg));
3349 match(VecA);
3350 match(vReg);
3351 op_cost(0);
3352 format %{ %}
3353 interface(REG_INTER);
3354 %}
3355
3356 operand vReg_V6()
3357 %{
3358 constraint(ALLOC_IN_RC(v6_reg));
3359 match(VecA);
3360 match(vReg);
3361 op_cost(0);
3362 format %{ %}
3363 interface(REG_INTER);
3364 %}
3365
3366 operand vReg_V7()
3367 %{
3368 constraint(ALLOC_IN_RC(v7_reg));
3369 match(VecA);
3370 match(vReg);
3371 op_cost(0);
3372 format %{ %}
3373 interface(REG_INTER);
3374 %}
3375
3376 operand vReg_V8()
3377 %{
3378 constraint(ALLOC_IN_RC(v8_reg));
3379 match(VecA);
3380 match(vReg);
3381 op_cost(0);
3382 format %{ %}
3383 interface(REG_INTER);
3384 %}
3385
3386 operand vReg_V9()
3387 %{
3388 constraint(ALLOC_IN_RC(v9_reg));
3389 match(VecA);
3390 match(vReg);
3391 op_cost(0);
3392 format %{ %}
3393 interface(REG_INTER);
3394 %}
3395
3396 operand vReg_V10()
3397 %{
3398 constraint(ALLOC_IN_RC(v10_reg));
3399 match(VecA);
3400 match(vReg);
3401 op_cost(0);
3402 format %{ %}
3403 interface(REG_INTER);
3404 %}
3405
3406 operand vReg_V11()
3407 %{
3408 constraint(ALLOC_IN_RC(v11_reg));
3409 match(VecA);
3410 match(vReg);
3411 op_cost(0);
3412 format %{ %}
3413 interface(REG_INTER);
3414 %}
3415
3416 operand vRegMask()
3417 %{
3418 constraint(ALLOC_IN_RC(vmask_reg));
3419 match(RegVectMask);
3420 match(vRegMask_V0);
3421 op_cost(0);
3422 format %{ %}
3423 interface(REG_INTER);
3424 %}
3425
3426 // The mask value used to control execution of a masked
3427 // vector instruction is always supplied by vector register v0.
3428 operand vRegMask_V0()
3429 %{
3430 constraint(ALLOC_IN_RC(vmask_reg_v0));
3431 match(RegVectMask);
3432 match(vRegMask);
3433 op_cost(0);
3434 format %{ %}
3435 interface(REG_INTER);
3436 %}
3437
3438 // Java Thread Register
3439 operand javaThread_RegP(iRegP reg)
3440 %{
3441 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3442 match(reg);
3443 op_cost(0);
3444 format %{ %}
3445 interface(REG_INTER);
3446 %}
3447
3448 //----------Memory Operands----------------------------------------------------
3449 // RISCV has only base_plus_offset and literal address mode, so no need to use
3450 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3451 operand indirect(iRegP reg)
3452 %{
3453 constraint(ALLOC_IN_RC(ptr_reg));
3454 match(reg);
3455 op_cost(0);
3456 format %{ "[$reg]" %}
3457 interface(MEMORY_INTER) %{
3458 base($reg);
3459 index(0xffffffff);
3460 scale(0x0);
3461 disp(0x0);
3462 %}
3463 %}
3464
3465 operand indOffI(iRegP reg, immIOffset off)
3466 %{
3467 constraint(ALLOC_IN_RC(ptr_reg));
3468 match(AddP reg off);
3469 op_cost(0);
3470 format %{ "[$reg, $off]" %}
3471 interface(MEMORY_INTER) %{
3472 base($reg);
3473 index(0xffffffff);
3474 scale(0x0);
3475 disp($off);
3476 %}
3477 %}
3478
3479 operand indOffL(iRegP reg, immLOffset off)
3480 %{
3481 constraint(ALLOC_IN_RC(ptr_reg));
3482 match(AddP reg off);
3483 op_cost(0);
3484 format %{ "[$reg, $off]" %}
3485 interface(MEMORY_INTER) %{
3486 base($reg);
3487 index(0xffffffff);
3488 scale(0x0);
3489 disp($off);
3490 %}
3491 %}
3492
3493 operand indirectN(iRegN reg)
3494 %{
3495 predicate(CompressedOops::shift() == 0);
3496 constraint(ALLOC_IN_RC(ptr_reg));
3497 match(DecodeN reg);
3498 op_cost(0);
3499 format %{ "[$reg]\t# narrow" %}
3500 interface(MEMORY_INTER) %{
3501 base($reg);
3502 index(0xffffffff);
3503 scale(0x0);
3504 disp(0x0);
3505 %}
3506 %}
3507
3508 operand indOffIN(iRegN reg, immIOffset off)
3509 %{
3510 predicate(CompressedOops::shift() == 0);
3511 constraint(ALLOC_IN_RC(ptr_reg));
3512 match(AddP (DecodeN reg) off);
3513 op_cost(0);
3514 format %{ "[$reg, $off]\t# narrow" %}
3515 interface(MEMORY_INTER) %{
3516 base($reg);
3517 index(0xffffffff);
3518 scale(0x0);
3519 disp($off);
3520 %}
3521 %}
3522
3523 operand indOffLN(iRegN reg, immLOffset off)
3524 %{
3525 predicate(CompressedOops::shift() == 0);
3526 constraint(ALLOC_IN_RC(ptr_reg));
3527 match(AddP (DecodeN reg) off);
3528 op_cost(0);
3529 format %{ "[$reg, $off]\t# narrow" %}
3530 interface(MEMORY_INTER) %{
3531 base($reg);
3532 index(0xffffffff);
3533 scale(0x0);
3534 disp($off);
3535 %}
3536 %}
3537
3538 //----------Special Memory Operands--------------------------------------------
3539 // Stack Slot Operand - This operand is used for loading and storing temporary
3540 // values on the stack where a match requires a value to
3541 // flow through memory.
3542 operand stackSlotI(sRegI reg)
3543 %{
3544 constraint(ALLOC_IN_RC(stack_slots));
3545 // No match rule because this operand is only generated in matching
3546 // match(RegI);
3547 format %{ "[$reg]" %}
3548 interface(MEMORY_INTER) %{
3549 base(0x02); // RSP
3550 index(0xffffffff); // No Index
3551 scale(0x0); // No Scale
3552 disp($reg); // Stack Offset
3553 %}
3554 %}
3555
3556 operand stackSlotF(sRegF reg)
3557 %{
3558 constraint(ALLOC_IN_RC(stack_slots));
3559 // No match rule because this operand is only generated in matching
3560 // match(RegF);
3561 format %{ "[$reg]" %}
3562 interface(MEMORY_INTER) %{
3563 base(0x02); // RSP
3564 index(0xffffffff); // No Index
3565 scale(0x0); // No Scale
3566 disp($reg); // Stack Offset
3567 %}
3568 %}
3569
3570 operand stackSlotD(sRegD reg)
3571 %{
3572 constraint(ALLOC_IN_RC(stack_slots));
3573 // No match rule because this operand is only generated in matching
3574 // match(RegD);
3575 format %{ "[$reg]" %}
3576 interface(MEMORY_INTER) %{
3577 base(0x02); // RSP
3578 index(0xffffffff); // No Index
3579 scale(0x0); // No Scale
3580 disp($reg); // Stack Offset
3581 %}
3582 %}
3583
3584 operand stackSlotL(sRegL reg)
3585 %{
3586 constraint(ALLOC_IN_RC(stack_slots));
3587 // No match rule because this operand is only generated in matching
3588 // match(RegL);
3589 format %{ "[$reg]" %}
3590 interface(MEMORY_INTER) %{
3591 base(0x02); // RSP
3592 index(0xffffffff); // No Index
3593 scale(0x0); // No Scale
3594 disp($reg); // Stack Offset
3595 %}
3596 %}
3597
3598 // Special operand allowing long args to int ops to be truncated for free
3599
3600 operand iRegL2I(iRegL reg) %{
3601
3602 op_cost(0);
3603
3604 match(ConvL2I reg);
3605
3606 format %{ "l2i($reg)" %}
3607
3608 interface(REG_INTER)
3609 %}
3610
3611
3612 // Comparison Operands
3613 // NOTE: Label is a predefined operand which should not be redefined in
3614 // the AD file. It is generically handled within the ADLC.
3615
3616 //----------Conditional Branch Operands----------------------------------------
3617 // Comparison Op - This is the operation of the comparison, and is limited to
3618 // the following set of codes:
3619 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3620 //
3621 // Other attributes of the comparison, such as unsignedness, are specified
3622 // by the comparison instruction that sets a condition code flags register.
3623 // That result is represented by a flags operand whose subtype is appropriate
3624 // to the unsignedness (etc.) of the comparison.
3625 //
3626 // Later, the instruction which matches both the Comparison Op (a Bool) and
3627 // the flags (produced by the Cmp) specifies the coding of the comparison op
3628 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3629
3630
3631 // used for signed integral comparisons and fp comparisons
3632 operand cmpOp()
3633 %{
3634 match(Bool);
3635
3636 format %{ "" %}
3637
3638 // the values in interface derives from struct BoolTest::mask
3639 interface(COND_INTER) %{
3640 equal(0x0, "eq");
3641 greater(0x1, "gt");
3642 overflow(0x2, "overflow");
3643 less(0x3, "lt");
3644 not_equal(0x4, "ne");
3645 less_equal(0x5, "le");
3646 no_overflow(0x6, "no_overflow");
3647 greater_equal(0x7, "ge");
3648 %}
3649 %}
3650
3651 // used for unsigned integral comparisons
3652 operand cmpOpU()
3653 %{
3654 match(Bool);
3655
3656 format %{ "" %}
3657 // the values in interface derives from struct BoolTest::mask
3658 interface(COND_INTER) %{
3659 equal(0x0, "eq");
3660 greater(0x1, "gtu");
3661 overflow(0x2, "overflow");
3662 less(0x3, "ltu");
3663 not_equal(0x4, "ne");
3664 less_equal(0x5, "leu");
3665 no_overflow(0x6, "no_overflow");
3666 greater_equal(0x7, "geu");
3667 %}
3668 %}
3669
3670 // used for certain integral comparisons which can be
3671 // converted to bxx instructions
3672 operand cmpOpEqNe()
3673 %{
3674 match(Bool);
3675 op_cost(0);
3676 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3677 n->as_Bool()->_test._test == BoolTest::eq);
3678
3679 format %{ "" %}
3680 interface(COND_INTER) %{
3681 equal(0x0, "eq");
3682 greater(0x1, "gt");
3683 overflow(0x2, "overflow");
3684 less(0x3, "lt");
3685 not_equal(0x4, "ne");
3686 less_equal(0x5, "le");
3687 no_overflow(0x6, "no_overflow");
3688 greater_equal(0x7, "ge");
3689 %}
3690 %}
3691
3692 operand cmpOpULtGe()
3693 %{
3694 match(Bool);
3695 op_cost(0);
3696 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3697 n->as_Bool()->_test._test == BoolTest::ge);
3698
3699 format %{ "" %}
3700 interface(COND_INTER) %{
3701 equal(0x0, "eq");
3702 greater(0x1, "gtu");
3703 overflow(0x2, "overflow");
3704 less(0x3, "ltu");
3705 not_equal(0x4, "ne");
3706 less_equal(0x5, "leu");
3707 no_overflow(0x6, "no_overflow");
3708 greater_equal(0x7, "geu");
3709 %}
3710 %}
3711
3712 operand cmpOpUEqNeLeGt()
3713 %{
3714 match(Bool);
3715 op_cost(0);
3716 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3717 n->as_Bool()->_test._test == BoolTest::eq ||
3718 n->as_Bool()->_test._test == BoolTest::le ||
3719 n->as_Bool()->_test._test == BoolTest::gt);
3720
3721 format %{ "" %}
3722 interface(COND_INTER) %{
3723 equal(0x0, "eq");
3724 greater(0x1, "gtu");
3725 overflow(0x2, "overflow");
3726 less(0x3, "ltu");
3727 not_equal(0x4, "ne");
3728 less_equal(0x5, "leu");
3729 no_overflow(0x6, "no_overflow");
3730 greater_equal(0x7, "geu");
3731 %}
3732 %}
3733
3734
3735 // Flags register, used as output of compare logic
3736 operand rFlagsReg()
3737 %{
3738 constraint(ALLOC_IN_RC(reg_flags));
3739 match(RegFlags);
3740
3741 op_cost(0);
3742 format %{ "RFLAGS" %}
3743 interface(REG_INTER);
3744 %}
3745
3746 // Special Registers
3747
3748 // Method Register
3749 operand inline_cache_RegP(iRegP reg)
3750 %{
3751 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3752 match(reg);
3753 match(iRegPNoSp);
3754 op_cost(0);
3755 format %{ %}
3756 interface(REG_INTER);
3757 %}
3758
3759 //----------OPERAND CLASSES----------------------------------------------------
3760 // Operand Classes are groups of operands that are used as to simplify
3761 // instruction definitions by not requiring the AD writer to specify
3762 // separate instructions for every form of operand when the
3763 // instruction accepts multiple operand types with the same basic
3764 // encoding and format. The classic case of this is memory operands.
3765
3766 // memory is used to define read/write location for load/store
3767 // instruction defs. we can turn a memory op into an Address
3768
3769 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3770
3771 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3772 // operations. it allows the src to be either an iRegI or a (ConvL2I
3773 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3774 // can be elided because the 32-bit instruction will just employ the
3775 // lower 32 bits anyway.
3776 //
3777 // n.b. this does not elide all L2I conversions. if the truncated
3778 // value is consumed by more than one operation then the ConvL2I
3779 // cannot be bundled into the consuming nodes so an l2i gets planted
3780 // (actually an addiw $dst, $src, 0) and the downstream instructions
3781 // consume the result of the L2I as an iRegI input. That's a shame since
3782 // the addiw is actually redundant but its not too costly.
3783
3784 opclass iRegIorL2I(iRegI, iRegL2I);
3785 opclass iRegIorL(iRegI, iRegL);
3786 opclass iRegNorP(iRegN, iRegP);
3787 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3788 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3789 opclass immIorL(immI, immL);
3790
3791 //----------PIPELINE-----------------------------------------------------------
3792 // Rules which define the behavior of the target architectures pipeline.
3793
3794 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3795 //pipe_desc(ID, EX, MEM, WR);
3796 #define ID S0
3797 #define EX S1
3798 #define MEM S2
3799 #define WR S3
3800
3801 // Integer ALU reg operation
3802 pipeline %{
3803
3804 attributes %{
3805 // RISC-V instructions are of length 2 or 4 bytes.
3806 variable_size_instructions;
3807 instruction_unit_size = 2;
3808
3809 // Up to 4 instructions per bundle
3810 max_instructions_per_bundle = 4;
3811
3812 // The RISC-V processor fetches 64 bytes...
3813 instruction_fetch_unit_size = 64;
3814
3815 // ...in one line.
3816 instruction_fetch_units = 1;
3817 %}
3818
3819 // We don't use an actual pipeline model so don't care about resources
3820 // or description. we do use pipeline classes to introduce fixed
3821 // latencies
3822
3823 //----------RESOURCES----------------------------------------------------------
3824 // Resources are the functional units available to the machine
3825
3826 // Generic RISC-V pipeline
3827 // 1 decoder
3828 // 1 instruction decoded per cycle
3829 // 1 load/store ops per cycle, 1 branch, 1 FPU
3830 // 1 mul, 1 div
3831
3832 resources ( DECODE,
3833 ALU,
3834 MUL,
3835 DIV,
3836 BRANCH,
3837 LDST,
3838 FPU);
3839
3840 //----------PIPELINE DESCRIPTION-----------------------------------------------
3841 // Pipeline Description specifies the stages in the machine's pipeline
3842
3843 // Define the pipeline as a generic 6 stage pipeline
3844 pipe_desc(S0, S1, S2, S3, S4, S5);
3845
3846 //----------PIPELINE CLASSES---------------------------------------------------
3847 // Pipeline Classes describe the stages in which input and output are
3848 // referenced by the hardware pipeline.
3849
3850 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3851 %{
3852 single_instruction;
3853 src1 : S1(read);
3854 src2 : S2(read);
3855 dst : S5(write);
3856 DECODE : ID;
3857 FPU : S5;
3858 %}
3859
3860 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3861 %{
3862 src1 : S1(read);
3863 src2 : S2(read);
3864 dst : S5(write);
3865 DECODE : ID;
3866 FPU : S5;
3867 %}
3868
3869 pipe_class fp_uop_s(fRegF dst, fRegF src)
3870 %{
3871 single_instruction;
3872 src : S1(read);
3873 dst : S5(write);
3874 DECODE : ID;
3875 FPU : S5;
3876 %}
3877
3878 pipe_class fp_uop_d(fRegD dst, fRegD src)
3879 %{
3880 single_instruction;
3881 src : S1(read);
3882 dst : S5(write);
3883 DECODE : ID;
3884 FPU : S5;
3885 %}
3886
3887 pipe_class fp_d2f(fRegF dst, fRegD src)
3888 %{
3889 single_instruction;
3890 src : S1(read);
3891 dst : S5(write);
3892 DECODE : ID;
3893 FPU : S5;
3894 %}
3895
3896 pipe_class fp_f2d(fRegD dst, fRegF src)
3897 %{
3898 single_instruction;
3899 src : S1(read);
3900 dst : S5(write);
3901 DECODE : ID;
3902 FPU : S5;
3903 %}
3904
3905 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3906 %{
3907 single_instruction;
3908 src : S1(read);
3909 dst : S5(write);
3910 DECODE : ID;
3911 FPU : S5;
3912 %}
3913
3914 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3915 %{
3916 single_instruction;
3917 src : S1(read);
3918 dst : S5(write);
3919 DECODE : ID;
3920 FPU : S5;
3921 %}
3922
3923 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3924 %{
3925 single_instruction;
3926 src : S1(read);
3927 dst : S5(write);
3928 DECODE : ID;
3929 FPU : S5;
3930 %}
3931
3932 pipe_class fp_l2f(fRegF dst, iRegL src)
3933 %{
3934 single_instruction;
3935 src : S1(read);
3936 dst : S5(write);
3937 DECODE : ID;
3938 FPU : S5;
3939 %}
3940
3941 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3942 %{
3943 single_instruction;
3944 src : S1(read);
3945 dst : S5(write);
3946 DECODE : ID;
3947 FPU : S5;
3948 %}
3949
3950 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3951 %{
3952 single_instruction;
3953 src : S1(read);
3954 dst : S5(write);
3955 DECODE : ID;
3956 FPU : S5;
3957 %}
3958
3959 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
3960 %{
3961 single_instruction;
3962 src : S1(read);
3963 dst : S5(write);
3964 DECODE : ID;
3965 FPU : S5;
3966 %}
3967
3968 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
3969 %{
3970 single_instruction;
3971 src : S1(read);
3972 dst : S5(write);
3973 DECODE : ID;
3974 FPU : S5;
3975 %}
3976
3977 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
3978 %{
3979 single_instruction;
3980 src1 : S1(read);
3981 src2 : S2(read);
3982 dst : S5(write);
3983 DECODE : ID;
3984 FPU : S5;
3985 %}
3986
3987 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
3988 %{
3989 single_instruction;
3990 src1 : S1(read);
3991 src2 : S2(read);
3992 dst : S5(write);
3993 DECODE : ID;
3994 FPU : S5;
3995 %}
3996
3997 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
3998 %{
3999 single_instruction;
4000 src : S1(read);
4001 dst : S5(write);
4002 DECODE : ID;
4003 FPU : S5;
4004 %}
4005
4006 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4007 %{
4008 single_instruction;
4009 src : S1(read);
4010 dst : S5(write);
4011 DECODE : ID;
4012 FPU : S5;
4013 %}
4014
4015 pipe_class fp_load_constant_s(fRegF dst)
4016 %{
4017 single_instruction;
4018 dst : S5(write);
4019 DECODE : ID;
4020 FPU : S5;
4021 %}
4022
4023 pipe_class fp_load_constant_d(fRegD dst)
4024 %{
4025 single_instruction;
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4032 %{
4033 single_instruction;
4034 mem : S1(read);
4035 dst : S5(write);
4036 DECODE : ID;
4037 LDST : MEM;
4038 %}
4039
4040 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4041 %{
4042 single_instruction;
4043 mem : S1(read);
4044 dst : S5(write);
4045 DECODE : ID;
4046 LDST : MEM;
4047 %}
4048
4049 pipe_class fp_store_reg_s(fRegF src, memory mem)
4050 %{
4051 single_instruction;
4052 src : S1(read);
4053 mem : S5(write);
4054 DECODE : ID;
4055 LDST : MEM;
4056 %}
4057
4058 pipe_class fp_store_reg_d(fRegD src, memory mem)
4059 %{
4060 single_instruction;
4061 src : S1(read);
4062 mem : S5(write);
4063 DECODE : ID;
4064 LDST : MEM;
4065 %}
4066
4067 //------- Integer ALU operations --------------------------
4068
4069 // Integer ALU reg-reg operation
4070 // Operands needs in ID, result generated in EX
4071 // E.g. ADD Rd, Rs1, Rs2
4072 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4073 %{
4074 single_instruction;
4075 dst : EX(write);
4076 src1 : ID(read);
4077 src2 : ID(read);
4078 DECODE : ID;
4079 ALU : EX;
4080 %}
4081
4082 // Integer ALU reg operation with constant shift
4083 // E.g. SLLI Rd, Rs1, #shift
4084 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4085 %{
4086 single_instruction;
4087 dst : EX(write);
4088 src1 : ID(read);
4089 DECODE : ID;
4090 ALU : EX;
4091 %}
4092
4093 // Integer ALU reg-reg operation with variable shift
4094 // both operands must be available in ID
4095 // E.g. SLL Rd, Rs1, Rs2
4096 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4097 %{
4098 single_instruction;
4099 dst : EX(write);
4100 src1 : ID(read);
4101 src2 : ID(read);
4102 DECODE : ID;
4103 ALU : EX;
4104 %}
4105
4106 // Integer ALU reg operation
4107 // E.g. NEG Rd, Rs2
4108 pipe_class ialu_reg(iRegI dst, iRegI src)
4109 %{
4110 single_instruction;
4111 dst : EX(write);
4112 src : ID(read);
4113 DECODE : ID;
4114 ALU : EX;
4115 %}
4116
4117 // Integer ALU reg immediate operation
4118 // E.g. ADDI Rd, Rs1, #imm
4119 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4120 %{
4121 single_instruction;
4122 dst : EX(write);
4123 src1 : ID(read);
4124 DECODE : ID;
4125 ALU : EX;
4126 %}
4127
4128 // Integer ALU immediate operation (no source operands)
4129 // E.g. LI Rd, #imm
4130 pipe_class ialu_imm(iRegI dst)
4131 %{
4132 single_instruction;
4133 dst : EX(write);
4134 DECODE : ID;
4135 ALU : EX;
4136 %}
4137
4138 //------- Multiply pipeline operations --------------------
4139
4140 // Multiply reg-reg
4141 // E.g. MULW Rd, Rs1, Rs2
4142 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4143 %{
4144 single_instruction;
4145 dst : WR(write);
4146 src1 : ID(read);
4147 src2 : ID(read);
4148 DECODE : ID;
4149 MUL : WR;
4150 %}
4151
4152 // E.g. MUL RD, Rs1, Rs2
4153 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4154 %{
4155 single_instruction;
4156 fixed_latency(3); // Maximum latency for 64 bit mul
4157 dst : WR(write);
4158 src1 : ID(read);
4159 src2 : ID(read);
4160 DECODE : ID;
4161 MUL : WR;
4162 %}
4163
4164 //------- Divide pipeline operations --------------------
4165
4166 // E.g. DIVW Rd, Rs1, Rs2
4167 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4168 %{
4169 single_instruction;
4170 fixed_latency(8); // Maximum latency for 32 bit divide
4171 dst : WR(write);
4172 src1 : ID(read);
4173 src2 : ID(read);
4174 DECODE : ID;
4175 DIV : WR;
4176 %}
4177
4178 // E.g. DIV RD, Rs1, Rs2
4179 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4180 %{
4181 single_instruction;
4182 fixed_latency(16); // Maximum latency for 64 bit divide
4183 dst : WR(write);
4184 src1 : ID(read);
4185 src2 : ID(read);
4186 DECODE : ID;
4187 DIV : WR;
4188 %}
4189
4190 //------- Load pipeline operations ------------------------
4191
4192 // Load - prefetch
4193 // Eg. PREFETCH_W mem
4194 pipe_class iload_prefetch(memory mem)
4195 %{
4196 single_instruction;
4197 mem : ID(read);
4198 DECODE : ID;
4199 LDST : MEM;
4200 %}
4201
4202 // Load - reg, mem
4203 // E.g. LA Rd, mem
4204 pipe_class iload_reg_mem(iRegI dst, memory mem)
4205 %{
4206 single_instruction;
4207 dst : WR(write);
4208 mem : ID(read);
4209 DECODE : ID;
4210 LDST : MEM;
4211 %}
4212
4213 // Load - reg, reg
4214 // E.g. LD Rd, Rs
4215 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4216 %{
4217 single_instruction;
4218 dst : WR(write);
4219 src : ID(read);
4220 DECODE : ID;
4221 LDST : MEM;
4222 %}
4223
4224 //------- Store pipeline operations -----------------------
4225
4226 // Store - zr, mem
4227 // E.g. SD zr, mem
4228 pipe_class istore_mem(memory mem)
4229 %{
4230 single_instruction;
4231 mem : ID(read);
4232 DECODE : ID;
4233 LDST : MEM;
4234 %}
4235
4236 // Store - reg, mem
4237 // E.g. SD Rs, mem
4238 pipe_class istore_reg_mem(iRegI src, memory mem)
4239 %{
4240 single_instruction;
4241 mem : ID(read);
4242 src : EX(read);
4243 DECODE : ID;
4244 LDST : MEM;
4245 %}
4246
4247 // Store - reg, reg
4248 // E.g. SD Rs2, Rs1
4249 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4250 %{
4251 single_instruction;
4252 dst : ID(read);
4253 src : EX(read);
4254 DECODE : ID;
4255 LDST : MEM;
4256 %}
4257
4258 //------- Control transfer pipeline operations ------------
4259
4260 // Branch
4261 pipe_class pipe_branch()
4262 %{
4263 single_instruction;
4264 DECODE : ID;
4265 BRANCH : EX;
4266 %}
4267
4268 // Branch
4269 pipe_class pipe_branch_reg(iRegI src)
4270 %{
4271 single_instruction;
4272 src : ID(read);
4273 DECODE : ID;
4274 BRANCH : EX;
4275 %}
4276
4277 // Compare & Branch
4278 // E.g. BEQ Rs1, Rs2, L
4279 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4280 %{
4281 single_instruction;
4282 src1 : ID(read);
4283 src2 : ID(read);
4284 DECODE : ID;
4285 BRANCH : EX;
4286 %}
4287
4288 // E.g. BEQZ Rs, L
4289 pipe_class pipe_cmpz_branch(iRegI src)
4290 %{
4291 single_instruction;
4292 src : ID(read);
4293 DECODE : ID;
4294 BRANCH : EX;
4295 %}
4296
4297 //------- Synchronisation operations ----------------------
4298 // Any operation requiring serialization
4299 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4300 pipe_class pipe_serial()
4301 %{
4302 single_instruction;
4303 force_serialization;
4304 fixed_latency(16);
4305 DECODE : ID;
4306 LDST : MEM;
4307 %}
4308
4309 pipe_class pipe_slow()
4310 %{
4311 instruction_count(10);
4312 multiple_bundles;
4313 force_serialization;
4314 fixed_latency(16);
4315 DECODE : ID;
4316 LDST : MEM;
4317 %}
4318
4319 // The real do-nothing guy
4320 pipe_class real_empty()
4321 %{
4322 instruction_count(0);
4323 %}
4324
4325 // Empty pipeline class
4326 pipe_class pipe_class_empty()
4327 %{
4328 single_instruction;
4329 fixed_latency(0);
4330 %}
4331
4332 // Default pipeline class.
4333 pipe_class pipe_class_default()
4334 %{
4335 single_instruction;
4336 fixed_latency(2);
4337 %}
4338
4339 // Pipeline class for compares.
4340 pipe_class pipe_class_compare()
4341 %{
4342 single_instruction;
4343 fixed_latency(16);
4344 %}
4345
4346 // Pipeline class for memory operations.
4347 pipe_class pipe_class_memory()
4348 %{
4349 single_instruction;
4350 fixed_latency(16);
4351 %}
4352
4353 // Pipeline class for call.
4354 pipe_class pipe_class_call()
4355 %{
4356 single_instruction;
4357 fixed_latency(100);
4358 %}
4359
4360 // Define the class for the Nop node.
4361 define %{
4362 MachNop = pipe_class_empty;
4363 %}
4364 %}
4365 //----------INSTRUCTIONS-------------------------------------------------------
4366 //
4367 // match -- States which machine-independent subtree may be replaced
4368 // by this instruction.
4369 // ins_cost -- The estimated cost of this instruction is used by instruction
4370 // selection to identify a minimum cost tree of machine
4371 // instructions that matches a tree of machine-independent
4372 // instructions.
4373 // format -- A string providing the disassembly for this instruction.
4374 // The value of an instruction's operand may be inserted
4375 // by referring to it with a '$' prefix.
4376 // opcode -- Three instruction opcodes may be provided. These are referred
4377 // to within an encode class as $primary, $secondary, and $tertiary
4378 // rrspectively. The primary opcode is commonly used to
4379 // indicate the type of machine instruction, while secondary
4380 // and tertiary are often used for prefix options or addressing
4381 // modes.
4382 // ins_encode -- A list of encode classes with parameters. The encode class
4383 // name must have been defined in an 'enc_class' specification
4384 // in the encode section of the architecture description.
4385
4386 // ============================================================================
4387 // Memory (Load/Store) Instructions
4388
4389 // Load Instructions
4390
4391 // Load Byte (8 bit signed)
4392 instruct loadB(iRegINoSp dst, memory mem)
4393 %{
4394 match(Set dst (LoadB mem));
4395
4396 ins_cost(LOAD_COST);
4397 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4398
4399 ins_encode %{
4400 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4401 %}
4402
4403 ins_pipe(iload_reg_mem);
4404 %}
4405
4406 // Load Byte (8 bit signed) into long
4407 instruct loadB2L(iRegLNoSp dst, memory mem)
4408 %{
4409 match(Set dst (ConvI2L (LoadB mem)));
4410
4411 ins_cost(LOAD_COST);
4412 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4413
4414 ins_encode %{
4415 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4416 %}
4417
4418 ins_pipe(iload_reg_mem);
4419 %}
4420
4421 // Load Byte (8 bit unsigned)
4422 instruct loadUB(iRegINoSp dst, memory mem)
4423 %{
4424 match(Set dst (LoadUB mem));
4425
4426 ins_cost(LOAD_COST);
4427 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4428
4429 ins_encode %{
4430 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4431 %}
4432
4433 ins_pipe(iload_reg_mem);
4434 %}
4435
4436 // Load Byte (8 bit unsigned) into long
4437 instruct loadUB2L(iRegLNoSp dst, memory mem)
4438 %{
4439 match(Set dst (ConvI2L (LoadUB mem)));
4440
4441 ins_cost(LOAD_COST);
4442 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4443
4444 ins_encode %{
4445 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4446 %}
4447
4448 ins_pipe(iload_reg_mem);
4449 %}
4450
4451 // Load Short (16 bit signed)
4452 instruct loadS(iRegINoSp dst, memory mem)
4453 %{
4454 match(Set dst (LoadS mem));
4455
4456 ins_cost(LOAD_COST);
4457 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4458
4459 ins_encode %{
4460 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4461 %}
4462
4463 ins_pipe(iload_reg_mem);
4464 %}
4465
4466 // Load Short (16 bit signed) into long
4467 instruct loadS2L(iRegLNoSp dst, memory mem)
4468 %{
4469 match(Set dst (ConvI2L (LoadS mem)));
4470
4471 ins_cost(LOAD_COST);
4472 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4473
4474 ins_encode %{
4475 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4476 %}
4477
4478 ins_pipe(iload_reg_mem);
4479 %}
4480
4481 // Load Char (16 bit unsigned)
4482 instruct loadUS(iRegINoSp dst, memory mem)
4483 %{
4484 match(Set dst (LoadUS mem));
4485
4486 ins_cost(LOAD_COST);
4487 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4488
4489 ins_encode %{
4490 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4491 %}
4492
4493 ins_pipe(iload_reg_mem);
4494 %}
4495
4496 // Load Short/Char (16 bit unsigned) into long
4497 instruct loadUS2L(iRegLNoSp dst, memory mem)
4498 %{
4499 match(Set dst (ConvI2L (LoadUS mem)));
4500
4501 ins_cost(LOAD_COST);
4502 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4503
4504 ins_encode %{
4505 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4506 %}
4507
4508 ins_pipe(iload_reg_mem);
4509 %}
4510
4511 // Load Integer (32 bit signed)
4512 instruct loadI(iRegINoSp dst, memory mem)
4513 %{
4514 match(Set dst (LoadI mem));
4515
4516 ins_cost(LOAD_COST);
4517 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4518
4519 ins_encode %{
4520 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4521 %}
4522
4523 ins_pipe(iload_reg_mem);
4524 %}
4525
4526 // Load Integer (32 bit signed) into long
4527 instruct loadI2L(iRegLNoSp dst, memory mem)
4528 %{
4529 match(Set dst (ConvI2L (LoadI mem)));
4530
4531 ins_cost(LOAD_COST);
4532 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4533
4534 ins_encode %{
4535 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4536 %}
4537
4538 ins_pipe(iload_reg_mem);
4539 %}
4540
4541 // Load Integer (32 bit unsigned) into long
4542 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4543 %{
4544 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4545
4546 ins_cost(LOAD_COST);
4547 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4548
4549 ins_encode %{
4550 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4551 %}
4552
4553 ins_pipe(iload_reg_mem);
4554 %}
4555
4556 // Load Long (64 bit signed)
4557 instruct loadL(iRegLNoSp dst, memory mem)
4558 %{
4559 match(Set dst (LoadL mem));
4560
4561 ins_cost(LOAD_COST);
4562 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4563
4564 ins_encode %{
4565 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4566 %}
4567
4568 ins_pipe(iload_reg_mem);
4569 %}
4570
4571 // Load Range
4572 instruct loadRange(iRegINoSp dst, memory mem)
4573 %{
4574 match(Set dst (LoadRange mem));
4575
4576 ins_cost(LOAD_COST);
4577 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4578
4579 ins_encode %{
4580 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4581 %}
4582
4583 ins_pipe(iload_reg_mem);
4584 %}
4585
4586 // Load Pointer
4587 instruct loadP(iRegPNoSp dst, memory mem)
4588 %{
4589 match(Set dst (LoadP mem));
4590 predicate(n->as_Load()->barrier_data() == 0);
4591
4592 ins_cost(LOAD_COST);
4593 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4594
4595 ins_encode %{
4596 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4597 %}
4598
4599 ins_pipe(iload_reg_mem);
4600 %}
4601
4602 // Load Compressed Pointer
4603 instruct loadN(iRegNNoSp dst, memory mem)
4604 %{
4605 predicate(n->as_Load()->barrier_data() == 0);
4606 match(Set dst (LoadN mem));
4607
4608 ins_cost(LOAD_COST);
4609 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4610
4611 ins_encode %{
4612 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4613 %}
4614
4615 ins_pipe(iload_reg_mem);
4616 %}
4617
4618 // Load Klass Pointer
4619 instruct loadKlass(iRegPNoSp dst, memory mem)
4620 %{
4621 match(Set dst (LoadKlass mem));
4622
4623 ins_cost(LOAD_COST);
4624 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4625
4626 ins_encode %{
4627 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4628 %}
4629
4630 ins_pipe(iload_reg_mem);
4631 %}
4632
4633 // Load Narrow Klass Pointer
4634 instruct loadNKlass(iRegNNoSp dst, memory mem)
4635 %{
4636 predicate(!UseCompactObjectHeaders);
4637 match(Set dst (LoadNKlass mem));
4638
4639 ins_cost(LOAD_COST);
4640 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4641
4642 ins_encode %{
4643 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4644 %}
4645
4646 ins_pipe(iload_reg_mem);
4647 %}
4648
4649 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4650 %{
4651 predicate(UseCompactObjectHeaders);
4652 match(Set dst (LoadNKlass mem));
4653
4654 ins_cost(LOAD_COST);
4655 format %{
4656 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4657 "srli $dst, $dst, markWord::klass_shift_at_offset"
4658 %}
4659
4660 ins_encode %{
4661 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4662 __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4663 %}
4664
4665 ins_pipe(iload_reg_mem);
4666 %}
4667
4668 // Load Float
4669 instruct loadF(fRegF dst, memory mem)
4670 %{
4671 match(Set dst (LoadF mem));
4672
4673 ins_cost(LOAD_COST);
4674 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4675
4676 ins_encode %{
4677 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4678 %}
4679
4680 ins_pipe(fp_load_mem_s);
4681 %}
4682
4683 // Load Double
4684 instruct loadD(fRegD dst, memory mem)
4685 %{
4686 match(Set dst (LoadD mem));
4687
4688 ins_cost(LOAD_COST);
4689 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4690
4691 ins_encode %{
4692 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4693 %}
4694
4695 ins_pipe(fp_load_mem_d);
4696 %}
4697
4698 // Load Int Constant
4699 instruct loadConI(iRegINoSp dst, immI src)
4700 %{
4701 match(Set dst src);
4702
4703 ins_cost(ALU_COST);
4704 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4705
4706 ins_encode(riscv_enc_mov_imm(dst, src));
4707
4708 ins_pipe(ialu_imm);
4709 %}
4710
4711 // Load Long Constant
4712 instruct loadConL(iRegLNoSp dst, immL src)
4713 %{
4714 match(Set dst src);
4715
4716 ins_cost(ALU_COST);
4717 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4718
4719 ins_encode(riscv_enc_mov_imm(dst, src));
4720
4721 ins_pipe(ialu_imm);
4722 %}
4723
4724 // Load Pointer Constant
4725 instruct loadConP(iRegPNoSp dst, immP con)
4726 %{
4727 match(Set dst con);
4728
4729 ins_cost(ALU_COST);
4730 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4731
4732 ins_encode(riscv_enc_mov_p(dst, con));
4733
4734 ins_pipe(ialu_imm);
4735 %}
4736
4737 // Load Null Pointer Constant
4738 instruct loadConP0(iRegPNoSp dst, immP0 con)
4739 %{
4740 match(Set dst con);
4741
4742 ins_cost(ALU_COST);
4743 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4744
4745 ins_encode(riscv_enc_mov_zero(dst));
4746
4747 ins_pipe(ialu_imm);
4748 %}
4749
4750 // Load Pointer Constant One
4751 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4752 %{
4753 match(Set dst con);
4754
4755 ins_cost(ALU_COST);
4756 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4757
4758 ins_encode(riscv_enc_mov_p1(dst));
4759
4760 ins_pipe(ialu_imm);
4761 %}
4762
4763 // Load Narrow Pointer Constant
4764 instruct loadConN(iRegNNoSp dst, immN con)
4765 %{
4766 match(Set dst con);
4767
4768 ins_cost(ALU_COST * 4);
4769 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4770
4771 ins_encode(riscv_enc_mov_n(dst, con));
4772
4773 ins_pipe(ialu_imm);
4774 %}
4775
4776 // Load Narrow Null Pointer Constant
4777 instruct loadConN0(iRegNNoSp dst, immN0 con)
4778 %{
4779 match(Set dst con);
4780
4781 ins_cost(ALU_COST);
4782 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4783
4784 ins_encode(riscv_enc_mov_zero(dst));
4785
4786 ins_pipe(ialu_imm);
4787 %}
4788
4789 // Load Narrow Klass Constant
4790 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4791 %{
4792 match(Set dst con);
4793
4794 ins_cost(ALU_COST * 6);
4795 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4796
4797 ins_encode(riscv_enc_mov_nk(dst, con));
4798
4799 ins_pipe(ialu_imm);
4800 %}
4801
4802 // Load Half Float Constant
4803 instruct loadConH(fRegF dst, immH con) %{
4804 match(Set dst con);
4805
4806 ins_cost(LOAD_COST);
4807 format %{
4808 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4809 %}
4810
4811 ins_encode %{
4812 assert(UseZfh || UseZfhmin, "must");
4813 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4814 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4815 } else {
4816 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4817 }
4818 %}
4819
4820 ins_pipe(fp_load_constant_s);
4821 %}
4822
4823 instruct loadConH0(fRegF dst, immH0 con) %{
4824 match(Set dst con);
4825
4826 ins_cost(XFER_COST);
4827
4828 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4829
4830 ins_encode %{
4831 assert(UseZfh || UseZfhmin, "must");
4832 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4833 %}
4834
4835 ins_pipe(fp_load_constant_s);
4836 %}
4837
4838 // Load Float Constant
4839 instruct loadConF(fRegF dst, immF con) %{
4840 match(Set dst con);
4841
4842 ins_cost(LOAD_COST);
4843 format %{
4844 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4845 %}
4846
4847 ins_encode %{
4848 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4849 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4850 } else {
4851 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4852 }
4853 %}
4854
4855 ins_pipe(fp_load_constant_s);
4856 %}
4857
4858 instruct loadConF0(fRegF dst, immF0 con) %{
4859 match(Set dst con);
4860
4861 ins_cost(XFER_COST);
4862
4863 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4864
4865 ins_encode %{
4866 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4867 %}
4868
4869 ins_pipe(fp_load_constant_s);
4870 %}
4871
4872 // Load Double Constant
4873 instruct loadConD(fRegD dst, immD con) %{
4874 match(Set dst con);
4875
4876 ins_cost(LOAD_COST);
4877 format %{
4878 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4879 %}
4880
4881 ins_encode %{
4882 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4883 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4884 } else {
4885 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4886 }
4887 %}
4888
4889 ins_pipe(fp_load_constant_d);
4890 %}
4891
4892 instruct loadConD0(fRegD dst, immD0 con) %{
4893 match(Set dst con);
4894
4895 ins_cost(XFER_COST);
4896
4897 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4898
4899 ins_encode %{
4900 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4901 %}
4902
4903 ins_pipe(fp_load_constant_d);
4904 %}
4905
4906 // Store Byte
4907 instruct storeB(iRegIorL2I src, memory mem)
4908 %{
4909 match(Set mem (StoreB mem src));
4910
4911 ins_cost(STORE_COST);
4912 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4913
4914 ins_encode %{
4915 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4916 %}
4917
4918 ins_pipe(istore_reg_mem);
4919 %}
4920
4921 instruct storeimmB0(immI0 zero, memory mem)
4922 %{
4923 match(Set mem (StoreB mem zero));
4924
4925 ins_cost(STORE_COST);
4926 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4927
4928 ins_encode %{
4929 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4930 %}
4931
4932 ins_pipe(istore_mem);
4933 %}
4934
4935 // Store Char/Short
4936 instruct storeC(iRegIorL2I src, memory mem)
4937 %{
4938 match(Set mem (StoreC mem src));
4939
4940 ins_cost(STORE_COST);
4941 format %{ "sh $src, $mem\t# short, #@storeC" %}
4942
4943 ins_encode %{
4944 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4945 %}
4946
4947 ins_pipe(istore_reg_mem);
4948 %}
4949
4950 instruct storeimmC0(immI0 zero, memory mem)
4951 %{
4952 match(Set mem (StoreC mem zero));
4953
4954 ins_cost(STORE_COST);
4955 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4956
4957 ins_encode %{
4958 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4959 %}
4960
4961 ins_pipe(istore_mem);
4962 %}
4963
4964 // Store Integer
4965 instruct storeI(iRegIorL2I src, memory mem)
4966 %{
4967 match(Set mem(StoreI mem src));
4968
4969 ins_cost(STORE_COST);
4970 format %{ "sw $src, $mem\t# int, #@storeI" %}
4971
4972 ins_encode %{
4973 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4974 %}
4975
4976 ins_pipe(istore_reg_mem);
4977 %}
4978
4979 instruct storeimmI0(immI0 zero, memory mem)
4980 %{
4981 match(Set mem(StoreI mem zero));
4982
4983 ins_cost(STORE_COST);
4984 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
4985
4986 ins_encode %{
4987 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
4988 %}
4989
4990 ins_pipe(istore_mem);
4991 %}
4992
4993 // Store Long (64 bit signed)
4994 instruct storeL(iRegL src, memory mem)
4995 %{
4996 match(Set mem (StoreL mem src));
4997
4998 ins_cost(STORE_COST);
4999 format %{ "sd $src, $mem\t# long, #@storeL" %}
5000
5001 ins_encode %{
5002 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5003 %}
5004
5005 ins_pipe(istore_reg_mem);
5006 %}
5007
5008 // Store Long (64 bit signed)
5009 instruct storeimmL0(immL0 zero, memory mem)
5010 %{
5011 match(Set mem (StoreL mem zero));
5012
5013 ins_cost(STORE_COST);
5014 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5015
5016 ins_encode %{
5017 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5018 %}
5019
5020 ins_pipe(istore_mem);
5021 %}
5022
5023 // Store Pointer
5024 instruct storeP(iRegP src, memory mem)
5025 %{
5026 match(Set mem (StoreP mem src));
5027 predicate(n->as_Store()->barrier_data() == 0);
5028
5029 ins_cost(STORE_COST);
5030 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5031
5032 ins_encode %{
5033 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5034 %}
5035
5036 ins_pipe(istore_reg_mem);
5037 %}
5038
5039 // Store Pointer
5040 instruct storeimmP0(immP0 zero, memory mem)
5041 %{
5042 match(Set mem (StoreP mem zero));
5043 predicate(n->as_Store()->barrier_data() == 0);
5044
5045 ins_cost(STORE_COST);
5046 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5047
5048 ins_encode %{
5049 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5050 %}
5051
5052 ins_pipe(istore_mem);
5053 %}
5054
5055 // Store Compressed Pointer
5056 instruct storeN(iRegN src, memory mem)
5057 %{
5058 predicate(n->as_Store()->barrier_data() == 0);
5059 match(Set mem (StoreN mem src));
5060
5061 ins_cost(STORE_COST);
5062 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5063
5064 ins_encode %{
5065 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5066 %}
5067
5068 ins_pipe(istore_reg_mem);
5069 %}
5070
5071 instruct storeImmN0(immN0 zero, memory mem)
5072 %{
5073 predicate(n->as_Store()->barrier_data() == 0);
5074 match(Set mem (StoreN mem zero));
5075
5076 ins_cost(STORE_COST);
5077 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5078
5079 ins_encode %{
5080 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5081 %}
5082
5083 ins_pipe(istore_reg_mem);
5084 %}
5085
5086 // Store Float
5087 instruct storeF(fRegF src, memory mem)
5088 %{
5089 match(Set mem (StoreF mem src));
5090
5091 ins_cost(STORE_COST);
5092 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5093
5094 ins_encode %{
5095 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5096 %}
5097
5098 ins_pipe(fp_store_reg_s);
5099 %}
5100
5101 // Store Double
5102 instruct storeD(fRegD src, memory mem)
5103 %{
5104 match(Set mem (StoreD mem src));
5105
5106 ins_cost(STORE_COST);
5107 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5108
5109 ins_encode %{
5110 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5111 %}
5112
5113 ins_pipe(fp_store_reg_d);
5114 %}
5115
5116 // Store Compressed Klass Pointer
5117 instruct storeNKlass(iRegN src, memory mem)
5118 %{
5119 match(Set mem (StoreNKlass mem src));
5120
5121 ins_cost(STORE_COST);
5122 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5123
5124 ins_encode %{
5125 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5126 %}
5127
5128 ins_pipe(istore_reg_mem);
5129 %}
5130
5131 // ============================================================================
5132 // Prefetch instructions
5133 // Must be safe to execute with invalid address (cannot fault).
5134
5135 instruct prefetchalloc( memory mem ) %{
5136 predicate(UseZicbop);
5137 match(PrefetchAllocation mem);
5138
5139 ins_cost(ALU_COST * 1);
5140 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5141
5142 ins_encode %{
5143 if (Assembler::is_simm12($mem$$disp)) {
5144 if (($mem$$disp & 0x1f) == 0) {
5145 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5146 } else {
5147 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5148 __ prefetch_w(t0, 0);
5149 }
5150 } else {
5151 __ mv(t0, $mem$$disp);
5152 __ add(t0, as_Register($mem$$base), t0);
5153 __ prefetch_w(t0, 0);
5154 }
5155 %}
5156
5157 ins_pipe(iload_prefetch);
5158 %}
5159
5160 // ============================================================================
5161 // Atomic operation instructions
5162 //
5163
5164 // standard CompareAndSwapX when we are using barriers
5165 // these have higher priority than the rules selected by a predicate
5166 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5167 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5168 %{
5169 predicate(!UseZabha || !UseZacas);
5170
5171 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5172
5173 ins_cost(2 * VOLATILE_REF_COST);
5174
5175 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5176
5177 format %{
5178 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5179 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5180 %}
5181
5182 ins_encode %{
5183 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5184 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5185 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5186 %}
5187
5188 ins_pipe(pipe_slow);
5189 %}
5190
5191 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5192 %{
5193 predicate(UseZabha && UseZacas);
5194
5195 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5196
5197 ins_cost(2 * VOLATILE_REF_COST);
5198
5199 format %{
5200 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5201 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5202 %}
5203
5204 ins_encode %{
5205 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5206 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5207 true /* result as bool */);
5208 %}
5209
5210 ins_pipe(pipe_slow);
5211 %}
5212
5213 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5214 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5215 %{
5216 predicate(!UseZabha || !UseZacas);
5217
5218 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5219
5220 ins_cost(2 * VOLATILE_REF_COST);
5221
5222 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5223
5224 format %{
5225 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5226 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5227 %}
5228
5229 ins_encode %{
5230 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5231 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5232 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5233 %}
5234
5235 ins_pipe(pipe_slow);
5236 %}
5237
5238 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5239 %{
5240 predicate(UseZabha && UseZacas);
5241
5242 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5243
5244 ins_cost(2 * VOLATILE_REF_COST);
5245
5246 format %{
5247 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5248 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5249 %}
5250
5251 ins_encode %{
5252 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5253 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5254 true /* result as bool */);
5255 %}
5256
5257 ins_pipe(pipe_slow);
5258 %}
5259
5260 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5261 %{
5262 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5263
5264 ins_cost(2 * VOLATILE_REF_COST);
5265
5266 format %{
5267 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5268 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5269 %}
5270
5271 ins_encode %{
5272 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5273 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5274 /*result as bool*/ true);
5275 %}
5276
5277 ins_pipe(pipe_slow);
5278 %}
5279
5280 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5281 %{
5282 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5283
5284 ins_cost(2 * VOLATILE_REF_COST);
5285
5286 format %{
5287 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5288 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5289 %}
5290
5291 ins_encode %{
5292 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5293 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5294 /*result as bool*/ true);
5295 %}
5296
5297 ins_pipe(pipe_slow);
5298 %}
5299
5300 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5301 %{
5302 predicate(n->as_LoadStore()->barrier_data() == 0);
5303
5304 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5305
5306 ins_cost(2 * VOLATILE_REF_COST);
5307
5308 format %{
5309 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5310 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5311 %}
5312
5313 ins_encode %{
5314 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5315 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5316 /*result as bool*/ true);
5317 %}
5318
5319 ins_pipe(pipe_slow);
5320 %}
5321
5322 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5323 %{
5324 predicate(n->as_LoadStore()->barrier_data() == 0);
5325
5326 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5327
5328 ins_cost(2 * VOLATILE_REF_COST);
5329
5330 format %{
5331 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5332 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5333 %}
5334
5335 ins_encode %{
5336 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5337 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5338 /*result as bool*/ true);
5339 %}
5340
5341 ins_pipe(pipe_slow);
5342 %}
5343
5344 // alternative CompareAndSwapX when we are eliding barriers
5345 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5346 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5347 %{
5348 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5349
5350 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5351
5352 ins_cost(2 * VOLATILE_REF_COST);
5353
5354 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5355
5356 format %{
5357 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5358 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5359 %}
5360
5361 ins_encode %{
5362 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5363 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5364 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5365 %}
5366
5367 ins_pipe(pipe_slow);
5368 %}
5369
5370 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5371 %{
5372 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5373
5374 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5375
5376 ins_cost(2 * VOLATILE_REF_COST);
5377
5378 format %{
5379 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5380 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5381 %}
5382
5383 ins_encode %{
5384 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5385 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5386 true /* result as bool */);
5387 %}
5388
5389 ins_pipe(pipe_slow);
5390 %}
5391
5392 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5393 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5394 %{
5395 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5396
5397 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5398
5399 ins_cost(2 * VOLATILE_REF_COST);
5400
5401 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5402
5403 format %{
5404 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5405 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5406 %}
5407
5408 ins_encode %{
5409 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5410 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5411 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5412 %}
5413
5414 ins_pipe(pipe_slow);
5415 %}
5416
5417 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5418 %{
5419 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5420
5421 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5422
5423 ins_cost(2 * VOLATILE_REF_COST);
5424
5425 format %{
5426 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5427 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5428 %}
5429
5430 ins_encode %{
5431 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5432 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5433 true /* result as bool */);
5434 %}
5435
5436 ins_pipe(pipe_slow);
5437 %}
5438
5439 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5440 %{
5441 predicate(needs_acquiring_load_reserved(n));
5442
5443 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5444
5445 ins_cost(2 * VOLATILE_REF_COST);
5446
5447 format %{
5448 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5449 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5450 %}
5451
5452 ins_encode %{
5453 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5454 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5455 /*result as bool*/ true);
5456 %}
5457
5458 ins_pipe(pipe_slow);
5459 %}
5460
5461 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5462 %{
5463 predicate(needs_acquiring_load_reserved(n));
5464
5465 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5466
5467 ins_cost(2 * VOLATILE_REF_COST);
5468
5469 format %{
5470 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5471 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5472 %}
5473
5474 ins_encode %{
5475 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5476 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5477 /*result as bool*/ true);
5478 %}
5479
5480 ins_pipe(pipe_slow);
5481 %}
5482
5483 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5484 %{
5485 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5486
5487 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5488
5489 ins_cost(2 * VOLATILE_REF_COST);
5490
5491 format %{
5492 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5493 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5494 %}
5495
5496 ins_encode %{
5497 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5498 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5499 /*result as bool*/ true);
5500 %}
5501
5502 ins_pipe(pipe_slow);
5503 %}
5504
5505 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5506 %{
5507 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5508
5509 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5510
5511 ins_cost(2 * VOLATILE_REF_COST);
5512
5513 format %{
5514 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5515 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5516 %}
5517
5518 ins_encode %{
5519 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5520 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5521 /*result as bool*/ true);
5522 %}
5523
5524 ins_pipe(pipe_slow);
5525 %}
5526
5527 // Sundry CAS operations. Note that release is always true,
5528 // regardless of the memory ordering of the CAS. This is because we
5529 // need the volatile case to be sequentially consistent but there is
5530 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5531 // can't check the type of memory ordering here, so we always emit a
5532 // sc_d(w) with rl bit set.
5533 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5534 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5535 %{
5536 predicate(!UseZabha || !UseZacas);
5537
5538 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5539
5540 ins_cost(2 * VOLATILE_REF_COST);
5541
5542 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5543
5544 format %{
5545 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5546 %}
5547
5548 ins_encode %{
5549 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5550 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5551 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5552 %}
5553
5554 ins_pipe(pipe_slow);
5555 %}
5556
5557 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5558 %{
5559 predicate(UseZabha && UseZacas);
5560
5561 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5562
5563 ins_cost(2 * VOLATILE_REF_COST);
5564
5565 format %{
5566 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5567 %}
5568
5569 ins_encode %{
5570 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5571 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5572 %}
5573
5574 ins_pipe(pipe_slow);
5575 %}
5576
5577 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5578 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5579 %{
5580 predicate(!UseZabha || !UseZacas);
5581
5582 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5583
5584 ins_cost(2 * VOLATILE_REF_COST);
5585
5586 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5587
5588 format %{
5589 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5590 %}
5591
5592 ins_encode %{
5593 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5594 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5595 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5596 %}
5597
5598 ins_pipe(pipe_slow);
5599 %}
5600
5601 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5602 %{
5603 predicate(UseZabha && UseZacas);
5604
5605 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5606
5607 ins_cost(2 * VOLATILE_REF_COST);
5608
5609 format %{
5610 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5611 %}
5612
5613 ins_encode %{
5614 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5615 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5616 %}
5617
5618 ins_pipe(pipe_slow);
5619 %}
5620
5621 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5622 %{
5623 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5624
5625 ins_cost(2 * VOLATILE_REF_COST);
5626
5627 format %{
5628 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5629 %}
5630
5631 ins_encode %{
5632 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5633 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5634 %}
5635
5636 ins_pipe(pipe_slow);
5637 %}
5638
5639 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5640 %{
5641 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5642
5643 ins_cost(2 * VOLATILE_REF_COST);
5644
5645 format %{
5646 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5647 %}
5648
5649 ins_encode %{
5650 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5651 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5652 %}
5653
5654 ins_pipe(pipe_slow);
5655 %}
5656
5657 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5658 %{
5659 predicate(n->as_LoadStore()->barrier_data() == 0);
5660
5661 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5662
5663 ins_cost(2 * VOLATILE_REF_COST);
5664
5665 format %{
5666 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5667 %}
5668
5669 ins_encode %{
5670 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5671 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5672 %}
5673
5674 ins_pipe(pipe_slow);
5675 %}
5676
5677 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5678 %{
5679 predicate(n->as_LoadStore()->barrier_data() == 0);
5680
5681 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5682
5683 ins_cost(2 * VOLATILE_REF_COST);
5684
5685 format %{
5686 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5687 %}
5688
5689 ins_encode %{
5690 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5691 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5692 %}
5693
5694 ins_pipe(pipe_slow);
5695 %}
5696
5697 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5698 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5699 %{
5700 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5701
5702 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5703
5704 ins_cost(2 * VOLATILE_REF_COST);
5705
5706 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5707
5708 format %{
5709 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5710 %}
5711
5712 ins_encode %{
5713 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5714 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5715 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5716 %}
5717
5718 ins_pipe(pipe_slow);
5719 %}
5720
5721 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5722 %{
5723 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5724
5725 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5726
5727 ins_cost(2 * VOLATILE_REF_COST);
5728
5729 format %{
5730 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5731 %}
5732
5733 ins_encode %{
5734 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5735 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5736 %}
5737
5738 ins_pipe(pipe_slow);
5739 %}
5740
5741 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5742 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5743 %{
5744 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5745
5746 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5747
5748 ins_cost(2 * VOLATILE_REF_COST);
5749
5750 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5751
5752 format %{
5753 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5754 %}
5755
5756 ins_encode %{
5757 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5758 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5759 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5760 %}
5761
5762 ins_pipe(pipe_slow);
5763 %}
5764
5765 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5766 %{
5767 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5768
5769 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5770
5771 ins_cost(2 * VOLATILE_REF_COST);
5772
5773 format %{
5774 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5775 %}
5776
5777 ins_encode %{
5778 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5779 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5780 %}
5781
5782 ins_pipe(pipe_slow);
5783 %}
5784
5785 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5786 %{
5787 predicate(needs_acquiring_load_reserved(n));
5788
5789 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5790
5791 ins_cost(2 * VOLATILE_REF_COST);
5792
5793 format %{
5794 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5795 %}
5796
5797 ins_encode %{
5798 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5799 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5800 %}
5801
5802 ins_pipe(pipe_slow);
5803 %}
5804
5805 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5806 %{
5807 predicate(needs_acquiring_load_reserved(n));
5808
5809 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5810
5811 ins_cost(2 * VOLATILE_REF_COST);
5812
5813 format %{
5814 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5815 %}
5816
5817 ins_encode %{
5818 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5819 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5820 %}
5821
5822 ins_pipe(pipe_slow);
5823 %}
5824
5825 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5826 %{
5827 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5828
5829 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5830
5831 ins_cost(2 * VOLATILE_REF_COST);
5832
5833 format %{
5834 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5835 %}
5836
5837 ins_encode %{
5838 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5839 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5840 %}
5841
5842 ins_pipe(pipe_slow);
5843 %}
5844
5845 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5846 %{
5847 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5848
5849 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5850
5851 ins_cost(2 * VOLATILE_REF_COST);
5852
5853 format %{
5854 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5855 %}
5856
5857 ins_encode %{
5858 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5859 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5860 %}
5861
5862 ins_pipe(pipe_slow);
5863 %}
5864
5865 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5866 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5867 %{
5868 predicate(!UseZabha || !UseZacas);
5869
5870 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5871
5872 ins_cost(2 * VOLATILE_REF_COST);
5873
5874 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5875
5876 format %{
5877 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5878 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5879 %}
5880
5881 ins_encode %{
5882 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5883 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5884 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5885 %}
5886
5887 ins_pipe(pipe_slow);
5888 %}
5889
5890 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5891 %{
5892 predicate(UseZabha && UseZacas);
5893
5894 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5895
5896 ins_cost(2 * VOLATILE_REF_COST);
5897
5898 format %{
5899 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5900 "# $res == 1 when success, #@weakCompareAndSwapB"
5901 %}
5902
5903 ins_encode %{
5904 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5905 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5906 %}
5907
5908 ins_pipe(pipe_slow);
5909 %}
5910
5911 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5912 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5913 %{
5914 predicate(!UseZabha || !UseZacas);
5915
5916 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5917
5918 ins_cost(2 * VOLATILE_REF_COST);
5919
5920 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5921
5922 format %{
5923 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5924 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5925 %}
5926
5927 ins_encode %{
5928 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5929 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5930 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5931 %}
5932
5933 ins_pipe(pipe_slow);
5934 %}
5935
5936 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5937 %{
5938 predicate(UseZabha && UseZacas);
5939
5940 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5941
5942 ins_cost(2 * VOLATILE_REF_COST);
5943
5944 format %{
5945 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5946 "# $res == 1 when success, #@weakCompareAndSwapS"
5947 %}
5948
5949 ins_encode %{
5950 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5951 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5952 %}
5953
5954 ins_pipe(pipe_slow);
5955 %}
5956
5957 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5958 %{
5959 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5960
5961 ins_cost(2 * VOLATILE_REF_COST);
5962
5963 format %{
5964 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5965 "# $res == 1 when success, #@weakCompareAndSwapI"
5966 %}
5967
5968 ins_encode %{
5969 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5970 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5971 %}
5972
5973 ins_pipe(pipe_slow);
5974 %}
5975
5976 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5977 %{
5978 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5979
5980 ins_cost(2 * VOLATILE_REF_COST);
5981
5982 format %{
5983 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5984 "# $res == 1 when success, #@weakCompareAndSwapL"
5985 %}
5986
5987 ins_encode %{
5988 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5989 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5990 %}
5991
5992 ins_pipe(pipe_slow);
5993 %}
5994
5995 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5996 %{
5997 predicate(n->as_LoadStore()->barrier_data() == 0);
5998
5999 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6000
6001 ins_cost(2 * VOLATILE_REF_COST);
6002
6003 format %{
6004 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6005 "# $res == 1 when success, #@weakCompareAndSwapN"
6006 %}
6007
6008 ins_encode %{
6009 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6010 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6011 %}
6012
6013 ins_pipe(pipe_slow);
6014 %}
6015
6016 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6017 %{
6018 predicate(n->as_LoadStore()->barrier_data() == 0);
6019
6020 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6021
6022 ins_cost(2 * VOLATILE_REF_COST);
6023
6024 format %{
6025 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6026 "# $res == 1 when success, #@weakCompareAndSwapP"
6027 %}
6028
6029 ins_encode %{
6030 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6031 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6032 %}
6033
6034 ins_pipe(pipe_slow);
6035 %}
6036
6037 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6038 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6039 %{
6040 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6041
6042 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6043
6044 ins_cost(2 * VOLATILE_REF_COST);
6045
6046 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6047
6048 format %{
6049 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6050 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6051 %}
6052
6053 ins_encode %{
6054 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6055 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6056 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6057 %}
6058
6059 ins_pipe(pipe_slow);
6060 %}
6061
6062 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6063 %{
6064 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6065
6066 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6067
6068 ins_cost(2 * VOLATILE_REF_COST);
6069
6070 format %{
6071 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6072 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6073 %}
6074
6075 ins_encode %{
6076 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6077 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6078 %}
6079
6080 ins_pipe(pipe_slow);
6081 %}
6082
6083 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6084 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6085 %{
6086 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6087
6088 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6089
6090 ins_cost(2 * VOLATILE_REF_COST);
6091
6092 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6093
6094 format %{
6095 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6096 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6097 %}
6098
6099 ins_encode %{
6100 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6101 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6102 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6103 %}
6104
6105 ins_pipe(pipe_slow);
6106 %}
6107
6108 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6109 %{
6110 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6111
6112 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6113
6114 ins_cost(2 * VOLATILE_REF_COST);
6115
6116 format %{
6117 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6118 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6119 %}
6120
6121 ins_encode %{
6122 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6123 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6124 %}
6125
6126 ins_pipe(pipe_slow);
6127 %}
6128
6129 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6130 %{
6131 predicate(needs_acquiring_load_reserved(n));
6132
6133 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6134
6135 ins_cost(2 * VOLATILE_REF_COST);
6136
6137 format %{
6138 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6139 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6140 %}
6141
6142 ins_encode %{
6143 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6144 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6145 %}
6146
6147 ins_pipe(pipe_slow);
6148 %}
6149
6150 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6151 %{
6152 predicate(needs_acquiring_load_reserved(n));
6153
6154 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6155
6156 ins_cost(2 * VOLATILE_REF_COST);
6157
6158 format %{
6159 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6160 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6161 %}
6162
6163 ins_encode %{
6164 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6165 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6166 %}
6167
6168 ins_pipe(pipe_slow);
6169 %}
6170
6171 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6172 %{
6173 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6174
6175 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6176
6177 ins_cost(2 * VOLATILE_REF_COST);
6178
6179 format %{
6180 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6181 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6182 %}
6183
6184 ins_encode %{
6185 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6186 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6187 %}
6188
6189 ins_pipe(pipe_slow);
6190 %}
6191
6192 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6193 %{
6194 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6195
6196 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6197
6198 ins_cost(2 * VOLATILE_REF_COST);
6199
6200 format %{
6201 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6202 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6203 %}
6204
6205 ins_encode %{
6206 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6207 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6208 %}
6209
6210 ins_pipe(pipe_slow);
6211 %}
6212
6213 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6214 %{
6215 match(Set prev (GetAndSetI mem newv));
6216
6217 ins_cost(ALU_COST);
6218
6219 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6220
6221 ins_encode %{
6222 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6223 %}
6224
6225 ins_pipe(pipe_serial);
6226 %}
6227
6228 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6229 %{
6230 match(Set prev (GetAndSetL mem newv));
6231
6232 ins_cost(ALU_COST);
6233
6234 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6235
6236 ins_encode %{
6237 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6238 %}
6239
6240 ins_pipe(pipe_serial);
6241 %}
6242
6243 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6244 %{
6245 predicate(n->as_LoadStore()->barrier_data() == 0);
6246
6247 match(Set prev (GetAndSetN mem newv));
6248
6249 ins_cost(ALU_COST);
6250
6251 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6252
6253 ins_encode %{
6254 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6255 %}
6256
6257 ins_pipe(pipe_serial);
6258 %}
6259
6260 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6261 %{
6262 predicate(n->as_LoadStore()->barrier_data() == 0);
6263 match(Set prev (GetAndSetP mem newv));
6264
6265 ins_cost(ALU_COST);
6266
6267 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6268
6269 ins_encode %{
6270 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6271 %}
6272
6273 ins_pipe(pipe_serial);
6274 %}
6275
6276 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6277 %{
6278 predicate(needs_acquiring_load_reserved(n));
6279
6280 match(Set prev (GetAndSetI mem newv));
6281
6282 ins_cost(ALU_COST);
6283
6284 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6285
6286 ins_encode %{
6287 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6288 %}
6289
6290 ins_pipe(pipe_serial);
6291 %}
6292
6293 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6294 %{
6295 predicate(needs_acquiring_load_reserved(n));
6296
6297 match(Set prev (GetAndSetL mem newv));
6298
6299 ins_cost(ALU_COST);
6300
6301 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6302
6303 ins_encode %{
6304 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6305 %}
6306
6307 ins_pipe(pipe_serial);
6308 %}
6309
6310 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6311 %{
6312 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6313
6314 match(Set prev (GetAndSetN mem newv));
6315
6316 ins_cost(ALU_COST);
6317
6318 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6319
6320 ins_encode %{
6321 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6322 %}
6323
6324 ins_pipe(pipe_serial);
6325 %}
6326
6327 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6328 %{
6329 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6330
6331 match(Set prev (GetAndSetP mem newv));
6332
6333 ins_cost(ALU_COST);
6334
6335 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6336
6337 ins_encode %{
6338 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6339 %}
6340
6341 ins_pipe(pipe_serial);
6342 %}
6343
6344 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6345 %{
6346 match(Set newval (GetAndAddL mem incr));
6347
6348 ins_cost(ALU_COST);
6349
6350 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6351
6352 ins_encode %{
6353 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6354 %}
6355
6356 ins_pipe(pipe_serial);
6357 %}
6358
6359 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6360 %{
6361 predicate(n->as_LoadStore()->result_not_used());
6362
6363 match(Set dummy (GetAndAddL mem incr));
6364
6365 ins_cost(ALU_COST);
6366
6367 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6368
6369 ins_encode %{
6370 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6371 %}
6372
6373 ins_pipe(pipe_serial);
6374 %}
6375
6376 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6377 %{
6378 match(Set newval (GetAndAddL mem incr));
6379
6380 ins_cost(ALU_COST);
6381
6382 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6383
6384 ins_encode %{
6385 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6386 %}
6387
6388 ins_pipe(pipe_serial);
6389 %}
6390
6391 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6392 %{
6393 predicate(n->as_LoadStore()->result_not_used());
6394
6395 match(Set dummy (GetAndAddL mem incr));
6396
6397 ins_cost(ALU_COST);
6398
6399 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6400
6401 ins_encode %{
6402 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6403 %}
6404
6405 ins_pipe(pipe_serial);
6406 %}
6407
6408 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6409 %{
6410 match(Set newval (GetAndAddI mem incr));
6411
6412 ins_cost(ALU_COST);
6413
6414 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6415
6416 ins_encode %{
6417 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6418 %}
6419
6420 ins_pipe(pipe_serial);
6421 %}
6422
6423 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6424 %{
6425 predicate(n->as_LoadStore()->result_not_used());
6426
6427 match(Set dummy (GetAndAddI mem incr));
6428
6429 ins_cost(ALU_COST);
6430
6431 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6432
6433 ins_encode %{
6434 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6435 %}
6436
6437 ins_pipe(pipe_serial);
6438 %}
6439
6440 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6441 %{
6442 match(Set newval (GetAndAddI mem incr));
6443
6444 ins_cost(ALU_COST);
6445
6446 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6447
6448 ins_encode %{
6449 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6450 %}
6451
6452 ins_pipe(pipe_serial);
6453 %}
6454
6455 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6456 %{
6457 predicate(n->as_LoadStore()->result_not_used());
6458
6459 match(Set dummy (GetAndAddI mem incr));
6460
6461 ins_cost(ALU_COST);
6462
6463 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6464
6465 ins_encode %{
6466 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6467 %}
6468
6469 ins_pipe(pipe_serial);
6470 %}
6471
6472 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6473 %{
6474 predicate(needs_acquiring_load_reserved(n));
6475
6476 match(Set newval (GetAndAddL mem incr));
6477
6478 ins_cost(ALU_COST);
6479
6480 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6481
6482 ins_encode %{
6483 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6484 %}
6485
6486 ins_pipe(pipe_serial);
6487 %}
6488
6489 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6490 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6491
6492 match(Set dummy (GetAndAddL mem incr));
6493
6494 ins_cost(ALU_COST);
6495
6496 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6497
6498 ins_encode %{
6499 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6500 %}
6501
6502 ins_pipe(pipe_serial);
6503 %}
6504
6505 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6506 %{
6507 predicate(needs_acquiring_load_reserved(n));
6508
6509 match(Set newval (GetAndAddL mem incr));
6510
6511 ins_cost(ALU_COST);
6512
6513 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6514
6515 ins_encode %{
6516 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6517 %}
6518
6519 ins_pipe(pipe_serial);
6520 %}
6521
6522 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6523 %{
6524 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6525
6526 match(Set dummy (GetAndAddL mem incr));
6527
6528 ins_cost(ALU_COST);
6529
6530 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6531
6532 ins_encode %{
6533 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6534 %}
6535
6536 ins_pipe(pipe_serial);
6537 %}
6538
6539 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6540 %{
6541 predicate(needs_acquiring_load_reserved(n));
6542
6543 match(Set newval (GetAndAddI mem incr));
6544
6545 ins_cost(ALU_COST);
6546
6547 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6548
6549 ins_encode %{
6550 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6551 %}
6552
6553 ins_pipe(pipe_serial);
6554 %}
6555
6556 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6557 %{
6558 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6559
6560 match(Set dummy (GetAndAddI mem incr));
6561
6562 ins_cost(ALU_COST);
6563
6564 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6565
6566 ins_encode %{
6567 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6568 %}
6569
6570 ins_pipe(pipe_serial);
6571 %}
6572
6573 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6574 %{
6575 predicate(needs_acquiring_load_reserved(n));
6576
6577 match(Set newval (GetAndAddI mem incr));
6578
6579 ins_cost(ALU_COST);
6580
6581 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6582
6583 ins_encode %{
6584 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6585 %}
6586
6587 ins_pipe(pipe_serial);
6588 %}
6589
6590 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6591 %{
6592 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6593
6594 match(Set dummy (GetAndAddI mem incr));
6595
6596 ins_cost(ALU_COST);
6597
6598 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6599
6600 ins_encode %{
6601 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6602 %}
6603
6604 ins_pipe(pipe_serial);
6605 %}
6606
6607 // ============================================================================
6608 // Arithmetic Instructions
6609 //
6610
6611 // Integer Addition
6612
6613 // TODO
6614 // these currently employ operations which do not set CR and hence are
6615 // not flagged as killing CR but we would like to isolate the cases
6616 // where we want to set flags from those where we don't. need to work
6617 // out how to do that.
6618 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6619 match(Set dst (AddI src1 src2));
6620
6621 ins_cost(ALU_COST);
6622 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6623
6624 ins_encode %{
6625 __ addw(as_Register($dst$$reg),
6626 as_Register($src1$$reg),
6627 as_Register($src2$$reg));
6628 %}
6629
6630 ins_pipe(ialu_reg_reg);
6631 %}
6632
6633 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6634 match(Set dst (AddI src1 src2));
6635
6636 ins_cost(ALU_COST);
6637 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6638
6639 ins_encode %{
6640 __ addiw(as_Register($dst$$reg),
6641 as_Register($src1$$reg),
6642 $src2$$constant);
6643 %}
6644
6645 ins_pipe(ialu_reg_imm);
6646 %}
6647
6648 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6649 match(Set dst (AddI (ConvL2I src1) src2));
6650
6651 ins_cost(ALU_COST);
6652 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6653
6654 ins_encode %{
6655 __ addiw(as_Register($dst$$reg),
6656 as_Register($src1$$reg),
6657 $src2$$constant);
6658 %}
6659
6660 ins_pipe(ialu_reg_imm);
6661 %}
6662
6663 // Pointer Addition
6664 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6665 match(Set dst (AddP src1 src2));
6666
6667 ins_cost(ALU_COST);
6668 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6669
6670 ins_encode %{
6671 __ add(as_Register($dst$$reg),
6672 as_Register($src1$$reg),
6673 as_Register($src2$$reg));
6674 %}
6675
6676 ins_pipe(ialu_reg_reg);
6677 %}
6678
6679 // If we shift more than 32 bits, we need not convert I2L.
6680 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6681 match(Set dst (LShiftL (ConvI2L src) scale));
6682 ins_cost(ALU_COST);
6683 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6684
6685 ins_encode %{
6686 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6687 %}
6688
6689 ins_pipe(ialu_reg_shift);
6690 %}
6691
6692 // Pointer Immediate Addition
6693 // n.b. this needs to be more expensive than using an indirect memory
6694 // operand
6695 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6696 match(Set dst (AddP src1 src2));
6697 ins_cost(ALU_COST);
6698 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6699
6700 ins_encode %{
6701 __ addi(as_Register($dst$$reg),
6702 as_Register($src1$$reg),
6703 $src2$$constant);
6704 %}
6705
6706 ins_pipe(ialu_reg_imm);
6707 %}
6708
6709 // Long Addition
6710 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6711 match(Set dst (AddL src1 src2));
6712 ins_cost(ALU_COST);
6713 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6714
6715 ins_encode %{
6716 __ add(as_Register($dst$$reg),
6717 as_Register($src1$$reg),
6718 as_Register($src2$$reg));
6719 %}
6720
6721 ins_pipe(ialu_reg_reg);
6722 %}
6723
6724 // No constant pool entries requiredLong Immediate Addition.
6725 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6726 match(Set dst (AddL src1 src2));
6727 ins_cost(ALU_COST);
6728 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6729
6730 ins_encode %{
6731 // src2 is imm, so actually call the addi
6732 __ addi(as_Register($dst$$reg),
6733 as_Register($src1$$reg),
6734 $src2$$constant);
6735 %}
6736
6737 ins_pipe(ialu_reg_imm);
6738 %}
6739
6740 // Integer Subtraction
6741 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6742 match(Set dst (SubI src1 src2));
6743
6744 ins_cost(ALU_COST);
6745 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6746
6747 ins_encode %{
6748 __ subw(as_Register($dst$$reg),
6749 as_Register($src1$$reg),
6750 as_Register($src2$$reg));
6751 %}
6752
6753 ins_pipe(ialu_reg_reg);
6754 %}
6755
6756 // Immediate Subtraction
6757 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6758 match(Set dst (SubI src1 src2));
6759
6760 ins_cost(ALU_COST);
6761 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6762
6763 ins_encode %{
6764 // src2 is imm, so actually call the addiw
6765 __ subiw(as_Register($dst$$reg),
6766 as_Register($src1$$reg),
6767 $src2$$constant);
6768 %}
6769
6770 ins_pipe(ialu_reg_imm);
6771 %}
6772
6773 // Long Subtraction
6774 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6775 match(Set dst (SubL src1 src2));
6776 ins_cost(ALU_COST);
6777 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6778
6779 ins_encode %{
6780 __ sub(as_Register($dst$$reg),
6781 as_Register($src1$$reg),
6782 as_Register($src2$$reg));
6783 %}
6784
6785 ins_pipe(ialu_reg_reg);
6786 %}
6787
6788 // No constant pool entries requiredLong Immediate Subtraction.
6789 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6790 match(Set dst (SubL src1 src2));
6791 ins_cost(ALU_COST);
6792 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6793
6794 ins_encode %{
6795 // src2 is imm, so actually call the addi
6796 __ subi(as_Register($dst$$reg),
6797 as_Register($src1$$reg),
6798 $src2$$constant);
6799 %}
6800
6801 ins_pipe(ialu_reg_imm);
6802 %}
6803
6804 // Integer Negation (special case for sub)
6805
6806 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6807 match(Set dst (SubI zero src));
6808 ins_cost(ALU_COST);
6809 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6810
6811 ins_encode %{
6812 // actually call the subw
6813 __ negw(as_Register($dst$$reg),
6814 as_Register($src$$reg));
6815 %}
6816
6817 ins_pipe(ialu_reg);
6818 %}
6819
6820 // Long Negation
6821
6822 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6823 match(Set dst (SubL zero src));
6824 ins_cost(ALU_COST);
6825 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6826
6827 ins_encode %{
6828 // actually call the sub
6829 __ neg(as_Register($dst$$reg),
6830 as_Register($src$$reg));
6831 %}
6832
6833 ins_pipe(ialu_reg);
6834 %}
6835
6836 // Integer Multiply
6837
6838 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6839 match(Set dst (MulI src1 src2));
6840 ins_cost(IMUL_COST);
6841 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6842
6843 //this means 2 word multi, and no sign extend to 64 bits
6844 ins_encode %{
6845 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6846 __ mulw(as_Register($dst$$reg),
6847 as_Register($src1$$reg),
6848 as_Register($src2$$reg));
6849 %}
6850
6851 ins_pipe(imul_reg_reg);
6852 %}
6853
6854 // Long Multiply
6855
6856 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6857 match(Set dst (MulL src1 src2));
6858 ins_cost(IMUL_COST);
6859 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6860
6861 ins_encode %{
6862 __ mul(as_Register($dst$$reg),
6863 as_Register($src1$$reg),
6864 as_Register($src2$$reg));
6865 %}
6866
6867 ins_pipe(lmul_reg_reg);
6868 %}
6869
6870 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6871 %{
6872 match(Set dst (MulHiL src1 src2));
6873 ins_cost(IMUL_COST);
6874 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6875
6876 ins_encode %{
6877 __ mulh(as_Register($dst$$reg),
6878 as_Register($src1$$reg),
6879 as_Register($src2$$reg));
6880 %}
6881
6882 ins_pipe(lmul_reg_reg);
6883 %}
6884
6885 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6886 %{
6887 match(Set dst (UMulHiL src1 src2));
6888 ins_cost(IMUL_COST);
6889 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6890
6891 ins_encode %{
6892 __ mulhu(as_Register($dst$$reg),
6893 as_Register($src1$$reg),
6894 as_Register($src2$$reg));
6895 %}
6896
6897 ins_pipe(lmul_reg_reg);
6898 %}
6899
6900 // Integer Divide
6901
6902 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6903 match(Set dst (DivI src1 src2));
6904 ins_cost(IDIVSI_COST);
6905 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6906
6907 ins_encode %{
6908 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6909 %}
6910 ins_pipe(idiv_reg_reg);
6911 %}
6912
6913 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6914 match(Set dst (UDivI src1 src2));
6915 ins_cost(IDIVSI_COST);
6916 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6917
6918 ins_encode %{
6919 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6920 %}
6921 ins_pipe(idiv_reg_reg);
6922 %}
6923
6924 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6925 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6926 ins_cost(ALU_COST);
6927 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6928
6929 ins_encode %{
6930 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6931 %}
6932 ins_pipe(ialu_reg_shift);
6933 %}
6934
6935 // Long Divide
6936
6937 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6938 match(Set dst (DivL src1 src2));
6939 ins_cost(IDIVDI_COST);
6940 format %{ "div $dst, $src1, $src2\t#@divL" %}
6941
6942 ins_encode %{
6943 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6944 %}
6945 ins_pipe(ldiv_reg_reg);
6946 %}
6947
6948 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6949 match(Set dst (UDivL src1 src2));
6950 ins_cost(IDIVDI_COST);
6951
6952 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6953
6954 ins_encode %{
6955 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6956 %}
6957 ins_pipe(ldiv_reg_reg);
6958 %}
6959
6960 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6961 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6962 ins_cost(ALU_COST);
6963 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6964
6965 ins_encode %{
6966 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6967 %}
6968 ins_pipe(ialu_reg_shift);
6969 %}
6970
6971 // Integer Remainder
6972
6973 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6974 match(Set dst (ModI src1 src2));
6975 ins_cost(IDIVSI_COST);
6976 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6977
6978 ins_encode %{
6979 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6980 %}
6981 ins_pipe(ialu_reg_reg);
6982 %}
6983
6984 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6985 match(Set dst (UModI src1 src2));
6986 ins_cost(IDIVSI_COST);
6987 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
6988
6989 ins_encode %{
6990 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6991 %}
6992 ins_pipe(ialu_reg_reg);
6993 %}
6994
6995 // Long Remainder
6996
6997 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6998 match(Set dst (ModL src1 src2));
6999 ins_cost(IDIVDI_COST);
7000 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7001
7002 ins_encode %{
7003 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7004 %}
7005 ins_pipe(ialu_reg_reg);
7006 %}
7007
7008 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7009 match(Set dst (UModL src1 src2));
7010 ins_cost(IDIVDI_COST);
7011 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7012
7013 ins_encode %{
7014 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7015 %}
7016 ins_pipe(ialu_reg_reg);
7017 %}
7018
7019 // Integer Shifts
7020
7021 // Shift Left Register
7022 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7023 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7024 match(Set dst (LShiftI src1 src2));
7025 ins_cost(ALU_COST);
7026 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7027
7028 ins_encode %{
7029 __ sllw(as_Register($dst$$reg),
7030 as_Register($src1$$reg),
7031 as_Register($src2$$reg));
7032 %}
7033
7034 ins_pipe(ialu_reg_reg_vshift);
7035 %}
7036
7037 // Shift Left Immediate
7038 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7039 match(Set dst (LShiftI src1 src2));
7040 ins_cost(ALU_COST);
7041 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7042
7043 ins_encode %{
7044 // the shift amount is encoded in the lower
7045 // 5 bits of the I-immediate field for RV32I
7046 __ slliw(as_Register($dst$$reg),
7047 as_Register($src1$$reg),
7048 (unsigned) $src2$$constant & 0x1f);
7049 %}
7050
7051 ins_pipe(ialu_reg_shift);
7052 %}
7053
7054 // Shift Right Logical Register
7055 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7056 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7057 match(Set dst (URShiftI src1 src2));
7058 ins_cost(ALU_COST);
7059 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7060
7061 ins_encode %{
7062 __ srlw(as_Register($dst$$reg),
7063 as_Register($src1$$reg),
7064 as_Register($src2$$reg));
7065 %}
7066
7067 ins_pipe(ialu_reg_reg_vshift);
7068 %}
7069
7070 // Shift Right Logical Immediate
7071 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7072 match(Set dst (URShiftI src1 src2));
7073 ins_cost(ALU_COST);
7074 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7075
7076 ins_encode %{
7077 // the shift amount is encoded in the lower
7078 // 6 bits of the I-immediate field for RV64I
7079 __ srliw(as_Register($dst$$reg),
7080 as_Register($src1$$reg),
7081 (unsigned) $src2$$constant & 0x1f);
7082 %}
7083
7084 ins_pipe(ialu_reg_shift);
7085 %}
7086
7087 // Shift Right Arithmetic Register
7088 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7089 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7090 match(Set dst (RShiftI src1 src2));
7091 ins_cost(ALU_COST);
7092 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7093
7094 ins_encode %{
7095 // riscv will sign-ext dst high 32 bits
7096 __ sraw(as_Register($dst$$reg),
7097 as_Register($src1$$reg),
7098 as_Register($src2$$reg));
7099 %}
7100
7101 ins_pipe(ialu_reg_reg_vshift);
7102 %}
7103
7104 // Shift Right Arithmetic Immediate
7105 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7106 match(Set dst (RShiftI src1 src2));
7107 ins_cost(ALU_COST);
7108 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7109
7110 ins_encode %{
7111 // riscv will sign-ext dst high 32 bits
7112 __ sraiw(as_Register($dst$$reg),
7113 as_Register($src1$$reg),
7114 (unsigned) $src2$$constant & 0x1f);
7115 %}
7116
7117 ins_pipe(ialu_reg_shift);
7118 %}
7119
7120 // Long Shifts
7121
7122 // Shift Left Register
7123 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7124 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7125 match(Set dst (LShiftL src1 src2));
7126
7127 ins_cost(ALU_COST);
7128 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7129
7130 ins_encode %{
7131 __ sll(as_Register($dst$$reg),
7132 as_Register($src1$$reg),
7133 as_Register($src2$$reg));
7134 %}
7135
7136 ins_pipe(ialu_reg_reg_vshift);
7137 %}
7138
7139 // Shift Left Immediate
7140 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7141 match(Set dst (LShiftL src1 src2));
7142
7143 ins_cost(ALU_COST);
7144 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7145
7146 ins_encode %{
7147 // the shift amount is encoded in the lower
7148 // 6 bits of the I-immediate field for RV64I
7149 __ slli(as_Register($dst$$reg),
7150 as_Register($src1$$reg),
7151 (unsigned) $src2$$constant & 0x3f);
7152 %}
7153
7154 ins_pipe(ialu_reg_shift);
7155 %}
7156
7157 // Shift Right Logical Register
7158 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7159 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7160 match(Set dst (URShiftL src1 src2));
7161
7162 ins_cost(ALU_COST);
7163 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7164
7165 ins_encode %{
7166 __ srl(as_Register($dst$$reg),
7167 as_Register($src1$$reg),
7168 as_Register($src2$$reg));
7169 %}
7170
7171 ins_pipe(ialu_reg_reg_vshift);
7172 %}
7173
7174 // Shift Right Logical Immediate
7175 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7176 match(Set dst (URShiftL src1 src2));
7177
7178 ins_cost(ALU_COST);
7179 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7180
7181 ins_encode %{
7182 // the shift amount is encoded in the lower
7183 // 6 bits of the I-immediate field for RV64I
7184 __ srli(as_Register($dst$$reg),
7185 as_Register($src1$$reg),
7186 (unsigned) $src2$$constant & 0x3f);
7187 %}
7188
7189 ins_pipe(ialu_reg_shift);
7190 %}
7191
7192 // A special-case pattern for card table stores.
7193 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7194 match(Set dst (URShiftL (CastP2X src1) src2));
7195
7196 ins_cost(ALU_COST);
7197 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7198
7199 ins_encode %{
7200 // the shift amount is encoded in the lower
7201 // 6 bits of the I-immediate field for RV64I
7202 __ srli(as_Register($dst$$reg),
7203 as_Register($src1$$reg),
7204 (unsigned) $src2$$constant & 0x3f);
7205 %}
7206
7207 ins_pipe(ialu_reg_shift);
7208 %}
7209
7210 // Shift Right Arithmetic Register
7211 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7212 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7213 match(Set dst (RShiftL src1 src2));
7214
7215 ins_cost(ALU_COST);
7216 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7217
7218 ins_encode %{
7219 __ sra(as_Register($dst$$reg),
7220 as_Register($src1$$reg),
7221 as_Register($src2$$reg));
7222 %}
7223
7224 ins_pipe(ialu_reg_reg_vshift);
7225 %}
7226
7227 // Shift Right Arithmetic Immediate
7228 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7229 match(Set dst (RShiftL src1 src2));
7230
7231 ins_cost(ALU_COST);
7232 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7233
7234 ins_encode %{
7235 // the shift amount is encoded in the lower
7236 // 6 bits of the I-immediate field for RV64I
7237 __ srai(as_Register($dst$$reg),
7238 as_Register($src1$$reg),
7239 (unsigned) $src2$$constant & 0x3f);
7240 %}
7241
7242 ins_pipe(ialu_reg_shift);
7243 %}
7244
7245 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7246 match(Set dst (XorI src1 m1));
7247 ins_cost(ALU_COST);
7248 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7249
7250 ins_encode %{
7251 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7252 %}
7253
7254 ins_pipe(ialu_reg_imm);
7255 %}
7256
7257 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7258 match(Set dst (XorL src1 m1));
7259 ins_cost(ALU_COST);
7260 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7261
7262 ins_encode %{
7263 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7264 %}
7265
7266 ins_pipe(ialu_reg_imm);
7267 %}
7268
7269
7270 // ============================================================================
7271 // Floating Point Arithmetic Instructions
7272
7273 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7274 match(Set dst (AddF src1 src2));
7275
7276 ins_cost(DEFAULT_COST * 5);
7277 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7278
7279 ins_encode %{
7280 __ fadd_s(as_FloatRegister($dst$$reg),
7281 as_FloatRegister($src1$$reg),
7282 as_FloatRegister($src2$$reg));
7283 %}
7284
7285 ins_pipe(fp_dop_reg_reg_s);
7286 %}
7287
7288 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7289 match(Set dst (AddD src1 src2));
7290
7291 ins_cost(DEFAULT_COST * 5);
7292 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7293
7294 ins_encode %{
7295 __ fadd_d(as_FloatRegister($dst$$reg),
7296 as_FloatRegister($src1$$reg),
7297 as_FloatRegister($src2$$reg));
7298 %}
7299
7300 ins_pipe(fp_dop_reg_reg_d);
7301 %}
7302
7303 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7304 match(Set dst (SubF src1 src2));
7305
7306 ins_cost(DEFAULT_COST * 5);
7307 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7308
7309 ins_encode %{
7310 __ fsub_s(as_FloatRegister($dst$$reg),
7311 as_FloatRegister($src1$$reg),
7312 as_FloatRegister($src2$$reg));
7313 %}
7314
7315 ins_pipe(fp_dop_reg_reg_s);
7316 %}
7317
7318 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7319 match(Set dst (SubD src1 src2));
7320
7321 ins_cost(DEFAULT_COST * 5);
7322 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7323
7324 ins_encode %{
7325 __ fsub_d(as_FloatRegister($dst$$reg),
7326 as_FloatRegister($src1$$reg),
7327 as_FloatRegister($src2$$reg));
7328 %}
7329
7330 ins_pipe(fp_dop_reg_reg_d);
7331 %}
7332
7333 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7334 match(Set dst (MulF src1 src2));
7335
7336 ins_cost(FMUL_SINGLE_COST);
7337 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7338
7339 ins_encode %{
7340 __ fmul_s(as_FloatRegister($dst$$reg),
7341 as_FloatRegister($src1$$reg),
7342 as_FloatRegister($src2$$reg));
7343 %}
7344
7345 ins_pipe(fp_dop_reg_reg_s);
7346 %}
7347
7348 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7349 match(Set dst (MulD src1 src2));
7350
7351 ins_cost(FMUL_DOUBLE_COST);
7352 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7353
7354 ins_encode %{
7355 __ fmul_d(as_FloatRegister($dst$$reg),
7356 as_FloatRegister($src1$$reg),
7357 as_FloatRegister($src2$$reg));
7358 %}
7359
7360 ins_pipe(fp_dop_reg_reg_d);
7361 %}
7362
7363 // src1 * src2 + src3
7364 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7365 match(Set dst (FmaF src3 (Binary src1 src2)));
7366
7367 ins_cost(FMUL_SINGLE_COST);
7368 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7369
7370 ins_encode %{
7371 assert(UseFMA, "Needs FMA instructions support.");
7372 __ fmadd_s(as_FloatRegister($dst$$reg),
7373 as_FloatRegister($src1$$reg),
7374 as_FloatRegister($src2$$reg),
7375 as_FloatRegister($src3$$reg));
7376 %}
7377
7378 ins_pipe(pipe_class_default);
7379 %}
7380
7381 // src1 * src2 + src3
7382 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7383 match(Set dst (FmaD src3 (Binary src1 src2)));
7384
7385 ins_cost(FMUL_DOUBLE_COST);
7386 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7387
7388 ins_encode %{
7389 assert(UseFMA, "Needs FMA instructions support.");
7390 __ fmadd_d(as_FloatRegister($dst$$reg),
7391 as_FloatRegister($src1$$reg),
7392 as_FloatRegister($src2$$reg),
7393 as_FloatRegister($src3$$reg));
7394 %}
7395
7396 ins_pipe(pipe_class_default);
7397 %}
7398
7399 // src1 * src2 - src3
7400 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7401 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7402
7403 ins_cost(FMUL_SINGLE_COST);
7404 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7405
7406 ins_encode %{
7407 assert(UseFMA, "Needs FMA instructions support.");
7408 __ fmsub_s(as_FloatRegister($dst$$reg),
7409 as_FloatRegister($src1$$reg),
7410 as_FloatRegister($src2$$reg),
7411 as_FloatRegister($src3$$reg));
7412 %}
7413
7414 ins_pipe(pipe_class_default);
7415 %}
7416
7417 // src1 * src2 - src3
7418 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7419 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7420
7421 ins_cost(FMUL_DOUBLE_COST);
7422 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7423
7424 ins_encode %{
7425 assert(UseFMA, "Needs FMA instructions support.");
7426 __ fmsub_d(as_FloatRegister($dst$$reg),
7427 as_FloatRegister($src1$$reg),
7428 as_FloatRegister($src2$$reg),
7429 as_FloatRegister($src3$$reg));
7430 %}
7431
7432 ins_pipe(pipe_class_default);
7433 %}
7434
7435 // src1 * (-src2) + src3
7436 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7437 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7438 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7439
7440 ins_cost(FMUL_SINGLE_COST);
7441 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7442
7443 ins_encode %{
7444 assert(UseFMA, "Needs FMA instructions support.");
7445 __ fnmsub_s(as_FloatRegister($dst$$reg),
7446 as_FloatRegister($src1$$reg),
7447 as_FloatRegister($src2$$reg),
7448 as_FloatRegister($src3$$reg));
7449 %}
7450
7451 ins_pipe(pipe_class_default);
7452 %}
7453
7454 // src1 * (-src2) + src3
7455 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7456 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7457 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7458
7459 ins_cost(FMUL_DOUBLE_COST);
7460 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7461
7462 ins_encode %{
7463 assert(UseFMA, "Needs FMA instructions support.");
7464 __ fnmsub_d(as_FloatRegister($dst$$reg),
7465 as_FloatRegister($src1$$reg),
7466 as_FloatRegister($src2$$reg),
7467 as_FloatRegister($src3$$reg));
7468 %}
7469
7470 ins_pipe(pipe_class_default);
7471 %}
7472
7473 // src1 * (-src2) - src3
7474 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7475 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7476 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7477
7478 ins_cost(FMUL_SINGLE_COST);
7479 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7480
7481 ins_encode %{
7482 assert(UseFMA, "Needs FMA instructions support.");
7483 __ fnmadd_s(as_FloatRegister($dst$$reg),
7484 as_FloatRegister($src1$$reg),
7485 as_FloatRegister($src2$$reg),
7486 as_FloatRegister($src3$$reg));
7487 %}
7488
7489 ins_pipe(pipe_class_default);
7490 %}
7491
7492 // src1 * (-src2) - src3
7493 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7494 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7495 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7496
7497 ins_cost(FMUL_DOUBLE_COST);
7498 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7499
7500 ins_encode %{
7501 assert(UseFMA, "Needs FMA instructions support.");
7502 __ fnmadd_d(as_FloatRegister($dst$$reg),
7503 as_FloatRegister($src1$$reg),
7504 as_FloatRegister($src2$$reg),
7505 as_FloatRegister($src3$$reg));
7506 %}
7507
7508 ins_pipe(pipe_class_default);
7509 %}
7510
7511 // Math.max(FF)F
7512 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7513 predicate(!UseZfa);
7514 match(Set dst (MaxF src1 src2));
7515 effect(KILL cr);
7516
7517 format %{ "maxF $dst, $src1, $src2" %}
7518
7519 ins_encode %{
7520 __ minmax_fp(as_FloatRegister($dst$$reg),
7521 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7522 __ FLOAT_TYPE::single_precision, false /* is_min */);
7523 %}
7524
7525 ins_pipe(pipe_class_default);
7526 %}
7527
7528 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7529 predicate(UseZfa);
7530 match(Set dst (MaxF src1 src2));
7531
7532 format %{ "maxF $dst, $src1, $src2" %}
7533
7534 ins_encode %{
7535 __ fmaxm_s(as_FloatRegister($dst$$reg),
7536 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7537 %}
7538
7539 ins_pipe(pipe_class_default);
7540 %}
7541
7542 // Math.min(FF)F
7543 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7544 predicate(!UseZfa);
7545 match(Set dst (MinF src1 src2));
7546 effect(KILL cr);
7547
7548 format %{ "minF $dst, $src1, $src2" %}
7549
7550 ins_encode %{
7551 __ minmax_fp(as_FloatRegister($dst$$reg),
7552 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7553 __ FLOAT_TYPE::single_precision, true /* is_min */);
7554 %}
7555
7556 ins_pipe(pipe_class_default);
7557 %}
7558
7559 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7560 predicate(UseZfa);
7561 match(Set dst (MinF src1 src2));
7562
7563 format %{ "minF $dst, $src1, $src2" %}
7564
7565 ins_encode %{
7566 __ fminm_s(as_FloatRegister($dst$$reg),
7567 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7568 %}
7569
7570 ins_pipe(pipe_class_default);
7571 %}
7572
7573 // Math.max(DD)D
7574 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7575 predicate(!UseZfa);
7576 match(Set dst (MaxD src1 src2));
7577 effect(KILL cr);
7578
7579 format %{ "maxD $dst, $src1, $src2" %}
7580
7581 ins_encode %{
7582 __ minmax_fp(as_FloatRegister($dst$$reg),
7583 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7584 __ FLOAT_TYPE::double_precision, false /* is_min */);
7585 %}
7586
7587 ins_pipe(pipe_class_default);
7588 %}
7589
7590 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7591 predicate(UseZfa);
7592 match(Set dst (MaxD src1 src2));
7593
7594 format %{ "maxD $dst, $src1, $src2" %}
7595
7596 ins_encode %{
7597 __ fmaxm_d(as_FloatRegister($dst$$reg),
7598 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7599 %}
7600
7601 ins_pipe(pipe_class_default);
7602 %}
7603
7604 // Math.min(DD)D
7605 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7606 predicate(!UseZfa);
7607 match(Set dst (MinD src1 src2));
7608 effect(KILL cr);
7609
7610 format %{ "minD $dst, $src1, $src2" %}
7611
7612 ins_encode %{
7613 __ minmax_fp(as_FloatRegister($dst$$reg),
7614 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7615 __ FLOAT_TYPE::double_precision, true /* is_min */);
7616 %}
7617
7618 ins_pipe(pipe_class_default);
7619 %}
7620
7621 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7622 predicate(UseZfa);
7623 match(Set dst (MinD src1 src2));
7624
7625 format %{ "minD $dst, $src1, $src2" %}
7626
7627 ins_encode %{
7628 __ fminm_d(as_FloatRegister($dst$$reg),
7629 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7630 %}
7631
7632 ins_pipe(pipe_class_default);
7633 %}
7634
7635 // Float.isInfinite
7636 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7637 %{
7638 match(Set dst (IsInfiniteF src));
7639
7640 format %{ "isInfinite $dst, $src" %}
7641 ins_encode %{
7642 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7643 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7644 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7645 %}
7646
7647 ins_pipe(pipe_class_default);
7648 %}
7649
7650 // Double.isInfinite
7651 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7652 %{
7653 match(Set dst (IsInfiniteD src));
7654
7655 format %{ "isInfinite $dst, $src" %}
7656 ins_encode %{
7657 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7658 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7659 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7660 %}
7661
7662 ins_pipe(pipe_class_default);
7663 %}
7664
7665 // Float.isFinite
7666 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7667 %{
7668 match(Set dst (IsFiniteF src));
7669
7670 format %{ "isFinite $dst, $src" %}
7671 ins_encode %{
7672 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7673 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7674 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7675 %}
7676
7677 ins_pipe(pipe_class_default);
7678 %}
7679
7680 // Double.isFinite
7681 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7682 %{
7683 match(Set dst (IsFiniteD src));
7684
7685 format %{ "isFinite $dst, $src" %}
7686 ins_encode %{
7687 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7688 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7689 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7690 %}
7691
7692 ins_pipe(pipe_class_default);
7693 %}
7694
7695 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7696 match(Set dst (DivF src1 src2));
7697
7698 ins_cost(FDIV_COST);
7699 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7700
7701 ins_encode %{
7702 __ fdiv_s(as_FloatRegister($dst$$reg),
7703 as_FloatRegister($src1$$reg),
7704 as_FloatRegister($src2$$reg));
7705 %}
7706
7707 ins_pipe(fp_div_s);
7708 %}
7709
7710 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7711 match(Set dst (DivD src1 src2));
7712
7713 ins_cost(FDIV_COST);
7714 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7715
7716 ins_encode %{
7717 __ fdiv_d(as_FloatRegister($dst$$reg),
7718 as_FloatRegister($src1$$reg),
7719 as_FloatRegister($src2$$reg));
7720 %}
7721
7722 ins_pipe(fp_div_d);
7723 %}
7724
7725 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7726 match(Set dst (NegF src));
7727
7728 ins_cost(XFER_COST);
7729 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7730
7731 ins_encode %{
7732 __ fneg_s(as_FloatRegister($dst$$reg),
7733 as_FloatRegister($src$$reg));
7734 %}
7735
7736 ins_pipe(fp_uop_s);
7737 %}
7738
7739 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7740 match(Set dst (NegD src));
7741
7742 ins_cost(XFER_COST);
7743 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7744
7745 ins_encode %{
7746 __ fneg_d(as_FloatRegister($dst$$reg),
7747 as_FloatRegister($src$$reg));
7748 %}
7749
7750 ins_pipe(fp_uop_d);
7751 %}
7752
7753 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7754 match(Set dst (AbsI src));
7755
7756 ins_cost(ALU_COST * 3);
7757 format %{
7758 "sraiw t0, $src, 0x1f\n\t"
7759 "addw $dst, $src, t0\n\t"
7760 "xorr $dst, $dst, t0\t#@absI_reg"
7761 %}
7762
7763 ins_encode %{
7764 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7765 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7766 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7767 %}
7768
7769 ins_pipe(pipe_class_default);
7770 %}
7771
7772 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7773 match(Set dst (AbsL src));
7774
7775 ins_cost(ALU_COST * 3);
7776 format %{
7777 "srai t0, $src, 0x3f\n\t"
7778 "add $dst, $src, t0\n\t"
7779 "xorr $dst, $dst, t0\t#@absL_reg"
7780 %}
7781
7782 ins_encode %{
7783 __ srai(t0, as_Register($src$$reg), 0x3f);
7784 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7785 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7786 %}
7787
7788 ins_pipe(pipe_class_default);
7789 %}
7790
7791 instruct absF_reg(fRegF dst, fRegF src) %{
7792 match(Set dst (AbsF src));
7793
7794 ins_cost(XFER_COST);
7795 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7796 ins_encode %{
7797 __ fabs_s(as_FloatRegister($dst$$reg),
7798 as_FloatRegister($src$$reg));
7799 %}
7800
7801 ins_pipe(fp_uop_s);
7802 %}
7803
7804 instruct absD_reg(fRegD dst, fRegD src) %{
7805 match(Set dst (AbsD src));
7806
7807 ins_cost(XFER_COST);
7808 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7809 ins_encode %{
7810 __ fabs_d(as_FloatRegister($dst$$reg),
7811 as_FloatRegister($src$$reg));
7812 %}
7813
7814 ins_pipe(fp_uop_d);
7815 %}
7816
7817 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7818 match(Set dst (SqrtF src));
7819
7820 ins_cost(FSQRT_COST);
7821 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7822 ins_encode %{
7823 __ fsqrt_s(as_FloatRegister($dst$$reg),
7824 as_FloatRegister($src$$reg));
7825 %}
7826
7827 ins_pipe(fp_sqrt_s);
7828 %}
7829
7830 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7831 match(Set dst (SqrtD src));
7832
7833 ins_cost(FSQRT_COST);
7834 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7835 ins_encode %{
7836 __ fsqrt_d(as_FloatRegister($dst$$reg),
7837 as_FloatRegister($src$$reg));
7838 %}
7839
7840 ins_pipe(fp_sqrt_d);
7841 %}
7842
7843 // Round Instruction
7844 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7845 match(Set dst (RoundDoubleMode src rmode));
7846 ins_cost(2 * XFER_COST + BRANCH_COST);
7847 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7848
7849 format %{ "RoundDoubleMode $src, $rmode" %}
7850 ins_encode %{
7851 __ round_double_mode(as_FloatRegister($dst$$reg),
7852 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7853 %}
7854 ins_pipe(pipe_class_default);
7855 %}
7856
7857 // Copysign and signum intrinsics
7858
7859 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7860 match(Set dst (CopySignD src1 (Binary src2 zero)));
7861 format %{ "CopySignD $dst $src1 $src2" %}
7862 ins_encode %{
7863 FloatRegister dst = as_FloatRegister($dst$$reg),
7864 src1 = as_FloatRegister($src1$$reg),
7865 src2 = as_FloatRegister($src2$$reg);
7866 __ fsgnj_d(dst, src1, src2);
7867 %}
7868 ins_pipe(fp_dop_reg_reg_d);
7869 %}
7870
7871 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7872 match(Set dst (CopySignF src1 src2));
7873 format %{ "CopySignF $dst $src1 $src2" %}
7874 ins_encode %{
7875 FloatRegister dst = as_FloatRegister($dst$$reg),
7876 src1 = as_FloatRegister($src1$$reg),
7877 src2 = as_FloatRegister($src2$$reg);
7878 __ fsgnj_s(dst, src1, src2);
7879 %}
7880 ins_pipe(fp_dop_reg_reg_s);
7881 %}
7882
7883 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7884 match(Set dst (SignumD dst (Binary zero one)));
7885 format %{ "signumD $dst, $dst" %}
7886 ins_encode %{
7887 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7888 %}
7889 ins_pipe(pipe_class_default);
7890 %}
7891
7892 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7893 match(Set dst (SignumF dst (Binary zero one)));
7894 format %{ "signumF $dst, $dst" %}
7895 ins_encode %{
7896 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7897 %}
7898 ins_pipe(pipe_class_default);
7899 %}
7900
7901 // Arithmetic Instructions End
7902
7903 // ============================================================================
7904 // Logical Instructions
7905
7906 // Register And
7907 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7908 match(Set dst (AndI src1 src2));
7909
7910 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7911
7912 ins_cost(ALU_COST);
7913 ins_encode %{
7914 __ andr(as_Register($dst$$reg),
7915 as_Register($src1$$reg),
7916 as_Register($src2$$reg));
7917 %}
7918
7919 ins_pipe(ialu_reg_reg);
7920 %}
7921
7922 // Immediate And
7923 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7924 match(Set dst (AndI src1 src2));
7925
7926 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7927
7928 ins_cost(ALU_COST);
7929 ins_encode %{
7930 __ andi(as_Register($dst$$reg),
7931 as_Register($src1$$reg),
7932 (int32_t)($src2$$constant));
7933 %}
7934
7935 ins_pipe(ialu_reg_imm);
7936 %}
7937
7938 // Register Or
7939 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7940 match(Set dst (OrI src1 src2));
7941
7942 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7943
7944 ins_cost(ALU_COST);
7945 ins_encode %{
7946 __ orr(as_Register($dst$$reg),
7947 as_Register($src1$$reg),
7948 as_Register($src2$$reg));
7949 %}
7950
7951 ins_pipe(ialu_reg_reg);
7952 %}
7953
7954 // Immediate Or
7955 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7956 match(Set dst (OrI src1 src2));
7957
7958 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7959
7960 ins_cost(ALU_COST);
7961 ins_encode %{
7962 __ ori(as_Register($dst$$reg),
7963 as_Register($src1$$reg),
7964 (int32_t)($src2$$constant));
7965 %}
7966
7967 ins_pipe(ialu_reg_imm);
7968 %}
7969
7970 // Register Xor
7971 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7972 match(Set dst (XorI src1 src2));
7973
7974 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7975
7976 ins_cost(ALU_COST);
7977 ins_encode %{
7978 __ xorr(as_Register($dst$$reg),
7979 as_Register($src1$$reg),
7980 as_Register($src2$$reg));
7981 %}
7982
7983 ins_pipe(ialu_reg_reg);
7984 %}
7985
7986 // Immediate Xor
7987 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7988 match(Set dst (XorI src1 src2));
7989
7990 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7991
7992 ins_cost(ALU_COST);
7993 ins_encode %{
7994 __ xori(as_Register($dst$$reg),
7995 as_Register($src1$$reg),
7996 (int32_t)($src2$$constant));
7997 %}
7998
7999 ins_pipe(ialu_reg_imm);
8000 %}
8001
8002 // Register And Long
8003 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8004 match(Set dst (AndL src1 src2));
8005
8006 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8007
8008 ins_cost(ALU_COST);
8009 ins_encode %{
8010 __ andr(as_Register($dst$$reg),
8011 as_Register($src1$$reg),
8012 as_Register($src2$$reg));
8013 %}
8014
8015 ins_pipe(ialu_reg_reg);
8016 %}
8017
8018 // Immediate And Long
8019 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8020 match(Set dst (AndL src1 src2));
8021
8022 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8023
8024 ins_cost(ALU_COST);
8025 ins_encode %{
8026 __ andi(as_Register($dst$$reg),
8027 as_Register($src1$$reg),
8028 (int32_t)($src2$$constant));
8029 %}
8030
8031 ins_pipe(ialu_reg_imm);
8032 %}
8033
8034 // Register Or Long
8035 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8036 match(Set dst (OrL src1 src2));
8037
8038 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8039
8040 ins_cost(ALU_COST);
8041 ins_encode %{
8042 __ orr(as_Register($dst$$reg),
8043 as_Register($src1$$reg),
8044 as_Register($src2$$reg));
8045 %}
8046
8047 ins_pipe(ialu_reg_reg);
8048 %}
8049
8050 // Immediate Or Long
8051 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8052 match(Set dst (OrL src1 src2));
8053
8054 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8055
8056 ins_cost(ALU_COST);
8057 ins_encode %{
8058 __ ori(as_Register($dst$$reg),
8059 as_Register($src1$$reg),
8060 (int32_t)($src2$$constant));
8061 %}
8062
8063 ins_pipe(ialu_reg_imm);
8064 %}
8065
8066 // Register Xor Long
8067 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8068 match(Set dst (XorL src1 src2));
8069
8070 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8071
8072 ins_cost(ALU_COST);
8073 ins_encode %{
8074 __ xorr(as_Register($dst$$reg),
8075 as_Register($src1$$reg),
8076 as_Register($src2$$reg));
8077 %}
8078
8079 ins_pipe(ialu_reg_reg);
8080 %}
8081
8082 // Immediate Xor Long
8083 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8084 match(Set dst (XorL src1 src2));
8085
8086 ins_cost(ALU_COST);
8087 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8088
8089 ins_encode %{
8090 __ xori(as_Register($dst$$reg),
8091 as_Register($src1$$reg),
8092 (int32_t)($src2$$constant));
8093 %}
8094
8095 ins_pipe(ialu_reg_imm);
8096 %}
8097
8098 // ============================================================================
8099 // MemBar Instruction
8100
8101 // RVTSO
8102
8103 instruct unnecessary_membar_rvtso() %{
8104 predicate(UseZtso);
8105 match(LoadFence);
8106 match(StoreFence);
8107 match(StoreStoreFence);
8108 match(MemBarAcquire);
8109 match(MemBarRelease);
8110 match(MemBarStoreStore);
8111 match(MemBarAcquireLock);
8112 match(MemBarReleaseLock);
8113
8114 ins_cost(0);
8115
8116 size(0);
8117
8118 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8119 ins_encode %{
8120 __ block_comment("unnecessary_membar_rvtso");
8121 %}
8122 ins_pipe(real_empty);
8123 %}
8124
8125 instruct membar_storeload_rvtso() %{
8126 predicate(UseZtso);
8127 match(MemBarStoreLoad);
8128 ins_cost(VOLATILE_REF_COST);
8129
8130 format %{ "#@membar_storeload_rvtso\n\t"
8131 "fence w, r"%}
8132
8133 ins_encode %{
8134 __ block_comment("membar_storeload_rvtso");
8135 __ membar(MacroAssembler::StoreLoad);
8136 %}
8137
8138 ins_pipe(pipe_slow);
8139 %}
8140
8141 instruct membar_volatile_rvtso() %{
8142 predicate(UseZtso);
8143 match(MemBarVolatile);
8144 ins_cost(VOLATILE_REF_COST);
8145
8146 format %{ "#@membar_volatile_rvtso\n\t"
8147 "fence w, r"%}
8148
8149 ins_encode %{
8150 __ block_comment("membar_volatile_rvtso");
8151 __ membar(MacroAssembler::StoreLoad);
8152 %}
8153
8154 ins_pipe(pipe_slow);
8155 %}
8156
8157 instruct unnecessary_membar_volatile_rvtso() %{
8158 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8159 match(MemBarVolatile);
8160 ins_cost(0);
8161
8162 size(0);
8163
8164 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8165 ins_encode %{
8166 __ block_comment("unnecessary_membar_volatile_rvtso");
8167 %}
8168 ins_pipe(real_empty);
8169 %}
8170
8171 instruct membar_full_rvtso() %{
8172 predicate(UseZtso);
8173 match(MemBarFull);
8174 ins_cost(VOLATILE_REF_COST);
8175
8176 format %{ "#@membar_full_rvtso\n\t"
8177 "fence rw, rw" %}
8178
8179 ins_encode %{
8180 __ block_comment("membar_full_rvtso");
8181 __ membar(MacroAssembler::AnyAny);
8182 %}
8183
8184 ins_pipe(pipe_slow);
8185 %}
8186
8187 // RVWMO
8188
8189 instruct membar_aqcuire_rvwmo() %{
8190 predicate(!UseZtso);
8191 match(LoadFence);
8192 match(MemBarAcquire);
8193 ins_cost(VOLATILE_REF_COST);
8194
8195 format %{ "#@membar_aqcuire_rvwmo\n\t"
8196 "fence r, rw" %}
8197
8198 ins_encode %{
8199 __ block_comment("membar_aqcuire_rvwmo");
8200 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8201 %}
8202 ins_pipe(pipe_serial);
8203 %}
8204
8205 instruct membar_release_rvwmo() %{
8206 predicate(!UseZtso);
8207 match(StoreFence);
8208 match(MemBarRelease);
8209 ins_cost(VOLATILE_REF_COST);
8210
8211 format %{ "#@membar_release_rvwmo\n\t"
8212 "fence rw, w" %}
8213
8214 ins_encode %{
8215 __ block_comment("membar_release_rvwmo");
8216 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8217 %}
8218 ins_pipe(pipe_serial);
8219 %}
8220
8221 instruct membar_storestore_rvwmo() %{
8222 predicate(!UseZtso);
8223 match(MemBarStoreStore);
8224 match(StoreStoreFence);
8225 ins_cost(VOLATILE_REF_COST);
8226
8227 format %{ "#@membar_storestore_rvwmo\n\t"
8228 "fence w, w" %}
8229
8230 ins_encode %{
8231 __ membar(MacroAssembler::StoreStore);
8232 %}
8233 ins_pipe(pipe_serial);
8234 %}
8235
8236 instruct membar_storeload_rvwmo() %{
8237 predicate(!UseZtso);
8238 match(MemBarStoreLoad);
8239 ins_cost(VOLATILE_REF_COST);
8240
8241 format %{ "#@membar_storeload_rvwmo\n\t"
8242 "fence w, r"%}
8243
8244 ins_encode %{
8245 __ block_comment("membar_storeload_rvwmo");
8246 __ membar(MacroAssembler::StoreLoad);
8247 %}
8248
8249 ins_pipe(pipe_serial);
8250 %}
8251
8252 instruct membar_volatile_rvwmo() %{
8253 predicate(!UseZtso);
8254 match(MemBarVolatile);
8255 ins_cost(VOLATILE_REF_COST);
8256
8257 format %{ "#@membar_volatile_rvwmo\n\t"
8258 "fence w, r"%}
8259
8260 ins_encode %{
8261 __ block_comment("membar_volatile_rvwmo");
8262 __ membar(MacroAssembler::StoreLoad);
8263 %}
8264
8265 ins_pipe(pipe_serial);
8266 %}
8267
8268 instruct membar_lock_rvwmo() %{
8269 predicate(!UseZtso);
8270 match(MemBarAcquireLock);
8271 match(MemBarReleaseLock);
8272 ins_cost(0);
8273
8274 format %{ "#@membar_lock_rvwmo (elided)" %}
8275
8276 ins_encode %{
8277 __ block_comment("membar_lock_rvwmo (elided)");
8278 %}
8279
8280 ins_pipe(pipe_serial);
8281 %}
8282
8283 instruct unnecessary_membar_volatile_rvwmo() %{
8284 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8285 match(MemBarVolatile);
8286 ins_cost(0);
8287
8288 size(0);
8289 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8290 ins_encode %{
8291 __ block_comment("unnecessary_membar_volatile_rvwmo");
8292 %}
8293 ins_pipe(real_empty);
8294 %}
8295
8296 instruct membar_full_rvwmo() %{
8297 predicate(!UseZtso);
8298 match(MemBarFull);
8299 ins_cost(VOLATILE_REF_COST);
8300
8301 format %{ "#@membar_full_rvwmo\n\t"
8302 "fence rw, rw" %}
8303
8304 ins_encode %{
8305 __ block_comment("membar_full_rvwmo");
8306 __ membar(MacroAssembler::AnyAny);
8307 %}
8308
8309 ins_pipe(pipe_serial);
8310 %}
8311
8312 instruct spin_wait() %{
8313 predicate(UseZihintpause);
8314 match(OnSpinWait);
8315 ins_cost(CACHE_MISS_COST);
8316
8317 format %{ "spin_wait" %}
8318
8319 ins_encode %{
8320 __ pause();
8321 %}
8322
8323 ins_pipe(pipe_serial);
8324 %}
8325
8326 // ============================================================================
8327 // Cast Instructions (Java-level type cast)
8328
8329 instruct castI2N(iRegNNoSp dst, iRegI src) %{
8330 match(Set dst (CastI2N src));
8331
8332 ins_cost(ALU_COST);
8333 format %{ "zext $dst, $src, 32\t# int -> narrow ptr" %}
8334
8335 ins_encode %{
8336 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8337 %}
8338
8339 ins_pipe(ialu_reg);
8340 %}
8341
8342 instruct castN2X(iRegLNoSp dst, iRegN src) %{
8343 match(Set dst (CastP2X src));
8344
8345 ins_cost(ALU_COST);
8346 format %{ "mv $dst, $src\t# ptr -> long" %}
8347
8348 ins_encode %{
8349 if ($dst$$reg != $src$$reg) {
8350 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8351 }
8352 %}
8353
8354 ins_pipe(ialu_reg);
8355 %}
8356
8357 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8358 match(Set dst (CastX2P src));
8359
8360 ins_cost(ALU_COST);
8361 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8362
8363 ins_encode %{
8364 if ($dst$$reg != $src$$reg) {
8365 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8366 }
8367 %}
8368
8369 ins_pipe(ialu_reg);
8370 %}
8371
8372 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8373 match(Set dst (CastP2X src));
8374
8375 ins_cost(ALU_COST);
8376 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8377
8378 ins_encode %{
8379 if ($dst$$reg != $src$$reg) {
8380 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8381 }
8382 %}
8383
8384 ins_pipe(ialu_reg);
8385 %}
8386
8387 instruct castPP(iRegPNoSp dst)
8388 %{
8389 match(Set dst (CastPP dst));
8390 ins_cost(0);
8391
8392 size(0);
8393 format %{ "# castPP of $dst, #@castPP" %}
8394 ins_encode(/* empty encoding */);
8395 ins_pipe(pipe_class_empty);
8396 %}
8397
8398 instruct castLL(iRegL dst)
8399 %{
8400 match(Set dst (CastLL dst));
8401
8402 size(0);
8403 format %{ "# castLL of $dst, #@castLL" %}
8404 ins_encode(/* empty encoding */);
8405 ins_cost(0);
8406 ins_pipe(pipe_class_empty);
8407 %}
8408
8409 instruct castII(iRegI dst)
8410 %{
8411 match(Set dst (CastII dst));
8412
8413 size(0);
8414 format %{ "# castII of $dst, #@castII" %}
8415 ins_encode(/* empty encoding */);
8416 ins_cost(0);
8417 ins_pipe(pipe_class_empty);
8418 %}
8419
8420 instruct checkCastPP(iRegPNoSp dst)
8421 %{
8422 match(Set dst (CheckCastPP dst));
8423
8424 size(0);
8425 ins_cost(0);
8426 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8427 ins_encode(/* empty encoding */);
8428 ins_pipe(pipe_class_empty);
8429 %}
8430
8431 instruct castHH(fRegF dst)
8432 %{
8433 match(Set dst (CastHH dst));
8434
8435 size(0);
8436 format %{ "# castHH of $dst" %}
8437 ins_encode(/* empty encoding */);
8438 ins_cost(0);
8439 ins_pipe(pipe_class_empty);
8440 %}
8441
8442 instruct castFF(fRegF dst)
8443 %{
8444 match(Set dst (CastFF dst));
8445
8446 size(0);
8447 format %{ "# castFF of $dst" %}
8448 ins_encode(/* empty encoding */);
8449 ins_cost(0);
8450 ins_pipe(pipe_class_empty);
8451 %}
8452
8453 instruct castDD(fRegD dst)
8454 %{
8455 match(Set dst (CastDD dst));
8456
8457 size(0);
8458 format %{ "# castDD of $dst" %}
8459 ins_encode(/* empty encoding */);
8460 ins_cost(0);
8461 ins_pipe(pipe_class_empty);
8462 %}
8463
8464 instruct castVV(vReg dst)
8465 %{
8466 match(Set dst (CastVV dst));
8467
8468 size(0);
8469 format %{ "# castVV of $dst" %}
8470 ins_encode(/* empty encoding */);
8471 ins_cost(0);
8472 ins_pipe(pipe_class_empty);
8473 %}
8474
8475 instruct castVVMask(vRegMask dst)
8476 %{
8477 match(Set dst (CastVV dst));
8478
8479 size(0);
8480 format %{ "# castVV of $dst" %}
8481 ins_encode(/* empty encoding */);
8482 ins_cost(0);
8483 ins_pipe(pipe_class_empty);
8484 %}
8485
8486 // ============================================================================
8487 // Convert Instructions
8488
8489 // int to bool
8490 instruct convI2Bool(iRegINoSp dst, iRegI src)
8491 %{
8492 match(Set dst (Conv2B src));
8493
8494 ins_cost(ALU_COST);
8495 format %{ "snez $dst, $src\t#@convI2Bool" %}
8496
8497 ins_encode %{
8498 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8499 %}
8500
8501 ins_pipe(ialu_reg);
8502 %}
8503
8504 // pointer to bool
8505 instruct convP2Bool(iRegINoSp dst, iRegP src)
8506 %{
8507 match(Set dst (Conv2B src));
8508
8509 ins_cost(ALU_COST);
8510 format %{ "snez $dst, $src\t#@convP2Bool" %}
8511
8512 ins_encode %{
8513 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8514 %}
8515
8516 ins_pipe(ialu_reg);
8517 %}
8518
8519 // int <-> long
8520
8521 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8522 %{
8523 match(Set dst (ConvI2L src));
8524
8525 ins_cost(ALU_COST);
8526 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8527 ins_encode %{
8528 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8529 %}
8530 ins_pipe(ialu_reg);
8531 %}
8532
8533 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8534 match(Set dst (ConvL2I src));
8535
8536 ins_cost(ALU_COST);
8537 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8538
8539 ins_encode %{
8540 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8541 %}
8542
8543 ins_pipe(ialu_reg);
8544 %}
8545
8546 // int to unsigned long (Zero-extend)
8547 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8548 %{
8549 match(Set dst (AndL (ConvI2L src) mask));
8550
8551 ins_cost(ALU_COST * 2);
8552 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8553
8554 ins_encode %{
8555 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8556 %}
8557
8558 ins_pipe(ialu_reg_shift);
8559 %}
8560
8561 // float <-> double
8562
8563 instruct convF2D_reg(fRegD dst, fRegF src) %{
8564 match(Set dst (ConvF2D src));
8565
8566 ins_cost(XFER_COST);
8567 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8568
8569 ins_encode %{
8570 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8571 %}
8572
8573 ins_pipe(fp_f2d);
8574 %}
8575
8576 instruct convD2F_reg(fRegF dst, fRegD src) %{
8577 match(Set dst (ConvD2F src));
8578
8579 ins_cost(XFER_COST);
8580 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8581
8582 ins_encode %{
8583 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8584 %}
8585
8586 ins_pipe(fp_d2f);
8587 %}
8588
8589 // single <-> half precision
8590
8591 instruct convHF2F_reg_reg(fRegF dst, iRegIorL2I src, iRegINoSp tmp) %{
8592 match(Set dst (ConvHF2F src));
8593 effect(TEMP tmp);
8594 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8595 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8596 %}
8597 ins_encode %{
8598 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8599 %}
8600 ins_pipe(pipe_slow);
8601 %}
8602
8603 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8604 match(Set dst (ConvF2HF src));
8605 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8606 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8607 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8608 %}
8609 ins_encode %{
8610 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8611 %}
8612 ins_pipe(pipe_slow);
8613 %}
8614
8615 // half precision operations
8616
8617 instruct reinterpretS2HF(fRegF dst, iRegI src)
8618 %{
8619 match(Set dst (ReinterpretS2HF src));
8620 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8621 ins_encode %{
8622 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8623 %}
8624 ins_pipe(fp_i2f);
8625 %}
8626
8627 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8628 %{
8629 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8630 format %{ "convF2HFAndS2HF $dst, $src" %}
8631 ins_encode %{
8632 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8633 %}
8634 ins_pipe(fp_uop_s);
8635 %}
8636
8637 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8638 %{
8639 match(Set dst (ReinterpretHF2S src));
8640 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8641 ins_encode %{
8642 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8643 %}
8644 ins_pipe(fp_f2i);
8645 %}
8646
8647 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8648 %{
8649 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8650 format %{ "convHF2SAndHF2F $dst, $src" %}
8651 ins_encode %{
8652 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8653 %}
8654 ins_pipe(fp_uop_s);
8655 %}
8656
8657 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8658 %{
8659 match(Set dst (SqrtHF src));
8660 format %{ "fsqrt.h $dst, $src" %}
8661 ins_encode %{
8662 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8663 %}
8664 ins_pipe(fp_sqrt_s);
8665 %}
8666
8667 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8668 %{
8669 match(Set dst (AddHF src1 src2));
8670 match(Set dst (SubHF src1 src2));
8671 match(Set dst (MulHF src1 src2));
8672 match(Set dst (DivHF src1 src2));
8673 format %{ "binop_hf $dst, $src1, $src2" %}
8674 ins_encode %{
8675 int opcode = this->ideal_Opcode();
8676 switch(opcode) {
8677 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8678 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8679 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8680 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8681 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8682 }
8683 %}
8684 ins_pipe(fp_dop_reg_reg_s);
8685 %}
8686
8687 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8688 %{
8689 predicate(!UseZfa);
8690 match(Set dst (MinHF src1 src2));
8691 effect(KILL cr);
8692
8693 format %{ "min_hf $dst, $src1, $src2" %}
8694
8695 ins_encode %{
8696 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8697 __ FLOAT_TYPE::half_precision, true /* is_min */);
8698 %}
8699 ins_pipe(pipe_class_default);
8700 %}
8701
8702 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8703 %{
8704 predicate(UseZfa);
8705 match(Set dst (MinHF src1 src2));
8706
8707 format %{ "min_hf $dst, $src1, $src2" %}
8708
8709 ins_encode %{
8710 __ fminm_h(as_FloatRegister($dst$$reg),
8711 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8712 %}
8713
8714 ins_pipe(pipe_class_default);
8715 %}
8716
8717 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8718 %{
8719 predicate(!UseZfa);
8720 match(Set dst (MaxHF src1 src2));
8721 effect(KILL cr);
8722
8723 format %{ "max_hf $dst, $src1, $src2" %}
8724
8725 ins_encode %{
8726 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8727 __ FLOAT_TYPE::half_precision, false /* is_min */);
8728 %}
8729 ins_pipe(pipe_class_default);
8730 %}
8731
8732 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8733 %{
8734 predicate(UseZfa);
8735 match(Set dst (MaxHF src1 src2));
8736
8737 format %{ "max_hf $dst, $src1, $src2" %}
8738
8739 ins_encode %{
8740 __ fmaxm_h(as_FloatRegister($dst$$reg),
8741 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8742 %}
8743
8744 ins_pipe(pipe_class_default);
8745 %}
8746
8747 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8748 %{
8749 match(Set dst (FmaHF src3 (Binary src1 src2)));
8750 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8751 ins_encode %{
8752 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8753 %}
8754 ins_pipe(pipe_class_default);
8755 %}
8756
8757 // float <-> int
8758
8759 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8760 match(Set dst (ConvF2I src));
8761
8762 ins_cost(XFER_COST);
8763 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8764
8765 ins_encode %{
8766 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8767 %}
8768
8769 ins_pipe(fp_f2i);
8770 %}
8771
8772 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8773 match(Set dst (ConvI2F src));
8774
8775 ins_cost(XFER_COST);
8776 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8777
8778 ins_encode %{
8779 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8780 %}
8781
8782 ins_pipe(fp_i2f);
8783 %}
8784
8785 // float <-> long
8786
8787 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8788 match(Set dst (ConvF2L src));
8789
8790 ins_cost(XFER_COST);
8791 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8792
8793 ins_encode %{
8794 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8795 %}
8796
8797 ins_pipe(fp_f2l);
8798 %}
8799
8800 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8801 match(Set dst (ConvL2F src));
8802
8803 ins_cost(XFER_COST);
8804 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8805
8806 ins_encode %{
8807 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8808 %}
8809
8810 ins_pipe(fp_l2f);
8811 %}
8812
8813 // double <-> int
8814
8815 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8816 match(Set dst (ConvD2I src));
8817
8818 ins_cost(XFER_COST);
8819 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8820
8821 ins_encode %{
8822 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8823 %}
8824
8825 ins_pipe(fp_d2i);
8826 %}
8827
8828 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8829 match(Set dst (ConvI2D src));
8830
8831 ins_cost(XFER_COST);
8832 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8833
8834 ins_encode %{
8835 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8836 %}
8837
8838 ins_pipe(fp_i2d);
8839 %}
8840
8841 // double <-> long
8842
8843 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8844 match(Set dst (ConvD2L src));
8845
8846 ins_cost(XFER_COST);
8847 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8848
8849 ins_encode %{
8850 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8851 %}
8852
8853 ins_pipe(fp_d2l);
8854 %}
8855
8856 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8857 match(Set dst (ConvL2D src));
8858
8859 ins_cost(XFER_COST);
8860 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8861
8862 ins_encode %{
8863 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8864 %}
8865
8866 ins_pipe(fp_l2d);
8867 %}
8868
8869 // Convert oop into int for vectors alignment masking
8870 instruct convP2I(iRegINoSp dst, iRegP src) %{
8871 match(Set dst (ConvL2I (CastP2X src)));
8872
8873 ins_cost(ALU_COST * 2);
8874 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8875
8876 ins_encode %{
8877 __ zext($dst$$Register, $src$$Register, 32);
8878 %}
8879
8880 ins_pipe(ialu_reg);
8881 %}
8882
8883 // Convert compressed oop into int for vectors alignment masking
8884 // in case of 32bit oops (heap < 4Gb).
8885 instruct convN2I(iRegINoSp dst, iRegN src)
8886 %{
8887 predicate(CompressedOops::shift() == 0);
8888 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8889
8890 ins_cost(ALU_COST);
8891 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8892
8893 ins_encode %{
8894 __ mv($dst$$Register, $src$$Register);
8895 %}
8896
8897 ins_pipe(ialu_reg);
8898 %}
8899
8900 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8901 match(Set dst (RoundD src));
8902
8903 ins_cost(XFER_COST + BRANCH_COST);
8904 effect(TEMP ftmp);
8905 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8906
8907 ins_encode %{
8908 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8909 %}
8910
8911 ins_pipe(pipe_slow);
8912 %}
8913
8914 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8915 match(Set dst (RoundF src));
8916
8917 ins_cost(XFER_COST + BRANCH_COST);
8918 effect(TEMP ftmp);
8919 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8920
8921 ins_encode %{
8922 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8923 %}
8924
8925 ins_pipe(pipe_slow);
8926 %}
8927
8928 // Convert oop pointer into compressed form
8929 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8930 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8931 match(Set dst (EncodeP src));
8932 ins_cost(ALU_COST);
8933 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8934 ins_encode %{
8935 Register s = $src$$Register;
8936 Register d = $dst$$Register;
8937 __ encode_heap_oop(d, s);
8938 %}
8939 ins_pipe(pipe_class_default);
8940 %}
8941
8942 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8943 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8944 match(Set dst (EncodeP src));
8945 ins_cost(ALU_COST);
8946 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8947 ins_encode %{
8948 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8949 %}
8950 ins_pipe(pipe_class_default);
8951 %}
8952
8953 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8954 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8955 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8956 match(Set dst (DecodeN src));
8957
8958 ins_cost(0);
8959 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8960 ins_encode %{
8961 Register s = $src$$Register;
8962 Register d = $dst$$Register;
8963 __ decode_heap_oop(d, s);
8964 %}
8965 ins_pipe(pipe_class_default);
8966 %}
8967
8968 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8969 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8970 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8971 match(Set dst (DecodeN src));
8972
8973 ins_cost(0);
8974 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8975 ins_encode %{
8976 Register s = $src$$Register;
8977 Register d = $dst$$Register;
8978 __ decode_heap_oop_not_null(d, s);
8979 %}
8980 ins_pipe(pipe_class_default);
8981 %}
8982
8983 // Convert klass pointer into compressed form.
8984 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8985 match(Set dst (EncodePKlass src));
8986
8987 ins_cost(ALU_COST);
8988 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8989
8990 ins_encode %{
8991 Register src_reg = as_Register($src$$reg);
8992 Register dst_reg = as_Register($dst$$reg);
8993 __ encode_klass_not_null(dst_reg, src_reg, t0);
8994 %}
8995
8996 ins_pipe(pipe_class_default);
8997 %}
8998
8999 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
9000 match(Set dst (DecodeNKlass src));
9001
9002 effect(TEMP_DEF dst, TEMP tmp);
9003
9004 ins_cost(ALU_COST);
9005 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
9006
9007 ins_encode %{
9008 Register src_reg = as_Register($src$$reg);
9009 Register dst_reg = as_Register($dst$$reg);
9010 Register tmp_reg = as_Register($tmp$$reg);
9011 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
9012 %}
9013
9014 ins_pipe(pipe_class_default);
9015 %}
9016
9017 // stack <-> reg and reg <-> reg shuffles with no conversion
9018
9019 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
9020
9021 match(Set dst (MoveF2I src));
9022
9023 effect(DEF dst, USE src);
9024
9025 ins_cost(LOAD_COST);
9026
9027 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
9028
9029 ins_encode %{
9030 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
9031 %}
9032
9033 ins_pipe(iload_reg_reg);
9034
9035 %}
9036
9037 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
9038
9039 match(Set dst (MoveI2F src));
9040
9041 effect(DEF dst, USE src);
9042
9043 ins_cost(LOAD_COST);
9044
9045 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
9046
9047 ins_encode %{
9048 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9049 %}
9050
9051 ins_pipe(fp_load_mem_s);
9052
9053 %}
9054
9055 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9056
9057 match(Set dst (MoveD2L src));
9058
9059 effect(DEF dst, USE src);
9060
9061 ins_cost(LOAD_COST);
9062
9063 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9064
9065 ins_encode %{
9066 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9067 %}
9068
9069 ins_pipe(iload_reg_reg);
9070
9071 %}
9072
9073 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9074
9075 match(Set dst (MoveL2D src));
9076
9077 effect(DEF dst, USE src);
9078
9079 ins_cost(LOAD_COST);
9080
9081 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9082
9083 ins_encode %{
9084 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9085 %}
9086
9087 ins_pipe(fp_load_mem_d);
9088
9089 %}
9090
9091 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9092
9093 match(Set dst (MoveF2I src));
9094
9095 effect(DEF dst, USE src);
9096
9097 ins_cost(STORE_COST);
9098
9099 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9100
9101 ins_encode %{
9102 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9103 %}
9104
9105 ins_pipe(fp_store_reg_s);
9106
9107 %}
9108
9109 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9110
9111 match(Set dst (MoveI2F src));
9112
9113 effect(DEF dst, USE src);
9114
9115 ins_cost(STORE_COST);
9116
9117 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9118
9119 ins_encode %{
9120 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9121 %}
9122
9123 ins_pipe(istore_reg_reg);
9124
9125 %}
9126
9127 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9128
9129 match(Set dst (MoveD2L src));
9130
9131 effect(DEF dst, USE src);
9132
9133 ins_cost(STORE_COST);
9134
9135 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9136
9137 ins_encode %{
9138 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9139 %}
9140
9141 ins_pipe(fp_store_reg_d);
9142
9143 %}
9144
9145 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9146
9147 match(Set dst (MoveL2D src));
9148
9149 effect(DEF dst, USE src);
9150
9151 ins_cost(STORE_COST);
9152
9153 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9154
9155 ins_encode %{
9156 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9157 %}
9158
9159 ins_pipe(istore_reg_reg);
9160
9161 %}
9162
9163 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9164
9165 match(Set dst (MoveF2I src));
9166
9167 effect(DEF dst, USE src);
9168
9169 ins_cost(FMVX_COST);
9170
9171 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9172
9173 ins_encode %{
9174 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9175 %}
9176
9177 ins_pipe(fp_f2i);
9178
9179 %}
9180
9181 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9182
9183 match(Set dst (MoveI2F src));
9184
9185 effect(DEF dst, USE src);
9186
9187 ins_cost(FMVX_COST);
9188
9189 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9190
9191 ins_encode %{
9192 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9193 %}
9194
9195 ins_pipe(fp_i2f);
9196
9197 %}
9198
9199 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9200
9201 match(Set dst (MoveD2L src));
9202
9203 effect(DEF dst, USE src);
9204
9205 ins_cost(FMVX_COST);
9206
9207 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9208
9209 ins_encode %{
9210 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9211 %}
9212
9213 ins_pipe(fp_d2l);
9214
9215 %}
9216
9217 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9218
9219 match(Set dst (MoveL2D src));
9220
9221 effect(DEF dst, USE src);
9222
9223 ins_cost(FMVX_COST);
9224
9225 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9226
9227 ins_encode %{
9228 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9229 %}
9230
9231 ins_pipe(fp_l2d);
9232
9233 %}
9234
9235 // ============================================================================
9236 // Compare Instructions which set the result float comparisons in dest register.
9237
9238 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9239 %{
9240 match(Set dst (CmpF3 op1 op2));
9241
9242 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9243 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9244 "bgtz $dst, done\n\t"
9245 "feq.s $dst, $op1, $op2\n\t"
9246 "addi $dst, $dst, -1\n\t"
9247 "done:"
9248 %}
9249
9250 ins_encode %{
9251 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9252 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9253 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9254 %}
9255
9256 ins_pipe(pipe_class_default);
9257 %}
9258
9259 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9260 %{
9261 match(Set dst (CmpD3 op1 op2));
9262
9263 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9264 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9265 "bgtz $dst, done\n\t"
9266 "feq.d $dst, $op1, $op2\n\t"
9267 "addi $dst, $dst, -1\n\t"
9268 "done:"
9269 %}
9270
9271 ins_encode %{
9272 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9273 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9274 %}
9275
9276 ins_pipe(pipe_class_default);
9277 %}
9278
9279 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9280 %{
9281 match(Set dst (CmpL3 op1 op2));
9282
9283 ins_cost(ALU_COST * 3 + BRANCH_COST);
9284 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9285 "bnez $dst, done\n\t"
9286 "slt $dst, $op1, $op2\n\t"
9287 "neg $dst, $dst\n\t"
9288 "done:"
9289 %}
9290 ins_encode %{
9291 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9292 __ mv(as_Register($dst$$reg), t0);
9293 %}
9294
9295 ins_pipe(pipe_class_default);
9296 %}
9297
9298 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9299 %{
9300 match(Set dst (CmpUL3 op1 op2));
9301
9302 ins_cost(ALU_COST * 3 + BRANCH_COST);
9303 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9304 "bnez $dst, done\n\t"
9305 "sltu $dst, $op1, $op2\n\t"
9306 "neg $dst, $dst\n\t"
9307 "done:"
9308 %}
9309 ins_encode %{
9310 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9311 __ mv(as_Register($dst$$reg), t0);
9312 %}
9313
9314 ins_pipe(pipe_class_default);
9315 %}
9316
9317 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9318 %{
9319 match(Set dst (CmpU3 op1 op2));
9320
9321 ins_cost(ALU_COST * 3 + BRANCH_COST);
9322 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9323 "bnez $dst, done\n\t"
9324 "sltu $dst, $op1, $op2\n\t"
9325 "neg $dst, $dst\n\t"
9326 "done:"
9327 %}
9328 ins_encode %{
9329 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9330 __ mv(as_Register($dst$$reg), t0);
9331 %}
9332
9333 ins_pipe(pipe_class_default);
9334 %}
9335
9336 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9337 %{
9338 match(Set dst (CmpLTMask p q));
9339
9340 ins_cost(2 * ALU_COST);
9341
9342 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9343 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9344 %}
9345
9346 ins_encode %{
9347 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9348 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9349 %}
9350
9351 ins_pipe(ialu_reg_reg);
9352 %}
9353
9354 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9355 %{
9356 match(Set dst (CmpLTMask op zero));
9357
9358 ins_cost(ALU_COST);
9359
9360 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9361
9362 ins_encode %{
9363 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9364 %}
9365
9366 ins_pipe(ialu_reg_shift);
9367 %}
9368
9369
9370 // ============================================================================
9371 // Max and Min
9372
9373 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9374 %{
9375 match(Set dst (MinI dst src));
9376
9377 ins_cost(BRANCH_COST + ALU_COST);
9378 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9379
9380 ins_encode %{
9381 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9382 as_Register($dst$$reg), as_Register($src$$reg));
9383 %}
9384
9385 ins_pipe(pipe_class_compare);
9386 %}
9387
9388 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9389 %{
9390 match(Set dst (MaxI dst src));
9391
9392 ins_cost(BRANCH_COST + ALU_COST);
9393 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9394
9395 ins_encode %{
9396 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9397 as_Register($dst$$reg), as_Register($src$$reg));
9398 %}
9399
9400 ins_pipe(pipe_class_compare);
9401 %}
9402
9403 // special case for comparing with zero
9404 // n.b. this is selected in preference to the rule above because it
9405 // avoids loading constant 0 into a source register
9406
9407 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9408 %{
9409 match(Set dst (MinI dst zero));
9410 match(Set dst (MinI zero dst));
9411
9412 ins_cost(BRANCH_COST + ALU_COST);
9413 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9414
9415 ins_encode %{
9416 __ cmov_gt(as_Register($dst$$reg), zr,
9417 as_Register($dst$$reg), zr);
9418 %}
9419
9420 ins_pipe(pipe_class_compare);
9421 %}
9422
9423 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9424 %{
9425 match(Set dst (MaxI dst zero));
9426 match(Set dst (MaxI zero dst));
9427
9428 ins_cost(BRANCH_COST + ALU_COST);
9429 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9430
9431 ins_encode %{
9432 __ cmov_lt(as_Register($dst$$reg), zr,
9433 as_Register($dst$$reg), zr);
9434 %}
9435
9436 ins_pipe(pipe_class_compare);
9437 %}
9438
9439 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9440 %{
9441 match(Set dst (MinI src1 src2));
9442
9443 effect(DEF dst, USE src1, USE src2);
9444
9445 ins_cost(BRANCH_COST + ALU_COST * 2);
9446 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9447
9448 ins_encode %{
9449 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9450 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9451 as_Register($dst$$reg), as_Register($src2$$reg));
9452 %}
9453
9454 ins_pipe(pipe_class_compare);
9455 %}
9456
9457 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9458 %{
9459 match(Set dst (MaxI src1 src2));
9460
9461 effect(DEF dst, USE src1, USE src2);
9462
9463 ins_cost(BRANCH_COST + ALU_COST * 2);
9464 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9465
9466 ins_encode %{
9467 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9468 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9469 as_Register($dst$$reg), as_Register($src2$$reg));
9470 %}
9471
9472 ins_pipe(pipe_class_compare);
9473 %}
9474
9475 // ============================================================================
9476 // Branch Instructions
9477 // Direct Branch.
9478 instruct branch(label lbl)
9479 %{
9480 match(Goto);
9481
9482 effect(USE lbl);
9483
9484 ins_cost(BRANCH_COST);
9485 format %{ "j $lbl\t#@branch" %}
9486
9487 ins_encode(riscv_enc_j(lbl));
9488
9489 ins_pipe(pipe_branch);
9490 %}
9491
9492 // ============================================================================
9493 // Compare and Branch Instructions
9494
9495 // Patterns for short (< 12KiB) variants
9496
9497 // Compare flags and branch near instructions.
9498 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9499 match(If cmp cr);
9500 effect(USE lbl);
9501
9502 ins_cost(BRANCH_COST);
9503 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9504
9505 ins_encode %{
9506 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9507 %}
9508 ins_pipe(pipe_cmpz_branch);
9509 ins_short_branch(1);
9510 %}
9511
9512 // Compare signed int and branch near instructions
9513 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9514 %{
9515 // Same match rule as `far_cmpI_branch'.
9516 match(If cmp (CmpI op1 op2));
9517
9518 effect(USE lbl);
9519
9520 ins_cost(BRANCH_COST);
9521
9522 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9523
9524 ins_encode %{
9525 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9526 %}
9527
9528 ins_pipe(pipe_cmp_branch);
9529 ins_short_branch(1);
9530 %}
9531
9532 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9533 %{
9534 // Same match rule as `far_cmpI_loop'.
9535 match(CountedLoopEnd cmp (CmpI op1 op2));
9536
9537 effect(USE lbl);
9538
9539 ins_cost(BRANCH_COST);
9540
9541 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9542
9543 ins_encode %{
9544 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9545 %}
9546
9547 ins_pipe(pipe_cmp_branch);
9548 ins_short_branch(1);
9549 %}
9550
9551 // Compare unsigned int and branch near instructions
9552 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9553 %{
9554 // Same match rule as `far_cmpU_branch'.
9555 match(If cmp (CmpU op1 op2));
9556
9557 effect(USE lbl);
9558
9559 ins_cost(BRANCH_COST);
9560
9561 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9562
9563 ins_encode %{
9564 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9565 as_Register($op2$$reg), *($lbl$$label));
9566 %}
9567
9568 ins_pipe(pipe_cmp_branch);
9569 ins_short_branch(1);
9570 %}
9571
9572 // Compare signed long and branch near instructions
9573 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9574 %{
9575 // Same match rule as `far_cmpL_branch'.
9576 match(If cmp (CmpL op1 op2));
9577
9578 effect(USE lbl);
9579
9580 ins_cost(BRANCH_COST);
9581
9582 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9583
9584 ins_encode %{
9585 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9586 %}
9587
9588 ins_pipe(pipe_cmp_branch);
9589 ins_short_branch(1);
9590 %}
9591
9592 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9593 %{
9594 // Same match rule as `far_cmpL_loop'.
9595 match(CountedLoopEnd cmp (CmpL op1 op2));
9596
9597 effect(USE lbl);
9598
9599 ins_cost(BRANCH_COST);
9600
9601 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9602
9603 ins_encode %{
9604 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9605 %}
9606
9607 ins_pipe(pipe_cmp_branch);
9608 ins_short_branch(1);
9609 %}
9610
9611 // Compare unsigned long and branch near instructions
9612 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9613 %{
9614 // Same match rule as `far_cmpUL_branch'.
9615 match(If cmp (CmpUL op1 op2));
9616
9617 effect(USE lbl);
9618
9619 ins_cost(BRANCH_COST);
9620 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9621
9622 ins_encode %{
9623 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9624 as_Register($op2$$reg), *($lbl$$label));
9625 %}
9626
9627 ins_pipe(pipe_cmp_branch);
9628 ins_short_branch(1);
9629 %}
9630
9631 // Compare pointer and branch near instructions
9632 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9633 %{
9634 // Same match rule as `far_cmpP_branch'.
9635 match(If cmp (CmpP op1 op2));
9636
9637 effect(USE lbl);
9638
9639 ins_cost(BRANCH_COST);
9640
9641 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9642
9643 ins_encode %{
9644 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9645 as_Register($op2$$reg), *($lbl$$label));
9646 %}
9647
9648 ins_pipe(pipe_cmp_branch);
9649 ins_short_branch(1);
9650 %}
9651
9652 // Compare narrow pointer and branch near instructions
9653 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9654 %{
9655 // Same match rule as `far_cmpN_branch'.
9656 match(If cmp (CmpN op1 op2));
9657
9658 effect(USE lbl);
9659
9660 ins_cost(BRANCH_COST);
9661
9662 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9663
9664 ins_encode %{
9665 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9666 as_Register($op2$$reg), *($lbl$$label));
9667 %}
9668
9669 ins_pipe(pipe_cmp_branch);
9670 ins_short_branch(1);
9671 %}
9672
9673 // Compare float and branch near instructions
9674 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9675 %{
9676 // Same match rule as `far_cmpF_branch'.
9677 match(If cmp (CmpF op1 op2));
9678
9679 effect(USE lbl);
9680
9681 ins_cost(XFER_COST + BRANCH_COST);
9682 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9683
9684 ins_encode %{
9685 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9686 %}
9687
9688 ins_pipe(pipe_class_compare);
9689 ins_short_branch(1);
9690 %}
9691
9692 // Compare double and branch near instructions
9693 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9694 %{
9695 // Same match rule as `far_cmpD_branch'.
9696 match(If cmp (CmpD op1 op2));
9697 effect(USE lbl);
9698
9699 ins_cost(XFER_COST + BRANCH_COST);
9700 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9701
9702 ins_encode %{
9703 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9704 as_FloatRegister($op2$$reg), *($lbl$$label));
9705 %}
9706
9707 ins_pipe(pipe_class_compare);
9708 ins_short_branch(1);
9709 %}
9710
9711 // Compare signed int with zero and branch near instructions
9712 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9713 %{
9714 // Same match rule as `far_cmpI_reg_imm0_branch'.
9715 match(If cmp (CmpI op1 zero));
9716
9717 effect(USE op1, USE lbl);
9718
9719 ins_cost(BRANCH_COST);
9720 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9721
9722 ins_encode %{
9723 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9724 %}
9725
9726 ins_pipe(pipe_cmpz_branch);
9727 ins_short_branch(1);
9728 %}
9729
9730 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9731 %{
9732 // Same match rule as `far_cmpI_reg_imm0_loop'.
9733 match(CountedLoopEnd cmp (CmpI op1 zero));
9734
9735 effect(USE op1, USE lbl);
9736
9737 ins_cost(BRANCH_COST);
9738
9739 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9740
9741 ins_encode %{
9742 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9743 %}
9744
9745 ins_pipe(pipe_cmpz_branch);
9746 ins_short_branch(1);
9747 %}
9748
9749 // Compare unsigned int with zero and branch near instructions
9750 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9751 %{
9752 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9753 match(If cmp (CmpU op1 zero));
9754
9755 effect(USE op1, USE lbl);
9756
9757 ins_cost(BRANCH_COST);
9758
9759 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9760
9761 ins_encode %{
9762 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9763 %}
9764
9765 ins_pipe(pipe_cmpz_branch);
9766 ins_short_branch(1);
9767 %}
9768
9769 // Compare signed long with zero and branch near instructions
9770 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9771 %{
9772 // Same match rule as `far_cmpL_reg_imm0_branch'.
9773 match(If cmp (CmpL op1 zero));
9774
9775 effect(USE op1, USE lbl);
9776
9777 ins_cost(BRANCH_COST);
9778
9779 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9780
9781 ins_encode %{
9782 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9783 %}
9784
9785 ins_pipe(pipe_cmpz_branch);
9786 ins_short_branch(1);
9787 %}
9788
9789 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9790 %{
9791 // Same match rule as `far_cmpL_reg_imm0_loop'.
9792 match(CountedLoopEnd cmp (CmpL op1 zero));
9793
9794 effect(USE op1, USE lbl);
9795
9796 ins_cost(BRANCH_COST);
9797
9798 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9799
9800 ins_encode %{
9801 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9802 %}
9803
9804 ins_pipe(pipe_cmpz_branch);
9805 ins_short_branch(1);
9806 %}
9807
9808 // Compare unsigned long with zero and branch near instructions
9809 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9810 %{
9811 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9812 match(If cmp (CmpUL op1 zero));
9813
9814 effect(USE op1, USE lbl);
9815
9816 ins_cost(BRANCH_COST);
9817
9818 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9819
9820 ins_encode %{
9821 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9822 %}
9823
9824 ins_pipe(pipe_cmpz_branch);
9825 ins_short_branch(1);
9826 %}
9827
9828 // Compare pointer with zero and branch near instructions
9829 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9830 // Same match rule as `far_cmpP_reg_imm0_branch'.
9831 match(If cmp (CmpP op1 zero));
9832 effect(USE lbl);
9833
9834 ins_cost(BRANCH_COST);
9835 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9836
9837 ins_encode %{
9838 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9839 %}
9840
9841 ins_pipe(pipe_cmpz_branch);
9842 ins_short_branch(1);
9843 %}
9844
9845 // Compare narrow pointer with zero and branch near instructions
9846 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9847 // Same match rule as `far_cmpN_reg_imm0_branch'.
9848 match(If cmp (CmpN op1 zero));
9849 effect(USE lbl);
9850
9851 ins_cost(BRANCH_COST);
9852
9853 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9854
9855 ins_encode %{
9856 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9857 %}
9858
9859 ins_pipe(pipe_cmpz_branch);
9860 ins_short_branch(1);
9861 %}
9862
9863 // Compare narrow pointer with pointer zero and branch near instructions
9864 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9865 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9866 match(If cmp (CmpP (DecodeN op1) zero));
9867 effect(USE lbl);
9868
9869 ins_cost(BRANCH_COST);
9870 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9871
9872 ins_encode %{
9873 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9874 %}
9875
9876 ins_pipe(pipe_cmpz_branch);
9877 ins_short_branch(1);
9878 %}
9879
9880 // Patterns for far (20KiB) variants
9881
9882 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9883 match(If cmp cr);
9884 effect(USE lbl);
9885
9886 ins_cost(BRANCH_COST);
9887 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9888
9889 ins_encode %{
9890 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9891 %}
9892
9893 ins_pipe(pipe_cmpz_branch);
9894 %}
9895
9896 // Compare signed int and branch far instructions
9897 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9898 match(If cmp (CmpI op1 op2));
9899 effect(USE lbl);
9900
9901 ins_cost(BRANCH_COST * 2);
9902
9903 // the format instruction [far_b$cmp] here is be used as two insructions
9904 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9905 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9906
9907 ins_encode %{
9908 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9909 %}
9910
9911 ins_pipe(pipe_cmp_branch);
9912 %}
9913
9914 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9915 match(CountedLoopEnd cmp (CmpI op1 op2));
9916 effect(USE lbl);
9917
9918 ins_cost(BRANCH_COST * 2);
9919 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9920
9921 ins_encode %{
9922 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9923 %}
9924
9925 ins_pipe(pipe_cmp_branch);
9926 %}
9927
9928 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9929 match(If cmp (CmpU op1 op2));
9930 effect(USE lbl);
9931
9932 ins_cost(BRANCH_COST * 2);
9933 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9934
9935 ins_encode %{
9936 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9937 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9938 %}
9939
9940 ins_pipe(pipe_cmp_branch);
9941 %}
9942
9943 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9944 match(If cmp (CmpL op1 op2));
9945 effect(USE lbl);
9946
9947 ins_cost(BRANCH_COST * 2);
9948 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9949
9950 ins_encode %{
9951 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9952 %}
9953
9954 ins_pipe(pipe_cmp_branch);
9955 %}
9956
9957 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9958 match(CountedLoopEnd cmp (CmpL op1 op2));
9959 effect(USE lbl);
9960
9961 ins_cost(BRANCH_COST * 2);
9962 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9963
9964 ins_encode %{
9965 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9966 %}
9967
9968 ins_pipe(pipe_cmp_branch);
9969 %}
9970
9971 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9972 match(If cmp (CmpUL op1 op2));
9973 effect(USE lbl);
9974
9975 ins_cost(BRANCH_COST * 2);
9976 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9977
9978 ins_encode %{
9979 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9980 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9981 %}
9982
9983 ins_pipe(pipe_cmp_branch);
9984 %}
9985
9986 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9987 %{
9988 match(If cmp (CmpP op1 op2));
9989
9990 effect(USE lbl);
9991
9992 ins_cost(BRANCH_COST * 2);
9993
9994 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9995
9996 ins_encode %{
9997 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9998 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9999 %}
10000
10001 ins_pipe(pipe_cmp_branch);
10002 %}
10003
10004 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
10005 %{
10006 match(If cmp (CmpN op1 op2));
10007
10008 effect(USE lbl);
10009
10010 ins_cost(BRANCH_COST * 2);
10011
10012 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
10013
10014 ins_encode %{
10015 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
10016 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
10017 %}
10018
10019 ins_pipe(pipe_cmp_branch);
10020 %}
10021
10022 // Float compare and branch instructions
10023 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
10024 %{
10025 match(If cmp (CmpF op1 op2));
10026
10027 effect(USE lbl);
10028
10029 ins_cost(XFER_COST + BRANCH_COST * 2);
10030 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
10031
10032 ins_encode %{
10033 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10034 *($lbl$$label), /* is_far */ true);
10035 %}
10036
10037 ins_pipe(pipe_class_compare);
10038 %}
10039
10040 // Double compare and branch instructions
10041 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
10042 %{
10043 match(If cmp (CmpD op1 op2));
10044 effect(USE lbl);
10045
10046 ins_cost(XFER_COST + BRANCH_COST * 2);
10047 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10048
10049 ins_encode %{
10050 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10051 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10052 %}
10053
10054 ins_pipe(pipe_class_compare);
10055 %}
10056
10057 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10058 %{
10059 match(If cmp (CmpI op1 zero));
10060
10061 effect(USE op1, USE lbl);
10062
10063 ins_cost(BRANCH_COST * 2);
10064
10065 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10066
10067 ins_encode %{
10068 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10069 %}
10070
10071 ins_pipe(pipe_cmpz_branch);
10072 %}
10073
10074 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10075 %{
10076 match(CountedLoopEnd cmp (CmpI op1 zero));
10077
10078 effect(USE op1, USE lbl);
10079
10080 ins_cost(BRANCH_COST * 2);
10081
10082 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10083
10084 ins_encode %{
10085 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10086 %}
10087
10088 ins_pipe(pipe_cmpz_branch);
10089 %}
10090
10091 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10092 %{
10093 match(If cmp (CmpU op1 zero));
10094
10095 effect(USE op1, USE lbl);
10096
10097 ins_cost(BRANCH_COST * 2);
10098
10099 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10100
10101 ins_encode %{
10102 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10103 %}
10104
10105 ins_pipe(pipe_cmpz_branch);
10106 %}
10107
10108 // compare lt/ge unsigned instructs has no short instruct with same match
10109 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10110 %{
10111 match(If cmp (CmpU op1 zero));
10112
10113 effect(USE op1, USE lbl);
10114
10115 ins_cost(BRANCH_COST);
10116
10117 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10118
10119 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10120
10121 ins_pipe(pipe_cmpz_branch);
10122 %}
10123
10124 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10125 %{
10126 match(If cmp (CmpL op1 zero));
10127
10128 effect(USE op1, USE lbl);
10129
10130 ins_cost(BRANCH_COST * 2);
10131
10132 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10133
10134 ins_encode %{
10135 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10136 %}
10137
10138 ins_pipe(pipe_cmpz_branch);
10139 %}
10140
10141 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10142 %{
10143 match(CountedLoopEnd cmp (CmpL op1 zero));
10144
10145 effect(USE op1, USE lbl);
10146
10147 ins_cost(BRANCH_COST * 2);
10148
10149 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10150
10151 ins_encode %{
10152 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10153 %}
10154
10155 ins_pipe(pipe_cmpz_branch);
10156 %}
10157
10158 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10159 %{
10160 match(If cmp (CmpUL op1 zero));
10161
10162 effect(USE op1, USE lbl);
10163
10164 ins_cost(BRANCH_COST * 2);
10165
10166 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10167
10168 ins_encode %{
10169 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10170 %}
10171
10172 ins_pipe(pipe_cmpz_branch);
10173 %}
10174
10175 // compare lt/ge unsigned instructs has no short instruct with same match
10176 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10177 %{
10178 match(If cmp (CmpUL op1 zero));
10179
10180 effect(USE op1, USE lbl);
10181
10182 ins_cost(BRANCH_COST);
10183
10184 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10185
10186 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10187
10188 ins_pipe(pipe_cmpz_branch);
10189 %}
10190
10191 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10192 match(If cmp (CmpP op1 zero));
10193 effect(USE lbl);
10194
10195 ins_cost(BRANCH_COST * 2);
10196 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10197
10198 ins_encode %{
10199 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10200 %}
10201
10202 ins_pipe(pipe_cmpz_branch);
10203 %}
10204
10205 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10206 match(If cmp (CmpN op1 zero));
10207 effect(USE lbl);
10208
10209 ins_cost(BRANCH_COST * 2);
10210
10211 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10212
10213 ins_encode %{
10214 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10215 %}
10216
10217 ins_pipe(pipe_cmpz_branch);
10218 %}
10219
10220 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10221 match(If cmp (CmpP (DecodeN op1) zero));
10222 effect(USE lbl);
10223
10224 ins_cost(BRANCH_COST * 2);
10225 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10226
10227 ins_encode %{
10228 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10229 %}
10230
10231 ins_pipe(pipe_cmpz_branch);
10232 %}
10233
10234 // ============================================================================
10235 // Conditional Move Instructions
10236
10237 // --------- CMoveI ---------
10238
10239 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10240 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10241 ins_cost(ALU_COST + BRANCH_COST);
10242
10243 format %{
10244 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10245 %}
10246
10247 ins_encode %{
10248 __ enc_cmove($cop$$cmpcode,
10249 as_Register($op1$$reg), as_Register($op2$$reg),
10250 as_Register($dst$$reg), as_Register($src$$reg));
10251 %}
10252
10253 ins_pipe(pipe_class_compare);
10254 %}
10255
10256 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10257 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10258 ins_cost(ALU_COST + BRANCH_COST);
10259
10260 format %{
10261 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10262 %}
10263
10264 ins_encode %{
10265 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10266 as_Register($op1$$reg), as_Register($op2$$reg),
10267 as_Register($dst$$reg), as_Register($src$$reg));
10268 %}
10269
10270 ins_pipe(pipe_class_compare);
10271 %}
10272
10273 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10274 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10275 ins_cost(ALU_COST + BRANCH_COST);
10276
10277 format %{
10278 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10279 %}
10280
10281 ins_encode %{
10282 __ enc_cmove($cop$$cmpcode,
10283 as_Register($op1$$reg), as_Register($op2$$reg),
10284 as_Register($dst$$reg), as_Register($src$$reg));
10285 %}
10286
10287 ins_pipe(pipe_class_compare);
10288 %}
10289
10290 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10291 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10292 ins_cost(ALU_COST + BRANCH_COST);
10293
10294 format %{
10295 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10296 %}
10297
10298 ins_encode %{
10299 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10300 as_Register($op1$$reg), as_Register($op2$$reg),
10301 as_Register($dst$$reg), as_Register($src$$reg));
10302 %}
10303
10304 ins_pipe(pipe_class_compare);
10305 %}
10306
10307 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10308 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10309 ins_cost(ALU_COST + BRANCH_COST);
10310
10311 format %{
10312 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10313 %}
10314
10315 ins_encode %{
10316 __ enc_cmove_cmp_fp($cop$$cmpcode,
10317 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10318 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10319 %}
10320
10321 ins_pipe(pipe_class_compare);
10322 %}
10323
10324 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10325 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10326 ins_cost(ALU_COST + BRANCH_COST);
10327
10328 format %{
10329 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10330 %}
10331
10332 ins_encode %{
10333 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10334 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10335 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10336 %}
10337
10338 ins_pipe(pipe_class_compare);
10339 %}
10340
10341 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10342 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10343 ins_cost(ALU_COST + BRANCH_COST);
10344
10345 format %{
10346 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10347 %}
10348
10349 ins_encode %{
10350 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10351 as_Register($op1$$reg), as_Register($op2$$reg),
10352 as_Register($dst$$reg), as_Register($src$$reg));
10353 %}
10354
10355 ins_pipe(pipe_class_compare);
10356 %}
10357
10358 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10359 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10360 ins_cost(ALU_COST + BRANCH_COST);
10361
10362 format %{
10363 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10364 %}
10365
10366 ins_encode %{
10367 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10368 as_Register($op1$$reg), as_Register($op2$$reg),
10369 as_Register($dst$$reg), as_Register($src$$reg));
10370 %}
10371
10372 ins_pipe(pipe_class_compare);
10373 %}
10374
10375 // --------- CMoveL ---------
10376
10377 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10378 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10379 ins_cost(ALU_COST + BRANCH_COST);
10380
10381 format %{
10382 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10383 %}
10384
10385 ins_encode %{
10386 __ enc_cmove($cop$$cmpcode,
10387 as_Register($op1$$reg), as_Register($op2$$reg),
10388 as_Register($dst$$reg), as_Register($src$$reg));
10389 %}
10390
10391 ins_pipe(pipe_class_compare);
10392 %}
10393
10394 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10395 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10396 ins_cost(ALU_COST + BRANCH_COST);
10397
10398 format %{
10399 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10400 %}
10401
10402 ins_encode %{
10403 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10404 as_Register($op1$$reg), as_Register($op2$$reg),
10405 as_Register($dst$$reg), as_Register($src$$reg));
10406 %}
10407
10408 ins_pipe(pipe_class_compare);
10409 %}
10410
10411 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10412 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10413 ins_cost(ALU_COST + BRANCH_COST);
10414
10415 format %{
10416 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10417 %}
10418
10419 ins_encode %{
10420 __ enc_cmove($cop$$cmpcode,
10421 as_Register($op1$$reg), as_Register($op2$$reg),
10422 as_Register($dst$$reg), as_Register($src$$reg));
10423 %}
10424
10425 ins_pipe(pipe_class_compare);
10426 %}
10427
10428 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10429 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10430 ins_cost(ALU_COST + BRANCH_COST);
10431
10432 format %{
10433 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10434 %}
10435
10436 ins_encode %{
10437 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10438 as_Register($op1$$reg), as_Register($op2$$reg),
10439 as_Register($dst$$reg), as_Register($src$$reg));
10440 %}
10441
10442 ins_pipe(pipe_class_compare);
10443 %}
10444
10445 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10446 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10447 ins_cost(ALU_COST + BRANCH_COST);
10448
10449 format %{
10450 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10451 %}
10452
10453 ins_encode %{
10454 __ enc_cmove_cmp_fp($cop$$cmpcode,
10455 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10456 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10457 %}
10458
10459 ins_pipe(pipe_class_compare);
10460 %}
10461
10462 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10463 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10464 ins_cost(ALU_COST + BRANCH_COST);
10465
10466 format %{
10467 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10468 %}
10469
10470 ins_encode %{
10471 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10472 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10473 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10474 %}
10475
10476 ins_pipe(pipe_class_compare);
10477 %}
10478
10479 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10480 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10481 ins_cost(ALU_COST + BRANCH_COST);
10482
10483 format %{
10484 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10485 %}
10486
10487 ins_encode %{
10488 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10489 as_Register($op1$$reg), as_Register($op2$$reg),
10490 as_Register($dst$$reg), as_Register($src$$reg));
10491 %}
10492
10493 ins_pipe(pipe_class_compare);
10494 %}
10495
10496 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10497 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10498 ins_cost(ALU_COST + BRANCH_COST);
10499
10500 format %{
10501 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10502 %}
10503
10504 ins_encode %{
10505 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10506 as_Register($op1$$reg), as_Register($op2$$reg),
10507 as_Register($dst$$reg), as_Register($src$$reg));
10508 %}
10509
10510 ins_pipe(pipe_class_compare);
10511 %}
10512
10513 // --------- CMoveF ---------
10514
10515 instruct cmovF_cmpI(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOp cop) %{
10516 match(Set dst (CMoveF (Binary cop (CmpI op1 op2)) (Binary dst src)));
10517 ins_cost(ALU_COST + BRANCH_COST);
10518
10519 format %{
10520 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpI\n\t"
10521 %}
10522
10523 ins_encode %{
10524 __ enc_cmove_fp_cmp($cop$$cmpcode,
10525 as_Register($op1$$reg), as_Register($op2$$reg),
10526 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10527 %}
10528
10529 ins_pipe(pipe_class_compare);
10530 %}
10531
10532 instruct cmovF_cmpU(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOpU cop) %{
10533 match(Set dst (CMoveF (Binary cop (CmpU op1 op2)) (Binary dst src)));
10534 ins_cost(ALU_COST + BRANCH_COST);
10535
10536 format %{
10537 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpU\n\t"
10538 %}
10539
10540 ins_encode %{
10541 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10542 as_Register($op1$$reg), as_Register($op2$$reg),
10543 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10544 %}
10545
10546 ins_pipe(pipe_class_compare);
10547 %}
10548
10549 instruct cmovF_cmpL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOp cop) %{
10550 match(Set dst (CMoveF (Binary cop (CmpL op1 op2)) (Binary dst src)));
10551 ins_cost(ALU_COST + BRANCH_COST);
10552
10553 format %{
10554 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpL\n\t"
10555 %}
10556
10557 ins_encode %{
10558 __ enc_cmove_fp_cmp($cop$$cmpcode,
10559 as_Register($op1$$reg), as_Register($op2$$reg),
10560 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10561 %}
10562
10563 ins_pipe(pipe_class_compare);
10564 %}
10565
10566 instruct cmovF_cmpUL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOpU cop) %{
10567 match(Set dst (CMoveF (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10568 ins_cost(ALU_COST + BRANCH_COST);
10569
10570 format %{
10571 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpUL\n\t"
10572 %}
10573
10574 ins_encode %{
10575 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10576 as_Register($op1$$reg), as_Register($op2$$reg),
10577 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10578 %}
10579
10580 ins_pipe(pipe_class_compare);
10581 %}
10582
10583 instruct cmovF_cmpF(fRegF dst, fRegF src, fRegF op1, fRegF op2, cmpOp cop) %{
10584 match(Set dst (CMoveF (Binary cop (CmpF op1 op2)) (Binary dst src)));
10585 ins_cost(ALU_COST + BRANCH_COST);
10586
10587 format %{
10588 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpF\n\t"
10589 %}
10590
10591 ins_encode %{
10592 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10593 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10594 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10595 true /* cmp_single */, true /* cmov_single */);
10596 %}
10597
10598 ins_pipe(pipe_class_compare);
10599 %}
10600
10601 instruct cmovF_cmpD(fRegF dst, fRegF src, fRegD op1, fRegD op2, cmpOp cop) %{
10602 match(Set dst (CMoveF (Binary cop (CmpD op1 op2)) (Binary dst src)));
10603 ins_cost(ALU_COST + BRANCH_COST);
10604
10605 format %{
10606 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpD\n\t"
10607 %}
10608
10609 ins_encode %{
10610 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10611 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10612 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10613 false /* cmp_single */, true /* cmov_single */);
10614 %}
10615
10616 ins_pipe(pipe_class_compare);
10617 %}
10618
10619 instruct cmovF_cmpN(fRegF dst, fRegF src, iRegN op1, iRegN op2, cmpOp cop) %{
10620 match(Set dst (CMoveF (Binary cop (CmpN op1 op2)) (Binary dst src)));
10621 ins_cost(ALU_COST + BRANCH_COST);
10622
10623 format %{
10624 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpN\n\t"
10625 %}
10626
10627 ins_encode %{
10628 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10629 as_Register($op1$$reg), as_Register($op2$$reg),
10630 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10631 %}
10632
10633 ins_pipe(pipe_class_compare);
10634 %}
10635
10636 instruct cmovF_cmpP(fRegF dst, fRegF src, iRegP op1, iRegP op2, cmpOp cop) %{
10637 match(Set dst (CMoveF (Binary cop (CmpP op1 op2)) (Binary dst src)));
10638 ins_cost(ALU_COST + BRANCH_COST);
10639
10640 format %{
10641 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpP\n\t"
10642 %}
10643
10644 ins_encode %{
10645 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10646 as_Register($op1$$reg), as_Register($op2$$reg),
10647 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10648 %}
10649
10650 ins_pipe(pipe_class_compare);
10651 %}
10652
10653 // --------- CMoveD ---------
10654
10655 instruct cmovD_cmpI(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOp cop) %{
10656 match(Set dst (CMoveD (Binary cop (CmpI op1 op2)) (Binary dst src)));
10657 ins_cost(ALU_COST + BRANCH_COST);
10658
10659 format %{
10660 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpI\n\t"
10661 %}
10662
10663 ins_encode %{
10664 __ enc_cmove_fp_cmp($cop$$cmpcode,
10665 as_Register($op1$$reg), as_Register($op2$$reg),
10666 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10667 %}
10668
10669 ins_pipe(pipe_class_compare);
10670 %}
10671
10672 instruct cmovD_cmpU(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOpU cop) %{
10673 match(Set dst (CMoveD (Binary cop (CmpU op1 op2)) (Binary dst src)));
10674 ins_cost(ALU_COST + BRANCH_COST);
10675
10676 format %{
10677 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpU\n\t"
10678 %}
10679
10680 ins_encode %{
10681 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10682 as_Register($op1$$reg), as_Register($op2$$reg),
10683 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10684 %}
10685
10686 ins_pipe(pipe_class_compare);
10687 %}
10688
10689 instruct cmovD_cmpL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOp cop) %{
10690 match(Set dst (CMoveD (Binary cop (CmpL op1 op2)) (Binary dst src)));
10691 ins_cost(ALU_COST + BRANCH_COST);
10692
10693 format %{
10694 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpL\n\t"
10695 %}
10696
10697 ins_encode %{
10698 __ enc_cmove_fp_cmp($cop$$cmpcode,
10699 as_Register($op1$$reg), as_Register($op2$$reg),
10700 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10701 %}
10702
10703 ins_pipe(pipe_class_compare);
10704 %}
10705
10706 instruct cmovD_cmpUL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOpU cop) %{
10707 match(Set dst (CMoveD (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10708 ins_cost(ALU_COST + BRANCH_COST);
10709
10710 format %{
10711 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpUL\n\t"
10712 %}
10713
10714 ins_encode %{
10715 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10716 as_Register($op1$$reg), as_Register($op2$$reg),
10717 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10718 %}
10719
10720 ins_pipe(pipe_class_compare);
10721 %}
10722
10723 instruct cmovD_cmpF(fRegD dst, fRegD src, fRegF op1, fRegF op2, cmpOp cop) %{
10724 match(Set dst (CMoveD (Binary cop (CmpF op1 op2)) (Binary dst src)));
10725 ins_cost(ALU_COST + BRANCH_COST);
10726
10727 format %{
10728 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpF\n\t"
10729 %}
10730
10731 ins_encode %{
10732 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10733 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10734 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10735 true /* cmp_single */, false /* cmov_single */);
10736 %}
10737
10738 ins_pipe(pipe_class_compare);
10739 %}
10740
10741 instruct cmovD_cmpD(fRegD dst, fRegD src, fRegD op1, fRegD op2, cmpOp cop) %{
10742 match(Set dst (CMoveD (Binary cop (CmpD op1 op2)) (Binary dst src)));
10743 ins_cost(ALU_COST + BRANCH_COST);
10744
10745 format %{
10746 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpD\n\t"
10747 %}
10748
10749 ins_encode %{
10750 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10751 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10752 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10753 false /* cmp_single */, false /* cmov_single */);
10754 %}
10755
10756 ins_pipe(pipe_class_compare);
10757 %}
10758
10759 instruct cmovD_cmpN(fRegD dst, fRegD src, iRegN op1, iRegN op2, cmpOp cop) %{
10760 match(Set dst (CMoveD (Binary cop (CmpN op1 op2)) (Binary dst src)));
10761 ins_cost(ALU_COST + BRANCH_COST);
10762
10763 format %{
10764 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpN\n\t"
10765 %}
10766
10767 ins_encode %{
10768 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10769 as_Register($op1$$reg), as_Register($op2$$reg),
10770 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10771 %}
10772
10773 ins_pipe(pipe_class_compare);
10774 %}
10775
10776 instruct cmovD_cmpP(fRegD dst, fRegD src, iRegP op1, iRegP op2, cmpOp cop) %{
10777 match(Set dst (CMoveD (Binary cop (CmpP op1 op2)) (Binary dst src)));
10778 ins_cost(ALU_COST + BRANCH_COST);
10779
10780 format %{
10781 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpP\n\t"
10782 %}
10783
10784 ins_encode %{
10785 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10786 as_Register($op1$$reg), as_Register($op2$$reg),
10787 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10788 %}
10789
10790 ins_pipe(pipe_class_compare);
10791 %}
10792
10793 // ============================================================================
10794 // Procedure Call/Return Instructions
10795
10796 // Call Java Static Instruction
10797 // Note: If this code changes, the corresponding ret_addr_offset() and
10798 // compute_padding() functions will have to be adjusted.
10799 instruct CallStaticJavaDirect(method meth)
10800 %{
10801 match(CallStaticJava);
10802
10803 effect(USE meth);
10804
10805 ins_cost(BRANCH_COST);
10806
10807 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10808
10809 ins_encode(riscv_enc_java_static_call(meth),
10810 riscv_enc_call_epilog);
10811
10812 ins_pipe(pipe_class_call);
10813 ins_alignment(4);
10814 %}
10815
10816 // TO HERE
10817
10818 // Call Java Dynamic Instruction
10819 // Note: If this code changes, the corresponding ret_addr_offset() and
10820 // compute_padding() functions will have to be adjusted.
10821 instruct CallDynamicJavaDirect(method meth)
10822 %{
10823 match(CallDynamicJava);
10824
10825 effect(USE meth);
10826
10827 ins_cost(BRANCH_COST + ALU_COST * 5);
10828
10829 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10830
10831 ins_encode(riscv_enc_java_dynamic_call(meth),
10832 riscv_enc_call_epilog);
10833
10834 ins_pipe(pipe_class_call);
10835 ins_alignment(4);
10836 %}
10837
10838 // Call Runtime Instruction
10839
10840 instruct CallRuntimeDirect(method meth)
10841 %{
10842 match(CallRuntime);
10843
10844 effect(USE meth);
10845
10846 ins_cost(BRANCH_COST);
10847
10848 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10849
10850 ins_encode(riscv_enc_java_to_runtime(meth));
10851
10852 ins_pipe(pipe_class_call);
10853 ins_alignment(4);
10854 %}
10855
10856 // Call Runtime Instruction
10857
10858 instruct CallLeafDirect(method meth)
10859 %{
10860 match(CallLeaf);
10861
10862 effect(USE meth);
10863
10864 ins_cost(BRANCH_COST);
10865
10866 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10867
10868 ins_encode(riscv_enc_java_to_runtime(meth));
10869
10870 ins_pipe(pipe_class_call);
10871 ins_alignment(4);
10872 %}
10873
10874 // Call Runtime Instruction without safepoint and with vector arguments
10875
10876 instruct CallLeafDirectVector(method meth)
10877 %{
10878 match(CallLeafVector);
10879
10880 effect(USE meth);
10881
10882 ins_cost(BRANCH_COST);
10883
10884 format %{ "CALL, runtime leaf vector $meth" %}
10885
10886 ins_encode(riscv_enc_java_to_runtime(meth));
10887
10888 ins_pipe(pipe_class_call);
10889 ins_alignment(4);
10890 %}
10891
10892 // Call Runtime Instruction
10893
10894 // entry point is null, target holds the address to call
10895 instruct CallLeafNoFPIndirect(iRegP target)
10896 %{
10897 predicate(n->as_Call()->entry_point() == nullptr);
10898
10899 match(CallLeafNoFP target);
10900
10901 ins_cost(BRANCH_COST);
10902
10903 format %{ "CALL, runtime leaf nofp indirect $target" %}
10904
10905 ins_encode %{
10906 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
10907 __ jalr($target$$Register);
10908 __ post_call_nop();
10909 %}
10910
10911 ins_pipe(pipe_class_call);
10912 ins_alignment(4);
10913 %}
10914
10915 instruct CallLeafNoFPDirect(method meth)
10916 %{
10917 predicate(n->as_Call()->entry_point() != nullptr);
10918
10919 match(CallLeafNoFP);
10920
10921 effect(USE meth);
10922
10923 ins_cost(BRANCH_COST);
10924
10925 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10926
10927 ins_encode(riscv_enc_java_to_runtime(meth));
10928
10929 ins_pipe(pipe_class_call);
10930 ins_alignment(4);
10931 %}
10932
10933 // ============================================================================
10934 // Partial Subtype Check
10935 //
10936 // superklass array for an instance of the superklass. Set a hidden
10937 // internal cache on a hit (cache is checked with exposed code in
10938 // gen_subtype_check()). Return zero for a hit. The encoding
10939 // ALSO sets flags.
10940
10941 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10942 %{
10943 predicate(!UseSecondarySupersTable);
10944 match(Set result (PartialSubtypeCheck sub super));
10945 effect(KILL tmp, KILL cr);
10946
10947 ins_cost(20 * DEFAULT_COST);
10948 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10949
10950 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10951
10952 opcode(0x1); // Force zero of result reg on hit
10953
10954 ins_pipe(pipe_class_memory);
10955 %}
10956
10957 // Two versions of partialSubtypeCheck, both used when we need to
10958 // search for a super class in the secondary supers array. The first
10959 // is used when we don't know _a priori_ the class being searched
10960 // for. The second, far more common, is used when we do know: this is
10961 // used for instanceof, checkcast, and any case where C2 can determine
10962 // it by constant propagation.
10963
10964 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10965 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10966 iRegP_R16 tmpR16, rFlagsReg cr)
10967 %{
10968 predicate(UseSecondarySupersTable);
10969 match(Set result (PartialSubtypeCheck sub super));
10970 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10971
10972 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10973 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10974
10975 ins_encode %{
10976 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10977 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10978 $tmpR16$$Register, nullptr /*L_success*/);
10979 %}
10980
10981 ins_pipe(pipe_class_memory);
10982 %}
10983
10984 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10985 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10986 %{
10987 predicate(UseSecondarySupersTable);
10988 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10989 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10990
10991 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10992 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10993
10994 ins_encode %{
10995 bool success = false;
10996 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10997 if (InlineSecondarySupersTest) {
10998 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10999 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
11000 $tmpR16$$Register, super_klass_slot);
11001 } else {
11002 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
11003 success = (call != nullptr);
11004 }
11005 if (!success) {
11006 ciEnv::current()->record_failure("CodeCache is full");
11007 return;
11008 }
11009 %}
11010
11011 ins_pipe(pipe_class_memory);
11012 %}
11013
11014 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11015 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11016 %{
11017 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
11018 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11019 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11020
11021 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
11022 ins_encode %{
11023 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11024 __ string_compare($str1$$Register, $str2$$Register,
11025 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11026 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11027 StrIntrinsicNode::UU);
11028 %}
11029 ins_pipe(pipe_class_memory);
11030 %}
11031
11032 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11033 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11034 %{
11035 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
11036 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11037 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11038
11039 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
11040 ins_encode %{
11041 __ string_compare($str1$$Register, $str2$$Register,
11042 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11043 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11044 StrIntrinsicNode::LL);
11045 %}
11046 ins_pipe(pipe_class_memory);
11047 %}
11048
11049 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11050 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11051 %{
11052 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
11053 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11054 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11055
11056 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
11057 ins_encode %{
11058 __ string_compare($str1$$Register, $str2$$Register,
11059 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11060 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11061 StrIntrinsicNode::UL);
11062 %}
11063 ins_pipe(pipe_class_memory);
11064 %}
11065
11066 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11067 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
11068 rFlagsReg cr)
11069 %{
11070 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
11071 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11072 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11073
11074 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
11075 ins_encode %{
11076 __ string_compare($str1$$Register, $str2$$Register,
11077 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11078 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11079 StrIntrinsicNode::LU);
11080 %}
11081 ins_pipe(pipe_class_memory);
11082 %}
11083
11084 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11085 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11086 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11087 %{
11088 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11089 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11090 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11091 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11092
11093 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
11094 ins_encode %{
11095 __ string_indexof($str1$$Register, $str2$$Register,
11096 $cnt1$$Register, $cnt2$$Register,
11097 $tmp1$$Register, $tmp2$$Register,
11098 $tmp3$$Register, $tmp4$$Register,
11099 $tmp5$$Register, $tmp6$$Register,
11100 $result$$Register, StrIntrinsicNode::UU);
11101 %}
11102 ins_pipe(pipe_class_memory);
11103 %}
11104
11105 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11106 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11107 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11108 %{
11109 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11110 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11111 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11112 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11113
11114 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
11115 ins_encode %{
11116 __ string_indexof($str1$$Register, $str2$$Register,
11117 $cnt1$$Register, $cnt2$$Register,
11118 $tmp1$$Register, $tmp2$$Register,
11119 $tmp3$$Register, $tmp4$$Register,
11120 $tmp5$$Register, $tmp6$$Register,
11121 $result$$Register, StrIntrinsicNode::LL);
11122 %}
11123 ins_pipe(pipe_class_memory);
11124 %}
11125
11126 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11127 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11128 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11129 %{
11130 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11131 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11132 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11133 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11134 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
11135
11136 ins_encode %{
11137 __ string_indexof($str1$$Register, $str2$$Register,
11138 $cnt1$$Register, $cnt2$$Register,
11139 $tmp1$$Register, $tmp2$$Register,
11140 $tmp3$$Register, $tmp4$$Register,
11141 $tmp5$$Register, $tmp6$$Register,
11142 $result$$Register, StrIntrinsicNode::UL);
11143 %}
11144 ins_pipe(pipe_class_memory);
11145 %}
11146
11147 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11148 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11149 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11150 %{
11151 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11152 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11153 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11154 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11155
11156 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
11157
11158 ins_encode %{
11159 int icnt2 = (int)$int_cnt2$$constant;
11160 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11161 $cnt1$$Register, zr,
11162 $tmp1$$Register, $tmp2$$Register,
11163 $tmp3$$Register, $tmp4$$Register,
11164 icnt2, $result$$Register, StrIntrinsicNode::UU);
11165 %}
11166 ins_pipe(pipe_class_memory);
11167 %}
11168
11169 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11170 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11171 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11172 %{
11173 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11174 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11175 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11176 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11177
11178 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
11179 ins_encode %{
11180 int icnt2 = (int)$int_cnt2$$constant;
11181 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11182 $cnt1$$Register, zr,
11183 $tmp1$$Register, $tmp2$$Register,
11184 $tmp3$$Register, $tmp4$$Register,
11185 icnt2, $result$$Register, StrIntrinsicNode::LL);
11186 %}
11187 ins_pipe(pipe_class_memory);
11188 %}
11189
11190 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11191 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11192 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11193 %{
11194 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11195 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11196 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11197 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11198
11199 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
11200 ins_encode %{
11201 int icnt2 = (int)$int_cnt2$$constant;
11202 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11203 $cnt1$$Register, zr,
11204 $tmp1$$Register, $tmp2$$Register,
11205 $tmp3$$Register, $tmp4$$Register,
11206 icnt2, $result$$Register, StrIntrinsicNode::UL);
11207 %}
11208 ins_pipe(pipe_class_memory);
11209 %}
11210
11211 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11212 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11213 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11214 %{
11215 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11216 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11217 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11218 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11219
11220 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11221 ins_encode %{
11222 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11223 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11224 $tmp3$$Register, $tmp4$$Register, false /* isU */);
11225 %}
11226 ins_pipe(pipe_class_memory);
11227 %}
11228
11229
11230 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11231 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11232 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11233 %{
11234 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11235 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11236 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11237 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11238
11239 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11240 ins_encode %{
11241 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11242 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11243 $tmp3$$Register, $tmp4$$Register, true /* isL */);
11244 %}
11245 ins_pipe(pipe_class_memory);
11246 %}
11247
11248 // ============================================================================
11249 // clearing of an array
11250
11251 instruct clearArray_reg_reg_immL0(iRegL_R29 cnt, iRegP_R28 base, immL0 zero,
11252 iRegP_R30 tmp1, iRegP_R31 tmp2, rFlagsReg cr,
11253 Universe dummy)
11254 %{
11255 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
11256 predicate(UseBlockZeroing || !UseRVV);
11257 match(Set dummy (ClearArray (Binary cnt base) zero));
11258 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
11259
11260 ins_cost(4 * DEFAULT_COST);
11261 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg_immL0" %}
11262
11263 ins_encode %{
11264 address tpc = __ zero_words($base$$Register, $cnt$$Register);
11265 if (tpc == nullptr) {
11266 ciEnv::current()->record_failure("CodeCache is full");
11267 return;
11268 }
11269 %}
11270
11271 ins_pipe(pipe_class_memory);
11272 %}
11273
11274 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegL val,
11275 iRegP_R30 tmp1, iRegP_R31 tmp2, rFlagsReg cr,
11276 Universe dummy)
11277 %{
11278 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
11279 predicate(((ClearArrayNode*)n)->word_copy_only());
11280 match(Set dummy (ClearArray (Binary cnt base) val));
11281 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
11282
11283 ins_cost(4 * DEFAULT_COST);
11284 format %{ "ClearArray $cnt, $base, $val\t#@clearArray_reg_reg" %}
11285
11286 ins_encode %{
11287 __ fill_words($base$$Register, $cnt$$Register, $val$$Register);
11288 %}
11289
11290 ins_pipe(pipe_class_memory);
11291 %}
11292
11293 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, immL0 zero, Universe dummy, rFlagsReg cr)
11294 %{
11295 predicate(!UseRVV
11296 && (uint64_t)n->in(2)->in(1)->get_long()
11297 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord)
11298 && !((ClearArrayNode*)n)->word_copy_only());
11299 match(Set dummy (ClearArray (Binary cnt base) zero));
11300 effect(USE_KILL base, KILL cr);
11301
11302 ins_cost(4 * DEFAULT_COST);
11303 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
11304
11305 ins_encode %{
11306 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
11307 %}
11308
11309 ins_pipe(pipe_class_memory);
11310 %}
11311
11312 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
11313 iRegI_R10 result, rFlagsReg cr)
11314 %{
11315 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11316 match(Set result (StrEquals (Binary str1 str2) cnt));
11317 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
11318
11319 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
11320 ins_encode %{
11321 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11322 __ string_equals($str1$$Register, $str2$$Register,
11323 $result$$Register, $cnt$$Register);
11324 %}
11325 ins_pipe(pipe_class_memory);
11326 %}
11327
11328 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11329 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11330 %{
11331 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11332 match(Set result (AryEq ary1 ary2));
11333 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11334
11335 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
11336 ins_encode %{
11337 __ arrays_equals($ary1$$Register, $ary2$$Register,
11338 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11339 $result$$Register, 1);
11340 %}
11341 ins_pipe(pipe_class_memory);
11342 %}
11343
11344 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11345 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11346 %{
11347 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11348 match(Set result (AryEq ary1 ary2));
11349 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11350
11351 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
11352 ins_encode %{
11353 __ arrays_equals($ary1$$Register, $ary2$$Register,
11354 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11355 $result$$Register, 2);
11356 %}
11357 ins_pipe(pipe_class_memory);
11358 %}
11359
11360 // fast ArraysSupport.vectorizedHashCode
11361 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
11362 iRegLNoSp tmp1, iRegLNoSp tmp2,
11363 iRegLNoSp tmp3, iRegLNoSp tmp4,
11364 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
11365 %{
11366 predicate(!UseRVV);
11367 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
11368 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
11369 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
11370
11371 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
11372 ins_encode %{
11373 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11374 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11375 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11376 (BasicType)$basic_type$$constant);
11377 %}
11378 ins_pipe(pipe_class_memory);
11379 %}
11380
11381 // ============================================================================
11382 // Safepoint Instructions
11383
11384 instruct safePoint(iRegP poll)
11385 %{
11386 match(SafePoint poll);
11387
11388 ins_cost(2 * LOAD_COST);
11389 format %{
11390 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11391 %}
11392 ins_encode %{
11393 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11394 %}
11395 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11396 %}
11397
11398 // ============================================================================
11399 // This name is KNOWN by the ADLC and cannot be changed.
11400 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11401 // for this guy.
11402 instruct tlsLoadP(javaThread_RegP dst)
11403 %{
11404 match(Set dst (ThreadLocal));
11405
11406 ins_cost(0);
11407
11408 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11409
11410 size(0);
11411
11412 ins_encode( /*empty*/ );
11413
11414 ins_pipe(pipe_class_empty);
11415 %}
11416
11417 // inlined locking and unlocking
11418 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11419 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11420 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11421 %{
11422 match(Set cr (FastLock object box));
11423 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11424
11425 ins_cost(10 * DEFAULT_COST);
11426 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11427
11428 ins_encode %{
11429 __ fast_lock($object$$Register, $box$$Register,
11430 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11431 %}
11432
11433 ins_pipe(pipe_serial);
11434 %}
11435
11436 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11437 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11438 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11439 %{
11440 match(Set cr (FastUnlock object box));
11441 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11442
11443 ins_cost(10 * DEFAULT_COST);
11444 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11445
11446 ins_encode %{
11447 __ fast_unlock($object$$Register, $box$$Register,
11448 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11449 %}
11450
11451 ins_pipe(pipe_serial);
11452 %}
11453
11454 // Tail Call; Jump from runtime stub to Java code.
11455 // Also known as an 'interprocedural jump'.
11456 // Target of jump will eventually return to caller.
11457 // TailJump below removes the return address.
11458 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11459 // emitted just above the TailCall which has reset fp to the caller state.
11460 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11461 %{
11462 match(TailCall jump_target method_oop);
11463
11464 ins_cost(BRANCH_COST);
11465
11466 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11467
11468 ins_encode(riscv_enc_tail_call(jump_target));
11469
11470 ins_pipe(pipe_class_call);
11471 %}
11472
11473 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11474 %{
11475 match(TailJump jump_target ex_oop);
11476
11477 ins_cost(ALU_COST + BRANCH_COST);
11478
11479 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11480
11481 ins_encode(riscv_enc_tail_jmp(jump_target));
11482
11483 ins_pipe(pipe_class_call);
11484 %}
11485
11486 // Forward exception.
11487 instruct ForwardExceptionjmp()
11488 %{
11489 match(ForwardException);
11490
11491 ins_cost(BRANCH_COST);
11492
11493 format %{ "j forward_exception_stub\t#@ForwardException" %}
11494
11495 ins_encode %{
11496 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11497 %}
11498
11499 ins_pipe(pipe_class_call);
11500 %}
11501
11502 // Create exception oop: created by stack-crawling runtime code.
11503 // Created exception is now available to this handler, and is setup
11504 // just prior to jumping to this handler. No code emitted.
11505 instruct CreateException(iRegP_R10 ex_oop)
11506 %{
11507 match(Set ex_oop (CreateEx));
11508
11509 ins_cost(0);
11510 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11511
11512 size(0);
11513
11514 ins_encode( /*empty*/ );
11515
11516 ins_pipe(pipe_class_empty);
11517 %}
11518
11519 // Rethrow exception: The exception oop will come in the first
11520 // argument position. Then JUMP (not call) to the rethrow stub code.
11521 instruct RethrowException()
11522 %{
11523 match(Rethrow);
11524
11525 ins_cost(BRANCH_COST);
11526
11527 format %{ "j rethrow_stub\t#@RethrowException" %}
11528
11529 ins_encode(riscv_enc_rethrow());
11530
11531 ins_pipe(pipe_class_call);
11532 %}
11533
11534 // Return Instruction
11535 // epilog node loads ret address into ra as part of frame pop
11536 instruct Ret()
11537 %{
11538 match(Return);
11539
11540 ins_cost(BRANCH_COST);
11541 format %{ "ret\t// return register, #@Ret" %}
11542
11543 ins_encode(riscv_enc_ret());
11544
11545 ins_pipe(pipe_branch);
11546 %}
11547
11548 // Die now.
11549 instruct ShouldNotReachHere() %{
11550 match(Halt);
11551
11552 ins_cost(BRANCH_COST);
11553
11554 format %{ "#@ShouldNotReachHere" %}
11555
11556 ins_encode %{
11557 if (is_reachable()) {
11558 const char* str = __ code_string(_halt_reason);
11559 __ stop(str);
11560 }
11561 %}
11562
11563 ins_pipe(pipe_class_default);
11564 %}
11565
11566
11567 //----------PEEPHOLE RULES-----------------------------------------------------
11568 // These must follow all instruction definitions as they use the names
11569 // defined in the instructions definitions.
11570 //
11571 // peepmatch ( root_instr_name [preceding_instruction]* );
11572 //
11573 // peepconstraint %{
11574 // (instruction_number.operand_name relational_op instruction_number.operand_name
11575 // [, ...] );
11576 // // instruction numbers are zero-based using left to right order in peepmatch
11577 //
11578 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11579 // // provide an instruction_number.operand_name for each operand that appears
11580 // // in the replacement instruction's match rule
11581 //
11582 // ---------VM FLAGS---------------------------------------------------------
11583 //
11584 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11585 //
11586 // Each peephole rule is given an identifying number starting with zero and
11587 // increasing by one in the order seen by the parser. An individual peephole
11588 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11589 // on the command-line.
11590 //
11591 // ---------CURRENT LIMITATIONS----------------------------------------------
11592 //
11593 // Only match adjacent instructions in same basic block
11594 // Only equality constraints
11595 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11596 // Only one replacement instruction
11597 //
11598 //----------SMARTSPILL RULES---------------------------------------------------
11599 // These must follow all instruction definitions as they use the names
11600 // defined in the instructions definitions.
11601
11602 // Local Variables:
11603 // mode: c++
11604 // End: