1 //
2 // Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_deopt_handler(C2_MacroAssembler* masm);
1053
1054 static uint size_deopt_handler() {
1055 // count far call + j
1056 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1057 }
1058 };
1059
1060 class Node::PD {
1061 public:
1062 enum NodeFlags {
1063 _last_flag = Node::_last_flag
1064 };
1065 };
1066
1067 bool is_CAS(int opcode, bool maybe_volatile);
1068
1069 // predicate controlling translation of CompareAndSwapX
1070 bool needs_acquiring_load_reserved(const Node *load);
1071
1072 // predicate controlling addressing modes
1073 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1074 %}
1075
1076 source %{
1077
1078 // Derived RegMask with conditionally allocatable registers
1079
1080 RegMask _ANY_REG32_mask;
1081 RegMask _ANY_REG_mask;
1082 RegMask _PTR_REG_mask;
1083 RegMask _NO_SPECIAL_REG32_mask;
1084 RegMask _NO_SPECIAL_REG_mask;
1085 RegMask _NO_SPECIAL_PTR_REG_mask;
1086 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1087
1088 void reg_mask_init() {
1089
1090 _ANY_REG32_mask.assignFrom(_ALL_REG32_mask);
1091 _ANY_REG32_mask.remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1092
1093 _ANY_REG_mask.assignFrom(_ALL_REG_mask);
1094 _ANY_REG_mask.subtract(_ZR_REG_mask);
1095
1096 _PTR_REG_mask.assignFrom(_ALL_REG_mask);
1097 _PTR_REG_mask.subtract(_ZR_REG_mask);
1098
1099 _NO_SPECIAL_REG32_mask.assignFrom(_ALL_REG32_mask);
1100 _NO_SPECIAL_REG32_mask.subtract(_NON_ALLOCATABLE_REG32_mask);
1101
1102 _NO_SPECIAL_REG_mask.assignFrom(_ALL_REG_mask);
1103 _NO_SPECIAL_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1104
1105 _NO_SPECIAL_PTR_REG_mask.assignFrom(_ALL_REG_mask);
1106 _NO_SPECIAL_PTR_REG_mask.subtract(_NON_ALLOCATABLE_REG_mask);
1107
1108 // x27 is not allocatable when compressed oops is on
1109 if (UseCompressedOops) {
1110 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1111 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1112 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1113 }
1114
1115 // x8 is not allocatable when PreserveFramePointer is on
1116 if (PreserveFramePointer) {
1117 _NO_SPECIAL_REG32_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1118 _NO_SPECIAL_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1119 _NO_SPECIAL_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1120 }
1121
1122 _NO_SPECIAL_NO_FP_PTR_REG_mask.assignFrom(_NO_SPECIAL_PTR_REG_mask);
1123 _NO_SPECIAL_NO_FP_PTR_REG_mask.remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 }
1125
1126 void PhaseOutput::pd_perform_mach_node_analysis() {
1127 }
1128
1129 int MachNode::pd_alignment_required() const {
1130 return 1;
1131 }
1132
1133 int MachNode::compute_padding(int current_offset) const {
1134 return 0;
1135 }
1136
1137 // is_CAS(int opcode, bool maybe_volatile)
1138 //
1139 // return true if opcode is one of the possible CompareAndSwapX
1140 // values otherwise false.
1141 bool is_CAS(int opcode, bool maybe_volatile)
1142 {
1143 switch (opcode) {
1144 // We handle these
1145 case Op_CompareAndSwapI:
1146 case Op_CompareAndSwapL:
1147 case Op_CompareAndSwapP:
1148 case Op_CompareAndSwapN:
1149 case Op_ShenandoahCompareAndSwapP:
1150 case Op_ShenandoahCompareAndSwapN:
1151 case Op_CompareAndSwapB:
1152 case Op_CompareAndSwapS:
1153 case Op_GetAndSetI:
1154 case Op_GetAndSetL:
1155 case Op_GetAndSetP:
1156 case Op_GetAndSetN:
1157 case Op_GetAndAddI:
1158 case Op_GetAndAddL:
1159 return true;
1160 case Op_CompareAndExchangeI:
1161 case Op_CompareAndExchangeN:
1162 case Op_CompareAndExchangeB:
1163 case Op_CompareAndExchangeS:
1164 case Op_CompareAndExchangeL:
1165 case Op_CompareAndExchangeP:
1166 case Op_WeakCompareAndSwapB:
1167 case Op_WeakCompareAndSwapS:
1168 case Op_WeakCompareAndSwapI:
1169 case Op_WeakCompareAndSwapL:
1170 case Op_WeakCompareAndSwapP:
1171 case Op_WeakCompareAndSwapN:
1172 case Op_ShenandoahWeakCompareAndSwapP:
1173 case Op_ShenandoahWeakCompareAndSwapN:
1174 case Op_ShenandoahCompareAndExchangeP:
1175 case Op_ShenandoahCompareAndExchangeN:
1176 return maybe_volatile;
1177 default:
1178 return false;
1179 }
1180 }
1181
1182 constexpr uint64_t MAJIK_DWORD = 0xabbaabbaabbaabbaull;
1183
1184 // predicate controlling translation of CAS
1185 //
1186 // returns true if CAS needs to use an acquiring load otherwise false
1187 bool needs_acquiring_load_reserved(const Node *n)
1188 {
1189 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1190
1191 LoadStoreNode* ldst = n->as_LoadStore();
1192 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1193 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1194 } else {
1195 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1196 }
1197 // so we can just return true here
1198 return true;
1199 }
1200 #define __ masm->
1201
1202 // advance declarations for helper functions to convert register
1203 // indices to register objects
1204
1205 // the ad file has to provide implementations of certain methods
1206 // expected by the generic code
1207 //
1208 // REQUIRED FUNCTIONALITY
1209
1210 //=============================================================================
1211
1212 // !!!!! Special hack to get all types of calls to specify the byte offset
1213 // from the start of the call to the point where the return address
1214 // will point.
1215
1216 int MachCallStaticJavaNode::ret_addr_offset()
1217 {
1218 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1219 }
1220
1221 int MachCallDynamicJavaNode::ret_addr_offset()
1222 {
1223 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1224 }
1225
1226 int MachCallRuntimeNode::ret_addr_offset() {
1227 // For address inside the code cache the call will be:
1228 // auipc + jalr
1229 // For real runtime callouts it will be 8 instructions
1230 // see riscv_enc_java_to_runtime
1231 // la(t0, retaddr) -> auipc + addi
1232 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1233 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1234 // jalr(t1, offset) -> jalr
1235 if (CodeCache::contains(_entry_point)) {
1236 return 2 * NativeInstruction::instruction_size;
1237 } else {
1238 return 8 * NativeInstruction::instruction_size;
1239 }
1240 }
1241
1242 //
1243 // Compute padding required for nodes which need alignment
1244 //
1245
1246 // With RVC a call instruction may get 2-byte aligned.
1247 // The address of the call instruction needs to be 4-byte aligned to
1248 // ensure that it does not span a cache line so that it can be patched.
1249 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1250 {
1251 // to make sure the address of jal 4-byte aligned.
1252 return align_up(current_offset, alignment_required()) - current_offset;
1253 }
1254
1255 // With RVC a call instruction may get 2-byte aligned.
1256 // The address of the call instruction needs to be 4-byte aligned to
1257 // ensure that it does not span a cache line so that it can be patched.
1258 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1259 {
1260 // skip the movptr2 in MacroAssembler::ic_call():
1261 // lui, lui, slli, add, addi
1262 // Though movptr2() has already 4-byte aligned with or without RVC,
1263 // We need to prevent from further changes by explicitly calculating the size.
1264 current_offset += NativeMovConstReg::movptr2_instruction_size;
1265 // to make sure the address of jal 4-byte aligned.
1266 return align_up(current_offset, alignment_required()) - current_offset;
1267 }
1268
1269 int CallRuntimeDirectNode::compute_padding(int current_offset) const
1270 {
1271 return align_up(current_offset, alignment_required()) - current_offset;
1272 }
1273
1274 int CallLeafDirectNode::compute_padding(int current_offset) const
1275 {
1276 return align_up(current_offset, alignment_required()) - current_offset;
1277 }
1278
1279 int CallLeafDirectVectorNode::compute_padding(int current_offset) const
1280 {
1281 return align_up(current_offset, alignment_required()) - current_offset;
1282 }
1283
1284 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const
1285 {
1286 return align_up(current_offset, alignment_required()) - current_offset;
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1293 assert_cond(st != nullptr);
1294 st->print("BREAKPOINT");
1295 }
1296 #endif
1297
1298 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1299 __ ebreak();
1300 }
1301
1302 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1303 return MachNode::size(ra_);
1304 }
1305
1306 //=============================================================================
1307
1308 #ifndef PRODUCT
1309 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1310 st->print("nop \t# %d bytes pad for loops and calls", _count);
1311 }
1312 #endif
1313
1314 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1315 Assembler::CompressibleScope scope(masm); // nops shall be 2-byte under RVC for alignment purposes.
1316 for (int i = 0; i < _count; i++) {
1317 __ nop();
1318 }
1319 }
1320
1321 uint MachNopNode::size(PhaseRegAlloc*) const {
1322 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1323 }
1324
1325 //=============================================================================
1326 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY;
1327
1328 int ConstantTable::calculate_table_base_offset() const {
1329 return 0; // absolute addressing, no offset
1330 }
1331
1332 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1333 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1334 ShouldNotReachHere();
1335 }
1336
1337 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1338 // Empty encoding
1339 }
1340
1341 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1342 return 0;
1343 }
1344
1345 #ifndef PRODUCT
1346 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1347 assert_cond(st != nullptr);
1348 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1349 }
1350 #endif
1351
1352 #ifndef PRODUCT
1353 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1354 assert_cond(st != nullptr && ra_ != nullptr);
1355 Compile* C = ra_->C;
1356
1357 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1358
1359 if (C->output()->need_stack_bang(framesize)) {
1360 st->print("# stack bang size=%d\n\t", framesize);
1361 }
1362
1363 st->print("sub sp, sp, #%d\n\t", framesize);
1364 st->print("sd fp, [sp, #%d]\n\t", framesize - 2 * wordSize);
1365 st->print("sd ra, [sp, #%d]\n\t", framesize - wordSize);
1366 if (PreserveFramePointer) { st->print("add fp, sp, #%d\n\t", framesize); }
1367
1368 if (VerifyStackAtCalls) {
1369 st->print("mv t2, %ld\n\t", MAJIK_DWORD);
1370 st->print("sd t2, [sp, #%d]\n\t", framesize - 3 * wordSize);
1371 }
1372
1373 if (C->stub_function() == nullptr) {
1374 st->print("ld t0, [guard]\n\t");
1375 st->print("membar LoadLoad\n\t");
1376 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1377 st->print("beq t0, t1, skip\n\t");
1378 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1379 st->print("j skip\n\t");
1380 st->print("guard: int\n\t");
1381 st->print("skip:\n\t");
1382 }
1383 }
1384 #endif
1385
1386 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1387 assert_cond(ra_ != nullptr);
1388 Compile* C = ra_->C;
1389
1390 // n.b. frame size includes space for return pc and fp
1391 const int framesize = C->output()->frame_size_in_bytes();
1392
1393 assert_cond(C != nullptr);
1394
1395 if (C->clinit_barrier_on_entry()) {
1396 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1397
1398 Label L_skip_barrier;
1399
1400 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1401 __ clinit_barrier(t1, t0, &L_skip_barrier);
1402 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1403 __ bind(L_skip_barrier);
1404 }
1405
1406 int bangsize = C->output()->bang_size_in_bytes();
1407 if (C->output()->need_stack_bang(bangsize)) {
1408 __ generate_stack_overflow_check(bangsize);
1409 }
1410
1411 __ build_frame(framesize);
1412
1413 if (VerifyStackAtCalls) {
1414 __ mv(t2, MAJIK_DWORD);
1415 __ sd(t2, Address(sp, framesize - 3 * wordSize));
1416 }
1417
1418 if (C->stub_function() == nullptr) {
1419 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1420 // Dummy labels for just measuring the code size
1421 Label dummy_slow_path;
1422 Label dummy_continuation;
1423 Label dummy_guard;
1424 Label* slow_path = &dummy_slow_path;
1425 Label* continuation = &dummy_continuation;
1426 Label* guard = &dummy_guard;
1427 if (!Compile::current()->output()->in_scratch_emit_size()) {
1428 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1429 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1430 Compile::current()->output()->add_stub(stub);
1431 slow_path = &stub->entry();
1432 continuation = &stub->continuation();
1433 guard = &stub->guard();
1434 }
1435 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1436 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1437 }
1438
1439 C->output()->set_frame_complete(__ offset());
1440
1441 if (C->has_mach_constant_base_node()) {
1442 // NOTE: We set the table base offset here because users might be
1443 // emitted before MachConstantBaseNode.
1444 ConstantTable& constant_table = C->output()->constant_table();
1445 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1446 }
1447 }
1448
1449 int MachPrologNode::reloc() const
1450 {
1451 return 0;
1452 }
1453
1454 //=============================================================================
1455
1456 #ifndef PRODUCT
1457 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1458 assert_cond(st != nullptr && ra_ != nullptr);
1459 Compile* C = ra_->C;
1460 assert_cond(C != nullptr);
1461 int framesize = C->output()->frame_size_in_bytes();
1462
1463 st->print("# pop frame %d\n\t", framesize);
1464
1465 if (framesize == 0) {
1466 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1467 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1468 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1469 } else {
1470 st->print("add sp, sp, #%d\n\t", framesize);
1471 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1472 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1473 }
1474
1475 if (do_polling() && C->is_method_compilation()) {
1476 st->print("# test polling word\n\t");
1477 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1478 st->print("bgtu sp, t0, #slow_path");
1479 }
1480 }
1481 #endif
1482
1483 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1484 assert_cond(ra_ != nullptr);
1485 Compile* C = ra_->C;
1486 assert_cond(C != nullptr);
1487 int framesize = C->output()->frame_size_in_bytes();
1488
1489 __ remove_frame(framesize);
1490
1491 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1492 __ reserved_stack_check();
1493 }
1494
1495 if (do_polling() && C->is_method_compilation()) {
1496 Label dummy_label;
1497 Label* code_stub = &dummy_label;
1498 if (!C->output()->in_scratch_emit_size()) {
1499 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1500 C->output()->add_stub(stub);
1501 code_stub = &stub->entry();
1502 }
1503 __ relocate(relocInfo::poll_return_type);
1504 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
1505 }
1506 }
1507
1508 int MachEpilogNode::reloc() const {
1509 // Return number of relocatable values contained in this instruction.
1510 return 1; // 1 for polling page.
1511 }
1512 const Pipeline * MachEpilogNode::pipeline() const {
1513 return MachNode::pipeline_class();
1514 }
1515
1516 //=============================================================================
1517
1518 // Figure out which register class each belongs in: rc_int, rc_float or
1519 // rc_stack.
1520 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1521
1522 static enum RC rc_class(OptoReg::Name reg) {
1523
1524 if (reg == OptoReg::Bad) {
1525 return rc_bad;
1526 }
1527
1528 // we have 30 int registers * 2 halves
1529 // (t0 and t1 are omitted)
1530 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1531 if (reg < slots_of_int_registers) {
1532 return rc_int;
1533 }
1534
1535 // we have 32 float register * 2 halves
1536 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1537 if (reg < slots_of_int_registers + slots_of_float_registers) {
1538 return rc_float;
1539 }
1540
1541 // we have 32 vector register * 4 halves
1542 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1543 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1544 return rc_vector;
1545 }
1546
1547 // Between vector regs & stack is the flags regs.
1548 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1549
1550 return rc_stack;
1551 }
1552
1553 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1554 assert_cond(ra_ != nullptr);
1555 Compile* C = ra_->C;
1556
1557 // Get registers to move.
1558 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1559 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1560 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1561 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1562
1563 enum RC src_hi_rc = rc_class(src_hi);
1564 enum RC src_lo_rc = rc_class(src_lo);
1565 enum RC dst_hi_rc = rc_class(dst_hi);
1566 enum RC dst_lo_rc = rc_class(dst_lo);
1567
1568 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1569
1570 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1571 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1572 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1573 "expected aligned-adjacent pairs");
1574 }
1575
1576 if (src_lo == dst_lo && src_hi == dst_hi) {
1577 return 0; // Self copy, no move.
1578 }
1579
1580 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1581 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1582 int src_offset = ra_->reg2offset(src_lo);
1583 int dst_offset = ra_->reg2offset(dst_lo);
1584
1585 if (bottom_type()->isa_vect() != nullptr) {
1586 uint ireg = ideal_reg();
1587 if (ireg == Op_VecA && masm) {
1588 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1589 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1590 // stack to stack
1591 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1592 vector_reg_size_in_bytes);
1593 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1594 // vpr to stack
1595 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1596 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1597 // stack to vpr
1598 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1599 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1600 // vpr to vpr
1601 __ vsetvli_helper(T_BYTE, MaxVectorSize);
1602 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1603 } else {
1604 ShouldNotReachHere();
1605 }
1606 } else if (bottom_type()->isa_vectmask() && masm) {
1607 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1608 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1609 // stack to stack
1610 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1611 vmask_size_in_bytes);
1612 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1613 // vmask to stack
1614 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1615 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1616 // stack to vmask
1617 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1618 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1619 // vmask to vmask
1620 __ vsetvli_helper(T_BYTE, MaxVectorSize >> 3);
1621 __ vmv_v_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1622 } else {
1623 ShouldNotReachHere();
1624 }
1625 }
1626 } else if (masm != nullptr) {
1627 switch (src_lo_rc) {
1628 case rc_int:
1629 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1630 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1631 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1632 } else {
1633 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1634 }
1635 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1636 if (is64) {
1637 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1638 as_Register(Matcher::_regEncode[src_lo]));
1639 } else {
1640 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1641 as_Register(Matcher::_regEncode[src_lo]));
1642 }
1643 } else { // gpr --> stack spill
1644 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1645 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1646 }
1647 break;
1648 case rc_float:
1649 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1650 if (is64) {
1651 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1652 as_FloatRegister(Matcher::_regEncode[src_lo]));
1653 } else {
1654 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1655 as_FloatRegister(Matcher::_regEncode[src_lo]));
1656 }
1657 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1658 if (is64) {
1659 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1660 as_FloatRegister(Matcher::_regEncode[src_lo]));
1661 } else {
1662 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1663 as_FloatRegister(Matcher::_regEncode[src_lo]));
1664 }
1665 } else { // fpr --> stack spill
1666 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1667 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1668 is64, dst_offset);
1669 }
1670 break;
1671 case rc_stack:
1672 if (dst_lo_rc == rc_int) { // stack --> gpr load
1673 if (this->ideal_reg() == Op_RegI) {
1674 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1675 } else { // // zero extended for narrow oop or klass
1676 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1677 }
1678 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1679 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1680 is64, src_offset);
1681 } else { // stack --> stack copy
1682 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1683 if (this->ideal_reg() == Op_RegI) {
1684 __ unspill(t0, is64, src_offset);
1685 } else { // zero extended for narrow oop or klass
1686 __ unspillu(t0, is64, src_offset);
1687 }
1688 __ spill(t0, is64, dst_offset);
1689 }
1690 break;
1691 default:
1692 ShouldNotReachHere();
1693 }
1694 }
1695
1696 if (st != nullptr) {
1697 st->print("spill ");
1698 if (src_lo_rc == rc_stack) {
1699 st->print("[sp, #%d] -> ", src_offset);
1700 } else {
1701 st->print("%s -> ", Matcher::regName[src_lo]);
1702 }
1703 if (dst_lo_rc == rc_stack) {
1704 st->print("[sp, #%d]", dst_offset);
1705 } else {
1706 st->print("%s", Matcher::regName[dst_lo]);
1707 }
1708 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1709 int vsize = 0;
1710 if (ideal_reg() == Op_VecA) {
1711 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1712 } else {
1713 ShouldNotReachHere();
1714 }
1715 st->print("\t# vector spill size = %d", vsize);
1716 } else if (ideal_reg() == Op_RegVectMask) {
1717 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1718 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1719 st->print("\t# vmask spill size = %d", vsize);
1720 } else {
1721 st->print("\t# spill size = %d", is64 ? 64 : 32);
1722 }
1723 }
1724
1725 return 0;
1726 }
1727
1728 #ifndef PRODUCT
1729 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1730 if (ra_ == nullptr) {
1731 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1732 } else {
1733 implementation(nullptr, ra_, false, st);
1734 }
1735 }
1736 #endif
1737
1738 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1739 implementation(masm, ra_, false, nullptr);
1740 }
1741
1742 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1743 return MachNode::size(ra_);
1744 }
1745
1746 //=============================================================================
1747
1748 #ifndef PRODUCT
1749 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1750 assert_cond(ra_ != nullptr && st != nullptr);
1751 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1752 int reg = ra_->get_reg_first(this);
1753 st->print("add %s, sp, #%d\t# box lock",
1754 Matcher::regName[reg], offset);
1755 }
1756 #endif
1757
1758 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1759 Assembler::IncompressibleScope scope(masm); // Fixed length: see BoxLockNode::size()
1760
1761 assert_cond(ra_ != nullptr);
1762 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1763 int reg = ra_->get_encode(this);
1764
1765 if (Assembler::is_simm12(offset)) {
1766 __ addi(as_Register(reg), sp, offset);
1767 } else {
1768 __ li32(t0, offset);
1769 __ add(as_Register(reg), sp, t0);
1770 }
1771 }
1772
1773 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1774 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1775 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1776
1777 if (Assembler::is_simm12(offset)) {
1778 return NativeInstruction::instruction_size;
1779 } else {
1780 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1781 }
1782 }
1783
1784 //=============================================================================
1785
1786 #ifndef PRODUCT
1787 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1788 {
1789 Unimplemented();
1790 }
1791 #endif
1792
1793 void MachVEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc* ra_) const
1794 {
1795 Unimplemented();
1796 }
1797
1798 #ifndef PRODUCT
1799 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1800 {
1801 assert_cond(st != nullptr);
1802 st->print_cr("# MachUEPNode");
1803 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1804 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1805 st->print_cr("\tbeq t1, t2, ic_hit");
1806 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1807 st->print_cr("\tic_hit:");
1808 }
1809 #endif
1810
1811 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1812 {
1813 // This is the unverified entry point.
1814 __ ic_check(CodeEntryAlignment);
1815
1816 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1817 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1818 }
1819
1820 // REQUIRED EMIT CODE
1821
1822 //=============================================================================
1823
1824 // Emit deopt handler code.
1825 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1826 {
1827 address base = __ start_a_stub(size_deopt_handler());
1828 if (base == nullptr) {
1829 ciEnv::current()->record_failure("CodeCache is full");
1830 return 0; // CodeBuffer::expand failed
1831 }
1832 int offset = __ offset();
1833
1834 Label start;
1835 __ bind(start);
1836
1837 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1838
1839 int entry_offset = __ offset();
1840 __ j(start);
1841
1842 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1843 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1844 "out of bounds read in post-call NOP check");
1845 __ end_a_stub();
1846 return entry_offset;
1847
1848 }
1849 // REQUIRED MATCHER CODE
1850
1851 //=============================================================================
1852
1853 bool Matcher::match_rule_supported(int opcode) {
1854 if (!has_match_rule(opcode)) {
1855 return false;
1856 }
1857
1858 switch (opcode) {
1859 case Op_OnSpinWait:
1860 return VM_Version::supports_on_spin_wait();
1861 case Op_CacheWB: // fall through
1862 case Op_CacheWBPreSync: // fall through
1863 case Op_CacheWBPostSync:
1864 if (!VM_Version::supports_data_cache_line_flush()) {
1865 return false;
1866 }
1867 break;
1868
1869 case Op_StrCompressedCopy: // fall through
1870 case Op_StrInflatedCopy: // fall through
1871 case Op_CountPositives: // fall through
1872 case Op_EncodeISOArray:
1873 return UseRVV;
1874
1875 case Op_PopCountI:
1876 case Op_PopCountL:
1877 return UsePopCountInstruction;
1878
1879 case Op_ReverseI:
1880 case Op_ReverseL:
1881 return UseZbkb;
1882
1883 case Op_ReverseBytesI:
1884 case Op_ReverseBytesL:
1885 case Op_ReverseBytesS:
1886 case Op_ReverseBytesUS:
1887 case Op_RotateRight:
1888 case Op_RotateLeft:
1889 case Op_CountLeadingZerosI:
1890 case Op_CountLeadingZerosL:
1891 case Op_CountTrailingZerosI:
1892 case Op_CountTrailingZerosL:
1893 return UseZbb;
1894
1895 case Op_FmaF:
1896 case Op_FmaD:
1897 return UseFMA;
1898
1899 case Op_ConvHF2F:
1900 case Op_ConvF2HF:
1901 return VM_Version::supports_float16_float_conversion();
1902 case Op_ReinterpretS2HF:
1903 case Op_ReinterpretHF2S:
1904 return UseZfh || UseZfhmin;
1905 case Op_AddHF:
1906 case Op_DivHF:
1907 case Op_FmaHF:
1908 case Op_MaxHF:
1909 case Op_MinHF:
1910 case Op_MulHF:
1911 case Op_SqrtHF:
1912 case Op_SubHF:
1913 return UseZfh;
1914
1915 case Op_CMoveP:
1916 case Op_CMoveN:
1917 return false;
1918 }
1919
1920 return true; // Per default match rules are supported.
1921 }
1922
1923 const RegMask* Matcher::predicate_reg_mask(void) {
1924 return &_VMASK_REG_mask;
1925 }
1926
1927 // Vector calling convention not yet implemented.
1928 bool Matcher::supports_vector_calling_convention(void) {
1929 return EnableVectorSupport;
1930 }
1931
1932 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1933 assert(EnableVectorSupport, "sanity");
1934 assert(ideal_reg == Op_VecA, "sanity");
1935 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1936 int lo = V8_num;
1937 int hi = V8_K_num;
1938 return OptoRegPair(hi, lo);
1939 }
1940
1941 // Is this branch offset short enough that a short branch can be used?
1942 //
1943 // NOTE: If the platform does not provide any short branch variants, then
1944 // this method should return false for offset 0.
1945 // |---label(L1)-----|
1946 // |-----------------|
1947 // |-----------------|----------eq: float-------------------
1948 // |-----------------| // far_cmpD_branch | cmpD_branch
1949 // |------- ---------| feq; | feq;
1950 // |-far_cmpD_branch-| beqz done; | bnez L;
1951 // |-----------------| j L; |
1952 // |-----------------| bind(done); |
1953 // |-----------------|--------------------------------------
1954 // |-----------------| // so shortBrSize = br_size - 4;
1955 // |-----------------| // so offs = offset - shortBrSize + 4;
1956 // |---label(L2)-----|
1957 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1958 // The passed offset is relative to address of the branch.
1959 int shortBrSize = br_size - 4;
1960 int offs = offset - shortBrSize + 4;
1961 return (-4096 <= offs && offs < 4096);
1962 }
1963
1964 // Vector width in bytes.
1965 int Matcher::vector_width_in_bytes(BasicType bt) {
1966 if (UseRVV) {
1967 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1968 // MaxVectorSize == VM_Version::_initial_vector_length
1969 int size = MaxVectorSize;
1970 // Minimum 2 values in vector
1971 if (size < 2 * type2aelembytes(bt)) size = 0;
1972 // But never < 4
1973 if (size < 4) size = 0;
1974 return size;
1975 }
1976 return 0;
1977 }
1978
1979 // Limits on vector size (number of elements) loaded into vector.
1980 int Matcher::max_vector_size(const BasicType bt) {
1981 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1982 }
1983
1984 int Matcher::min_vector_size(const BasicType bt) {
1985 int size;
1986 switch(bt) {
1987 case T_BOOLEAN:
1988 // Load/store a vector mask with only 2 elements for vector types
1989 // such as "2I/2F/2L/2D".
1990 size = 2;
1991 break;
1992 case T_BYTE:
1993 // Generate a "4B" vector, to support vector cast between "8B/16B"
1994 // and "4S/4I/4L/4F/4D".
1995 size = 4;
1996 break;
1997 case T_SHORT:
1998 // Generate a "2S" vector, to support vector cast between "4S/8S"
1999 // and "2I/2L/2F/2D".
2000 size = 2;
2001 break;
2002 default:
2003 // Limit the min vector length to 64-bit.
2004 size = 8 / type2aelembytes(bt);
2005 // The number of elements in a vector should be at least 2.
2006 size = MAX2(size, 2);
2007 }
2008
2009 int max_size = max_vector_size(bt);
2010 return MIN2(size, max_size);
2011 }
2012
2013 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2014 return Matcher::max_vector_size(bt);
2015 }
2016
2017 // Vector ideal reg.
2018 uint Matcher::vector_ideal_reg(int len) {
2019 assert(MaxVectorSize >= len, "");
2020 if (UseRVV) {
2021 return Op_VecA;
2022 }
2023
2024 ShouldNotReachHere();
2025 return 0;
2026 }
2027
2028 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2029 return Matcher::max_vector_size(bt);
2030 }
2031
2032 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2033 ShouldNotReachHere(); // generic vector operands not supported
2034 return nullptr;
2035 }
2036
2037 bool Matcher::is_reg2reg_move(MachNode* m) {
2038 ShouldNotReachHere(); // generic vector operands not supported
2039 return false;
2040 }
2041
2042 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
2043 return false;
2044 }
2045
2046 bool Matcher::is_generic_vector(MachOper* opnd) {
2047 ShouldNotReachHere(); // generic vector operands not supported
2048 return false;
2049 }
2050
2051 #ifdef ASSERT
2052 // Return whether or not this register is ever used as an argument.
2053 bool Matcher::can_be_java_arg(int reg)
2054 {
2055 return
2056 reg == R10_num || reg == R10_H_num ||
2057 reg == R11_num || reg == R11_H_num ||
2058 reg == R12_num || reg == R12_H_num ||
2059 reg == R13_num || reg == R13_H_num ||
2060 reg == R14_num || reg == R14_H_num ||
2061 reg == R15_num || reg == R15_H_num ||
2062 reg == R16_num || reg == R16_H_num ||
2063 reg == R17_num || reg == R17_H_num ||
2064 reg == F10_num || reg == F10_H_num ||
2065 reg == F11_num || reg == F11_H_num ||
2066 reg == F12_num || reg == F12_H_num ||
2067 reg == F13_num || reg == F13_H_num ||
2068 reg == F14_num || reg == F14_H_num ||
2069 reg == F15_num || reg == F15_H_num ||
2070 reg == F16_num || reg == F16_H_num ||
2071 reg == F17_num || reg == F17_H_num;
2072 }
2073 #endif
2074
2075 uint Matcher::int_pressure_limit()
2076 {
2077 // A derived pointer is live at CallNode and then is flagged by RA
2078 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2079 // derived pointers and lastly fail to spill after reaching maximum
2080 // number of iterations. Lowering the default pressure threshold to
2081 // (_NO_SPECIAL_REG32_mask.size() minus 1) forces CallNode to become
2082 // a high register pressure area of the code so that split_DEF can
2083 // generate DefinitionSpillCopy for the derived pointer.
2084 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size() - 1;
2085 if (!PreserveFramePointer) {
2086 // When PreserveFramePointer is off, frame pointer is allocatable,
2087 // but different from other SOC registers, it is excluded from
2088 // fatproj's mask because its save type is No-Save. Decrease 1 to
2089 // ensure high pressure at fatproj when PreserveFramePointer is off.
2090 // See check_pressure_at_fatproj().
2091 default_int_pressure_threshold--;
2092 }
2093 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2094 }
2095
2096 uint Matcher::float_pressure_limit()
2097 {
2098 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2099 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size() : FLOATPRESSURE;
2100 }
2101
2102 const RegMask& Matcher::divI_proj_mask() {
2103 ShouldNotReachHere();
2104 return RegMask::EMPTY;
2105 }
2106
2107 // Register for MODI projection of divmodI.
2108 const RegMask& Matcher::modI_proj_mask() {
2109 ShouldNotReachHere();
2110 return RegMask::EMPTY;
2111 }
2112
2113 // Register for DIVL projection of divmodL.
2114 const RegMask& Matcher::divL_proj_mask() {
2115 ShouldNotReachHere();
2116 return RegMask::EMPTY;
2117 }
2118
2119 // Register for MODL projection of divmodL.
2120 const RegMask& Matcher::modL_proj_mask() {
2121 ShouldNotReachHere();
2122 return RegMask::EMPTY;
2123 }
2124
2125 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2126 assert_cond(addp != nullptr);
2127 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2128 Node* u = addp->fast_out(i);
2129 if (u != nullptr && u->is_Mem()) {
2130 int opsize = u->as_Mem()->memory_size();
2131 assert(opsize > 0, "unexpected memory operand size");
2132 if (u->as_Mem()->memory_size() != (1 << shift)) {
2133 return false;
2134 }
2135 }
2136 }
2137 return true;
2138 }
2139
2140 // Binary src (Replicate scalar/immediate)
2141 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2142 if (n == nullptr || m == nullptr) {
2143 return false;
2144 }
2145
2146 if (m->Opcode() != Op_Replicate) {
2147 return false;
2148 }
2149
2150 switch (n->Opcode()) {
2151 case Op_AndV:
2152 case Op_OrV:
2153 case Op_XorV:
2154 case Op_AddVB:
2155 case Op_AddVS:
2156 case Op_AddVI:
2157 case Op_AddVL:
2158 case Op_SubVB:
2159 case Op_SubVS:
2160 case Op_SubVI:
2161 case Op_SubVL:
2162 case Op_MulVB:
2163 case Op_MulVS:
2164 case Op_MulVI:
2165 case Op_MulVL: {
2166 return true;
2167 }
2168 default:
2169 return false;
2170 }
2171 }
2172
2173 // (XorV src (Replicate m1))
2174 // (XorVMask src (MaskAll m1))
2175 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2176 if (n != nullptr && m != nullptr) {
2177 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2178 VectorNode::is_all_ones_vector(m);
2179 }
2180 return false;
2181 }
2182
2183 // Should the Matcher clone input 'm' of node 'n'?
2184 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2185 assert_cond(m != nullptr);
2186 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2187 is_vector_bitwise_not_pattern(n, m) ||
2188 is_vector_scalar_bitwise_pattern(n, m) ||
2189 is_encode_and_store_pattern(n, m)) {
2190 mstack.push(m, Visit);
2191 return true;
2192 }
2193 return false;
2194 }
2195
2196 // Should the Matcher clone shifts on addressing modes, expecting them
2197 // to be subsumed into complex addressing expressions or compute them
2198 // into registers?
2199 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2200 return clone_base_plus_offset_address(m, mstack, address_visited);
2201 }
2202
2203 %}
2204
2205
2206
2207 //----------ENCODING BLOCK-----------------------------------------------------
2208 // This block specifies the encoding classes used by the compiler to
2209 // output byte streams. Encoding classes are parameterized macros
2210 // used by Machine Instruction Nodes in order to generate the bit
2211 // encoding of the instruction. Operands specify their base encoding
2212 // interface with the interface keyword. There are currently
2213 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2214 // COND_INTER. REG_INTER causes an operand to generate a function
2215 // which returns its register number when queried. CONST_INTER causes
2216 // an operand to generate a function which returns the value of the
2217 // constant when queried. MEMORY_INTER causes an operand to generate
2218 // four functions which return the Base Register, the Index Register,
2219 // the Scale Value, and the Offset Value of the operand when queried.
2220 // COND_INTER causes an operand to generate six functions which return
2221 // the encoding code (ie - encoding bits for the instruction)
2222 // associated with each basic boolean condition for a conditional
2223 // instruction.
2224 //
2225 // Instructions specify two basic values for encoding. Again, a
2226 // function is available to check if the constant displacement is an
2227 // oop. They use the ins_encode keyword to specify their encoding
2228 // classes (which must be a sequence of enc_class names, and their
2229 // parameters, specified in the encoding block), and they use the
2230 // opcode keyword to specify, in order, their primary, secondary, and
2231 // tertiary opcode. Only the opcode sections which a particular
2232 // instruction needs for encoding need to be specified.
2233 encode %{
2234 // BEGIN Non-volatile memory access
2235
2236 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2237 int64_t con = (int64_t)$src$$constant;
2238 Register dst_reg = as_Register($dst$$reg);
2239 __ mv(dst_reg, con);
2240 %}
2241
2242 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2243 Register dst_reg = as_Register($dst$$reg);
2244 address con = (address)$src$$constant;
2245 if (con == nullptr || con == (address)1) {
2246 ShouldNotReachHere();
2247 } else {
2248 relocInfo::relocType rtype = $src->constant_reloc();
2249 if (rtype == relocInfo::oop_type) {
2250 __ movoop(dst_reg, (jobject)con);
2251 } else if (rtype == relocInfo::metadata_type) {
2252 __ mov_metadata(dst_reg, (Metadata*)con);
2253 } else {
2254 assert(rtype == relocInfo::none || rtype == relocInfo::external_word_type, "unexpected reloc type");
2255 __ mv(dst_reg, $src$$constant);
2256 }
2257 }
2258 %}
2259
2260 enc_class riscv_enc_mov_p1(iRegP dst) %{
2261 Register dst_reg = as_Register($dst$$reg);
2262 __ mv(dst_reg, 1);
2263 %}
2264
2265 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2266 Register dst_reg = as_Register($dst$$reg);
2267 address con = (address)$src$$constant;
2268 if (con == nullptr) {
2269 ShouldNotReachHere();
2270 } else {
2271 relocInfo::relocType rtype = $src->constant_reloc();
2272 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2273 __ set_narrow_oop(dst_reg, (jobject)con);
2274 }
2275 %}
2276
2277 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2278 Register dst_reg = as_Register($dst$$reg);
2279 __ mv(dst_reg, zr);
2280 %}
2281
2282 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2283 Register dst_reg = as_Register($dst$$reg);
2284 address con = (address)$src$$constant;
2285 if (con == nullptr) {
2286 ShouldNotReachHere();
2287 } else {
2288 relocInfo::relocType rtype = $src->constant_reloc();
2289 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2290 __ set_narrow_klass(dst_reg, (Klass *)con);
2291 }
2292 %}
2293
2294 // compare and branch instruction encodings
2295
2296 enc_class riscv_enc_j(label lbl) %{
2297 Label* L = $lbl$$label;
2298 __ j(*L);
2299 %}
2300
2301 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2302 Label* L = $lbl$$label;
2303 switch ($cmp$$cmpcode) {
2304 case(BoolTest::ge):
2305 __ j(*L);
2306 break;
2307 case(BoolTest::lt):
2308 break;
2309 default:
2310 Unimplemented();
2311 }
2312 %}
2313
2314 // call instruction encodings
2315
2316 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2317 Register sub_reg = as_Register($sub$$reg);
2318 Register super_reg = as_Register($super$$reg);
2319 Register temp_reg = as_Register($temp$$reg);
2320 Register result_reg = as_Register($result$$reg);
2321 Register cr_reg = t1;
2322
2323 Label miss;
2324 Label done;
2325 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2326 nullptr, &miss, /*set_cond_codes*/ true);
2327 if ($primary) {
2328 __ mv(result_reg, zr);
2329 } else {
2330 __ mv(cr_reg, zr);
2331 __ j(done);
2332 }
2333
2334 __ bind(miss);
2335 if (!$primary) {
2336 __ mv(cr_reg, 1);
2337 }
2338
2339 __ bind(done);
2340 %}
2341
2342 enc_class riscv_enc_java_static_call(method meth) %{
2343 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2344
2345 address addr = (address)$meth$$method;
2346 address call = nullptr;
2347 assert_cond(addr != nullptr);
2348 if (!_method) {
2349 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2350 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2351 if (call == nullptr) {
2352 ciEnv::current()->record_failure("CodeCache is full");
2353 return;
2354 }
2355 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2356 // The NOP here is purely to ensure that eliding a call to
2357 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2358 __ nop();
2359 __ nop();
2360 __ nop();
2361 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2362 } else {
2363 int method_index = resolved_method_index(masm);
2364 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2365 : static_call_Relocation::spec(method_index);
2366 call = __ reloc_call(Address(addr, rspec));
2367 if (call == nullptr) {
2368 ciEnv::current()->record_failure("CodeCache is full");
2369 return;
2370 }
2371
2372 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2373 // Calls of the same statically bound method can share
2374 // a stub to the interpreter.
2375 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2376 } else {
2377 // Emit stub for static call
2378 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2379 if (stub == nullptr) {
2380 ciEnv::current()->record_failure("CodeCache is full");
2381 return;
2382 }
2383 }
2384 }
2385
2386 __ post_call_nop();
2387 %}
2388
2389 enc_class riscv_enc_java_dynamic_call(method meth) %{
2390 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2391 int method_index = resolved_method_index(masm);
2392 address call = __ ic_call((address)$meth$$method, method_index);
2393 if (call == nullptr) {
2394 ciEnv::current()->record_failure("CodeCache is full");
2395 return;
2396 }
2397
2398 __ post_call_nop();
2399 %}
2400
2401 enc_class riscv_enc_call_epilog() %{
2402 if (VerifyStackAtCalls) {
2403 // Check that stack depth is unchanged: find majik cookie on stack
2404 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3 * VMRegImpl::slots_per_word));
2405 Label stack_ok;
2406 __ ld(t1, Address(sp, framesize));
2407 __ mv(t2, MAJIK_DWORD);
2408 __ beq(t2, t1, stack_ok);
2409 __ stop("MAJIK_DWORD not found");
2410 __ bind(stack_ok);
2411 }
2412 %}
2413
2414 enc_class riscv_enc_java_to_runtime(method meth) %{
2415 Assembler::IncompressibleScope scope(masm); // Fixed length: see ret_addr_offset
2416
2417 // Some calls to generated routines (arraycopy code) are scheduled by C2
2418 // as runtime calls. if so we can call them using a far call (they will be
2419 // in the code cache, thus in a reachable segment) otherwise we have to use
2420 // a movptr+jalr pair which loads the absolute address into a register.
2421 address entry = (address)$meth$$method;
2422 if (CodeCache::contains(entry)) {
2423 __ far_call(Address(entry, relocInfo::runtime_call_type));
2424 __ post_call_nop();
2425 } else {
2426 Label retaddr;
2427 // Make the anchor frame walkable
2428 __ la(t0, retaddr);
2429 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2430 int32_t offset = 0;
2431 // No relocation needed
2432 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2433 __ jalr(t1, offset);
2434 __ bind(retaddr);
2435 __ post_call_nop();
2436 }
2437 %}
2438
2439 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2440 Register target_reg = as_Register($jump_target$$reg);
2441 __ jr(target_reg);
2442 %}
2443
2444 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2445 Register target_reg = as_Register($jump_target$$reg);
2446 // exception oop should be in x10
2447 // ret addr has been popped into ra
2448 // callee expects it in x13
2449 __ mv(x13, ra);
2450 __ jr(target_reg);
2451 %}
2452
2453 enc_class riscv_enc_rethrow() %{
2454 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2455 %}
2456
2457 enc_class riscv_enc_ret() %{
2458 __ ret();
2459 %}
2460
2461 %}
2462
2463 //----------FRAME--------------------------------------------------------------
2464 // Definition of frame structure and management information.
2465 //
2466 // S T A C K L A Y O U T Allocators stack-slot number
2467 // | (to get allocators register number
2468 // G Owned by | | v add OptoReg::stack0())
2469 // r CALLER | |
2470 // o | +--------+ pad to even-align allocators stack-slot
2471 // w V | pad0 | numbers; owned by CALLER
2472 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2473 // h ^ | in | 5
2474 // | | args | 4 Holes in incoming args owned by SELF
2475 // | | | | 3
2476 // | | +--------+
2477 // V | | old out| Empty on Intel, window on Sparc
2478 // | old |preserve| Must be even aligned.
2479 // | SP-+--------+----> Matcher::_old_SP, even aligned
2480 // | | in | 3 area for Intel ret address
2481 // Owned by |preserve| Empty on Sparc.
2482 // SELF +--------+
2483 // | | pad2 | 2 pad to align old SP
2484 // | +--------+ 1
2485 // | | locks | 0
2486 // | +--------+----> OptoReg::stack0(), even aligned
2487 // | | pad1 | 11 pad to align new SP
2488 // | +--------+
2489 // | | | 10
2490 // | | spills | 9 spills
2491 // V | | 8 (pad0 slot for callee)
2492 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2493 // ^ | out | 7
2494 // | | args | 6 Holes in outgoing args owned by CALLEE
2495 // Owned by +--------+
2496 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2497 // | new |preserve| Must be even-aligned.
2498 // | SP-+--------+----> Matcher::_new_SP, even aligned
2499 // | | |
2500 //
2501 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2502 // known from SELF's arguments and the Java calling convention.
2503 // Region 6-7 is determined per call site.
2504 // Note 2: If the calling convention leaves holes in the incoming argument
2505 // area, those holes are owned by SELF. Holes in the outgoing area
2506 // are owned by the CALLEE. Holes should not be necessary in the
2507 // incoming area, as the Java calling convention is completely under
2508 // the control of the AD file. Doubles can be sorted and packed to
2509 // avoid holes. Holes in the outgoing arguments may be necessary for
2510 // varargs C calling conventions.
2511 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2512 // even aligned with pad0 as needed.
2513 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2514 // (the latter is true on Intel but is it false on RISCV?)
2515 // region 6-11 is even aligned; it may be padded out more so that
2516 // the region from SP to FP meets the minimum stack alignment.
2517 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2518 // alignment. Region 11, pad1, may be dynamically extended so that
2519 // SP meets the minimum alignment.
2520
2521 frame %{
2522 // These three registers define part of the calling convention
2523 // between compiled code and the interpreter.
2524
2525 // Inline Cache Register or methodOop for I2C.
2526 inline_cache_reg(R31);
2527
2528 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2529 cisc_spilling_operand_name(indOffset);
2530
2531 // Number of stack slots consumed by locking an object
2532 // generate Compile::sync_stack_slots
2533 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2534 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2535
2536 // Compiled code's Frame Pointer
2537 frame_pointer(R2);
2538
2539 // Stack alignment requirement
2540 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2541
2542 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2543 // for calls to C. Supports the var-args backing area for register parms.
2544 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2545
2546 // The after-PROLOG location of the return address. Location of
2547 // return address specifies a type (REG or STACK) and a number
2548 // representing the register number (i.e. - use a register name) or
2549 // stack slot.
2550 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2551 // Otherwise, it is above the locks and verification slot and alignment word
2552 // TODO this may well be correct but need to check why that - 2 is there
2553 // ppc port uses 0 but we definitely need to allow for fixed_slots
2554 // which folds in the space used for monitors
2555 return_addr(STACK - 2 +
2556 align_up((Compile::current()->in_preserve_stack_slots() +
2557 Compile::current()->fixed_slots()),
2558 stack_alignment_in_slots()));
2559
2560 // Location of compiled Java return values. Same as C for now.
2561 return_value
2562 %{
2563 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2564 "only return normal values");
2565
2566 static const int lo[Op_RegL + 1] = { // enum name
2567 0, // Op_Node
2568 0, // Op_Set
2569 R10_num, // Op_RegN
2570 R10_num, // Op_RegI
2571 R10_num, // Op_RegP
2572 F10_num, // Op_RegF
2573 F10_num, // Op_RegD
2574 R10_num // Op_RegL
2575 };
2576
2577 static const int hi[Op_RegL + 1] = { // enum name
2578 0, // Op_Node
2579 0, // Op_Set
2580 OptoReg::Bad, // Op_RegN
2581 OptoReg::Bad, // Op_RegI
2582 R10_H_num, // Op_RegP
2583 OptoReg::Bad, // Op_RegF
2584 F10_H_num, // Op_RegD
2585 R10_H_num // Op_RegL
2586 };
2587
2588 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2589 %}
2590 %}
2591
2592 //----------ATTRIBUTES---------------------------------------------------------
2593 //----------Operand Attributes-------------------------------------------------
2594 op_attrib op_cost(1); // Required cost attribute
2595
2596 //----------Instruction Attributes---------------------------------------------
2597 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2598 ins_attrib ins_size(32); // Required size attribute (in bits)
2599 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2600 // a non-matching short branch variant
2601 // of some long branch?
2602 ins_attrib ins_alignment(4); // Required alignment attribute (must
2603 // be a power of 2) specifies the
2604 // alignment that some part of the
2605 // instruction (not necessarily the
2606 // start) requires. If > 1, a
2607 // compute_padding() function must be
2608 // provided for the instruction
2609
2610 // Whether this node is expanded during code emission into a sequence of
2611 // instructions and the first instruction can perform an implicit null check.
2612 ins_attrib ins_is_late_expanded_null_check_candidate(false);
2613
2614 //----------OPERANDS-----------------------------------------------------------
2615 // Operand definitions must precede instruction definitions for correct parsing
2616 // in the ADLC because operands constitute user defined types which are used in
2617 // instruction definitions.
2618
2619 //----------Simple Operands----------------------------------------------------
2620
2621 // Integer operands 32 bit
2622 // 32 bit immediate
2623 operand immI()
2624 %{
2625 match(ConI);
2626
2627 op_cost(0);
2628 format %{ %}
2629 interface(CONST_INTER);
2630 %}
2631
2632 // 32 bit zero
2633 operand immI0()
2634 %{
2635 predicate(n->get_int() == 0);
2636 match(ConI);
2637
2638 op_cost(0);
2639 format %{ %}
2640 interface(CONST_INTER);
2641 %}
2642
2643 // 32 bit unit increment
2644 operand immI_1()
2645 %{
2646 predicate(n->get_int() == 1);
2647 match(ConI);
2648
2649 op_cost(0);
2650 format %{ %}
2651 interface(CONST_INTER);
2652 %}
2653
2654 // 32 bit unit decrement
2655 operand immI_M1()
2656 %{
2657 predicate(n->get_int() == -1);
2658 match(ConI);
2659
2660 op_cost(0);
2661 format %{ %}
2662 interface(CONST_INTER);
2663 %}
2664
2665 // Unsigned Integer Immediate: 6-bit int, greater than 32
2666 operand uimmI6_ge32() %{
2667 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2668 match(ConI);
2669 op_cost(0);
2670 format %{ %}
2671 interface(CONST_INTER);
2672 %}
2673
2674 operand immI_le_4()
2675 %{
2676 predicate(n->get_int() <= 4);
2677 match(ConI);
2678
2679 op_cost(0);
2680 format %{ %}
2681 interface(CONST_INTER);
2682 %}
2683
2684 operand immI_16()
2685 %{
2686 predicate(n->get_int() == 16);
2687 match(ConI);
2688 op_cost(0);
2689 format %{ %}
2690 interface(CONST_INTER);
2691 %}
2692
2693 operand immI_24()
2694 %{
2695 predicate(n->get_int() == 24);
2696 match(ConI);
2697 op_cost(0);
2698 format %{ %}
2699 interface(CONST_INTER);
2700 %}
2701
2702 operand immI_31()
2703 %{
2704 predicate(n->get_int() == 31);
2705 match(ConI);
2706
2707 op_cost(0);
2708 format %{ %}
2709 interface(CONST_INTER);
2710 %}
2711
2712 operand immI_63()
2713 %{
2714 predicate(n->get_int() == 63);
2715 match(ConI);
2716
2717 op_cost(0);
2718 format %{ %}
2719 interface(CONST_INTER);
2720 %}
2721
2722 // 32 bit integer valid for add immediate
2723 operand immIAdd()
2724 %{
2725 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2726 match(ConI);
2727 op_cost(0);
2728 format %{ %}
2729 interface(CONST_INTER);
2730 %}
2731
2732 // 32 bit integer valid for sub immediate
2733 operand immISub()
2734 %{
2735 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2736 match(ConI);
2737 op_cost(0);
2738 format %{ %}
2739 interface(CONST_INTER);
2740 %}
2741
2742 // 5 bit signed value.
2743 operand immI5()
2744 %{
2745 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2746 match(ConI);
2747
2748 op_cost(0);
2749 format %{ %}
2750 interface(CONST_INTER);
2751 %}
2752
2753 // 5 bit signed value (simm5)
2754 operand immL5()
2755 %{
2756 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2757 match(ConL);
2758
2759 op_cost(0);
2760 format %{ %}
2761 interface(CONST_INTER);
2762 %}
2763
2764 // Integer operands 64 bit
2765 // 64 bit immediate
2766 operand immL()
2767 %{
2768 match(ConL);
2769
2770 op_cost(0);
2771 format %{ %}
2772 interface(CONST_INTER);
2773 %}
2774
2775 // 64 bit zero
2776 operand immL0()
2777 %{
2778 predicate(n->get_long() == 0);
2779 match(ConL);
2780
2781 op_cost(0);
2782 format %{ %}
2783 interface(CONST_INTER);
2784 %}
2785
2786 // Pointer operands
2787 // Pointer Immediate
2788 operand immP()
2789 %{
2790 match(ConP);
2791
2792 op_cost(0);
2793 format %{ %}
2794 interface(CONST_INTER);
2795 %}
2796
2797 // Null Pointer Immediate
2798 operand immP0()
2799 %{
2800 predicate(n->get_ptr() == 0);
2801 match(ConP);
2802
2803 op_cost(0);
2804 format %{ %}
2805 interface(CONST_INTER);
2806 %}
2807
2808 // Pointer Immediate One
2809 // this is used in object initialization (initial object header)
2810 operand immP_1()
2811 %{
2812 predicate(n->get_ptr() == 1);
2813 match(ConP);
2814
2815 op_cost(0);
2816 format %{ %}
2817 interface(CONST_INTER);
2818 %}
2819
2820 // Int Immediate: low 16-bit mask
2821 operand immI_16bits()
2822 %{
2823 predicate(n->get_int() == 0xFFFF);
2824 match(ConI);
2825 op_cost(0);
2826 format %{ %}
2827 interface(CONST_INTER);
2828 %}
2829
2830 operand immIpowerOf2() %{
2831 predicate(is_power_of_2((juint)(n->get_int())));
2832 match(ConI);
2833 op_cost(0);
2834 format %{ %}
2835 interface(CONST_INTER);
2836 %}
2837
2838 // Long Immediate: low 32-bit mask
2839 operand immL_32bits()
2840 %{
2841 predicate(n->get_long() == 0xFFFFFFFFL);
2842 match(ConL);
2843 op_cost(0);
2844 format %{ %}
2845 interface(CONST_INTER);
2846 %}
2847
2848 // 64 bit unit decrement
2849 operand immL_M1()
2850 %{
2851 predicate(n->get_long() == -1);
2852 match(ConL);
2853
2854 op_cost(0);
2855 format %{ %}
2856 interface(CONST_INTER);
2857 %}
2858
2859
2860 // 64 bit integer valid for add immediate
2861 operand immLAdd()
2862 %{
2863 predicate(Assembler::is_simm12(n->get_long()));
2864 match(ConL);
2865 op_cost(0);
2866 format %{ %}
2867 interface(CONST_INTER);
2868 %}
2869
2870 // 64 bit integer valid for sub immediate
2871 operand immLSub()
2872 %{
2873 predicate(Assembler::is_simm12(-(n->get_long())));
2874 match(ConL);
2875 op_cost(0);
2876 format %{ %}
2877 interface(CONST_INTER);
2878 %}
2879
2880 // Narrow pointer operands
2881 // Narrow Pointer Immediate
2882 operand immN()
2883 %{
2884 match(ConN);
2885
2886 op_cost(0);
2887 format %{ %}
2888 interface(CONST_INTER);
2889 %}
2890
2891 // Narrow Null Pointer Immediate
2892 operand immN0()
2893 %{
2894 predicate(n->get_narrowcon() == 0);
2895 match(ConN);
2896
2897 op_cost(0);
2898 format %{ %}
2899 interface(CONST_INTER);
2900 %}
2901
2902 operand immNKlass()
2903 %{
2904 match(ConNKlass);
2905
2906 op_cost(0);
2907 format %{ %}
2908 interface(CONST_INTER);
2909 %}
2910
2911 // Float and Double operands
2912 // Double Immediate
2913 operand immD()
2914 %{
2915 match(ConD);
2916 op_cost(0);
2917 format %{ %}
2918 interface(CONST_INTER);
2919 %}
2920
2921 // Double Immediate: +0.0d
2922 operand immD0()
2923 %{
2924 predicate(jlong_cast(n->getd()) == 0);
2925 match(ConD);
2926
2927 op_cost(0);
2928 format %{ %}
2929 interface(CONST_INTER);
2930 %}
2931
2932 // Float Immediate
2933 operand immF()
2934 %{
2935 match(ConF);
2936 op_cost(0);
2937 format %{ %}
2938 interface(CONST_INTER);
2939 %}
2940
2941 // Float Immediate: +0.0f.
2942 operand immF0()
2943 %{
2944 predicate(jint_cast(n->getf()) == 0);
2945 match(ConF);
2946
2947 op_cost(0);
2948 format %{ %}
2949 interface(CONST_INTER);
2950 %}
2951
2952 // Half Float Immediate
2953 operand immH()
2954 %{
2955 match(ConH);
2956
2957 op_cost(0);
2958 format %{ %}
2959 interface(CONST_INTER);
2960 %}
2961
2962 // Half Float Immediate: +0.0f.
2963 operand immH0()
2964 %{
2965 predicate(jint_cast(n->geth()) == 0);
2966 match(ConH);
2967
2968 op_cost(0);
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 operand immIOffset()
2974 %{
2975 predicate(Assembler::is_simm12(n->get_int()));
2976 match(ConI);
2977 op_cost(0);
2978 format %{ %}
2979 interface(CONST_INTER);
2980 %}
2981
2982 operand immLOffset()
2983 %{
2984 predicate(Assembler::is_simm12(n->get_long()));
2985 match(ConL);
2986 op_cost(0);
2987 format %{ %}
2988 interface(CONST_INTER);
2989 %}
2990
2991 // Scale values
2992 operand immIScale()
2993 %{
2994 predicate(1 <= n->get_int() && (n->get_int() <= 3));
2995 match(ConI);
2996
2997 op_cost(0);
2998 format %{ %}
2999 interface(CONST_INTER);
3000 %}
3001
3002 // Integer 32 bit Register Operands
3003 operand iRegI()
3004 %{
3005 constraint(ALLOC_IN_RC(any_reg32));
3006 match(RegI);
3007 match(iRegINoSp);
3008 op_cost(0);
3009 format %{ %}
3010 interface(REG_INTER);
3011 %}
3012
3013 // Integer 32 bit Register not Special
3014 operand iRegINoSp()
3015 %{
3016 constraint(ALLOC_IN_RC(no_special_reg32));
3017 match(RegI);
3018 op_cost(0);
3019 format %{ %}
3020 interface(REG_INTER);
3021 %}
3022
3023 // Register R10 only
3024 operand iRegI_R10()
3025 %{
3026 constraint(ALLOC_IN_RC(int_r10_reg));
3027 match(RegI);
3028 match(iRegINoSp);
3029 op_cost(0);
3030 format %{ %}
3031 interface(REG_INTER);
3032 %}
3033
3034 // Register R12 only
3035 operand iRegI_R12()
3036 %{
3037 constraint(ALLOC_IN_RC(int_r12_reg));
3038 match(RegI);
3039 match(iRegINoSp);
3040 op_cost(0);
3041 format %{ %}
3042 interface(REG_INTER);
3043 %}
3044
3045 // Register R13 only
3046 operand iRegI_R13()
3047 %{
3048 constraint(ALLOC_IN_RC(int_r13_reg));
3049 match(RegI);
3050 match(iRegINoSp);
3051 op_cost(0);
3052 format %{ %}
3053 interface(REG_INTER);
3054 %}
3055
3056 // Register R14 only
3057 operand iRegI_R14()
3058 %{
3059 constraint(ALLOC_IN_RC(int_r14_reg));
3060 match(RegI);
3061 match(iRegINoSp);
3062 op_cost(0);
3063 format %{ %}
3064 interface(REG_INTER);
3065 %}
3066
3067 // Integer 64 bit Register Operands
3068 operand iRegL()
3069 %{
3070 constraint(ALLOC_IN_RC(any_reg));
3071 match(RegL);
3072 match(iRegLNoSp);
3073 op_cost(0);
3074 format %{ %}
3075 interface(REG_INTER);
3076 %}
3077
3078 // Integer 64 bit Register not Special
3079 operand iRegLNoSp()
3080 %{
3081 constraint(ALLOC_IN_RC(no_special_reg));
3082 match(RegL);
3083 match(iRegL_R10);
3084 format %{ %}
3085 interface(REG_INTER);
3086 %}
3087
3088 // Long 64 bit Register R29 only
3089 operand iRegL_R29()
3090 %{
3091 constraint(ALLOC_IN_RC(r29_reg));
3092 match(RegL);
3093 match(iRegLNoSp);
3094 op_cost(0);
3095 format %{ %}
3096 interface(REG_INTER);
3097 %}
3098
3099 // Long 64 bit Register R30 only
3100 operand iRegL_R30()
3101 %{
3102 constraint(ALLOC_IN_RC(r30_reg));
3103 match(RegL);
3104 match(iRegLNoSp);
3105 op_cost(0);
3106 format %{ %}
3107 interface(REG_INTER);
3108 %}
3109
3110 // Pointer Register Operands
3111 // Pointer Register
3112 operand iRegP()
3113 %{
3114 constraint(ALLOC_IN_RC(ptr_reg));
3115 match(RegP);
3116 match(iRegPNoSp);
3117 match(iRegP_R10);
3118 match(iRegP_R15);
3119 match(javaThread_RegP);
3120 op_cost(0);
3121 format %{ %}
3122 interface(REG_INTER);
3123 %}
3124
3125 // Pointer 64 bit Register not Special
3126 operand iRegPNoSp()
3127 %{
3128 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3129 match(RegP);
3130 op_cost(0);
3131 format %{ %}
3132 interface(REG_INTER);
3133 %}
3134
3135 // This operand is not allowed to use fp even if
3136 // fp is not used to hold the frame pointer.
3137 operand iRegPNoSpNoFp()
3138 %{
3139 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3140 match(RegP);
3141 match(iRegPNoSp);
3142 op_cost(0);
3143 format %{ %}
3144 interface(REG_INTER);
3145 %}
3146
3147 operand iRegP_R10()
3148 %{
3149 constraint(ALLOC_IN_RC(r10_reg));
3150 match(RegP);
3151 // match(iRegP);
3152 match(iRegPNoSp);
3153 op_cost(0);
3154 format %{ %}
3155 interface(REG_INTER);
3156 %}
3157
3158 // Pointer 64 bit Register R11 only
3159 operand iRegP_R11()
3160 %{
3161 constraint(ALLOC_IN_RC(r11_reg));
3162 match(RegP);
3163 match(iRegPNoSp);
3164 op_cost(0);
3165 format %{ %}
3166 interface(REG_INTER);
3167 %}
3168
3169 operand iRegP_R12()
3170 %{
3171 constraint(ALLOC_IN_RC(r12_reg));
3172 match(RegP);
3173 // match(iRegP);
3174 match(iRegPNoSp);
3175 op_cost(0);
3176 format %{ %}
3177 interface(REG_INTER);
3178 %}
3179
3180 // Pointer 64 bit Register R13 only
3181 operand iRegP_R13()
3182 %{
3183 constraint(ALLOC_IN_RC(r13_reg));
3184 match(RegP);
3185 match(iRegPNoSp);
3186 op_cost(0);
3187 format %{ %}
3188 interface(REG_INTER);
3189 %}
3190
3191 operand iRegP_R14()
3192 %{
3193 constraint(ALLOC_IN_RC(r14_reg));
3194 match(RegP);
3195 // match(iRegP);
3196 match(iRegPNoSp);
3197 op_cost(0);
3198 format %{ %}
3199 interface(REG_INTER);
3200 %}
3201
3202 operand iRegP_R15()
3203 %{
3204 constraint(ALLOC_IN_RC(r15_reg));
3205 match(RegP);
3206 // match(iRegP);
3207 match(iRegPNoSp);
3208 op_cost(0);
3209 format %{ %}
3210 interface(REG_INTER);
3211 %}
3212
3213 operand iRegP_R16()
3214 %{
3215 constraint(ALLOC_IN_RC(r16_reg));
3216 match(RegP);
3217 match(iRegPNoSp);
3218 op_cost(0);
3219 format %{ %}
3220 interface(REG_INTER);
3221 %}
3222
3223 // Pointer 64 bit Register R28 only
3224 operand iRegP_R28()
3225 %{
3226 constraint(ALLOC_IN_RC(r28_reg));
3227 match(RegP);
3228 match(iRegPNoSp);
3229 op_cost(0);
3230 format %{ %}
3231 interface(REG_INTER);
3232 %}
3233
3234 // Pointer 64 bit Register R30 only
3235 operand iRegP_R30()
3236 %{
3237 constraint(ALLOC_IN_RC(r30_reg));
3238 match(RegP);
3239 match(iRegPNoSp);
3240 op_cost(0);
3241 format %{ %}
3242 interface(REG_INTER);
3243 %}
3244
3245 // Pointer 64 bit Register R31 only
3246 operand iRegP_R31()
3247 %{
3248 constraint(ALLOC_IN_RC(r31_reg));
3249 match(RegP);
3250 match(iRegPNoSp);
3251 op_cost(0);
3252 format %{ %}
3253 interface(REG_INTER);
3254 %}
3255
3256 // Pointer Register Operands
3257 // Narrow Pointer Register
3258 operand iRegN()
3259 %{
3260 constraint(ALLOC_IN_RC(any_reg32));
3261 match(RegN);
3262 match(iRegNNoSp);
3263 op_cost(0);
3264 format %{ %}
3265 interface(REG_INTER);
3266 %}
3267
3268 // Integer 64 bit Register not Special
3269 operand iRegNNoSp()
3270 %{
3271 constraint(ALLOC_IN_RC(no_special_reg32));
3272 match(RegN);
3273 op_cost(0);
3274 format %{ %}
3275 interface(REG_INTER);
3276 %}
3277
3278 // Long 64 bit Register R10 only
3279 operand iRegL_R10()
3280 %{
3281 constraint(ALLOC_IN_RC(r10_reg));
3282 match(RegL);
3283 match(iRegLNoSp);
3284 op_cost(0);
3285 format %{ %}
3286 interface(REG_INTER);
3287 %}
3288
3289 // Float Register
3290 // Float register operands
3291 operand fRegF()
3292 %{
3293 constraint(ALLOC_IN_RC(float_reg));
3294 match(RegF);
3295
3296 op_cost(0);
3297 format %{ %}
3298 interface(REG_INTER);
3299 %}
3300
3301 // Double Register
3302 // Double register operands
3303 operand fRegD()
3304 %{
3305 constraint(ALLOC_IN_RC(double_reg));
3306 match(RegD);
3307
3308 op_cost(0);
3309 format %{ %}
3310 interface(REG_INTER);
3311 %}
3312
3313 // Generic vector class. This will be used for
3314 // all vector operands.
3315 operand vReg()
3316 %{
3317 constraint(ALLOC_IN_RC(vectora_reg));
3318 match(VecA);
3319 op_cost(0);
3320 format %{ %}
3321 interface(REG_INTER);
3322 %}
3323
3324 operand vReg_V1()
3325 %{
3326 constraint(ALLOC_IN_RC(v1_reg));
3327 match(VecA);
3328 match(vReg);
3329 op_cost(0);
3330 format %{ %}
3331 interface(REG_INTER);
3332 %}
3333
3334 operand vReg_V2()
3335 %{
3336 constraint(ALLOC_IN_RC(v2_reg));
3337 match(VecA);
3338 match(vReg);
3339 op_cost(0);
3340 format %{ %}
3341 interface(REG_INTER);
3342 %}
3343
3344 operand vReg_V3()
3345 %{
3346 constraint(ALLOC_IN_RC(v3_reg));
3347 match(VecA);
3348 match(vReg);
3349 op_cost(0);
3350 format %{ %}
3351 interface(REG_INTER);
3352 %}
3353
3354 operand vReg_V4()
3355 %{
3356 constraint(ALLOC_IN_RC(v4_reg));
3357 match(VecA);
3358 match(vReg);
3359 op_cost(0);
3360 format %{ %}
3361 interface(REG_INTER);
3362 %}
3363
3364 operand vReg_V5()
3365 %{
3366 constraint(ALLOC_IN_RC(v5_reg));
3367 match(VecA);
3368 match(vReg);
3369 op_cost(0);
3370 format %{ %}
3371 interface(REG_INTER);
3372 %}
3373
3374 operand vReg_V6()
3375 %{
3376 constraint(ALLOC_IN_RC(v6_reg));
3377 match(VecA);
3378 match(vReg);
3379 op_cost(0);
3380 format %{ %}
3381 interface(REG_INTER);
3382 %}
3383
3384 operand vReg_V7()
3385 %{
3386 constraint(ALLOC_IN_RC(v7_reg));
3387 match(VecA);
3388 match(vReg);
3389 op_cost(0);
3390 format %{ %}
3391 interface(REG_INTER);
3392 %}
3393
3394 operand vReg_V8()
3395 %{
3396 constraint(ALLOC_IN_RC(v8_reg));
3397 match(VecA);
3398 match(vReg);
3399 op_cost(0);
3400 format %{ %}
3401 interface(REG_INTER);
3402 %}
3403
3404 operand vReg_V9()
3405 %{
3406 constraint(ALLOC_IN_RC(v9_reg));
3407 match(VecA);
3408 match(vReg);
3409 op_cost(0);
3410 format %{ %}
3411 interface(REG_INTER);
3412 %}
3413
3414 operand vReg_V10()
3415 %{
3416 constraint(ALLOC_IN_RC(v10_reg));
3417 match(VecA);
3418 match(vReg);
3419 op_cost(0);
3420 format %{ %}
3421 interface(REG_INTER);
3422 %}
3423
3424 operand vReg_V11()
3425 %{
3426 constraint(ALLOC_IN_RC(v11_reg));
3427 match(VecA);
3428 match(vReg);
3429 op_cost(0);
3430 format %{ %}
3431 interface(REG_INTER);
3432 %}
3433
3434 operand vRegMask()
3435 %{
3436 constraint(ALLOC_IN_RC(vmask_reg));
3437 match(RegVectMask);
3438 match(vRegMask_V0);
3439 op_cost(0);
3440 format %{ %}
3441 interface(REG_INTER);
3442 %}
3443
3444 // The mask value used to control execution of a masked
3445 // vector instruction is always supplied by vector register v0.
3446 operand vRegMask_V0()
3447 %{
3448 constraint(ALLOC_IN_RC(vmask_reg_v0));
3449 match(RegVectMask);
3450 match(vRegMask);
3451 op_cost(0);
3452 format %{ %}
3453 interface(REG_INTER);
3454 %}
3455
3456 // Java Thread Register
3457 operand javaThread_RegP(iRegP reg)
3458 %{
3459 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3460 match(reg);
3461 op_cost(0);
3462 format %{ %}
3463 interface(REG_INTER);
3464 %}
3465
3466 //----------Memory Operands----------------------------------------------------
3467 // RISCV has only base_plus_offset and literal address mode, so no need to use
3468 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3469 operand indirect(iRegP reg)
3470 %{
3471 constraint(ALLOC_IN_RC(ptr_reg));
3472 match(reg);
3473 op_cost(0);
3474 format %{ "[$reg]" %}
3475 interface(MEMORY_INTER) %{
3476 base($reg);
3477 index(0xffffffff);
3478 scale(0x0);
3479 disp(0x0);
3480 %}
3481 %}
3482
3483 operand indOffI(iRegP reg, immIOffset off)
3484 %{
3485 constraint(ALLOC_IN_RC(ptr_reg));
3486 match(AddP reg off);
3487 op_cost(0);
3488 format %{ "[$reg, $off]" %}
3489 interface(MEMORY_INTER) %{
3490 base($reg);
3491 index(0xffffffff);
3492 scale(0x0);
3493 disp($off);
3494 %}
3495 %}
3496
3497 operand indOffL(iRegP reg, immLOffset off)
3498 %{
3499 constraint(ALLOC_IN_RC(ptr_reg));
3500 match(AddP reg off);
3501 op_cost(0);
3502 format %{ "[$reg, $off]" %}
3503 interface(MEMORY_INTER) %{
3504 base($reg);
3505 index(0xffffffff);
3506 scale(0x0);
3507 disp($off);
3508 %}
3509 %}
3510
3511 operand indirectN(iRegN reg)
3512 %{
3513 predicate(CompressedOops::shift() == 0);
3514 constraint(ALLOC_IN_RC(ptr_reg));
3515 match(DecodeN reg);
3516 op_cost(0);
3517 format %{ "[$reg]\t# narrow" %}
3518 interface(MEMORY_INTER) %{
3519 base($reg);
3520 index(0xffffffff);
3521 scale(0x0);
3522 disp(0x0);
3523 %}
3524 %}
3525
3526 operand indOffIN(iRegN reg, immIOffset off)
3527 %{
3528 predicate(CompressedOops::shift() == 0);
3529 constraint(ALLOC_IN_RC(ptr_reg));
3530 match(AddP (DecodeN reg) off);
3531 op_cost(0);
3532 format %{ "[$reg, $off]\t# narrow" %}
3533 interface(MEMORY_INTER) %{
3534 base($reg);
3535 index(0xffffffff);
3536 scale(0x0);
3537 disp($off);
3538 %}
3539 %}
3540
3541 operand indOffLN(iRegN reg, immLOffset off)
3542 %{
3543 predicate(CompressedOops::shift() == 0);
3544 constraint(ALLOC_IN_RC(ptr_reg));
3545 match(AddP (DecodeN reg) off);
3546 op_cost(0);
3547 format %{ "[$reg, $off]\t# narrow" %}
3548 interface(MEMORY_INTER) %{
3549 base($reg);
3550 index(0xffffffff);
3551 scale(0x0);
3552 disp($off);
3553 %}
3554 %}
3555
3556 //----------Special Memory Operands--------------------------------------------
3557 // Stack Slot Operand - This operand is used for loading and storing temporary
3558 // values on the stack where a match requires a value to
3559 // flow through memory.
3560 operand stackSlotI(sRegI reg)
3561 %{
3562 constraint(ALLOC_IN_RC(stack_slots));
3563 // No match rule because this operand is only generated in matching
3564 // match(RegI);
3565 format %{ "[$reg]" %}
3566 interface(MEMORY_INTER) %{
3567 base(0x02); // RSP
3568 index(0xffffffff); // No Index
3569 scale(0x0); // No Scale
3570 disp($reg); // Stack Offset
3571 %}
3572 %}
3573
3574 operand stackSlotF(sRegF reg)
3575 %{
3576 constraint(ALLOC_IN_RC(stack_slots));
3577 // No match rule because this operand is only generated in matching
3578 // match(RegF);
3579 format %{ "[$reg]" %}
3580 interface(MEMORY_INTER) %{
3581 base(0x02); // RSP
3582 index(0xffffffff); // No Index
3583 scale(0x0); // No Scale
3584 disp($reg); // Stack Offset
3585 %}
3586 %}
3587
3588 operand stackSlotD(sRegD reg)
3589 %{
3590 constraint(ALLOC_IN_RC(stack_slots));
3591 // No match rule because this operand is only generated in matching
3592 // match(RegD);
3593 format %{ "[$reg]" %}
3594 interface(MEMORY_INTER) %{
3595 base(0x02); // RSP
3596 index(0xffffffff); // No Index
3597 scale(0x0); // No Scale
3598 disp($reg); // Stack Offset
3599 %}
3600 %}
3601
3602 operand stackSlotL(sRegL reg)
3603 %{
3604 constraint(ALLOC_IN_RC(stack_slots));
3605 // No match rule because this operand is only generated in matching
3606 // match(RegL);
3607 format %{ "[$reg]" %}
3608 interface(MEMORY_INTER) %{
3609 base(0x02); // RSP
3610 index(0xffffffff); // No Index
3611 scale(0x0); // No Scale
3612 disp($reg); // Stack Offset
3613 %}
3614 %}
3615
3616 // Special operand allowing long args to int ops to be truncated for free
3617
3618 operand iRegL2I(iRegL reg) %{
3619
3620 op_cost(0);
3621
3622 match(ConvL2I reg);
3623
3624 format %{ "l2i($reg)" %}
3625
3626 interface(REG_INTER)
3627 %}
3628
3629
3630 // Comparison Operands
3631 // NOTE: Label is a predefined operand which should not be redefined in
3632 // the AD file. It is generically handled within the ADLC.
3633
3634 //----------Conditional Branch Operands----------------------------------------
3635 // Comparison Op - This is the operation of the comparison, and is limited to
3636 // the following set of codes:
3637 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3638 //
3639 // Other attributes of the comparison, such as unsignedness, are specified
3640 // by the comparison instruction that sets a condition code flags register.
3641 // That result is represented by a flags operand whose subtype is appropriate
3642 // to the unsignedness (etc.) of the comparison.
3643 //
3644 // Later, the instruction which matches both the Comparison Op (a Bool) and
3645 // the flags (produced by the Cmp) specifies the coding of the comparison op
3646 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3647
3648
3649 // used for signed integral comparisons and fp comparisons
3650 operand cmpOp()
3651 %{
3652 match(Bool);
3653
3654 format %{ "" %}
3655
3656 // the values in interface derives from struct BoolTest::mask
3657 interface(COND_INTER) %{
3658 equal(0x0, "eq");
3659 greater(0x1, "gt");
3660 overflow(0x2, "overflow");
3661 less(0x3, "lt");
3662 not_equal(0x4, "ne");
3663 less_equal(0x5, "le");
3664 no_overflow(0x6, "no_overflow");
3665 greater_equal(0x7, "ge");
3666 %}
3667 %}
3668
3669 // used for unsigned integral comparisons
3670 operand cmpOpU()
3671 %{
3672 match(Bool);
3673
3674 format %{ "" %}
3675 // the values in interface derives from struct BoolTest::mask
3676 interface(COND_INTER) %{
3677 equal(0x0, "eq");
3678 greater(0x1, "gtu");
3679 overflow(0x2, "overflow");
3680 less(0x3, "ltu");
3681 not_equal(0x4, "ne");
3682 less_equal(0x5, "leu");
3683 no_overflow(0x6, "no_overflow");
3684 greater_equal(0x7, "geu");
3685 %}
3686 %}
3687
3688 // used for certain integral comparisons which can be
3689 // converted to bxx instructions
3690 operand cmpOpEqNe()
3691 %{
3692 match(Bool);
3693 op_cost(0);
3694 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3695 n->as_Bool()->_test._test == BoolTest::eq);
3696
3697 format %{ "" %}
3698 interface(COND_INTER) %{
3699 equal(0x0, "eq");
3700 greater(0x1, "gt");
3701 overflow(0x2, "overflow");
3702 less(0x3, "lt");
3703 not_equal(0x4, "ne");
3704 less_equal(0x5, "le");
3705 no_overflow(0x6, "no_overflow");
3706 greater_equal(0x7, "ge");
3707 %}
3708 %}
3709
3710 operand cmpOpULtGe()
3711 %{
3712 match(Bool);
3713 op_cost(0);
3714 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3715 n->as_Bool()->_test._test == BoolTest::ge);
3716
3717 format %{ "" %}
3718 interface(COND_INTER) %{
3719 equal(0x0, "eq");
3720 greater(0x1, "gtu");
3721 overflow(0x2, "overflow");
3722 less(0x3, "ltu");
3723 not_equal(0x4, "ne");
3724 less_equal(0x5, "leu");
3725 no_overflow(0x6, "no_overflow");
3726 greater_equal(0x7, "geu");
3727 %}
3728 %}
3729
3730 operand cmpOpUEqNeLeGt()
3731 %{
3732 match(Bool);
3733 op_cost(0);
3734 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3735 n->as_Bool()->_test._test == BoolTest::eq ||
3736 n->as_Bool()->_test._test == BoolTest::le ||
3737 n->as_Bool()->_test._test == BoolTest::gt);
3738
3739 format %{ "" %}
3740 interface(COND_INTER) %{
3741 equal(0x0, "eq");
3742 greater(0x1, "gtu");
3743 overflow(0x2, "overflow");
3744 less(0x3, "ltu");
3745 not_equal(0x4, "ne");
3746 less_equal(0x5, "leu");
3747 no_overflow(0x6, "no_overflow");
3748 greater_equal(0x7, "geu");
3749 %}
3750 %}
3751
3752
3753 // Flags register, used as output of compare logic
3754 operand rFlagsReg()
3755 %{
3756 constraint(ALLOC_IN_RC(reg_flags));
3757 match(RegFlags);
3758
3759 op_cost(0);
3760 format %{ "RFLAGS" %}
3761 interface(REG_INTER);
3762 %}
3763
3764 // Special Registers
3765
3766 // Method Register
3767 operand inline_cache_RegP(iRegP reg)
3768 %{
3769 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3770 match(reg);
3771 match(iRegPNoSp);
3772 op_cost(0);
3773 format %{ %}
3774 interface(REG_INTER);
3775 %}
3776
3777 //----------OPERAND CLASSES----------------------------------------------------
3778 // Operand Classes are groups of operands that are used as to simplify
3779 // instruction definitions by not requiring the AD writer to specify
3780 // separate instructions for every form of operand when the
3781 // instruction accepts multiple operand types with the same basic
3782 // encoding and format. The classic case of this is memory operands.
3783
3784 // memory is used to define read/write location for load/store
3785 // instruction defs. we can turn a memory op into an Address
3786
3787 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3788
3789 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3790 // operations. it allows the src to be either an iRegI or a (ConvL2I
3791 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3792 // can be elided because the 32-bit instruction will just employ the
3793 // lower 32 bits anyway.
3794 //
3795 // n.b. this does not elide all L2I conversions. if the truncated
3796 // value is consumed by more than one operation then the ConvL2I
3797 // cannot be bundled into the consuming nodes so an l2i gets planted
3798 // (actually an addiw $dst, $src, 0) and the downstream instructions
3799 // consume the result of the L2I as an iRegI input. That's a shame since
3800 // the addiw is actually redundant but its not too costly.
3801
3802 opclass iRegIorL2I(iRegI, iRegL2I);
3803 opclass iRegIorL(iRegI, iRegL);
3804 opclass iRegNorP(iRegN, iRegP);
3805 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3806 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3807 opclass immIorL(immI, immL);
3808
3809 //----------PIPELINE-----------------------------------------------------------
3810 // Rules which define the behavior of the target architectures pipeline.
3811
3812 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3813 //pipe_desc(ID, EX, MEM, WR);
3814 #define ID S0
3815 #define EX S1
3816 #define MEM S2
3817 #define WR S3
3818
3819 // Integer ALU reg operation
3820 pipeline %{
3821
3822 attributes %{
3823 // RISC-V instructions are of length 2 or 4 bytes.
3824 variable_size_instructions;
3825 instruction_unit_size = 2;
3826
3827 // Up to 4 instructions per bundle
3828 max_instructions_per_bundle = 4;
3829
3830 // The RISC-V processor fetches 64 bytes...
3831 instruction_fetch_unit_size = 64;
3832
3833 // ...in one line.
3834 instruction_fetch_units = 1;
3835 %}
3836
3837 // We don't use an actual pipeline model so don't care about resources
3838 // or description. we do use pipeline classes to introduce fixed
3839 // latencies
3840
3841 //----------RESOURCES----------------------------------------------------------
3842 // Resources are the functional units available to the machine
3843
3844 // Generic RISC-V pipeline
3845 // 1 decoder
3846 // 1 instruction decoded per cycle
3847 // 1 load/store ops per cycle, 1 branch, 1 FPU
3848 // 1 mul, 1 div
3849
3850 resources ( DECODE,
3851 ALU,
3852 MUL,
3853 DIV,
3854 BRANCH,
3855 LDST,
3856 FPU);
3857
3858 //----------PIPELINE DESCRIPTION-----------------------------------------------
3859 // Pipeline Description specifies the stages in the machine's pipeline
3860
3861 // Define the pipeline as a generic 6 stage pipeline
3862 pipe_desc(S0, S1, S2, S3, S4, S5);
3863
3864 //----------PIPELINE CLASSES---------------------------------------------------
3865 // Pipeline Classes describe the stages in which input and output are
3866 // referenced by the hardware pipeline.
3867
3868 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3869 %{
3870 single_instruction;
3871 src1 : S1(read);
3872 src2 : S2(read);
3873 dst : S5(write);
3874 DECODE : ID;
3875 FPU : S5;
3876 %}
3877
3878 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3879 %{
3880 src1 : S1(read);
3881 src2 : S2(read);
3882 dst : S5(write);
3883 DECODE : ID;
3884 FPU : S5;
3885 %}
3886
3887 pipe_class fp_uop_s(fRegF dst, fRegF src)
3888 %{
3889 single_instruction;
3890 src : S1(read);
3891 dst : S5(write);
3892 DECODE : ID;
3893 FPU : S5;
3894 %}
3895
3896 pipe_class fp_uop_d(fRegD dst, fRegD src)
3897 %{
3898 single_instruction;
3899 src : S1(read);
3900 dst : S5(write);
3901 DECODE : ID;
3902 FPU : S5;
3903 %}
3904
3905 pipe_class fp_d2f(fRegF dst, fRegD src)
3906 %{
3907 single_instruction;
3908 src : S1(read);
3909 dst : S5(write);
3910 DECODE : ID;
3911 FPU : S5;
3912 %}
3913
3914 pipe_class fp_f2d(fRegD dst, fRegF src)
3915 %{
3916 single_instruction;
3917 src : S1(read);
3918 dst : S5(write);
3919 DECODE : ID;
3920 FPU : S5;
3921 %}
3922
3923 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3924 %{
3925 single_instruction;
3926 src : S1(read);
3927 dst : S5(write);
3928 DECODE : ID;
3929 FPU : S5;
3930 %}
3931
3932 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3933 %{
3934 single_instruction;
3935 src : S1(read);
3936 dst : S5(write);
3937 DECODE : ID;
3938 FPU : S5;
3939 %}
3940
3941 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3942 %{
3943 single_instruction;
3944 src : S1(read);
3945 dst : S5(write);
3946 DECODE : ID;
3947 FPU : S5;
3948 %}
3949
3950 pipe_class fp_l2f(fRegF dst, iRegL src)
3951 %{
3952 single_instruction;
3953 src : S1(read);
3954 dst : S5(write);
3955 DECODE : ID;
3956 FPU : S5;
3957 %}
3958
3959 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3960 %{
3961 single_instruction;
3962 src : S1(read);
3963 dst : S5(write);
3964 DECODE : ID;
3965 FPU : S5;
3966 %}
3967
3968 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3969 %{
3970 single_instruction;
3971 src : S1(read);
3972 dst : S5(write);
3973 DECODE : ID;
3974 FPU : S5;
3975 %}
3976
3977 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
3978 %{
3979 single_instruction;
3980 src : S1(read);
3981 dst : S5(write);
3982 DECODE : ID;
3983 FPU : S5;
3984 %}
3985
3986 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
3987 %{
3988 single_instruction;
3989 src : S1(read);
3990 dst : S5(write);
3991 DECODE : ID;
3992 FPU : S5;
3993 %}
3994
3995 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
3996 %{
3997 single_instruction;
3998 src1 : S1(read);
3999 src2 : S2(read);
4000 dst : S5(write);
4001 DECODE : ID;
4002 FPU : S5;
4003 %}
4004
4005 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4006 %{
4007 single_instruction;
4008 src1 : S1(read);
4009 src2 : S2(read);
4010 dst : S5(write);
4011 DECODE : ID;
4012 FPU : S5;
4013 %}
4014
4015 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4016 %{
4017 single_instruction;
4018 src : S1(read);
4019 dst : S5(write);
4020 DECODE : ID;
4021 FPU : S5;
4022 %}
4023
4024 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4025 %{
4026 single_instruction;
4027 src : S1(read);
4028 dst : S5(write);
4029 DECODE : ID;
4030 FPU : S5;
4031 %}
4032
4033 pipe_class fp_load_constant_s(fRegF dst)
4034 %{
4035 single_instruction;
4036 dst : S5(write);
4037 DECODE : ID;
4038 FPU : S5;
4039 %}
4040
4041 pipe_class fp_load_constant_d(fRegD dst)
4042 %{
4043 single_instruction;
4044 dst : S5(write);
4045 DECODE : ID;
4046 FPU : S5;
4047 %}
4048
4049 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4050 %{
4051 single_instruction;
4052 mem : S1(read);
4053 dst : S5(write);
4054 DECODE : ID;
4055 LDST : MEM;
4056 %}
4057
4058 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4059 %{
4060 single_instruction;
4061 mem : S1(read);
4062 dst : S5(write);
4063 DECODE : ID;
4064 LDST : MEM;
4065 %}
4066
4067 pipe_class fp_store_reg_s(fRegF src, memory mem)
4068 %{
4069 single_instruction;
4070 src : S1(read);
4071 mem : S5(write);
4072 DECODE : ID;
4073 LDST : MEM;
4074 %}
4075
4076 pipe_class fp_store_reg_d(fRegD src, memory mem)
4077 %{
4078 single_instruction;
4079 src : S1(read);
4080 mem : S5(write);
4081 DECODE : ID;
4082 LDST : MEM;
4083 %}
4084
4085 //------- Integer ALU operations --------------------------
4086
4087 // Integer ALU reg-reg operation
4088 // Operands needs in ID, result generated in EX
4089 // E.g. ADD Rd, Rs1, Rs2
4090 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4091 %{
4092 single_instruction;
4093 dst : EX(write);
4094 src1 : ID(read);
4095 src2 : ID(read);
4096 DECODE : ID;
4097 ALU : EX;
4098 %}
4099
4100 // Integer ALU reg operation with constant shift
4101 // E.g. SLLI Rd, Rs1, #shift
4102 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4103 %{
4104 single_instruction;
4105 dst : EX(write);
4106 src1 : ID(read);
4107 DECODE : ID;
4108 ALU : EX;
4109 %}
4110
4111 // Integer ALU reg-reg operation with variable shift
4112 // both operands must be available in ID
4113 // E.g. SLL Rd, Rs1, Rs2
4114 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4115 %{
4116 single_instruction;
4117 dst : EX(write);
4118 src1 : ID(read);
4119 src2 : ID(read);
4120 DECODE : ID;
4121 ALU : EX;
4122 %}
4123
4124 // Integer ALU reg operation
4125 // E.g. NEG Rd, Rs2
4126 pipe_class ialu_reg(iRegI dst, iRegI src)
4127 %{
4128 single_instruction;
4129 dst : EX(write);
4130 src : ID(read);
4131 DECODE : ID;
4132 ALU : EX;
4133 %}
4134
4135 // Integer ALU reg immediate operation
4136 // E.g. ADDI Rd, Rs1, #imm
4137 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4138 %{
4139 single_instruction;
4140 dst : EX(write);
4141 src1 : ID(read);
4142 DECODE : ID;
4143 ALU : EX;
4144 %}
4145
4146 // Integer ALU immediate operation (no source operands)
4147 // E.g. LI Rd, #imm
4148 pipe_class ialu_imm(iRegI dst)
4149 %{
4150 single_instruction;
4151 dst : EX(write);
4152 DECODE : ID;
4153 ALU : EX;
4154 %}
4155
4156 //------- Multiply pipeline operations --------------------
4157
4158 // Multiply reg-reg
4159 // E.g. MULW Rd, Rs1, Rs2
4160 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4161 %{
4162 single_instruction;
4163 dst : WR(write);
4164 src1 : ID(read);
4165 src2 : ID(read);
4166 DECODE : ID;
4167 MUL : WR;
4168 %}
4169
4170 // E.g. MUL RD, Rs1, Rs2
4171 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4172 %{
4173 single_instruction;
4174 fixed_latency(3); // Maximum latency for 64 bit mul
4175 dst : WR(write);
4176 src1 : ID(read);
4177 src2 : ID(read);
4178 DECODE : ID;
4179 MUL : WR;
4180 %}
4181
4182 //------- Divide pipeline operations --------------------
4183
4184 // E.g. DIVW Rd, Rs1, Rs2
4185 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4186 %{
4187 single_instruction;
4188 fixed_latency(8); // Maximum latency for 32 bit divide
4189 dst : WR(write);
4190 src1 : ID(read);
4191 src2 : ID(read);
4192 DECODE : ID;
4193 DIV : WR;
4194 %}
4195
4196 // E.g. DIV RD, Rs1, Rs2
4197 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4198 %{
4199 single_instruction;
4200 fixed_latency(16); // Maximum latency for 64 bit divide
4201 dst : WR(write);
4202 src1 : ID(read);
4203 src2 : ID(read);
4204 DECODE : ID;
4205 DIV : WR;
4206 %}
4207
4208 //------- Load pipeline operations ------------------------
4209
4210 // Load - prefetch
4211 // Eg. PREFETCH_W mem
4212 pipe_class iload_prefetch(memory mem)
4213 %{
4214 single_instruction;
4215 mem : ID(read);
4216 DECODE : ID;
4217 LDST : MEM;
4218 %}
4219
4220 // Load - reg, mem
4221 // E.g. LA Rd, mem
4222 pipe_class iload_reg_mem(iRegI dst, memory mem)
4223 %{
4224 single_instruction;
4225 dst : WR(write);
4226 mem : ID(read);
4227 DECODE : ID;
4228 LDST : MEM;
4229 %}
4230
4231 // Load - reg, reg
4232 // E.g. LD Rd, Rs
4233 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4234 %{
4235 single_instruction;
4236 dst : WR(write);
4237 src : ID(read);
4238 DECODE : ID;
4239 LDST : MEM;
4240 %}
4241
4242 //------- Store pipeline operations -----------------------
4243
4244 // Store - zr, mem
4245 // E.g. SD zr, mem
4246 pipe_class istore_mem(memory mem)
4247 %{
4248 single_instruction;
4249 mem : ID(read);
4250 DECODE : ID;
4251 LDST : MEM;
4252 %}
4253
4254 // Store - reg, mem
4255 // E.g. SD Rs, mem
4256 pipe_class istore_reg_mem(iRegI src, memory mem)
4257 %{
4258 single_instruction;
4259 mem : ID(read);
4260 src : EX(read);
4261 DECODE : ID;
4262 LDST : MEM;
4263 %}
4264
4265 // Store - reg, reg
4266 // E.g. SD Rs2, Rs1
4267 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4268 %{
4269 single_instruction;
4270 dst : ID(read);
4271 src : EX(read);
4272 DECODE : ID;
4273 LDST : MEM;
4274 %}
4275
4276 //------- Control transfer pipeline operations ------------
4277
4278 // Branch
4279 pipe_class pipe_branch()
4280 %{
4281 single_instruction;
4282 DECODE : ID;
4283 BRANCH : EX;
4284 %}
4285
4286 // Branch
4287 pipe_class pipe_branch_reg(iRegI src)
4288 %{
4289 single_instruction;
4290 src : ID(read);
4291 DECODE : ID;
4292 BRANCH : EX;
4293 %}
4294
4295 // Compare & Branch
4296 // E.g. BEQ Rs1, Rs2, L
4297 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4298 %{
4299 single_instruction;
4300 src1 : ID(read);
4301 src2 : ID(read);
4302 DECODE : ID;
4303 BRANCH : EX;
4304 %}
4305
4306 // E.g. BEQZ Rs, L
4307 pipe_class pipe_cmpz_branch(iRegI src)
4308 %{
4309 single_instruction;
4310 src : ID(read);
4311 DECODE : ID;
4312 BRANCH : EX;
4313 %}
4314
4315 //------- Synchronisation operations ----------------------
4316 // Any operation requiring serialization
4317 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4318 pipe_class pipe_serial()
4319 %{
4320 single_instruction;
4321 force_serialization;
4322 fixed_latency(16);
4323 DECODE : ID;
4324 LDST : MEM;
4325 %}
4326
4327 pipe_class pipe_slow()
4328 %{
4329 instruction_count(10);
4330 multiple_bundles;
4331 force_serialization;
4332 fixed_latency(16);
4333 DECODE : ID;
4334 LDST : MEM;
4335 %}
4336
4337 // The real do-nothing guy
4338 pipe_class real_empty()
4339 %{
4340 instruction_count(0);
4341 %}
4342
4343 // Empty pipeline class
4344 pipe_class pipe_class_empty()
4345 %{
4346 single_instruction;
4347 fixed_latency(0);
4348 %}
4349
4350 // Default pipeline class.
4351 pipe_class pipe_class_default()
4352 %{
4353 single_instruction;
4354 fixed_latency(2);
4355 %}
4356
4357 // Pipeline class for compares.
4358 pipe_class pipe_class_compare()
4359 %{
4360 single_instruction;
4361 fixed_latency(16);
4362 %}
4363
4364 // Pipeline class for memory operations.
4365 pipe_class pipe_class_memory()
4366 %{
4367 single_instruction;
4368 fixed_latency(16);
4369 %}
4370
4371 // Pipeline class for call.
4372 pipe_class pipe_class_call()
4373 %{
4374 single_instruction;
4375 fixed_latency(100);
4376 %}
4377
4378 // Define the class for the Nop node.
4379 define %{
4380 MachNop = pipe_class_empty;
4381 %}
4382 %}
4383 //----------INSTRUCTIONS-------------------------------------------------------
4384 //
4385 // match -- States which machine-independent subtree may be replaced
4386 // by this instruction.
4387 // ins_cost -- The estimated cost of this instruction is used by instruction
4388 // selection to identify a minimum cost tree of machine
4389 // instructions that matches a tree of machine-independent
4390 // instructions.
4391 // format -- A string providing the disassembly for this instruction.
4392 // The value of an instruction's operand may be inserted
4393 // by referring to it with a '$' prefix.
4394 // opcode -- Three instruction opcodes may be provided. These are referred
4395 // to within an encode class as $primary, $secondary, and $tertiary
4396 // rrspectively. The primary opcode is commonly used to
4397 // indicate the type of machine instruction, while secondary
4398 // and tertiary are often used for prefix options or addressing
4399 // modes.
4400 // ins_encode -- A list of encode classes with parameters. The encode class
4401 // name must have been defined in an 'enc_class' specification
4402 // in the encode section of the architecture description.
4403
4404 // ============================================================================
4405 // Memory (Load/Store) Instructions
4406
4407 // Load Instructions
4408
4409 // Load Byte (8 bit signed)
4410 instruct loadB(iRegINoSp dst, memory mem)
4411 %{
4412 match(Set dst (LoadB mem));
4413
4414 ins_cost(LOAD_COST);
4415 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4416
4417 ins_encode %{
4418 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4419 %}
4420
4421 ins_pipe(iload_reg_mem);
4422 %}
4423
4424 // Load Byte (8 bit signed) into long
4425 instruct loadB2L(iRegLNoSp dst, memory mem)
4426 %{
4427 match(Set dst (ConvI2L (LoadB mem)));
4428
4429 ins_cost(LOAD_COST);
4430 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4431
4432 ins_encode %{
4433 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4434 %}
4435
4436 ins_pipe(iload_reg_mem);
4437 %}
4438
4439 // Load Byte (8 bit unsigned)
4440 instruct loadUB(iRegINoSp dst, memory mem)
4441 %{
4442 match(Set dst (LoadUB mem));
4443
4444 ins_cost(LOAD_COST);
4445 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4446
4447 ins_encode %{
4448 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4449 %}
4450
4451 ins_pipe(iload_reg_mem);
4452 %}
4453
4454 // Load Byte (8 bit unsigned) into long
4455 instruct loadUB2L(iRegLNoSp dst, memory mem)
4456 %{
4457 match(Set dst (ConvI2L (LoadUB mem)));
4458
4459 ins_cost(LOAD_COST);
4460 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4461
4462 ins_encode %{
4463 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4464 %}
4465
4466 ins_pipe(iload_reg_mem);
4467 %}
4468
4469 // Load Short (16 bit signed)
4470 instruct loadS(iRegINoSp dst, memory mem)
4471 %{
4472 match(Set dst (LoadS mem));
4473
4474 ins_cost(LOAD_COST);
4475 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4476
4477 ins_encode %{
4478 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4479 %}
4480
4481 ins_pipe(iload_reg_mem);
4482 %}
4483
4484 // Load Short (16 bit signed) into long
4485 instruct loadS2L(iRegLNoSp dst, memory mem)
4486 %{
4487 match(Set dst (ConvI2L (LoadS mem)));
4488
4489 ins_cost(LOAD_COST);
4490 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4491
4492 ins_encode %{
4493 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4494 %}
4495
4496 ins_pipe(iload_reg_mem);
4497 %}
4498
4499 // Load Char (16 bit unsigned)
4500 instruct loadUS(iRegINoSp dst, memory mem)
4501 %{
4502 match(Set dst (LoadUS mem));
4503
4504 ins_cost(LOAD_COST);
4505 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4506
4507 ins_encode %{
4508 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4509 %}
4510
4511 ins_pipe(iload_reg_mem);
4512 %}
4513
4514 // Load Short/Char (16 bit unsigned) into long
4515 instruct loadUS2L(iRegLNoSp dst, memory mem)
4516 %{
4517 match(Set dst (ConvI2L (LoadUS mem)));
4518
4519 ins_cost(LOAD_COST);
4520 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4521
4522 ins_encode %{
4523 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4524 %}
4525
4526 ins_pipe(iload_reg_mem);
4527 %}
4528
4529 // Load Integer (32 bit signed)
4530 instruct loadI(iRegINoSp dst, memory mem)
4531 %{
4532 match(Set dst (LoadI mem));
4533
4534 ins_cost(LOAD_COST);
4535 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4536
4537 ins_encode %{
4538 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4539 %}
4540
4541 ins_pipe(iload_reg_mem);
4542 %}
4543
4544 // Load Integer (32 bit signed) into long
4545 instruct loadI2L(iRegLNoSp dst, memory mem)
4546 %{
4547 match(Set dst (ConvI2L (LoadI mem)));
4548
4549 ins_cost(LOAD_COST);
4550 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4551
4552 ins_encode %{
4553 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4554 %}
4555
4556 ins_pipe(iload_reg_mem);
4557 %}
4558
4559 // Load Integer (32 bit unsigned) into long
4560 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4561 %{
4562 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4563
4564 ins_cost(LOAD_COST);
4565 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4566
4567 ins_encode %{
4568 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4569 %}
4570
4571 ins_pipe(iload_reg_mem);
4572 %}
4573
4574 // Load Long (64 bit signed)
4575 instruct loadL(iRegLNoSp dst, memory mem)
4576 %{
4577 match(Set dst (LoadL mem));
4578
4579 ins_cost(LOAD_COST);
4580 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4581
4582 ins_encode %{
4583 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4584 %}
4585
4586 ins_pipe(iload_reg_mem);
4587 %}
4588
4589 // Load Range
4590 instruct loadRange(iRegINoSp dst, memory mem)
4591 %{
4592 match(Set dst (LoadRange mem));
4593
4594 ins_cost(LOAD_COST);
4595 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4596
4597 ins_encode %{
4598 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4599 %}
4600
4601 ins_pipe(iload_reg_mem);
4602 %}
4603
4604 // Load Pointer
4605 instruct loadP(iRegPNoSp dst, memory mem)
4606 %{
4607 match(Set dst (LoadP mem));
4608 predicate(n->as_Load()->barrier_data() == 0);
4609
4610 ins_cost(LOAD_COST);
4611 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4612
4613 ins_encode %{
4614 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4615 %}
4616
4617 ins_pipe(iload_reg_mem);
4618 %}
4619
4620 // Load Compressed Pointer
4621 instruct loadN(iRegNNoSp dst, memory mem)
4622 %{
4623 predicate(n->as_Load()->barrier_data() == 0);
4624 match(Set dst (LoadN mem));
4625
4626 ins_cost(LOAD_COST);
4627 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4628
4629 ins_encode %{
4630 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4631 %}
4632
4633 ins_pipe(iload_reg_mem);
4634 %}
4635
4636 // Load Klass Pointer
4637 instruct loadKlass(iRegPNoSp dst, memory mem)
4638 %{
4639 match(Set dst (LoadKlass mem));
4640
4641 ins_cost(LOAD_COST);
4642 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4643
4644 ins_encode %{
4645 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4646 %}
4647
4648 ins_pipe(iload_reg_mem);
4649 %}
4650
4651 // Load Narrow Klass Pointer
4652 instruct loadNKlass(iRegNNoSp dst, memory mem)
4653 %{
4654 predicate(!UseCompactObjectHeaders);
4655 match(Set dst (LoadNKlass mem));
4656
4657 ins_cost(LOAD_COST);
4658 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4659
4660 ins_encode %{
4661 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4662 %}
4663
4664 ins_pipe(iload_reg_mem);
4665 %}
4666
4667 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4668 %{
4669 predicate(UseCompactObjectHeaders);
4670 match(Set dst (LoadNKlass mem));
4671
4672 ins_cost(LOAD_COST);
4673 format %{
4674 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4675 "srli $dst, $dst, markWord::klass_shift_at_offset"
4676 %}
4677
4678 ins_encode %{
4679 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4680 __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4681 %}
4682
4683 ins_pipe(iload_reg_mem);
4684 %}
4685
4686 // Load Float
4687 instruct loadF(fRegF dst, memory mem)
4688 %{
4689 match(Set dst (LoadF mem));
4690
4691 ins_cost(LOAD_COST);
4692 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4693
4694 ins_encode %{
4695 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4696 %}
4697
4698 ins_pipe(fp_load_mem_s);
4699 %}
4700
4701 // Load Double
4702 instruct loadD(fRegD dst, memory mem)
4703 %{
4704 match(Set dst (LoadD mem));
4705
4706 ins_cost(LOAD_COST);
4707 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4708
4709 ins_encode %{
4710 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4711 %}
4712
4713 ins_pipe(fp_load_mem_d);
4714 %}
4715
4716 // Load Int Constant
4717 instruct loadConI(iRegINoSp dst, immI src)
4718 %{
4719 match(Set dst src);
4720
4721 ins_cost(ALU_COST);
4722 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4723
4724 ins_encode(riscv_enc_mov_imm(dst, src));
4725
4726 ins_pipe(ialu_imm);
4727 %}
4728
4729 // Load Long Constant
4730 instruct loadConL(iRegLNoSp dst, immL src)
4731 %{
4732 match(Set dst src);
4733
4734 ins_cost(ALU_COST);
4735 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4736
4737 ins_encode(riscv_enc_mov_imm(dst, src));
4738
4739 ins_pipe(ialu_imm);
4740 %}
4741
4742 // Load Pointer Constant
4743 instruct loadConP(iRegPNoSp dst, immP con)
4744 %{
4745 match(Set dst con);
4746
4747 ins_cost(ALU_COST);
4748 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4749
4750 ins_encode(riscv_enc_mov_p(dst, con));
4751
4752 ins_pipe(ialu_imm);
4753 %}
4754
4755 // Load Null Pointer Constant
4756 instruct loadConP0(iRegPNoSp dst, immP0 con)
4757 %{
4758 match(Set dst con);
4759
4760 ins_cost(ALU_COST);
4761 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4762
4763 ins_encode(riscv_enc_mov_zero(dst));
4764
4765 ins_pipe(ialu_imm);
4766 %}
4767
4768 // Load Pointer Constant One
4769 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4770 %{
4771 match(Set dst con);
4772
4773 ins_cost(ALU_COST);
4774 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4775
4776 ins_encode(riscv_enc_mov_p1(dst));
4777
4778 ins_pipe(ialu_imm);
4779 %}
4780
4781 // Load Narrow Pointer Constant
4782 instruct loadConN(iRegNNoSp dst, immN con)
4783 %{
4784 match(Set dst con);
4785
4786 ins_cost(ALU_COST * 4);
4787 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4788
4789 ins_encode(riscv_enc_mov_n(dst, con));
4790
4791 ins_pipe(ialu_imm);
4792 %}
4793
4794 // Load Narrow Null Pointer Constant
4795 instruct loadConN0(iRegNNoSp dst, immN0 con)
4796 %{
4797 match(Set dst con);
4798
4799 ins_cost(ALU_COST);
4800 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4801
4802 ins_encode(riscv_enc_mov_zero(dst));
4803
4804 ins_pipe(ialu_imm);
4805 %}
4806
4807 // Load Narrow Klass Constant
4808 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4809 %{
4810 match(Set dst con);
4811
4812 ins_cost(ALU_COST * 6);
4813 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4814
4815 ins_encode(riscv_enc_mov_nk(dst, con));
4816
4817 ins_pipe(ialu_imm);
4818 %}
4819
4820 // Load Half Float Constant
4821 instruct loadConH(fRegF dst, immH con) %{
4822 match(Set dst con);
4823
4824 ins_cost(LOAD_COST);
4825 format %{
4826 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4827 %}
4828
4829 ins_encode %{
4830 assert(UseZfh || UseZfhmin, "must");
4831 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4832 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4833 } else {
4834 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4835 }
4836 %}
4837
4838 ins_pipe(fp_load_constant_s);
4839 %}
4840
4841 instruct loadConH0(fRegF dst, immH0 con) %{
4842 match(Set dst con);
4843
4844 ins_cost(XFER_COST);
4845
4846 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4847
4848 ins_encode %{
4849 assert(UseZfh || UseZfhmin, "must");
4850 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4851 %}
4852
4853 ins_pipe(fp_load_constant_s);
4854 %}
4855
4856 // Load Float Constant
4857 instruct loadConF(fRegF dst, immF con) %{
4858 match(Set dst con);
4859
4860 ins_cost(LOAD_COST);
4861 format %{
4862 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4863 %}
4864
4865 ins_encode %{
4866 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4867 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4868 } else {
4869 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4870 }
4871 %}
4872
4873 ins_pipe(fp_load_constant_s);
4874 %}
4875
4876 instruct loadConF0(fRegF dst, immF0 con) %{
4877 match(Set dst con);
4878
4879 ins_cost(XFER_COST);
4880
4881 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4882
4883 ins_encode %{
4884 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4885 %}
4886
4887 ins_pipe(fp_load_constant_s);
4888 %}
4889
4890 // Load Double Constant
4891 instruct loadConD(fRegD dst, immD con) %{
4892 match(Set dst con);
4893
4894 ins_cost(LOAD_COST);
4895 format %{
4896 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4897 %}
4898
4899 ins_encode %{
4900 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4901 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4902 } else {
4903 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4904 }
4905 %}
4906
4907 ins_pipe(fp_load_constant_d);
4908 %}
4909
4910 instruct loadConD0(fRegD dst, immD0 con) %{
4911 match(Set dst con);
4912
4913 ins_cost(XFER_COST);
4914
4915 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4916
4917 ins_encode %{
4918 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4919 %}
4920
4921 ins_pipe(fp_load_constant_d);
4922 %}
4923
4924 // Store Byte
4925 instruct storeB(iRegIorL2I src, memory mem)
4926 %{
4927 match(Set mem (StoreB mem src));
4928
4929 ins_cost(STORE_COST);
4930 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4931
4932 ins_encode %{
4933 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4934 %}
4935
4936 ins_pipe(istore_reg_mem);
4937 %}
4938
4939 instruct storeimmB0(immI0 zero, memory mem)
4940 %{
4941 match(Set mem (StoreB mem zero));
4942
4943 ins_cost(STORE_COST);
4944 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4945
4946 ins_encode %{
4947 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4948 %}
4949
4950 ins_pipe(istore_mem);
4951 %}
4952
4953 // Store Char/Short
4954 instruct storeC(iRegIorL2I src, memory mem)
4955 %{
4956 match(Set mem (StoreC mem src));
4957
4958 ins_cost(STORE_COST);
4959 format %{ "sh $src, $mem\t# short, #@storeC" %}
4960
4961 ins_encode %{
4962 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4963 %}
4964
4965 ins_pipe(istore_reg_mem);
4966 %}
4967
4968 instruct storeimmC0(immI0 zero, memory mem)
4969 %{
4970 match(Set mem (StoreC mem zero));
4971
4972 ins_cost(STORE_COST);
4973 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4974
4975 ins_encode %{
4976 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4977 %}
4978
4979 ins_pipe(istore_mem);
4980 %}
4981
4982 // Store Integer
4983 instruct storeI(iRegIorL2I src, memory mem)
4984 %{
4985 match(Set mem(StoreI mem src));
4986
4987 ins_cost(STORE_COST);
4988 format %{ "sw $src, $mem\t# int, #@storeI" %}
4989
4990 ins_encode %{
4991 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4992 %}
4993
4994 ins_pipe(istore_reg_mem);
4995 %}
4996
4997 instruct storeimmI0(immI0 zero, memory mem)
4998 %{
4999 match(Set mem(StoreI mem zero));
5000
5001 ins_cost(STORE_COST);
5002 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5003
5004 ins_encode %{
5005 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5006 %}
5007
5008 ins_pipe(istore_mem);
5009 %}
5010
5011 // Store Long (64 bit signed)
5012 instruct storeL(iRegL src, memory mem)
5013 %{
5014 match(Set mem (StoreL mem src));
5015
5016 ins_cost(STORE_COST);
5017 format %{ "sd $src, $mem\t# long, #@storeL" %}
5018
5019 ins_encode %{
5020 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5021 %}
5022
5023 ins_pipe(istore_reg_mem);
5024 %}
5025
5026 // Store Long (64 bit signed)
5027 instruct storeimmL0(immL0 zero, memory mem)
5028 %{
5029 match(Set mem (StoreL mem zero));
5030
5031 ins_cost(STORE_COST);
5032 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5033
5034 ins_encode %{
5035 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5036 %}
5037
5038 ins_pipe(istore_mem);
5039 %}
5040
5041 // Store Pointer
5042 instruct storeP(iRegP src, memory mem)
5043 %{
5044 match(Set mem (StoreP mem src));
5045 predicate(n->as_Store()->barrier_data() == 0);
5046
5047 ins_cost(STORE_COST);
5048 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5049
5050 ins_encode %{
5051 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5052 %}
5053
5054 ins_pipe(istore_reg_mem);
5055 %}
5056
5057 // Store Pointer
5058 instruct storeimmP0(immP0 zero, memory mem)
5059 %{
5060 match(Set mem (StoreP mem zero));
5061 predicate(n->as_Store()->barrier_data() == 0);
5062
5063 ins_cost(STORE_COST);
5064 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5065
5066 ins_encode %{
5067 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5068 %}
5069
5070 ins_pipe(istore_mem);
5071 %}
5072
5073 // Store Compressed Pointer
5074 instruct storeN(iRegN src, memory mem)
5075 %{
5076 predicate(n->as_Store()->barrier_data() == 0);
5077 match(Set mem (StoreN mem src));
5078
5079 ins_cost(STORE_COST);
5080 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5081
5082 ins_encode %{
5083 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5084 %}
5085
5086 ins_pipe(istore_reg_mem);
5087 %}
5088
5089 instruct storeImmN0(immN0 zero, memory mem)
5090 %{
5091 predicate(n->as_Store()->barrier_data() == 0);
5092 match(Set mem (StoreN mem zero));
5093
5094 ins_cost(STORE_COST);
5095 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5096
5097 ins_encode %{
5098 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5099 %}
5100
5101 ins_pipe(istore_reg_mem);
5102 %}
5103
5104 // Store Float
5105 instruct storeF(fRegF src, memory mem)
5106 %{
5107 match(Set mem (StoreF mem src));
5108
5109 ins_cost(STORE_COST);
5110 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5111
5112 ins_encode %{
5113 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5114 %}
5115
5116 ins_pipe(fp_store_reg_s);
5117 %}
5118
5119 // Store Double
5120 instruct storeD(fRegD src, memory mem)
5121 %{
5122 match(Set mem (StoreD mem src));
5123
5124 ins_cost(STORE_COST);
5125 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5126
5127 ins_encode %{
5128 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5129 %}
5130
5131 ins_pipe(fp_store_reg_d);
5132 %}
5133
5134 // Store Compressed Klass Pointer
5135 instruct storeNKlass(iRegN src, memory mem)
5136 %{
5137 match(Set mem (StoreNKlass mem src));
5138
5139 ins_cost(STORE_COST);
5140 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5141
5142 ins_encode %{
5143 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5144 %}
5145
5146 ins_pipe(istore_reg_mem);
5147 %}
5148
5149 // ============================================================================
5150 // Prefetch instructions
5151 // Must be safe to execute with invalid address (cannot fault).
5152
5153 instruct prefetchalloc( memory mem ) %{
5154 predicate(UseZicbop);
5155 match(PrefetchAllocation mem);
5156
5157 ins_cost(ALU_COST * 1);
5158 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5159
5160 ins_encode %{
5161 if (Assembler::is_simm12($mem$$disp)) {
5162 if (($mem$$disp & 0x1f) == 0) {
5163 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5164 } else {
5165 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5166 __ prefetch_w(t0, 0);
5167 }
5168 } else {
5169 __ mv(t0, $mem$$disp);
5170 __ add(t0, as_Register($mem$$base), t0);
5171 __ prefetch_w(t0, 0);
5172 }
5173 %}
5174
5175 ins_pipe(iload_prefetch);
5176 %}
5177
5178 // ============================================================================
5179 // Atomic operation instructions
5180 //
5181
5182 // standard CompareAndSwapX when we are using barriers
5183 // these have higher priority than the rules selected by a predicate
5184 instruct compareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5185 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5186 %{
5187 predicate(!UseZabha || !UseZacas);
5188
5189 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5190
5191 ins_cost(2 * VOLATILE_REF_COST);
5192
5193 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5194
5195 format %{
5196 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5197 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB_narrow"
5198 %}
5199
5200 ins_encode %{
5201 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5202 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5203 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5204 %}
5205
5206 ins_pipe(pipe_slow);
5207 %}
5208
5209 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5210 %{
5211 predicate(UseZabha && UseZacas);
5212
5213 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5214
5215 ins_cost(2 * VOLATILE_REF_COST);
5216
5217 format %{
5218 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5219 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5220 %}
5221
5222 ins_encode %{
5223 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5224 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5225 true /* result as bool */);
5226 %}
5227
5228 ins_pipe(pipe_slow);
5229 %}
5230
5231 instruct compareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5232 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5233 %{
5234 predicate(!UseZabha || !UseZacas);
5235
5236 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5237
5238 ins_cost(2 * VOLATILE_REF_COST);
5239
5240 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5241
5242 format %{
5243 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5244 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS_narrow"
5245 %}
5246
5247 ins_encode %{
5248 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5249 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5250 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5251 %}
5252
5253 ins_pipe(pipe_slow);
5254 %}
5255
5256 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5257 %{
5258 predicate(UseZabha && UseZacas);
5259
5260 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5261
5262 ins_cost(2 * VOLATILE_REF_COST);
5263
5264 format %{
5265 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5266 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5267 %}
5268
5269 ins_encode %{
5270 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5271 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5272 true /* result as bool */);
5273 %}
5274
5275 ins_pipe(pipe_slow);
5276 %}
5277
5278 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5279 %{
5280 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5281
5282 ins_cost(2 * VOLATILE_REF_COST);
5283
5284 format %{
5285 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5286 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5287 %}
5288
5289 ins_encode %{
5290 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5291 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5292 /*result as bool*/ true);
5293 %}
5294
5295 ins_pipe(pipe_slow);
5296 %}
5297
5298 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5299 %{
5300 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5301
5302 ins_cost(2 * VOLATILE_REF_COST);
5303
5304 format %{
5305 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5306 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5307 %}
5308
5309 ins_encode %{
5310 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5311 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5312 /*result as bool*/ true);
5313 %}
5314
5315 ins_pipe(pipe_slow);
5316 %}
5317
5318 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5319 %{
5320 predicate(n->as_LoadStore()->barrier_data() == 0);
5321
5322 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5323
5324 ins_cost(2 * VOLATILE_REF_COST);
5325
5326 format %{
5327 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5328 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5329 %}
5330
5331 ins_encode %{
5332 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5333 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5334 /*result as bool*/ true);
5335 %}
5336
5337 ins_pipe(pipe_slow);
5338 %}
5339
5340 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5341 %{
5342 predicate(n->as_LoadStore()->barrier_data() == 0);
5343
5344 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5345
5346 ins_cost(2 * VOLATILE_REF_COST);
5347
5348 format %{
5349 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5350 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5351 %}
5352
5353 ins_encode %{
5354 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5355 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5356 /*result as bool*/ true);
5357 %}
5358
5359 ins_pipe(pipe_slow);
5360 %}
5361
5362 // alternative CompareAndSwapX when we are eliding barriers
5363 instruct compareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5364 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5365 %{
5366 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5367
5368 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5369
5370 ins_cost(2 * VOLATILE_REF_COST);
5371
5372 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5373
5374 format %{
5375 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5376 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq_narrow"
5377 %}
5378
5379 ins_encode %{
5380 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5381 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5382 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5383 %}
5384
5385 ins_pipe(pipe_slow);
5386 %}
5387
5388 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5389 %{
5390 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5391
5392 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5393
5394 ins_cost(2 * VOLATILE_REF_COST);
5395
5396 format %{
5397 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5398 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5399 %}
5400
5401 ins_encode %{
5402 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5403 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5404 true /* result as bool */);
5405 %}
5406
5407 ins_pipe(pipe_slow);
5408 %}
5409
5410 instruct compareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5411 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5412 %{
5413 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5414
5415 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5416
5417 ins_cost(2 * VOLATILE_REF_COST);
5418
5419 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5420
5421 format %{
5422 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5423 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq_narrow"
5424 %}
5425
5426 ins_encode %{
5427 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5428 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5429 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5430 %}
5431
5432 ins_pipe(pipe_slow);
5433 %}
5434
5435 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5436 %{
5437 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5438
5439 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5440
5441 ins_cost(2 * VOLATILE_REF_COST);
5442
5443 format %{
5444 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5445 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5446 %}
5447
5448 ins_encode %{
5449 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5450 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5451 true /* result as bool */);
5452 %}
5453
5454 ins_pipe(pipe_slow);
5455 %}
5456
5457 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5458 %{
5459 predicate(needs_acquiring_load_reserved(n));
5460
5461 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5462
5463 ins_cost(2 * VOLATILE_REF_COST);
5464
5465 format %{
5466 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5467 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5468 %}
5469
5470 ins_encode %{
5471 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5472 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5473 /*result as bool*/ true);
5474 %}
5475
5476 ins_pipe(pipe_slow);
5477 %}
5478
5479 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5480 %{
5481 predicate(needs_acquiring_load_reserved(n));
5482
5483 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5484
5485 ins_cost(2 * VOLATILE_REF_COST);
5486
5487 format %{
5488 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5489 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5490 %}
5491
5492 ins_encode %{
5493 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5494 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5495 /*result as bool*/ true);
5496 %}
5497
5498 ins_pipe(pipe_slow);
5499 %}
5500
5501 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5502 %{
5503 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5504
5505 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5506
5507 ins_cost(2 * VOLATILE_REF_COST);
5508
5509 format %{
5510 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5511 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5512 %}
5513
5514 ins_encode %{
5515 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5516 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5517 /*result as bool*/ true);
5518 %}
5519
5520 ins_pipe(pipe_slow);
5521 %}
5522
5523 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5524 %{
5525 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5526
5527 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5528
5529 ins_cost(2 * VOLATILE_REF_COST);
5530
5531 format %{
5532 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5533 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5534 %}
5535
5536 ins_encode %{
5537 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5538 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5539 /*result as bool*/ true);
5540 %}
5541
5542 ins_pipe(pipe_slow);
5543 %}
5544
5545 // Sundry CAS operations. Note that release is always true,
5546 // regardless of the memory ordering of the CAS. This is because we
5547 // need the volatile case to be sequentially consistent but there is
5548 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5549 // can't check the type of memory ordering here, so we always emit a
5550 // sc_d(w) with rl bit set.
5551 instruct compareAndExchangeB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5552 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5553 %{
5554 predicate(!UseZabha || !UseZacas);
5555
5556 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5557
5558 ins_cost(2 * VOLATILE_REF_COST);
5559
5560 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5561
5562 format %{
5563 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB_narrow"
5564 %}
5565
5566 ins_encode %{
5567 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5568 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5569 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5570 %}
5571
5572 ins_pipe(pipe_slow);
5573 %}
5574
5575 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5576 %{
5577 predicate(UseZabha && UseZacas);
5578
5579 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5580
5581 ins_cost(2 * VOLATILE_REF_COST);
5582
5583 format %{
5584 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5585 %}
5586
5587 ins_encode %{
5588 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5589 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5590 %}
5591
5592 ins_pipe(pipe_slow);
5593 %}
5594
5595 instruct compareAndExchangeS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5596 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5597 %{
5598 predicate(!UseZabha || !UseZacas);
5599
5600 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5601
5602 ins_cost(2 * VOLATILE_REF_COST);
5603
5604 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5605
5606 format %{
5607 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS_narrow"
5608 %}
5609
5610 ins_encode %{
5611 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5612 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5613 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5614 %}
5615
5616 ins_pipe(pipe_slow);
5617 %}
5618
5619 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5620 %{
5621 predicate(UseZabha && UseZacas);
5622
5623 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5624
5625 ins_cost(2 * VOLATILE_REF_COST);
5626
5627 format %{
5628 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5629 %}
5630
5631 ins_encode %{
5632 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5633 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5634 %}
5635
5636 ins_pipe(pipe_slow);
5637 %}
5638
5639 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5640 %{
5641 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5642
5643 ins_cost(2 * VOLATILE_REF_COST);
5644
5645 format %{
5646 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5647 %}
5648
5649 ins_encode %{
5650 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5651 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5652 %}
5653
5654 ins_pipe(pipe_slow);
5655 %}
5656
5657 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5658 %{
5659 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5660
5661 ins_cost(2 * VOLATILE_REF_COST);
5662
5663 format %{
5664 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5665 %}
5666
5667 ins_encode %{
5668 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5669 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5670 %}
5671
5672 ins_pipe(pipe_slow);
5673 %}
5674
5675 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5676 %{
5677 predicate(n->as_LoadStore()->barrier_data() == 0);
5678
5679 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5680
5681 ins_cost(2 * VOLATILE_REF_COST);
5682
5683 format %{
5684 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5685 %}
5686
5687 ins_encode %{
5688 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5689 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5690 %}
5691
5692 ins_pipe(pipe_slow);
5693 %}
5694
5695 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5696 %{
5697 predicate(n->as_LoadStore()->barrier_data() == 0);
5698
5699 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5700
5701 ins_cost(2 * VOLATILE_REF_COST);
5702
5703 format %{
5704 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5705 %}
5706
5707 ins_encode %{
5708 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5709 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5710 %}
5711
5712 ins_pipe(pipe_slow);
5713 %}
5714
5715 instruct compareAndExchangeBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5716 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5717 %{
5718 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5719
5720 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5721
5722 ins_cost(2 * VOLATILE_REF_COST);
5723
5724 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5725
5726 format %{
5727 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq_narrow"
5728 %}
5729
5730 ins_encode %{
5731 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5732 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5733 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5734 %}
5735
5736 ins_pipe(pipe_slow);
5737 %}
5738
5739 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5740 %{
5741 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5742
5743 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5744
5745 ins_cost(2 * VOLATILE_REF_COST);
5746
5747 format %{
5748 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5749 %}
5750
5751 ins_encode %{
5752 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5753 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5754 %}
5755
5756 ins_pipe(pipe_slow);
5757 %}
5758
5759 instruct compareAndExchangeSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5760 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5761 %{
5762 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
5763
5764 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5765
5766 ins_cost(2 * VOLATILE_REF_COST);
5767
5768 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5769
5770 format %{
5771 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq_narrow"
5772 %}
5773
5774 ins_encode %{
5775 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5776 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5777 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5778 %}
5779
5780 ins_pipe(pipe_slow);
5781 %}
5782
5783 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5784 %{
5785 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
5786
5787 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5788
5789 ins_cost(2 * VOLATILE_REF_COST);
5790
5791 format %{
5792 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5793 %}
5794
5795 ins_encode %{
5796 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5797 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5798 %}
5799
5800 ins_pipe(pipe_slow);
5801 %}
5802
5803 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5804 %{
5805 predicate(needs_acquiring_load_reserved(n));
5806
5807 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5808
5809 ins_cost(2 * VOLATILE_REF_COST);
5810
5811 format %{
5812 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5813 %}
5814
5815 ins_encode %{
5816 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5817 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5818 %}
5819
5820 ins_pipe(pipe_slow);
5821 %}
5822
5823 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5824 %{
5825 predicate(needs_acquiring_load_reserved(n));
5826
5827 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5828
5829 ins_cost(2 * VOLATILE_REF_COST);
5830
5831 format %{
5832 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5833 %}
5834
5835 ins_encode %{
5836 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5837 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5838 %}
5839
5840 ins_pipe(pipe_slow);
5841 %}
5842
5843 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5844 %{
5845 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5846
5847 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5848
5849 ins_cost(2 * VOLATILE_REF_COST);
5850
5851 format %{
5852 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5853 %}
5854
5855 ins_encode %{
5856 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5857 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5858 %}
5859
5860 ins_pipe(pipe_slow);
5861 %}
5862
5863 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5864 %{
5865 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5866
5867 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5868
5869 ins_cost(2 * VOLATILE_REF_COST);
5870
5871 format %{
5872 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5873 %}
5874
5875 ins_encode %{
5876 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5877 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5878 %}
5879
5880 ins_pipe(pipe_slow);
5881 %}
5882
5883 instruct weakCompareAndSwapB_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5884 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5885 %{
5886 predicate(!UseZabha || !UseZacas);
5887
5888 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5889
5890 ins_cost(2 * VOLATILE_REF_COST);
5891
5892 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5893
5894 format %{
5895 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5896 "# $res == 1 when success, #@weakCompareAndSwapB_narrow"
5897 %}
5898
5899 ins_encode %{
5900 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5901 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5902 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5903 %}
5904
5905 ins_pipe(pipe_slow);
5906 %}
5907
5908 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5909 %{
5910 predicate(UseZabha && UseZacas);
5911
5912 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5913
5914 ins_cost(2 * VOLATILE_REF_COST);
5915
5916 format %{
5917 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5918 "# $res == 1 when success, #@weakCompareAndSwapB"
5919 %}
5920
5921 ins_encode %{
5922 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5923 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5924 %}
5925
5926 ins_pipe(pipe_slow);
5927 %}
5928
5929 instruct weakCompareAndSwapS_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5930 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5931 %{
5932 predicate(!UseZabha || !UseZacas);
5933
5934 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5935
5936 ins_cost(2 * VOLATILE_REF_COST);
5937
5938 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5939
5940 format %{
5941 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5942 "# $res == 1 when success, #@weakCompareAndSwapS_narrow"
5943 %}
5944
5945 ins_encode %{
5946 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5947 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5948 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5949 %}
5950
5951 ins_pipe(pipe_slow);
5952 %}
5953
5954 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5955 %{
5956 predicate(UseZabha && UseZacas);
5957
5958 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5959
5960 ins_cost(2 * VOLATILE_REF_COST);
5961
5962 format %{
5963 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5964 "# $res == 1 when success, #@weakCompareAndSwapS"
5965 %}
5966
5967 ins_encode %{
5968 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5969 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5970 %}
5971
5972 ins_pipe(pipe_slow);
5973 %}
5974
5975 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5976 %{
5977 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5978
5979 ins_cost(2 * VOLATILE_REF_COST);
5980
5981 format %{
5982 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5983 "# $res == 1 when success, #@weakCompareAndSwapI"
5984 %}
5985
5986 ins_encode %{
5987 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5988 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5989 %}
5990
5991 ins_pipe(pipe_slow);
5992 %}
5993
5994 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5995 %{
5996 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5997
5998 ins_cost(2 * VOLATILE_REF_COST);
5999
6000 format %{
6001 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6002 "# $res == 1 when success, #@weakCompareAndSwapL"
6003 %}
6004
6005 ins_encode %{
6006 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6007 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6008 %}
6009
6010 ins_pipe(pipe_slow);
6011 %}
6012
6013 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6014 %{
6015 predicate(n->as_LoadStore()->barrier_data() == 0);
6016
6017 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6018
6019 ins_cost(2 * VOLATILE_REF_COST);
6020
6021 format %{
6022 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6023 "# $res == 1 when success, #@weakCompareAndSwapN"
6024 %}
6025
6026 ins_encode %{
6027 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6028 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6029 %}
6030
6031 ins_pipe(pipe_slow);
6032 %}
6033
6034 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6035 %{
6036 predicate(n->as_LoadStore()->barrier_data() == 0);
6037
6038 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6039
6040 ins_cost(2 * VOLATILE_REF_COST);
6041
6042 format %{
6043 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6044 "# $res == 1 when success, #@weakCompareAndSwapP"
6045 %}
6046
6047 ins_encode %{
6048 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6049 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
6050 %}
6051
6052 ins_pipe(pipe_slow);
6053 %}
6054
6055 instruct weakCompareAndSwapBAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6056 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6057 %{
6058 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6059
6060 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6061
6062 ins_cost(2 * VOLATILE_REF_COST);
6063
6064 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6065
6066 format %{
6067 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6068 "# $res == 1 when success, #@weakCompareAndSwapBAcq_narrow"
6069 %}
6070
6071 ins_encode %{
6072 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6073 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6074 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6075 %}
6076
6077 ins_pipe(pipe_slow);
6078 %}
6079
6080 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6081 %{
6082 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6083
6084 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
6085
6086 ins_cost(2 * VOLATILE_REF_COST);
6087
6088 format %{
6089 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6090 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
6091 %}
6092
6093 ins_encode %{
6094 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
6095 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6096 %}
6097
6098 ins_pipe(pipe_slow);
6099 %}
6100
6101 instruct weakCompareAndSwapSAcq_narrow(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
6102 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
6103 %{
6104 predicate((!UseZabha || !UseZacas) && needs_acquiring_load_reserved(n));
6105
6106 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6107
6108 ins_cost(2 * VOLATILE_REF_COST);
6109
6110 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
6111
6112 format %{
6113 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6114 "# $res == 1 when success, #@weakCompareAndSwapSAcq_narrow"
6115 %}
6116
6117 ins_encode %{
6118 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6119 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
6120 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
6121 %}
6122
6123 ins_pipe(pipe_slow);
6124 %}
6125
6126 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6127 %{
6128 predicate((UseZabha && UseZacas) && needs_acquiring_load_reserved(n));
6129
6130 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
6131
6132 ins_cost(2 * VOLATILE_REF_COST);
6133
6134 format %{
6135 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6136 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
6137 %}
6138
6139 ins_encode %{
6140 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
6141 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6142 %}
6143
6144 ins_pipe(pipe_slow);
6145 %}
6146
6147 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
6148 %{
6149 predicate(needs_acquiring_load_reserved(n));
6150
6151 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
6152
6153 ins_cost(2 * VOLATILE_REF_COST);
6154
6155 format %{
6156 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6157 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
6158 %}
6159
6160 ins_encode %{
6161 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
6162 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6163 %}
6164
6165 ins_pipe(pipe_slow);
6166 %}
6167
6168 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
6169 %{
6170 predicate(needs_acquiring_load_reserved(n));
6171
6172 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
6173
6174 ins_cost(2 * VOLATILE_REF_COST);
6175
6176 format %{
6177 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6178 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
6179 %}
6180
6181 ins_encode %{
6182 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6183 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6184 %}
6185
6186 ins_pipe(pipe_slow);
6187 %}
6188
6189 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
6190 %{
6191 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6192
6193 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
6194
6195 ins_cost(2 * VOLATILE_REF_COST);
6196
6197 format %{
6198 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6199 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
6200 %}
6201
6202 ins_encode %{
6203 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
6204 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6205 %}
6206
6207 ins_pipe(pipe_slow);
6208 %}
6209
6210 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
6211 %{
6212 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6213
6214 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6215
6216 ins_cost(2 * VOLATILE_REF_COST);
6217
6218 format %{
6219 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6220 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6221 %}
6222
6223 ins_encode %{
6224 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6225 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6226 %}
6227
6228 ins_pipe(pipe_slow);
6229 %}
6230
6231 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6232 %{
6233 match(Set prev (GetAndSetI mem newv));
6234
6235 ins_cost(ALU_COST);
6236
6237 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6238
6239 ins_encode %{
6240 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6241 %}
6242
6243 ins_pipe(pipe_serial);
6244 %}
6245
6246 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6247 %{
6248 match(Set prev (GetAndSetL mem newv));
6249
6250 ins_cost(ALU_COST);
6251
6252 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6253
6254 ins_encode %{
6255 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6256 %}
6257
6258 ins_pipe(pipe_serial);
6259 %}
6260
6261 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6262 %{
6263 predicate(n->as_LoadStore()->barrier_data() == 0);
6264
6265 match(Set prev (GetAndSetN mem newv));
6266
6267 ins_cost(ALU_COST);
6268
6269 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6270
6271 ins_encode %{
6272 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6273 %}
6274
6275 ins_pipe(pipe_serial);
6276 %}
6277
6278 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6279 %{
6280 predicate(n->as_LoadStore()->barrier_data() == 0);
6281 match(Set prev (GetAndSetP mem newv));
6282
6283 ins_cost(ALU_COST);
6284
6285 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6286
6287 ins_encode %{
6288 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6289 %}
6290
6291 ins_pipe(pipe_serial);
6292 %}
6293
6294 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6295 %{
6296 predicate(needs_acquiring_load_reserved(n));
6297
6298 match(Set prev (GetAndSetI mem newv));
6299
6300 ins_cost(ALU_COST);
6301
6302 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6303
6304 ins_encode %{
6305 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6306 %}
6307
6308 ins_pipe(pipe_serial);
6309 %}
6310
6311 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6312 %{
6313 predicate(needs_acquiring_load_reserved(n));
6314
6315 match(Set prev (GetAndSetL mem newv));
6316
6317 ins_cost(ALU_COST);
6318
6319 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6320
6321 ins_encode %{
6322 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6323 %}
6324
6325 ins_pipe(pipe_serial);
6326 %}
6327
6328 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6329 %{
6330 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6331
6332 match(Set prev (GetAndSetN mem newv));
6333
6334 ins_cost(ALU_COST);
6335
6336 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6337
6338 ins_encode %{
6339 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6340 %}
6341
6342 ins_pipe(pipe_serial);
6343 %}
6344
6345 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6346 %{
6347 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6348
6349 match(Set prev (GetAndSetP mem newv));
6350
6351 ins_cost(ALU_COST);
6352
6353 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6354
6355 ins_encode %{
6356 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6357 %}
6358
6359 ins_pipe(pipe_serial);
6360 %}
6361
6362 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6363 %{
6364 match(Set newval (GetAndAddL mem incr));
6365
6366 ins_cost(ALU_COST);
6367
6368 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6369
6370 ins_encode %{
6371 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6372 %}
6373
6374 ins_pipe(pipe_serial);
6375 %}
6376
6377 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6378 %{
6379 predicate(n->as_LoadStore()->result_not_used());
6380
6381 match(Set dummy (GetAndAddL mem incr));
6382
6383 ins_cost(ALU_COST);
6384
6385 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6386
6387 ins_encode %{
6388 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6389 %}
6390
6391 ins_pipe(pipe_serial);
6392 %}
6393
6394 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6395 %{
6396 match(Set newval (GetAndAddL mem incr));
6397
6398 ins_cost(ALU_COST);
6399
6400 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6401
6402 ins_encode %{
6403 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6404 %}
6405
6406 ins_pipe(pipe_serial);
6407 %}
6408
6409 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6410 %{
6411 predicate(n->as_LoadStore()->result_not_used());
6412
6413 match(Set dummy (GetAndAddL mem incr));
6414
6415 ins_cost(ALU_COST);
6416
6417 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6418
6419 ins_encode %{
6420 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6421 %}
6422
6423 ins_pipe(pipe_serial);
6424 %}
6425
6426 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6427 %{
6428 match(Set newval (GetAndAddI mem incr));
6429
6430 ins_cost(ALU_COST);
6431
6432 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6433
6434 ins_encode %{
6435 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6436 %}
6437
6438 ins_pipe(pipe_serial);
6439 %}
6440
6441 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6442 %{
6443 predicate(n->as_LoadStore()->result_not_used());
6444
6445 match(Set dummy (GetAndAddI mem incr));
6446
6447 ins_cost(ALU_COST);
6448
6449 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6450
6451 ins_encode %{
6452 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6453 %}
6454
6455 ins_pipe(pipe_serial);
6456 %}
6457
6458 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6459 %{
6460 match(Set newval (GetAndAddI mem incr));
6461
6462 ins_cost(ALU_COST);
6463
6464 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6465
6466 ins_encode %{
6467 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6468 %}
6469
6470 ins_pipe(pipe_serial);
6471 %}
6472
6473 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6474 %{
6475 predicate(n->as_LoadStore()->result_not_used());
6476
6477 match(Set dummy (GetAndAddI mem incr));
6478
6479 ins_cost(ALU_COST);
6480
6481 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6482
6483 ins_encode %{
6484 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6485 %}
6486
6487 ins_pipe(pipe_serial);
6488 %}
6489
6490 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6491 %{
6492 predicate(needs_acquiring_load_reserved(n));
6493
6494 match(Set newval (GetAndAddL mem incr));
6495
6496 ins_cost(ALU_COST);
6497
6498 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6499
6500 ins_encode %{
6501 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6502 %}
6503
6504 ins_pipe(pipe_serial);
6505 %}
6506
6507 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6508 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6509
6510 match(Set dummy (GetAndAddL mem incr));
6511
6512 ins_cost(ALU_COST);
6513
6514 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6515
6516 ins_encode %{
6517 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6518 %}
6519
6520 ins_pipe(pipe_serial);
6521 %}
6522
6523 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6524 %{
6525 predicate(needs_acquiring_load_reserved(n));
6526
6527 match(Set newval (GetAndAddL mem incr));
6528
6529 ins_cost(ALU_COST);
6530
6531 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6532
6533 ins_encode %{
6534 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6535 %}
6536
6537 ins_pipe(pipe_serial);
6538 %}
6539
6540 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6541 %{
6542 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6543
6544 match(Set dummy (GetAndAddL mem incr));
6545
6546 ins_cost(ALU_COST);
6547
6548 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6549
6550 ins_encode %{
6551 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6552 %}
6553
6554 ins_pipe(pipe_serial);
6555 %}
6556
6557 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6558 %{
6559 predicate(needs_acquiring_load_reserved(n));
6560
6561 match(Set newval (GetAndAddI mem incr));
6562
6563 ins_cost(ALU_COST);
6564
6565 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6566
6567 ins_encode %{
6568 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6569 %}
6570
6571 ins_pipe(pipe_serial);
6572 %}
6573
6574 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6575 %{
6576 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6577
6578 match(Set dummy (GetAndAddI mem incr));
6579
6580 ins_cost(ALU_COST);
6581
6582 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6583
6584 ins_encode %{
6585 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6586 %}
6587
6588 ins_pipe(pipe_serial);
6589 %}
6590
6591 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6592 %{
6593 predicate(needs_acquiring_load_reserved(n));
6594
6595 match(Set newval (GetAndAddI mem incr));
6596
6597 ins_cost(ALU_COST);
6598
6599 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6600
6601 ins_encode %{
6602 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6603 %}
6604
6605 ins_pipe(pipe_serial);
6606 %}
6607
6608 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6609 %{
6610 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6611
6612 match(Set dummy (GetAndAddI mem incr));
6613
6614 ins_cost(ALU_COST);
6615
6616 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6617
6618 ins_encode %{
6619 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6620 %}
6621
6622 ins_pipe(pipe_serial);
6623 %}
6624
6625 // ============================================================================
6626 // Arithmetic Instructions
6627 //
6628
6629 // Integer Addition
6630
6631 // TODO
6632 // these currently employ operations which do not set CR and hence are
6633 // not flagged as killing CR but we would like to isolate the cases
6634 // where we want to set flags from those where we don't. need to work
6635 // out how to do that.
6636 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6637 match(Set dst (AddI src1 src2));
6638
6639 ins_cost(ALU_COST);
6640 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6641
6642 ins_encode %{
6643 __ addw(as_Register($dst$$reg),
6644 as_Register($src1$$reg),
6645 as_Register($src2$$reg));
6646 %}
6647
6648 ins_pipe(ialu_reg_reg);
6649 %}
6650
6651 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6652 match(Set dst (AddI src1 src2));
6653
6654 ins_cost(ALU_COST);
6655 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6656
6657 ins_encode %{
6658 __ addiw(as_Register($dst$$reg),
6659 as_Register($src1$$reg),
6660 $src2$$constant);
6661 %}
6662
6663 ins_pipe(ialu_reg_imm);
6664 %}
6665
6666 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6667 match(Set dst (AddI (ConvL2I src1) src2));
6668
6669 ins_cost(ALU_COST);
6670 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6671
6672 ins_encode %{
6673 __ addiw(as_Register($dst$$reg),
6674 as_Register($src1$$reg),
6675 $src2$$constant);
6676 %}
6677
6678 ins_pipe(ialu_reg_imm);
6679 %}
6680
6681 // Pointer Addition
6682 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6683 match(Set dst (AddP src1 src2));
6684
6685 ins_cost(ALU_COST);
6686 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6687
6688 ins_encode %{
6689 __ add(as_Register($dst$$reg),
6690 as_Register($src1$$reg),
6691 as_Register($src2$$reg));
6692 %}
6693
6694 ins_pipe(ialu_reg_reg);
6695 %}
6696
6697 // If we shift more than 32 bits, we need not convert I2L.
6698 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6699 match(Set dst (LShiftL (ConvI2L src) scale));
6700 ins_cost(ALU_COST);
6701 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6702
6703 ins_encode %{
6704 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6705 %}
6706
6707 ins_pipe(ialu_reg_shift);
6708 %}
6709
6710 // Pointer Immediate Addition
6711 // n.b. this needs to be more expensive than using an indirect memory
6712 // operand
6713 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6714 match(Set dst (AddP src1 src2));
6715 ins_cost(ALU_COST);
6716 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6717
6718 ins_encode %{
6719 __ addi(as_Register($dst$$reg),
6720 as_Register($src1$$reg),
6721 $src2$$constant);
6722 %}
6723
6724 ins_pipe(ialu_reg_imm);
6725 %}
6726
6727 // Long Addition
6728 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6729 match(Set dst (AddL src1 src2));
6730 ins_cost(ALU_COST);
6731 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6732
6733 ins_encode %{
6734 __ add(as_Register($dst$$reg),
6735 as_Register($src1$$reg),
6736 as_Register($src2$$reg));
6737 %}
6738
6739 ins_pipe(ialu_reg_reg);
6740 %}
6741
6742 // No constant pool entries requiredLong Immediate Addition.
6743 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6744 match(Set dst (AddL src1 src2));
6745 ins_cost(ALU_COST);
6746 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6747
6748 ins_encode %{
6749 // src2 is imm, so actually call the addi
6750 __ addi(as_Register($dst$$reg),
6751 as_Register($src1$$reg),
6752 $src2$$constant);
6753 %}
6754
6755 ins_pipe(ialu_reg_imm);
6756 %}
6757
6758 // Integer Subtraction
6759 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6760 match(Set dst (SubI src1 src2));
6761
6762 ins_cost(ALU_COST);
6763 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6764
6765 ins_encode %{
6766 __ subw(as_Register($dst$$reg),
6767 as_Register($src1$$reg),
6768 as_Register($src2$$reg));
6769 %}
6770
6771 ins_pipe(ialu_reg_reg);
6772 %}
6773
6774 // Immediate Subtraction
6775 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6776 match(Set dst (SubI src1 src2));
6777
6778 ins_cost(ALU_COST);
6779 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6780
6781 ins_encode %{
6782 // src2 is imm, so actually call the addiw
6783 __ subiw(as_Register($dst$$reg),
6784 as_Register($src1$$reg),
6785 $src2$$constant);
6786 %}
6787
6788 ins_pipe(ialu_reg_imm);
6789 %}
6790
6791 // Long Subtraction
6792 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6793 match(Set dst (SubL src1 src2));
6794 ins_cost(ALU_COST);
6795 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6796
6797 ins_encode %{
6798 __ sub(as_Register($dst$$reg),
6799 as_Register($src1$$reg),
6800 as_Register($src2$$reg));
6801 %}
6802
6803 ins_pipe(ialu_reg_reg);
6804 %}
6805
6806 // No constant pool entries requiredLong Immediate Subtraction.
6807 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6808 match(Set dst (SubL src1 src2));
6809 ins_cost(ALU_COST);
6810 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6811
6812 ins_encode %{
6813 // src2 is imm, so actually call the addi
6814 __ subi(as_Register($dst$$reg),
6815 as_Register($src1$$reg),
6816 $src2$$constant);
6817 %}
6818
6819 ins_pipe(ialu_reg_imm);
6820 %}
6821
6822 // Integer Negation (special case for sub)
6823
6824 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6825 match(Set dst (SubI zero src));
6826 ins_cost(ALU_COST);
6827 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6828
6829 ins_encode %{
6830 // actually call the subw
6831 __ negw(as_Register($dst$$reg),
6832 as_Register($src$$reg));
6833 %}
6834
6835 ins_pipe(ialu_reg);
6836 %}
6837
6838 // Long Negation
6839
6840 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6841 match(Set dst (SubL zero src));
6842 ins_cost(ALU_COST);
6843 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6844
6845 ins_encode %{
6846 // actually call the sub
6847 __ neg(as_Register($dst$$reg),
6848 as_Register($src$$reg));
6849 %}
6850
6851 ins_pipe(ialu_reg);
6852 %}
6853
6854 // Integer Multiply
6855
6856 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6857 match(Set dst (MulI src1 src2));
6858 ins_cost(IMUL_COST);
6859 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6860
6861 //this means 2 word multi, and no sign extend to 64 bits
6862 ins_encode %{
6863 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6864 __ mulw(as_Register($dst$$reg),
6865 as_Register($src1$$reg),
6866 as_Register($src2$$reg));
6867 %}
6868
6869 ins_pipe(imul_reg_reg);
6870 %}
6871
6872 // Long Multiply
6873
6874 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6875 match(Set dst (MulL src1 src2));
6876 ins_cost(IMUL_COST);
6877 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6878
6879 ins_encode %{
6880 __ mul(as_Register($dst$$reg),
6881 as_Register($src1$$reg),
6882 as_Register($src2$$reg));
6883 %}
6884
6885 ins_pipe(lmul_reg_reg);
6886 %}
6887
6888 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6889 %{
6890 match(Set dst (MulHiL src1 src2));
6891 ins_cost(IMUL_COST);
6892 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6893
6894 ins_encode %{
6895 __ mulh(as_Register($dst$$reg),
6896 as_Register($src1$$reg),
6897 as_Register($src2$$reg));
6898 %}
6899
6900 ins_pipe(lmul_reg_reg);
6901 %}
6902
6903 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6904 %{
6905 match(Set dst (UMulHiL src1 src2));
6906 ins_cost(IMUL_COST);
6907 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6908
6909 ins_encode %{
6910 __ mulhu(as_Register($dst$$reg),
6911 as_Register($src1$$reg),
6912 as_Register($src2$$reg));
6913 %}
6914
6915 ins_pipe(lmul_reg_reg);
6916 %}
6917
6918 // Integer Divide
6919
6920 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6921 match(Set dst (DivI src1 src2));
6922 ins_cost(IDIVSI_COST);
6923 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6924
6925 ins_encode %{
6926 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6927 %}
6928 ins_pipe(idiv_reg_reg);
6929 %}
6930
6931 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6932 match(Set dst (UDivI src1 src2));
6933 ins_cost(IDIVSI_COST);
6934 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6935
6936 ins_encode %{
6937 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6938 %}
6939 ins_pipe(idiv_reg_reg);
6940 %}
6941
6942 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6943 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6944 ins_cost(ALU_COST);
6945 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6946
6947 ins_encode %{
6948 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6949 %}
6950 ins_pipe(ialu_reg_shift);
6951 %}
6952
6953 // Long Divide
6954
6955 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6956 match(Set dst (DivL src1 src2));
6957 ins_cost(IDIVDI_COST);
6958 format %{ "div $dst, $src1, $src2\t#@divL" %}
6959
6960 ins_encode %{
6961 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6962 %}
6963 ins_pipe(ldiv_reg_reg);
6964 %}
6965
6966 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6967 match(Set dst (UDivL src1 src2));
6968 ins_cost(IDIVDI_COST);
6969
6970 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6971
6972 ins_encode %{
6973 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6974 %}
6975 ins_pipe(ldiv_reg_reg);
6976 %}
6977
6978 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6979 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6980 ins_cost(ALU_COST);
6981 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6982
6983 ins_encode %{
6984 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6985 %}
6986 ins_pipe(ialu_reg_shift);
6987 %}
6988
6989 // Integer Remainder
6990
6991 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6992 match(Set dst (ModI src1 src2));
6993 ins_cost(IDIVSI_COST);
6994 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6995
6996 ins_encode %{
6997 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6998 %}
6999 ins_pipe(ialu_reg_reg);
7000 %}
7001
7002 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7003 match(Set dst (UModI src1 src2));
7004 ins_cost(IDIVSI_COST);
7005 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
7006
7007 ins_encode %{
7008 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7009 %}
7010 ins_pipe(ialu_reg_reg);
7011 %}
7012
7013 // Long Remainder
7014
7015 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7016 match(Set dst (ModL src1 src2));
7017 ins_cost(IDIVDI_COST);
7018 format %{ "rem $dst, $src1, $src2\t#@modL" %}
7019
7020 ins_encode %{
7021 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7022 %}
7023 ins_pipe(ialu_reg_reg);
7024 %}
7025
7026 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7027 match(Set dst (UModL src1 src2));
7028 ins_cost(IDIVDI_COST);
7029 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
7030
7031 ins_encode %{
7032 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
7033 %}
7034 ins_pipe(ialu_reg_reg);
7035 %}
7036
7037 // Integer Shifts
7038
7039 // Shift Left Register
7040 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7041 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7042 match(Set dst (LShiftI src1 src2));
7043 ins_cost(ALU_COST);
7044 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
7045
7046 ins_encode %{
7047 __ sllw(as_Register($dst$$reg),
7048 as_Register($src1$$reg),
7049 as_Register($src2$$reg));
7050 %}
7051
7052 ins_pipe(ialu_reg_reg_vshift);
7053 %}
7054
7055 // Shift Left Immediate
7056 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7057 match(Set dst (LShiftI src1 src2));
7058 ins_cost(ALU_COST);
7059 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
7060
7061 ins_encode %{
7062 // the shift amount is encoded in the lower
7063 // 5 bits of the I-immediate field for RV32I
7064 __ slliw(as_Register($dst$$reg),
7065 as_Register($src1$$reg),
7066 (unsigned) $src2$$constant & 0x1f);
7067 %}
7068
7069 ins_pipe(ialu_reg_shift);
7070 %}
7071
7072 // Shift Right Logical Register
7073 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7074 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7075 match(Set dst (URShiftI src1 src2));
7076 ins_cost(ALU_COST);
7077 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
7078
7079 ins_encode %{
7080 __ srlw(as_Register($dst$$reg),
7081 as_Register($src1$$reg),
7082 as_Register($src2$$reg));
7083 %}
7084
7085 ins_pipe(ialu_reg_reg_vshift);
7086 %}
7087
7088 // Shift Right Logical Immediate
7089 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7090 match(Set dst (URShiftI src1 src2));
7091 ins_cost(ALU_COST);
7092 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
7093
7094 ins_encode %{
7095 // the shift amount is encoded in the lower
7096 // 6 bits of the I-immediate field for RV64I
7097 __ srliw(as_Register($dst$$reg),
7098 as_Register($src1$$reg),
7099 (unsigned) $src2$$constant & 0x1f);
7100 %}
7101
7102 ins_pipe(ialu_reg_shift);
7103 %}
7104
7105 // Shift Right Arithmetic Register
7106 // Only the low 5 bits of src2 are considered for the shift amount, all other bits are ignored.
7107 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
7108 match(Set dst (RShiftI src1 src2));
7109 ins_cost(ALU_COST);
7110 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
7111
7112 ins_encode %{
7113 // riscv will sign-ext dst high 32 bits
7114 __ sraw(as_Register($dst$$reg),
7115 as_Register($src1$$reg),
7116 as_Register($src2$$reg));
7117 %}
7118
7119 ins_pipe(ialu_reg_reg_vshift);
7120 %}
7121
7122 // Shift Right Arithmetic Immediate
7123 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
7124 match(Set dst (RShiftI src1 src2));
7125 ins_cost(ALU_COST);
7126 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
7127
7128 ins_encode %{
7129 // riscv will sign-ext dst high 32 bits
7130 __ sraiw(as_Register($dst$$reg),
7131 as_Register($src1$$reg),
7132 (unsigned) $src2$$constant & 0x1f);
7133 %}
7134
7135 ins_pipe(ialu_reg_shift);
7136 %}
7137
7138 // Long Shifts
7139
7140 // Shift Left Register
7141 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7142 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7143 match(Set dst (LShiftL src1 src2));
7144
7145 ins_cost(ALU_COST);
7146 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
7147
7148 ins_encode %{
7149 __ sll(as_Register($dst$$reg),
7150 as_Register($src1$$reg),
7151 as_Register($src2$$reg));
7152 %}
7153
7154 ins_pipe(ialu_reg_reg_vshift);
7155 %}
7156
7157 // Shift Left Immediate
7158 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7159 match(Set dst (LShiftL src1 src2));
7160
7161 ins_cost(ALU_COST);
7162 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
7163
7164 ins_encode %{
7165 // the shift amount is encoded in the lower
7166 // 6 bits of the I-immediate field for RV64I
7167 __ slli(as_Register($dst$$reg),
7168 as_Register($src1$$reg),
7169 (unsigned) $src2$$constant & 0x3f);
7170 %}
7171
7172 ins_pipe(ialu_reg_shift);
7173 %}
7174
7175 // Shift Right Logical Register
7176 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7177 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7178 match(Set dst (URShiftL src1 src2));
7179
7180 ins_cost(ALU_COST);
7181 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
7182
7183 ins_encode %{
7184 __ srl(as_Register($dst$$reg),
7185 as_Register($src1$$reg),
7186 as_Register($src2$$reg));
7187 %}
7188
7189 ins_pipe(ialu_reg_reg_vshift);
7190 %}
7191
7192 // Shift Right Logical Immediate
7193 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7194 match(Set dst (URShiftL src1 src2));
7195
7196 ins_cost(ALU_COST);
7197 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
7198
7199 ins_encode %{
7200 // the shift amount is encoded in the lower
7201 // 6 bits of the I-immediate field for RV64I
7202 __ srli(as_Register($dst$$reg),
7203 as_Register($src1$$reg),
7204 (unsigned) $src2$$constant & 0x3f);
7205 %}
7206
7207 ins_pipe(ialu_reg_shift);
7208 %}
7209
7210 // A special-case pattern for card table stores.
7211 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
7212 match(Set dst (URShiftL (CastP2X src1) src2));
7213
7214 ins_cost(ALU_COST);
7215 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7216
7217 ins_encode %{
7218 // the shift amount is encoded in the lower
7219 // 6 bits of the I-immediate field for RV64I
7220 __ srli(as_Register($dst$$reg),
7221 as_Register($src1$$reg),
7222 (unsigned) $src2$$constant & 0x3f);
7223 %}
7224
7225 ins_pipe(ialu_reg_shift);
7226 %}
7227
7228 // Shift Right Arithmetic Register
7229 // Only the low 6 bits of src2 are considered for the shift amount, all other bits are ignored.
7230 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7231 match(Set dst (RShiftL src1 src2));
7232
7233 ins_cost(ALU_COST);
7234 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7235
7236 ins_encode %{
7237 __ sra(as_Register($dst$$reg),
7238 as_Register($src1$$reg),
7239 as_Register($src2$$reg));
7240 %}
7241
7242 ins_pipe(ialu_reg_reg_vshift);
7243 %}
7244
7245 // Shift Right Arithmetic Immediate
7246 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7247 match(Set dst (RShiftL src1 src2));
7248
7249 ins_cost(ALU_COST);
7250 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7251
7252 ins_encode %{
7253 // the shift amount is encoded in the lower
7254 // 6 bits of the I-immediate field for RV64I
7255 __ srai(as_Register($dst$$reg),
7256 as_Register($src1$$reg),
7257 (unsigned) $src2$$constant & 0x3f);
7258 %}
7259
7260 ins_pipe(ialu_reg_shift);
7261 %}
7262
7263 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7264 match(Set dst (XorI src1 m1));
7265 ins_cost(ALU_COST);
7266 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7267
7268 ins_encode %{
7269 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7270 %}
7271
7272 ins_pipe(ialu_reg_imm);
7273 %}
7274
7275 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7276 match(Set dst (XorL src1 m1));
7277 ins_cost(ALU_COST);
7278 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7279
7280 ins_encode %{
7281 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7282 %}
7283
7284 ins_pipe(ialu_reg_imm);
7285 %}
7286
7287
7288 // ============================================================================
7289 // Floating Point Arithmetic Instructions
7290
7291 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7292 match(Set dst (AddF src1 src2));
7293
7294 ins_cost(DEFAULT_COST * 5);
7295 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7296
7297 ins_encode %{
7298 __ fadd_s(as_FloatRegister($dst$$reg),
7299 as_FloatRegister($src1$$reg),
7300 as_FloatRegister($src2$$reg));
7301 %}
7302
7303 ins_pipe(fp_dop_reg_reg_s);
7304 %}
7305
7306 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7307 match(Set dst (AddD src1 src2));
7308
7309 ins_cost(DEFAULT_COST * 5);
7310 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7311
7312 ins_encode %{
7313 __ fadd_d(as_FloatRegister($dst$$reg),
7314 as_FloatRegister($src1$$reg),
7315 as_FloatRegister($src2$$reg));
7316 %}
7317
7318 ins_pipe(fp_dop_reg_reg_d);
7319 %}
7320
7321 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7322 match(Set dst (SubF src1 src2));
7323
7324 ins_cost(DEFAULT_COST * 5);
7325 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7326
7327 ins_encode %{
7328 __ fsub_s(as_FloatRegister($dst$$reg),
7329 as_FloatRegister($src1$$reg),
7330 as_FloatRegister($src2$$reg));
7331 %}
7332
7333 ins_pipe(fp_dop_reg_reg_s);
7334 %}
7335
7336 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7337 match(Set dst (SubD src1 src2));
7338
7339 ins_cost(DEFAULT_COST * 5);
7340 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7341
7342 ins_encode %{
7343 __ fsub_d(as_FloatRegister($dst$$reg),
7344 as_FloatRegister($src1$$reg),
7345 as_FloatRegister($src2$$reg));
7346 %}
7347
7348 ins_pipe(fp_dop_reg_reg_d);
7349 %}
7350
7351 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7352 match(Set dst (MulF src1 src2));
7353
7354 ins_cost(FMUL_SINGLE_COST);
7355 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7356
7357 ins_encode %{
7358 __ fmul_s(as_FloatRegister($dst$$reg),
7359 as_FloatRegister($src1$$reg),
7360 as_FloatRegister($src2$$reg));
7361 %}
7362
7363 ins_pipe(fp_dop_reg_reg_s);
7364 %}
7365
7366 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7367 match(Set dst (MulD src1 src2));
7368
7369 ins_cost(FMUL_DOUBLE_COST);
7370 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7371
7372 ins_encode %{
7373 __ fmul_d(as_FloatRegister($dst$$reg),
7374 as_FloatRegister($src1$$reg),
7375 as_FloatRegister($src2$$reg));
7376 %}
7377
7378 ins_pipe(fp_dop_reg_reg_d);
7379 %}
7380
7381 // src1 * src2 + src3
7382 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7383 match(Set dst (FmaF src3 (Binary src1 src2)));
7384
7385 ins_cost(FMUL_SINGLE_COST);
7386 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7387
7388 ins_encode %{
7389 assert(UseFMA, "Needs FMA instructions support.");
7390 __ fmadd_s(as_FloatRegister($dst$$reg),
7391 as_FloatRegister($src1$$reg),
7392 as_FloatRegister($src2$$reg),
7393 as_FloatRegister($src3$$reg));
7394 %}
7395
7396 ins_pipe(pipe_class_default);
7397 %}
7398
7399 // src1 * src2 + src3
7400 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7401 match(Set dst (FmaD src3 (Binary src1 src2)));
7402
7403 ins_cost(FMUL_DOUBLE_COST);
7404 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7405
7406 ins_encode %{
7407 assert(UseFMA, "Needs FMA instructions support.");
7408 __ fmadd_d(as_FloatRegister($dst$$reg),
7409 as_FloatRegister($src1$$reg),
7410 as_FloatRegister($src2$$reg),
7411 as_FloatRegister($src3$$reg));
7412 %}
7413
7414 ins_pipe(pipe_class_default);
7415 %}
7416
7417 // src1 * src2 - src3
7418 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7419 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7420
7421 ins_cost(FMUL_SINGLE_COST);
7422 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7423
7424 ins_encode %{
7425 assert(UseFMA, "Needs FMA instructions support.");
7426 __ fmsub_s(as_FloatRegister($dst$$reg),
7427 as_FloatRegister($src1$$reg),
7428 as_FloatRegister($src2$$reg),
7429 as_FloatRegister($src3$$reg));
7430 %}
7431
7432 ins_pipe(pipe_class_default);
7433 %}
7434
7435 // src1 * src2 - src3
7436 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7437 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7438
7439 ins_cost(FMUL_DOUBLE_COST);
7440 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7441
7442 ins_encode %{
7443 assert(UseFMA, "Needs FMA instructions support.");
7444 __ fmsub_d(as_FloatRegister($dst$$reg),
7445 as_FloatRegister($src1$$reg),
7446 as_FloatRegister($src2$$reg),
7447 as_FloatRegister($src3$$reg));
7448 %}
7449
7450 ins_pipe(pipe_class_default);
7451 %}
7452
7453 // src1 * (-src2) + src3
7454 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7455 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7456 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7457
7458 ins_cost(FMUL_SINGLE_COST);
7459 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7460
7461 ins_encode %{
7462 assert(UseFMA, "Needs FMA instructions support.");
7463 __ fnmsub_s(as_FloatRegister($dst$$reg),
7464 as_FloatRegister($src1$$reg),
7465 as_FloatRegister($src2$$reg),
7466 as_FloatRegister($src3$$reg));
7467 %}
7468
7469 ins_pipe(pipe_class_default);
7470 %}
7471
7472 // src1 * (-src2) + src3
7473 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7474 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7475 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7476
7477 ins_cost(FMUL_DOUBLE_COST);
7478 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7479
7480 ins_encode %{
7481 assert(UseFMA, "Needs FMA instructions support.");
7482 __ fnmsub_d(as_FloatRegister($dst$$reg),
7483 as_FloatRegister($src1$$reg),
7484 as_FloatRegister($src2$$reg),
7485 as_FloatRegister($src3$$reg));
7486 %}
7487
7488 ins_pipe(pipe_class_default);
7489 %}
7490
7491 // src1 * (-src2) - src3
7492 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7493 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7494 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7495
7496 ins_cost(FMUL_SINGLE_COST);
7497 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7498
7499 ins_encode %{
7500 assert(UseFMA, "Needs FMA instructions support.");
7501 __ fnmadd_s(as_FloatRegister($dst$$reg),
7502 as_FloatRegister($src1$$reg),
7503 as_FloatRegister($src2$$reg),
7504 as_FloatRegister($src3$$reg));
7505 %}
7506
7507 ins_pipe(pipe_class_default);
7508 %}
7509
7510 // src1 * (-src2) - src3
7511 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7512 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7513 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7514
7515 ins_cost(FMUL_DOUBLE_COST);
7516 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7517
7518 ins_encode %{
7519 assert(UseFMA, "Needs FMA instructions support.");
7520 __ fnmadd_d(as_FloatRegister($dst$$reg),
7521 as_FloatRegister($src1$$reg),
7522 as_FloatRegister($src2$$reg),
7523 as_FloatRegister($src3$$reg));
7524 %}
7525
7526 ins_pipe(pipe_class_default);
7527 %}
7528
7529 // Math.max(FF)F
7530 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7531 predicate(!UseZfa);
7532 match(Set dst (MaxF src1 src2));
7533 effect(KILL cr);
7534
7535 format %{ "maxF $dst, $src1, $src2" %}
7536
7537 ins_encode %{
7538 __ minmax_fp(as_FloatRegister($dst$$reg),
7539 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7540 __ FLOAT_TYPE::single_precision, false /* is_min */);
7541 %}
7542
7543 ins_pipe(pipe_class_default);
7544 %}
7545
7546 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7547 predicate(UseZfa);
7548 match(Set dst (MaxF src1 src2));
7549
7550 format %{ "maxF $dst, $src1, $src2" %}
7551
7552 ins_encode %{
7553 __ fmaxm_s(as_FloatRegister($dst$$reg),
7554 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7555 %}
7556
7557 ins_pipe(pipe_class_default);
7558 %}
7559
7560 // Math.min(FF)F
7561 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7562 predicate(!UseZfa);
7563 match(Set dst (MinF src1 src2));
7564 effect(KILL cr);
7565
7566 format %{ "minF $dst, $src1, $src2" %}
7567
7568 ins_encode %{
7569 __ minmax_fp(as_FloatRegister($dst$$reg),
7570 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7571 __ FLOAT_TYPE::single_precision, true /* is_min */);
7572 %}
7573
7574 ins_pipe(pipe_class_default);
7575 %}
7576
7577 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7578 predicate(UseZfa);
7579 match(Set dst (MinF src1 src2));
7580
7581 format %{ "minF $dst, $src1, $src2" %}
7582
7583 ins_encode %{
7584 __ fminm_s(as_FloatRegister($dst$$reg),
7585 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7586 %}
7587
7588 ins_pipe(pipe_class_default);
7589 %}
7590
7591 // Math.max(DD)D
7592 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7593 predicate(!UseZfa);
7594 match(Set dst (MaxD src1 src2));
7595 effect(KILL cr);
7596
7597 format %{ "maxD $dst, $src1, $src2" %}
7598
7599 ins_encode %{
7600 __ minmax_fp(as_FloatRegister($dst$$reg),
7601 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7602 __ FLOAT_TYPE::double_precision, false /* is_min */);
7603 %}
7604
7605 ins_pipe(pipe_class_default);
7606 %}
7607
7608 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7609 predicate(UseZfa);
7610 match(Set dst (MaxD src1 src2));
7611
7612 format %{ "maxD $dst, $src1, $src2" %}
7613
7614 ins_encode %{
7615 __ fmaxm_d(as_FloatRegister($dst$$reg),
7616 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7617 %}
7618
7619 ins_pipe(pipe_class_default);
7620 %}
7621
7622 // Math.min(DD)D
7623 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7624 predicate(!UseZfa);
7625 match(Set dst (MinD src1 src2));
7626 effect(KILL cr);
7627
7628 format %{ "minD $dst, $src1, $src2" %}
7629
7630 ins_encode %{
7631 __ minmax_fp(as_FloatRegister($dst$$reg),
7632 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7633 __ FLOAT_TYPE::double_precision, true /* is_min */);
7634 %}
7635
7636 ins_pipe(pipe_class_default);
7637 %}
7638
7639 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7640 predicate(UseZfa);
7641 match(Set dst (MinD src1 src2));
7642
7643 format %{ "minD $dst, $src1, $src2" %}
7644
7645 ins_encode %{
7646 __ fminm_d(as_FloatRegister($dst$$reg),
7647 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7648 %}
7649
7650 ins_pipe(pipe_class_default);
7651 %}
7652
7653 // Float.isInfinite
7654 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7655 %{
7656 match(Set dst (IsInfiniteF src));
7657
7658 format %{ "isInfinite $dst, $src" %}
7659 ins_encode %{
7660 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7661 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7662 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7663 %}
7664
7665 ins_pipe(pipe_class_default);
7666 %}
7667
7668 // Double.isInfinite
7669 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7670 %{
7671 match(Set dst (IsInfiniteD src));
7672
7673 format %{ "isInfinite $dst, $src" %}
7674 ins_encode %{
7675 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7676 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7677 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7678 %}
7679
7680 ins_pipe(pipe_class_default);
7681 %}
7682
7683 // Float.isFinite
7684 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7685 %{
7686 match(Set dst (IsFiniteF src));
7687
7688 format %{ "isFinite $dst, $src" %}
7689 ins_encode %{
7690 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7691 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7692 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7693 %}
7694
7695 ins_pipe(pipe_class_default);
7696 %}
7697
7698 // Double.isFinite
7699 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7700 %{
7701 match(Set dst (IsFiniteD src));
7702
7703 format %{ "isFinite $dst, $src" %}
7704 ins_encode %{
7705 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7706 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7707 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7708 %}
7709
7710 ins_pipe(pipe_class_default);
7711 %}
7712
7713 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7714 match(Set dst (DivF src1 src2));
7715
7716 ins_cost(FDIV_COST);
7717 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7718
7719 ins_encode %{
7720 __ fdiv_s(as_FloatRegister($dst$$reg),
7721 as_FloatRegister($src1$$reg),
7722 as_FloatRegister($src2$$reg));
7723 %}
7724
7725 ins_pipe(fp_div_s);
7726 %}
7727
7728 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7729 match(Set dst (DivD src1 src2));
7730
7731 ins_cost(FDIV_COST);
7732 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7733
7734 ins_encode %{
7735 __ fdiv_d(as_FloatRegister($dst$$reg),
7736 as_FloatRegister($src1$$reg),
7737 as_FloatRegister($src2$$reg));
7738 %}
7739
7740 ins_pipe(fp_div_d);
7741 %}
7742
7743 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7744 match(Set dst (NegF src));
7745
7746 ins_cost(XFER_COST);
7747 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7748
7749 ins_encode %{
7750 __ fneg_s(as_FloatRegister($dst$$reg),
7751 as_FloatRegister($src$$reg));
7752 %}
7753
7754 ins_pipe(fp_uop_s);
7755 %}
7756
7757 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7758 match(Set dst (NegD src));
7759
7760 ins_cost(XFER_COST);
7761 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7762
7763 ins_encode %{
7764 __ fneg_d(as_FloatRegister($dst$$reg),
7765 as_FloatRegister($src$$reg));
7766 %}
7767
7768 ins_pipe(fp_uop_d);
7769 %}
7770
7771 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7772 match(Set dst (AbsI src));
7773
7774 ins_cost(ALU_COST * 3);
7775 format %{
7776 "sraiw t0, $src, 0x1f\n\t"
7777 "addw $dst, $src, t0\n\t"
7778 "xorr $dst, $dst, t0\t#@absI_reg"
7779 %}
7780
7781 ins_encode %{
7782 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7783 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7784 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7785 %}
7786
7787 ins_pipe(pipe_class_default);
7788 %}
7789
7790 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7791 match(Set dst (AbsL src));
7792
7793 ins_cost(ALU_COST * 3);
7794 format %{
7795 "srai t0, $src, 0x3f\n\t"
7796 "add $dst, $src, t0\n\t"
7797 "xorr $dst, $dst, t0\t#@absL_reg"
7798 %}
7799
7800 ins_encode %{
7801 __ srai(t0, as_Register($src$$reg), 0x3f);
7802 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7803 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7804 %}
7805
7806 ins_pipe(pipe_class_default);
7807 %}
7808
7809 instruct absF_reg(fRegF dst, fRegF src) %{
7810 match(Set dst (AbsF src));
7811
7812 ins_cost(XFER_COST);
7813 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7814 ins_encode %{
7815 __ fabs_s(as_FloatRegister($dst$$reg),
7816 as_FloatRegister($src$$reg));
7817 %}
7818
7819 ins_pipe(fp_uop_s);
7820 %}
7821
7822 instruct absD_reg(fRegD dst, fRegD src) %{
7823 match(Set dst (AbsD src));
7824
7825 ins_cost(XFER_COST);
7826 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7827 ins_encode %{
7828 __ fabs_d(as_FloatRegister($dst$$reg),
7829 as_FloatRegister($src$$reg));
7830 %}
7831
7832 ins_pipe(fp_uop_d);
7833 %}
7834
7835 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7836 match(Set dst (SqrtF src));
7837
7838 ins_cost(FSQRT_COST);
7839 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7840 ins_encode %{
7841 __ fsqrt_s(as_FloatRegister($dst$$reg),
7842 as_FloatRegister($src$$reg));
7843 %}
7844
7845 ins_pipe(fp_sqrt_s);
7846 %}
7847
7848 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7849 match(Set dst (SqrtD src));
7850
7851 ins_cost(FSQRT_COST);
7852 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7853 ins_encode %{
7854 __ fsqrt_d(as_FloatRegister($dst$$reg),
7855 as_FloatRegister($src$$reg));
7856 %}
7857
7858 ins_pipe(fp_sqrt_d);
7859 %}
7860
7861 // Round Instruction
7862 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7863 match(Set dst (RoundDoubleMode src rmode));
7864 ins_cost(2 * XFER_COST + BRANCH_COST);
7865 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7866
7867 format %{ "RoundDoubleMode $src, $rmode" %}
7868 ins_encode %{
7869 __ round_double_mode(as_FloatRegister($dst$$reg),
7870 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7871 %}
7872 ins_pipe(pipe_class_default);
7873 %}
7874
7875 // Copysign and signum intrinsics
7876
7877 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7878 match(Set dst (CopySignD src1 (Binary src2 zero)));
7879 format %{ "CopySignD $dst $src1 $src2" %}
7880 ins_encode %{
7881 FloatRegister dst = as_FloatRegister($dst$$reg),
7882 src1 = as_FloatRegister($src1$$reg),
7883 src2 = as_FloatRegister($src2$$reg);
7884 __ fsgnj_d(dst, src1, src2);
7885 %}
7886 ins_pipe(fp_dop_reg_reg_d);
7887 %}
7888
7889 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7890 match(Set dst (CopySignF src1 src2));
7891 format %{ "CopySignF $dst $src1 $src2" %}
7892 ins_encode %{
7893 FloatRegister dst = as_FloatRegister($dst$$reg),
7894 src1 = as_FloatRegister($src1$$reg),
7895 src2 = as_FloatRegister($src2$$reg);
7896 __ fsgnj_s(dst, src1, src2);
7897 %}
7898 ins_pipe(fp_dop_reg_reg_s);
7899 %}
7900
7901 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7902 match(Set dst (SignumD dst (Binary zero one)));
7903 format %{ "signumD $dst, $dst" %}
7904 ins_encode %{
7905 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7906 %}
7907 ins_pipe(pipe_class_default);
7908 %}
7909
7910 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7911 match(Set dst (SignumF dst (Binary zero one)));
7912 format %{ "signumF $dst, $dst" %}
7913 ins_encode %{
7914 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7915 %}
7916 ins_pipe(pipe_class_default);
7917 %}
7918
7919 // Arithmetic Instructions End
7920
7921 // ============================================================================
7922 // Logical Instructions
7923
7924 // Register And
7925 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7926 match(Set dst (AndI src1 src2));
7927
7928 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7929
7930 ins_cost(ALU_COST);
7931 ins_encode %{
7932 __ andr(as_Register($dst$$reg),
7933 as_Register($src1$$reg),
7934 as_Register($src2$$reg));
7935 %}
7936
7937 ins_pipe(ialu_reg_reg);
7938 %}
7939
7940 // Immediate And
7941 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7942 match(Set dst (AndI src1 src2));
7943
7944 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7945
7946 ins_cost(ALU_COST);
7947 ins_encode %{
7948 __ andi(as_Register($dst$$reg),
7949 as_Register($src1$$reg),
7950 (int32_t)($src2$$constant));
7951 %}
7952
7953 ins_pipe(ialu_reg_imm);
7954 %}
7955
7956 // Register Or
7957 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7958 match(Set dst (OrI src1 src2));
7959
7960 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7961
7962 ins_cost(ALU_COST);
7963 ins_encode %{
7964 __ orr(as_Register($dst$$reg),
7965 as_Register($src1$$reg),
7966 as_Register($src2$$reg));
7967 %}
7968
7969 ins_pipe(ialu_reg_reg);
7970 %}
7971
7972 // Immediate Or
7973 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7974 match(Set dst (OrI src1 src2));
7975
7976 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7977
7978 ins_cost(ALU_COST);
7979 ins_encode %{
7980 __ ori(as_Register($dst$$reg),
7981 as_Register($src1$$reg),
7982 (int32_t)($src2$$constant));
7983 %}
7984
7985 ins_pipe(ialu_reg_imm);
7986 %}
7987
7988 // Register Xor
7989 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7990 match(Set dst (XorI src1 src2));
7991
7992 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7993
7994 ins_cost(ALU_COST);
7995 ins_encode %{
7996 __ xorr(as_Register($dst$$reg),
7997 as_Register($src1$$reg),
7998 as_Register($src2$$reg));
7999 %}
8000
8001 ins_pipe(ialu_reg_reg);
8002 %}
8003
8004 // Immediate Xor
8005 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
8006 match(Set dst (XorI src1 src2));
8007
8008 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
8009
8010 ins_cost(ALU_COST);
8011 ins_encode %{
8012 __ xori(as_Register($dst$$reg),
8013 as_Register($src1$$reg),
8014 (int32_t)($src2$$constant));
8015 %}
8016
8017 ins_pipe(ialu_reg_imm);
8018 %}
8019
8020 // Register And Long
8021 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8022 match(Set dst (AndL src1 src2));
8023
8024 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
8025
8026 ins_cost(ALU_COST);
8027 ins_encode %{
8028 __ andr(as_Register($dst$$reg),
8029 as_Register($src1$$reg),
8030 as_Register($src2$$reg));
8031 %}
8032
8033 ins_pipe(ialu_reg_reg);
8034 %}
8035
8036 // Immediate And Long
8037 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8038 match(Set dst (AndL src1 src2));
8039
8040 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
8041
8042 ins_cost(ALU_COST);
8043 ins_encode %{
8044 __ andi(as_Register($dst$$reg),
8045 as_Register($src1$$reg),
8046 (int32_t)($src2$$constant));
8047 %}
8048
8049 ins_pipe(ialu_reg_imm);
8050 %}
8051
8052 // Register Or Long
8053 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8054 match(Set dst (OrL src1 src2));
8055
8056 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
8057
8058 ins_cost(ALU_COST);
8059 ins_encode %{
8060 __ orr(as_Register($dst$$reg),
8061 as_Register($src1$$reg),
8062 as_Register($src2$$reg));
8063 %}
8064
8065 ins_pipe(ialu_reg_reg);
8066 %}
8067
8068 // Immediate Or Long
8069 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8070 match(Set dst (OrL src1 src2));
8071
8072 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
8073
8074 ins_cost(ALU_COST);
8075 ins_encode %{
8076 __ ori(as_Register($dst$$reg),
8077 as_Register($src1$$reg),
8078 (int32_t)($src2$$constant));
8079 %}
8080
8081 ins_pipe(ialu_reg_imm);
8082 %}
8083
8084 // Register Xor Long
8085 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
8086 match(Set dst (XorL src1 src2));
8087
8088 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
8089
8090 ins_cost(ALU_COST);
8091 ins_encode %{
8092 __ xorr(as_Register($dst$$reg),
8093 as_Register($src1$$reg),
8094 as_Register($src2$$reg));
8095 %}
8096
8097 ins_pipe(ialu_reg_reg);
8098 %}
8099
8100 // Immediate Xor Long
8101 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
8102 match(Set dst (XorL src1 src2));
8103
8104 ins_cost(ALU_COST);
8105 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
8106
8107 ins_encode %{
8108 __ xori(as_Register($dst$$reg),
8109 as_Register($src1$$reg),
8110 (int32_t)($src2$$constant));
8111 %}
8112
8113 ins_pipe(ialu_reg_imm);
8114 %}
8115
8116 // ============================================================================
8117 // MemBar Instruction
8118
8119 // RVTSO
8120
8121 instruct unnecessary_membar_rvtso() %{
8122 predicate(UseZtso);
8123 match(LoadFence);
8124 match(StoreFence);
8125 match(StoreStoreFence);
8126 match(MemBarAcquire);
8127 match(MemBarRelease);
8128 match(MemBarStoreStore);
8129 match(MemBarAcquireLock);
8130 match(MemBarReleaseLock);
8131
8132 ins_cost(0);
8133
8134 size(0);
8135
8136 format %{ "#@unnecessary_membar_rvtso elided/tso (empty encoding)" %}
8137 ins_encode %{
8138 __ block_comment("unnecessary_membar_rvtso");
8139 %}
8140 ins_pipe(real_empty);
8141 %}
8142
8143 instruct membar_storeload_rvtso() %{
8144 predicate(UseZtso);
8145 match(MemBarStoreLoad);
8146 ins_cost(VOLATILE_REF_COST);
8147
8148 format %{ "#@membar_storeload_rvtso\n\t"
8149 "fence w, r"%}
8150
8151 ins_encode %{
8152 __ block_comment("membar_storeload_rvtso");
8153 __ membar(MacroAssembler::StoreLoad);
8154 %}
8155
8156 ins_pipe(pipe_slow);
8157 %}
8158
8159 instruct membar_volatile_rvtso() %{
8160 predicate(UseZtso);
8161 match(MemBarVolatile);
8162 ins_cost(VOLATILE_REF_COST);
8163
8164 format %{ "#@membar_volatile_rvtso\n\t"
8165 "fence w, r"%}
8166
8167 ins_encode %{
8168 __ block_comment("membar_volatile_rvtso");
8169 __ membar(MacroAssembler::StoreLoad);
8170 %}
8171
8172 ins_pipe(pipe_slow);
8173 %}
8174
8175 instruct unnecessary_membar_volatile_rvtso() %{
8176 predicate(UseZtso && Matcher::post_store_load_barrier(n));
8177 match(MemBarVolatile);
8178 ins_cost(0);
8179
8180 size(0);
8181
8182 format %{ "#@unnecessary_membar_volatile_rvtso (unnecessary so empty encoding)" %}
8183 ins_encode %{
8184 __ block_comment("unnecessary_membar_volatile_rvtso");
8185 %}
8186 ins_pipe(real_empty);
8187 %}
8188
8189 instruct membar_full_rvtso() %{
8190 predicate(UseZtso);
8191 match(MemBarFull);
8192 ins_cost(VOLATILE_REF_COST);
8193
8194 format %{ "#@membar_full_rvtso\n\t"
8195 "fence rw, rw" %}
8196
8197 ins_encode %{
8198 __ block_comment("membar_full_rvtso");
8199 __ membar(MacroAssembler::AnyAny);
8200 %}
8201
8202 ins_pipe(pipe_slow);
8203 %}
8204
8205 // RVWMO
8206
8207 instruct membar_aqcuire_rvwmo() %{
8208 predicate(!UseZtso);
8209 match(LoadFence);
8210 match(MemBarAcquire);
8211 ins_cost(VOLATILE_REF_COST);
8212
8213 format %{ "#@membar_aqcuire_rvwmo\n\t"
8214 "fence r, rw" %}
8215
8216 ins_encode %{
8217 __ block_comment("membar_aqcuire_rvwmo");
8218 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
8219 %}
8220 ins_pipe(pipe_serial);
8221 %}
8222
8223 instruct membar_release_rvwmo() %{
8224 predicate(!UseZtso);
8225 match(StoreFence);
8226 match(MemBarRelease);
8227 ins_cost(VOLATILE_REF_COST);
8228
8229 format %{ "#@membar_release_rvwmo\n\t"
8230 "fence rw, w" %}
8231
8232 ins_encode %{
8233 __ block_comment("membar_release_rvwmo");
8234 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
8235 %}
8236 ins_pipe(pipe_serial);
8237 %}
8238
8239 instruct membar_storestore_rvwmo() %{
8240 predicate(!UseZtso);
8241 match(MemBarStoreStore);
8242 match(StoreStoreFence);
8243 ins_cost(VOLATILE_REF_COST);
8244
8245 format %{ "#@membar_storestore_rvwmo\n\t"
8246 "fence w, w" %}
8247
8248 ins_encode %{
8249 __ membar(MacroAssembler::StoreStore);
8250 %}
8251 ins_pipe(pipe_serial);
8252 %}
8253
8254 instruct membar_storeload_rvwmo() %{
8255 predicate(!UseZtso);
8256 match(MemBarStoreLoad);
8257 ins_cost(VOLATILE_REF_COST);
8258
8259 format %{ "#@membar_storeload_rvwmo\n\t"
8260 "fence w, r"%}
8261
8262 ins_encode %{
8263 __ block_comment("membar_storeload_rvwmo");
8264 __ membar(MacroAssembler::StoreLoad);
8265 %}
8266
8267 ins_pipe(pipe_serial);
8268 %}
8269
8270 instruct membar_volatile_rvwmo() %{
8271 predicate(!UseZtso);
8272 match(MemBarVolatile);
8273 ins_cost(VOLATILE_REF_COST);
8274
8275 format %{ "#@membar_volatile_rvwmo\n\t"
8276 "fence w, r"%}
8277
8278 ins_encode %{
8279 __ block_comment("membar_volatile_rvwmo");
8280 __ membar(MacroAssembler::StoreLoad);
8281 %}
8282
8283 ins_pipe(pipe_serial);
8284 %}
8285
8286 instruct membar_lock_rvwmo() %{
8287 predicate(!UseZtso);
8288 match(MemBarAcquireLock);
8289 match(MemBarReleaseLock);
8290 ins_cost(0);
8291
8292 format %{ "#@membar_lock_rvwmo (elided)" %}
8293
8294 ins_encode %{
8295 __ block_comment("membar_lock_rvwmo (elided)");
8296 %}
8297
8298 ins_pipe(pipe_serial);
8299 %}
8300
8301 instruct unnecessary_membar_volatile_rvwmo() %{
8302 predicate(!UseZtso && Matcher::post_store_load_barrier(n));
8303 match(MemBarVolatile);
8304 ins_cost(0);
8305
8306 size(0);
8307 format %{ "#@unnecessary_membar_volatile_rvwmo (unnecessary so empty encoding)" %}
8308 ins_encode %{
8309 __ block_comment("unnecessary_membar_volatile_rvwmo");
8310 %}
8311 ins_pipe(real_empty);
8312 %}
8313
8314 instruct membar_full_rvwmo() %{
8315 predicate(!UseZtso);
8316 match(MemBarFull);
8317 ins_cost(VOLATILE_REF_COST);
8318
8319 format %{ "#@membar_full_rvwmo\n\t"
8320 "fence rw, rw" %}
8321
8322 ins_encode %{
8323 __ block_comment("membar_full_rvwmo");
8324 __ membar(MacroAssembler::AnyAny);
8325 %}
8326
8327 ins_pipe(pipe_serial);
8328 %}
8329
8330 instruct spin_wait() %{
8331 predicate(UseZihintpause);
8332 match(OnSpinWait);
8333 ins_cost(CACHE_MISS_COST);
8334
8335 format %{ "spin_wait" %}
8336
8337 ins_encode %{
8338 __ pause();
8339 %}
8340
8341 ins_pipe(pipe_serial);
8342 %}
8343
8344 // ============================================================================
8345 // Cast Instructions (Java-level type cast)
8346
8347 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8348 match(Set dst (CastX2P src));
8349
8350 ins_cost(ALU_COST);
8351 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8352
8353 ins_encode %{
8354 if ($dst$$reg != $src$$reg) {
8355 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8356 }
8357 %}
8358
8359 ins_pipe(ialu_reg);
8360 %}
8361
8362 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8363 match(Set dst (CastP2X src));
8364
8365 ins_cost(ALU_COST);
8366 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8367
8368 ins_encode %{
8369 if ($dst$$reg != $src$$reg) {
8370 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8371 }
8372 %}
8373
8374 ins_pipe(ialu_reg);
8375 %}
8376
8377 instruct castPP(iRegPNoSp dst)
8378 %{
8379 match(Set dst (CastPP dst));
8380 ins_cost(0);
8381
8382 size(0);
8383 format %{ "# castPP of $dst, #@castPP" %}
8384 ins_encode(/* empty encoding */);
8385 ins_pipe(pipe_class_empty);
8386 %}
8387
8388 instruct castLL(iRegL dst)
8389 %{
8390 match(Set dst (CastLL dst));
8391
8392 size(0);
8393 format %{ "# castLL of $dst, #@castLL" %}
8394 ins_encode(/* empty encoding */);
8395 ins_cost(0);
8396 ins_pipe(pipe_class_empty);
8397 %}
8398
8399 instruct castII(iRegI dst)
8400 %{
8401 match(Set dst (CastII dst));
8402
8403 size(0);
8404 format %{ "# castII of $dst, #@castII" %}
8405 ins_encode(/* empty encoding */);
8406 ins_cost(0);
8407 ins_pipe(pipe_class_empty);
8408 %}
8409
8410 instruct checkCastPP(iRegPNoSp dst)
8411 %{
8412 match(Set dst (CheckCastPP dst));
8413
8414 size(0);
8415 ins_cost(0);
8416 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8417 ins_encode(/* empty encoding */);
8418 ins_pipe(pipe_class_empty);
8419 %}
8420
8421 instruct castHH(fRegF dst)
8422 %{
8423 match(Set dst (CastHH dst));
8424
8425 size(0);
8426 format %{ "# castHH of $dst" %}
8427 ins_encode(/* empty encoding */);
8428 ins_cost(0);
8429 ins_pipe(pipe_class_empty);
8430 %}
8431
8432 instruct castFF(fRegF dst)
8433 %{
8434 match(Set dst (CastFF dst));
8435
8436 size(0);
8437 format %{ "# castFF of $dst" %}
8438 ins_encode(/* empty encoding */);
8439 ins_cost(0);
8440 ins_pipe(pipe_class_empty);
8441 %}
8442
8443 instruct castDD(fRegD dst)
8444 %{
8445 match(Set dst (CastDD dst));
8446
8447 size(0);
8448 format %{ "# castDD of $dst" %}
8449 ins_encode(/* empty encoding */);
8450 ins_cost(0);
8451 ins_pipe(pipe_class_empty);
8452 %}
8453
8454 instruct castVV(vReg dst)
8455 %{
8456 match(Set dst (CastVV dst));
8457
8458 size(0);
8459 format %{ "# castVV of $dst" %}
8460 ins_encode(/* empty encoding */);
8461 ins_cost(0);
8462 ins_pipe(pipe_class_empty);
8463 %}
8464
8465 instruct castVVMask(vRegMask dst)
8466 %{
8467 match(Set dst (CastVV dst));
8468
8469 size(0);
8470 format %{ "# castVV of $dst" %}
8471 ins_encode(/* empty encoding */);
8472 ins_cost(0);
8473 ins_pipe(pipe_class_empty);
8474 %}
8475
8476 // ============================================================================
8477 // Convert Instructions
8478
8479 // int to bool
8480 instruct convI2Bool(iRegINoSp dst, iRegI src)
8481 %{
8482 match(Set dst (Conv2B src));
8483
8484 ins_cost(ALU_COST);
8485 format %{ "snez $dst, $src\t#@convI2Bool" %}
8486
8487 ins_encode %{
8488 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8489 %}
8490
8491 ins_pipe(ialu_reg);
8492 %}
8493
8494 // pointer to bool
8495 instruct convP2Bool(iRegINoSp dst, iRegP src)
8496 %{
8497 match(Set dst (Conv2B src));
8498
8499 ins_cost(ALU_COST);
8500 format %{ "snez $dst, $src\t#@convP2Bool" %}
8501
8502 ins_encode %{
8503 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8504 %}
8505
8506 ins_pipe(ialu_reg);
8507 %}
8508
8509 // int <-> long
8510
8511 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8512 %{
8513 match(Set dst (ConvI2L src));
8514
8515 ins_cost(ALU_COST);
8516 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8517 ins_encode %{
8518 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8519 %}
8520 ins_pipe(ialu_reg);
8521 %}
8522
8523 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8524 match(Set dst (ConvL2I src));
8525
8526 ins_cost(ALU_COST);
8527 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8528
8529 ins_encode %{
8530 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8531 %}
8532
8533 ins_pipe(ialu_reg);
8534 %}
8535
8536 // int to unsigned long (Zero-extend)
8537 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8538 %{
8539 match(Set dst (AndL (ConvI2L src) mask));
8540
8541 ins_cost(ALU_COST * 2);
8542 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8543
8544 ins_encode %{
8545 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8546 %}
8547
8548 ins_pipe(ialu_reg_shift);
8549 %}
8550
8551 // float <-> double
8552
8553 instruct convF2D_reg(fRegD dst, fRegF src) %{
8554 match(Set dst (ConvF2D src));
8555
8556 ins_cost(XFER_COST);
8557 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8558
8559 ins_encode %{
8560 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8561 %}
8562
8563 ins_pipe(fp_f2d);
8564 %}
8565
8566 instruct convD2F_reg(fRegF dst, fRegD src) %{
8567 match(Set dst (ConvD2F src));
8568
8569 ins_cost(XFER_COST);
8570 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8571
8572 ins_encode %{
8573 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8574 %}
8575
8576 ins_pipe(fp_d2f);
8577 %}
8578
8579 // single <-> half precision
8580
8581 instruct convHF2F_reg_reg(fRegF dst, iRegIorL2I src, iRegINoSp tmp) %{
8582 match(Set dst (ConvHF2F src));
8583 effect(TEMP tmp);
8584 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8585 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8586 %}
8587 ins_encode %{
8588 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8589 %}
8590 ins_pipe(pipe_slow);
8591 %}
8592
8593 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8594 match(Set dst (ConvF2HF src));
8595 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8596 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8597 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8598 %}
8599 ins_encode %{
8600 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8601 %}
8602 ins_pipe(pipe_slow);
8603 %}
8604
8605 // half precision operations
8606
8607 instruct reinterpretS2HF(fRegF dst, iRegI src)
8608 %{
8609 match(Set dst (ReinterpretS2HF src));
8610 format %{ "fmv.h.x $dst, $src\t# reinterpretS2HF" %}
8611 ins_encode %{
8612 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8613 %}
8614 ins_pipe(fp_i2f);
8615 %}
8616
8617 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8618 %{
8619 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8620 format %{ "convF2HFAndS2HF $dst, $src" %}
8621 ins_encode %{
8622 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8623 %}
8624 ins_pipe(fp_uop_s);
8625 %}
8626
8627 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8628 %{
8629 match(Set dst (ReinterpretHF2S src));
8630 format %{ "fmv.x.h $dst, $src\t# reinterpretHF2S" %}
8631 ins_encode %{
8632 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8633 %}
8634 ins_pipe(fp_f2i);
8635 %}
8636
8637 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8638 %{
8639 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8640 format %{ "convHF2SAndHF2F $dst, $src" %}
8641 ins_encode %{
8642 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8643 %}
8644 ins_pipe(fp_uop_s);
8645 %}
8646
8647 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8648 %{
8649 match(Set dst (SqrtHF src));
8650 format %{ "fsqrt.h $dst, $src" %}
8651 ins_encode %{
8652 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8653 %}
8654 ins_pipe(fp_sqrt_s);
8655 %}
8656
8657 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8658 %{
8659 match(Set dst (AddHF src1 src2));
8660 match(Set dst (SubHF src1 src2));
8661 match(Set dst (MulHF src1 src2));
8662 match(Set dst (DivHF src1 src2));
8663 format %{ "binop_hf $dst, $src1, $src2" %}
8664 ins_encode %{
8665 int opcode = this->ideal_Opcode();
8666 switch(opcode) {
8667 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8668 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8669 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8670 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8671 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8672 }
8673 %}
8674 ins_pipe(fp_dop_reg_reg_s);
8675 %}
8676
8677 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8678 %{
8679 predicate(!UseZfa);
8680 match(Set dst (MinHF src1 src2));
8681 effect(KILL cr);
8682
8683 format %{ "min_hf $dst, $src1, $src2" %}
8684
8685 ins_encode %{
8686 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8687 __ FLOAT_TYPE::half_precision, true /* is_min */);
8688 %}
8689 ins_pipe(pipe_class_default);
8690 %}
8691
8692 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8693 %{
8694 predicate(UseZfa);
8695 match(Set dst (MinHF src1 src2));
8696
8697 format %{ "min_hf $dst, $src1, $src2" %}
8698
8699 ins_encode %{
8700 __ fminm_h(as_FloatRegister($dst$$reg),
8701 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8702 %}
8703
8704 ins_pipe(pipe_class_default);
8705 %}
8706
8707 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8708 %{
8709 predicate(!UseZfa);
8710 match(Set dst (MaxHF src1 src2));
8711 effect(KILL cr);
8712
8713 format %{ "max_hf $dst, $src1, $src2" %}
8714
8715 ins_encode %{
8716 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8717 __ FLOAT_TYPE::half_precision, false /* is_min */);
8718 %}
8719 ins_pipe(pipe_class_default);
8720 %}
8721
8722 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8723 %{
8724 predicate(UseZfa);
8725 match(Set dst (MaxHF src1 src2));
8726
8727 format %{ "max_hf $dst, $src1, $src2" %}
8728
8729 ins_encode %{
8730 __ fmaxm_h(as_FloatRegister($dst$$reg),
8731 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8732 %}
8733
8734 ins_pipe(pipe_class_default);
8735 %}
8736
8737 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8738 %{
8739 match(Set dst (FmaHF src3 (Binary src1 src2)));
8740 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8741 ins_encode %{
8742 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8743 %}
8744 ins_pipe(pipe_class_default);
8745 %}
8746
8747 // float <-> int
8748
8749 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8750 match(Set dst (ConvF2I src));
8751
8752 ins_cost(XFER_COST);
8753 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8754
8755 ins_encode %{
8756 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8757 %}
8758
8759 ins_pipe(fp_f2i);
8760 %}
8761
8762 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8763 match(Set dst (ConvI2F src));
8764
8765 ins_cost(XFER_COST);
8766 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8767
8768 ins_encode %{
8769 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8770 %}
8771
8772 ins_pipe(fp_i2f);
8773 %}
8774
8775 // float <-> long
8776
8777 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8778 match(Set dst (ConvF2L src));
8779
8780 ins_cost(XFER_COST);
8781 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8782
8783 ins_encode %{
8784 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8785 %}
8786
8787 ins_pipe(fp_f2l);
8788 %}
8789
8790 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8791 match(Set dst (ConvL2F src));
8792
8793 ins_cost(XFER_COST);
8794 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8795
8796 ins_encode %{
8797 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8798 %}
8799
8800 ins_pipe(fp_l2f);
8801 %}
8802
8803 // double <-> int
8804
8805 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8806 match(Set dst (ConvD2I src));
8807
8808 ins_cost(XFER_COST);
8809 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8810
8811 ins_encode %{
8812 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8813 %}
8814
8815 ins_pipe(fp_d2i);
8816 %}
8817
8818 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8819 match(Set dst (ConvI2D src));
8820
8821 ins_cost(XFER_COST);
8822 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8823
8824 ins_encode %{
8825 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8826 %}
8827
8828 ins_pipe(fp_i2d);
8829 %}
8830
8831 // double <-> long
8832
8833 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8834 match(Set dst (ConvD2L src));
8835
8836 ins_cost(XFER_COST);
8837 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8838
8839 ins_encode %{
8840 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8841 %}
8842
8843 ins_pipe(fp_d2l);
8844 %}
8845
8846 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8847 match(Set dst (ConvL2D src));
8848
8849 ins_cost(XFER_COST);
8850 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8851
8852 ins_encode %{
8853 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8854 %}
8855
8856 ins_pipe(fp_l2d);
8857 %}
8858
8859 // Convert oop into int for vectors alignment masking
8860 instruct convP2I(iRegINoSp dst, iRegP src) %{
8861 match(Set dst (ConvL2I (CastP2X src)));
8862
8863 ins_cost(ALU_COST * 2);
8864 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8865
8866 ins_encode %{
8867 __ zext($dst$$Register, $src$$Register, 32);
8868 %}
8869
8870 ins_pipe(ialu_reg);
8871 %}
8872
8873 // Convert compressed oop into int for vectors alignment masking
8874 // in case of 32bit oops (heap < 4Gb).
8875 instruct convN2I(iRegINoSp dst, iRegN src)
8876 %{
8877 predicate(CompressedOops::shift() == 0);
8878 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8879
8880 ins_cost(ALU_COST);
8881 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8882
8883 ins_encode %{
8884 __ mv($dst$$Register, $src$$Register);
8885 %}
8886
8887 ins_pipe(ialu_reg);
8888 %}
8889
8890 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8891 match(Set dst (RoundD src));
8892
8893 ins_cost(XFER_COST + BRANCH_COST);
8894 effect(TEMP ftmp);
8895 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8896
8897 ins_encode %{
8898 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8899 %}
8900
8901 ins_pipe(pipe_slow);
8902 %}
8903
8904 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8905 match(Set dst (RoundF src));
8906
8907 ins_cost(XFER_COST + BRANCH_COST);
8908 effect(TEMP ftmp);
8909 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8910
8911 ins_encode %{
8912 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8913 %}
8914
8915 ins_pipe(pipe_slow);
8916 %}
8917
8918 // Convert oop pointer into compressed form
8919 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8920 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8921 match(Set dst (EncodeP src));
8922 ins_cost(ALU_COST);
8923 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8924 ins_encode %{
8925 Register s = $src$$Register;
8926 Register d = $dst$$Register;
8927 __ encode_heap_oop(d, s);
8928 %}
8929 ins_pipe(pipe_class_default);
8930 %}
8931
8932 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8933 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8934 match(Set dst (EncodeP src));
8935 ins_cost(ALU_COST);
8936 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8937 ins_encode %{
8938 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8939 %}
8940 ins_pipe(pipe_class_default);
8941 %}
8942
8943 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8944 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8945 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8946 match(Set dst (DecodeN src));
8947
8948 ins_cost(0);
8949 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8950 ins_encode %{
8951 Register s = $src$$Register;
8952 Register d = $dst$$Register;
8953 __ decode_heap_oop(d, s);
8954 %}
8955 ins_pipe(pipe_class_default);
8956 %}
8957
8958 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8959 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8960 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8961 match(Set dst (DecodeN src));
8962
8963 ins_cost(0);
8964 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8965 ins_encode %{
8966 Register s = $src$$Register;
8967 Register d = $dst$$Register;
8968 __ decode_heap_oop_not_null(d, s);
8969 %}
8970 ins_pipe(pipe_class_default);
8971 %}
8972
8973 // Convert klass pointer into compressed form.
8974 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8975 match(Set dst (EncodePKlass src));
8976
8977 ins_cost(ALU_COST);
8978 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8979
8980 ins_encode %{
8981 Register src_reg = as_Register($src$$reg);
8982 Register dst_reg = as_Register($dst$$reg);
8983 __ encode_klass_not_null(dst_reg, src_reg, t0);
8984 %}
8985
8986 ins_pipe(pipe_class_default);
8987 %}
8988
8989 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8990 match(Set dst (DecodeNKlass src));
8991
8992 effect(TEMP_DEF dst, TEMP tmp);
8993
8994 ins_cost(ALU_COST);
8995 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8996
8997 ins_encode %{
8998 Register src_reg = as_Register($src$$reg);
8999 Register dst_reg = as_Register($dst$$reg);
9000 Register tmp_reg = as_Register($tmp$$reg);
9001 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
9002 %}
9003
9004 ins_pipe(pipe_class_default);
9005 %}
9006
9007 // stack <-> reg and reg <-> reg shuffles with no conversion
9008
9009 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
9010
9011 match(Set dst (MoveF2I src));
9012
9013 effect(DEF dst, USE src);
9014
9015 ins_cost(LOAD_COST);
9016
9017 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
9018
9019 ins_encode %{
9020 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
9021 %}
9022
9023 ins_pipe(iload_reg_reg);
9024
9025 %}
9026
9027 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
9028
9029 match(Set dst (MoveI2F src));
9030
9031 effect(DEF dst, USE src);
9032
9033 ins_cost(LOAD_COST);
9034
9035 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
9036
9037 ins_encode %{
9038 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9039 %}
9040
9041 ins_pipe(fp_load_mem_s);
9042
9043 %}
9044
9045 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
9046
9047 match(Set dst (MoveD2L src));
9048
9049 effect(DEF dst, USE src);
9050
9051 ins_cost(LOAD_COST);
9052
9053 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
9054
9055 ins_encode %{
9056 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
9057 %}
9058
9059 ins_pipe(iload_reg_reg);
9060
9061 %}
9062
9063 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
9064
9065 match(Set dst (MoveL2D src));
9066
9067 effect(DEF dst, USE src);
9068
9069 ins_cost(LOAD_COST);
9070
9071 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
9072
9073 ins_encode %{
9074 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
9075 %}
9076
9077 ins_pipe(fp_load_mem_d);
9078
9079 %}
9080
9081 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
9082
9083 match(Set dst (MoveF2I src));
9084
9085 effect(DEF dst, USE src);
9086
9087 ins_cost(STORE_COST);
9088
9089 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
9090
9091 ins_encode %{
9092 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9093 %}
9094
9095 ins_pipe(fp_store_reg_s);
9096
9097 %}
9098
9099 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
9100
9101 match(Set dst (MoveI2F src));
9102
9103 effect(DEF dst, USE src);
9104
9105 ins_cost(STORE_COST);
9106
9107 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
9108
9109 ins_encode %{
9110 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
9111 %}
9112
9113 ins_pipe(istore_reg_reg);
9114
9115 %}
9116
9117 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
9118
9119 match(Set dst (MoveD2L src));
9120
9121 effect(DEF dst, USE src);
9122
9123 ins_cost(STORE_COST);
9124
9125 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
9126
9127 ins_encode %{
9128 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
9129 %}
9130
9131 ins_pipe(fp_store_reg_d);
9132
9133 %}
9134
9135 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
9136
9137 match(Set dst (MoveL2D src));
9138
9139 effect(DEF dst, USE src);
9140
9141 ins_cost(STORE_COST);
9142
9143 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
9144
9145 ins_encode %{
9146 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
9147 %}
9148
9149 ins_pipe(istore_reg_reg);
9150
9151 %}
9152
9153 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
9154
9155 match(Set dst (MoveF2I src));
9156
9157 effect(DEF dst, USE src);
9158
9159 ins_cost(FMVX_COST);
9160
9161 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
9162
9163 ins_encode %{
9164 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9165 %}
9166
9167 ins_pipe(fp_f2i);
9168
9169 %}
9170
9171 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
9172
9173 match(Set dst (MoveI2F src));
9174
9175 effect(DEF dst, USE src);
9176
9177 ins_cost(FMVX_COST);
9178
9179 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
9180
9181 ins_encode %{
9182 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9183 %}
9184
9185 ins_pipe(fp_i2f);
9186
9187 %}
9188
9189 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
9190
9191 match(Set dst (MoveD2L src));
9192
9193 effect(DEF dst, USE src);
9194
9195 ins_cost(FMVX_COST);
9196
9197 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
9198
9199 ins_encode %{
9200 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
9201 %}
9202
9203 ins_pipe(fp_d2l);
9204
9205 %}
9206
9207 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
9208
9209 match(Set dst (MoveL2D src));
9210
9211 effect(DEF dst, USE src);
9212
9213 ins_cost(FMVX_COST);
9214
9215 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
9216
9217 ins_encode %{
9218 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
9219 %}
9220
9221 ins_pipe(fp_l2d);
9222
9223 %}
9224
9225 // ============================================================================
9226 // Compare Instructions which set the result float comparisons in dest register.
9227
9228 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
9229 %{
9230 match(Set dst (CmpF3 op1 op2));
9231
9232 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9233 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
9234 "bgtz $dst, done\n\t"
9235 "feq.s $dst, $op1, $op2\n\t"
9236 "addi $dst, $dst, -1\n\t"
9237 "done:"
9238 %}
9239
9240 ins_encode %{
9241 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9242 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
9243 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9244 %}
9245
9246 ins_pipe(pipe_class_default);
9247 %}
9248
9249 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
9250 %{
9251 match(Set dst (CmpD3 op1 op2));
9252
9253 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
9254 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
9255 "bgtz $dst, done\n\t"
9256 "feq.d $dst, $op1, $op2\n\t"
9257 "addi $dst, $dst, -1\n\t"
9258 "done:"
9259 %}
9260
9261 ins_encode %{
9262 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
9263 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
9264 %}
9265
9266 ins_pipe(pipe_class_default);
9267 %}
9268
9269 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9270 %{
9271 match(Set dst (CmpL3 op1 op2));
9272
9273 ins_cost(ALU_COST * 3 + BRANCH_COST);
9274 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
9275 "bnez $dst, done\n\t"
9276 "slt $dst, $op1, $op2\n\t"
9277 "neg $dst, $dst\n\t"
9278 "done:"
9279 %}
9280 ins_encode %{
9281 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9282 __ mv(as_Register($dst$$reg), t0);
9283 %}
9284
9285 ins_pipe(pipe_class_default);
9286 %}
9287
9288 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
9289 %{
9290 match(Set dst (CmpUL3 op1 op2));
9291
9292 ins_cost(ALU_COST * 3 + BRANCH_COST);
9293 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
9294 "bnez $dst, done\n\t"
9295 "sltu $dst, $op1, $op2\n\t"
9296 "neg $dst, $dst\n\t"
9297 "done:"
9298 %}
9299 ins_encode %{
9300 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9301 __ mv(as_Register($dst$$reg), t0);
9302 %}
9303
9304 ins_pipe(pipe_class_default);
9305 %}
9306
9307 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
9308 %{
9309 match(Set dst (CmpU3 op1 op2));
9310
9311 ins_cost(ALU_COST * 3 + BRANCH_COST);
9312 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
9313 "bnez $dst, done\n\t"
9314 "sltu $dst, $op1, $op2\n\t"
9315 "neg $dst, $dst\n\t"
9316 "done:"
9317 %}
9318 ins_encode %{
9319 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
9320 __ mv(as_Register($dst$$reg), t0);
9321 %}
9322
9323 ins_pipe(pipe_class_default);
9324 %}
9325
9326 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
9327 %{
9328 match(Set dst (CmpLTMask p q));
9329
9330 ins_cost(2 * ALU_COST);
9331
9332 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9333 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9334 %}
9335
9336 ins_encode %{
9337 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9338 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9339 %}
9340
9341 ins_pipe(ialu_reg_reg);
9342 %}
9343
9344 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9345 %{
9346 match(Set dst (CmpLTMask op zero));
9347
9348 ins_cost(ALU_COST);
9349
9350 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9351
9352 ins_encode %{
9353 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9354 %}
9355
9356 ins_pipe(ialu_reg_shift);
9357 %}
9358
9359
9360 // ============================================================================
9361 // Max and Min
9362
9363 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9364 %{
9365 match(Set dst (MinI dst src));
9366
9367 ins_cost(BRANCH_COST + ALU_COST);
9368 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9369
9370 ins_encode %{
9371 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9372 as_Register($dst$$reg), as_Register($src$$reg));
9373 %}
9374
9375 ins_pipe(pipe_class_compare);
9376 %}
9377
9378 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9379 %{
9380 match(Set dst (MaxI dst src));
9381
9382 ins_cost(BRANCH_COST + ALU_COST);
9383 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9384
9385 ins_encode %{
9386 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9387 as_Register($dst$$reg), as_Register($src$$reg));
9388 %}
9389
9390 ins_pipe(pipe_class_compare);
9391 %}
9392
9393 // special case for comparing with zero
9394 // n.b. this is selected in preference to the rule above because it
9395 // avoids loading constant 0 into a source register
9396
9397 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9398 %{
9399 match(Set dst (MinI dst zero));
9400 match(Set dst (MinI zero dst));
9401
9402 ins_cost(BRANCH_COST + ALU_COST);
9403 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9404
9405 ins_encode %{
9406 __ cmov_gt(as_Register($dst$$reg), zr,
9407 as_Register($dst$$reg), zr);
9408 %}
9409
9410 ins_pipe(pipe_class_compare);
9411 %}
9412
9413 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9414 %{
9415 match(Set dst (MaxI dst zero));
9416 match(Set dst (MaxI zero dst));
9417
9418 ins_cost(BRANCH_COST + ALU_COST);
9419 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9420
9421 ins_encode %{
9422 __ cmov_lt(as_Register($dst$$reg), zr,
9423 as_Register($dst$$reg), zr);
9424 %}
9425
9426 ins_pipe(pipe_class_compare);
9427 %}
9428
9429 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9430 %{
9431 match(Set dst (MinI src1 src2));
9432
9433 effect(DEF dst, USE src1, USE src2);
9434
9435 ins_cost(BRANCH_COST + ALU_COST * 2);
9436 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9437
9438 ins_encode %{
9439 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9440 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9441 as_Register($dst$$reg), as_Register($src2$$reg));
9442 %}
9443
9444 ins_pipe(pipe_class_compare);
9445 %}
9446
9447 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9448 %{
9449 match(Set dst (MaxI src1 src2));
9450
9451 effect(DEF dst, USE src1, USE src2);
9452
9453 ins_cost(BRANCH_COST + ALU_COST * 2);
9454 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9455
9456 ins_encode %{
9457 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9458 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9459 as_Register($dst$$reg), as_Register($src2$$reg));
9460 %}
9461
9462 ins_pipe(pipe_class_compare);
9463 %}
9464
9465 // ============================================================================
9466 // Branch Instructions
9467 // Direct Branch.
9468 instruct branch(label lbl)
9469 %{
9470 match(Goto);
9471
9472 effect(USE lbl);
9473
9474 ins_cost(BRANCH_COST);
9475 format %{ "j $lbl\t#@branch" %}
9476
9477 ins_encode(riscv_enc_j(lbl));
9478
9479 ins_pipe(pipe_branch);
9480 %}
9481
9482 // ============================================================================
9483 // Compare and Branch Instructions
9484
9485 // Patterns for short (< 12KiB) variants
9486
9487 // Compare flags and branch near instructions.
9488 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9489 match(If cmp cr);
9490 effect(USE lbl);
9491
9492 ins_cost(BRANCH_COST);
9493 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9494
9495 ins_encode %{
9496 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9497 %}
9498 ins_pipe(pipe_cmpz_branch);
9499 ins_short_branch(1);
9500 %}
9501
9502 // Compare signed int and branch near instructions
9503 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9504 %{
9505 // Same match rule as `far_cmpI_branch'.
9506 match(If cmp (CmpI op1 op2));
9507
9508 effect(USE lbl);
9509
9510 ins_cost(BRANCH_COST);
9511
9512 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9513
9514 ins_encode %{
9515 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9516 %}
9517
9518 ins_pipe(pipe_cmp_branch);
9519 ins_short_branch(1);
9520 %}
9521
9522 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9523 %{
9524 // Same match rule as `far_cmpI_loop'.
9525 match(CountedLoopEnd cmp (CmpI op1 op2));
9526
9527 effect(USE lbl);
9528
9529 ins_cost(BRANCH_COST);
9530
9531 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9532
9533 ins_encode %{
9534 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9535 %}
9536
9537 ins_pipe(pipe_cmp_branch);
9538 ins_short_branch(1);
9539 %}
9540
9541 // Compare unsigned int and branch near instructions
9542 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9543 %{
9544 // Same match rule as `far_cmpU_branch'.
9545 match(If cmp (CmpU op1 op2));
9546
9547 effect(USE lbl);
9548
9549 ins_cost(BRANCH_COST);
9550
9551 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9552
9553 ins_encode %{
9554 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9555 as_Register($op2$$reg), *($lbl$$label));
9556 %}
9557
9558 ins_pipe(pipe_cmp_branch);
9559 ins_short_branch(1);
9560 %}
9561
9562 // Compare signed long and branch near instructions
9563 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9564 %{
9565 // Same match rule as `far_cmpL_branch'.
9566 match(If cmp (CmpL op1 op2));
9567
9568 effect(USE lbl);
9569
9570 ins_cost(BRANCH_COST);
9571
9572 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9573
9574 ins_encode %{
9575 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9576 %}
9577
9578 ins_pipe(pipe_cmp_branch);
9579 ins_short_branch(1);
9580 %}
9581
9582 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9583 %{
9584 // Same match rule as `far_cmpL_loop'.
9585 match(CountedLoopEnd cmp (CmpL op1 op2));
9586
9587 effect(USE lbl);
9588
9589 ins_cost(BRANCH_COST);
9590
9591 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9592
9593 ins_encode %{
9594 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9595 %}
9596
9597 ins_pipe(pipe_cmp_branch);
9598 ins_short_branch(1);
9599 %}
9600
9601 // Compare unsigned long and branch near instructions
9602 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9603 %{
9604 // Same match rule as `far_cmpUL_branch'.
9605 match(If cmp (CmpUL op1 op2));
9606
9607 effect(USE lbl);
9608
9609 ins_cost(BRANCH_COST);
9610 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9611
9612 ins_encode %{
9613 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9614 as_Register($op2$$reg), *($lbl$$label));
9615 %}
9616
9617 ins_pipe(pipe_cmp_branch);
9618 ins_short_branch(1);
9619 %}
9620
9621 // Compare pointer and branch near instructions
9622 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9623 %{
9624 // Same match rule as `far_cmpP_branch'.
9625 match(If cmp (CmpP op1 op2));
9626
9627 effect(USE lbl);
9628
9629 ins_cost(BRANCH_COST);
9630
9631 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9632
9633 ins_encode %{
9634 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9635 as_Register($op2$$reg), *($lbl$$label));
9636 %}
9637
9638 ins_pipe(pipe_cmp_branch);
9639 ins_short_branch(1);
9640 %}
9641
9642 // Compare narrow pointer and branch near instructions
9643 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9644 %{
9645 // Same match rule as `far_cmpN_branch'.
9646 match(If cmp (CmpN op1 op2));
9647
9648 effect(USE lbl);
9649
9650 ins_cost(BRANCH_COST);
9651
9652 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9653
9654 ins_encode %{
9655 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9656 as_Register($op2$$reg), *($lbl$$label));
9657 %}
9658
9659 ins_pipe(pipe_cmp_branch);
9660 ins_short_branch(1);
9661 %}
9662
9663 // Compare float and branch near instructions
9664 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9665 %{
9666 // Same match rule as `far_cmpF_branch'.
9667 match(If cmp (CmpF op1 op2));
9668
9669 effect(USE lbl);
9670
9671 ins_cost(XFER_COST + BRANCH_COST);
9672 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9673
9674 ins_encode %{
9675 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9676 %}
9677
9678 ins_pipe(pipe_class_compare);
9679 ins_short_branch(1);
9680 %}
9681
9682 // Compare double and branch near instructions
9683 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9684 %{
9685 // Same match rule as `far_cmpD_branch'.
9686 match(If cmp (CmpD op1 op2));
9687 effect(USE lbl);
9688
9689 ins_cost(XFER_COST + BRANCH_COST);
9690 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9691
9692 ins_encode %{
9693 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9694 as_FloatRegister($op2$$reg), *($lbl$$label));
9695 %}
9696
9697 ins_pipe(pipe_class_compare);
9698 ins_short_branch(1);
9699 %}
9700
9701 // Compare signed int with zero and branch near instructions
9702 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9703 %{
9704 // Same match rule as `far_cmpI_reg_imm0_branch'.
9705 match(If cmp (CmpI op1 zero));
9706
9707 effect(USE op1, USE lbl);
9708
9709 ins_cost(BRANCH_COST);
9710 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9711
9712 ins_encode %{
9713 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9714 %}
9715
9716 ins_pipe(pipe_cmpz_branch);
9717 ins_short_branch(1);
9718 %}
9719
9720 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9721 %{
9722 // Same match rule as `far_cmpI_reg_imm0_loop'.
9723 match(CountedLoopEnd cmp (CmpI op1 zero));
9724
9725 effect(USE op1, USE lbl);
9726
9727 ins_cost(BRANCH_COST);
9728
9729 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9730
9731 ins_encode %{
9732 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9733 %}
9734
9735 ins_pipe(pipe_cmpz_branch);
9736 ins_short_branch(1);
9737 %}
9738
9739 // Compare unsigned int with zero and branch near instructions
9740 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9741 %{
9742 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9743 match(If cmp (CmpU op1 zero));
9744
9745 effect(USE op1, USE lbl);
9746
9747 ins_cost(BRANCH_COST);
9748
9749 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9750
9751 ins_encode %{
9752 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9753 %}
9754
9755 ins_pipe(pipe_cmpz_branch);
9756 ins_short_branch(1);
9757 %}
9758
9759 // Compare signed long with zero and branch near instructions
9760 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9761 %{
9762 // Same match rule as `far_cmpL_reg_imm0_branch'.
9763 match(If cmp (CmpL op1 zero));
9764
9765 effect(USE op1, USE lbl);
9766
9767 ins_cost(BRANCH_COST);
9768
9769 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9770
9771 ins_encode %{
9772 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9773 %}
9774
9775 ins_pipe(pipe_cmpz_branch);
9776 ins_short_branch(1);
9777 %}
9778
9779 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9780 %{
9781 // Same match rule as `far_cmpL_reg_imm0_loop'.
9782 match(CountedLoopEnd cmp (CmpL op1 zero));
9783
9784 effect(USE op1, USE lbl);
9785
9786 ins_cost(BRANCH_COST);
9787
9788 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9789
9790 ins_encode %{
9791 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9792 %}
9793
9794 ins_pipe(pipe_cmpz_branch);
9795 ins_short_branch(1);
9796 %}
9797
9798 // Compare unsigned long with zero and branch near instructions
9799 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9800 %{
9801 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9802 match(If cmp (CmpUL op1 zero));
9803
9804 effect(USE op1, USE lbl);
9805
9806 ins_cost(BRANCH_COST);
9807
9808 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9809
9810 ins_encode %{
9811 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9812 %}
9813
9814 ins_pipe(pipe_cmpz_branch);
9815 ins_short_branch(1);
9816 %}
9817
9818 // Compare pointer with zero and branch near instructions
9819 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9820 // Same match rule as `far_cmpP_reg_imm0_branch'.
9821 match(If cmp (CmpP op1 zero));
9822 effect(USE lbl);
9823
9824 ins_cost(BRANCH_COST);
9825 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9826
9827 ins_encode %{
9828 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9829 %}
9830
9831 ins_pipe(pipe_cmpz_branch);
9832 ins_short_branch(1);
9833 %}
9834
9835 // Compare narrow pointer with zero and branch near instructions
9836 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9837 // Same match rule as `far_cmpN_reg_imm0_branch'.
9838 match(If cmp (CmpN op1 zero));
9839 effect(USE lbl);
9840
9841 ins_cost(BRANCH_COST);
9842
9843 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9844
9845 ins_encode %{
9846 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9847 %}
9848
9849 ins_pipe(pipe_cmpz_branch);
9850 ins_short_branch(1);
9851 %}
9852
9853 // Compare narrow pointer with pointer zero and branch near instructions
9854 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9855 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9856 match(If cmp (CmpP (DecodeN op1) zero));
9857 effect(USE lbl);
9858
9859 ins_cost(BRANCH_COST);
9860 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9861
9862 ins_encode %{
9863 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9864 %}
9865
9866 ins_pipe(pipe_cmpz_branch);
9867 ins_short_branch(1);
9868 %}
9869
9870 // Patterns for far (20KiB) variants
9871
9872 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9873 match(If cmp cr);
9874 effect(USE lbl);
9875
9876 ins_cost(BRANCH_COST);
9877 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9878
9879 ins_encode %{
9880 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9881 %}
9882
9883 ins_pipe(pipe_cmpz_branch);
9884 %}
9885
9886 // Compare signed int and branch far instructions
9887 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9888 match(If cmp (CmpI op1 op2));
9889 effect(USE lbl);
9890
9891 ins_cost(BRANCH_COST * 2);
9892
9893 // the format instruction [far_b$cmp] here is be used as two insructions
9894 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9895 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9896
9897 ins_encode %{
9898 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9899 %}
9900
9901 ins_pipe(pipe_cmp_branch);
9902 %}
9903
9904 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9905 match(CountedLoopEnd cmp (CmpI op1 op2));
9906 effect(USE lbl);
9907
9908 ins_cost(BRANCH_COST * 2);
9909 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9910
9911 ins_encode %{
9912 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9913 %}
9914
9915 ins_pipe(pipe_cmp_branch);
9916 %}
9917
9918 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9919 match(If cmp (CmpU op1 op2));
9920 effect(USE lbl);
9921
9922 ins_cost(BRANCH_COST * 2);
9923 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9924
9925 ins_encode %{
9926 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9927 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9928 %}
9929
9930 ins_pipe(pipe_cmp_branch);
9931 %}
9932
9933 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9934 match(If cmp (CmpL op1 op2));
9935 effect(USE lbl);
9936
9937 ins_cost(BRANCH_COST * 2);
9938 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9939
9940 ins_encode %{
9941 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9942 %}
9943
9944 ins_pipe(pipe_cmp_branch);
9945 %}
9946
9947 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9948 match(CountedLoopEnd cmp (CmpL op1 op2));
9949 effect(USE lbl);
9950
9951 ins_cost(BRANCH_COST * 2);
9952 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9953
9954 ins_encode %{
9955 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9956 %}
9957
9958 ins_pipe(pipe_cmp_branch);
9959 %}
9960
9961 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9962 match(If cmp (CmpUL op1 op2));
9963 effect(USE lbl);
9964
9965 ins_cost(BRANCH_COST * 2);
9966 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9967
9968 ins_encode %{
9969 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9970 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9971 %}
9972
9973 ins_pipe(pipe_cmp_branch);
9974 %}
9975
9976 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9977 %{
9978 match(If cmp (CmpP op1 op2));
9979
9980 effect(USE lbl);
9981
9982 ins_cost(BRANCH_COST * 2);
9983
9984 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9985
9986 ins_encode %{
9987 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9988 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9989 %}
9990
9991 ins_pipe(pipe_cmp_branch);
9992 %}
9993
9994 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9995 %{
9996 match(If cmp (CmpN op1 op2));
9997
9998 effect(USE lbl);
9999
10000 ins_cost(BRANCH_COST * 2);
10001
10002 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
10003
10004 ins_encode %{
10005 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
10006 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
10007 %}
10008
10009 ins_pipe(pipe_cmp_branch);
10010 %}
10011
10012 // Float compare and branch instructions
10013 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
10014 %{
10015 match(If cmp (CmpF op1 op2));
10016
10017 effect(USE lbl);
10018
10019 ins_cost(XFER_COST + BRANCH_COST * 2);
10020 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
10021
10022 ins_encode %{
10023 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10024 *($lbl$$label), /* is_far */ true);
10025 %}
10026
10027 ins_pipe(pipe_class_compare);
10028 %}
10029
10030 // Double compare and branch instructions
10031 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
10032 %{
10033 match(If cmp (CmpD op1 op2));
10034 effect(USE lbl);
10035
10036 ins_cost(XFER_COST + BRANCH_COST * 2);
10037 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
10038
10039 ins_encode %{
10040 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
10041 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
10042 %}
10043
10044 ins_pipe(pipe_class_compare);
10045 %}
10046
10047 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10048 %{
10049 match(If cmp (CmpI op1 zero));
10050
10051 effect(USE op1, USE lbl);
10052
10053 ins_cost(BRANCH_COST * 2);
10054
10055 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
10056
10057 ins_encode %{
10058 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10059 %}
10060
10061 ins_pipe(pipe_cmpz_branch);
10062 %}
10063
10064 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
10065 %{
10066 match(CountedLoopEnd cmp (CmpI op1 zero));
10067
10068 effect(USE op1, USE lbl);
10069
10070 ins_cost(BRANCH_COST * 2);
10071
10072 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
10073
10074 ins_encode %{
10075 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10076 %}
10077
10078 ins_pipe(pipe_cmpz_branch);
10079 %}
10080
10081 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
10082 %{
10083 match(If cmp (CmpU op1 zero));
10084
10085 effect(USE op1, USE lbl);
10086
10087 ins_cost(BRANCH_COST * 2);
10088
10089 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
10090
10091 ins_encode %{
10092 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10093 %}
10094
10095 ins_pipe(pipe_cmpz_branch);
10096 %}
10097
10098 // compare lt/ge unsigned instructs has no short instruct with same match
10099 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
10100 %{
10101 match(If cmp (CmpU op1 zero));
10102
10103 effect(USE op1, USE lbl);
10104
10105 ins_cost(BRANCH_COST);
10106
10107 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
10108
10109 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10110
10111 ins_pipe(pipe_cmpz_branch);
10112 %}
10113
10114 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10115 %{
10116 match(If cmp (CmpL op1 zero));
10117
10118 effect(USE op1, USE lbl);
10119
10120 ins_cost(BRANCH_COST * 2);
10121
10122 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
10123
10124 ins_encode %{
10125 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10126 %}
10127
10128 ins_pipe(pipe_cmpz_branch);
10129 %}
10130
10131 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
10132 %{
10133 match(CountedLoopEnd cmp (CmpL op1 zero));
10134
10135 effect(USE op1, USE lbl);
10136
10137 ins_cost(BRANCH_COST * 2);
10138
10139 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
10140
10141 ins_encode %{
10142 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
10143 %}
10144
10145 ins_pipe(pipe_cmpz_branch);
10146 %}
10147
10148 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
10149 %{
10150 match(If cmp (CmpUL op1 zero));
10151
10152 effect(USE op1, USE lbl);
10153
10154 ins_cost(BRANCH_COST * 2);
10155
10156 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
10157
10158 ins_encode %{
10159 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10160 %}
10161
10162 ins_pipe(pipe_cmpz_branch);
10163 %}
10164
10165 // compare lt/ge unsigned instructs has no short instruct with same match
10166 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
10167 %{
10168 match(If cmp (CmpUL op1 zero));
10169
10170 effect(USE op1, USE lbl);
10171
10172 ins_cost(BRANCH_COST);
10173
10174 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
10175
10176 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
10177
10178 ins_pipe(pipe_cmpz_branch);
10179 %}
10180
10181 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
10182 match(If cmp (CmpP op1 zero));
10183 effect(USE lbl);
10184
10185 ins_cost(BRANCH_COST * 2);
10186 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
10187
10188 ins_encode %{
10189 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10190 %}
10191
10192 ins_pipe(pipe_cmpz_branch);
10193 %}
10194
10195 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
10196 match(If cmp (CmpN op1 zero));
10197 effect(USE lbl);
10198
10199 ins_cost(BRANCH_COST * 2);
10200
10201 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
10202
10203 ins_encode %{
10204 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10205 %}
10206
10207 ins_pipe(pipe_cmpz_branch);
10208 %}
10209
10210 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
10211 match(If cmp (CmpP (DecodeN op1) zero));
10212 effect(USE lbl);
10213
10214 ins_cost(BRANCH_COST * 2);
10215 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
10216
10217 ins_encode %{
10218 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
10219 %}
10220
10221 ins_pipe(pipe_cmpz_branch);
10222 %}
10223
10224 // ============================================================================
10225 // Conditional Move Instructions
10226
10227 // --------- CMoveI ---------
10228
10229 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
10230 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
10231 ins_cost(ALU_COST + BRANCH_COST);
10232
10233 format %{
10234 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
10235 %}
10236
10237 ins_encode %{
10238 __ enc_cmove($cop$$cmpcode,
10239 as_Register($op1$$reg), as_Register($op2$$reg),
10240 as_Register($dst$$reg), as_Register($src$$reg));
10241 %}
10242
10243 ins_pipe(pipe_class_compare);
10244 %}
10245
10246 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
10247 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
10248 ins_cost(ALU_COST + BRANCH_COST);
10249
10250 format %{
10251 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
10252 %}
10253
10254 ins_encode %{
10255 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10256 as_Register($op1$$reg), as_Register($op2$$reg),
10257 as_Register($dst$$reg), as_Register($src$$reg));
10258 %}
10259
10260 ins_pipe(pipe_class_compare);
10261 %}
10262
10263 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
10264 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
10265 ins_cost(ALU_COST + BRANCH_COST);
10266
10267 format %{
10268 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
10269 %}
10270
10271 ins_encode %{
10272 __ enc_cmove($cop$$cmpcode,
10273 as_Register($op1$$reg), as_Register($op2$$reg),
10274 as_Register($dst$$reg), as_Register($src$$reg));
10275 %}
10276
10277 ins_pipe(pipe_class_compare);
10278 %}
10279
10280 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
10281 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10282 ins_cost(ALU_COST + BRANCH_COST);
10283
10284 format %{
10285 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
10286 %}
10287
10288 ins_encode %{
10289 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10290 as_Register($op1$$reg), as_Register($op2$$reg),
10291 as_Register($dst$$reg), as_Register($src$$reg));
10292 %}
10293
10294 ins_pipe(pipe_class_compare);
10295 %}
10296
10297 instruct cmovI_cmpF(iRegINoSp dst, iRegI src, fRegF op1, fRegF op2, cmpOp cop) %{
10298 match(Set dst (CMoveI (Binary cop (CmpF op1 op2)) (Binary dst src)));
10299 ins_cost(ALU_COST + BRANCH_COST);
10300
10301 format %{
10302 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpF\n\t"
10303 %}
10304
10305 ins_encode %{
10306 __ enc_cmove_cmp_fp($cop$$cmpcode,
10307 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10308 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10309 %}
10310
10311 ins_pipe(pipe_class_compare);
10312 %}
10313
10314 instruct cmovI_cmpD(iRegINoSp dst, iRegI src, fRegD op1, fRegD op2, cmpOp cop) %{
10315 match(Set dst (CMoveI (Binary cop (CmpD op1 op2)) (Binary dst src)));
10316 ins_cost(ALU_COST + BRANCH_COST);
10317
10318 format %{
10319 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpD\n\t"
10320 %}
10321
10322 ins_encode %{
10323 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10324 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10325 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10326 %}
10327
10328 ins_pipe(pipe_class_compare);
10329 %}
10330
10331 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
10332 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
10333 ins_cost(ALU_COST + BRANCH_COST);
10334
10335 format %{
10336 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
10337 %}
10338
10339 ins_encode %{
10340 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10341 as_Register($op1$$reg), as_Register($op2$$reg),
10342 as_Register($dst$$reg), as_Register($src$$reg));
10343 %}
10344
10345 ins_pipe(pipe_class_compare);
10346 %}
10347
10348 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
10349 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
10350 ins_cost(ALU_COST + BRANCH_COST);
10351
10352 format %{
10353 "CMoveI $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
10354 %}
10355
10356 ins_encode %{
10357 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10358 as_Register($op1$$reg), as_Register($op2$$reg),
10359 as_Register($dst$$reg), as_Register($src$$reg));
10360 %}
10361
10362 ins_pipe(pipe_class_compare);
10363 %}
10364
10365 // --------- CMoveL ---------
10366
10367 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10368 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10369 ins_cost(ALU_COST + BRANCH_COST);
10370
10371 format %{
10372 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10373 %}
10374
10375 ins_encode %{
10376 __ enc_cmove($cop$$cmpcode,
10377 as_Register($op1$$reg), as_Register($op2$$reg),
10378 as_Register($dst$$reg), as_Register($src$$reg));
10379 %}
10380
10381 ins_pipe(pipe_class_compare);
10382 %}
10383
10384 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10385 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10386 ins_cost(ALU_COST + BRANCH_COST);
10387
10388 format %{
10389 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10390 %}
10391
10392 ins_encode %{
10393 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10394 as_Register($op1$$reg), as_Register($op2$$reg),
10395 as_Register($dst$$reg), as_Register($src$$reg));
10396 %}
10397
10398 ins_pipe(pipe_class_compare);
10399 %}
10400
10401 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10402 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10403 ins_cost(ALU_COST + BRANCH_COST);
10404
10405 format %{
10406 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10407 %}
10408
10409 ins_encode %{
10410 __ enc_cmove($cop$$cmpcode,
10411 as_Register($op1$$reg), as_Register($op2$$reg),
10412 as_Register($dst$$reg), as_Register($src$$reg));
10413 %}
10414
10415 ins_pipe(pipe_class_compare);
10416 %}
10417
10418 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10419 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10420 ins_cost(ALU_COST + BRANCH_COST);
10421
10422 format %{
10423 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10424 %}
10425
10426 ins_encode %{
10427 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10428 as_Register($op1$$reg), as_Register($op2$$reg),
10429 as_Register($dst$$reg), as_Register($src$$reg));
10430 %}
10431
10432 ins_pipe(pipe_class_compare);
10433 %}
10434
10435 instruct cmovL_cmpF(iRegLNoSp dst, iRegL src, fRegF op1, fRegF op2, cmpOp cop) %{
10436 match(Set dst (CMoveL (Binary cop (CmpF op1 op2)) (Binary dst src)));
10437 ins_cost(ALU_COST + BRANCH_COST);
10438
10439 format %{
10440 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpF\n\t"
10441 %}
10442
10443 ins_encode %{
10444 __ enc_cmove_cmp_fp($cop$$cmpcode,
10445 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10446 as_Register($dst$$reg), as_Register($src$$reg), true /* is_single */);
10447 %}
10448
10449 ins_pipe(pipe_class_compare);
10450 %}
10451
10452 instruct cmovL_cmpD(iRegLNoSp dst, iRegL src, fRegD op1, fRegD op2, cmpOp cop) %{
10453 match(Set dst (CMoveL (Binary cop (CmpD op1 op2)) (Binary dst src)));
10454 ins_cost(ALU_COST + BRANCH_COST);
10455
10456 format %{
10457 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpD\n\t"
10458 %}
10459
10460 ins_encode %{
10461 __ enc_cmove_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10462 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10463 as_Register($dst$$reg), as_Register($src$$reg), false /* is_single */);
10464 %}
10465
10466 ins_pipe(pipe_class_compare);
10467 %}
10468
10469 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10470 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10471 ins_cost(ALU_COST + BRANCH_COST);
10472
10473 format %{
10474 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10475 %}
10476
10477 ins_encode %{
10478 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10479 as_Register($op1$$reg), as_Register($op2$$reg),
10480 as_Register($dst$$reg), as_Register($src$$reg));
10481 %}
10482
10483 ins_pipe(pipe_class_compare);
10484 %}
10485
10486 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10487 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10488 ins_cost(ALU_COST + BRANCH_COST);
10489
10490 format %{
10491 "CMoveL $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10492 %}
10493
10494 ins_encode %{
10495 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10496 as_Register($op1$$reg), as_Register($op2$$reg),
10497 as_Register($dst$$reg), as_Register($src$$reg));
10498 %}
10499
10500 ins_pipe(pipe_class_compare);
10501 %}
10502
10503 // --------- CMoveF ---------
10504
10505 instruct cmovF_cmpI(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOp cop) %{
10506 match(Set dst (CMoveF (Binary cop (CmpI op1 op2)) (Binary dst src)));
10507 ins_cost(ALU_COST + BRANCH_COST);
10508
10509 format %{
10510 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpI\n\t"
10511 %}
10512
10513 ins_encode %{
10514 __ enc_cmove_fp_cmp($cop$$cmpcode,
10515 as_Register($op1$$reg), as_Register($op2$$reg),
10516 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10517 %}
10518
10519 ins_pipe(pipe_class_compare);
10520 %}
10521
10522 instruct cmovF_cmpU(fRegF dst, fRegF src, iRegI op1, iRegI op2, cmpOpU cop) %{
10523 match(Set dst (CMoveF (Binary cop (CmpU op1 op2)) (Binary dst src)));
10524 ins_cost(ALU_COST + BRANCH_COST);
10525
10526 format %{
10527 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpU\n\t"
10528 %}
10529
10530 ins_encode %{
10531 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10532 as_Register($op1$$reg), as_Register($op2$$reg),
10533 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10534 %}
10535
10536 ins_pipe(pipe_class_compare);
10537 %}
10538
10539 instruct cmovF_cmpL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOp cop) %{
10540 match(Set dst (CMoveF (Binary cop (CmpL op1 op2)) (Binary dst src)));
10541 ins_cost(ALU_COST + BRANCH_COST);
10542
10543 format %{
10544 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpL\n\t"
10545 %}
10546
10547 ins_encode %{
10548 __ enc_cmove_fp_cmp($cop$$cmpcode,
10549 as_Register($op1$$reg), as_Register($op2$$reg),
10550 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10551 %}
10552
10553 ins_pipe(pipe_class_compare);
10554 %}
10555
10556 instruct cmovF_cmpUL(fRegF dst, fRegF src, iRegL op1, iRegL op2, cmpOpU cop) %{
10557 match(Set dst (CMoveF (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10558 ins_cost(ALU_COST + BRANCH_COST);
10559
10560 format %{
10561 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpUL\n\t"
10562 %}
10563
10564 ins_encode %{
10565 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10566 as_Register($op1$$reg), as_Register($op2$$reg),
10567 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10568 %}
10569
10570 ins_pipe(pipe_class_compare);
10571 %}
10572
10573 instruct cmovF_cmpF(fRegF dst, fRegF src, fRegF op1, fRegF op2, cmpOp cop) %{
10574 match(Set dst (CMoveF (Binary cop (CmpF op1 op2)) (Binary dst src)));
10575 ins_cost(ALU_COST + BRANCH_COST);
10576
10577 format %{
10578 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpF\n\t"
10579 %}
10580
10581 ins_encode %{
10582 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10583 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10584 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10585 true /* cmp_single */, true /* cmov_single */);
10586 %}
10587
10588 ins_pipe(pipe_class_compare);
10589 %}
10590
10591 instruct cmovF_cmpD(fRegF dst, fRegF src, fRegD op1, fRegD op2, cmpOp cop) %{
10592 match(Set dst (CMoveF (Binary cop (CmpD op1 op2)) (Binary dst src)));
10593 ins_cost(ALU_COST + BRANCH_COST);
10594
10595 format %{
10596 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpD\n\t"
10597 %}
10598
10599 ins_encode %{
10600 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10601 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10602 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10603 false /* cmp_single */, true /* cmov_single */);
10604 %}
10605
10606 ins_pipe(pipe_class_compare);
10607 %}
10608
10609 instruct cmovF_cmpN(fRegF dst, fRegF src, iRegN op1, iRegN op2, cmpOp cop) %{
10610 match(Set dst (CMoveF (Binary cop (CmpN op1 op2)) (Binary dst src)));
10611 ins_cost(ALU_COST + BRANCH_COST);
10612
10613 format %{
10614 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpN\n\t"
10615 %}
10616
10617 ins_encode %{
10618 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10619 as_Register($op1$$reg), as_Register($op2$$reg),
10620 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10621 %}
10622
10623 ins_pipe(pipe_class_compare);
10624 %}
10625
10626 instruct cmovF_cmpP(fRegF dst, fRegF src, iRegP op1, iRegP op2, cmpOp cop) %{
10627 match(Set dst (CMoveF (Binary cop (CmpP op1 op2)) (Binary dst src)));
10628 ins_cost(ALU_COST + BRANCH_COST);
10629
10630 format %{
10631 "CMoveF $dst, ($op1 $cop $op2), $dst, $src\t#@cmovF_cmpP\n\t"
10632 %}
10633
10634 ins_encode %{
10635 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10636 as_Register($op1$$reg), as_Register($op2$$reg),
10637 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), true /* is_single */);
10638 %}
10639
10640 ins_pipe(pipe_class_compare);
10641 %}
10642
10643 // --------- CMoveD ---------
10644
10645 instruct cmovD_cmpI(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOp cop) %{
10646 match(Set dst (CMoveD (Binary cop (CmpI op1 op2)) (Binary dst src)));
10647 ins_cost(ALU_COST + BRANCH_COST);
10648
10649 format %{
10650 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpI\n\t"
10651 %}
10652
10653 ins_encode %{
10654 __ enc_cmove_fp_cmp($cop$$cmpcode,
10655 as_Register($op1$$reg), as_Register($op2$$reg),
10656 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10657 %}
10658
10659 ins_pipe(pipe_class_compare);
10660 %}
10661
10662 instruct cmovD_cmpU(fRegD dst, fRegD src, iRegI op1, iRegI op2, cmpOpU cop) %{
10663 match(Set dst (CMoveD (Binary cop (CmpU op1 op2)) (Binary dst src)));
10664 ins_cost(ALU_COST + BRANCH_COST);
10665
10666 format %{
10667 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpU\n\t"
10668 %}
10669
10670 ins_encode %{
10671 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10672 as_Register($op1$$reg), as_Register($op2$$reg),
10673 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10674 %}
10675
10676 ins_pipe(pipe_class_compare);
10677 %}
10678
10679 instruct cmovD_cmpL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOp cop) %{
10680 match(Set dst (CMoveD (Binary cop (CmpL op1 op2)) (Binary dst src)));
10681 ins_cost(ALU_COST + BRANCH_COST);
10682
10683 format %{
10684 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpL\n\t"
10685 %}
10686
10687 ins_encode %{
10688 __ enc_cmove_fp_cmp($cop$$cmpcode,
10689 as_Register($op1$$reg), as_Register($op2$$reg),
10690 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10691 %}
10692
10693 ins_pipe(pipe_class_compare);
10694 %}
10695
10696 instruct cmovD_cmpUL(fRegD dst, fRegD src, iRegL op1, iRegL op2, cmpOpU cop) %{
10697 match(Set dst (CMoveD (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10698 ins_cost(ALU_COST + BRANCH_COST);
10699
10700 format %{
10701 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpUL\n\t"
10702 %}
10703
10704 ins_encode %{
10705 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10706 as_Register($op1$$reg), as_Register($op2$$reg),
10707 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10708 %}
10709
10710 ins_pipe(pipe_class_compare);
10711 %}
10712
10713 instruct cmovD_cmpF(fRegD dst, fRegD src, fRegF op1, fRegF op2, cmpOp cop) %{
10714 match(Set dst (CMoveD (Binary cop (CmpF op1 op2)) (Binary dst src)));
10715 ins_cost(ALU_COST + BRANCH_COST);
10716
10717 format %{
10718 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpF\n\t"
10719 %}
10720
10721 ins_encode %{
10722 __ enc_cmove_fp_cmp_fp($cop$$cmpcode,
10723 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10724 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10725 true /* cmp_single */, false /* cmov_single */);
10726 %}
10727
10728 ins_pipe(pipe_class_compare);
10729 %}
10730
10731 instruct cmovD_cmpD(fRegD dst, fRegD src, fRegD op1, fRegD op2, cmpOp cop) %{
10732 match(Set dst (CMoveD (Binary cop (CmpD op1 op2)) (Binary dst src)));
10733 ins_cost(ALU_COST + BRANCH_COST);
10734
10735 format %{
10736 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpD\n\t"
10737 %}
10738
10739 ins_encode %{
10740 __ enc_cmove_fp_cmp_fp($cop$$cmpcode | C2_MacroAssembler::double_branch_mask,
10741 as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
10742 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg),
10743 false /* cmp_single */, false /* cmov_single */);
10744 %}
10745
10746 ins_pipe(pipe_class_compare);
10747 %}
10748
10749 instruct cmovD_cmpN(fRegD dst, fRegD src, iRegN op1, iRegN op2, cmpOp cop) %{
10750 match(Set dst (CMoveD (Binary cop (CmpN op1 op2)) (Binary dst src)));
10751 ins_cost(ALU_COST + BRANCH_COST);
10752
10753 format %{
10754 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpN\n\t"
10755 %}
10756
10757 ins_encode %{
10758 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10759 as_Register($op1$$reg), as_Register($op2$$reg),
10760 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10761 %}
10762
10763 ins_pipe(pipe_class_compare);
10764 %}
10765
10766 instruct cmovD_cmpP(fRegD dst, fRegD src, iRegP op1, iRegP op2, cmpOp cop) %{
10767 match(Set dst (CMoveD (Binary cop (CmpP op1 op2)) (Binary dst src)));
10768 ins_cost(ALU_COST + BRANCH_COST);
10769
10770 format %{
10771 "CMoveD $dst, ($op1 $cop $op2), $dst, $src\t#@cmovD_cmpP\n\t"
10772 %}
10773
10774 ins_encode %{
10775 __ enc_cmove_fp_cmp($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10776 as_Register($op1$$reg), as_Register($op2$$reg),
10777 as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), false /* is_single */);
10778 %}
10779
10780 ins_pipe(pipe_class_compare);
10781 %}
10782
10783 // ============================================================================
10784 // Procedure Call/Return Instructions
10785
10786 // Call Java Static Instruction
10787 // Note: If this code changes, the corresponding ret_addr_offset() and
10788 // compute_padding() functions will have to be adjusted.
10789 instruct CallStaticJavaDirect(method meth)
10790 %{
10791 match(CallStaticJava);
10792
10793 effect(USE meth);
10794
10795 ins_cost(BRANCH_COST);
10796
10797 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10798
10799 ins_encode(riscv_enc_java_static_call(meth),
10800 riscv_enc_call_epilog);
10801
10802 ins_pipe(pipe_class_call);
10803 ins_alignment(4);
10804 %}
10805
10806 // TO HERE
10807
10808 // Call Java Dynamic Instruction
10809 // Note: If this code changes, the corresponding ret_addr_offset() and
10810 // compute_padding() functions will have to be adjusted.
10811 instruct CallDynamicJavaDirect(method meth)
10812 %{
10813 match(CallDynamicJava);
10814
10815 effect(USE meth);
10816
10817 ins_cost(BRANCH_COST + ALU_COST * 5);
10818
10819 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10820
10821 ins_encode(riscv_enc_java_dynamic_call(meth),
10822 riscv_enc_call_epilog);
10823
10824 ins_pipe(pipe_class_call);
10825 ins_alignment(4);
10826 %}
10827
10828 // Call Runtime Instruction
10829
10830 instruct CallRuntimeDirect(method meth)
10831 %{
10832 match(CallRuntime);
10833
10834 effect(USE meth);
10835
10836 ins_cost(BRANCH_COST);
10837
10838 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10839
10840 ins_encode(riscv_enc_java_to_runtime(meth));
10841
10842 ins_pipe(pipe_class_call);
10843 ins_alignment(4);
10844 %}
10845
10846 // Call Runtime Instruction
10847
10848 instruct CallLeafDirect(method meth)
10849 %{
10850 match(CallLeaf);
10851
10852 effect(USE meth);
10853
10854 ins_cost(BRANCH_COST);
10855
10856 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10857
10858 ins_encode(riscv_enc_java_to_runtime(meth));
10859
10860 ins_pipe(pipe_class_call);
10861 ins_alignment(4);
10862 %}
10863
10864 // Call Runtime Instruction without safepoint and with vector arguments
10865
10866 instruct CallLeafDirectVector(method meth)
10867 %{
10868 match(CallLeafVector);
10869
10870 effect(USE meth);
10871
10872 ins_cost(BRANCH_COST);
10873
10874 format %{ "CALL, runtime leaf vector $meth" %}
10875
10876 ins_encode(riscv_enc_java_to_runtime(meth));
10877
10878 ins_pipe(pipe_class_call);
10879 ins_alignment(4);
10880 %}
10881
10882 // Call Runtime Instruction
10883
10884 instruct CallLeafNoFPDirect(method meth)
10885 %{
10886 match(CallLeafNoFP);
10887
10888 effect(USE meth);
10889
10890 ins_cost(BRANCH_COST);
10891
10892 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10893
10894 ins_encode(riscv_enc_java_to_runtime(meth));
10895
10896 ins_pipe(pipe_class_call);
10897 ins_alignment(4);
10898 %}
10899
10900 // ============================================================================
10901 // Partial Subtype Check
10902 //
10903 // superklass array for an instance of the superklass. Set a hidden
10904 // internal cache on a hit (cache is checked with exposed code in
10905 // gen_subtype_check()). Return zero for a hit. The encoding
10906 // ALSO sets flags.
10907
10908 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10909 %{
10910 predicate(!UseSecondarySupersTable);
10911 match(Set result (PartialSubtypeCheck sub super));
10912 effect(KILL tmp, KILL cr);
10913
10914 ins_cost(20 * DEFAULT_COST);
10915 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10916
10917 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10918
10919 opcode(0x1); // Force zero of result reg on hit
10920
10921 ins_pipe(pipe_class_memory);
10922 %}
10923
10924 // Two versions of partialSubtypeCheck, both used when we need to
10925 // search for a super class in the secondary supers array. The first
10926 // is used when we don't know _a priori_ the class being searched
10927 // for. The second, far more common, is used when we do know: this is
10928 // used for instanceof, checkcast, and any case where C2 can determine
10929 // it by constant propagation.
10930
10931 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10932 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10933 iRegP_R16 tmpR16, rFlagsReg cr)
10934 %{
10935 predicate(UseSecondarySupersTable);
10936 match(Set result (PartialSubtypeCheck sub super));
10937 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10938
10939 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10940 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10941
10942 ins_encode %{
10943 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10944 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10945 $tmpR16$$Register, nullptr /*L_success*/);
10946 %}
10947
10948 ins_pipe(pipe_class_memory);
10949 %}
10950
10951 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10952 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10953 %{
10954 predicate(UseSecondarySupersTable);
10955 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10956 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10957
10958 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10959 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10960
10961 ins_encode %{
10962 bool success = false;
10963 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10964 if (InlineSecondarySupersTest) {
10965 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10966 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10967 $tmpR16$$Register, super_klass_slot);
10968 } else {
10969 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10970 success = (call != nullptr);
10971 }
10972 if (!success) {
10973 ciEnv::current()->record_failure("CodeCache is full");
10974 return;
10975 }
10976 %}
10977
10978 ins_pipe(pipe_class_memory);
10979 %}
10980
10981 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10982 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10983 %{
10984 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10985 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10986 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10987
10988 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10989 ins_encode %{
10990 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10991 __ string_compare($str1$$Register, $str2$$Register,
10992 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10993 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10994 StrIntrinsicNode::UU);
10995 %}
10996 ins_pipe(pipe_class_memory);
10997 %}
10998
10999 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11000 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11001 %{
11002 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
11003 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11004 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11005
11006 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
11007 ins_encode %{
11008 __ string_compare($str1$$Register, $str2$$Register,
11009 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11010 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11011 StrIntrinsicNode::LL);
11012 %}
11013 ins_pipe(pipe_class_memory);
11014 %}
11015
11016 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11017 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
11018 %{
11019 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
11020 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11021 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11022
11023 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
11024 ins_encode %{
11025 __ string_compare($str1$$Register, $str2$$Register,
11026 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11027 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11028 StrIntrinsicNode::UL);
11029 %}
11030 ins_pipe(pipe_class_memory);
11031 %}
11032
11033 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11034 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
11035 rFlagsReg cr)
11036 %{
11037 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
11038 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11039 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11040
11041 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
11042 ins_encode %{
11043 __ string_compare($str1$$Register, $str2$$Register,
11044 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11045 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11046 StrIntrinsicNode::LU);
11047 %}
11048 ins_pipe(pipe_class_memory);
11049 %}
11050
11051 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11052 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11053 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11054 %{
11055 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11056 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11057 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11058 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11059
11060 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
11061 ins_encode %{
11062 __ string_indexof($str1$$Register, $str2$$Register,
11063 $cnt1$$Register, $cnt2$$Register,
11064 $tmp1$$Register, $tmp2$$Register,
11065 $tmp3$$Register, $tmp4$$Register,
11066 $tmp5$$Register, $tmp6$$Register,
11067 $result$$Register, StrIntrinsicNode::UU);
11068 %}
11069 ins_pipe(pipe_class_memory);
11070 %}
11071
11072 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11073 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11074 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11075 %{
11076 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11077 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11078 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11079 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11080
11081 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
11082 ins_encode %{
11083 __ string_indexof($str1$$Register, $str2$$Register,
11084 $cnt1$$Register, $cnt2$$Register,
11085 $tmp1$$Register, $tmp2$$Register,
11086 $tmp3$$Register, $tmp4$$Register,
11087 $tmp5$$Register, $tmp6$$Register,
11088 $result$$Register, StrIntrinsicNode::LL);
11089 %}
11090 ins_pipe(pipe_class_memory);
11091 %}
11092
11093 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
11094 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
11095 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
11096 %{
11097 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11098 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11099 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
11100 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
11101 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
11102
11103 ins_encode %{
11104 __ string_indexof($str1$$Register, $str2$$Register,
11105 $cnt1$$Register, $cnt2$$Register,
11106 $tmp1$$Register, $tmp2$$Register,
11107 $tmp3$$Register, $tmp4$$Register,
11108 $tmp5$$Register, $tmp6$$Register,
11109 $result$$Register, StrIntrinsicNode::UL);
11110 %}
11111 ins_pipe(pipe_class_memory);
11112 %}
11113
11114 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11115 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11116 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11117 %{
11118 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11119 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11120 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11121 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11122
11123 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
11124
11125 ins_encode %{
11126 int icnt2 = (int)$int_cnt2$$constant;
11127 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11128 $cnt1$$Register, zr,
11129 $tmp1$$Register, $tmp2$$Register,
11130 $tmp3$$Register, $tmp4$$Register,
11131 icnt2, $result$$Register, StrIntrinsicNode::UU);
11132 %}
11133 ins_pipe(pipe_class_memory);
11134 %}
11135
11136 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11137 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11138 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11139 %{
11140 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11141 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11142 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11143 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11144
11145 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
11146 ins_encode %{
11147 int icnt2 = (int)$int_cnt2$$constant;
11148 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11149 $cnt1$$Register, zr,
11150 $tmp1$$Register, $tmp2$$Register,
11151 $tmp3$$Register, $tmp4$$Register,
11152 icnt2, $result$$Register, StrIntrinsicNode::LL);
11153 %}
11154 ins_pipe(pipe_class_memory);
11155 %}
11156
11157 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
11158 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11159 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11160 %{
11161 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11162 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11163 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
11164 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11165
11166 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
11167 ins_encode %{
11168 int icnt2 = (int)$int_cnt2$$constant;
11169 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
11170 $cnt1$$Register, zr,
11171 $tmp1$$Register, $tmp2$$Register,
11172 $tmp3$$Register, $tmp4$$Register,
11173 icnt2, $result$$Register, StrIntrinsicNode::UL);
11174 %}
11175 ins_pipe(pipe_class_memory);
11176 %}
11177
11178 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11179 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11180 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11181 %{
11182 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11183 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11184 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11185 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11186
11187 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11188 ins_encode %{
11189 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11190 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11191 $tmp3$$Register, $tmp4$$Register, false /* isU */);
11192 %}
11193 ins_pipe(pipe_class_memory);
11194 %}
11195
11196
11197 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
11198 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
11199 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
11200 %{
11201 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11202 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11203 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
11204 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
11205
11206 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
11207 ins_encode %{
11208 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
11209 $result$$Register, $tmp1$$Register, $tmp2$$Register,
11210 $tmp3$$Register, $tmp4$$Register, true /* isL */);
11211 %}
11212 ins_pipe(pipe_class_memory);
11213 %}
11214
11215 // clearing of an array
11216 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
11217 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
11218 %{
11219 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
11220 predicate(UseBlockZeroing || !UseRVV);
11221 match(Set dummy (ClearArray cnt base));
11222 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
11223
11224 ins_cost(4 * DEFAULT_COST);
11225 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
11226
11227 ins_encode %{
11228 address tpc = __ zero_words($base$$Register, $cnt$$Register);
11229 if (tpc == nullptr) {
11230 ciEnv::current()->record_failure("CodeCache is full");
11231 return;
11232 }
11233 %}
11234
11235 ins_pipe(pipe_class_memory);
11236 %}
11237
11238 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
11239 %{
11240 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
11241 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
11242 match(Set dummy (ClearArray cnt base));
11243 effect(USE_KILL base, KILL cr);
11244
11245 ins_cost(4 * DEFAULT_COST);
11246 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
11247
11248 ins_encode %{
11249 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
11250 %}
11251
11252 ins_pipe(pipe_class_memory);
11253 %}
11254
11255 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
11256 iRegI_R10 result, rFlagsReg cr)
11257 %{
11258 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11259 match(Set result (StrEquals (Binary str1 str2) cnt));
11260 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
11261
11262 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
11263 ins_encode %{
11264 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
11265 __ string_equals($str1$$Register, $str2$$Register,
11266 $result$$Register, $cnt$$Register);
11267 %}
11268 ins_pipe(pipe_class_memory);
11269 %}
11270
11271 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11272 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11273 %{
11274 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11275 match(Set result (AryEq ary1 ary2));
11276 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11277
11278 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
11279 ins_encode %{
11280 __ arrays_equals($ary1$$Register, $ary2$$Register,
11281 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11282 $result$$Register, 1);
11283 %}
11284 ins_pipe(pipe_class_memory);
11285 %}
11286
11287 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
11288 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
11289 %{
11290 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11291 match(Set result (AryEq ary1 ary2));
11292 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
11293
11294 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
11295 ins_encode %{
11296 __ arrays_equals($ary1$$Register, $ary2$$Register,
11297 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11298 $result$$Register, 2);
11299 %}
11300 ins_pipe(pipe_class_memory);
11301 %}
11302
11303 // fast ArraysSupport.vectorizedHashCode
11304 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
11305 iRegLNoSp tmp1, iRegLNoSp tmp2,
11306 iRegLNoSp tmp3, iRegLNoSp tmp4,
11307 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
11308 %{
11309 predicate(!UseRVV);
11310 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
11311 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
11312 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
11313
11314 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
11315 ins_encode %{
11316 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
11317 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11318 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
11319 (BasicType)$basic_type$$constant);
11320 %}
11321 ins_pipe(pipe_class_memory);
11322 %}
11323
11324 // ============================================================================
11325 // Safepoint Instructions
11326
11327 instruct safePoint(iRegP poll)
11328 %{
11329 match(SafePoint poll);
11330
11331 ins_cost(2 * LOAD_COST);
11332 format %{
11333 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
11334 %}
11335 ins_encode %{
11336 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
11337 %}
11338 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
11339 %}
11340
11341 // ============================================================================
11342 // This name is KNOWN by the ADLC and cannot be changed.
11343 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11344 // for this guy.
11345 instruct tlsLoadP(javaThread_RegP dst)
11346 %{
11347 match(Set dst (ThreadLocal));
11348
11349 ins_cost(0);
11350
11351 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
11352
11353 size(0);
11354
11355 ins_encode( /*empty*/ );
11356
11357 ins_pipe(pipe_class_empty);
11358 %}
11359
11360 // inlined locking and unlocking
11361 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11362 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
11363 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
11364 %{
11365 match(Set cr (FastLock object box));
11366 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
11367
11368 ins_cost(10 * DEFAULT_COST);
11369 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
11370
11371 ins_encode %{
11372 __ fast_lock($object$$Register, $box$$Register,
11373 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11374 %}
11375
11376 ins_pipe(pipe_serial);
11377 %}
11378
11379 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
11380 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box,
11381 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
11382 %{
11383 match(Set cr (FastUnlock object box));
11384 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11385
11386 ins_cost(10 * DEFAULT_COST);
11387 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlock" %}
11388
11389 ins_encode %{
11390 __ fast_unlock($object$$Register, $box$$Register,
11391 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
11392 %}
11393
11394 ins_pipe(pipe_serial);
11395 %}
11396
11397 // Tail Call; Jump from runtime stub to Java code.
11398 // Also known as an 'interprocedural jump'.
11399 // Target of jump will eventually return to caller.
11400 // TailJump below removes the return address.
11401 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
11402 // emitted just above the TailCall which has reset fp to the caller state.
11403 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
11404 %{
11405 match(TailCall jump_target method_oop);
11406
11407 ins_cost(BRANCH_COST);
11408
11409 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
11410
11411 ins_encode(riscv_enc_tail_call(jump_target));
11412
11413 ins_pipe(pipe_class_call);
11414 %}
11415
11416 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
11417 %{
11418 match(TailJump jump_target ex_oop);
11419
11420 ins_cost(ALU_COST + BRANCH_COST);
11421
11422 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
11423
11424 ins_encode(riscv_enc_tail_jmp(jump_target));
11425
11426 ins_pipe(pipe_class_call);
11427 %}
11428
11429 // Forward exception.
11430 instruct ForwardExceptionjmp()
11431 %{
11432 match(ForwardException);
11433
11434 ins_cost(BRANCH_COST);
11435
11436 format %{ "j forward_exception_stub\t#@ForwardException" %}
11437
11438 ins_encode %{
11439 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
11440 %}
11441
11442 ins_pipe(pipe_class_call);
11443 %}
11444
11445 // Create exception oop: created by stack-crawling runtime code.
11446 // Created exception is now available to this handler, and is setup
11447 // just prior to jumping to this handler. No code emitted.
11448 instruct CreateException(iRegP_R10 ex_oop)
11449 %{
11450 match(Set ex_oop (CreateEx));
11451
11452 ins_cost(0);
11453 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
11454
11455 size(0);
11456
11457 ins_encode( /*empty*/ );
11458
11459 ins_pipe(pipe_class_empty);
11460 %}
11461
11462 // Rethrow exception: The exception oop will come in the first
11463 // argument position. Then JUMP (not call) to the rethrow stub code.
11464 instruct RethrowException()
11465 %{
11466 match(Rethrow);
11467
11468 ins_cost(BRANCH_COST);
11469
11470 format %{ "j rethrow_stub\t#@RethrowException" %}
11471
11472 ins_encode(riscv_enc_rethrow());
11473
11474 ins_pipe(pipe_class_call);
11475 %}
11476
11477 // Return Instruction
11478 // epilog node loads ret address into ra as part of frame pop
11479 instruct Ret()
11480 %{
11481 match(Return);
11482
11483 ins_cost(BRANCH_COST);
11484 format %{ "ret\t// return register, #@Ret" %}
11485
11486 ins_encode(riscv_enc_ret());
11487
11488 ins_pipe(pipe_branch);
11489 %}
11490
11491 // Die now.
11492 instruct ShouldNotReachHere() %{
11493 match(Halt);
11494
11495 ins_cost(BRANCH_COST);
11496
11497 format %{ "#@ShouldNotReachHere" %}
11498
11499 ins_encode %{
11500 if (is_reachable()) {
11501 const char* str = __ code_string(_halt_reason);
11502 __ stop(str);
11503 }
11504 %}
11505
11506 ins_pipe(pipe_class_default);
11507 %}
11508
11509
11510 //----------PEEPHOLE RULES-----------------------------------------------------
11511 // These must follow all instruction definitions as they use the names
11512 // defined in the instructions definitions.
11513 //
11514 // peepmatch ( root_instr_name [preceding_instruction]* );
11515 //
11516 // peepconstraint %{
11517 // (instruction_number.operand_name relational_op instruction_number.operand_name
11518 // [, ...] );
11519 // // instruction numbers are zero-based using left to right order in peepmatch
11520 //
11521 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11522 // // provide an instruction_number.operand_name for each operand that appears
11523 // // in the replacement instruction's match rule
11524 //
11525 // ---------VM FLAGS---------------------------------------------------------
11526 //
11527 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11528 //
11529 // Each peephole rule is given an identifying number starting with zero and
11530 // increasing by one in the order seen by the parser. An individual peephole
11531 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11532 // on the command-line.
11533 //
11534 // ---------CURRENT LIMITATIONS----------------------------------------------
11535 //
11536 // Only match adjacent instructions in same basic block
11537 // Only equality constraints
11538 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11539 // Only one replacement instruction
11540 //
11541 //----------SMARTSPILL RULES---------------------------------------------------
11542 // These must follow all instruction definitions as they use the names
11543 // defined in the instructions definitions.
11544
11545 // Local Variables:
11546 // mode: c++
11547 // End: