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__ leave();
__ bind(L);
}
static void gen_c2i_adapter(MacroAssembler *masm,
- int total_args_passed,
int comp_args_on_stack,
- const BasicType *sig_bt,
+ const GrowableArray<SigEntry>* sig,
const VMRegPair *regs,
Label& skip_fixup) {
// Before we get into the guts of the C2I adapter, see if we should be here
// at all. We've come from compiled code and are attempting to jump to the
// interpreter, which means the caller made a static call to get here
int words_pushed = 0;
// Since all args are passed on the stack, total_args_passed *
// Interpreter::stackElementSize is the space we need.
+ int total_args_passed = sig->length();
int extraspace = total_args_passed * Interpreter::stackElementSize;
__ mv(x19_sender_sp, sp);
// stack is aligned, keep it that way
__ sub(sp, sp, extraspace);
}
// Now write the args into the outgoing interpreter space
for (int i = 0; i < total_args_passed; i++) {
- if (sig_bt[i] == T_VOID) {
- assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
+ BasicType bt = sig->at(i)._bt;
+ if (bt == T_VOID) {
+ assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
continue;
}
// offset to start parameters
int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
} else {
__ ld(t0, Address(sp, ld_off), /*temp register*/esp);
// Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
// T_DOUBLE and T_LONG use two slots in the interpreter
- if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
+ if (bt == T_LONG || bt == T_DOUBLE) {
// ld_off == LSW, ld_off+wordSize == MSW
// st_off == MSW, next_off == LSW
__ sd(t0, Address(sp, next_off), /*temp register*/esp);
#ifdef ASSERT
// Overwrite the unused slot with known junk
// must be only an int (or less ) so move only 32bits to slot
__ sd(r, Address(sp, st_off));
} else {
// Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
// T_DOUBLE and T_LONG use two slots in the interpreter
- if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
+ if (bt == T_LONG || bt == T_DOUBLE) {
// long/double in gpr
#ifdef ASSERT
// Overwrite the unused slot with known junk
__ mv(t0, 0xdeadffffdeadaaabul);
__ sd(t0, Address(sp, st_off), /*temp register*/esp);
__ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
__ jr(t1);
}
void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
- int total_args_passed,
int comp_args_on_stack,
- const BasicType *sig_bt,
+ const GrowableArray<SigEntry>* sig,
const VMRegPair *regs) {
// Note: x19_sender_sp contains the senderSP on entry. We must
// preserve it since we may do a i2c -> c2i transition if we lose a
// race where compiled code goes non-entrant while we get args
// ready.
__ bind(no_alternative_target);
}
#endif // INCLUDE_JVMCI
// Now generate the shuffle code.
+ int total_args_passed = sig->length();
for (int i = 0; i < total_args_passed; i++) {
- if (sig_bt[i] == T_VOID) {
- assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
+ BasicType bt = sig->at(i)._bt;
+ if (bt == T_VOID) {
+ assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
continue;
}
// Pick up 0, 1 or 2 words from SP+offset.
//
// Interpreter local[n] == MSW, local[n+1] == LSW however locals
// are accessed as negative so LSW is at LOW address
// ld_off is MSW so get LSW
- const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
+ const int offset = (bt == T_LONG || bt == T_DOUBLE) ?
next_off : ld_off;
__ ld(t0, Address(esp, offset));
// st_off is LSW (i.e. reg.first())
__ sd(t0, Address(sp, st_off), /*temp register*/t2);
}
// T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
// two slots but only uses one for thr T_LONG or T_DOUBLE case
// So we must adjust where to pick up the data to match the
// interpreter.
- const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
+ const int offset = (bt == T_LONG || bt == T_DOUBLE) ?
next_off : ld_off;
// this can be a misaligned move
__ ld(r, Address(esp, offset));
} else {
__ jr(t1);
}
// ---------------------------------------------------------------
- void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
- int total_args_passed,
+ void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
int comp_args_on_stack,
- const BasicType *sig_bt,
- const VMRegPair *regs,
- address entry_address[AdapterBlob::ENTRY_COUNT]) {
+ const GrowableArray<SigEntry>* sig,
+ const VMRegPair* regs,
+ const GrowableArray<SigEntry>* sig_cc,
+ const VMRegPair* regs_cc,
+ const GrowableArray<SigEntry>* sig_cc_ro,
+ const VMRegPair* regs_cc_ro,
+ address entry_address[AdapterBlob::ENTRY_COUNT],
+ AdapterBlob*& new_adapter,
+ bool allocate_code_blob) {
entry_address[AdapterBlob::I2C] = __ pc();
- gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
+ gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
entry_address[AdapterBlob::C2I_Unverified] = __ pc();
Label skip_fixup;
const Register receiver = j_rarg0;
entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
bs->c2i_entry_barrier(masm);
- gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
+ gen_c2i_adapter(masm, comp_args_on_stack, sig, regs, skip_fixup);
return;
}
int SharedRuntime::vector_calling_convention(VMRegPair *regs,
uint num_bits,
oop_maps, false);
return stub;
}
#endif // INCLUDE_JFR
+
+ const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j;
+ const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
+
+ int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
+ Unimplemented();
+ return 0;
+ }
+
+ BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
+ Unimplemented();
+ return nullptr;
+ }
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