src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp

@@ -1,7 +1,7 @@
  /*
-  * Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
+  * Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
   * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it

@@ -1421,11 +1421,11 @@
  }
  
  //
  // Generic interpreted method entry to (asm) interpreter
  //
- address TemplateInterpreterGenerator::generate_normal_entry(bool synchronized) {
+ address TemplateInterpreterGenerator::generate_normal_entry(bool synchronized, bool object_init) {
  
    // determine code generation flags
    const bool inc_counter  = UseCompiler || CountCompiledCalls;
  
    // t0: sender sp

@@ -1534,10 +1534,16 @@
      __ load_unsigned_short(x10, access_flags);
      __ verify_access_flags(x10, JVM_ACC_SYNCHRONIZED, "method needs synchronization");
  #endif
    }
  
+   // Issue a StoreStore barrier on entry to Object_init if the
+   // class has strict field fields.  Be lazy, always do it.
+   if (object_init) {
+     __ membar(MacroAssembler::StoreStore);
+   }
+ 
    // start execution
    __ verify_frame_setup();
  
    // jvmti support
    __ notify_method_entry();