1 /*
2 * Copyright (c) 2016, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_s390.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/safepointMechanism.inline.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "utilities/macros.hpp"
44 #include "utilities/powerOfTwo.hpp"
45 #include "vmreg_s390.inline.hpp"
46
47 #define __ _masm->
48
49 #ifndef PRODUCT
50 #undef __
51 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
52 #endif
53
54 //------------------------------------------------------------
55
56 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
57 // Not used on ZARCH_64
58 ShouldNotCallThis();
59 return false;
60 }
61
62 LIR_Opr LIR_Assembler::receiverOpr() {
63 return FrameMap::Z_R2_oop_opr;
64 }
65
66 LIR_Opr LIR_Assembler::osrBufferPointer() {
67 return FrameMap::Z_R2_opr;
68 }
69
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74 // Inline cache check: done before the frame is built.
75 // The inline cached class is in Z_inline_cache(Z_R9).
76 // We fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to the slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = Z_R1_scratch;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
92 __ z_br(klass);
93
94 __ bind(L_skip_barrier);
95 }
96
97 void LIR_Assembler::osr_entry() {
98 // On-stack-replacement entry sequence (interpreter frame layout described in frame_s390.hpp):
99 //
100 // 1. Create a new compiled activation.
101 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
102 // at the osr_bci; it is not initialized.
103 // 3. Jump to the continuation address in compiled code to resume execution.
104
105 // OSR entry point
106 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
107 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
108 ValueStack* entry_state = osr_entry->end()->state();
109 int number_of_locks = entry_state->locks_size();
110
111 // Create a frame for the compiled activation.
112 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
113
114 // OSR buffer is
115 //
116 // locals[nlocals-1..0]
117 // monitors[number_of_locks-1..0]
118 //
119 // Locals is a direct copy of the interpreter frame so in the osr buffer
120 // the first slot in the local array is the last local from the interpreter
121 // and the last slot is local[0] (receiver) from the interpreter
122 //
123 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
124 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
125 // in the interpreter frame (the method lock if a sync method)
126
127 // Initialize monitors in the compiled activation.
128 // I0: pointer to osr buffer
129 //
130 // All other registers are dead at this point and the locals will be
131 // copied into place by code emitted in the IR.
132
133 Register OSR_buf = osrBufferPointer()->as_register();
134 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
135 int monitor_offset = BytesPerWord * method()->max_locals() +
136 (2 * BytesPerWord) * (number_of_locks - 1);
137 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
138 // the OSR buffer using 2 word entries: first the lock and then
139 // the oop.
140 for (int i = 0; i < number_of_locks; i++) {
141 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
142 // Verify the interpreter's monitor has a non-null object.
143 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is null", __LINE__);
144 // Copy the lock field into the compiled activation.
145 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
146 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
147 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
148 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
149 }
150 }
151 }
152
153 // --------------------------------------------------------------------------------------------
154
155 address LIR_Assembler::emit_call_c(address a) {
156 __ align_call_far_patchable(__ pc());
157 address call_addr = __ call_c_opt(a);
158 if (call_addr == nullptr) {
159 bailout("const section overflow");
160 }
161 return call_addr;
162 }
163
164 int LIR_Assembler::emit_exception_handler() {
165 // Generate code for exception handler.
166 address handler_base = __ start_a_stub(exception_handler_size());
167 if (handler_base == nullptr) {
168 // Not enough space left for the handler.
169 bailout("exception handler overflow");
170 return -1;
171 }
172
173 int offset = code_offset();
174
175 address a = Runtime1::entry_for (C1StubId::handle_exception_from_callee_id);
176 address call_addr = emit_call_c(a);
177 CHECK_BAILOUT_(-1);
178 __ should_not_reach_here();
179 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
180 __ end_a_stub();
181
182 return offset;
183 }
184
185 // Emit the code to remove the frame from the stack in the exception
186 // unwind path.
187 int LIR_Assembler::emit_unwind_handler() {
188 #ifndef PRODUCT
189 if (CommentedAssembly) {
190 _masm->block_comment("Unwind handler");
191 }
192 #endif
193
194 int offset = code_offset();
195 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
196 Register Rtmp1 = Z_R11;
197 Register Rtmp2 = Z_R12;
198
199 // Fetch the exception from TLS and clear out exception related thread state.
200 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
201 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
202 __ z_lg(Z_EXC_OOP, exc_oop_addr);
203 __ clear_mem(exc_oop_addr, sizeof(oop));
204 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
205
206 __ bind(_unwind_handler_entry);
207 __ verify_not_null_oop(Z_EXC_OOP);
208 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
209 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
210 }
211
212 // Perform needed unlocking.
213 MonitorExitStub* stub = nullptr;
214 if (method()->is_synchronized()) {
215 // C1StubId::monitorexit_id expects lock address in Z_R1_scratch.
216 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
217 monitor_address(0, lock);
218 stub = new MonitorExitStub(lock, true, 0);
219 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
220 __ bind(*stub->continuation());
221 }
222
223 if (compilation()->env()->dtrace_method_probes()) {
224 ShouldNotReachHere(); // Not supported.
225 #if 0
226 __ mov(rdi, r15_thread);
227 __ mov_metadata(rsi, method()->constant_encoding());
228 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
229 #endif
230 }
231
232 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
233 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
234 }
235
236 // Remove the activation and dispatch to the unwind handler.
237 __ pop_frame();
238 __ z_lg(Z_EXC_PC, _z_common_abi(return_pc), Z_SP);
239
240 // Z_EXC_OOP: exception oop
241 // Z_EXC_PC: exception pc
242
243 // Dispatch to the unwind logic.
244 __ load_const_optimized(Z_R5, Runtime1::entry_for (C1StubId::unwind_exception_id));
245 __ z_br(Z_R5);
246
247 // Emit the slow path assembly.
248 if (stub != nullptr) {
249 stub->emit_code(this);
250 }
251
252 return offset;
253 }
254
255 int LIR_Assembler::emit_deopt_handler() {
256 // Generate code for exception handler.
257 address handler_base = __ start_a_stub(deopt_handler_size());
258 if (handler_base == nullptr) {
259 // Not enough space left for the handler.
260 bailout("deopt handler overflow");
261 return -1;
262 } int offset = code_offset();
263 // Size must be constant (see HandlerImpl::emit_deopt_handler).
264 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
265 __ call(Z_R1_scratch);
266 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
267 __ end_a_stub();
268
269 return offset;
270 }
271
272 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
273 if (o == nullptr) {
274 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
275 } else {
276 AddressLiteral a = __ allocate_oop_address(o);
277 bool success = __ load_oop_from_toc(reg, a, reg);
278 if (!success) {
279 bailout("const section overflow");
280 }
281 }
282 }
283
284 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
285 // Allocate a new index in table to hold the object once it's been patched.
286 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
287 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
288
289 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
290 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
291 // The null will be dynamically patched later so the sequence to
292 // load the address literal must not be optimized.
293 __ load_const(reg, addrlit);
294
295 patching_epilog(patch, lir_patch_normal, reg, info);
296 }
297
298 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
299 bool success = __ set_metadata_constant(md, reg);
300 if (!success) {
301 bailout("const section overflow");
302 return;
303 }
304 }
305
306 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
307 // Allocate a new index in table to hold the klass once it's been patched.
308 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
309 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
310 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
311 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
312 // The null will be dynamically patched later so the sequence to
313 // load the address literal must not be optimized.
314 __ load_const(reg, addrlit);
315
316 patching_epilog(patch, lir_patch_normal, reg, info);
317 }
318
319 void LIR_Assembler::emit_op3(LIR_Op3* op) {
320 switch (op->code()) {
321 case lir_idiv:
322 case lir_irem:
323 arithmetic_idiv(op->code(),
324 op->in_opr1(),
325 op->in_opr2(),
326 op->in_opr3(),
327 op->result_opr(),
328 op->info());
329 break;
330 case lir_fmad: {
331 const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
332 opr2 = op->in_opr2()->as_double_reg(),
333 opr3 = op->in_opr3()->as_double_reg(),
334 res = op->result_opr()->as_double_reg();
335 __ z_madbr(opr3, opr1, opr2);
336 if (res != opr3) { __ z_ldr(res, opr3); }
337 } break;
338 case lir_fmaf: {
339 const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
340 opr2 = op->in_opr2()->as_float_reg(),
341 opr3 = op->in_opr3()->as_float_reg(),
342 res = op->result_opr()->as_float_reg();
343 __ z_maebr(opr3, opr1, opr2);
344 if (res != opr3) { __ z_ler(res, opr3); }
345 } break;
346 default: ShouldNotReachHere(); break;
347 }
348 }
349
350
351 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
352 #ifdef ASSERT
353 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
354 if (op->block() != nullptr) { _branch_target_blocks.append(op->block()); }
355 if (op->ublock() != nullptr) { _branch_target_blocks.append(op->ublock()); }
356 #endif
357
358 if (op->cond() == lir_cond_always) {
359 if (op->info() != nullptr) { add_debug_info_for_branch(op->info()); }
360 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
361 } else {
362 Assembler::branch_condition acond = Assembler::bcondZero;
363 if (op->code() == lir_cond_float_branch) {
364 assert(op->ublock() != nullptr, "must have unordered successor");
365 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
366 }
367 switch (op->cond()) {
368 case lir_cond_equal: acond = Assembler::bcondEqual; break;
369 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
370 case lir_cond_less: acond = Assembler::bcondLow; break;
371 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
372 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
373 case lir_cond_greater: acond = Assembler::bcondHigh; break;
374 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
375 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
376 default: ShouldNotReachHere();
377 }
378 __ branch_optimized(acond,*(op->label()));
379 }
380 }
381
382
383 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
384 LIR_Opr src = op->in_opr();
385 LIR_Opr dest = op->result_opr();
386
387 switch (op->bytecode()) {
388 case Bytecodes::_i2l:
389 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
390 break;
391
392 case Bytecodes::_l2i:
393 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
394 break;
395
396 case Bytecodes::_i2b:
397 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
398 break;
399
400 case Bytecodes::_i2c:
401 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
402 break;
403
404 case Bytecodes::_i2s:
405 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
406 break;
407
408 case Bytecodes::_f2d:
409 assert(dest->is_double_fpu(), "check");
410 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
411 break;
412
413 case Bytecodes::_d2f:
414 assert(dest->is_single_fpu(), "check");
415 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
416 break;
417
418 case Bytecodes::_i2f:
419 __ z_cefbr(dest->as_float_reg(), src->as_register());
420 break;
421
422 case Bytecodes::_i2d:
423 __ z_cdfbr(dest->as_double_reg(), src->as_register());
424 break;
425
426 case Bytecodes::_l2f:
427 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
428 break;
429 case Bytecodes::_l2d:
430 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
431 break;
432
433 case Bytecodes::_f2i:
434 case Bytecodes::_f2l: {
435 Label done;
436 FloatRegister Rsrc = src->as_float_reg();
437 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
438 __ clear_reg(Rdst, true, false);
439 __ z_cebr(Rsrc, Rsrc);
440 __ z_brno(done); // NaN -> 0
441 if (op->bytecode() == Bytecodes::_f2i) {
442 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
443 } else { // op->bytecode() == Bytecodes::_f2l
444 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
445 }
446 __ bind(done);
447 }
448 break;
449
450 case Bytecodes::_d2i:
451 case Bytecodes::_d2l: {
452 Label done;
453 FloatRegister Rsrc = src->as_double_reg();
454 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
455 __ clear_reg(Rdst, true, false); // Don't set CC.
456 __ z_cdbr(Rsrc, Rsrc);
457 __ z_brno(done); // NaN -> 0
458 if (op->bytecode() == Bytecodes::_d2i) {
459 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
460 } else { // Bytecodes::_d2l
461 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
462 }
463 __ bind(done);
464 }
465 break;
466
467 default: ShouldNotReachHere();
468 }
469 }
470
471 void LIR_Assembler::align_call(LIR_Code code) {
472 // End of call instruction must be 4 byte aligned.
473 int offset = __ offset();
474 switch (code) {
475 case lir_icvirtual_call:
476 offset += MacroAssembler::load_const_from_toc_size();
477 // no break
478 case lir_static_call:
479 case lir_optvirtual_call:
480 case lir_dynamic_call:
481 offset += NativeCall::call_far_pcrelative_displacement_offset;
482 break;
483 default: ShouldNotReachHere();
484 }
485 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
486 __ nop();
487 }
488 }
489
490 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
491 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
492 "must be aligned (offset=%d)", __ offset());
493 assert(rtype == relocInfo::none ||
494 rtype == relocInfo::opt_virtual_call_type ||
495 rtype == relocInfo::static_call_type, "unexpected rtype");
496 // Prepend each BRASL with a nop.
497 __ relocate(rtype);
498 __ z_nop();
499 __ z_brasl(Z_R14, op->addr());
500 add_call_info(code_offset(), op->info());
501 }
502
503 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
504 address virtual_call_oop_addr = nullptr;
505 AddressLiteral empty_ic((address) Universe::non_oop_word());
506 virtual_call_oop_addr = __ pc();
507 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
508 if (!success) {
509 bailout("const section overflow");
510 return;
511 }
512
513 // CALL to fixup routine. Fixup routine uses ScopeDesc info
514 // to determine who we intended to call.
515 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
516 call(op, relocInfo::none);
517 }
518
519 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
520 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
521 }
522
523 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
524 assert(src->is_constant(), "should not call otherwise");
525 assert(dest->is_stack(), "should not call otherwise");
526 LIR_Const* c = src->as_constant_ptr();
527
528 unsigned int lmem = 0;
529 unsigned int lcon = 0;
530 int64_t cbits = 0;
531 Address dest_addr;
532 switch (c->type()) {
533 case T_INT: // fall through
534 case T_FLOAT:
535 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
536 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
537 break;
538
539 case T_ADDRESS:
540 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
541 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
542 break;
543
544 case T_OBJECT:
545 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
546 if (c->as_jobject() == nullptr) {
547 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
548 } else {
549 jobject2reg(c->as_jobject(), Z_R1_scratch);
550 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
551 }
552 return;
553
554 case T_LONG: // fall through
555 case T_DOUBLE:
556 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
557 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
558 break;
559
560 default:
561 ShouldNotReachHere();
562 }
563
564 __ store_const(dest_addr, cbits, lmem, lcon);
565 }
566
567 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
568 assert(src->is_constant(), "should not call otherwise");
569 assert(dest->is_address(), "should not call otherwise");
570
571 LIR_Const* c = src->as_constant_ptr();
572 Address addr = as_Address(dest->as_address_ptr());
573
574 int store_offset = -1;
575
576 if (dest->as_address_ptr()->index()->is_valid()) {
577 switch (type) {
578 case T_INT: // fall through
579 case T_FLOAT:
580 __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
581 store_offset = __ offset();
582 if (Immediate::is_uimm12(addr.disp())) {
583 __ z_st(Z_R0_scratch, addr);
584 } else {
585 __ z_sty(Z_R0_scratch, addr);
586 }
587 break;
588
589 case T_ADDRESS:
590 __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
591 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
592 break;
593
594 case T_OBJECT: // fall through
595 case T_ARRAY:
596 if (c->as_jobject() == nullptr) {
597 if (UseCompressedOops && !wide) {
598 __ clear_reg(Z_R1_scratch, false);
599 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
600 } else {
601 __ clear_reg(Z_R1_scratch, true);
602 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
603 }
604 } else {
605 jobject2reg(c->as_jobject(), Z_R1_scratch);
606 if (UseCompressedOops && !wide) {
607 __ encode_heap_oop(Z_R1_scratch);
608 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
609 } else {
610 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
611 }
612 }
613 assert(store_offset >= 0, "check");
614 break;
615
616 case T_LONG: // fall through
617 case T_DOUBLE:
618 __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
619 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
620 break;
621
622 case T_BOOLEAN: // fall through
623 case T_BYTE:
624 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
625 store_offset = __ offset();
626 if (Immediate::is_uimm12(addr.disp())) {
627 __ z_stc(Z_R0_scratch, addr);
628 } else {
629 __ z_stcy(Z_R0_scratch, addr);
630 }
631 break;
632
633 case T_CHAR: // fall through
634 case T_SHORT:
635 __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
636 store_offset = __ offset();
637 if (Immediate::is_uimm12(addr.disp())) {
638 __ z_sth(Z_R0_scratch, addr);
639 } else {
640 __ z_sthy(Z_R0_scratch, addr);
641 }
642 break;
643
644 default:
645 ShouldNotReachHere();
646 }
647
648 } else { // no index
649
650 unsigned int lmem = 0;
651 unsigned int lcon = 0;
652 int64_t cbits = 0;
653
654 switch (type) {
655 case T_INT: // fall through
656 case T_FLOAT:
657 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
658 break;
659
660 case T_ADDRESS:
661 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
662 break;
663
664 case T_OBJECT: // fall through
665 case T_ARRAY:
666 if (c->as_jobject() == nullptr) {
667 if (UseCompressedOops && !wide) {
668 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
669 } else {
670 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
671 }
672 } else {
673 jobject2reg(c->as_jobject(), Z_R1_scratch);
674 if (UseCompressedOops && !wide) {
675 __ encode_heap_oop(Z_R1_scratch);
676 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
677 } else {
678 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
679 }
680 }
681 assert(store_offset >= 0, "check");
682 break;
683
684 case T_LONG: // fall through
685 case T_DOUBLE:
686 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
687 break;
688
689 case T_BOOLEAN: // fall through
690 case T_BYTE:
691 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
692 break;
693
694 case T_CHAR: // fall through
695 case T_SHORT:
696 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
697 break;
698
699 default:
700 ShouldNotReachHere();
701 }
702
703 if (store_offset == -1) {
704 store_offset = __ store_const(addr, cbits, lmem, lcon);
705 assert(store_offset >= 0, "check");
706 }
707 }
708
709 if (info != nullptr) {
710 add_debug_info_for_null_check(store_offset, info);
711 }
712 }
713
714 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
715 assert(src->is_constant(), "should not call otherwise");
716 assert(dest->is_register(), "should not call otherwise");
717 LIR_Const* c = src->as_constant_ptr();
718
719 switch (c->type()) {
720 case T_INT: {
721 assert(patch_code == lir_patch_none, "no patching handled here");
722 __ load_const_optimized(dest->as_register(), c->as_jint());
723 break;
724 }
725
726 case T_ADDRESS: {
727 assert(patch_code == lir_patch_none, "no patching handled here");
728 __ load_const_optimized(dest->as_register(), c->as_jint());
729 break;
730 }
731
732 case T_LONG: {
733 assert(patch_code == lir_patch_none, "no patching handled here");
734 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
735 break;
736 }
737
738 case T_OBJECT: {
739 if (patch_code != lir_patch_none) {
740 jobject2reg_with_patching(dest->as_register(), info);
741 } else {
742 jobject2reg(c->as_jobject(), dest->as_register());
743 }
744 break;
745 }
746
747 case T_METADATA: {
748 if (patch_code != lir_patch_none) {
749 klass2reg_with_patching(dest->as_register(), info);
750 } else {
751 metadata2reg(c->as_metadata(), dest->as_register());
752 }
753 break;
754 }
755
756 case T_FLOAT: {
757 Register toc_reg = Z_R1_scratch;
758 __ load_toc(toc_reg);
759 address const_addr = __ float_constant(c->as_jfloat());
760 if (const_addr == nullptr) {
761 bailout("const section overflow");
762 break;
763 }
764 int displ = const_addr - _masm->code()->consts()->start();
765 if (dest->is_single_fpu()) {
766 __ z_ley(dest->as_float_reg(), displ, toc_reg);
767 } else {
768 assert(dest->is_single_cpu(), "Must be a cpu register.");
769 __ z_ly(dest->as_register(), displ, toc_reg);
770 }
771 }
772 break;
773
774 case T_DOUBLE: {
775 Register toc_reg = Z_R1_scratch;
776 __ load_toc(toc_reg);
777 address const_addr = __ double_constant(c->as_jdouble());
778 if (const_addr == nullptr) {
779 bailout("const section overflow");
780 break;
781 }
782 int displ = const_addr - _masm->code()->consts()->start();
783 if (dest->is_double_fpu()) {
784 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
785 } else {
786 assert(dest->is_double_cpu(), "Must be a long register.");
787 __ z_lg(dest->as_register_lo(), displ, toc_reg);
788 }
789 }
790 break;
791
792 default:
793 ShouldNotReachHere();
794 }
795 }
796
797 Address LIR_Assembler::as_Address(LIR_Address* addr) {
798 if (addr->base()->is_illegal()) {
799 Unimplemented();
800 }
801
802 Register base = addr->base()->as_pointer_register();
803
804 if (addr->index()->is_illegal()) {
805 return Address(base, addr->disp());
806 } else if (addr->index()->is_cpu_register()) {
807 Register index = addr->index()->as_pointer_register();
808 return Address(base, index, addr->disp());
809 } else if (addr->index()->is_constant()) {
810 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
811 return Address(base, addr_offset);
812 } else {
813 ShouldNotReachHere();
814 return Address();
815 }
816 }
817
818 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
819 switch (type) {
820 case T_INT:
821 case T_FLOAT: {
822 Register tmp = Z_R1_scratch;
823 Address from = frame_map()->address_for_slot(src->single_stack_ix());
824 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
825 __ mem2reg_opt(tmp, from, false);
826 __ reg2mem_opt(tmp, to, false);
827 break;
828 }
829 case T_ADDRESS:
830 case T_OBJECT: {
831 Register tmp = Z_R1_scratch;
832 Address from = frame_map()->address_for_slot(src->single_stack_ix());
833 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
834 __ mem2reg_opt(tmp, from, true);
835 __ reg2mem_opt(tmp, to, true);
836 break;
837 }
838 case T_LONG:
839 case T_DOUBLE: {
840 Register tmp = Z_R1_scratch;
841 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
842 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
843 __ mem2reg_opt(tmp, from, true);
844 __ reg2mem_opt(tmp, to, true);
845 break;
846 }
847
848 default:
849 ShouldNotReachHere();
850 }
851 }
852
853 // 4-byte accesses only! Don't use it to access 8 bytes!
854 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
855 ShouldNotCallThis();
856 return Address(); // unused
857 }
858
859 // 4-byte accesses only! Don't use it to access 8 bytes!
860 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
861 ShouldNotCallThis();
862 return Address(); // unused
863 }
864
865 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
866 CodeEmitInfo* info, bool wide) {
867
868 assert(type != T_METADATA, "load of metadata ptr not supported");
869 LIR_Address* addr = src_opr->as_address_ptr();
870 LIR_Opr to_reg = dest;
871
872 Register src = addr->base()->as_pointer_register();
873 Register disp_reg = Z_R0;
874 int disp_value = addr->disp();
875 bool needs_patching = (patch_code != lir_patch_none);
876
877 if (addr->base()->type() == T_OBJECT) {
878 __ verify_oop(src, FILE_AND_LINE);
879 }
880
881 PatchingStub* patch = nullptr;
882 if (needs_patching) {
883 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
884 assert(!to_reg->is_double_cpu() ||
885 patch_code == lir_patch_none ||
886 patch_code == lir_patch_normal, "patching doesn't match register");
887 }
888
889 if (addr->index()->is_illegal()) {
890 if (!Immediate::is_simm20(disp_value)) {
891 if (needs_patching) {
892 __ load_const(Z_R1_scratch, (intptr_t)0);
893 } else {
894 __ load_const_optimized(Z_R1_scratch, disp_value);
895 }
896 disp_reg = Z_R1_scratch;
897 disp_value = 0;
898 }
899 } else {
900 if (!Immediate::is_simm20(disp_value)) {
901 __ load_const_optimized(Z_R1_scratch, disp_value);
902 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
903 disp_reg = Z_R1_scratch;
904 disp_value = 0;
905 }
906 disp_reg = addr->index()->as_pointer_register();
907 }
908
909 // Remember the offset of the load. The patching_epilog must be done
910 // before the call to add_debug_info, otherwise the PcDescs don't get
911 // entered in increasing order.
912 int offset = code_offset();
913
914 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
915
916 bool short_disp = Immediate::is_uimm12(disp_value);
917
918 switch (type) {
919 case T_BOOLEAN: // fall through
920 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
921 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
922 case T_SHORT :
923 if (short_disp) {
924 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
925 } else {
926 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
927 }
928 break;
929 case T_INT :
930 if (short_disp) {
931 __ z_l(dest->as_register(), disp_value, disp_reg, src);
932 } else {
933 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
934 }
935 break;
936 case T_ADDRESS:
937 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
938 break;
939 case T_ARRAY : // fall through
940 case T_OBJECT:
941 {
942 if (UseCompressedOops && !wide) {
943 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
944 __ oop_decoder(dest->as_register(), dest->as_register(), true);
945 } else {
946 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
947 }
948 __ verify_oop(dest->as_register(), FILE_AND_LINE);
949 break;
950 }
951 case T_FLOAT:
952 if (short_disp) {
953 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
954 } else {
955 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
956 }
957 break;
958 case T_DOUBLE:
959 if (short_disp) {
960 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
961 } else {
962 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
963 }
964 break;
965 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
966 default : ShouldNotReachHere();
967 }
968
969 if (patch != nullptr) {
970 patching_epilog(patch, patch_code, src, info);
971 }
972 if (info != nullptr) add_debug_info_for_null_check(offset, info);
973 }
974
975 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
976 assert(src->is_stack(), "should not call otherwise");
977 assert(dest->is_register(), "should not call otherwise");
978
979 if (dest->is_single_cpu()) {
980 if (is_reference_type(type)) {
981 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
982 __ verify_oop(dest->as_register(), FILE_AND_LINE);
983 } else if (type == T_METADATA || type == T_ADDRESS) {
984 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
985 } else {
986 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
987 }
988 } else if (dest->is_double_cpu()) {
989 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
990 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
991 } else if (dest->is_single_fpu()) {
992 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
993 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
994 } else if (dest->is_double_fpu()) {
995 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
996 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
997 } else {
998 ShouldNotReachHere();
999 }
1000 }
1001
1002 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1003 assert(src->is_register(), "should not call otherwise");
1004 assert(dest->is_stack(), "should not call otherwise");
1005
1006 if (src->is_single_cpu()) {
1007 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1008 if (is_reference_type(type)) {
1009 __ verify_oop(src->as_register(), FILE_AND_LINE);
1010 __ reg2mem_opt(src->as_register(), dst, true);
1011 } else if (type == T_METADATA || type == T_ADDRESS) {
1012 __ reg2mem_opt(src->as_register(), dst, true);
1013 } else {
1014 __ reg2mem_opt(src->as_register(), dst, false);
1015 }
1016 } else if (src->is_double_cpu()) {
1017 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1018 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1019 } else if (src->is_single_fpu()) {
1020 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1021 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1022 } else if (src->is_double_fpu()) {
1023 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1024 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1025 } else {
1026 ShouldNotReachHere();
1027 }
1028 }
1029
1030 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1031 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1032 if (from_reg->is_double_fpu()) {
1033 // double to double moves
1034 assert(to_reg->is_double_fpu(), "should match");
1035 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1036 } else {
1037 // float to float moves
1038 assert(to_reg->is_single_fpu(), "should match");
1039 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1040 }
1041 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1042 if (from_reg->is_double_cpu()) {
1043 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1044 } else if (to_reg->is_double_cpu()) {
1045 // int to int moves
1046 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1047 } else {
1048 // int to int moves
1049 __ z_lgr(to_reg->as_register(), from_reg->as_register());
1050 }
1051 } else {
1052 ShouldNotReachHere();
1053 }
1054 if (is_reference_type(to_reg->type())) {
1055 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1056 }
1057 }
1058
1059 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1060 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1061 bool wide) {
1062 assert(type != T_METADATA, "store of metadata ptr not supported");
1063 LIR_Address* addr = dest_opr->as_address_ptr();
1064
1065 Register dest = addr->base()->as_pointer_register();
1066 Register disp_reg = Z_R0;
1067 int disp_value = addr->disp();
1068 bool needs_patching = (patch_code != lir_patch_none);
1069
1070 if (addr->base()->is_oop_register()) {
1071 __ verify_oop(dest, FILE_AND_LINE);
1072 }
1073
1074 PatchingStub* patch = nullptr;
1075 if (needs_patching) {
1076 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1077 assert(!from->is_double_cpu() ||
1078 patch_code == lir_patch_none ||
1079 patch_code == lir_patch_normal, "patching doesn't match register");
1080 }
1081
1082 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1083 if (addr->index()->is_illegal()) {
1084 if (!Immediate::is_simm20(disp_value)) {
1085 if (needs_patching) {
1086 __ load_const(Z_R1_scratch, (intptr_t)0);
1087 } else {
1088 __ load_const_optimized(Z_R1_scratch, disp_value);
1089 }
1090 disp_reg = Z_R1_scratch;
1091 disp_value = 0;
1092 }
1093 } else {
1094 if (!Immediate::is_simm20(disp_value)) {
1095 __ load_const_optimized(Z_R1_scratch, disp_value);
1096 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1097 disp_reg = Z_R1_scratch;
1098 disp_value = 0;
1099 }
1100 disp_reg = addr->index()->as_pointer_register();
1101 }
1102
1103 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1104
1105 if (is_reference_type(type)) {
1106 __ verify_oop(from->as_register(), FILE_AND_LINE);
1107 }
1108
1109 bool short_disp = Immediate::is_uimm12(disp_value);
1110
1111 // Remember the offset of the store. The patching_epilog must be done
1112 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1113 // entered in increasing order.
1114 int offset = code_offset();
1115 switch (type) {
1116 case T_BOOLEAN: // fall through
1117 case T_BYTE :
1118 if (short_disp) {
1119 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1120 } else {
1121 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1122 }
1123 break;
1124 case T_CHAR : // fall through
1125 case T_SHORT :
1126 if (short_disp) {
1127 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1128 } else {
1129 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1130 }
1131 break;
1132 case T_INT :
1133 if (short_disp) {
1134 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1135 } else {
1136 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1137 }
1138 break;
1139 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1140 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1141 break;
1142 case T_ARRAY : // fall through
1143 case T_OBJECT:
1144 {
1145 if (UseCompressedOops && !wide) {
1146 Register compressed_src = Z_R14;
1147 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1148 offset = code_offset();
1149 if (short_disp) {
1150 __ z_st(compressed_src, disp_value, disp_reg, dest);
1151 } else {
1152 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1153 }
1154 } else {
1155 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1156 }
1157 break;
1158 }
1159 case T_FLOAT :
1160 if (short_disp) {
1161 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1162 } else {
1163 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1164 }
1165 break;
1166 case T_DOUBLE:
1167 if (short_disp) {
1168 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1169 } else {
1170 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1171 }
1172 break;
1173 default: ShouldNotReachHere();
1174 }
1175
1176 if (patch != nullptr) {
1177 patching_epilog(patch, patch_code, dest, info);
1178 }
1179
1180 if (info != nullptr) add_debug_info_for_null_check(offset, info);
1181 }
1182
1183
1184 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1185 assert(result->is_illegal() ||
1186 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1187 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1188 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1189 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1190
1191 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1192
1193 // Pop the frame before the safepoint code.
1194 __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1195
1196 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1197 __ reserved_stack_check(Z_R14);
1198 }
1199
1200 // We need to mark the code position where the load from the safepoint
1201 // polling page was emitted as relocInfo::poll_return_type here.
1202 __ relocate(relocInfo::poll_return_type);
1203 __ load_from_polling_page(Z_R1_scratch);
1204
1205 __ z_br(Z_R14); // Return to caller.
1206 }
1207
1208 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1209 const Register poll_addr = tmp->as_register_lo();
1210 __ z_lg(poll_addr, Address(Z_thread, JavaThread::polling_page_offset()));
1211 guarantee(info != nullptr, "Shouldn't be null");
1212 add_debug_info_for_branch(info);
1213 int offset = __ offset();
1214 __ relocate(relocInfo::poll_type);
1215 __ load_from_polling_page(poll_addr);
1216 return offset;
1217 }
1218
1219 void LIR_Assembler::emit_static_call_stub() {
1220
1221 // Stub is fixed up when the corresponding call is converted from calling
1222 // compiled code to calling interpreted code.
1223
1224 address call_pc = __ pc();
1225 address stub = __ start_a_stub(call_stub_size());
1226 if (stub == nullptr) {
1227 bailout("static call stub overflow");
1228 return;
1229 }
1230
1231 int start = __ offset();
1232
1233 __ relocate(static_stub_Relocation::spec(call_pc));
1234
1235 // See also Matcher::interpreter_method_reg().
1236 AddressLiteral meta = __ allocate_metadata_address(nullptr);
1237 bool success = __ load_const_from_toc(Z_method, meta);
1238
1239 __ set_inst_mark();
1240 AddressLiteral a((address)-1);
1241 success = success && __ load_const_from_toc(Z_R1, a);
1242 if (!success) {
1243 bailout("const section overflow");
1244 return;
1245 }
1246
1247 __ z_br(Z_R1);
1248 assert(__ offset() - start <= call_stub_size(), "stub too big");
1249 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1250 }
1251
1252 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1253 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1254 if (opr1->is_single_cpu()) {
1255 Register reg1 = opr1->as_register();
1256 if (opr2->is_single_cpu()) {
1257 // cpu register - cpu register
1258 if (is_reference_type(opr1->type())) {
1259 __ z_clgr(reg1, opr2->as_register());
1260 } else {
1261 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1262 if (unsigned_comp) {
1263 __ z_clr(reg1, opr2->as_register());
1264 } else {
1265 __ z_cr(reg1, opr2->as_register());
1266 }
1267 }
1268 } else if (opr2->is_stack()) {
1269 // cpu register - stack
1270 if (is_reference_type(opr1->type())) {
1271 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1272 } else {
1273 if (unsigned_comp) {
1274 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1275 } else {
1276 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1277 }
1278 }
1279 } else if (opr2->is_constant()) {
1280 // cpu register - constant
1281 LIR_Const* c = opr2->as_constant_ptr();
1282 if (c->type() == T_INT) {
1283 if (unsigned_comp) {
1284 __ z_clfi(reg1, c->as_jint());
1285 } else {
1286 __ z_cfi(reg1, c->as_jint());
1287 }
1288 } else if (c->type() == T_METADATA) {
1289 // We only need, for now, comparison with null for metadata.
1290 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1291 Metadata* m = c->as_metadata();
1292 if (m == nullptr) {
1293 __ z_cghi(reg1, 0);
1294 } else {
1295 ShouldNotReachHere();
1296 }
1297 } else if (is_reference_type(c->type())) {
1298 // In 64bit oops are single register.
1299 jobject o = c->as_jobject();
1300 if (o == nullptr) {
1301 __ z_ltgr(reg1, reg1);
1302 } else {
1303 jobject2reg(o, Z_R1_scratch);
1304 __ z_cgr(reg1, Z_R1_scratch);
1305 }
1306 } else {
1307 fatal("unexpected type: %s", basictype_to_str(c->type()));
1308 }
1309 // cpu register - address
1310 } else if (opr2->is_address()) {
1311 if (op->info() != nullptr) {
1312 add_debug_info_for_null_check_here(op->info());
1313 }
1314 if (unsigned_comp) {
1315 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1316 } else {
1317 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1318 }
1319 } else {
1320 ShouldNotReachHere();
1321 }
1322
1323 } else if (opr1->is_double_cpu()) {
1324 assert(!unsigned_comp, "unexpected");
1325 Register xlo = opr1->as_register_lo();
1326 Register xhi = opr1->as_register_hi();
1327 if (opr2->is_double_cpu()) {
1328 __ z_cgr(xlo, opr2->as_register_lo());
1329 } else if (opr2->is_constant()) {
1330 // cpu register - constant 0
1331 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1332 __ z_ltgr(xlo, xlo);
1333 } else {
1334 ShouldNotReachHere();
1335 }
1336
1337 } else if (opr1->is_single_fpu()) {
1338 if (opr2->is_single_fpu()) {
1339 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1340 } else {
1341 // stack slot
1342 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1343 if (Immediate::is_uimm12(addr.disp())) {
1344 __ z_ceb(opr1->as_float_reg(), addr);
1345 } else {
1346 __ z_ley(Z_fscratch_1, addr);
1347 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1348 }
1349 }
1350 } else if (opr1->is_double_fpu()) {
1351 if (opr2->is_double_fpu()) {
1352 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1353 } else {
1354 // stack slot
1355 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1356 if (Immediate::is_uimm12(addr.disp())) {
1357 __ z_cdb(opr1->as_double_reg(), addr);
1358 } else {
1359 __ z_ldy(Z_fscratch_1, addr);
1360 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1361 }
1362 }
1363 } else {
1364 ShouldNotReachHere();
1365 }
1366 }
1367
1368 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1369 Label done;
1370 Register dreg = dst->as_register();
1371
1372 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1373 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1374 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1375 bool is_single = left->is_single_fpu();
1376 bool is_unordered_less = (code == lir_ucmp_fd2i);
1377 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1378 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1379 if (is_single) {
1380 __ z_cebr(lreg, rreg);
1381 } else {
1382 __ z_cdbr(lreg, rreg);
1383 }
1384 if (VM_Version::has_LoadStoreConditional()) {
1385 Register one = Z_R0_scratch;
1386 Register minus_one = Z_R1_scratch;
1387 __ z_lghi(minus_one, -1);
1388 __ z_lghi(one, 1);
1389 __ z_lghi(dreg, 0);
1390 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1391 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1392 } else {
1393 __ clear_reg(dreg, true, false);
1394 __ z_bre(done); // if (left == right) dst = 0
1395
1396 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1397 __ z_lhi(dreg, 1);
1398 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1399
1400 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1401 __ z_lhi(dreg, -1);
1402 }
1403 } else {
1404 assert(code == lir_cmp_l2i, "check");
1405 if (VM_Version::has_LoadStoreConditional()) {
1406 Register one = Z_R0_scratch;
1407 Register minus_one = Z_R1_scratch;
1408 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1409 __ z_lghi(minus_one, -1);
1410 __ z_lghi(one, 1);
1411 __ z_lghi(dreg, 0);
1412 __ z_locgr(dreg, one, Assembler::bcondHigh);
1413 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1414 } else {
1415 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1416 __ z_lghi(dreg, 0); // eq value
1417 __ z_bre(done);
1418 __ z_lghi(dreg, 1); // gt value
1419 __ z_brh(done);
1420 __ z_lghi(dreg, -1); // lt value
1421 }
1422 }
1423 __ bind(done);
1424 }
1425
1426 // result = condition ? opr1 : opr2
1427 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1428 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1429 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390");
1430
1431 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1432 switch (condition) {
1433 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1434 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1435 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1436 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1437 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1438 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1439 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1440 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1441 default: ShouldNotReachHere();
1442 }
1443
1444 if (opr1->is_cpu_register()) {
1445 reg2reg(opr1, result);
1446 } else if (opr1->is_stack()) {
1447 stack2reg(opr1, result, result->type());
1448 } else if (opr1->is_constant()) {
1449 const2reg(opr1, result, lir_patch_none, nullptr);
1450 } else {
1451 ShouldNotReachHere();
1452 }
1453
1454 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1455 // Optimized version that does not require a branch.
1456 if (opr2->is_single_cpu()) {
1457 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1458 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1459 } else if (opr2->is_double_cpu()) {
1460 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1461 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1462 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1463 } else if (opr2->is_single_stack()) {
1464 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1465 } else if (opr2->is_double_stack()) {
1466 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1467 } else {
1468 ShouldNotReachHere();
1469 }
1470 } else {
1471 Label skip;
1472 __ z_brc(acond, skip);
1473 if (opr2->is_cpu_register()) {
1474 reg2reg(opr2, result);
1475 } else if (opr2->is_stack()) {
1476 stack2reg(opr2, result, result->type());
1477 } else if (opr2->is_constant()) {
1478 const2reg(opr2, result, lir_patch_none, nullptr);
1479 } else {
1480 ShouldNotReachHere();
1481 }
1482 __ bind(skip);
1483 }
1484 }
1485
1486 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1487 CodeEmitInfo* info, bool pop_fpu_stack) {
1488 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1489
1490 if (left->is_single_cpu()) {
1491 assert(left == dest, "left and dest must be equal");
1492 Register lreg = left->as_register();
1493
1494 if (right->is_single_cpu()) {
1495 // cpu register - cpu register
1496 Register rreg = right->as_register();
1497 switch (code) {
1498 case lir_add: __ z_ar (lreg, rreg); break;
1499 case lir_sub: __ z_sr (lreg, rreg); break;
1500 case lir_mul: __ z_msr(lreg, rreg); break;
1501 default: ShouldNotReachHere();
1502 }
1503
1504 } else if (right->is_stack()) {
1505 // cpu register - stack
1506 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1507 switch (code) {
1508 case lir_add: __ z_ay(lreg, raddr); break;
1509 case lir_sub: __ z_sy(lreg, raddr); break;
1510 default: ShouldNotReachHere();
1511 }
1512
1513 } else if (right->is_constant()) {
1514 // cpu register - constant
1515 jint c = right->as_constant_ptr()->as_jint();
1516 switch (code) {
1517 case lir_add: __ z_agfi(lreg, c); break;
1518 case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
1519 case lir_mul: __ z_msfi(lreg, c); break;
1520 default: ShouldNotReachHere();
1521 }
1522
1523 } else {
1524 ShouldNotReachHere();
1525 }
1526
1527 } else if (left->is_double_cpu()) {
1528 assert(left == dest, "left and dest must be equal");
1529 Register lreg_lo = left->as_register_lo();
1530 Register lreg_hi = left->as_register_hi();
1531
1532 if (right->is_double_cpu()) {
1533 // cpu register - cpu register
1534 Register rreg_lo = right->as_register_lo();
1535 Register rreg_hi = right->as_register_hi();
1536 assert_different_registers(lreg_lo, rreg_lo);
1537 switch (code) {
1538 case lir_add:
1539 __ z_agr(lreg_lo, rreg_lo);
1540 break;
1541 case lir_sub:
1542 __ z_sgr(lreg_lo, rreg_lo);
1543 break;
1544 case lir_mul:
1545 __ z_msgr(lreg_lo, rreg_lo);
1546 break;
1547 default:
1548 ShouldNotReachHere();
1549 }
1550
1551 } else if (right->is_constant()) {
1552 // cpu register - constant
1553 jlong c = right->as_constant_ptr()->as_jlong_bits();
1554 switch (code) {
1555 case lir_add: __ z_agfi(lreg_lo, c); break;
1556 case lir_sub:
1557 if (c != min_jint) {
1558 __ z_agfi(lreg_lo, -c);
1559 } else {
1560 // -min_jint cannot be represented as simm32 in z_agfi
1561 // min_jint sign extended: 0xffffffff80000000
1562 // -min_jint as 64 bit integer: 0x0000000080000000
1563 // 0x80000000 can be represented as uimm32 in z_algfi
1564 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1565 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1566 }
1567 break;
1568 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1569 default:
1570 ShouldNotReachHere();
1571 }
1572
1573 } else {
1574 ShouldNotReachHere();
1575 }
1576
1577 } else if (left->is_single_fpu()) {
1578 assert(left == dest, "left and dest must be equal");
1579 FloatRegister lreg = left->as_float_reg();
1580 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1581 Address raddr;
1582
1583 if (rreg == fnoreg) {
1584 assert(right->is_single_stack(), "constants should be loaded into register");
1585 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1586 if (!Immediate::is_uimm12(raddr.disp())) {
1587 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1588 }
1589 }
1590
1591 if (rreg != fnoreg) {
1592 switch (code) {
1593 case lir_add: __ z_aebr(lreg, rreg); break;
1594 case lir_sub: __ z_sebr(lreg, rreg); break;
1595 case lir_mul: __ z_meebr(lreg, rreg); break;
1596 case lir_div: __ z_debr(lreg, rreg); break;
1597 default: ShouldNotReachHere();
1598 }
1599 } else {
1600 switch (code) {
1601 case lir_add: __ z_aeb(lreg, raddr); break;
1602 case lir_sub: __ z_seb(lreg, raddr); break;
1603 case lir_mul: __ z_meeb(lreg, raddr); break;
1604 case lir_div: __ z_deb(lreg, raddr); break;
1605 default: ShouldNotReachHere();
1606 }
1607 }
1608 } else if (left->is_double_fpu()) {
1609 assert(left == dest, "left and dest must be equal");
1610 FloatRegister lreg = left->as_double_reg();
1611 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1612 Address raddr;
1613
1614 if (rreg == fnoreg) {
1615 assert(right->is_double_stack(), "constants should be loaded into register");
1616 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1617 if (!Immediate::is_uimm12(raddr.disp())) {
1618 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1619 }
1620 }
1621
1622 if (rreg != fnoreg) {
1623 switch (code) {
1624 case lir_add: __ z_adbr(lreg, rreg); break;
1625 case lir_sub: __ z_sdbr(lreg, rreg); break;
1626 case lir_mul: __ z_mdbr(lreg, rreg); break;
1627 case lir_div: __ z_ddbr(lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630 } else {
1631 switch (code) {
1632 case lir_add: __ z_adb(lreg, raddr); break;
1633 case lir_sub: __ z_sdb(lreg, raddr); break;
1634 case lir_mul: __ z_mdb(lreg, raddr); break;
1635 case lir_div: __ z_ddb(lreg, raddr); break;
1636 default: ShouldNotReachHere();
1637 }
1638 }
1639 } else if (left->is_address()) {
1640 assert(left == dest, "left and dest must be equal");
1641 assert(code == lir_add, "unsupported operation");
1642 assert(right->is_constant(), "unsupported operand");
1643 jint c = right->as_constant_ptr()->as_jint();
1644 LIR_Address* lir_addr = left->as_address_ptr();
1645 Address addr = as_Address(lir_addr);
1646 switch (lir_addr->type()) {
1647 case T_INT:
1648 __ add2mem_32(addr, c, Z_R1_scratch);
1649 break;
1650 case T_LONG:
1651 __ add2mem_64(addr, c, Z_R1_scratch);
1652 break;
1653 default:
1654 ShouldNotReachHere();
1655 }
1656 } else {
1657 ShouldNotReachHere();
1658 }
1659 }
1660
1661 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1662 switch (code) {
1663 case lir_sqrt: {
1664 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1665 FloatRegister src_reg = value->as_double_reg();
1666 FloatRegister dst_reg = dest->as_double_reg();
1667 __ z_sqdbr(dst_reg, src_reg);
1668 break;
1669 }
1670 case lir_abs: {
1671 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1672 FloatRegister src_reg = value->as_double_reg();
1673 FloatRegister dst_reg = dest->as_double_reg();
1674 __ z_lpdbr(dst_reg, src_reg);
1675 break;
1676 }
1677 default: {
1678 ShouldNotReachHere();
1679 break;
1680 }
1681 }
1682 }
1683
1684 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1685 if (left->is_single_cpu()) {
1686 Register reg = left->as_register();
1687 if (right->is_constant()) {
1688 int val = right->as_constant_ptr()->as_jint();
1689 switch (code) {
1690 case lir_logic_and: __ z_nilf(reg, val); break;
1691 case lir_logic_or: __ z_oilf(reg, val); break;
1692 case lir_logic_xor: __ z_xilf(reg, val); break;
1693 default: ShouldNotReachHere();
1694 }
1695 } else if (right->is_stack()) {
1696 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1697 switch (code) {
1698 case lir_logic_and: __ z_ny(reg, raddr); break;
1699 case lir_logic_or: __ z_oy(reg, raddr); break;
1700 case lir_logic_xor: __ z_xy(reg, raddr); break;
1701 default: ShouldNotReachHere();
1702 }
1703 } else {
1704 Register rright = right->as_register();
1705 switch (code) {
1706 case lir_logic_and: __ z_nr(reg, rright); break;
1707 case lir_logic_or : __ z_or(reg, rright); break;
1708 case lir_logic_xor: __ z_xr(reg, rright); break;
1709 default: ShouldNotReachHere();
1710 }
1711 }
1712 move_regs(reg, dst->as_register());
1713 } else {
1714 Register l_lo = left->as_register_lo();
1715 if (right->is_constant()) {
1716 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1717 switch (code) {
1718 case lir_logic_and:
1719 __ z_ngr(l_lo, Z_R1_scratch);
1720 break;
1721 case lir_logic_or:
1722 __ z_ogr(l_lo, Z_R1_scratch);
1723 break;
1724 case lir_logic_xor:
1725 __ z_xgr(l_lo, Z_R1_scratch);
1726 break;
1727 default: ShouldNotReachHere();
1728 }
1729 } else {
1730 Register r_lo;
1731 if (is_reference_type(right->type())) {
1732 r_lo = right->as_register();
1733 } else {
1734 r_lo = right->as_register_lo();
1735 }
1736 switch (code) {
1737 case lir_logic_and:
1738 __ z_ngr(l_lo, r_lo);
1739 break;
1740 case lir_logic_or:
1741 __ z_ogr(l_lo, r_lo);
1742 break;
1743 case lir_logic_xor:
1744 __ z_xgr(l_lo, r_lo);
1745 break;
1746 default: ShouldNotReachHere();
1747 }
1748 }
1749
1750 Register dst_lo = dst->as_register_lo();
1751
1752 move_regs(l_lo, dst_lo);
1753 }
1754 }
1755
1756 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1757 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1758 if (left->is_double_cpu()) {
1759 // 64 bit integer case
1760 assert(left->is_double_cpu(), "left must be register");
1761 assert(right->is_double_cpu() || is_power_of_2(right->as_jlong()),
1762 "right must be register or power of 2 constant");
1763 assert(result->is_double_cpu(), "result must be register");
1764
1765 Register lreg = left->as_register_lo();
1766 Register dreg = result->as_register_lo();
1767
1768 if (right->is_constant()) {
1769 // Convert division by a power of two into some shifts and logical operations.
1770 Register treg1 = Z_R0_scratch;
1771 Register treg2 = Z_R1_scratch;
1772 jlong divisor = right->as_jlong();
1773 jlong log_divisor = log2i_exact(right->as_jlong());
1774
1775 if (divisor == min_jlong) {
1776 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1777 if (dreg == lreg) {
1778 NearLabel done;
1779 __ load_const_optimized(treg2, min_jlong);
1780 __ z_cgr(lreg, treg2);
1781 __ z_lghi(dreg, 0); // Preserves condition code.
1782 __ z_brne(done);
1783 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1784 __ bind(done);
1785 } else {
1786 assert_different_registers(dreg, lreg);
1787 NearLabel done;
1788 __ z_lghi(dreg, 0);
1789 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1790 __ z_lghi(dreg, 1);
1791 __ bind(done);
1792 }
1793 return;
1794 }
1795 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1796 if (divisor == 2) {
1797 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1798 } else {
1799 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1800 __ and_imm(treg2, divisor - 1, treg1, true);
1801 }
1802 if (code == lir_idiv) {
1803 __ z_agr(dreg, treg2);
1804 __ z_srag(dreg, dreg, log_divisor);
1805 } else {
1806 assert(code == lir_irem, "check");
1807 __ z_agr(treg2, dreg);
1808 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1809 __ z_sgr(dreg, treg2);
1810 }
1811 return;
1812 }
1813
1814 // Divisor is not a power of 2 constant.
1815 Register rreg = right->as_register_lo();
1816 Register treg = temp->as_register_lo();
1817 assert(right->is_double_cpu(), "right must be register");
1818 assert(lreg == Z_R11, "see ldivInOpr()");
1819 assert(rreg != lreg, "right register must not be same as left register");
1820 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1821 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1822
1823 Register R1 = lreg->predecessor();
1824 Register R2 = rreg;
1825 assert(code != lir_idiv || lreg==dreg, "see code below");
1826 if (code == lir_idiv) {
1827 __ z_lcgr(lreg, lreg);
1828 } else {
1829 __ clear_reg(dreg, true, false);
1830 }
1831 NearLabel done;
1832 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1833 if (code == lir_idiv) {
1834 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1835 }
1836 if (ImplicitDiv0Checks) {
1837 // No debug info because the idiv won't trap.
1838 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1839 // which is unnecessary, too.
1840 add_debug_info_for_div0(__ offset(), info);
1841 }
1842 __ z_dsgr(R1, R2);
1843 __ bind(done);
1844 return;
1845 }
1846
1847 // 32 bit integer case
1848
1849 assert(left->is_single_cpu(), "left must be register");
1850 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1851 assert(result->is_single_cpu(), "result must be register");
1852
1853 Register lreg = left->as_register();
1854 Register dreg = result->as_register();
1855
1856 if (right->is_constant()) {
1857 // Convert division by a power of two into some shifts and logical operations.
1858 Register treg1 = Z_R0_scratch;
1859 Register treg2 = Z_R1_scratch;
1860 jlong divisor = right->as_jint();
1861 jlong log_divisor = log2i_exact(right->as_jint());
1862 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1863 if (divisor == 2) {
1864 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1865 } else {
1866 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1867 __ and_imm(treg2, divisor - 1, treg1, true);
1868 }
1869 if (code == lir_idiv) {
1870 __ z_agr(dreg, treg2);
1871 __ z_srag(dreg, dreg, log_divisor);
1872 } else {
1873 assert(code == lir_irem, "check");
1874 __ z_agr(treg2, dreg);
1875 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1876 __ z_sgr(dreg, treg2);
1877 }
1878 return;
1879 }
1880
1881 // Divisor is not a power of 2 constant.
1882 Register rreg = right->as_register();
1883 Register treg = temp->as_register();
1884 assert(right->is_single_cpu(), "right must be register");
1885 assert(lreg == Z_R11, "left register must be rax,");
1886 assert(rreg != lreg, "right register must not be same as left register");
1887 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1888 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1889
1890 Register R1 = lreg->predecessor();
1891 Register R2 = rreg;
1892 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1893 if (ImplicitDiv0Checks) {
1894 // No debug info because the idiv won't trap.
1895 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1896 // which is unnecessary, too.
1897 add_debug_info_for_div0(__ offset(), info);
1898 }
1899 __ z_dsgfr(R1, R2);
1900 }
1901
1902 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1903 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1904 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1905
1906 // Exception object is not added to oop map by LinearScan
1907 // (LinearScan assumes that no oops are in fixed registers).
1908 info->add_register_oop(exceptionOop);
1909
1910 // Reuse the debug info from the safepoint poll for the throw op itself.
1911 __ get_PC(Z_EXC_PC);
1912 add_call_info(__ offset(), info); // for exception handler
1913 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? C1StubId::handle_exception_id
1914 : C1StubId::handle_exception_nofpu_id);
1915 emit_call_c(stub);
1916 }
1917
1918 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1919 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1920
1921 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1922 }
1923
1924 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1925 ciArrayKlass* default_type = op->expected_type();
1926 Register src = op->src()->as_register();
1927 Register dst = op->dst()->as_register();
1928 Register src_pos = op->src_pos()->as_register();
1929 Register dst_pos = op->dst_pos()->as_register();
1930 Register length = op->length()->as_register();
1931 Register tmp = op->tmp()->as_register();
1932
1933 CodeStub* stub = op->stub();
1934 int flags = op->flags();
1935 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
1936 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1937
1938 // If we don't know anything, just go through the generic arraycopy.
1939 if (default_type == nullptr) {
1940 address copyfunc_addr = StubRoutines::generic_arraycopy();
1941
1942 if (copyfunc_addr == nullptr) {
1943 // Take a slow path for generic arraycopy.
1944 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1945 __ bind(*stub->continuation());
1946 return;
1947 }
1948
1949 // Save outgoing arguments in callee saved registers (C convention) in case
1950 // a call to System.arraycopy is needed.
1951 Register callee_saved_src = Z_R10;
1952 Register callee_saved_src_pos = Z_R11;
1953 Register callee_saved_dst = Z_R12;
1954 Register callee_saved_dst_pos = Z_R13;
1955 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1956
1957 __ lgr_if_needed(callee_saved_src, src);
1958 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1959 __ lgr_if_needed(callee_saved_dst, dst);
1960 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1961 __ lgr_if_needed(callee_saved_length, length);
1962
1963 // C function requires 64 bit values.
1964 __ z_lgfr(src_pos, src_pos);
1965 __ z_lgfr(dst_pos, dst_pos);
1966 __ z_lgfr(length, length);
1967
1968 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
1969
1970 // The arguments are in the corresponding registers.
1971 assert(Z_ARG1 == src, "assumption");
1972 assert(Z_ARG2 == src_pos, "assumption");
1973 assert(Z_ARG3 == dst, "assumption");
1974 assert(Z_ARG4 == dst_pos, "assumption");
1975 assert(Z_ARG5 == length, "assumption");
1976 #ifndef PRODUCT
1977 if (PrintC1Statistics) {
1978 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
1979 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
1980 }
1981 #endif
1982 emit_call_c(copyfunc_addr);
1983 CHECK_BAILOUT();
1984
1985 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
1986
1987 __ z_lgr(tmp, Z_RET);
1988 __ z_xilf(tmp, -1);
1989
1990 // Restore values from callee saved registers so they are where the stub
1991 // expects them.
1992 __ lgr_if_needed(src, callee_saved_src);
1993 __ lgr_if_needed(src_pos, callee_saved_src_pos);
1994 __ lgr_if_needed(dst, callee_saved_dst);
1995 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
1996 __ lgr_if_needed(length, callee_saved_length);
1997
1998 __ z_sr(length, tmp);
1999 __ z_ar(src_pos, tmp);
2000 __ z_ar(dst_pos, tmp);
2001 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2002
2003 __ bind(*stub->continuation());
2004 return;
2005 }
2006
2007 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2008
2009 int elem_size = type2aelembytes(basic_type);
2010 int shift_amount;
2011
2012 switch (elem_size) {
2013 case 1 :
2014 shift_amount = 0;
2015 break;
2016 case 2 :
2017 shift_amount = 1;
2018 break;
2019 case 4 :
2020 shift_amount = 2;
2021 break;
2022 case 8 :
2023 shift_amount = 3;
2024 break;
2025 default:
2026 shift_amount = -1;
2027 ShouldNotReachHere();
2028 }
2029
2030 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2031 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2032 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2033 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2034
2035 // Length and pos's are all sign extended at this point on 64bit.
2036
2037 // test for null
2038 if (flags & LIR_OpArrayCopy::src_null_check) {
2039 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2040 }
2041 if (flags & LIR_OpArrayCopy::dst_null_check) {
2042 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2043 }
2044
2045 // Check if negative.
2046 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2047 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2048 }
2049 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2050 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2051 }
2052
2053 // If the compiler was not able to prove that exact type of the source or the destination
2054 // of the arraycopy is an array type, check at runtime if the source or the destination is
2055 // an instance type.
2056 if (flags & LIR_OpArrayCopy::type_check) {
2057 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2058
2059 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2060 __ load_klass(tmp, dst);
2061 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2062 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2063 }
2064
2065 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2066 __ load_klass(tmp, src);
2067 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2068 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2069 }
2070 }
2071
2072 if (flags & LIR_OpArrayCopy::src_range_check) {
2073 __ z_la(tmp, Address(src_pos, length));
2074 __ z_cl(tmp, src_length_addr);
2075 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2076 }
2077 if (flags & LIR_OpArrayCopy::dst_range_check) {
2078 __ z_la(tmp, Address(dst_pos, length));
2079 __ z_cl(tmp, dst_length_addr);
2080 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2081 }
2082
2083 if (flags & LIR_OpArrayCopy::length_positive_check) {
2084 __ z_ltr(length, length);
2085 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2086 }
2087
2088 // Stubs require 64 bit values.
2089 __ z_lgfr(src_pos, src_pos); // int -> long
2090 __ z_lgfr(dst_pos, dst_pos); // int -> long
2091 __ z_lgfr(length, length); // int -> long
2092
2093 if (flags & LIR_OpArrayCopy::type_check) {
2094 // We don't know the array types are compatible.
2095 if (basic_type != T_OBJECT) {
2096 // Simple test for basic type arrays.
2097 if (UseCompressedClassPointers) {
2098 __ z_l(tmp, src_klass_addr);
2099 __ z_c(tmp, dst_klass_addr);
2100 } else {
2101 __ z_lg(tmp, src_klass_addr);
2102 __ z_cg(tmp, dst_klass_addr);
2103 }
2104 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2105 } else {
2106 // For object arrays, if src is a sub class of dst then we can
2107 // safely do the copy.
2108 NearLabel cont, slow;
2109 Register src_klass = Z_R1_scratch;
2110 Register dst_klass = Z_R10;
2111
2112 __ load_klass(src_klass, src);
2113 __ load_klass(dst_klass, dst);
2114
2115 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, nullptr);
2116
2117 store_parameter(src_klass, 0); // sub
2118 store_parameter(dst_klass, 1); // super
2119 emit_call_c(Runtime1::entry_for (C1StubId::slow_subtype_check_id));
2120 CHECK_BAILOUT2(cont, slow);
2121 // Sets condition code 0 for match (2 otherwise).
2122 __ branch_optimized(Assembler::bcondEqual, cont);
2123
2124 __ bind(slow);
2125
2126 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2127 if (copyfunc_addr != nullptr) { // use stub if available
2128 // Src is not a sub class of dst so we have to do a
2129 // per-element check.
2130
2131 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2132 if ((flags & mask) != mask) {
2133 // Check that at least both of them object arrays.
2134 assert(flags & mask, "one of the two should be known to be an object array");
2135
2136 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2137 __ load_klass(tmp, src);
2138 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2139 __ load_klass(tmp, dst);
2140 }
2141 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2142 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2143 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2144 __ z_c(Z_R1_scratch, klass_lh_addr);
2145 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2146 }
2147
2148 // Save outgoing arguments in callee saved registers (C convention) in case
2149 // a call to System.arraycopy is needed.
2150 Register callee_saved_src = Z_R10;
2151 Register callee_saved_src_pos = Z_R11;
2152 Register callee_saved_dst = Z_R12;
2153 Register callee_saved_dst_pos = Z_R13;
2154 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2155
2156 __ lgr_if_needed(callee_saved_src, src);
2157 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2158 __ lgr_if_needed(callee_saved_dst, dst);
2159 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2160 __ lgr_if_needed(callee_saved_length, length);
2161
2162 __ z_llgfr(length, length); // Higher 32bits must be null.
2163
2164 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2165 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2166
2167 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2168 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2169 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2170 assert_different_registers(Z_ARG2, dst, length);
2171
2172 __ z_lgr(Z_ARG3, length);
2173 assert_different_registers(Z_ARG3, dst);
2174
2175 __ load_klass(Z_ARG5, dst);
2176 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2177 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2178 emit_call_c(copyfunc_addr);
2179 CHECK_BAILOUT2(cont, slow);
2180
2181 #ifndef PRODUCT
2182 if (PrintC1Statistics) {
2183 NearLabel failed;
2184 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2185 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2186 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2187 __ bind(failed);
2188 }
2189 #endif
2190
2191 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2192
2193 #ifndef PRODUCT
2194 if (PrintC1Statistics) {
2195 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2196 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2197 }
2198 #endif
2199
2200 __ z_lgr(tmp, Z_RET);
2201 __ z_xilf(tmp, -1);
2202
2203 // Restore previously spilled arguments
2204 __ lgr_if_needed(src, callee_saved_src);
2205 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2206 __ lgr_if_needed(dst, callee_saved_dst);
2207 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2208 __ lgr_if_needed(length, callee_saved_length);
2209
2210 __ z_sr(length, tmp);
2211 __ z_ar(src_pos, tmp);
2212 __ z_ar(dst_pos, tmp);
2213 }
2214
2215 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2216
2217 __ bind(cont);
2218 }
2219 }
2220
2221 #ifdef ASSERT
2222 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2223 // Sanity check the known type with the incoming class. For the
2224 // primitive case the types must match exactly with src.klass and
2225 // dst.klass each exactly matching the default type. For the
2226 // object array case, if no type check is needed then either the
2227 // dst type is exactly the expected type and the src type is a
2228 // subtype which we can't check or src is the same array as dst
2229 // but not necessarily exactly of type default_type.
2230 NearLabel known_ok, halt;
2231 metadata2reg(default_type->constant_encoding(), tmp);
2232 if (UseCompressedClassPointers) {
2233 __ encode_klass_not_null(tmp);
2234 }
2235
2236 if (basic_type != T_OBJECT) {
2237 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2238 else { __ z_cg(tmp, dst_klass_addr); }
2239 __ branch_optimized(Assembler::bcondNotEqual, halt);
2240 if (UseCompressedClassPointers) { __ z_c (tmp, src_klass_addr); }
2241 else { __ z_cg(tmp, src_klass_addr); }
2242 __ branch_optimized(Assembler::bcondEqual, known_ok);
2243 } else {
2244 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2245 else { __ z_cg(tmp, dst_klass_addr); }
2246 __ branch_optimized(Assembler::bcondEqual, known_ok);
2247 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2248 }
2249 __ bind(halt);
2250 __ stop("incorrect type information in arraycopy");
2251 __ bind(known_ok);
2252 }
2253 #endif
2254
2255 #ifndef PRODUCT
2256 if (PrintC1Statistics) {
2257 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2258 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2259 }
2260 #endif
2261
2262 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2263 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2264
2265 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2266 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2267 assert_different_registers(Z_ARG2, length);
2268 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2269 __ lgr_if_needed(Z_ARG3, length);
2270
2271 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2272 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2273 const char *name;
2274 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2275 __ call_VM_leaf(entry);
2276
2277 if (stub != nullptr) {
2278 __ bind(*stub->continuation());
2279 }
2280 }
2281
2282 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2283 if (dest->is_single_cpu()) {
2284 if (left->type() == T_OBJECT) {
2285 switch (code) {
2286 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2287 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2288 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2289 default: ShouldNotReachHere();
2290 }
2291 } else {
2292 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2293 Register masked_count = Z_R1_scratch;
2294 __ z_lr(masked_count, count->as_register());
2295 __ z_nill(masked_count, 31);
2296 switch (code) {
2297 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2298 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2299 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2300 default: ShouldNotReachHere();
2301 }
2302 }
2303 } else {
2304 switch (code) {
2305 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2306 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2307 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2308 default: ShouldNotReachHere();
2309 }
2310 }
2311 }
2312
2313 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2314 if (left->type() == T_OBJECT) {
2315 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2316 Register l = left->as_register();
2317 Register d = dest->as_register_lo();
2318 switch (code) {
2319 case lir_shl: __ z_sllg (d, l, count); break;
2320 case lir_shr: __ z_srag (d, l, count); break;
2321 case lir_ushr: __ z_srlg (d, l, count); break;
2322 default: ShouldNotReachHere();
2323 }
2324 return;
2325 }
2326 if (dest->is_single_cpu()) {
2327 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2328 count = count & 0x1F; // Java spec
2329 switch (code) {
2330 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2331 case lir_shr: __ z_sra (dest->as_register(), count); break;
2332 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2333 default: ShouldNotReachHere();
2334 }
2335 } else if (dest->is_double_cpu()) {
2336 count = count & 63; // Java spec
2337 Register l = left->as_pointer_register();
2338 Register d = dest->as_pointer_register();
2339 switch (code) {
2340 case lir_shl: __ z_sllg (d, l, count); break;
2341 case lir_shr: __ z_srag (d, l, count); break;
2342 case lir_ushr: __ z_srlg (d, l, count); break;
2343 default: ShouldNotReachHere();
2344 }
2345 } else {
2346 ShouldNotReachHere();
2347 }
2348 }
2349
2350 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2351 if (op->init_check()) {
2352 // Make sure klass is initialized & doesn't have finalizer.
2353 // init_state needs acquire, but S390 is TSO, and so we are already good.
2354 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2355 Register iklass = op->klass()->as_register();
2356 add_debug_info_for_null_check_here(op->stub()->info());
2357 if (Immediate::is_uimm12(state_offset)) {
2358 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2359 } else {
2360 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2361 }
2362 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2363 }
2364 __ allocate_object(op->obj()->as_register(),
2365 op->tmp1()->as_register(),
2366 op->tmp2()->as_register(),
2367 op->header_size(),
2368 op->object_size(),
2369 op->klass()->as_register(),
2370 *op->stub()->entry());
2371 __ bind(*op->stub()->continuation());
2372 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2373 }
2374
2375 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2376 Register len = op->len()->as_register();
2377 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2378
2379 if (UseSlowPath ||
2380 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2381 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2382 __ z_brul(*op->stub()->entry());
2383 } else {
2384 __ allocate_array(op->obj()->as_register(),
2385 op->len()->as_register(),
2386 op->tmp1()->as_register(),
2387 op->tmp2()->as_register(),
2388 arrayOopDesc::base_offset_in_bytes(op->type()),
2389 type2aelembytes(op->type()),
2390 op->klass()->as_register(),
2391 *op->stub()->entry(),
2392 op->zero_array());
2393 }
2394 __ bind(*op->stub()->continuation());
2395 }
2396
2397 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2398 Register recv, Register tmp1, Label* update_done) {
2399 uint i;
2400 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2401 Label next_test;
2402 // See if the receiver is receiver[n].
2403 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2404 __ z_cg(recv, receiver_addr);
2405 __ z_brne(next_test);
2406 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2407 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2408 __ branch_optimized(Assembler::bcondAlways, *update_done);
2409 __ bind(next_test);
2410 }
2411
2412 // Didn't find receiver; find next empty slot and fill it in.
2413 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2414 Label next_test;
2415 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2416 __ z_ltg(Z_R0_scratch, recv_addr);
2417 __ z_brne(next_test);
2418 __ z_stg(recv, recv_addr);
2419 __ load_const_optimized(tmp1, DataLayout::counter_increment);
2420 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2421 __ branch_optimized(Assembler::bcondAlways, *update_done);
2422 __ bind(next_test);
2423 }
2424 }
2425
2426 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2427 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2428 Unimplemented();
2429 }
2430
2431 void LIR_Assembler::store_parameter(Register r, int param_num) {
2432 assert(param_num >= 0, "invalid num");
2433 int offset_in_bytes = param_num * BytesPerWord;
2434 check_reserved_argument_area(offset_in_bytes);
2435 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2436 __ z_stg(r, offset_in_bytes, Z_SP);
2437 }
2438
2439 void LIR_Assembler::store_parameter(jint c, int param_num) {
2440 assert(param_num >= 0, "invalid num");
2441 int offset_in_bytes = param_num * BytesPerWord;
2442 check_reserved_argument_area(offset_in_bytes);
2443 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2444 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2445 }
2446
2447 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2448 // We always need a stub for the failure case.
2449 CodeStub* stub = op->stub();
2450 Register obj = op->object()->as_register();
2451 Register k_RInfo = op->tmp1()->as_register();
2452 Register klass_RInfo = op->tmp2()->as_register();
2453 Register dst = op->result_opr()->as_register();
2454 Register Rtmp1 = Z_R1_scratch;
2455 ciKlass* k = op->klass();
2456
2457 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2458
2459 // Check if it needs to be profiled.
2460 ciMethodData* md = nullptr;
2461 ciProfileData* data = nullptr;
2462
2463 if (op->should_profile()) {
2464 ciMethod* method = op->profiled_method();
2465 assert(method != nullptr, "Should have method");
2466 int bci = op->profiled_bci();
2467 md = method->method_data_or_null();
2468 assert(md != nullptr, "Sanity");
2469 data = md->bci_to_data(bci);
2470 assert(data != nullptr, "need data for type check");
2471 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2472 }
2473
2474 // Temp operands do not overlap with inputs, if this is their last
2475 // use (end of range is exclusive), so a register conflict is possible.
2476 if (obj == k_RInfo) {
2477 k_RInfo = dst;
2478 } else if (obj == klass_RInfo) {
2479 klass_RInfo = dst;
2480 }
2481 assert_different_registers(obj, k_RInfo, klass_RInfo);
2482
2483 if (op->should_profile()) {
2484 Register mdo = klass_RInfo;
2485 metadata2reg(md->constant_encoding(), mdo);
2486 NearLabel not_null;
2487 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2488 // Object is null; update MDO and exit.
2489 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2490 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2491 __ or2mem_8(data_addr, header_bits);
2492 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2493 __ bind(not_null);
2494
2495 NearLabel update_done;
2496 Register recv = k_RInfo;
2497 __ load_klass(recv, obj);
2498 type_profile_helper(mdo, md, data, recv, Rtmp1, &update_done);
2499 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2500 __ add2mem_64(counter_addr, DataLayout::counter_increment, Rtmp1);
2501 __ bind(update_done);
2502 } else {
2503 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2504 }
2505
2506 Label *failure_target = failure;
2507 Label *success_target = success;
2508
2509 // Patching may screw with our temporaries,
2510 // so let's do it before loading the class.
2511 if (k->is_loaded()) {
2512 metadata2reg(k->constant_encoding(), k_RInfo);
2513 } else {
2514 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2515 }
2516 assert(obj != k_RInfo, "must be different");
2517
2518 __ verify_oop(obj, FILE_AND_LINE);
2519
2520 // Get object class.
2521 // Not a safepoint as obj null check happens earlier.
2522 if (op->fast_check()) {
2523 if (UseCompressedClassPointers) {
2524 __ load_klass(klass_RInfo, obj);
2525 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2526 } else {
2527 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2528 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2529 }
2530 // Successful cast, fall through to profile or jump.
2531 } else {
2532 bool need_slow_path = !k->is_loaded() ||
2533 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2534 intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L;
2535 __ load_klass(klass_RInfo, obj);
2536 // Perform the fast part of the checking logic.
2537 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2538 (need_slow_path ? success_target : nullptr),
2539 failure_target, nullptr,
2540 RegisterOrConstant(super_check_offset));
2541 if (need_slow_path) {
2542 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2543 address a = Runtime1::entry_for (C1StubId::slow_subtype_check_id);
2544 store_parameter(klass_RInfo, 0); // sub
2545 store_parameter(k_RInfo, 1); // super
2546 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2547 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2548 // Fall through to success case.
2549 }
2550 }
2551
2552 __ branch_optimized(Assembler::bcondAlways, *success);
2553 }
2554
2555 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2556 LIR_Code code = op->code();
2557 if (code == lir_store_check) {
2558 Register value = op->object()->as_register();
2559 Register array = op->array()->as_register();
2560 Register k_RInfo = op->tmp1()->as_register();
2561 Register klass_RInfo = op->tmp2()->as_register();
2562 Register Rtmp1 = Z_R1_scratch;
2563
2564 CodeStub* stub = op->stub();
2565
2566 // Check if it needs to be profiled.
2567 ciMethodData* md = nullptr;
2568 ciProfileData* data = nullptr;
2569
2570 assert_different_registers(value, k_RInfo, klass_RInfo);
2571
2572 if (op->should_profile()) {
2573 ciMethod* method = op->profiled_method();
2574 assert(method != nullptr, "Should have method");
2575 int bci = op->profiled_bci();
2576 md = method->method_data_or_null();
2577 assert(md != nullptr, "Sanity");
2578 data = md->bci_to_data(bci);
2579 assert(data != nullptr, "need data for type check");
2580 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2581 }
2582 NearLabel done;
2583 Label *success_target = &done;
2584 Label *failure_target = stub->entry();
2585
2586 if (op->should_profile()) {
2587 Register mdo = klass_RInfo;
2588 metadata2reg(md->constant_encoding(), mdo);
2589 NearLabel not_null;
2590 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2591 // Object is null; update MDO and exit.
2592 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2593 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2594 __ or2mem_8(data_addr, header_bits);
2595 __ branch_optimized(Assembler::bcondAlways, done);
2596 __ bind(not_null);
2597
2598 NearLabel update_done;
2599 Register recv = k_RInfo;
2600 __ load_klass(recv, value);
2601 type_profile_helper(mdo, md, data, recv, Rtmp1, &update_done);
2602 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2603 __ add2mem_64(counter_addr, DataLayout::counter_increment, Rtmp1);
2604 __ bind(update_done);
2605 } else {
2606 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2607 }
2608
2609 add_debug_info_for_null_check_here(op->info_for_exception());
2610 __ load_klass(k_RInfo, array);
2611 __ load_klass(klass_RInfo, value);
2612
2613 // Get instance klass (it's already uncompressed).
2614 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2615 // Perform the fast part of the checking logic.
2616 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
2617 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2618 address a = Runtime1::entry_for (C1StubId::slow_subtype_check_id);
2619 store_parameter(klass_RInfo, 0); // sub
2620 store_parameter(k_RInfo, 1); // super
2621 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2622 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2623 // Fall through to success case.
2624
2625 __ bind(done);
2626 } else {
2627 if (code == lir_checkcast) {
2628 Register obj = op->object()->as_register();
2629 Register dst = op->result_opr()->as_register();
2630 NearLabel success;
2631 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2632 __ bind(success);
2633 __ lgr_if_needed(dst, obj);
2634 } else {
2635 if (code == lir_instanceof) {
2636 Register obj = op->object()->as_register();
2637 Register dst = op->result_opr()->as_register();
2638 NearLabel success, failure, done;
2639 emit_typecheck_helper(op, &success, &failure, &failure);
2640 __ bind(failure);
2641 __ clear_reg(dst);
2642 __ branch_optimized(Assembler::bcondAlways, done);
2643 __ bind(success);
2644 __ load_const_optimized(dst, 1);
2645 __ bind(done);
2646 } else {
2647 ShouldNotReachHere();
2648 }
2649 }
2650 }
2651 }
2652
2653 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2654 Register addr = op->addr()->as_pointer_register();
2655 Register t1_cmp = Z_R1_scratch;
2656 if (op->code() == lir_cas_long) {
2657 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2658 Register new_value_lo = op->new_value()->as_register_lo();
2659 __ z_lgr(t1_cmp, cmp_value_lo);
2660 // Perform the compare and swap operation.
2661 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2662 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2663 Register cmp_value = op->cmp_value()->as_register();
2664 Register new_value = op->new_value()->as_register();
2665 if (op->code() == lir_cas_obj) {
2666 if (UseCompressedOops) {
2667 t1_cmp = op->tmp1()->as_register();
2668 Register t2_new = op->tmp2()->as_register();
2669 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2670 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2671 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2672 __ z_cs(t1_cmp, t2_new, 0, addr);
2673 } else {
2674 __ z_lgr(t1_cmp, cmp_value);
2675 __ z_csg(t1_cmp, new_value, 0, addr);
2676 }
2677 } else {
2678 __ z_lr(t1_cmp, cmp_value);
2679 __ z_cs(t1_cmp, new_value, 0, addr);
2680 }
2681 } else {
2682 ShouldNotReachHere(); // new lir_cas_??
2683 }
2684 }
2685
2686 void LIR_Assembler::breakpoint() {
2687 Unimplemented();
2688 // __ breakpoint_trap();
2689 }
2690
2691 void LIR_Assembler::push(LIR_Opr opr) {
2692 ShouldNotCallThis(); // unused
2693 }
2694
2695 void LIR_Assembler::pop(LIR_Opr opr) {
2696 ShouldNotCallThis(); // unused
2697 }
2698
2699 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2700 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2701 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2702 }
2703
2704 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2705 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2706 Register hdr = op->hdr_opr()->as_register();
2707 Register lock = op->lock_opr()->as_register();
2708 if (LockingMode == LM_MONITOR) {
2709 if (op->info() != nullptr) {
2710 add_debug_info_for_null_check_here(op->info());
2711 __ null_check(obj);
2712 }
2713 __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry());
2714 } else if (op->code() == lir_lock) {
2715 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2716 // Add debug info for NullPointerException only if one is possible.
2717 if (op->info() != nullptr) {
2718 add_debug_info_for_null_check_here(op->info());
2719 }
2720 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2721 // done
2722 } else if (op->code() == lir_unlock) {
2723 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2724 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2725 } else {
2726 ShouldNotReachHere();
2727 }
2728 __ bind(*op->stub()->continuation());
2729 }
2730
2731 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2732 Register obj = op->obj()->as_pointer_register();
2733 Register result = op->result_opr()->as_pointer_register();
2734
2735 CodeEmitInfo* info = op->info();
2736 if (info != nullptr) {
2737 add_debug_info_for_null_check_here(info);
2738 }
2739
2740 if (UseCompressedClassPointers) {
2741 __ z_llgf(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2742 __ decode_klass_not_null(result);
2743 } else {
2744 __ z_lg(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2745 }
2746 }
2747 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2748 ciMethod* method = op->profiled_method();
2749 int bci = op->profiled_bci();
2750 ciMethod* callee = op->profiled_callee();
2751
2752 // Update counter for all call types.
2753 ciMethodData* md = method->method_data_or_null();
2754 assert(md != nullptr, "Sanity");
2755 ciProfileData* data = md->bci_to_data(bci);
2756 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2757 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2758 Register mdo = op->mdo()->as_register();
2759 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2760 Register tmp1 = op->tmp1()->as_register_lo();
2761 metadata2reg(md->constant_encoding(), mdo);
2762
2763 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2764 // Perform additional virtual call profiling for invokevirtual and
2765 // invokeinterface bytecodes
2766 if (op->should_profile_receiver_type()) {
2767 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2768 Register recv = op->recv()->as_register();
2769 assert_different_registers(mdo, tmp1, recv);
2770 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2771 ciKlass* known_klass = op->known_holder();
2772 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2773 // We know the type that will be seen at this call site; we can
2774 // statically update the MethodData* rather than needing to do
2775 // dynamic tests on the receiver type.
2776
2777 // NOTE: we should probably put a lock around this search to
2778 // avoid collisions by concurrent compilations.
2779 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2780 uint i;
2781 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2782 ciKlass* receiver = vc_data->receiver(i);
2783 if (known_klass->equals(receiver)) {
2784 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2785 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2786 return;
2787 }
2788 }
2789
2790 // Receiver type not found in profile data. Select an empty slot.
2791
2792 // Note that this is less efficient than it should be because it
2793 // always does a write to the receiver part of the
2794 // VirtualCallData rather than just the first time.
2795 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2796 ciKlass* receiver = vc_data->receiver(i);
2797 if (receiver == nullptr) {
2798 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2799 metadata2reg(known_klass->constant_encoding(), tmp1);
2800 __ z_stg(tmp1, recv_addr);
2801 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2802 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2803 return;
2804 }
2805 }
2806 } else {
2807 __ load_klass(recv, recv);
2808 NearLabel update_done;
2809 type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2810 // Receiver did not match any saved receiver and there is no empty row for it.
2811 // Increment total counter to indicate polymorphic case.
2812 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2813 __ bind(update_done);
2814 }
2815 } else {
2816 // static call
2817 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2818 }
2819 }
2820
2821 void LIR_Assembler::align_backward_branch_target() {
2822 __ align(OptoLoopAlignment);
2823 }
2824
2825 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2826 ShouldNotCallThis(); // There are no delay slots on ZARCH_64.
2827 }
2828
2829 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2830 // tmp must be unused
2831 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2832 assert(left->is_register(), "can only handle registers");
2833
2834 if (left->is_single_cpu()) {
2835 __ z_lcr(dest->as_register(), left->as_register());
2836 } else if (left->is_single_fpu()) {
2837 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2838 } else if (left->is_double_fpu()) {
2839 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2840 } else {
2841 assert(left->is_double_cpu(), "Must be a long");
2842 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2843 }
2844 }
2845
2846 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2847 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2848 assert(!tmp->is_valid(), "don't need temporary");
2849 emit_call_c(dest);
2850 CHECK_BAILOUT();
2851 if (info != nullptr) {
2852 add_call_info_here(info);
2853 }
2854 }
2855
2856 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2857 ShouldNotCallThis(); // not needed on ZARCH_64
2858 }
2859
2860 void LIR_Assembler::membar() {
2861 __ z_fence();
2862 }
2863
2864 void LIR_Assembler::membar_acquire() {
2865 __ z_acquire();
2866 }
2867
2868 void LIR_Assembler::membar_release() {
2869 __ z_release();
2870 }
2871
2872 void LIR_Assembler::membar_loadload() {
2873 __ z_acquire();
2874 }
2875
2876 void LIR_Assembler::membar_storestore() {
2877 __ z_release();
2878 }
2879
2880 void LIR_Assembler::membar_loadstore() {
2881 __ z_acquire();
2882 }
2883
2884 void LIR_Assembler::membar_storeload() {
2885 __ z_fence();
2886 }
2887
2888 void LIR_Assembler::on_spin_wait() {
2889 Unimplemented();
2890 }
2891
2892 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2893 assert(patch_code == lir_patch_none, "Patch code not supported");
2894 LIR_Address* addr = addr_opr->as_address_ptr();
2895 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2896 __ load_address(dest->as_pointer_register(), as_Address(addr));
2897 }
2898
2899 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2900 ShouldNotCallThis(); // unused
2901 }
2902
2903 #ifdef ASSERT
2904 // Emit run-time assertion.
2905 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2906 Unimplemented();
2907 }
2908 #endif
2909
2910 void LIR_Assembler::peephole(LIR_List*) {
2911 // Do nothing for now.
2912 }
2913
2914 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2915 assert(code == lir_xadd, "lir_xchg not supported");
2916 Address src_addr = as_Address(src->as_address_ptr());
2917 Register base = src_addr.base();
2918 intptr_t disp = src_addr.disp();
2919 if (src_addr.index()->is_valid()) {
2920 // LAA and LAAG do not support index register.
2921 __ load_address(Z_R1_scratch, src_addr);
2922 base = Z_R1_scratch;
2923 disp = 0;
2924 }
2925 if (data->type() == T_INT) {
2926 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2927 } else if (data->type() == T_LONG) {
2928 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2929 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2930 } else {
2931 ShouldNotReachHere();
2932 }
2933 }
2934
2935 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2936 Register obj = op->obj()->as_register();
2937 Register tmp1 = op->tmp()->as_pointer_register();
2938 Register tmp2 = Z_R1_scratch;
2939 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2940 ciKlass* exact_klass = op->exact_klass();
2941 intptr_t current_klass = op->current_klass();
2942 bool not_null = op->not_null();
2943 bool no_conflict = op->no_conflict();
2944
2945 Label update, next, none, null_seen, init_klass;
2946
2947 bool do_null = !not_null;
2948 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2949 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2950
2951 assert(do_null || do_update, "why are we here?");
2952 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2953
2954 __ verify_oop(obj, FILE_AND_LINE);
2955
2956 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2957 __ z_ltgr(tmp1, obj);
2958 }
2959 if (do_null) {
2960 __ z_brnz(update);
2961 if (!TypeEntries::was_null_seen(current_klass)) {
2962 __ z_lg(tmp1, mdo_addr);
2963 __ z_oill(tmp1, TypeEntries::null_seen);
2964 __ z_stg(tmp1, mdo_addr);
2965 }
2966 if (do_update) {
2967 __ z_bru(next);
2968 }
2969 } else {
2970 __ asm_assert(Assembler::bcondNotZero, "unexpected null obj", __LINE__);
2971 }
2972
2973 __ bind(update);
2974
2975 if (do_update) {
2976 #ifdef ASSERT
2977 if (exact_klass != nullptr) {
2978 __ load_klass(tmp1, tmp1);
2979 metadata2reg(exact_klass->constant_encoding(), tmp2);
2980 __ z_cgr(tmp1, tmp2);
2981 __ asm_assert(Assembler::bcondEqual, "exact klass and actual klass differ", __LINE__);
2982 }
2983 #endif
2984
2985 Label do_update;
2986 __ z_lg(tmp2, mdo_addr);
2987
2988 if (!no_conflict) {
2989 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2990 if (exact_klass != nullptr) {
2991 metadata2reg(exact_klass->constant_encoding(), tmp1);
2992 } else {
2993 __ load_klass(tmp1, tmp1);
2994 }
2995
2996 // Klass seen before: nothing to do (regardless of unknown bit).
2997 __ z_lgr(Z_R0_scratch, tmp2);
2998 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2999 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3000 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3001
3002 // Already unknown: Nothing to do anymore.
3003 __ z_tmll(tmp2, TypeEntries::type_unknown);
3004 __ z_brc(Assembler::bcondAllOne, next);
3005
3006 if (TypeEntries::is_type_none(current_klass)) {
3007 __ z_lgr(Z_R0_scratch, tmp2);
3008 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3009 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3010 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
3011 }
3012 } else {
3013 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3014 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3015
3016 // Already unknown: Nothing to do anymore.
3017 __ z_tmll(tmp2, TypeEntries::type_unknown);
3018 __ z_brc(Assembler::bcondAllOne, next);
3019 }
3020
3021 // Different than before. Cannot keep accurate profile.
3022 __ z_oill(tmp2, TypeEntries::type_unknown);
3023 __ z_bru(do_update);
3024 } else {
3025 // There's a single possible klass at this profile point.
3026 assert(exact_klass != nullptr, "should be");
3027 if (TypeEntries::is_type_none(current_klass)) {
3028 metadata2reg(exact_klass->constant_encoding(), tmp1);
3029 __ z_lgr(Z_R0_scratch, tmp2);
3030 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3031 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3032 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3033 #ifdef ASSERT
3034 {
3035 Label ok;
3036 __ z_lgr(Z_R0_scratch, tmp2);
3037 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3038 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3039 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
3040 __ stop("unexpected profiling mismatch");
3041 __ bind(ok);
3042 }
3043 #endif
3044
3045 } else {
3046 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3047 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3048
3049 // Already unknown: Nothing to do anymore.
3050 __ z_tmll(tmp2, TypeEntries::type_unknown);
3051 __ z_brc(Assembler::bcondAllOne, next);
3052 __ z_oill(tmp2, TypeEntries::type_unknown);
3053 __ z_bru(do_update);
3054 }
3055 }
3056
3057 __ bind(init_klass);
3058 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3059 __ z_ogr(tmp2, tmp1);
3060
3061 __ bind(do_update);
3062 __ z_stg(tmp2, mdo_addr);
3063
3064 __ bind(next);
3065 }
3066 }
3067
3068 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3069 assert(op->crc()->is_single_cpu(), "crc must be register");
3070 assert(op->val()->is_single_cpu(), "byte value must be register");
3071 assert(op->result_opr()->is_single_cpu(), "result must be register");
3072 Register crc = op->crc()->as_register();
3073 Register val = op->val()->as_register();
3074 Register res = op->result_opr()->as_register();
3075
3076 assert_different_registers(val, crc, res);
3077
3078 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3079 __ kernel_crc32_singleByteReg(crc, val, res, true);
3080 __ z_lgfr(res, crc);
3081 }
3082
3083 #undef __