1 /*
2 * Copyright (c) 2016, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_s390.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/safepointMechanism.inline.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "utilities/macros.hpp"
44 #include "utilities/powerOfTwo.hpp"
45 #include "vmreg_s390.inline.hpp"
46
47 #define __ _masm->
48
49 #ifndef PRODUCT
50 #undef __
51 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
52 #endif
53
54 //------------------------------------------------------------
55
56 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
57 // Not used on ZARCH_64
58 ShouldNotCallThis();
59 return false;
60 }
61
62 LIR_Opr LIR_Assembler::receiverOpr() {
63 return FrameMap::Z_R2_oop_opr;
64 }
65
66 LIR_Opr LIR_Assembler::osrBufferPointer() {
67 return FrameMap::Z_R2_opr;
68 }
69
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74 // Inline cache check: done before the frame is built.
75 // The inline cached class is in Z_inline_cache(Z_R9).
76 // We fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to the slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = Z_R1_scratch;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
92 __ z_br(klass);
93
94 __ bind(L_skip_barrier);
95 }
96
97 void LIR_Assembler::osr_entry() {
98 // On-stack-replacement entry sequence (interpreter frame layout described in frame_s390.hpp):
99 //
100 // 1. Create a new compiled activation.
101 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
102 // at the osr_bci; it is not initialized.
103 // 3. Jump to the continuation address in compiled code to resume execution.
104
105 // OSR entry point
106 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
107 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
108 ValueStack* entry_state = osr_entry->end()->state();
109 int number_of_locks = entry_state->locks_size();
110
111 // Create a frame for the compiled activation.
112 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
113
114 // OSR buffer is
115 //
116 // locals[nlocals-1..0]
117 // monitors[number_of_locks-1..0]
118 //
119 // Locals is a direct copy of the interpreter frame so in the osr buffer
120 // the first slot in the local array is the last local from the interpreter
121 // and the last slot is local[0] (receiver) from the interpreter
122 //
123 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
124 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
125 // in the interpreter frame (the method lock if a sync method)
126
127 // Initialize monitors in the compiled activation.
128 // I0: pointer to osr buffer
129 //
130 // All other registers are dead at this point and the locals will be
131 // copied into place by code emitted in the IR.
132
133 Register OSR_buf = osrBufferPointer()->as_register();
134 {
135 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
136
137 const int locals_space = BytesPerWord * method() -> max_locals();
138 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
139 bool large_offset = !Immediate::is_simm20(monitor_offset + BytesPerWord) && number_of_locks > 0;
140
141 if (large_offset) {
142 // z_lg can only handle displacement upto 20bit signed binary integer
143 __ z_algfi(OSR_buf, locals_space);
144 monitor_offset -= locals_space;
145 }
146
147 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
148 // the OSR buffer using 2 word entries: first the lock and then
149 // the oop.
150 for (int i = 0; i < number_of_locks; i++) {
151 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
152 // Verify the interpreter's monitor has a non-null object.
153 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is null", __LINE__);
154 // Copy the lock field into the compiled activation.
155 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
156 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
157 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
158 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
159 }
160
161 if (large_offset) {
162 __ z_slgfi(OSR_buf, locals_space);
163 }
164 }
165 }
166
167 // --------------------------------------------------------------------------------------------
168
169 address LIR_Assembler::emit_call_c(address a) {
170 __ align_call_far_patchable(__ pc());
171 address call_addr = __ call_c_opt(a);
172 if (call_addr == nullptr) {
173 bailout("const section overflow");
174 }
175 return call_addr;
176 }
177
178 int LIR_Assembler::emit_exception_handler() {
179 // Generate code for exception handler.
180 address handler_base = __ start_a_stub(exception_handler_size());
181 if (handler_base == nullptr) {
182 // Not enough space left for the handler.
183 bailout("exception handler overflow");
184 return -1;
185 }
186
187 int offset = code_offset();
188
189 address a = Runtime1::entry_for (StubId::c1_handle_exception_from_callee_id);
190 address call_addr = emit_call_c(a);
191 CHECK_BAILOUT_(-1);
192 __ should_not_reach_here();
193 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
194 __ end_a_stub();
195
196 return offset;
197 }
198
199 // Emit the code to remove the frame from the stack in the exception
200 // unwind path.
201 int LIR_Assembler::emit_unwind_handler() {
202 #ifndef PRODUCT
203 if (CommentedAssembly) {
204 _masm->block_comment("Unwind handler");
205 }
206 #endif
207
208 int offset = code_offset();
209 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
210 Register Rtmp1 = Z_R11;
211 Register Rtmp2 = Z_R12;
212
213 // Fetch the exception from TLS and clear out exception related thread state.
214 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
215 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
216 __ z_lg(Z_EXC_OOP, exc_oop_addr);
217 __ clear_mem(exc_oop_addr, sizeof(oop));
218 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
219
220 __ bind(_unwind_handler_entry);
221 __ verify_not_null_oop(Z_EXC_OOP);
222 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
223 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
224 }
225
226 // Perform needed unlocking.
227 MonitorExitStub* stub = nullptr;
228 if (method()->is_synchronized()) {
229 // StubId::c1_monitorexit_id expects lock address in Z_R1_scratch.
230 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
231 monitor_address(0, lock);
232 stub = new MonitorExitStub(lock, 0);
233 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
234 __ bind(*stub->continuation());
235 }
236
237 if (compilation()->env()->dtrace_method_probes()) {
238 ShouldNotReachHere(); // Not supported.
239 #if 0
240 __ mov(rdi, r15_thread);
241 __ mov_metadata(rsi, method()->constant_encoding());
242 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
243 #endif
244 }
245
246 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
247 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
248 }
249
250 // Remove the activation and dispatch to the unwind handler.
251 __ pop_frame();
252 __ z_lg(Z_EXC_PC, _z_common_abi(return_pc), Z_SP);
253
254 // Z_EXC_OOP: exception oop
255 // Z_EXC_PC: exception pc
256
257 // Dispatch to the unwind logic.
258 __ load_const_optimized(Z_R5, Runtime1::entry_for (StubId::c1_unwind_exception_id));
259 __ z_br(Z_R5);
260
261 // Emit the slow path assembly.
262 if (stub != nullptr) {
263 stub->emit_code(this);
264 }
265
266 return offset;
267 }
268
269 int LIR_Assembler::emit_deopt_handler() {
270 // Generate code for exception handler.
271 address handler_base = __ start_a_stub(deopt_handler_size());
272 if (handler_base == nullptr) {
273 // Not enough space left for the handler.
274 bailout("deopt handler overflow");
275 return -1;
276 }
277
278 int offset = code_offset();
279
280 Label start;
281 __ bind(start);
282
283 // Size must be constant (see HandlerImpl::emit_deopt_handler).
284 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
285 __ call(Z_R1_scratch);
286
287 int entry_offset = __ offset();
288
289 __ z_bru(start);
290
291 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
292 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
293 "out of bounds read in post-call NOP check");
294 __ end_a_stub();
295
296 return entry_offset;
297 }
298
299 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
300 if (o == nullptr) {
301 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
302 } else {
303 AddressLiteral a = __ allocate_oop_address(o);
304 bool success = __ load_oop_from_toc(reg, a, reg);
305 if (!success) {
306 bailout("const section overflow");
307 }
308 }
309 }
310
311 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
312 // Allocate a new index in table to hold the object once it's been patched.
313 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
314 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
315
316 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
317 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
318 // The null will be dynamically patched later so the sequence to
319 // load the address literal must not be optimized.
320 __ load_const(reg, addrlit);
321
322 patching_epilog(patch, lir_patch_normal, reg, info);
323 }
324
325 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
326 bool success = __ set_metadata_constant(md, reg);
327 if (!success) {
328 bailout("const section overflow");
329 return;
330 }
331 }
332
333 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
334 // Allocate a new index in table to hold the klass once it's been patched.
335 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
336 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
337 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
338 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
339 // The null will be dynamically patched later so the sequence to
340 // load the address literal must not be optimized.
341 __ load_const(reg, addrlit);
342
343 patching_epilog(patch, lir_patch_normal, reg, info);
344 }
345
346 void LIR_Assembler::emit_op3(LIR_Op3* op) {
347 switch (op->code()) {
348 case lir_idiv:
349 case lir_irem:
350 arithmetic_idiv(op->code(),
351 op->in_opr1(),
352 op->in_opr2(),
353 op->in_opr3(),
354 op->result_opr(),
355 op->info());
356 break;
357 case lir_fmad: {
358 const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
359 opr2 = op->in_opr2()->as_double_reg(),
360 opr3 = op->in_opr3()->as_double_reg(),
361 res = op->result_opr()->as_double_reg();
362 __ z_madbr(opr3, opr1, opr2);
363 if (res != opr3) { __ z_ldr(res, opr3); }
364 } break;
365 case lir_fmaf: {
366 const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
367 opr2 = op->in_opr2()->as_float_reg(),
368 opr3 = op->in_opr3()->as_float_reg(),
369 res = op->result_opr()->as_float_reg();
370 __ z_maebr(opr3, opr1, opr2);
371 if (res != opr3) { __ z_ler(res, opr3); }
372 } break;
373 default: ShouldNotReachHere(); break;
374 }
375 }
376
377
378 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
379 #ifdef ASSERT
380 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
381 if (op->block() != nullptr) { _branch_target_blocks.append(op->block()); }
382 if (op->ublock() != nullptr) { _branch_target_blocks.append(op->ublock()); }
383 #endif
384
385 if (op->cond() == lir_cond_always) {
386 if (op->info() != nullptr) { add_debug_info_for_branch(op->info()); }
387 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
388 } else {
389 Assembler::branch_condition acond = Assembler::bcondZero;
390 if (op->code() == lir_cond_float_branch) {
391 assert(op->ublock() != nullptr, "must have unordered successor");
392 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
393 }
394 switch (op->cond()) {
395 case lir_cond_equal: acond = Assembler::bcondEqual; break;
396 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
397 case lir_cond_less: acond = Assembler::bcondLow; break;
398 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
399 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
400 case lir_cond_greater: acond = Assembler::bcondHigh; break;
401 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
402 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
403 default: ShouldNotReachHere();
404 }
405 __ branch_optimized(acond,*(op->label()));
406 }
407 }
408
409
410 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
411 LIR_Opr src = op->in_opr();
412 LIR_Opr dest = op->result_opr();
413
414 switch (op->bytecode()) {
415 case Bytecodes::_i2l:
416 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
417 break;
418
419 case Bytecodes::_l2i:
420 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
421 break;
422
423 case Bytecodes::_i2b:
424 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
425 break;
426
427 case Bytecodes::_i2c:
428 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
429 break;
430
431 case Bytecodes::_i2s:
432 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
433 break;
434
435 case Bytecodes::_f2d:
436 assert(dest->is_double_fpu(), "check");
437 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
438 break;
439
440 case Bytecodes::_d2f:
441 assert(dest->is_single_fpu(), "check");
442 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
443 break;
444
445 case Bytecodes::_i2f:
446 __ z_cefbr(dest->as_float_reg(), src->as_register());
447 break;
448
449 case Bytecodes::_i2d:
450 __ z_cdfbr(dest->as_double_reg(), src->as_register());
451 break;
452
453 case Bytecodes::_l2f:
454 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
455 break;
456 case Bytecodes::_l2d:
457 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
458 break;
459
460 case Bytecodes::_f2i:
461 case Bytecodes::_f2l: {
462 Label done;
463 FloatRegister Rsrc = src->as_float_reg();
464 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
465 __ clear_reg(Rdst, true, false);
466 __ z_cebr(Rsrc, Rsrc);
467 __ z_brno(done); // NaN -> 0
468 if (op->bytecode() == Bytecodes::_f2i) {
469 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
470 } else { // op->bytecode() == Bytecodes::_f2l
471 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
472 }
473 __ bind(done);
474 }
475 break;
476
477 case Bytecodes::_d2i:
478 case Bytecodes::_d2l: {
479 Label done;
480 FloatRegister Rsrc = src->as_double_reg();
481 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
482 __ clear_reg(Rdst, true, false); // Don't set CC.
483 __ z_cdbr(Rsrc, Rsrc);
484 __ z_brno(done); // NaN -> 0
485 if (op->bytecode() == Bytecodes::_d2i) {
486 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
487 } else { // Bytecodes::_d2l
488 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
489 }
490 __ bind(done);
491 }
492 break;
493
494 default: ShouldNotReachHere();
495 }
496 }
497
498 void LIR_Assembler::align_call(LIR_Code code) {
499 // End of call instruction must be 4 byte aligned.
500 int offset = __ offset();
501 switch (code) {
502 case lir_icvirtual_call:
503 offset += MacroAssembler::load_const_from_toc_size();
504 // no break
505 case lir_static_call:
506 case lir_optvirtual_call:
507 case lir_dynamic_call:
508 offset += NativeCall::call_far_pcrelative_displacement_offset;
509 break;
510 default: ShouldNotReachHere();
511 }
512 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
513 __ nop();
514 }
515 }
516
517 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
518 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
519 "must be aligned (offset=%d)", __ offset());
520 assert(rtype == relocInfo::none ||
521 rtype == relocInfo::opt_virtual_call_type ||
522 rtype == relocInfo::static_call_type, "unexpected rtype");
523 // Prepend each BRASL with a nop.
524 __ relocate(rtype);
525 __ z_nop();
526 __ z_brasl(Z_R14, op->addr());
527 add_call_info(code_offset(), op->info());
528 __ post_call_nop();
529 }
530
531 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
532 address virtual_call_oop_addr = nullptr;
533 AddressLiteral empty_ic((address) Universe::non_oop_word());
534 virtual_call_oop_addr = __ pc();
535 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
536 if (!success) {
537 bailout("const section overflow");
538 return;
539 }
540
541 // CALL to fixup routine. Fixup routine uses ScopeDesc info
542 // to determine who we intended to call.
543 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
544 call(op, relocInfo::none); // call will emit a post call nop, see above method.
545 }
546
547 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
548 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
549 }
550
551 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
552 assert(src->is_constant(), "should not call otherwise");
553 assert(dest->is_stack(), "should not call otherwise");
554 LIR_Const* c = src->as_constant_ptr();
555
556 unsigned int lmem = 0;
557 unsigned int lcon = 0;
558 int64_t cbits = 0;
559 Address dest_addr;
560 switch (c->type()) {
561 case T_INT: // fall through
562 case T_FLOAT:
563 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
564 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
565 break;
566
567 case T_ADDRESS:
568 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
569 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
570 break;
571
572 case T_OBJECT:
573 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
574 if (c->as_jobject() == nullptr) {
575 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
576 } else {
577 jobject2reg(c->as_jobject(), Z_R1_scratch);
578 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
579 }
580 return;
581
582 case T_LONG: // fall through
583 case T_DOUBLE:
584 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
585 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
586 break;
587
588 default:
589 ShouldNotReachHere();
590 }
591
592 __ store_const(dest_addr, cbits, lmem, lcon);
593 }
594
595 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
596 assert(src->is_constant(), "should not call otherwise");
597 assert(dest->is_address(), "should not call otherwise");
598
599 LIR_Const* c = src->as_constant_ptr();
600 Address addr = as_Address(dest->as_address_ptr());
601
602 int store_offset = -1;
603
604 if (dest->as_address_ptr()->index()->is_valid()) {
605 switch (type) {
606 case T_INT: // fall through
607 case T_FLOAT:
608 __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
609 store_offset = __ offset();
610 if (Immediate::is_uimm12(addr.disp())) {
611 __ z_st(Z_R0_scratch, addr);
612 } else {
613 __ z_sty(Z_R0_scratch, addr);
614 }
615 break;
616
617 case T_ADDRESS:
618 __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
619 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
620 break;
621
622 case T_OBJECT: // fall through
623 case T_ARRAY:
624 if (c->as_jobject() == nullptr) {
625 if (UseCompressedOops && !wide) {
626 __ clear_reg(Z_R1_scratch, false);
627 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
628 } else {
629 __ clear_reg(Z_R1_scratch, true);
630 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
631 }
632 } else {
633 jobject2reg(c->as_jobject(), Z_R1_scratch);
634 if (UseCompressedOops && !wide) {
635 __ encode_heap_oop(Z_R1_scratch);
636 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
637 } else {
638 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
639 }
640 }
641 assert(store_offset >= 0, "check");
642 break;
643
644 case T_LONG: // fall through
645 case T_DOUBLE:
646 __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
647 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
648 break;
649
650 case T_BOOLEAN: // fall through
651 case T_BYTE:
652 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
653 store_offset = __ offset();
654 if (Immediate::is_uimm12(addr.disp())) {
655 __ z_stc(Z_R0_scratch, addr);
656 } else {
657 __ z_stcy(Z_R0_scratch, addr);
658 }
659 break;
660
661 case T_CHAR: // fall through
662 case T_SHORT:
663 __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
664 store_offset = __ offset();
665 if (Immediate::is_uimm12(addr.disp())) {
666 __ z_sth(Z_R0_scratch, addr);
667 } else {
668 __ z_sthy(Z_R0_scratch, addr);
669 }
670 break;
671
672 default:
673 ShouldNotReachHere();
674 }
675
676 } else { // no index
677
678 unsigned int lmem = 0;
679 unsigned int lcon = 0;
680 int64_t cbits = 0;
681
682 switch (type) {
683 case T_INT: // fall through
684 case T_FLOAT:
685 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
686 break;
687
688 case T_ADDRESS:
689 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
690 break;
691
692 case T_OBJECT: // fall through
693 case T_ARRAY:
694 if (c->as_jobject() == nullptr) {
695 if (UseCompressedOops && !wide) {
696 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
697 } else {
698 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
699 }
700 } else {
701 jobject2reg(c->as_jobject(), Z_R1_scratch);
702 if (UseCompressedOops && !wide) {
703 __ encode_heap_oop(Z_R1_scratch);
704 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
705 } else {
706 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
707 }
708 }
709 assert(store_offset >= 0, "check");
710 break;
711
712 case T_LONG: // fall through
713 case T_DOUBLE:
714 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
715 break;
716
717 case T_BOOLEAN: // fall through
718 case T_BYTE:
719 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
720 break;
721
722 case T_CHAR: // fall through
723 case T_SHORT:
724 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
725 break;
726
727 default:
728 ShouldNotReachHere();
729 }
730
731 if (store_offset == -1) {
732 store_offset = __ store_const(addr, cbits, lmem, lcon);
733 assert(store_offset >= 0, "check");
734 }
735 }
736
737 if (info != nullptr) {
738 add_debug_info_for_null_check(store_offset, info);
739 }
740 }
741
742 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
743 assert(src->is_constant(), "should not call otherwise");
744 assert(dest->is_register(), "should not call otherwise");
745 LIR_Const* c = src->as_constant_ptr();
746
747 switch (c->type()) {
748 case T_INT: {
749 assert(patch_code == lir_patch_none, "no patching handled here");
750 __ load_const_optimized(dest->as_register(), c->as_jint());
751 break;
752 }
753
754 case T_ADDRESS: {
755 assert(patch_code == lir_patch_none, "no patching handled here");
756 __ load_const_optimized(dest->as_register(), c->as_jint());
757 break;
758 }
759
760 case T_LONG: {
761 assert(patch_code == lir_patch_none, "no patching handled here");
762 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
763 break;
764 }
765
766 case T_OBJECT: {
767 if (patch_code != lir_patch_none) {
768 jobject2reg_with_patching(dest->as_register(), info);
769 } else {
770 jobject2reg(c->as_jobject(), dest->as_register());
771 }
772 break;
773 }
774
775 case T_METADATA: {
776 if (patch_code != lir_patch_none) {
777 klass2reg_with_patching(dest->as_register(), info);
778 } else {
779 metadata2reg(c->as_metadata(), dest->as_register());
780 }
781 break;
782 }
783
784 case T_FLOAT: {
785 Register toc_reg = Z_R1_scratch;
786 __ load_toc(toc_reg);
787 address const_addr = __ float_constant(c->as_jfloat());
788 if (const_addr == nullptr) {
789 bailout("const section overflow");
790 break;
791 }
792 int displ = const_addr - _masm->code()->consts()->start();
793 if (dest->is_single_fpu()) {
794 __ z_ley(dest->as_float_reg(), displ, toc_reg);
795 } else {
796 assert(dest->is_single_cpu(), "Must be a cpu register.");
797 __ z_ly(dest->as_register(), displ, toc_reg);
798 }
799 }
800 break;
801
802 case T_DOUBLE: {
803 Register toc_reg = Z_R1_scratch;
804 __ load_toc(toc_reg);
805 address const_addr = __ double_constant(c->as_jdouble());
806 if (const_addr == nullptr) {
807 bailout("const section overflow");
808 break;
809 }
810 int displ = const_addr - _masm->code()->consts()->start();
811 if (dest->is_double_fpu()) {
812 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
813 } else {
814 assert(dest->is_double_cpu(), "Must be a long register.");
815 __ z_lg(dest->as_register_lo(), displ, toc_reg);
816 }
817 }
818 break;
819
820 default:
821 ShouldNotReachHere();
822 }
823 }
824
825 Address LIR_Assembler::as_Address(LIR_Address* addr) {
826 if (addr->base()->is_illegal()) {
827 Unimplemented();
828 }
829
830 Register base = addr->base()->as_pointer_register();
831
832 if (addr->index()->is_illegal()) {
833 return Address(base, addr->disp());
834 } else if (addr->index()->is_cpu_register()) {
835 Register index = addr->index()->as_pointer_register();
836 return Address(base, index, addr->disp());
837 } else if (addr->index()->is_constant()) {
838 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
839 return Address(base, addr_offset);
840 } else {
841 ShouldNotReachHere();
842 return Address();
843 }
844 }
845
846 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
847 switch (type) {
848 case T_INT:
849 case T_FLOAT: {
850 Register tmp = Z_R1_scratch;
851 Address from = frame_map()->address_for_slot(src->single_stack_ix());
852 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
853 __ mem2reg_opt(tmp, from, false);
854 __ reg2mem_opt(tmp, to, false);
855 break;
856 }
857 case T_ADDRESS:
858 case T_OBJECT: {
859 Register tmp = Z_R1_scratch;
860 Address from = frame_map()->address_for_slot(src->single_stack_ix());
861 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
862 __ mem2reg_opt(tmp, from, true);
863 __ reg2mem_opt(tmp, to, true);
864 break;
865 }
866 case T_LONG:
867 case T_DOUBLE: {
868 Register tmp = Z_R1_scratch;
869 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
870 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
871 __ mem2reg_opt(tmp, from, true);
872 __ reg2mem_opt(tmp, to, true);
873 break;
874 }
875
876 default:
877 ShouldNotReachHere();
878 }
879 }
880
881 // 4-byte accesses only! Don't use it to access 8 bytes!
882 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
883 ShouldNotCallThis();
884 return Address(); // unused
885 }
886
887 // 4-byte accesses only! Don't use it to access 8 bytes!
888 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
889 ShouldNotCallThis();
890 return Address(); // unused
891 }
892
893 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
894 CodeEmitInfo* info, bool wide) {
895
896 assert(type != T_METADATA, "load of metadata ptr not supported");
897 LIR_Address* addr = src_opr->as_address_ptr();
898 LIR_Opr to_reg = dest;
899
900 Register src = addr->base()->as_pointer_register();
901 Register disp_reg = Z_R0;
902 int disp_value = addr->disp();
903 bool needs_patching = (patch_code != lir_patch_none);
904
905 if (addr->base()->type() == T_OBJECT) {
906 __ verify_oop(src, FILE_AND_LINE);
907 }
908
909 PatchingStub* patch = nullptr;
910 if (needs_patching) {
911 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
912 assert(!to_reg->is_double_cpu() ||
913 patch_code == lir_patch_none ||
914 patch_code == lir_patch_normal, "patching doesn't match register");
915 }
916
917 if (addr->index()->is_illegal()) {
918 if (!Immediate::is_simm20(disp_value)) {
919 if (needs_patching) {
920 __ load_const(Z_R1_scratch, (intptr_t)0);
921 } else {
922 __ load_const_optimized(Z_R1_scratch, disp_value);
923 }
924 disp_reg = Z_R1_scratch;
925 disp_value = 0;
926 }
927 } else {
928 if (!Immediate::is_simm20(disp_value)) {
929 __ load_const_optimized(Z_R1_scratch, disp_value);
930 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
931 disp_reg = Z_R1_scratch;
932 disp_value = 0;
933 }
934 disp_reg = addr->index()->as_pointer_register();
935 }
936
937 // Remember the offset of the load. The patching_epilog must be done
938 // before the call to add_debug_info, otherwise the PcDescs don't get
939 // entered in increasing order.
940 int offset = code_offset();
941
942 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
943
944 bool short_disp = Immediate::is_uimm12(disp_value);
945
946 switch (type) {
947 case T_BOOLEAN: // fall through
948 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
949 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
950 case T_SHORT :
951 if (short_disp) {
952 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
953 } else {
954 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
955 }
956 break;
957 case T_INT :
958 if (short_disp) {
959 __ z_l(dest->as_register(), disp_value, disp_reg, src);
960 } else {
961 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
962 }
963 break;
964 case T_ADDRESS:
965 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
966 break;
967 case T_ARRAY : // fall through
968 case T_OBJECT:
969 {
970 if (UseCompressedOops && !wide) {
971 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
972 __ oop_decoder(dest->as_register(), dest->as_register(), true);
973 } else {
974 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
975 }
976 break;
977 }
978 case T_FLOAT:
979 if (short_disp) {
980 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
981 } else {
982 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
983 }
984 break;
985 case T_DOUBLE:
986 if (short_disp) {
987 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
988 } else {
989 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
990 }
991 break;
992 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
993 default : ShouldNotReachHere();
994 }
995
996 if (patch != nullptr) {
997 patching_epilog(patch, patch_code, src, info);
998 }
999 if (info != nullptr) add_debug_info_for_null_check(offset, info);
1000 }
1001
1002 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1003 assert(src->is_stack(), "should not call otherwise");
1004 assert(dest->is_register(), "should not call otherwise");
1005
1006 if (dest->is_single_cpu()) {
1007 if (is_reference_type(type)) {
1008 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1009 } else if (type == T_METADATA || type == T_ADDRESS) {
1010 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1011 } else {
1012 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
1013 }
1014 } else if (dest->is_double_cpu()) {
1015 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
1016 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
1017 } else if (dest->is_single_fpu()) {
1018 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1019 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
1020 } else if (dest->is_double_fpu()) {
1021 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1022 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
1023 } else {
1024 ShouldNotReachHere();
1025 }
1026 }
1027
1028 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1029 assert(src->is_register(), "should not call otherwise");
1030 assert(dest->is_stack(), "should not call otherwise");
1031
1032 if (src->is_single_cpu()) {
1033 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1034 if (is_reference_type(type)) {
1035 if (VerifyOops) {
1036 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1037 bs->check_oop(_masm, src->as_register(), FILE_AND_LINE);
1038 }
1039 __ reg2mem_opt(src->as_register(), dst, true);
1040 } else if (type == T_METADATA || type == T_ADDRESS) {
1041 __ reg2mem_opt(src->as_register(), dst, true);
1042 } else {
1043 __ reg2mem_opt(src->as_register(), dst, false);
1044 }
1045 } else if (src->is_double_cpu()) {
1046 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1047 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1048 } else if (src->is_single_fpu()) {
1049 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1050 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1051 } else if (src->is_double_fpu()) {
1052 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1053 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1054 } else {
1055 ShouldNotReachHere();
1056 }
1057 }
1058
1059 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1060 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1061 if (from_reg->is_double_fpu()) {
1062 // double to double moves
1063 assert(to_reg->is_double_fpu(), "should match");
1064 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1065 } else {
1066 // float to float moves
1067 assert(to_reg->is_single_fpu(), "should match");
1068 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1069 }
1070 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1071 if (from_reg->is_double_cpu()) {
1072 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1073 } else if (to_reg->is_double_cpu()) {
1074 // int to int moves
1075 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1076 } else {
1077 // int to int moves
1078 __ z_lgr(to_reg->as_register(), from_reg->as_register());
1079 }
1080 } else {
1081 ShouldNotReachHere();
1082 }
1083 if (is_reference_type(to_reg->type())) {
1084 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1085 }
1086 }
1087
1088 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1089 LIR_PatchCode patch_code, CodeEmitInfo* info,
1090 bool wide) {
1091 assert(type != T_METADATA, "store of metadata ptr not supported");
1092 LIR_Address* addr = dest_opr->as_address_ptr();
1093
1094 Register dest = addr->base()->as_pointer_register();
1095 Register disp_reg = Z_R0;
1096 int disp_value = addr->disp();
1097 bool needs_patching = (patch_code != lir_patch_none);
1098
1099 if (addr->base()->is_oop_register()) {
1100 __ verify_oop(dest, FILE_AND_LINE);
1101 }
1102
1103 PatchingStub* patch = nullptr;
1104 if (needs_patching) {
1105 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1106 assert(!from->is_double_cpu() ||
1107 patch_code == lir_patch_none ||
1108 patch_code == lir_patch_normal, "patching doesn't match register");
1109 }
1110
1111 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1112 if (addr->index()->is_illegal()) {
1113 if (!Immediate::is_simm20(disp_value)) {
1114 if (needs_patching) {
1115 __ load_const(Z_R1_scratch, (intptr_t)0);
1116 } else {
1117 __ load_const_optimized(Z_R1_scratch, disp_value);
1118 }
1119 disp_reg = Z_R1_scratch;
1120 disp_value = 0;
1121 }
1122 } else {
1123 if (!Immediate::is_simm20(disp_value)) {
1124 __ load_const_optimized(Z_R1_scratch, disp_value);
1125 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1126 disp_reg = Z_R1_scratch;
1127 disp_value = 0;
1128 }
1129 disp_reg = addr->index()->as_pointer_register();
1130 }
1131
1132 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1133
1134 if (is_reference_type(type) && VerifyOops) {
1135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1136 bs->check_oop(_masm, from->as_register(), FILE_AND_LINE);
1137 }
1138
1139 bool short_disp = Immediate::is_uimm12(disp_value);
1140
1141 // Remember the offset of the store. The patching_epilog must be done
1142 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1143 // entered in increasing order.
1144 int offset = code_offset();
1145 switch (type) {
1146 case T_BOOLEAN: // fall through
1147 case T_BYTE :
1148 if (short_disp) {
1149 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1150 } else {
1151 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1152 }
1153 break;
1154 case T_CHAR : // fall through
1155 case T_SHORT :
1156 if (short_disp) {
1157 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1158 } else {
1159 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1160 }
1161 break;
1162 case T_INT :
1163 if (short_disp) {
1164 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1165 } else {
1166 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1167 }
1168 break;
1169 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1170 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1171 break;
1172 case T_ARRAY : // fall through
1173 case T_OBJECT:
1174 {
1175 if (UseCompressedOops && !wide) {
1176 Register compressed_src = Z_R14;
1177 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1178 offset = code_offset();
1179 if (short_disp) {
1180 __ z_st(compressed_src, disp_value, disp_reg, dest);
1181 } else {
1182 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1183 }
1184 } else {
1185 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1186 }
1187 break;
1188 }
1189 case T_FLOAT :
1190 if (short_disp) {
1191 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1192 } else {
1193 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1194 }
1195 break;
1196 case T_DOUBLE:
1197 if (short_disp) {
1198 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1199 } else {
1200 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1201 }
1202 break;
1203 default: ShouldNotReachHere();
1204 }
1205
1206 if (patch != nullptr) {
1207 patching_epilog(patch, patch_code, dest, info);
1208 }
1209
1210 if (info != nullptr) add_debug_info_for_null_check(offset, info);
1211 }
1212
1213
1214 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1215 assert(result->is_illegal() ||
1216 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1217 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1218 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1219 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1220
1221 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1222
1223 // Pop the frame before the safepoint code.
1224 __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1225
1226 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1227 __ reserved_stack_check(Z_R14);
1228 }
1229
1230 // We need to mark the code position where the load from the safepoint
1231 // polling page was emitted as relocInfo::poll_return_type here.
1232 __ relocate(relocInfo::poll_return_type);
1233 __ load_from_polling_page(Z_R1_scratch);
1234
1235 __ z_br(Z_R14); // Return to caller.
1236 }
1237
1238 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1239 const Register poll_addr = tmp->as_register_lo();
1240 __ z_lg(poll_addr, Address(Z_thread, JavaThread::polling_page_offset()));
1241 guarantee(info != nullptr, "Shouldn't be null");
1242 add_debug_info_for_branch(info);
1243 int offset = __ offset();
1244 __ relocate(relocInfo::poll_type);
1245 __ load_from_polling_page(poll_addr);
1246 return offset;
1247 }
1248
1249 void LIR_Assembler::emit_static_call_stub() {
1250
1251 // Stub is fixed up when the corresponding call is converted from calling
1252 // compiled code to calling interpreted code.
1253
1254 address call_pc = __ pc();
1255 address stub = __ start_a_stub(call_stub_size());
1256 if (stub == nullptr) {
1257 bailout("static call stub overflow");
1258 return;
1259 }
1260
1261 int start = __ offset();
1262
1263 __ relocate(static_stub_Relocation::spec(call_pc));
1264
1265 // See also Matcher::interpreter_method_reg().
1266 AddressLiteral meta = __ allocate_metadata_address(nullptr);
1267 bool success = __ load_const_from_toc(Z_method, meta);
1268
1269 __ set_inst_mark();
1270 AddressLiteral a((address)-1);
1271 success = success && __ load_const_from_toc(Z_R1, a);
1272 if (!success) {
1273 bailout("const section overflow");
1274 return;
1275 }
1276
1277 __ z_br(Z_R1);
1278 assert(__ offset() - start <= call_stub_size(), "stub too big");
1279 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1280 }
1281
1282 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1283 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1284 if (opr1->is_single_cpu()) {
1285 Register reg1 = opr1->as_register();
1286 if (opr2->is_single_cpu()) {
1287 // cpu register - cpu register
1288 if (is_reference_type(opr1->type())) {
1289 __ z_clgr(reg1, opr2->as_register());
1290 } else {
1291 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1292 if (unsigned_comp) {
1293 __ z_clr(reg1, opr2->as_register());
1294 } else {
1295 __ z_cr(reg1, opr2->as_register());
1296 }
1297 }
1298 } else if (opr2->is_stack()) {
1299 // cpu register - stack
1300 if (is_reference_type(opr1->type())) {
1301 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1302 } else {
1303 if (unsigned_comp) {
1304 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1305 } else {
1306 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1307 }
1308 }
1309 } else if (opr2->is_constant()) {
1310 // cpu register - constant
1311 LIR_Const* c = opr2->as_constant_ptr();
1312 if (c->type() == T_INT) {
1313 if (unsigned_comp) {
1314 __ z_clfi(reg1, c->as_jint());
1315 } else {
1316 __ z_cfi(reg1, c->as_jint());
1317 }
1318 } else if (c->type() == T_METADATA) {
1319 // We only need, for now, comparison with null for metadata.
1320 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1321 Metadata* m = c->as_metadata();
1322 if (m == nullptr) {
1323 __ z_cghi(reg1, 0);
1324 } else {
1325 ShouldNotReachHere();
1326 }
1327 } else if (is_reference_type(c->type())) {
1328 // In 64bit oops are single register.
1329 jobject o = c->as_jobject();
1330 if (o == nullptr) {
1331 __ z_ltgr(reg1, reg1);
1332 } else {
1333 jobject2reg(o, Z_R1_scratch);
1334 __ z_cgr(reg1, Z_R1_scratch);
1335 }
1336 } else {
1337 fatal("unexpected type: %s", basictype_to_str(c->type()));
1338 }
1339 // cpu register - address
1340 } else if (opr2->is_address()) {
1341 if (op->info() != nullptr) {
1342 add_debug_info_for_null_check_here(op->info());
1343 }
1344 if (unsigned_comp) {
1345 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1346 } else {
1347 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1348 }
1349 } else {
1350 ShouldNotReachHere();
1351 }
1352
1353 } else if (opr1->is_double_cpu()) {
1354 assert(!unsigned_comp, "unexpected");
1355 Register xlo = opr1->as_register_lo();
1356 Register xhi = opr1->as_register_hi();
1357 if (opr2->is_double_cpu()) {
1358 __ z_cgr(xlo, opr2->as_register_lo());
1359 } else if (opr2->is_constant()) {
1360 // cpu register - constant 0
1361 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1362 __ z_ltgr(xlo, xlo);
1363 } else {
1364 ShouldNotReachHere();
1365 }
1366
1367 } else if (opr1->is_single_fpu()) {
1368 if (opr2->is_single_fpu()) {
1369 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1370 } else {
1371 // stack slot
1372 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1373 if (Immediate::is_uimm12(addr.disp())) {
1374 __ z_ceb(opr1->as_float_reg(), addr);
1375 } else {
1376 __ z_ley(Z_fscratch_1, addr);
1377 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1378 }
1379 }
1380 } else if (opr1->is_double_fpu()) {
1381 if (opr2->is_double_fpu()) {
1382 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1383 } else {
1384 // stack slot
1385 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1386 if (Immediate::is_uimm12(addr.disp())) {
1387 __ z_cdb(opr1->as_double_reg(), addr);
1388 } else {
1389 __ z_ldy(Z_fscratch_1, addr);
1390 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1391 }
1392 }
1393 } else {
1394 ShouldNotReachHere();
1395 }
1396 }
1397
1398 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1399 Label done;
1400 Register dreg = dst->as_register();
1401
1402 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1403 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1404 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1405 bool is_single = left->is_single_fpu();
1406 bool is_unordered_less = (code == lir_ucmp_fd2i);
1407 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1408 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1409 if (is_single) {
1410 __ z_cebr(lreg, rreg);
1411 } else {
1412 __ z_cdbr(lreg, rreg);
1413 }
1414 if (VM_Version::has_LoadStoreConditional()) {
1415 Register one = Z_R0_scratch;
1416 Register minus_one = Z_R1_scratch;
1417 __ z_lghi(minus_one, -1);
1418 __ z_lghi(one, 1);
1419 __ z_lghi(dreg, 0);
1420 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1421 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1422 } else {
1423 __ clear_reg(dreg, true, false);
1424 __ z_bre(done); // if (left == right) dst = 0
1425
1426 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1427 __ z_lhi(dreg, 1);
1428 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1429
1430 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1431 __ z_lhi(dreg, -1);
1432 }
1433 } else {
1434 assert(code == lir_cmp_l2i, "check");
1435 if (VM_Version::has_LoadStoreConditional()) {
1436 Register one = Z_R0_scratch;
1437 Register minus_one = Z_R1_scratch;
1438 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1439 __ z_lghi(minus_one, -1);
1440 __ z_lghi(one, 1);
1441 __ z_lghi(dreg, 0);
1442 __ z_locgr(dreg, one, Assembler::bcondHigh);
1443 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1444 } else {
1445 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1446 __ z_lghi(dreg, 0); // eq value
1447 __ z_bre(done);
1448 __ z_lghi(dreg, 1); // gt value
1449 __ z_brh(done);
1450 __ z_lghi(dreg, -1); // lt value
1451 }
1452 }
1453 __ bind(done);
1454 }
1455
1456 // result = condition ? opr1 : opr2
1457 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1458 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1459 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390");
1460
1461 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1462 switch (condition) {
1463 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1464 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1465 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1466 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1467 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1468 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1469 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1470 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1471 default: ShouldNotReachHere();
1472 }
1473
1474 if (opr1->is_cpu_register()) {
1475 reg2reg(opr1, result);
1476 } else if (opr1->is_stack()) {
1477 stack2reg(opr1, result, result->type());
1478 } else if (opr1->is_constant()) {
1479 const2reg(opr1, result, lir_patch_none, nullptr);
1480 } else {
1481 ShouldNotReachHere();
1482 }
1483
1484 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1485 // Optimized version that does not require a branch.
1486 if (opr2->is_single_cpu()) {
1487 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1488 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1489 } else if (opr2->is_double_cpu()) {
1490 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1491 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1492 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1493 } else if (opr2->is_single_stack()) {
1494 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1495 } else if (opr2->is_double_stack()) {
1496 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1497 } else {
1498 ShouldNotReachHere();
1499 }
1500 } else {
1501 Label skip;
1502 __ z_brc(acond, skip);
1503 if (opr2->is_cpu_register()) {
1504 reg2reg(opr2, result);
1505 } else if (opr2->is_stack()) {
1506 stack2reg(opr2, result, result->type());
1507 } else if (opr2->is_constant()) {
1508 const2reg(opr2, result, lir_patch_none, nullptr);
1509 } else {
1510 ShouldNotReachHere();
1511 }
1512 __ bind(skip);
1513 }
1514 }
1515
1516 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1517 CodeEmitInfo* info) {
1518 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1519
1520 if (left->is_single_cpu()) {
1521 assert(left == dest, "left and dest must be equal");
1522 Register lreg = left->as_register();
1523
1524 if (right->is_single_cpu()) {
1525 // cpu register - cpu register
1526 Register rreg = right->as_register();
1527 switch (code) {
1528 case lir_add: __ z_ar (lreg, rreg); break;
1529 case lir_sub: __ z_sr (lreg, rreg); break;
1530 case lir_mul: __ z_msr(lreg, rreg); break;
1531 default: ShouldNotReachHere();
1532 }
1533
1534 } else if (right->is_stack()) {
1535 // cpu register - stack
1536 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1537 switch (code) {
1538 case lir_add: __ z_ay(lreg, raddr); break;
1539 case lir_sub: __ z_sy(lreg, raddr); break;
1540 default: ShouldNotReachHere();
1541 }
1542
1543 } else if (right->is_constant()) {
1544 // cpu register - constant
1545 jint c = right->as_constant_ptr()->as_jint();
1546 switch (code) {
1547 case lir_add:
1548 __ add2reg_32(lreg, c);
1549 break;
1550 case lir_sub:
1551 __ add2reg_32(lreg, java_negate(c));
1552 break;
1553 case lir_mul: __ z_msfi(lreg, c); break;
1554 default: ShouldNotReachHere();
1555 }
1556
1557 } else {
1558 ShouldNotReachHere();
1559 }
1560
1561 } else if (left->is_double_cpu()) {
1562 assert(left == dest, "left and dest must be equal");
1563 Register lreg_lo = left->as_register_lo();
1564 Register lreg_hi = left->as_register_hi();
1565
1566 if (right->is_double_cpu()) {
1567 // cpu register - cpu register
1568 Register rreg_lo = right->as_register_lo();
1569 Register rreg_hi = right->as_register_hi();
1570 assert_different_registers(lreg_lo, rreg_lo);
1571 switch (code) {
1572 case lir_add:
1573 __ z_agr(lreg_lo, rreg_lo);
1574 break;
1575 case lir_sub:
1576 __ z_sgr(lreg_lo, rreg_lo);
1577 break;
1578 case lir_mul:
1579 __ z_msgr(lreg_lo, rreg_lo);
1580 break;
1581 default:
1582 ShouldNotReachHere();
1583 }
1584
1585 } else if (right->is_constant()) {
1586 // cpu register - constant
1587 jlong c = right->as_constant_ptr()->as_jlong_bits();
1588 switch (code) {
1589 case lir_add: __ z_agfi(lreg_lo, c); break;
1590 case lir_sub:
1591 if (c != min_jint) {
1592 __ z_agfi(lreg_lo, -c);
1593 } else {
1594 // -min_jint cannot be represented as simm32 in z_agfi
1595 // min_jint sign extended: 0xffffffff80000000
1596 // -min_jint as 64 bit integer: 0x0000000080000000
1597 // 0x80000000 can be represented as uimm32 in z_algfi
1598 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1599 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1600 }
1601 break;
1602 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1603 default:
1604 ShouldNotReachHere();
1605 }
1606
1607 } else {
1608 ShouldNotReachHere();
1609 }
1610
1611 } else if (left->is_single_fpu()) {
1612 assert(left == dest, "left and dest must be equal");
1613 FloatRegister lreg = left->as_float_reg();
1614 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1615 Address raddr;
1616
1617 if (rreg == fnoreg) {
1618 assert(right->is_single_stack(), "constants should be loaded into register");
1619 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1620 if (!Immediate::is_uimm12(raddr.disp())) {
1621 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1622 }
1623 }
1624
1625 if (rreg != fnoreg) {
1626 switch (code) {
1627 case lir_add: __ z_aebr(lreg, rreg); break;
1628 case lir_sub: __ z_sebr(lreg, rreg); break;
1629 case lir_mul: __ z_meebr(lreg, rreg); break;
1630 case lir_div: __ z_debr(lreg, rreg); break;
1631 default: ShouldNotReachHere();
1632 }
1633 } else {
1634 switch (code) {
1635 case lir_add: __ z_aeb(lreg, raddr); break;
1636 case lir_sub: __ z_seb(lreg, raddr); break;
1637 case lir_mul: __ z_meeb(lreg, raddr); break;
1638 case lir_div: __ z_deb(lreg, raddr); break;
1639 default: ShouldNotReachHere();
1640 }
1641 }
1642 } else if (left->is_double_fpu()) {
1643 assert(left == dest, "left and dest must be equal");
1644 FloatRegister lreg = left->as_double_reg();
1645 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1646 Address raddr;
1647
1648 if (rreg == fnoreg) {
1649 assert(right->is_double_stack(), "constants should be loaded into register");
1650 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1651 if (!Immediate::is_uimm12(raddr.disp())) {
1652 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1653 }
1654 }
1655
1656 if (rreg != fnoreg) {
1657 switch (code) {
1658 case lir_add: __ z_adbr(lreg, rreg); break;
1659 case lir_sub: __ z_sdbr(lreg, rreg); break;
1660 case lir_mul: __ z_mdbr(lreg, rreg); break;
1661 case lir_div: __ z_ddbr(lreg, rreg); break;
1662 default: ShouldNotReachHere();
1663 }
1664 } else {
1665 switch (code) {
1666 case lir_add: __ z_adb(lreg, raddr); break;
1667 case lir_sub: __ z_sdb(lreg, raddr); break;
1668 case lir_mul: __ z_mdb(lreg, raddr); break;
1669 case lir_div: __ z_ddb(lreg, raddr); break;
1670 default: ShouldNotReachHere();
1671 }
1672 }
1673 } else if (left->is_address()) {
1674 assert(left == dest, "left and dest must be equal");
1675 assert(code == lir_add, "unsupported operation");
1676 assert(right->is_constant(), "unsupported operand");
1677 jint c = right->as_constant_ptr()->as_jint();
1678 LIR_Address* lir_addr = left->as_address_ptr();
1679 Address addr = as_Address(lir_addr);
1680 switch (lir_addr->type()) {
1681 case T_INT:
1682 __ add2mem_32(addr, c, Z_R1_scratch);
1683 break;
1684 case T_LONG:
1685 __ add2mem_64(addr, c, Z_R1_scratch);
1686 break;
1687 default:
1688 ShouldNotReachHere();
1689 }
1690 } else {
1691 ShouldNotReachHere();
1692 }
1693 }
1694
1695 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1696 switch (code) {
1697 case lir_sqrt: {
1698 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1699 FloatRegister src_reg = value->as_double_reg();
1700 FloatRegister dst_reg = dest->as_double_reg();
1701 __ z_sqdbr(dst_reg, src_reg);
1702 break;
1703 }
1704 case lir_abs: {
1705 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1706 FloatRegister src_reg = value->as_double_reg();
1707 FloatRegister dst_reg = dest->as_double_reg();
1708 __ z_lpdbr(dst_reg, src_reg);
1709 break;
1710 }
1711 default: {
1712 ShouldNotReachHere();
1713 break;
1714 }
1715 }
1716 }
1717
1718 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1719 if (left->is_single_cpu()) {
1720 Register reg = left->as_register();
1721 if (right->is_constant()) {
1722 int val = right->as_constant_ptr()->as_jint();
1723 switch (code) {
1724 case lir_logic_and: __ z_nilf(reg, val); break;
1725 case lir_logic_or: __ z_oilf(reg, val); break;
1726 case lir_logic_xor: __ z_xilf(reg, val); break;
1727 default: ShouldNotReachHere();
1728 }
1729 } else if (right->is_stack()) {
1730 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1731 switch (code) {
1732 case lir_logic_and: __ z_ny(reg, raddr); break;
1733 case lir_logic_or: __ z_oy(reg, raddr); break;
1734 case lir_logic_xor: __ z_xy(reg, raddr); break;
1735 default: ShouldNotReachHere();
1736 }
1737 } else {
1738 Register rright = right->as_register();
1739 switch (code) {
1740 case lir_logic_and: __ z_nr(reg, rright); break;
1741 case lir_logic_or : __ z_or(reg, rright); break;
1742 case lir_logic_xor: __ z_xr(reg, rright); break;
1743 default: ShouldNotReachHere();
1744 }
1745 }
1746 move_regs(reg, dst->as_register());
1747 } else {
1748 Register l_lo = left->as_register_lo();
1749 if (right->is_constant()) {
1750 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1751 switch (code) {
1752 case lir_logic_and:
1753 __ z_ngr(l_lo, Z_R1_scratch);
1754 break;
1755 case lir_logic_or:
1756 __ z_ogr(l_lo, Z_R1_scratch);
1757 break;
1758 case lir_logic_xor:
1759 __ z_xgr(l_lo, Z_R1_scratch);
1760 break;
1761 default: ShouldNotReachHere();
1762 }
1763 } else {
1764 Register r_lo;
1765 if (is_reference_type(right->type())) {
1766 r_lo = right->as_register();
1767 } else {
1768 r_lo = right->as_register_lo();
1769 }
1770 switch (code) {
1771 case lir_logic_and:
1772 __ z_ngr(l_lo, r_lo);
1773 break;
1774 case lir_logic_or:
1775 __ z_ogr(l_lo, r_lo);
1776 break;
1777 case lir_logic_xor:
1778 __ z_xgr(l_lo, r_lo);
1779 break;
1780 default: ShouldNotReachHere();
1781 }
1782 }
1783
1784 Register dst_lo = dst->as_register_lo();
1785
1786 move_regs(l_lo, dst_lo);
1787 }
1788 }
1789
1790 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1791 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1792 if (left->is_double_cpu()) {
1793 // 64 bit integer case
1794 assert(left->is_double_cpu(), "left must be register");
1795 assert(right->is_double_cpu() || is_power_of_2(right->as_jlong()),
1796 "right must be register or power of 2 constant");
1797 assert(result->is_double_cpu(), "result must be register");
1798
1799 Register lreg = left->as_register_lo();
1800 Register dreg = result->as_register_lo();
1801
1802 if (right->is_constant()) {
1803 // Convert division by a power of two into some shifts and logical operations.
1804 Register treg1 = Z_R0_scratch;
1805 Register treg2 = Z_R1_scratch;
1806 jlong divisor = right->as_jlong();
1807 jlong log_divisor = log2i_exact(right->as_jlong());
1808
1809 if (divisor == min_jlong) {
1810 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1811 if (dreg == lreg) {
1812 NearLabel done;
1813 __ load_const_optimized(treg2, min_jlong);
1814 __ z_cgr(lreg, treg2);
1815 __ z_lghi(dreg, 0); // Preserves condition code.
1816 __ z_brne(done);
1817 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1818 __ bind(done);
1819 } else {
1820 assert_different_registers(dreg, lreg);
1821 NearLabel done;
1822 __ z_lghi(dreg, 0);
1823 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1824 __ z_lghi(dreg, 1);
1825 __ bind(done);
1826 }
1827 return;
1828 }
1829 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1830 if (divisor == 2) {
1831 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1832 } else {
1833 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1834 __ and_imm(treg2, divisor - 1, treg1, true);
1835 }
1836 if (code == lir_idiv) {
1837 __ z_agr(dreg, treg2);
1838 __ z_srag(dreg, dreg, log_divisor);
1839 } else {
1840 assert(code == lir_irem, "check");
1841 __ z_agr(treg2, dreg);
1842 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1843 __ z_sgr(dreg, treg2);
1844 }
1845 return;
1846 }
1847
1848 // Divisor is not a power of 2 constant.
1849 Register rreg = right->as_register_lo();
1850 Register treg = temp->as_register_lo();
1851 assert(right->is_double_cpu(), "right must be register");
1852 assert(lreg == Z_R11, "see ldivInOpr()");
1853 assert(rreg != lreg, "right register must not be same as left register");
1854 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1855 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1856
1857 Register R1 = lreg->predecessor();
1858 Register R2 = rreg;
1859 assert(code != lir_idiv || lreg==dreg, "see code below");
1860 if (code == lir_idiv) {
1861 __ z_lcgr(lreg, lreg);
1862 } else {
1863 __ clear_reg(dreg, true, false);
1864 }
1865 NearLabel done;
1866 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1867 if (code == lir_idiv) {
1868 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1869 }
1870 if (ImplicitDiv0Checks) {
1871 // No debug info because the idiv won't trap.
1872 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1873 // which is unnecessary, too.
1874 add_debug_info_for_div0(__ offset(), info);
1875 }
1876 __ z_dsgr(R1, R2);
1877 __ bind(done);
1878 return;
1879 }
1880
1881 // 32 bit integer case
1882
1883 assert(left->is_single_cpu(), "left must be register");
1884 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1885 assert(result->is_single_cpu(), "result must be register");
1886
1887 Register lreg = left->as_register();
1888 Register dreg = result->as_register();
1889
1890 if (right->is_constant()) {
1891 // Convert division by a power of two into some shifts and logical operations.
1892 Register treg1 = Z_R0_scratch;
1893 Register treg2 = Z_R1_scratch;
1894 jlong divisor = right->as_jint();
1895 jlong log_divisor = log2i_exact(right->as_jint());
1896 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1897 if (divisor == 2) {
1898 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1899 } else {
1900 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1901 __ and_imm(treg2, divisor - 1, treg1, true);
1902 }
1903 if (code == lir_idiv) {
1904 __ z_agr(dreg, treg2);
1905 __ z_srag(dreg, dreg, log_divisor);
1906 } else {
1907 assert(code == lir_irem, "check");
1908 __ z_agr(treg2, dreg);
1909 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1910 __ z_sgr(dreg, treg2);
1911 }
1912 return;
1913 }
1914
1915 // Divisor is not a power of 2 constant.
1916 Register rreg = right->as_register();
1917 Register treg = temp->as_register();
1918 assert(right->is_single_cpu(), "right must be register");
1919 assert(lreg == Z_R11, "left register must be rax,");
1920 assert(rreg != lreg, "right register must not be same as left register");
1921 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1922 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1923
1924 Register R1 = lreg->predecessor();
1925 Register R2 = rreg;
1926 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1927 if (ImplicitDiv0Checks) {
1928 // No debug info because the idiv won't trap.
1929 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1930 // which is unnecessary, too.
1931 add_debug_info_for_div0(__ offset(), info);
1932 }
1933 __ z_dsgfr(R1, R2);
1934 }
1935
1936 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1937 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1938 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1939
1940 // Exception object is not added to oop map by LinearScan
1941 // (LinearScan assumes that no oops are in fixed registers).
1942 info->add_register_oop(exceptionOop);
1943
1944 // Reuse the debug info from the safepoint poll for the throw op itself.
1945 __ get_PC(Z_EXC_PC);
1946 add_call_info(__ offset(), info); // for exception handler
1947 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1948 : StubId::c1_handle_exception_nofpu_id);
1949 emit_call_c(stub);
1950 }
1951
1952 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1953 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1954
1955 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1956 }
1957
1958 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1959 ciArrayKlass* default_type = op->expected_type();
1960 Register src = op->src()->as_register();
1961 Register dst = op->dst()->as_register();
1962 Register src_pos = op->src_pos()->as_register();
1963 Register dst_pos = op->dst_pos()->as_register();
1964 Register length = op->length()->as_register();
1965 Register tmp = op->tmp()->as_register();
1966
1967 CodeStub* stub = op->stub();
1968 int flags = op->flags();
1969 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
1970 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1971
1972 // If we don't know anything, just go through the generic arraycopy.
1973 if (default_type == nullptr) {
1974 address copyfunc_addr = StubRoutines::generic_arraycopy();
1975
1976 if (copyfunc_addr == nullptr) {
1977 // Take a slow path for generic arraycopy.
1978 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1979 __ bind(*stub->continuation());
1980 return;
1981 }
1982
1983 // Save outgoing arguments in callee saved registers (C convention) in case
1984 // a call to System.arraycopy is needed.
1985 Register callee_saved_src = Z_R10;
1986 Register callee_saved_src_pos = Z_R11;
1987 Register callee_saved_dst = Z_R12;
1988 Register callee_saved_dst_pos = Z_R13;
1989 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1990
1991 __ lgr_if_needed(callee_saved_src, src);
1992 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1993 __ lgr_if_needed(callee_saved_dst, dst);
1994 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1995 __ lgr_if_needed(callee_saved_length, length);
1996
1997 // C function requires 64 bit values.
1998 __ z_lgfr(src_pos, src_pos);
1999 __ z_lgfr(dst_pos, dst_pos);
2000 __ z_lgfr(length, length);
2001
2002 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
2003
2004 // The arguments are in the corresponding registers.
2005 assert(Z_ARG1 == src, "assumption");
2006 assert(Z_ARG2 == src_pos, "assumption");
2007 assert(Z_ARG3 == dst, "assumption");
2008 assert(Z_ARG4 == dst_pos, "assumption");
2009 assert(Z_ARG5 == length, "assumption");
2010 #ifndef PRODUCT
2011 if (PrintC1Statistics) {
2012 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
2013 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2014 }
2015 #endif
2016 emit_call_c(copyfunc_addr);
2017 CHECK_BAILOUT();
2018
2019 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2020
2021 __ z_lgr(tmp, Z_RET);
2022 __ z_xilf(tmp, -1);
2023
2024 // Restore values from callee saved registers so they are where the stub
2025 // expects them.
2026 __ lgr_if_needed(src, callee_saved_src);
2027 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2028 __ lgr_if_needed(dst, callee_saved_dst);
2029 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2030 __ lgr_if_needed(length, callee_saved_length);
2031
2032 __ z_sr(length, tmp);
2033 __ z_ar(src_pos, tmp);
2034 __ z_ar(dst_pos, tmp);
2035 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2036
2037 __ bind(*stub->continuation());
2038 return;
2039 }
2040
2041 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2042
2043 int elem_size = type2aelembytes(basic_type);
2044 int shift_amount;
2045
2046 switch (elem_size) {
2047 case 1 :
2048 shift_amount = 0;
2049 break;
2050 case 2 :
2051 shift_amount = 1;
2052 break;
2053 case 4 :
2054 shift_amount = 2;
2055 break;
2056 case 8 :
2057 shift_amount = 3;
2058 break;
2059 default:
2060 shift_amount = -1;
2061 ShouldNotReachHere();
2062 }
2063
2064 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2065 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2066
2067 // Length and pos's are all sign extended at this point on 64bit.
2068
2069 // test for null
2070 if (flags & LIR_OpArrayCopy::src_null_check) {
2071 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2072 }
2073 if (flags & LIR_OpArrayCopy::dst_null_check) {
2074 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2075 }
2076
2077 // Check if negative.
2078 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2079 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2080 }
2081 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2082 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2083 }
2084
2085 // If the compiler was not able to prove that exact type of the source or the destination
2086 // of the arraycopy is an array type, check at runtime if the source or the destination is
2087 // an instance type.
2088 if (flags & LIR_OpArrayCopy::type_check) {
2089 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2090
2091 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2092 __ load_klass(tmp, dst);
2093 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2094 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2095 }
2096
2097 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2098 __ load_klass(tmp, src);
2099 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2100 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2101 }
2102 }
2103
2104 if (flags & LIR_OpArrayCopy::src_range_check) {
2105 __ z_la(tmp, Address(src_pos, length));
2106 __ z_cl(tmp, src_length_addr);
2107 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2108 }
2109 if (flags & LIR_OpArrayCopy::dst_range_check) {
2110 __ z_la(tmp, Address(dst_pos, length));
2111 __ z_cl(tmp, dst_length_addr);
2112 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2113 }
2114
2115 if (flags & LIR_OpArrayCopy::length_positive_check) {
2116 __ z_ltr(length, length);
2117 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2118 }
2119
2120 // Stubs require 64 bit values.
2121 __ z_lgfr(src_pos, src_pos); // int -> long
2122 __ z_lgfr(dst_pos, dst_pos); // int -> long
2123 __ z_lgfr(length, length); // int -> long
2124
2125 if (flags & LIR_OpArrayCopy::type_check) {
2126 // We don't know the array types are compatible.
2127 if (basic_type != T_OBJECT) {
2128 // Simple test for basic type arrays.
2129 __ cmp_klasses_from_objects(src, dst, tmp, Z_R1_scratch);
2130 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2131 } else {
2132 // For object arrays, if src is a sub class of dst then we can
2133 // safely do the copy.
2134 NearLabel cont, slow;
2135 Register src_klass = Z_R1_scratch;
2136 Register dst_klass = Z_R10;
2137
2138 __ load_klass(src_klass, src);
2139 __ load_klass(dst_klass, dst);
2140
2141 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, nullptr);
2142
2143 store_parameter(src_klass, 0); // sub
2144 store_parameter(dst_klass, 1); // super
2145 emit_call_c(Runtime1::entry_for (StubId::c1_slow_subtype_check_id));
2146 CHECK_BAILOUT2(cont, slow);
2147 // Sets condition code 0 for match (2 otherwise).
2148 __ branch_optimized(Assembler::bcondEqual, cont);
2149
2150 __ bind(slow);
2151
2152 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2153 if (copyfunc_addr != nullptr) { // use stub if available
2154 // Src is not a sub class of dst so we have to do a
2155 // per-element check.
2156
2157 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2158 if ((flags & mask) != mask) {
2159 // Check that at least both of them object arrays.
2160 assert(flags & mask, "one of the two should be known to be an object array");
2161
2162 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2163 __ load_klass(tmp, src);
2164 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2165 __ load_klass(tmp, dst);
2166 }
2167 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2168 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2169 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2170 __ z_c(Z_R1_scratch, klass_lh_addr);
2171 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2172 }
2173
2174 // Save outgoing arguments in callee saved registers (C convention) in case
2175 // a call to System.arraycopy is needed.
2176 Register callee_saved_src = Z_R10;
2177 Register callee_saved_src_pos = Z_R11;
2178 Register callee_saved_dst = Z_R12;
2179 Register callee_saved_dst_pos = Z_R13;
2180 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2181
2182 __ lgr_if_needed(callee_saved_src, src);
2183 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2184 __ lgr_if_needed(callee_saved_dst, dst);
2185 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2186 __ lgr_if_needed(callee_saved_length, length);
2187
2188 __ z_llgfr(length, length); // Higher 32bits must be null.
2189
2190 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2191 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2192
2193 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2194 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2195 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2196 assert_different_registers(Z_ARG2, dst, length);
2197
2198 __ z_lgr(Z_ARG3, length);
2199 assert_different_registers(Z_ARG3, dst);
2200
2201 __ load_klass(Z_ARG5, dst);
2202 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2203 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2204 emit_call_c(copyfunc_addr);
2205 CHECK_BAILOUT2(cont, slow);
2206
2207 #ifndef PRODUCT
2208 if (PrintC1Statistics) {
2209 NearLabel failed;
2210 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2211 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2212 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2213 __ bind(failed);
2214 }
2215 #endif
2216
2217 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2218
2219 #ifndef PRODUCT
2220 if (PrintC1Statistics) {
2221 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2222 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2223 }
2224 #endif
2225
2226 __ z_lgr(tmp, Z_RET);
2227 __ z_xilf(tmp, -1);
2228
2229 // Restore previously spilled arguments
2230 __ lgr_if_needed(src, callee_saved_src);
2231 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2232 __ lgr_if_needed(dst, callee_saved_dst);
2233 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2234 __ lgr_if_needed(length, callee_saved_length);
2235
2236 __ z_sr(length, tmp);
2237 __ z_ar(src_pos, tmp);
2238 __ z_ar(dst_pos, tmp);
2239 }
2240
2241 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2242
2243 __ bind(cont);
2244 }
2245 }
2246
2247 #ifdef ASSERT
2248 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2249 // Sanity check the known type with the incoming class. For the
2250 // primitive case the types must match exactly with src.klass and
2251 // dst.klass each exactly matching the default type. For the
2252 // object array case, if no type check is needed then either the
2253 // dst type is exactly the expected type and the src type is a
2254 // subtype which we can't check or src is the same array as dst
2255 // but not necessarily exactly of type default_type.
2256 NearLabel known_ok, halt;
2257 metadata2reg(default_type->constant_encoding(), tmp);
2258 __ encode_klass_not_null(tmp);
2259
2260 if (basic_type != T_OBJECT) {
2261 __ cmp_klass(tmp, dst, Z_R1_scratch);
2262 __ branch_optimized(Assembler::bcondNotEqual, halt);
2263
2264 __ cmp_klass(tmp, src, Z_R1_scratch);
2265 __ branch_optimized(Assembler::bcondEqual, known_ok);
2266 } else {
2267 __ cmp_klass(tmp, dst, Z_R1_scratch);
2268 __ branch_optimized(Assembler::bcondEqual, known_ok);
2269 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2270 }
2271 __ bind(halt);
2272 __ stop("incorrect type information in arraycopy");
2273 __ bind(known_ok);
2274 }
2275 #endif
2276
2277 #ifndef PRODUCT
2278 if (PrintC1Statistics) {
2279 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2280 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2281 }
2282 #endif
2283
2284 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2285 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2286
2287 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2288 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2289 assert_different_registers(Z_ARG2, length);
2290 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2291 __ lgr_if_needed(Z_ARG3, length);
2292
2293 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2294 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2295 const char *name;
2296 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2297 __ call_VM_leaf(entry);
2298
2299 if (stub != nullptr) {
2300 __ bind(*stub->continuation());
2301 }
2302 }
2303
2304 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2305 if (dest->is_single_cpu()) {
2306 if (left->type() == T_OBJECT) {
2307 switch (code) {
2308 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2309 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2310 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2311 default: ShouldNotReachHere();
2312 }
2313 } else {
2314 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2315 Register masked_count = Z_R1_scratch;
2316 __ z_lr(masked_count, count->as_register());
2317 __ z_nill(masked_count, 31);
2318 switch (code) {
2319 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2320 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2321 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2322 default: ShouldNotReachHere();
2323 }
2324 }
2325 } else {
2326 switch (code) {
2327 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2328 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2329 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2330 default: ShouldNotReachHere();
2331 }
2332 }
2333 }
2334
2335 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2336 if (left->type() == T_OBJECT) {
2337 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2338 Register l = left->as_register();
2339 Register d = dest->as_register_lo();
2340 switch (code) {
2341 case lir_shl: __ z_sllg (d, l, count); break;
2342 case lir_shr: __ z_srag (d, l, count); break;
2343 case lir_ushr: __ z_srlg (d, l, count); break;
2344 default: ShouldNotReachHere();
2345 }
2346 return;
2347 }
2348 if (dest->is_single_cpu()) {
2349 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2350 count = count & 0x1F; // Java spec
2351 switch (code) {
2352 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2353 case lir_shr: __ z_sra (dest->as_register(), count); break;
2354 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2355 default: ShouldNotReachHere();
2356 }
2357 } else if (dest->is_double_cpu()) {
2358 count = count & 63; // Java spec
2359 Register l = left->as_pointer_register();
2360 Register d = dest->as_pointer_register();
2361 switch (code) {
2362 case lir_shl: __ z_sllg (d, l, count); break;
2363 case lir_shr: __ z_srag (d, l, count); break;
2364 case lir_ushr: __ z_srlg (d, l, count); break;
2365 default: ShouldNotReachHere();
2366 }
2367 } else {
2368 ShouldNotReachHere();
2369 }
2370 }
2371
2372 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2373 if (op->init_check()) {
2374 // Make sure klass is initialized & doesn't have finalizer.
2375 // init_state needs acquire, but S390 is TSO, and so we are already good.
2376 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2377 Register iklass = op->klass()->as_register();
2378 add_debug_info_for_null_check_here(op->stub()->info());
2379 if (Immediate::is_uimm12(state_offset)) {
2380 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2381 } else {
2382 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2383 }
2384 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2385 }
2386 __ allocate_object(op->obj()->as_register(),
2387 op->tmp1()->as_register(),
2388 op->tmp2()->as_register(),
2389 op->header_size(),
2390 op->object_size(),
2391 op->klass()->as_register(),
2392 *op->stub()->entry());
2393 __ bind(*op->stub()->continuation());
2394 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2395 }
2396
2397 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2398 Register len = op->len()->as_register();
2399 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2400
2401 if (UseSlowPath ||
2402 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2403 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2404 __ z_brul(*op->stub()->entry());
2405 } else {
2406 __ allocate_array(op->obj()->as_register(),
2407 op->len()->as_register(),
2408 op->tmp1()->as_register(),
2409 op->tmp2()->as_register(),
2410 arrayOopDesc::base_offset_in_bytes(op->type()),
2411 type2aelembytes(op->type()),
2412 op->klass()->as_register(),
2413 *op->stub()->entry(),
2414 op->zero_array());
2415 }
2416 __ bind(*op->stub()->continuation());
2417 }
2418
2419 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2420 Register recv, Register tmp1) {
2421 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
2422 __ profile_receiver_type(recv, mdo, mdp_offset, tmp1);
2423 }
2424
2425 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2426 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2427 Unimplemented();
2428 }
2429
2430 void LIR_Assembler::store_parameter(Register r, int param_num) {
2431 assert(param_num >= 0, "invalid num");
2432 int offset_in_bytes = param_num * BytesPerWord;
2433 check_reserved_argument_area(offset_in_bytes);
2434 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2435 __ z_stg(r, offset_in_bytes, Z_SP);
2436 }
2437
2438 void LIR_Assembler::store_parameter(jint c, int param_num) {
2439 assert(param_num >= 0, "invalid num");
2440 int offset_in_bytes = param_num * BytesPerWord;
2441 check_reserved_argument_area(offset_in_bytes);
2442 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2443 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2444 }
2445
2446 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2447 // We always need a stub for the failure case.
2448 CodeStub* stub = op->stub();
2449 Register obj = op->object()->as_register();
2450 Register k_RInfo = op->tmp1()->as_register();
2451 Register klass_RInfo = op->tmp2()->as_register();
2452 Register dst = op->result_opr()->as_register();
2453 Register Rtmp1 = Z_R1_scratch;
2454 ciKlass* k = op->klass();
2455
2456 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2457
2458 // Check if it needs to be profiled.
2459 ciMethodData* md = nullptr;
2460 ciProfileData* data = nullptr;
2461
2462 if (op->should_profile()) {
2463 ciMethod* method = op->profiled_method();
2464 assert(method != nullptr, "Should have method");
2465 int bci = op->profiled_bci();
2466 md = method->method_data_or_null();
2467 assert(md != nullptr, "Sanity");
2468 data = md->bci_to_data(bci);
2469 assert(data != nullptr, "need data for type check");
2470 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2471 }
2472
2473 // Temp operands do not overlap with inputs, if this is their last
2474 // use (end of range is exclusive), so a register conflict is possible.
2475 if (obj == k_RInfo) {
2476 k_RInfo = dst;
2477 } else if (obj == klass_RInfo) {
2478 klass_RInfo = dst;
2479 }
2480 assert_different_registers(obj, k_RInfo, klass_RInfo);
2481
2482 if (op->should_profile()) {
2483 Register mdo = klass_RInfo;
2484 metadata2reg(md->constant_encoding(), mdo);
2485 NearLabel not_null;
2486 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2487 // Object is null; update MDO and exit.
2488 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2489 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2490 __ or2mem_8(data_addr, header_bits);
2491 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2492 __ bind(not_null);
2493
2494 Register recv = k_RInfo;
2495 __ load_klass(recv, obj);
2496 type_profile_helper(mdo, md, data, recv, Rtmp1);
2497 } else {
2498 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2499 }
2500
2501 Label *failure_target = failure;
2502 Label *success_target = success;
2503
2504 // Patching may screw with our temporaries,
2505 // so let's do it before loading the class.
2506 if (k->is_loaded()) {
2507 metadata2reg(k->constant_encoding(), k_RInfo);
2508 } else {
2509 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2510 }
2511 assert(obj != k_RInfo, "must be different");
2512
2513 __ verify_oop(obj, FILE_AND_LINE);
2514
2515 // Get object class.
2516 // Not a safepoint as obj null check happens earlier.
2517 if (op->fast_check()) {
2518 __ load_klass(klass_RInfo, obj);
2519 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2520 // Successful cast, fall through to profile or jump.
2521 } else {
2522 bool need_slow_path = !k->is_loaded() ||
2523 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2524 __ load_klass(klass_RInfo, obj);
2525 // Perform the fast part of the checking logic.
2526 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2527 (need_slow_path ? success_target : nullptr),
2528 failure_target, nullptr);
2529 if (need_slow_path) {
2530 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2531 address a = Runtime1::entry_for (StubId::c1_slow_subtype_check_id);
2532 store_parameter(klass_RInfo, 0); // sub
2533 store_parameter(k_RInfo, 1); // super
2534 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2535 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2536 // Fall through to success case.
2537 }
2538 }
2539
2540 __ branch_optimized(Assembler::bcondAlways, *success);
2541 }
2542
2543 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2544 LIR_Code code = op->code();
2545 if (code == lir_store_check) {
2546 Register value = op->object()->as_register();
2547 Register array = op->array()->as_register();
2548 Register k_RInfo = op->tmp1()->as_register();
2549 Register klass_RInfo = op->tmp2()->as_register();
2550 Register Rtmp1 = Z_R1_scratch;
2551
2552 CodeStub* stub = op->stub();
2553
2554 // Check if it needs to be profiled.
2555 ciMethodData* md = nullptr;
2556 ciProfileData* data = nullptr;
2557
2558 assert_different_registers(value, k_RInfo, klass_RInfo);
2559
2560 if (op->should_profile()) {
2561 ciMethod* method = op->profiled_method();
2562 assert(method != nullptr, "Should have method");
2563 int bci = op->profiled_bci();
2564 md = method->method_data_or_null();
2565 assert(md != nullptr, "Sanity");
2566 data = md->bci_to_data(bci);
2567 assert(data != nullptr, "need data for type check");
2568 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2569 }
2570 NearLabel done;
2571 Label *success_target = &done;
2572 Label *failure_target = stub->entry();
2573
2574 if (op->should_profile()) {
2575 Register mdo = klass_RInfo;
2576 metadata2reg(md->constant_encoding(), mdo);
2577 NearLabel not_null;
2578 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2579 // Object is null; update MDO and exit.
2580 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2581 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2582 __ or2mem_8(data_addr, header_bits);
2583 __ branch_optimized(Assembler::bcondAlways, done);
2584 __ bind(not_null);
2585
2586 Register recv = k_RInfo;
2587 __ load_klass(recv, value);
2588 type_profile_helper(mdo, md, data, recv, Rtmp1);
2589 } else {
2590 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2591 }
2592
2593 add_debug_info_for_null_check_here(op->info_for_exception());
2594 __ load_klass(k_RInfo, array);
2595 __ load_klass(klass_RInfo, value);
2596
2597 // Get instance klass (it's already uncompressed).
2598 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2599 // Perform the fast part of the checking logic.
2600 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
2601 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2602 address a = Runtime1::entry_for (StubId::c1_slow_subtype_check_id);
2603 store_parameter(klass_RInfo, 0); // sub
2604 store_parameter(k_RInfo, 1); // super
2605 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2606 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2607 // Fall through to success case.
2608
2609 __ bind(done);
2610 } else {
2611 if (code == lir_checkcast) {
2612 Register obj = op->object()->as_register();
2613 Register dst = op->result_opr()->as_register();
2614 NearLabel success;
2615 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2616 __ bind(success);
2617 __ lgr_if_needed(dst, obj);
2618 } else {
2619 if (code == lir_instanceof) {
2620 Register obj = op->object()->as_register();
2621 Register dst = op->result_opr()->as_register();
2622 NearLabel success, failure, done;
2623 emit_typecheck_helper(op, &success, &failure, &failure);
2624 __ bind(failure);
2625 __ clear_reg(dst);
2626 __ branch_optimized(Assembler::bcondAlways, done);
2627 __ bind(success);
2628 __ load_const_optimized(dst, 1);
2629 __ bind(done);
2630 } else {
2631 ShouldNotReachHere();
2632 }
2633 }
2634 }
2635 }
2636
2637 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2638 Register addr = op->addr()->as_pointer_register();
2639 Register t1_cmp = Z_R1_scratch;
2640 if (op->code() == lir_cas_long) {
2641 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2642 Register new_value_lo = op->new_value()->as_register_lo();
2643 __ z_lgr(t1_cmp, cmp_value_lo);
2644 // Perform the compare and swap operation.
2645 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2646 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2647 Register cmp_value = op->cmp_value()->as_register();
2648 Register new_value = op->new_value()->as_register();
2649 if (op->code() == lir_cas_obj) {
2650 if (UseCompressedOops) {
2651 t1_cmp = op->tmp1()->as_register();
2652 Register t2_new = op->tmp2()->as_register();
2653 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2654 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2655 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2656 __ z_cs(t1_cmp, t2_new, 0, addr);
2657 } else {
2658 __ z_lgr(t1_cmp, cmp_value);
2659 __ z_csg(t1_cmp, new_value, 0, addr);
2660 }
2661 } else {
2662 __ z_lr(t1_cmp, cmp_value);
2663 __ z_cs(t1_cmp, new_value, 0, addr);
2664 }
2665 } else {
2666 ShouldNotReachHere(); // new lir_cas_??
2667 }
2668 }
2669
2670 void LIR_Assembler::breakpoint() {
2671 Unimplemented();
2672 // __ breakpoint_trap();
2673 }
2674
2675 void LIR_Assembler::push(LIR_Opr opr) {
2676 ShouldNotCallThis(); // unused
2677 }
2678
2679 void LIR_Assembler::pop(LIR_Opr opr) {
2680 ShouldNotCallThis(); // unused
2681 }
2682
2683 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2684 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2685 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2686 }
2687
2688 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2689 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2690 Register hdr = op->hdr_opr()->as_register();
2691 Register lock = op->lock_opr()->as_register();
2692 if (op->code() == lir_lock) {
2693 // Add debug info for NullPointerException only if one is possible.
2694 if (op->info() != nullptr) {
2695 add_debug_info_for_null_check_here(op->info());
2696 }
2697 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2698 // done
2699 } else if (op->code() == lir_unlock) {
2700 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2701 } else {
2702 ShouldNotReachHere();
2703 }
2704 __ bind(*op->stub()->continuation());
2705 }
2706
2707 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2708 Register obj = op->obj()->as_pointer_register();
2709 Register result = op->result_opr()->as_pointer_register();
2710
2711 CodeEmitInfo* info = op->info();
2712 if (info != nullptr) {
2713 add_debug_info_for_null_check_here(info);
2714 }
2715
2716 __ load_klass(result, obj);
2717 }
2718 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2719 ciMethod* method = op->profiled_method();
2720 int bci = op->profiled_bci();
2721 ciMethod* callee = op->profiled_callee();
2722
2723 // Update counter for all call types.
2724 ciMethodData* md = method->method_data_or_null();
2725 assert(md != nullptr, "Sanity");
2726 ciProfileData* data = md->bci_to_data(bci);
2727 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2728 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2729 Register mdo = op->mdo()->as_register();
2730 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2731 Register tmp1 = op->tmp1()->as_register_lo();
2732 metadata2reg(md->constant_encoding(), mdo);
2733
2734 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2735 // Perform additional virtual call profiling for invokevirtual and
2736 // invokeinterface bytecodes
2737 if (op->should_profile_receiver_type()) {
2738 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2739 Register recv = op->recv()->as_register();
2740 assert_different_registers(mdo, tmp1, recv);
2741 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2742 ciKlass* known_klass = op->known_holder();
2743 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2744 // We know the type that will be seen at this call site; we can
2745 // statically update the MethodData* rather than needing to do
2746 // dynamic tests on the receiver type.
2747
2748 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2749 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2750 ciKlass* receiver = vc_data->receiver(i);
2751 if (known_klass->equals(receiver)) {
2752 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2753 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2754 return;
2755 }
2756 }
2757 // Receiver type is not found in profile data.
2758 // Fall back to runtime helper to handle the rest at runtime.
2759 metadata2reg(known_klass->constant_encoding(), recv);
2760 } else {
2761 __ load_klass(recv, recv);
2762 }
2763 type_profile_helper(mdo, md, data, recv, tmp1);
2764 } else {
2765 // static call
2766 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2767 }
2768 }
2769
2770 void LIR_Assembler::align_backward_branch_target() {
2771 __ align(OptoLoopAlignment);
2772 }
2773
2774 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2775 // tmp must be unused
2776 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2777 assert(left->is_register(), "can only handle registers");
2778
2779 if (left->is_single_cpu()) {
2780 __ z_lcr(dest->as_register(), left->as_register());
2781 } else if (left->is_single_fpu()) {
2782 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2783 } else if (left->is_double_fpu()) {
2784 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2785 } else {
2786 assert(left->is_double_cpu(), "Must be a long");
2787 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2788 }
2789 }
2790
2791 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2792 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2793 assert(!tmp->is_valid(), "don't need temporary");
2794 emit_call_c(dest);
2795 CHECK_BAILOUT();
2796 if (info != nullptr) {
2797 add_call_info_here(info);
2798 }
2799 __ post_call_nop();
2800 }
2801
2802 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2803 ShouldNotCallThis(); // not needed on ZARCH_64
2804 }
2805
2806 void LIR_Assembler::membar() {
2807 __ z_fence();
2808 }
2809
2810 void LIR_Assembler::membar_acquire() {
2811 __ z_acquire();
2812 }
2813
2814 void LIR_Assembler::membar_release() {
2815 __ z_release();
2816 }
2817
2818 void LIR_Assembler::membar_loadload() {
2819 __ z_acquire();
2820 }
2821
2822 void LIR_Assembler::membar_storestore() {
2823 __ z_release();
2824 }
2825
2826 void LIR_Assembler::membar_loadstore() {
2827 __ z_acquire();
2828 }
2829
2830 void LIR_Assembler::membar_storeload() {
2831 __ z_fence();
2832 }
2833
2834 void LIR_Assembler::on_spin_wait() {
2835 Unimplemented();
2836 }
2837
2838 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2839 assert(addr_opr->is_address(), "must be an address");
2840 assert(dest->is_register(), "must be a register");
2841
2842 LIR_Address* addr = addr_opr->as_address_ptr();
2843 Register reg = dest->as_pointer_register();
2844 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2845
2846 if (addr->index()->is_illegal() && patch_code != lir_patch_none) {
2847 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2848
2849 // TODO: Use load_const_32to64 here by extending NativeMovRegMem to support both instruction patterns.
2850 __ load_const(Z_R0_scratch, (intptr_t)0);
2851 __ z_agrk(reg, addr->base()->as_pointer_register(), Z_R0_scratch);
2852 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2853 } else {
2854 __ load_address(reg, as_Address(addr));
2855 }
2856 }
2857
2858 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2859 ShouldNotCallThis(); // unused
2860 }
2861
2862 #ifdef ASSERT
2863 // Emit run-time assertion.
2864 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2865 Unimplemented();
2866 }
2867 #endif
2868
2869 void LIR_Assembler::peephole(LIR_List*) {
2870 // Do nothing for now.
2871 }
2872
2873 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2874 assert(code == lir_xadd, "lir_xchg not supported");
2875 Address src_addr = as_Address(src->as_address_ptr());
2876 Register base = src_addr.base();
2877 intptr_t disp = src_addr.disp();
2878 if (src_addr.index()->is_valid()) {
2879 // LAA and LAAG do not support index register.
2880 __ load_address(Z_R1_scratch, src_addr);
2881 base = Z_R1_scratch;
2882 disp = 0;
2883 }
2884 if (data->type() == T_INT) {
2885 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2886 } else if (data->type() == T_LONG) {
2887 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2888 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2889 } else {
2890 ShouldNotReachHere();
2891 }
2892 }
2893
2894 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2895 Register obj = op->obj()->as_register();
2896 Register tmp1 = op->tmp()->as_pointer_register();
2897 Register tmp2 = Z_R1_scratch;
2898 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2899 ciKlass* exact_klass = op->exact_klass();
2900 intptr_t current_klass = op->current_klass();
2901 bool not_null = op->not_null();
2902 bool no_conflict = op->no_conflict();
2903
2904 Label update, next, none, null_seen, init_klass;
2905
2906 bool do_null = !not_null;
2907 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2908 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2909
2910 assert(do_null || do_update, "why are we here?");
2911 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2912
2913 __ verify_oop(obj, FILE_AND_LINE);
2914
2915 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2916 __ z_ltgr(tmp1, obj);
2917 }
2918 if (do_null) {
2919 __ z_brnz(update);
2920 if (!TypeEntries::was_null_seen(current_klass)) {
2921 __ z_lg(tmp1, mdo_addr);
2922 __ z_oill(tmp1, TypeEntries::null_seen);
2923 __ z_stg(tmp1, mdo_addr);
2924 }
2925 if (do_update) {
2926 __ z_bru(next);
2927 }
2928 } else {
2929 __ asm_assert(Assembler::bcondNotZero, "unexpected null obj", __LINE__);
2930 }
2931
2932 __ bind(update);
2933
2934 if (do_update) {
2935 #ifdef ASSERT
2936 if (exact_klass != nullptr) {
2937 __ load_klass(tmp1, tmp1);
2938 metadata2reg(exact_klass->constant_encoding(), tmp2);
2939 __ z_cgr(tmp1, tmp2);
2940 __ asm_assert(Assembler::bcondEqual, "exact klass and actual klass differ", __LINE__);
2941 }
2942 #endif
2943
2944 Label do_update;
2945 __ z_lg(tmp2, mdo_addr);
2946
2947 if (!no_conflict) {
2948 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2949 if (exact_klass != nullptr) {
2950 metadata2reg(exact_klass->constant_encoding(), tmp1);
2951 } else {
2952 __ load_klass(tmp1, tmp1);
2953 }
2954
2955 // Klass seen before: nothing to do (regardless of unknown bit).
2956 __ z_lgr(Z_R0_scratch, tmp2);
2957 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2958 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2959 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2960
2961 // Already unknown: Nothing to do anymore.
2962 __ z_tmll(tmp2, TypeEntries::type_unknown);
2963 __ z_brc(Assembler::bcondAllOne, next);
2964
2965 if (TypeEntries::is_type_none(current_klass)) {
2966 __ z_lgr(Z_R0_scratch, tmp2);
2967 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2968 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2969 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
2970 }
2971 } else {
2972 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2973 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2974
2975 // Already unknown: Nothing to do anymore.
2976 __ z_tmll(tmp2, TypeEntries::type_unknown);
2977 __ z_brc(Assembler::bcondAllOne, next);
2978 }
2979
2980 // Different than before. Cannot keep accurate profile.
2981 __ z_oill(tmp2, TypeEntries::type_unknown);
2982 __ z_bru(do_update);
2983 } else {
2984 // There's a single possible klass at this profile point.
2985 assert(exact_klass != nullptr, "should be");
2986 if (TypeEntries::is_type_none(current_klass)) {
2987 metadata2reg(exact_klass->constant_encoding(), tmp1);
2988 __ z_lgr(Z_R0_scratch, tmp2);
2989 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2990 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2991 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2992 #ifdef ASSERT
2993 {
2994 Label ok;
2995 __ z_lgr(Z_R0_scratch, tmp2);
2996 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2997 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2998 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
2999 __ stop("unexpected profiling mismatch");
3000 __ bind(ok);
3001 }
3002 #endif
3003
3004 } else {
3005 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3006 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3007
3008 // Already unknown: Nothing to do anymore.
3009 __ z_tmll(tmp2, TypeEntries::type_unknown);
3010 __ z_brc(Assembler::bcondAllOne, next);
3011 __ z_oill(tmp2, TypeEntries::type_unknown);
3012 __ z_bru(do_update);
3013 }
3014 }
3015
3016 __ bind(init_klass);
3017 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3018 __ z_ogr(tmp2, tmp1);
3019
3020 __ bind(do_update);
3021 __ z_stg(tmp2, mdo_addr);
3022
3023 __ bind(next);
3024 }
3025 }
3026
3027 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3028 assert(op->crc()->is_single_cpu(), "crc must be register");
3029 assert(op->val()->is_single_cpu(), "byte value must be register");
3030 assert(op->result_opr()->is_single_cpu(), "result must be register");
3031 Register crc = op->crc()->as_register();
3032 Register val = op->val()->as_register();
3033 Register res = op->result_opr()->as_register();
3034
3035 assert_different_registers(val, crc, res);
3036
3037 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3038 __ kernel_crc32_singleByteReg(crc, val, res, true);
3039 __ z_lgfr(res, crc);
3040 }
3041
3042 #undef __