1 /*
2 * Copyright (c) 2016, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_s390.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/safepointMechanism.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "utilities/macros.hpp"
43 #include "utilities/powerOfTwo.hpp"
44 #include "vmreg_s390.inline.hpp"
45
46 #define __ _masm->
47
48 #ifndef PRODUCT
49 #undef __
50 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
51 #endif
52
53 //------------------------------------------------------------
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 // Not used on ZARCH_64
57 ShouldNotCallThis();
58 return false;
59 }
60
61 LIR_Opr LIR_Assembler::receiverOpr() {
62 return FrameMap::Z_R2_oop_opr;
63 }
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::Z_R2_opr;
67 }
68
69 int LIR_Assembler::initial_frame_size_in_bytes() const {
70 return in_bytes(frame_map()->framesize_in_bytes());
71 }
72
73 // Inline cache check: done before the frame is built.
74 // The inline cached class is in Z_inline_cache(Z_R9).
75 // We fetch the class of the receiver and compare it with the cached class.
76 // If they do not match we jump to the slow case.
77 int LIR_Assembler::check_icache() {
78 return __ ic_check(CodeEntryAlignment);
79 }
80
81 void LIR_Assembler::clinit_barrier(ciMethod* method) {
82 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
83
84 Label L_skip_barrier;
85 Register klass = Z_R1_scratch;
86
87 metadata2reg(method->holder()->constant_encoding(), klass);
88 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
89
90 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
91 __ z_br(klass);
92
93 __ bind(L_skip_barrier);
94 }
95
96 void LIR_Assembler::osr_entry() {
97 // On-stack-replacement entry sequence (interpreter frame layout described in frame_s390.hpp):
98 //
99 // 1. Create a new compiled activation.
100 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
101 // at the osr_bci; it is not initialized.
102 // 3. Jump to the continuation address in compiled code to resume execution.
103
104 // OSR entry point
105 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
106 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
107 ValueStack* entry_state = osr_entry->end()->state();
108 int number_of_locks = entry_state->locks_size();
109
110 // Create a frame for the compiled activation.
111 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
112
113 // OSR buffer is
114 //
115 // locals[nlocals-1..0]
116 // monitors[number_of_locks-1..0]
117 //
118 // Locals is a direct copy of the interpreter frame so in the osr buffer
119 // the first slot in the local array is the last local from the interpreter
120 // and the last slot is local[0] (receiver) from the interpreter
121 //
122 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
123 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
124 // in the interpreter frame (the method lock if a sync method)
125
126 // Initialize monitors in the compiled activation.
127 // I0: pointer to osr buffer
128 //
129 // All other registers are dead at this point and the locals will be
130 // copied into place by code emitted in the IR.
131
132 Register OSR_buf = osrBufferPointer()->as_register();
133 {
134 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
135
136 const int locals_space = BytesPerWord * method() -> max_locals();
137 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
138 bool large_offset = !Immediate::is_simm20(monitor_offset + BytesPerWord) && number_of_locks > 0;
139
140 if (large_offset) {
141 // z_lg can only handle displacement upto 20bit signed binary integer
142 __ z_algfi(OSR_buf, locals_space);
143 monitor_offset -= locals_space;
144 }
145
146 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
147 // the OSR buffer using 2 word entries: first the lock and then
148 // the oop.
149 for (int i = 0; i < number_of_locks; i++) {
150 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
151 // Verify the interpreter's monitor has a non-null object.
152 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is null", __LINE__);
153 // Copy the lock field into the compiled activation.
154 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
155 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
156 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
157 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
158 }
159
160 if (large_offset) {
161 __ z_slgfi(OSR_buf, locals_space);
162 }
163 }
164 }
165
166 // --------------------------------------------------------------------------------------------
167
168 address LIR_Assembler::emit_call_c(address a) {
169 __ align_call_far_patchable(__ pc());
170 address call_addr = __ call_c_opt(a);
171 if (call_addr == nullptr) {
172 bailout("const section overflow");
173 }
174 return call_addr;
175 }
176
177 int LIR_Assembler::emit_exception_handler() {
178 // Generate code for exception handler.
179 address handler_base = __ start_a_stub(exception_handler_size());
180 if (handler_base == nullptr) {
181 // Not enough space left for the handler.
182 bailout("exception handler overflow");
183 return -1;
184 }
185
186 int offset = code_offset();
187
188 address a = Runtime1::entry_for (StubId::c1_handle_exception_from_callee_id);
189 address call_addr = emit_call_c(a);
190 CHECK_BAILOUT_(-1);
191 __ should_not_reach_here();
192 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
193 __ end_a_stub();
194
195 return offset;
196 }
197
198 // Emit the code to remove the frame from the stack in the exception
199 // unwind path.
200 int LIR_Assembler::emit_unwind_handler() {
201 #ifndef PRODUCT
202 if (CommentedAssembly) {
203 _masm->block_comment("Unwind handler");
204 }
205 #endif
206
207 int offset = code_offset();
208 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
209 Register Rtmp1 = Z_R11;
210 Register Rtmp2 = Z_R12;
211
212 // Fetch the exception from TLS and clear out exception related thread state.
213 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
214 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
215 __ z_lg(Z_EXC_OOP, exc_oop_addr);
216 __ clear_mem(exc_oop_addr, sizeof(oop));
217 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
218
219 __ bind(_unwind_handler_entry);
220 __ verify_not_null_oop(Z_EXC_OOP);
221 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
222 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
223 }
224
225 // Perform needed unlocking.
226 MonitorExitStub* stub = nullptr;
227 if (method()->is_synchronized()) {
228 // StubId::c1_monitorexit_id expects lock address in Z_R1_scratch.
229 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
230 monitor_address(0, lock);
231 stub = new MonitorExitStub(lock, 0);
232 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
233 __ bind(*stub->continuation());
234 }
235
236 if (compilation()->env()->dtrace_method_probes()) {
237 ShouldNotReachHere(); // Not supported.
238 #if 0
239 __ mov(rdi, r15_thread);
240 __ mov_metadata(rsi, method()->constant_encoding());
241 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
242 #endif
243 }
244
245 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
246 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
247 }
248
249 // Remove the activation and dispatch to the unwind handler.
250 __ pop_frame();
251 __ z_lg(Z_EXC_PC, _z_common_abi(return_pc), Z_SP);
252
253 // Z_EXC_OOP: exception oop
254 // Z_EXC_PC: exception pc
255
256 // Dispatch to the unwind logic.
257 __ load_const_optimized(Z_R5, Runtime1::entry_for (StubId::c1_unwind_exception_id));
258 __ z_br(Z_R5);
259
260 // Emit the slow path assembly.
261 if (stub != nullptr) {
262 stub->emit_code(this);
263 }
264
265 return offset;
266 }
267
268 int LIR_Assembler::emit_deopt_handler() {
269 // Generate code for exception handler.
270 address handler_base = __ start_a_stub(deopt_handler_size());
271 if (handler_base == nullptr) {
272 // Not enough space left for the handler.
273 bailout("deopt handler overflow");
274 return -1;
275 }
276
277 int offset = code_offset();
278
279 Label start;
280 __ bind(start);
281
282 // Size must be constant (see HandlerImpl::emit_deopt_handler).
283 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
284 __ call(Z_R1_scratch);
285
286 int entry_offset = __ offset();
287
288 __ z_bru(start);
289
290 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
291 __ end_a_stub();
292
293 return entry_offset;
294 }
295
296 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
297 if (o == nullptr) {
298 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
299 } else {
300 AddressLiteral a = __ allocate_oop_address(o);
301 bool success = __ load_oop_from_toc(reg, a, reg);
302 if (!success) {
303 bailout("const section overflow");
304 }
305 }
306 }
307
308 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
309 // Allocate a new index in table to hold the object once it's been patched.
310 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
311 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
312
313 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
314 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
315 // The null will be dynamically patched later so the sequence to
316 // load the address literal must not be optimized.
317 __ load_const(reg, addrlit);
318
319 patching_epilog(patch, lir_patch_normal, reg, info);
320 }
321
322 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
323 bool success = __ set_metadata_constant(md, reg);
324 if (!success) {
325 bailout("const section overflow");
326 return;
327 }
328 }
329
330 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
331 // Allocate a new index in table to hold the klass once it's been patched.
332 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
333 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
334 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
335 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
336 // The null will be dynamically patched later so the sequence to
337 // load the address literal must not be optimized.
338 __ load_const(reg, addrlit);
339
340 patching_epilog(patch, lir_patch_normal, reg, info);
341 }
342
343 void LIR_Assembler::emit_op3(LIR_Op3* op) {
344 switch (op->code()) {
345 case lir_idiv:
346 case lir_irem:
347 arithmetic_idiv(op->code(),
348 op->in_opr1(),
349 op->in_opr2(),
350 op->in_opr3(),
351 op->result_opr(),
352 op->info());
353 break;
354 case lir_fmad: {
355 const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
356 opr2 = op->in_opr2()->as_double_reg(),
357 opr3 = op->in_opr3()->as_double_reg(),
358 res = op->result_opr()->as_double_reg();
359 __ z_madbr(opr3, opr1, opr2);
360 if (res != opr3) { __ z_ldr(res, opr3); }
361 } break;
362 case lir_fmaf: {
363 const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
364 opr2 = op->in_opr2()->as_float_reg(),
365 opr3 = op->in_opr3()->as_float_reg(),
366 res = op->result_opr()->as_float_reg();
367 __ z_maebr(opr3, opr1, opr2);
368 if (res != opr3) { __ z_ler(res, opr3); }
369 } break;
370 default: ShouldNotReachHere(); break;
371 }
372 }
373
374
375 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
376 #ifdef ASSERT
377 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
378 if (op->block() != nullptr) { _branch_target_blocks.append(op->block()); }
379 if (op->ublock() != nullptr) { _branch_target_blocks.append(op->ublock()); }
380 #endif
381
382 if (op->cond() == lir_cond_always) {
383 if (op->info() != nullptr) { add_debug_info_for_branch(op->info()); }
384 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
385 } else {
386 Assembler::branch_condition acond = Assembler::bcondZero;
387 if (op->code() == lir_cond_float_branch) {
388 assert(op->ublock() != nullptr, "must have unordered successor");
389 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
390 }
391 switch (op->cond()) {
392 case lir_cond_equal: acond = Assembler::bcondEqual; break;
393 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
394 case lir_cond_less: acond = Assembler::bcondLow; break;
395 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
396 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
397 case lir_cond_greater: acond = Assembler::bcondHigh; break;
398 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
399 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
400 default: ShouldNotReachHere();
401 }
402 __ branch_optimized(acond,*(op->label()));
403 }
404 }
405
406
407 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
408 LIR_Opr src = op->in_opr();
409 LIR_Opr dest = op->result_opr();
410
411 switch (op->bytecode()) {
412 case Bytecodes::_i2l:
413 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
414 break;
415
416 case Bytecodes::_l2i:
417 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
418 break;
419
420 case Bytecodes::_i2b:
421 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
422 break;
423
424 case Bytecodes::_i2c:
425 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
426 break;
427
428 case Bytecodes::_i2s:
429 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
430 break;
431
432 case Bytecodes::_f2d:
433 assert(dest->is_double_fpu(), "check");
434 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
435 break;
436
437 case Bytecodes::_d2f:
438 assert(dest->is_single_fpu(), "check");
439 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
440 break;
441
442 case Bytecodes::_i2f:
443 __ z_cefbr(dest->as_float_reg(), src->as_register());
444 break;
445
446 case Bytecodes::_i2d:
447 __ z_cdfbr(dest->as_double_reg(), src->as_register());
448 break;
449
450 case Bytecodes::_l2f:
451 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
452 break;
453 case Bytecodes::_l2d:
454 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
455 break;
456
457 case Bytecodes::_f2i:
458 case Bytecodes::_f2l: {
459 Label done;
460 FloatRegister Rsrc = src->as_float_reg();
461 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
462 __ clear_reg(Rdst, true, false);
463 __ z_cebr(Rsrc, Rsrc);
464 __ z_brno(done); // NaN -> 0
465 if (op->bytecode() == Bytecodes::_f2i) {
466 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
467 } else { // op->bytecode() == Bytecodes::_f2l
468 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
469 }
470 __ bind(done);
471 }
472 break;
473
474 case Bytecodes::_d2i:
475 case Bytecodes::_d2l: {
476 Label done;
477 FloatRegister Rsrc = src->as_double_reg();
478 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
479 __ clear_reg(Rdst, true, false); // Don't set CC.
480 __ z_cdbr(Rsrc, Rsrc);
481 __ z_brno(done); // NaN -> 0
482 if (op->bytecode() == Bytecodes::_d2i) {
483 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
484 } else { // Bytecodes::_d2l
485 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
486 }
487 __ bind(done);
488 }
489 break;
490
491 default: ShouldNotReachHere();
492 }
493 }
494
495 void LIR_Assembler::align_call(LIR_Code code) {
496 // End of call instruction must be 4 byte aligned.
497 int offset = __ offset();
498 switch (code) {
499 case lir_icvirtual_call:
500 offset += MacroAssembler::load_const_from_toc_size();
501 // no break
502 case lir_static_call:
503 case lir_optvirtual_call:
504 case lir_dynamic_call:
505 offset += NativeCall::call_far_pcrelative_displacement_offset;
506 break;
507 default: ShouldNotReachHere();
508 }
509 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
510 __ nop();
511 }
512 }
513
514 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
515 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
516 "must be aligned (offset=%d)", __ offset());
517 assert(rtype == relocInfo::none ||
518 rtype == relocInfo::opt_virtual_call_type ||
519 rtype == relocInfo::static_call_type, "unexpected rtype");
520 // Prepend each BRASL with a nop.
521 __ relocate(rtype);
522 __ z_nop();
523 __ z_brasl(Z_R14, op->addr());
524 add_call_info(code_offset(), op->info());
525 }
526
527 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
528 address virtual_call_oop_addr = nullptr;
529 AddressLiteral empty_ic((address) Universe::non_oop_word());
530 virtual_call_oop_addr = __ pc();
531 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
532 if (!success) {
533 bailout("const section overflow");
534 return;
535 }
536
537 // CALL to fixup routine. Fixup routine uses ScopeDesc info
538 // to determine who we intended to call.
539 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
540 call(op, relocInfo::none);
541 }
542
543 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
544 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
545 }
546
547 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
548 assert(src->is_constant(), "should not call otherwise");
549 assert(dest->is_stack(), "should not call otherwise");
550 LIR_Const* c = src->as_constant_ptr();
551
552 unsigned int lmem = 0;
553 unsigned int lcon = 0;
554 int64_t cbits = 0;
555 Address dest_addr;
556 switch (c->type()) {
557 case T_INT: // fall through
558 case T_FLOAT:
559 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
560 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
561 break;
562
563 case T_ADDRESS:
564 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
565 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
566 break;
567
568 case T_OBJECT:
569 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
570 if (c->as_jobject() == nullptr) {
571 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
572 } else {
573 jobject2reg(c->as_jobject(), Z_R1_scratch);
574 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
575 }
576 return;
577
578 case T_LONG: // fall through
579 case T_DOUBLE:
580 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
581 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
582 break;
583
584 default:
585 ShouldNotReachHere();
586 }
587
588 __ store_const(dest_addr, cbits, lmem, lcon);
589 }
590
591 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
592 assert(src->is_constant(), "should not call otherwise");
593 assert(dest->is_address(), "should not call otherwise");
594
595 LIR_Const* c = src->as_constant_ptr();
596 Address addr = as_Address(dest->as_address_ptr());
597
598 int store_offset = -1;
599
600 if (dest->as_address_ptr()->index()->is_valid()) {
601 switch (type) {
602 case T_INT: // fall through
603 case T_FLOAT:
604 __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
605 store_offset = __ offset();
606 if (Immediate::is_uimm12(addr.disp())) {
607 __ z_st(Z_R0_scratch, addr);
608 } else {
609 __ z_sty(Z_R0_scratch, addr);
610 }
611 break;
612
613 case T_ADDRESS:
614 __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
615 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
616 break;
617
618 case T_OBJECT: // fall through
619 case T_ARRAY:
620 if (c->as_jobject() == nullptr) {
621 if (UseCompressedOops && !wide) {
622 __ clear_reg(Z_R1_scratch, false);
623 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
624 } else {
625 __ clear_reg(Z_R1_scratch, true);
626 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
627 }
628 } else {
629 jobject2reg(c->as_jobject(), Z_R1_scratch);
630 if (UseCompressedOops && !wide) {
631 __ encode_heap_oop(Z_R1_scratch);
632 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
633 } else {
634 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
635 }
636 }
637 assert(store_offset >= 0, "check");
638 break;
639
640 case T_LONG: // fall through
641 case T_DOUBLE:
642 __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
643 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
644 break;
645
646 case T_BOOLEAN: // fall through
647 case T_BYTE:
648 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
649 store_offset = __ offset();
650 if (Immediate::is_uimm12(addr.disp())) {
651 __ z_stc(Z_R0_scratch, addr);
652 } else {
653 __ z_stcy(Z_R0_scratch, addr);
654 }
655 break;
656
657 case T_CHAR: // fall through
658 case T_SHORT:
659 __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
660 store_offset = __ offset();
661 if (Immediate::is_uimm12(addr.disp())) {
662 __ z_sth(Z_R0_scratch, addr);
663 } else {
664 __ z_sthy(Z_R0_scratch, addr);
665 }
666 break;
667
668 default:
669 ShouldNotReachHere();
670 }
671
672 } else { // no index
673
674 unsigned int lmem = 0;
675 unsigned int lcon = 0;
676 int64_t cbits = 0;
677
678 switch (type) {
679 case T_INT: // fall through
680 case T_FLOAT:
681 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
682 break;
683
684 case T_ADDRESS:
685 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
686 break;
687
688 case T_OBJECT: // fall through
689 case T_ARRAY:
690 if (c->as_jobject() == nullptr) {
691 if (UseCompressedOops && !wide) {
692 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
693 } else {
694 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
695 }
696 } else {
697 jobject2reg(c->as_jobject(), Z_R1_scratch);
698 if (UseCompressedOops && !wide) {
699 __ encode_heap_oop(Z_R1_scratch);
700 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
701 } else {
702 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
703 }
704 }
705 assert(store_offset >= 0, "check");
706 break;
707
708 case T_LONG: // fall through
709 case T_DOUBLE:
710 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
711 break;
712
713 case T_BOOLEAN: // fall through
714 case T_BYTE:
715 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
716 break;
717
718 case T_CHAR: // fall through
719 case T_SHORT:
720 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
721 break;
722
723 default:
724 ShouldNotReachHere();
725 }
726
727 if (store_offset == -1) {
728 store_offset = __ store_const(addr, cbits, lmem, lcon);
729 assert(store_offset >= 0, "check");
730 }
731 }
732
733 if (info != nullptr) {
734 add_debug_info_for_null_check(store_offset, info);
735 }
736 }
737
738 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
739 assert(src->is_constant(), "should not call otherwise");
740 assert(dest->is_register(), "should not call otherwise");
741 LIR_Const* c = src->as_constant_ptr();
742
743 switch (c->type()) {
744 case T_INT: {
745 assert(patch_code == lir_patch_none, "no patching handled here");
746 __ load_const_optimized(dest->as_register(), c->as_jint());
747 break;
748 }
749
750 case T_ADDRESS: {
751 assert(patch_code == lir_patch_none, "no patching handled here");
752 __ load_const_optimized(dest->as_register(), c->as_jint());
753 break;
754 }
755
756 case T_LONG: {
757 assert(patch_code == lir_patch_none, "no patching handled here");
758 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
759 break;
760 }
761
762 case T_OBJECT: {
763 if (patch_code != lir_patch_none) {
764 jobject2reg_with_patching(dest->as_register(), info);
765 } else {
766 jobject2reg(c->as_jobject(), dest->as_register());
767 }
768 break;
769 }
770
771 case T_METADATA: {
772 if (patch_code != lir_patch_none) {
773 klass2reg_with_patching(dest->as_register(), info);
774 } else {
775 metadata2reg(c->as_metadata(), dest->as_register());
776 }
777 break;
778 }
779
780 case T_FLOAT: {
781 Register toc_reg = Z_R1_scratch;
782 __ load_toc(toc_reg);
783 address const_addr = __ float_constant(c->as_jfloat());
784 if (const_addr == nullptr) {
785 bailout("const section overflow");
786 break;
787 }
788 int displ = const_addr - _masm->code()->consts()->start();
789 if (dest->is_single_fpu()) {
790 __ z_ley(dest->as_float_reg(), displ, toc_reg);
791 } else {
792 assert(dest->is_single_cpu(), "Must be a cpu register.");
793 __ z_ly(dest->as_register(), displ, toc_reg);
794 }
795 }
796 break;
797
798 case T_DOUBLE: {
799 Register toc_reg = Z_R1_scratch;
800 __ load_toc(toc_reg);
801 address const_addr = __ double_constant(c->as_jdouble());
802 if (const_addr == nullptr) {
803 bailout("const section overflow");
804 break;
805 }
806 int displ = const_addr - _masm->code()->consts()->start();
807 if (dest->is_double_fpu()) {
808 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
809 } else {
810 assert(dest->is_double_cpu(), "Must be a long register.");
811 __ z_lg(dest->as_register_lo(), displ, toc_reg);
812 }
813 }
814 break;
815
816 default:
817 ShouldNotReachHere();
818 }
819 }
820
821 Address LIR_Assembler::as_Address(LIR_Address* addr) {
822 if (addr->base()->is_illegal()) {
823 Unimplemented();
824 }
825
826 Register base = addr->base()->as_pointer_register();
827
828 if (addr->index()->is_illegal()) {
829 return Address(base, addr->disp());
830 } else if (addr->index()->is_cpu_register()) {
831 Register index = addr->index()->as_pointer_register();
832 return Address(base, index, addr->disp());
833 } else if (addr->index()->is_constant()) {
834 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
835 return Address(base, addr_offset);
836 } else {
837 ShouldNotReachHere();
838 return Address();
839 }
840 }
841
842 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
843 switch (type) {
844 case T_INT:
845 case T_FLOAT: {
846 Register tmp = Z_R1_scratch;
847 Address from = frame_map()->address_for_slot(src->single_stack_ix());
848 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
849 __ mem2reg_opt(tmp, from, false);
850 __ reg2mem_opt(tmp, to, false);
851 break;
852 }
853 case T_ADDRESS:
854 case T_OBJECT: {
855 Register tmp = Z_R1_scratch;
856 Address from = frame_map()->address_for_slot(src->single_stack_ix());
857 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
858 __ mem2reg_opt(tmp, from, true);
859 __ reg2mem_opt(tmp, to, true);
860 break;
861 }
862 case T_LONG:
863 case T_DOUBLE: {
864 Register tmp = Z_R1_scratch;
865 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
866 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
867 __ mem2reg_opt(tmp, from, true);
868 __ reg2mem_opt(tmp, to, true);
869 break;
870 }
871
872 default:
873 ShouldNotReachHere();
874 }
875 }
876
877 // 4-byte accesses only! Don't use it to access 8 bytes!
878 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
879 ShouldNotCallThis();
880 return Address(); // unused
881 }
882
883 // 4-byte accesses only! Don't use it to access 8 bytes!
884 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
885 ShouldNotCallThis();
886 return Address(); // unused
887 }
888
889 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
890 CodeEmitInfo* info, bool wide) {
891
892 assert(type != T_METADATA, "load of metadata ptr not supported");
893 LIR_Address* addr = src_opr->as_address_ptr();
894 LIR_Opr to_reg = dest;
895
896 Register src = addr->base()->as_pointer_register();
897 Register disp_reg = Z_R0;
898 int disp_value = addr->disp();
899 bool needs_patching = (patch_code != lir_patch_none);
900
901 if (addr->base()->type() == T_OBJECT) {
902 __ verify_oop(src, FILE_AND_LINE);
903 }
904
905 PatchingStub* patch = nullptr;
906 if (needs_patching) {
907 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
908 assert(!to_reg->is_double_cpu() ||
909 patch_code == lir_patch_none ||
910 patch_code == lir_patch_normal, "patching doesn't match register");
911 }
912
913 if (addr->index()->is_illegal()) {
914 if (!Immediate::is_simm20(disp_value)) {
915 if (needs_patching) {
916 __ load_const(Z_R1_scratch, (intptr_t)0);
917 } else {
918 __ load_const_optimized(Z_R1_scratch, disp_value);
919 }
920 disp_reg = Z_R1_scratch;
921 disp_value = 0;
922 }
923 } else {
924 if (!Immediate::is_simm20(disp_value)) {
925 __ load_const_optimized(Z_R1_scratch, disp_value);
926 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
927 disp_reg = Z_R1_scratch;
928 disp_value = 0;
929 }
930 disp_reg = addr->index()->as_pointer_register();
931 }
932
933 // Remember the offset of the load. The patching_epilog must be done
934 // before the call to add_debug_info, otherwise the PcDescs don't get
935 // entered in increasing order.
936 int offset = code_offset();
937
938 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
939
940 bool short_disp = Immediate::is_uimm12(disp_value);
941
942 switch (type) {
943 case T_BOOLEAN: // fall through
944 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
945 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
946 case T_SHORT :
947 if (short_disp) {
948 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
949 } else {
950 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
951 }
952 break;
953 case T_INT :
954 if (short_disp) {
955 __ z_l(dest->as_register(), disp_value, disp_reg, src);
956 } else {
957 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
958 }
959 break;
960 case T_ADDRESS:
961 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
962 break;
963 case T_ARRAY : // fall through
964 case T_OBJECT:
965 {
966 if (UseCompressedOops && !wide) {
967 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
968 __ oop_decoder(dest->as_register(), dest->as_register(), true);
969 } else {
970 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
971 }
972 __ verify_oop(dest->as_register(), FILE_AND_LINE);
973 break;
974 }
975 case T_FLOAT:
976 if (short_disp) {
977 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
978 } else {
979 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
980 }
981 break;
982 case T_DOUBLE:
983 if (short_disp) {
984 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
985 } else {
986 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
987 }
988 break;
989 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
990 default : ShouldNotReachHere();
991 }
992
993 if (patch != nullptr) {
994 patching_epilog(patch, patch_code, src, info);
995 }
996 if (info != nullptr) add_debug_info_for_null_check(offset, info);
997 }
998
999 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1000 assert(src->is_stack(), "should not call otherwise");
1001 assert(dest->is_register(), "should not call otherwise");
1002
1003 if (dest->is_single_cpu()) {
1004 if (is_reference_type(type)) {
1005 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1006 __ verify_oop(dest->as_register(), FILE_AND_LINE);
1007 } else if (type == T_METADATA || type == T_ADDRESS) {
1008 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1009 } else {
1010 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
1011 }
1012 } else if (dest->is_double_cpu()) {
1013 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
1014 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
1015 } else if (dest->is_single_fpu()) {
1016 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1017 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
1018 } else if (dest->is_double_fpu()) {
1019 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1020 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1027 assert(src->is_register(), "should not call otherwise");
1028 assert(dest->is_stack(), "should not call otherwise");
1029
1030 if (src->is_single_cpu()) {
1031 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1032 if (is_reference_type(type)) {
1033 __ verify_oop(src->as_register(), FILE_AND_LINE);
1034 __ reg2mem_opt(src->as_register(), dst, true);
1035 } else if (type == T_METADATA || type == T_ADDRESS) {
1036 __ reg2mem_opt(src->as_register(), dst, true);
1037 } else {
1038 __ reg2mem_opt(src->as_register(), dst, false);
1039 }
1040 } else if (src->is_double_cpu()) {
1041 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1042 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1043 } else if (src->is_single_fpu()) {
1044 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1045 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1046 } else if (src->is_double_fpu()) {
1047 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1048 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1049 } else {
1050 ShouldNotReachHere();
1051 }
1052 }
1053
1054 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1055 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1056 if (from_reg->is_double_fpu()) {
1057 // double to double moves
1058 assert(to_reg->is_double_fpu(), "should match");
1059 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1060 } else {
1061 // float to float moves
1062 assert(to_reg->is_single_fpu(), "should match");
1063 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1064 }
1065 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1066 if (from_reg->is_double_cpu()) {
1067 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1068 } else if (to_reg->is_double_cpu()) {
1069 // int to int moves
1070 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1071 } else {
1072 // int to int moves
1073 __ z_lgr(to_reg->as_register(), from_reg->as_register());
1074 }
1075 } else {
1076 ShouldNotReachHere();
1077 }
1078 if (is_reference_type(to_reg->type())) {
1079 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1080 }
1081 }
1082
1083 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1084 LIR_PatchCode patch_code, CodeEmitInfo* info,
1085 bool wide) {
1086 assert(type != T_METADATA, "store of metadata ptr not supported");
1087 LIR_Address* addr = dest_opr->as_address_ptr();
1088
1089 Register dest = addr->base()->as_pointer_register();
1090 Register disp_reg = Z_R0;
1091 int disp_value = addr->disp();
1092 bool needs_patching = (patch_code != lir_patch_none);
1093
1094 if (addr->base()->is_oop_register()) {
1095 __ verify_oop(dest, FILE_AND_LINE);
1096 }
1097
1098 PatchingStub* patch = nullptr;
1099 if (needs_patching) {
1100 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1101 assert(!from->is_double_cpu() ||
1102 patch_code == lir_patch_none ||
1103 patch_code == lir_patch_normal, "patching doesn't match register");
1104 }
1105
1106 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1107 if (addr->index()->is_illegal()) {
1108 if (!Immediate::is_simm20(disp_value)) {
1109 if (needs_patching) {
1110 __ load_const(Z_R1_scratch, (intptr_t)0);
1111 } else {
1112 __ load_const_optimized(Z_R1_scratch, disp_value);
1113 }
1114 disp_reg = Z_R1_scratch;
1115 disp_value = 0;
1116 }
1117 } else {
1118 if (!Immediate::is_simm20(disp_value)) {
1119 __ load_const_optimized(Z_R1_scratch, disp_value);
1120 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1121 disp_reg = Z_R1_scratch;
1122 disp_value = 0;
1123 }
1124 disp_reg = addr->index()->as_pointer_register();
1125 }
1126
1127 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1128
1129 if (is_reference_type(type)) {
1130 __ verify_oop(from->as_register(), FILE_AND_LINE);
1131 }
1132
1133 bool short_disp = Immediate::is_uimm12(disp_value);
1134
1135 // Remember the offset of the store. The patching_epilog must be done
1136 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1137 // entered in increasing order.
1138 int offset = code_offset();
1139 switch (type) {
1140 case T_BOOLEAN: // fall through
1141 case T_BYTE :
1142 if (short_disp) {
1143 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1144 } else {
1145 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1146 }
1147 break;
1148 case T_CHAR : // fall through
1149 case T_SHORT :
1150 if (short_disp) {
1151 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1152 } else {
1153 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1154 }
1155 break;
1156 case T_INT :
1157 if (short_disp) {
1158 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1159 } else {
1160 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1161 }
1162 break;
1163 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1164 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1165 break;
1166 case T_ARRAY : // fall through
1167 case T_OBJECT:
1168 {
1169 if (UseCompressedOops && !wide) {
1170 Register compressed_src = Z_R14;
1171 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1172 offset = code_offset();
1173 if (short_disp) {
1174 __ z_st(compressed_src, disp_value, disp_reg, dest);
1175 } else {
1176 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1177 }
1178 } else {
1179 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1180 }
1181 break;
1182 }
1183 case T_FLOAT :
1184 if (short_disp) {
1185 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1186 } else {
1187 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1188 }
1189 break;
1190 case T_DOUBLE:
1191 if (short_disp) {
1192 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1193 } else {
1194 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1195 }
1196 break;
1197 default: ShouldNotReachHere();
1198 }
1199
1200 if (patch != nullptr) {
1201 patching_epilog(patch, patch_code, dest, info);
1202 }
1203
1204 if (info != nullptr) add_debug_info_for_null_check(offset, info);
1205 }
1206
1207
1208 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1209 assert(result->is_illegal() ||
1210 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1211 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1212 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1213 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1214
1215 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1216
1217 // Pop the frame before the safepoint code.
1218 __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1219
1220 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1221 __ reserved_stack_check(Z_R14);
1222 }
1223
1224 // We need to mark the code position where the load from the safepoint
1225 // polling page was emitted as relocInfo::poll_return_type here.
1226 __ relocate(relocInfo::poll_return_type);
1227 __ load_from_polling_page(Z_R1_scratch);
1228
1229 __ z_br(Z_R14); // Return to caller.
1230 }
1231
1232 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1233 const Register poll_addr = tmp->as_register_lo();
1234 __ z_lg(poll_addr, Address(Z_thread, JavaThread::polling_page_offset()));
1235 guarantee(info != nullptr, "Shouldn't be null");
1236 add_debug_info_for_branch(info);
1237 int offset = __ offset();
1238 __ relocate(relocInfo::poll_type);
1239 __ load_from_polling_page(poll_addr);
1240 return offset;
1241 }
1242
1243 void LIR_Assembler::emit_static_call_stub() {
1244
1245 // Stub is fixed up when the corresponding call is converted from calling
1246 // compiled code to calling interpreted code.
1247
1248 address call_pc = __ pc();
1249 address stub = __ start_a_stub(call_stub_size());
1250 if (stub == nullptr) {
1251 bailout("static call stub overflow");
1252 return;
1253 }
1254
1255 int start = __ offset();
1256
1257 __ relocate(static_stub_Relocation::spec(call_pc));
1258
1259 // See also Matcher::interpreter_method_reg().
1260 AddressLiteral meta = __ allocate_metadata_address(nullptr);
1261 bool success = __ load_const_from_toc(Z_method, meta);
1262
1263 __ set_inst_mark();
1264 AddressLiteral a((address)-1);
1265 success = success && __ load_const_from_toc(Z_R1, a);
1266 if (!success) {
1267 bailout("const section overflow");
1268 return;
1269 }
1270
1271 __ z_br(Z_R1);
1272 assert(__ offset() - start <= call_stub_size(), "stub too big");
1273 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1274 }
1275
1276 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1277 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1278 if (opr1->is_single_cpu()) {
1279 Register reg1 = opr1->as_register();
1280 if (opr2->is_single_cpu()) {
1281 // cpu register - cpu register
1282 if (is_reference_type(opr1->type())) {
1283 __ z_clgr(reg1, opr2->as_register());
1284 } else {
1285 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1286 if (unsigned_comp) {
1287 __ z_clr(reg1, opr2->as_register());
1288 } else {
1289 __ z_cr(reg1, opr2->as_register());
1290 }
1291 }
1292 } else if (opr2->is_stack()) {
1293 // cpu register - stack
1294 if (is_reference_type(opr1->type())) {
1295 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1296 } else {
1297 if (unsigned_comp) {
1298 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1299 } else {
1300 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1301 }
1302 }
1303 } else if (opr2->is_constant()) {
1304 // cpu register - constant
1305 LIR_Const* c = opr2->as_constant_ptr();
1306 if (c->type() == T_INT) {
1307 if (unsigned_comp) {
1308 __ z_clfi(reg1, c->as_jint());
1309 } else {
1310 __ z_cfi(reg1, c->as_jint());
1311 }
1312 } else if (c->type() == T_METADATA) {
1313 // We only need, for now, comparison with null for metadata.
1314 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1315 Metadata* m = c->as_metadata();
1316 if (m == nullptr) {
1317 __ z_cghi(reg1, 0);
1318 } else {
1319 ShouldNotReachHere();
1320 }
1321 } else if (is_reference_type(c->type())) {
1322 // In 64bit oops are single register.
1323 jobject o = c->as_jobject();
1324 if (o == nullptr) {
1325 __ z_ltgr(reg1, reg1);
1326 } else {
1327 jobject2reg(o, Z_R1_scratch);
1328 __ z_cgr(reg1, Z_R1_scratch);
1329 }
1330 } else {
1331 fatal("unexpected type: %s", basictype_to_str(c->type()));
1332 }
1333 // cpu register - address
1334 } else if (opr2->is_address()) {
1335 if (op->info() != nullptr) {
1336 add_debug_info_for_null_check_here(op->info());
1337 }
1338 if (unsigned_comp) {
1339 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1340 } else {
1341 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1342 }
1343 } else {
1344 ShouldNotReachHere();
1345 }
1346
1347 } else if (opr1->is_double_cpu()) {
1348 assert(!unsigned_comp, "unexpected");
1349 Register xlo = opr1->as_register_lo();
1350 Register xhi = opr1->as_register_hi();
1351 if (opr2->is_double_cpu()) {
1352 __ z_cgr(xlo, opr2->as_register_lo());
1353 } else if (opr2->is_constant()) {
1354 // cpu register - constant 0
1355 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1356 __ z_ltgr(xlo, xlo);
1357 } else {
1358 ShouldNotReachHere();
1359 }
1360
1361 } else if (opr1->is_single_fpu()) {
1362 if (opr2->is_single_fpu()) {
1363 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1364 } else {
1365 // stack slot
1366 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1367 if (Immediate::is_uimm12(addr.disp())) {
1368 __ z_ceb(opr1->as_float_reg(), addr);
1369 } else {
1370 __ z_ley(Z_fscratch_1, addr);
1371 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1372 }
1373 }
1374 } else if (opr1->is_double_fpu()) {
1375 if (opr2->is_double_fpu()) {
1376 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1377 } else {
1378 // stack slot
1379 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1380 if (Immediate::is_uimm12(addr.disp())) {
1381 __ z_cdb(opr1->as_double_reg(), addr);
1382 } else {
1383 __ z_ldy(Z_fscratch_1, addr);
1384 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1385 }
1386 }
1387 } else {
1388 ShouldNotReachHere();
1389 }
1390 }
1391
1392 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1393 Label done;
1394 Register dreg = dst->as_register();
1395
1396 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1397 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1398 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1399 bool is_single = left->is_single_fpu();
1400 bool is_unordered_less = (code == lir_ucmp_fd2i);
1401 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1402 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1403 if (is_single) {
1404 __ z_cebr(lreg, rreg);
1405 } else {
1406 __ z_cdbr(lreg, rreg);
1407 }
1408 if (VM_Version::has_LoadStoreConditional()) {
1409 Register one = Z_R0_scratch;
1410 Register minus_one = Z_R1_scratch;
1411 __ z_lghi(minus_one, -1);
1412 __ z_lghi(one, 1);
1413 __ z_lghi(dreg, 0);
1414 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1415 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1416 } else {
1417 __ clear_reg(dreg, true, false);
1418 __ z_bre(done); // if (left == right) dst = 0
1419
1420 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1421 __ z_lhi(dreg, 1);
1422 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1423
1424 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1425 __ z_lhi(dreg, -1);
1426 }
1427 } else {
1428 assert(code == lir_cmp_l2i, "check");
1429 if (VM_Version::has_LoadStoreConditional()) {
1430 Register one = Z_R0_scratch;
1431 Register minus_one = Z_R1_scratch;
1432 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1433 __ z_lghi(minus_one, -1);
1434 __ z_lghi(one, 1);
1435 __ z_lghi(dreg, 0);
1436 __ z_locgr(dreg, one, Assembler::bcondHigh);
1437 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1438 } else {
1439 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1440 __ z_lghi(dreg, 0); // eq value
1441 __ z_bre(done);
1442 __ z_lghi(dreg, 1); // gt value
1443 __ z_brh(done);
1444 __ z_lghi(dreg, -1); // lt value
1445 }
1446 }
1447 __ bind(done);
1448 }
1449
1450 // result = condition ? opr1 : opr2
1451 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1452 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1453 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390");
1454
1455 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1456 switch (condition) {
1457 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1458 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1459 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1460 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1461 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1462 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1463 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1464 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1465 default: ShouldNotReachHere();
1466 }
1467
1468 if (opr1->is_cpu_register()) {
1469 reg2reg(opr1, result);
1470 } else if (opr1->is_stack()) {
1471 stack2reg(opr1, result, result->type());
1472 } else if (opr1->is_constant()) {
1473 const2reg(opr1, result, lir_patch_none, nullptr);
1474 } else {
1475 ShouldNotReachHere();
1476 }
1477
1478 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1479 // Optimized version that does not require a branch.
1480 if (opr2->is_single_cpu()) {
1481 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1482 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1483 } else if (opr2->is_double_cpu()) {
1484 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1485 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1486 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1487 } else if (opr2->is_single_stack()) {
1488 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1489 } else if (opr2->is_double_stack()) {
1490 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1491 } else {
1492 ShouldNotReachHere();
1493 }
1494 } else {
1495 Label skip;
1496 __ z_brc(acond, skip);
1497 if (opr2->is_cpu_register()) {
1498 reg2reg(opr2, result);
1499 } else if (opr2->is_stack()) {
1500 stack2reg(opr2, result, result->type());
1501 } else if (opr2->is_constant()) {
1502 const2reg(opr2, result, lir_patch_none, nullptr);
1503 } else {
1504 ShouldNotReachHere();
1505 }
1506 __ bind(skip);
1507 }
1508 }
1509
1510 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1511 CodeEmitInfo* info) {
1512 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1513
1514 if (left->is_single_cpu()) {
1515 assert(left == dest, "left and dest must be equal");
1516 Register lreg = left->as_register();
1517
1518 if (right->is_single_cpu()) {
1519 // cpu register - cpu register
1520 Register rreg = right->as_register();
1521 switch (code) {
1522 case lir_add: __ z_ar (lreg, rreg); break;
1523 case lir_sub: __ z_sr (lreg, rreg); break;
1524 case lir_mul: __ z_msr(lreg, rreg); break;
1525 default: ShouldNotReachHere();
1526 }
1527
1528 } else if (right->is_stack()) {
1529 // cpu register - stack
1530 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1531 switch (code) {
1532 case lir_add: __ z_ay(lreg, raddr); break;
1533 case lir_sub: __ z_sy(lreg, raddr); break;
1534 default: ShouldNotReachHere();
1535 }
1536
1537 } else if (right->is_constant()) {
1538 // cpu register - constant
1539 jint c = right->as_constant_ptr()->as_jint();
1540 switch (code) {
1541 case lir_add:
1542 __ add2reg_32(lreg, c);
1543 break;
1544 case lir_sub:
1545 __ add2reg_32(lreg, java_negate(c));
1546 break;
1547 case lir_mul: __ z_msfi(lreg, c); break;
1548 default: ShouldNotReachHere();
1549 }
1550
1551 } else {
1552 ShouldNotReachHere();
1553 }
1554
1555 } else if (left->is_double_cpu()) {
1556 assert(left == dest, "left and dest must be equal");
1557 Register lreg_lo = left->as_register_lo();
1558 Register lreg_hi = left->as_register_hi();
1559
1560 if (right->is_double_cpu()) {
1561 // cpu register - cpu register
1562 Register rreg_lo = right->as_register_lo();
1563 Register rreg_hi = right->as_register_hi();
1564 assert_different_registers(lreg_lo, rreg_lo);
1565 switch (code) {
1566 case lir_add:
1567 __ z_agr(lreg_lo, rreg_lo);
1568 break;
1569 case lir_sub:
1570 __ z_sgr(lreg_lo, rreg_lo);
1571 break;
1572 case lir_mul:
1573 __ z_msgr(lreg_lo, rreg_lo);
1574 break;
1575 default:
1576 ShouldNotReachHere();
1577 }
1578
1579 } else if (right->is_constant()) {
1580 // cpu register - constant
1581 jlong c = right->as_constant_ptr()->as_jlong_bits();
1582 switch (code) {
1583 case lir_add: __ z_agfi(lreg_lo, c); break;
1584 case lir_sub:
1585 if (c != min_jint) {
1586 __ z_agfi(lreg_lo, -c);
1587 } else {
1588 // -min_jint cannot be represented as simm32 in z_agfi
1589 // min_jint sign extended: 0xffffffff80000000
1590 // -min_jint as 64 bit integer: 0x0000000080000000
1591 // 0x80000000 can be represented as uimm32 in z_algfi
1592 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1593 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1594 }
1595 break;
1596 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1597 default:
1598 ShouldNotReachHere();
1599 }
1600
1601 } else {
1602 ShouldNotReachHere();
1603 }
1604
1605 } else if (left->is_single_fpu()) {
1606 assert(left == dest, "left and dest must be equal");
1607 FloatRegister lreg = left->as_float_reg();
1608 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1609 Address raddr;
1610
1611 if (rreg == fnoreg) {
1612 assert(right->is_single_stack(), "constants should be loaded into register");
1613 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1614 if (!Immediate::is_uimm12(raddr.disp())) {
1615 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1616 }
1617 }
1618
1619 if (rreg != fnoreg) {
1620 switch (code) {
1621 case lir_add: __ z_aebr(lreg, rreg); break;
1622 case lir_sub: __ z_sebr(lreg, rreg); break;
1623 case lir_mul: __ z_meebr(lreg, rreg); break;
1624 case lir_div: __ z_debr(lreg, rreg); break;
1625 default: ShouldNotReachHere();
1626 }
1627 } else {
1628 switch (code) {
1629 case lir_add: __ z_aeb(lreg, raddr); break;
1630 case lir_sub: __ z_seb(lreg, raddr); break;
1631 case lir_mul: __ z_meeb(lreg, raddr); break;
1632 case lir_div: __ z_deb(lreg, raddr); break;
1633 default: ShouldNotReachHere();
1634 }
1635 }
1636 } else if (left->is_double_fpu()) {
1637 assert(left == dest, "left and dest must be equal");
1638 FloatRegister lreg = left->as_double_reg();
1639 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1640 Address raddr;
1641
1642 if (rreg == fnoreg) {
1643 assert(right->is_double_stack(), "constants should be loaded into register");
1644 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1645 if (!Immediate::is_uimm12(raddr.disp())) {
1646 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1647 }
1648 }
1649
1650 if (rreg != fnoreg) {
1651 switch (code) {
1652 case lir_add: __ z_adbr(lreg, rreg); break;
1653 case lir_sub: __ z_sdbr(lreg, rreg); break;
1654 case lir_mul: __ z_mdbr(lreg, rreg); break;
1655 case lir_div: __ z_ddbr(lreg, rreg); break;
1656 default: ShouldNotReachHere();
1657 }
1658 } else {
1659 switch (code) {
1660 case lir_add: __ z_adb(lreg, raddr); break;
1661 case lir_sub: __ z_sdb(lreg, raddr); break;
1662 case lir_mul: __ z_mdb(lreg, raddr); break;
1663 case lir_div: __ z_ddb(lreg, raddr); break;
1664 default: ShouldNotReachHere();
1665 }
1666 }
1667 } else if (left->is_address()) {
1668 assert(left == dest, "left and dest must be equal");
1669 assert(code == lir_add, "unsupported operation");
1670 assert(right->is_constant(), "unsupported operand");
1671 jint c = right->as_constant_ptr()->as_jint();
1672 LIR_Address* lir_addr = left->as_address_ptr();
1673 Address addr = as_Address(lir_addr);
1674 switch (lir_addr->type()) {
1675 case T_INT:
1676 __ add2mem_32(addr, c, Z_R1_scratch);
1677 break;
1678 case T_LONG:
1679 __ add2mem_64(addr, c, Z_R1_scratch);
1680 break;
1681 default:
1682 ShouldNotReachHere();
1683 }
1684 } else {
1685 ShouldNotReachHere();
1686 }
1687 }
1688
1689 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1690 switch (code) {
1691 case lir_sqrt: {
1692 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1693 FloatRegister src_reg = value->as_double_reg();
1694 FloatRegister dst_reg = dest->as_double_reg();
1695 __ z_sqdbr(dst_reg, src_reg);
1696 break;
1697 }
1698 case lir_abs: {
1699 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1700 FloatRegister src_reg = value->as_double_reg();
1701 FloatRegister dst_reg = dest->as_double_reg();
1702 __ z_lpdbr(dst_reg, src_reg);
1703 break;
1704 }
1705 default: {
1706 ShouldNotReachHere();
1707 break;
1708 }
1709 }
1710 }
1711
1712 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1713 if (left->is_single_cpu()) {
1714 Register reg = left->as_register();
1715 if (right->is_constant()) {
1716 int val = right->as_constant_ptr()->as_jint();
1717 switch (code) {
1718 case lir_logic_and: __ z_nilf(reg, val); break;
1719 case lir_logic_or: __ z_oilf(reg, val); break;
1720 case lir_logic_xor: __ z_xilf(reg, val); break;
1721 default: ShouldNotReachHere();
1722 }
1723 } else if (right->is_stack()) {
1724 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1725 switch (code) {
1726 case lir_logic_and: __ z_ny(reg, raddr); break;
1727 case lir_logic_or: __ z_oy(reg, raddr); break;
1728 case lir_logic_xor: __ z_xy(reg, raddr); break;
1729 default: ShouldNotReachHere();
1730 }
1731 } else {
1732 Register rright = right->as_register();
1733 switch (code) {
1734 case lir_logic_and: __ z_nr(reg, rright); break;
1735 case lir_logic_or : __ z_or(reg, rright); break;
1736 case lir_logic_xor: __ z_xr(reg, rright); break;
1737 default: ShouldNotReachHere();
1738 }
1739 }
1740 move_regs(reg, dst->as_register());
1741 } else {
1742 Register l_lo = left->as_register_lo();
1743 if (right->is_constant()) {
1744 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1745 switch (code) {
1746 case lir_logic_and:
1747 __ z_ngr(l_lo, Z_R1_scratch);
1748 break;
1749 case lir_logic_or:
1750 __ z_ogr(l_lo, Z_R1_scratch);
1751 break;
1752 case lir_logic_xor:
1753 __ z_xgr(l_lo, Z_R1_scratch);
1754 break;
1755 default: ShouldNotReachHere();
1756 }
1757 } else {
1758 Register r_lo;
1759 if (is_reference_type(right->type())) {
1760 r_lo = right->as_register();
1761 } else {
1762 r_lo = right->as_register_lo();
1763 }
1764 switch (code) {
1765 case lir_logic_and:
1766 __ z_ngr(l_lo, r_lo);
1767 break;
1768 case lir_logic_or:
1769 __ z_ogr(l_lo, r_lo);
1770 break;
1771 case lir_logic_xor:
1772 __ z_xgr(l_lo, r_lo);
1773 break;
1774 default: ShouldNotReachHere();
1775 }
1776 }
1777
1778 Register dst_lo = dst->as_register_lo();
1779
1780 move_regs(l_lo, dst_lo);
1781 }
1782 }
1783
1784 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1785 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1786 if (left->is_double_cpu()) {
1787 // 64 bit integer case
1788 assert(left->is_double_cpu(), "left must be register");
1789 assert(right->is_double_cpu() || is_power_of_2(right->as_jlong()),
1790 "right must be register or power of 2 constant");
1791 assert(result->is_double_cpu(), "result must be register");
1792
1793 Register lreg = left->as_register_lo();
1794 Register dreg = result->as_register_lo();
1795
1796 if (right->is_constant()) {
1797 // Convert division by a power of two into some shifts and logical operations.
1798 Register treg1 = Z_R0_scratch;
1799 Register treg2 = Z_R1_scratch;
1800 jlong divisor = right->as_jlong();
1801 jlong log_divisor = log2i_exact(right->as_jlong());
1802
1803 if (divisor == min_jlong) {
1804 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1805 if (dreg == lreg) {
1806 NearLabel done;
1807 __ load_const_optimized(treg2, min_jlong);
1808 __ z_cgr(lreg, treg2);
1809 __ z_lghi(dreg, 0); // Preserves condition code.
1810 __ z_brne(done);
1811 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1812 __ bind(done);
1813 } else {
1814 assert_different_registers(dreg, lreg);
1815 NearLabel done;
1816 __ z_lghi(dreg, 0);
1817 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1818 __ z_lghi(dreg, 1);
1819 __ bind(done);
1820 }
1821 return;
1822 }
1823 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1824 if (divisor == 2) {
1825 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1826 } else {
1827 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1828 __ and_imm(treg2, divisor - 1, treg1, true);
1829 }
1830 if (code == lir_idiv) {
1831 __ z_agr(dreg, treg2);
1832 __ z_srag(dreg, dreg, log_divisor);
1833 } else {
1834 assert(code == lir_irem, "check");
1835 __ z_agr(treg2, dreg);
1836 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1837 __ z_sgr(dreg, treg2);
1838 }
1839 return;
1840 }
1841
1842 // Divisor is not a power of 2 constant.
1843 Register rreg = right->as_register_lo();
1844 Register treg = temp->as_register_lo();
1845 assert(right->is_double_cpu(), "right must be register");
1846 assert(lreg == Z_R11, "see ldivInOpr()");
1847 assert(rreg != lreg, "right register must not be same as left register");
1848 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1849 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1850
1851 Register R1 = lreg->predecessor();
1852 Register R2 = rreg;
1853 assert(code != lir_idiv || lreg==dreg, "see code below");
1854 if (code == lir_idiv) {
1855 __ z_lcgr(lreg, lreg);
1856 } else {
1857 __ clear_reg(dreg, true, false);
1858 }
1859 NearLabel done;
1860 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1861 if (code == lir_idiv) {
1862 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1863 }
1864 if (ImplicitDiv0Checks) {
1865 // No debug info because the idiv won't trap.
1866 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1867 // which is unnecessary, too.
1868 add_debug_info_for_div0(__ offset(), info);
1869 }
1870 __ z_dsgr(R1, R2);
1871 __ bind(done);
1872 return;
1873 }
1874
1875 // 32 bit integer case
1876
1877 assert(left->is_single_cpu(), "left must be register");
1878 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1879 assert(result->is_single_cpu(), "result must be register");
1880
1881 Register lreg = left->as_register();
1882 Register dreg = result->as_register();
1883
1884 if (right->is_constant()) {
1885 // Convert division by a power of two into some shifts and logical operations.
1886 Register treg1 = Z_R0_scratch;
1887 Register treg2 = Z_R1_scratch;
1888 jlong divisor = right->as_jint();
1889 jlong log_divisor = log2i_exact(right->as_jint());
1890 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1891 if (divisor == 2) {
1892 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1893 } else {
1894 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1895 __ and_imm(treg2, divisor - 1, treg1, true);
1896 }
1897 if (code == lir_idiv) {
1898 __ z_agr(dreg, treg2);
1899 __ z_srag(dreg, dreg, log_divisor);
1900 } else {
1901 assert(code == lir_irem, "check");
1902 __ z_agr(treg2, dreg);
1903 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1904 __ z_sgr(dreg, treg2);
1905 }
1906 return;
1907 }
1908
1909 // Divisor is not a power of 2 constant.
1910 Register rreg = right->as_register();
1911 Register treg = temp->as_register();
1912 assert(right->is_single_cpu(), "right must be register");
1913 assert(lreg == Z_R11, "left register must be rax,");
1914 assert(rreg != lreg, "right register must not be same as left register");
1915 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1916 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1917
1918 Register R1 = lreg->predecessor();
1919 Register R2 = rreg;
1920 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1921 if (ImplicitDiv0Checks) {
1922 // No debug info because the idiv won't trap.
1923 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1924 // which is unnecessary, too.
1925 add_debug_info_for_div0(__ offset(), info);
1926 }
1927 __ z_dsgfr(R1, R2);
1928 }
1929
1930 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1931 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1932 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1933
1934 // Exception object is not added to oop map by LinearScan
1935 // (LinearScan assumes that no oops are in fixed registers).
1936 info->add_register_oop(exceptionOop);
1937
1938 // Reuse the debug info from the safepoint poll for the throw op itself.
1939 __ get_PC(Z_EXC_PC);
1940 add_call_info(__ offset(), info); // for exception handler
1941 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1942 : StubId::c1_handle_exception_nofpu_id);
1943 emit_call_c(stub);
1944 }
1945
1946 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1947 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1948
1949 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1950 }
1951
1952 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1953 ciArrayKlass* default_type = op->expected_type();
1954 Register src = op->src()->as_register();
1955 Register dst = op->dst()->as_register();
1956 Register src_pos = op->src_pos()->as_register();
1957 Register dst_pos = op->dst_pos()->as_register();
1958 Register length = op->length()->as_register();
1959 Register tmp = op->tmp()->as_register();
1960
1961 CodeStub* stub = op->stub();
1962 int flags = op->flags();
1963 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
1964 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1965
1966 // If we don't know anything, just go through the generic arraycopy.
1967 if (default_type == nullptr) {
1968 address copyfunc_addr = StubRoutines::generic_arraycopy();
1969
1970 if (copyfunc_addr == nullptr) {
1971 // Take a slow path for generic arraycopy.
1972 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1973 __ bind(*stub->continuation());
1974 return;
1975 }
1976
1977 // Save outgoing arguments in callee saved registers (C convention) in case
1978 // a call to System.arraycopy is needed.
1979 Register callee_saved_src = Z_R10;
1980 Register callee_saved_src_pos = Z_R11;
1981 Register callee_saved_dst = Z_R12;
1982 Register callee_saved_dst_pos = Z_R13;
1983 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1984
1985 __ lgr_if_needed(callee_saved_src, src);
1986 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1987 __ lgr_if_needed(callee_saved_dst, dst);
1988 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1989 __ lgr_if_needed(callee_saved_length, length);
1990
1991 // C function requires 64 bit values.
1992 __ z_lgfr(src_pos, src_pos);
1993 __ z_lgfr(dst_pos, dst_pos);
1994 __ z_lgfr(length, length);
1995
1996 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
1997
1998 // The arguments are in the corresponding registers.
1999 assert(Z_ARG1 == src, "assumption");
2000 assert(Z_ARG2 == src_pos, "assumption");
2001 assert(Z_ARG3 == dst, "assumption");
2002 assert(Z_ARG4 == dst_pos, "assumption");
2003 assert(Z_ARG5 == length, "assumption");
2004 #ifndef PRODUCT
2005 if (PrintC1Statistics) {
2006 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
2007 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2008 }
2009 #endif
2010 emit_call_c(copyfunc_addr);
2011 CHECK_BAILOUT();
2012
2013 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2014
2015 __ z_lgr(tmp, Z_RET);
2016 __ z_xilf(tmp, -1);
2017
2018 // Restore values from callee saved registers so they are where the stub
2019 // expects them.
2020 __ lgr_if_needed(src, callee_saved_src);
2021 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2022 __ lgr_if_needed(dst, callee_saved_dst);
2023 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2024 __ lgr_if_needed(length, callee_saved_length);
2025
2026 __ z_sr(length, tmp);
2027 __ z_ar(src_pos, tmp);
2028 __ z_ar(dst_pos, tmp);
2029 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2030
2031 __ bind(*stub->continuation());
2032 return;
2033 }
2034
2035 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2036
2037 int elem_size = type2aelembytes(basic_type);
2038 int shift_amount;
2039
2040 switch (elem_size) {
2041 case 1 :
2042 shift_amount = 0;
2043 break;
2044 case 2 :
2045 shift_amount = 1;
2046 break;
2047 case 4 :
2048 shift_amount = 2;
2049 break;
2050 case 8 :
2051 shift_amount = 3;
2052 break;
2053 default:
2054 shift_amount = -1;
2055 ShouldNotReachHere();
2056 }
2057
2058 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2059 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2060
2061 // Length and pos's are all sign extended at this point on 64bit.
2062
2063 // test for null
2064 if (flags & LIR_OpArrayCopy::src_null_check) {
2065 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2066 }
2067 if (flags & LIR_OpArrayCopy::dst_null_check) {
2068 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2069 }
2070
2071 // Check if negative.
2072 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2073 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2074 }
2075 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2076 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2077 }
2078
2079 // If the compiler was not able to prove that exact type of the source or the destination
2080 // of the arraycopy is an array type, check at runtime if the source or the destination is
2081 // an instance type.
2082 if (flags & LIR_OpArrayCopy::type_check) {
2083 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2084
2085 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2086 __ load_klass(tmp, dst);
2087 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2088 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2089 }
2090
2091 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2092 __ load_klass(tmp, src);
2093 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2094 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2095 }
2096 }
2097
2098 if (flags & LIR_OpArrayCopy::src_range_check) {
2099 __ z_la(tmp, Address(src_pos, length));
2100 __ z_cl(tmp, src_length_addr);
2101 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2102 }
2103 if (flags & LIR_OpArrayCopy::dst_range_check) {
2104 __ z_la(tmp, Address(dst_pos, length));
2105 __ z_cl(tmp, dst_length_addr);
2106 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2107 }
2108
2109 if (flags & LIR_OpArrayCopy::length_positive_check) {
2110 __ z_ltr(length, length);
2111 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2112 }
2113
2114 // Stubs require 64 bit values.
2115 __ z_lgfr(src_pos, src_pos); // int -> long
2116 __ z_lgfr(dst_pos, dst_pos); // int -> long
2117 __ z_lgfr(length, length); // int -> long
2118
2119 if (flags & LIR_OpArrayCopy::type_check) {
2120 // We don't know the array types are compatible.
2121 if (basic_type != T_OBJECT) {
2122 // Simple test for basic type arrays.
2123 __ cmp_klasses_from_objects(src, dst, tmp, Z_R1_scratch);
2124 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2125 } else {
2126 // For object arrays, if src is a sub class of dst then we can
2127 // safely do the copy.
2128 NearLabel cont, slow;
2129 Register src_klass = Z_R1_scratch;
2130 Register dst_klass = Z_R10;
2131
2132 __ load_klass(src_klass, src);
2133 __ load_klass(dst_klass, dst);
2134
2135 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, nullptr);
2136
2137 store_parameter(src_klass, 0); // sub
2138 store_parameter(dst_klass, 1); // super
2139 emit_call_c(Runtime1::entry_for (StubId::c1_slow_subtype_check_id));
2140 CHECK_BAILOUT2(cont, slow);
2141 // Sets condition code 0 for match (2 otherwise).
2142 __ branch_optimized(Assembler::bcondEqual, cont);
2143
2144 __ bind(slow);
2145
2146 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2147 if (copyfunc_addr != nullptr) { // use stub if available
2148 // Src is not a sub class of dst so we have to do a
2149 // per-element check.
2150
2151 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2152 if ((flags & mask) != mask) {
2153 // Check that at least both of them object arrays.
2154 assert(flags & mask, "one of the two should be known to be an object array");
2155
2156 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2157 __ load_klass(tmp, src);
2158 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2159 __ load_klass(tmp, dst);
2160 }
2161 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2162 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2163 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2164 __ z_c(Z_R1_scratch, klass_lh_addr);
2165 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2166 }
2167
2168 // Save outgoing arguments in callee saved registers (C convention) in case
2169 // a call to System.arraycopy is needed.
2170 Register callee_saved_src = Z_R10;
2171 Register callee_saved_src_pos = Z_R11;
2172 Register callee_saved_dst = Z_R12;
2173 Register callee_saved_dst_pos = Z_R13;
2174 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2175
2176 __ lgr_if_needed(callee_saved_src, src);
2177 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2178 __ lgr_if_needed(callee_saved_dst, dst);
2179 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2180 __ lgr_if_needed(callee_saved_length, length);
2181
2182 __ z_llgfr(length, length); // Higher 32bits must be null.
2183
2184 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2185 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2186
2187 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2188 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2189 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2190 assert_different_registers(Z_ARG2, dst, length);
2191
2192 __ z_lgr(Z_ARG3, length);
2193 assert_different_registers(Z_ARG3, dst);
2194
2195 __ load_klass(Z_ARG5, dst);
2196 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2197 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2198 emit_call_c(copyfunc_addr);
2199 CHECK_BAILOUT2(cont, slow);
2200
2201 #ifndef PRODUCT
2202 if (PrintC1Statistics) {
2203 NearLabel failed;
2204 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2205 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2206 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2207 __ bind(failed);
2208 }
2209 #endif
2210
2211 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2212
2213 #ifndef PRODUCT
2214 if (PrintC1Statistics) {
2215 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2216 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2217 }
2218 #endif
2219
2220 __ z_lgr(tmp, Z_RET);
2221 __ z_xilf(tmp, -1);
2222
2223 // Restore previously spilled arguments
2224 __ lgr_if_needed(src, callee_saved_src);
2225 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2226 __ lgr_if_needed(dst, callee_saved_dst);
2227 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2228 __ lgr_if_needed(length, callee_saved_length);
2229
2230 __ z_sr(length, tmp);
2231 __ z_ar(src_pos, tmp);
2232 __ z_ar(dst_pos, tmp);
2233 }
2234
2235 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2236
2237 __ bind(cont);
2238 }
2239 }
2240
2241 #ifdef ASSERT
2242 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2243 // Sanity check the known type with the incoming class. For the
2244 // primitive case the types must match exactly with src.klass and
2245 // dst.klass each exactly matching the default type. For the
2246 // object array case, if no type check is needed then either the
2247 // dst type is exactly the expected type and the src type is a
2248 // subtype which we can't check or src is the same array as dst
2249 // but not necessarily exactly of type default_type.
2250 NearLabel known_ok, halt;
2251 metadata2reg(default_type->constant_encoding(), tmp);
2252 if (UseCompressedClassPointers) {
2253 __ encode_klass_not_null(tmp);
2254 }
2255
2256 if (basic_type != T_OBJECT) {
2257 __ cmp_klass(tmp, dst, Z_R1_scratch);
2258 __ branch_optimized(Assembler::bcondNotEqual, halt);
2259
2260 __ cmp_klass(tmp, src, Z_R1_scratch);
2261 __ branch_optimized(Assembler::bcondEqual, known_ok);
2262 } else {
2263 __ cmp_klass(tmp, dst, Z_R1_scratch);
2264 __ branch_optimized(Assembler::bcondEqual, known_ok);
2265 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2266 }
2267 __ bind(halt);
2268 __ stop("incorrect type information in arraycopy");
2269 __ bind(known_ok);
2270 }
2271 #endif
2272
2273 #ifndef PRODUCT
2274 if (PrintC1Statistics) {
2275 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2276 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2277 }
2278 #endif
2279
2280 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2281 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2282
2283 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2284 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2285 assert_different_registers(Z_ARG2, length);
2286 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2287 __ lgr_if_needed(Z_ARG3, length);
2288
2289 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2290 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2291 const char *name;
2292 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2293 __ call_VM_leaf(entry);
2294
2295 if (stub != nullptr) {
2296 __ bind(*stub->continuation());
2297 }
2298 }
2299
2300 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2301 if (dest->is_single_cpu()) {
2302 if (left->type() == T_OBJECT) {
2303 switch (code) {
2304 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2305 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2306 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2307 default: ShouldNotReachHere();
2308 }
2309 } else {
2310 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2311 Register masked_count = Z_R1_scratch;
2312 __ z_lr(masked_count, count->as_register());
2313 __ z_nill(masked_count, 31);
2314 switch (code) {
2315 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2316 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2317 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2318 default: ShouldNotReachHere();
2319 }
2320 }
2321 } else {
2322 switch (code) {
2323 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2324 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2325 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2326 default: ShouldNotReachHere();
2327 }
2328 }
2329 }
2330
2331 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2332 if (left->type() == T_OBJECT) {
2333 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2334 Register l = left->as_register();
2335 Register d = dest->as_register_lo();
2336 switch (code) {
2337 case lir_shl: __ z_sllg (d, l, count); break;
2338 case lir_shr: __ z_srag (d, l, count); break;
2339 case lir_ushr: __ z_srlg (d, l, count); break;
2340 default: ShouldNotReachHere();
2341 }
2342 return;
2343 }
2344 if (dest->is_single_cpu()) {
2345 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2346 count = count & 0x1F; // Java spec
2347 switch (code) {
2348 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2349 case lir_shr: __ z_sra (dest->as_register(), count); break;
2350 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2351 default: ShouldNotReachHere();
2352 }
2353 } else if (dest->is_double_cpu()) {
2354 count = count & 63; // Java spec
2355 Register l = left->as_pointer_register();
2356 Register d = dest->as_pointer_register();
2357 switch (code) {
2358 case lir_shl: __ z_sllg (d, l, count); break;
2359 case lir_shr: __ z_srag (d, l, count); break;
2360 case lir_ushr: __ z_srlg (d, l, count); break;
2361 default: ShouldNotReachHere();
2362 }
2363 } else {
2364 ShouldNotReachHere();
2365 }
2366 }
2367
2368 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2369 if (op->init_check()) {
2370 // Make sure klass is initialized & doesn't have finalizer.
2371 // init_state needs acquire, but S390 is TSO, and so we are already good.
2372 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2373 Register iklass = op->klass()->as_register();
2374 add_debug_info_for_null_check_here(op->stub()->info());
2375 if (Immediate::is_uimm12(state_offset)) {
2376 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2377 } else {
2378 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2379 }
2380 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2381 }
2382 __ allocate_object(op->obj()->as_register(),
2383 op->tmp1()->as_register(),
2384 op->tmp2()->as_register(),
2385 op->header_size(),
2386 op->object_size(),
2387 op->klass()->as_register(),
2388 *op->stub()->entry());
2389 __ bind(*op->stub()->continuation());
2390 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2391 }
2392
2393 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2394 Register len = op->len()->as_register();
2395 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2396
2397 if (UseSlowPath ||
2398 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2399 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2400 __ z_brul(*op->stub()->entry());
2401 } else {
2402 __ allocate_array(op->obj()->as_register(),
2403 op->len()->as_register(),
2404 op->tmp1()->as_register(),
2405 op->tmp2()->as_register(),
2406 arrayOopDesc::base_offset_in_bytes(op->type()),
2407 type2aelembytes(op->type()),
2408 op->klass()->as_register(),
2409 *op->stub()->entry(),
2410 op->zero_array());
2411 }
2412 __ bind(*op->stub()->continuation());
2413 }
2414
2415 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2416 Register recv, Register tmp1, Label* update_done) {
2417 uint i;
2418 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2419 Label next_test;
2420 // See if the receiver is receiver[n].
2421 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2422 __ z_cg(recv, receiver_addr);
2423 __ z_brne(next_test);
2424 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2425 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2426 __ branch_optimized(Assembler::bcondAlways, *update_done);
2427 __ bind(next_test);
2428 }
2429
2430 // Didn't find receiver; find next empty slot and fill it in.
2431 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2432 Label next_test;
2433 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2434 __ z_ltg(Z_R0_scratch, recv_addr);
2435 __ z_brne(next_test);
2436 __ z_stg(recv, recv_addr);
2437 __ load_const_optimized(tmp1, DataLayout::counter_increment);
2438 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2439 __ branch_optimized(Assembler::bcondAlways, *update_done);
2440 __ bind(next_test);
2441 }
2442 }
2443
2444 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2445 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2446 Unimplemented();
2447 }
2448
2449 void LIR_Assembler::store_parameter(Register r, int param_num) {
2450 assert(param_num >= 0, "invalid num");
2451 int offset_in_bytes = param_num * BytesPerWord;
2452 check_reserved_argument_area(offset_in_bytes);
2453 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2454 __ z_stg(r, offset_in_bytes, Z_SP);
2455 }
2456
2457 void LIR_Assembler::store_parameter(jint c, int param_num) {
2458 assert(param_num >= 0, "invalid num");
2459 int offset_in_bytes = param_num * BytesPerWord;
2460 check_reserved_argument_area(offset_in_bytes);
2461 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2462 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2463 }
2464
2465 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2466 // We always need a stub for the failure case.
2467 CodeStub* stub = op->stub();
2468 Register obj = op->object()->as_register();
2469 Register k_RInfo = op->tmp1()->as_register();
2470 Register klass_RInfo = op->tmp2()->as_register();
2471 Register dst = op->result_opr()->as_register();
2472 Register Rtmp1 = Z_R1_scratch;
2473 ciKlass* k = op->klass();
2474
2475 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2476
2477 // Check if it needs to be profiled.
2478 ciMethodData* md = nullptr;
2479 ciProfileData* data = nullptr;
2480
2481 if (op->should_profile()) {
2482 ciMethod* method = op->profiled_method();
2483 assert(method != nullptr, "Should have method");
2484 int bci = op->profiled_bci();
2485 md = method->method_data_or_null();
2486 assert(md != nullptr, "Sanity");
2487 data = md->bci_to_data(bci);
2488 assert(data != nullptr, "need data for type check");
2489 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2490 }
2491
2492 // Temp operands do not overlap with inputs, if this is their last
2493 // use (end of range is exclusive), so a register conflict is possible.
2494 if (obj == k_RInfo) {
2495 k_RInfo = dst;
2496 } else if (obj == klass_RInfo) {
2497 klass_RInfo = dst;
2498 }
2499 assert_different_registers(obj, k_RInfo, klass_RInfo);
2500
2501 if (op->should_profile()) {
2502 Register mdo = klass_RInfo;
2503 metadata2reg(md->constant_encoding(), mdo);
2504 NearLabel not_null;
2505 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2506 // Object is null; update MDO and exit.
2507 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2508 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2509 __ or2mem_8(data_addr, header_bits);
2510 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2511 __ bind(not_null);
2512
2513 NearLabel update_done;
2514 Register recv = k_RInfo;
2515 __ load_klass(recv, obj);
2516 type_profile_helper(mdo, md, data, recv, Rtmp1, &update_done);
2517 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2518 __ add2mem_64(counter_addr, DataLayout::counter_increment, Rtmp1);
2519 __ bind(update_done);
2520 } else {
2521 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2522 }
2523
2524 Label *failure_target = failure;
2525 Label *success_target = success;
2526
2527 // Patching may screw with our temporaries,
2528 // so let's do it before loading the class.
2529 if (k->is_loaded()) {
2530 metadata2reg(k->constant_encoding(), k_RInfo);
2531 } else {
2532 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2533 }
2534 assert(obj != k_RInfo, "must be different");
2535
2536 __ verify_oop(obj, FILE_AND_LINE);
2537
2538 // Get object class.
2539 // Not a safepoint as obj null check happens earlier.
2540 if (op->fast_check()) {
2541 if (UseCompressedClassPointers) {
2542 __ load_klass(klass_RInfo, obj);
2543 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2544 } else {
2545 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2546 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2547 }
2548 // Successful cast, fall through to profile or jump.
2549 } else {
2550 bool need_slow_path = !k->is_loaded() ||
2551 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2552 __ load_klass(klass_RInfo, obj);
2553 // Perform the fast part of the checking logic.
2554 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2555 (need_slow_path ? success_target : nullptr),
2556 failure_target, nullptr);
2557 if (need_slow_path) {
2558 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2559 address a = Runtime1::entry_for (StubId::c1_slow_subtype_check_id);
2560 store_parameter(klass_RInfo, 0); // sub
2561 store_parameter(k_RInfo, 1); // super
2562 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2563 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2564 // Fall through to success case.
2565 }
2566 }
2567
2568 __ branch_optimized(Assembler::bcondAlways, *success);
2569 }
2570
2571 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2572 LIR_Code code = op->code();
2573 if (code == lir_store_check) {
2574 Register value = op->object()->as_register();
2575 Register array = op->array()->as_register();
2576 Register k_RInfo = op->tmp1()->as_register();
2577 Register klass_RInfo = op->tmp2()->as_register();
2578 Register Rtmp1 = Z_R1_scratch;
2579
2580 CodeStub* stub = op->stub();
2581
2582 // Check if it needs to be profiled.
2583 ciMethodData* md = nullptr;
2584 ciProfileData* data = nullptr;
2585
2586 assert_different_registers(value, k_RInfo, klass_RInfo);
2587
2588 if (op->should_profile()) {
2589 ciMethod* method = op->profiled_method();
2590 assert(method != nullptr, "Should have method");
2591 int bci = op->profiled_bci();
2592 md = method->method_data_or_null();
2593 assert(md != nullptr, "Sanity");
2594 data = md->bci_to_data(bci);
2595 assert(data != nullptr, "need data for type check");
2596 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2597 }
2598 NearLabel done;
2599 Label *success_target = &done;
2600 Label *failure_target = stub->entry();
2601
2602 if (op->should_profile()) {
2603 Register mdo = klass_RInfo;
2604 metadata2reg(md->constant_encoding(), mdo);
2605 NearLabel not_null;
2606 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2607 // Object is null; update MDO and exit.
2608 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2609 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2610 __ or2mem_8(data_addr, header_bits);
2611 __ branch_optimized(Assembler::bcondAlways, done);
2612 __ bind(not_null);
2613
2614 NearLabel update_done;
2615 Register recv = k_RInfo;
2616 __ load_klass(recv, value);
2617 type_profile_helper(mdo, md, data, recv, Rtmp1, &update_done);
2618 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2619 __ add2mem_64(counter_addr, DataLayout::counter_increment, Rtmp1);
2620 __ bind(update_done);
2621 } else {
2622 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2623 }
2624
2625 add_debug_info_for_null_check_here(op->info_for_exception());
2626 __ load_klass(k_RInfo, array);
2627 __ load_klass(klass_RInfo, value);
2628
2629 // Get instance klass (it's already uncompressed).
2630 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2631 // Perform the fast part of the checking logic.
2632 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
2633 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2634 address a = Runtime1::entry_for (StubId::c1_slow_subtype_check_id);
2635 store_parameter(klass_RInfo, 0); // sub
2636 store_parameter(k_RInfo, 1); // super
2637 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2638 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2639 // Fall through to success case.
2640
2641 __ bind(done);
2642 } else {
2643 if (code == lir_checkcast) {
2644 Register obj = op->object()->as_register();
2645 Register dst = op->result_opr()->as_register();
2646 NearLabel success;
2647 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2648 __ bind(success);
2649 __ lgr_if_needed(dst, obj);
2650 } else {
2651 if (code == lir_instanceof) {
2652 Register obj = op->object()->as_register();
2653 Register dst = op->result_opr()->as_register();
2654 NearLabel success, failure, done;
2655 emit_typecheck_helper(op, &success, &failure, &failure);
2656 __ bind(failure);
2657 __ clear_reg(dst);
2658 __ branch_optimized(Assembler::bcondAlways, done);
2659 __ bind(success);
2660 __ load_const_optimized(dst, 1);
2661 __ bind(done);
2662 } else {
2663 ShouldNotReachHere();
2664 }
2665 }
2666 }
2667 }
2668
2669 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2670 Register addr = op->addr()->as_pointer_register();
2671 Register t1_cmp = Z_R1_scratch;
2672 if (op->code() == lir_cas_long) {
2673 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2674 Register new_value_lo = op->new_value()->as_register_lo();
2675 __ z_lgr(t1_cmp, cmp_value_lo);
2676 // Perform the compare and swap operation.
2677 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2678 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2679 Register cmp_value = op->cmp_value()->as_register();
2680 Register new_value = op->new_value()->as_register();
2681 if (op->code() == lir_cas_obj) {
2682 if (UseCompressedOops) {
2683 t1_cmp = op->tmp1()->as_register();
2684 Register t2_new = op->tmp2()->as_register();
2685 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2686 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2687 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2688 __ z_cs(t1_cmp, t2_new, 0, addr);
2689 } else {
2690 __ z_lgr(t1_cmp, cmp_value);
2691 __ z_csg(t1_cmp, new_value, 0, addr);
2692 }
2693 } else {
2694 __ z_lr(t1_cmp, cmp_value);
2695 __ z_cs(t1_cmp, new_value, 0, addr);
2696 }
2697 } else {
2698 ShouldNotReachHere(); // new lir_cas_??
2699 }
2700 }
2701
2702 void LIR_Assembler::breakpoint() {
2703 Unimplemented();
2704 // __ breakpoint_trap();
2705 }
2706
2707 void LIR_Assembler::push(LIR_Opr opr) {
2708 ShouldNotCallThis(); // unused
2709 }
2710
2711 void LIR_Assembler::pop(LIR_Opr opr) {
2712 ShouldNotCallThis(); // unused
2713 }
2714
2715 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2716 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2717 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2718 }
2719
2720 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2721 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2722 Register hdr = op->hdr_opr()->as_register();
2723 Register lock = op->lock_opr()->as_register();
2724 if (op->code() == lir_lock) {
2725 // Add debug info for NullPointerException only if one is possible.
2726 if (op->info() != nullptr) {
2727 add_debug_info_for_null_check_here(op->info());
2728 }
2729 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2730 // done
2731 } else if (op->code() == lir_unlock) {
2732 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2733 } else {
2734 ShouldNotReachHere();
2735 }
2736 __ bind(*op->stub()->continuation());
2737 }
2738
2739 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2740 Register obj = op->obj()->as_pointer_register();
2741 Register result = op->result_opr()->as_pointer_register();
2742
2743 CodeEmitInfo* info = op->info();
2744 if (info != nullptr) {
2745 add_debug_info_for_null_check_here(info);
2746 }
2747
2748 __ load_klass(result, obj);
2749 }
2750 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2751 ciMethod* method = op->profiled_method();
2752 int bci = op->profiled_bci();
2753 ciMethod* callee = op->profiled_callee();
2754
2755 // Update counter for all call types.
2756 ciMethodData* md = method->method_data_or_null();
2757 assert(md != nullptr, "Sanity");
2758 ciProfileData* data = md->bci_to_data(bci);
2759 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2760 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2761 Register mdo = op->mdo()->as_register();
2762 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2763 Register tmp1 = op->tmp1()->as_register_lo();
2764 metadata2reg(md->constant_encoding(), mdo);
2765
2766 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2767 // Perform additional virtual call profiling for invokevirtual and
2768 // invokeinterface bytecodes
2769 if (op->should_profile_receiver_type()) {
2770 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2771 Register recv = op->recv()->as_register();
2772 assert_different_registers(mdo, tmp1, recv);
2773 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2774 ciKlass* known_klass = op->known_holder();
2775 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2776 // We know the type that will be seen at this call site; we can
2777 // statically update the MethodData* rather than needing to do
2778 // dynamic tests on the receiver type.
2779
2780 // NOTE: we should probably put a lock around this search to
2781 // avoid collisions by concurrent compilations.
2782 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2783 uint i;
2784 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2785 ciKlass* receiver = vc_data->receiver(i);
2786 if (known_klass->equals(receiver)) {
2787 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2788 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2789 return;
2790 }
2791 }
2792
2793 // Receiver type not found in profile data. Select an empty slot.
2794
2795 // Note that this is less efficient than it should be because it
2796 // always does a write to the receiver part of the
2797 // VirtualCallData rather than just the first time.
2798 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2799 ciKlass* receiver = vc_data->receiver(i);
2800 if (receiver == nullptr) {
2801 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2802 metadata2reg(known_klass->constant_encoding(), tmp1);
2803 __ z_stg(tmp1, recv_addr);
2804 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2805 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2806 return;
2807 }
2808 }
2809 } else {
2810 __ load_klass(recv, recv);
2811 NearLabel update_done;
2812 type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2813 // Receiver did not match any saved receiver and there is no empty row for it.
2814 // Increment total counter to indicate polymorphic case.
2815 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2816 __ bind(update_done);
2817 }
2818 } else {
2819 // static call
2820 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2821 }
2822 }
2823
2824 void LIR_Assembler::align_backward_branch_target() {
2825 __ align(OptoLoopAlignment);
2826 }
2827
2828 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2829 // tmp must be unused
2830 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2831 assert(left->is_register(), "can only handle registers");
2832
2833 if (left->is_single_cpu()) {
2834 __ z_lcr(dest->as_register(), left->as_register());
2835 } else if (left->is_single_fpu()) {
2836 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2837 } else if (left->is_double_fpu()) {
2838 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2839 } else {
2840 assert(left->is_double_cpu(), "Must be a long");
2841 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2842 }
2843 }
2844
2845 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2846 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2847 assert(!tmp->is_valid(), "don't need temporary");
2848 emit_call_c(dest);
2849 CHECK_BAILOUT();
2850 if (info != nullptr) {
2851 add_call_info_here(info);
2852 }
2853 }
2854
2855 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2856 ShouldNotCallThis(); // not needed on ZARCH_64
2857 }
2858
2859 void LIR_Assembler::membar() {
2860 __ z_fence();
2861 }
2862
2863 void LIR_Assembler::membar_acquire() {
2864 __ z_acquire();
2865 }
2866
2867 void LIR_Assembler::membar_release() {
2868 __ z_release();
2869 }
2870
2871 void LIR_Assembler::membar_loadload() {
2872 __ z_acquire();
2873 }
2874
2875 void LIR_Assembler::membar_storestore() {
2876 __ z_release();
2877 }
2878
2879 void LIR_Assembler::membar_loadstore() {
2880 __ z_acquire();
2881 }
2882
2883 void LIR_Assembler::membar_storeload() {
2884 __ z_fence();
2885 }
2886
2887 void LIR_Assembler::on_spin_wait() {
2888 Unimplemented();
2889 }
2890
2891 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2892 assert(patch_code == lir_patch_none, "Patch code not supported");
2893 LIR_Address* addr = addr_opr->as_address_ptr();
2894 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2895 __ load_address(dest->as_pointer_register(), as_Address(addr));
2896 }
2897
2898 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2899 ShouldNotCallThis(); // unused
2900 }
2901
2902 #ifdef ASSERT
2903 // Emit run-time assertion.
2904 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2905 Unimplemented();
2906 }
2907 #endif
2908
2909 void LIR_Assembler::peephole(LIR_List*) {
2910 // Do nothing for now.
2911 }
2912
2913 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2914 assert(code == lir_xadd, "lir_xchg not supported");
2915 Address src_addr = as_Address(src->as_address_ptr());
2916 Register base = src_addr.base();
2917 intptr_t disp = src_addr.disp();
2918 if (src_addr.index()->is_valid()) {
2919 // LAA and LAAG do not support index register.
2920 __ load_address(Z_R1_scratch, src_addr);
2921 base = Z_R1_scratch;
2922 disp = 0;
2923 }
2924 if (data->type() == T_INT) {
2925 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2926 } else if (data->type() == T_LONG) {
2927 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2928 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2929 } else {
2930 ShouldNotReachHere();
2931 }
2932 }
2933
2934 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2935 Register obj = op->obj()->as_register();
2936 Register tmp1 = op->tmp()->as_pointer_register();
2937 Register tmp2 = Z_R1_scratch;
2938 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2939 ciKlass* exact_klass = op->exact_klass();
2940 intptr_t current_klass = op->current_klass();
2941 bool not_null = op->not_null();
2942 bool no_conflict = op->no_conflict();
2943
2944 Label update, next, none, null_seen, init_klass;
2945
2946 bool do_null = !not_null;
2947 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2948 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2949
2950 assert(do_null || do_update, "why are we here?");
2951 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2952
2953 __ verify_oop(obj, FILE_AND_LINE);
2954
2955 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2956 __ z_ltgr(tmp1, obj);
2957 }
2958 if (do_null) {
2959 __ z_brnz(update);
2960 if (!TypeEntries::was_null_seen(current_klass)) {
2961 __ z_lg(tmp1, mdo_addr);
2962 __ z_oill(tmp1, TypeEntries::null_seen);
2963 __ z_stg(tmp1, mdo_addr);
2964 }
2965 if (do_update) {
2966 __ z_bru(next);
2967 }
2968 } else {
2969 __ asm_assert(Assembler::bcondNotZero, "unexpected null obj", __LINE__);
2970 }
2971
2972 __ bind(update);
2973
2974 if (do_update) {
2975 #ifdef ASSERT
2976 if (exact_klass != nullptr) {
2977 __ load_klass(tmp1, tmp1);
2978 metadata2reg(exact_klass->constant_encoding(), tmp2);
2979 __ z_cgr(tmp1, tmp2);
2980 __ asm_assert(Assembler::bcondEqual, "exact klass and actual klass differ", __LINE__);
2981 }
2982 #endif
2983
2984 Label do_update;
2985 __ z_lg(tmp2, mdo_addr);
2986
2987 if (!no_conflict) {
2988 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2989 if (exact_klass != nullptr) {
2990 metadata2reg(exact_klass->constant_encoding(), tmp1);
2991 } else {
2992 __ load_klass(tmp1, tmp1);
2993 }
2994
2995 // Klass seen before: nothing to do (regardless of unknown bit).
2996 __ z_lgr(Z_R0_scratch, tmp2);
2997 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2998 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2999 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3000
3001 // Already unknown: Nothing to do anymore.
3002 __ z_tmll(tmp2, TypeEntries::type_unknown);
3003 __ z_brc(Assembler::bcondAllOne, next);
3004
3005 if (TypeEntries::is_type_none(current_klass)) {
3006 __ z_lgr(Z_R0_scratch, tmp2);
3007 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3008 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3009 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
3010 }
3011 } else {
3012 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3013 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3014
3015 // Already unknown: Nothing to do anymore.
3016 __ z_tmll(tmp2, TypeEntries::type_unknown);
3017 __ z_brc(Assembler::bcondAllOne, next);
3018 }
3019
3020 // Different than before. Cannot keep accurate profile.
3021 __ z_oill(tmp2, TypeEntries::type_unknown);
3022 __ z_bru(do_update);
3023 } else {
3024 // There's a single possible klass at this profile point.
3025 assert(exact_klass != nullptr, "should be");
3026 if (TypeEntries::is_type_none(current_klass)) {
3027 metadata2reg(exact_klass->constant_encoding(), tmp1);
3028 __ z_lgr(Z_R0_scratch, tmp2);
3029 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3030 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3031 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3032 #ifdef ASSERT
3033 {
3034 Label ok;
3035 __ z_lgr(Z_R0_scratch, tmp2);
3036 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3037 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3038 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
3039 __ stop("unexpected profiling mismatch");
3040 __ bind(ok);
3041 }
3042 #endif
3043
3044 } else {
3045 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3046 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3047
3048 // Already unknown: Nothing to do anymore.
3049 __ z_tmll(tmp2, TypeEntries::type_unknown);
3050 __ z_brc(Assembler::bcondAllOne, next);
3051 __ z_oill(tmp2, TypeEntries::type_unknown);
3052 __ z_bru(do_update);
3053 }
3054 }
3055
3056 __ bind(init_klass);
3057 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3058 __ z_ogr(tmp2, tmp1);
3059
3060 __ bind(do_update);
3061 __ z_stg(tmp2, mdo_addr);
3062
3063 __ bind(next);
3064 }
3065 }
3066
3067 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3068 assert(op->crc()->is_single_cpu(), "crc must be register");
3069 assert(op->val()->is_single_cpu(), "byte value must be register");
3070 assert(op->result_opr()->is_single_cpu(), "result must be register");
3071 Register crc = op->crc()->as_register();
3072 Register val = op->val()->as_register();
3073 Register res = op->result_opr()->as_register();
3074
3075 assert_different_registers(val, crc, res);
3076
3077 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3078 __ kernel_crc32_singleByteReg(crc, val, res, true);
3079 __ z_lgfr(res, crc);
3080 }
3081
3082 #undef __