1 /*
2 * Copyright (c) 2016, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_s390.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/safepointMechanism.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "utilities/macros.hpp"
43 #include "utilities/powerOfTwo.hpp"
44 #include "vmreg_s390.inline.hpp"
45
46 #define __ _masm->
47
48 #ifndef PRODUCT
49 #undef __
50 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
51 #endif
52
53 //------------------------------------------------------------
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 // Not used on ZARCH_64
57 ShouldNotCallThis();
58 return false;
59 }
60
61 LIR_Opr LIR_Assembler::receiverOpr() {
62 return FrameMap::Z_R2_oop_opr;
63 }
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::Z_R2_opr;
67 }
68
69 int LIR_Assembler::initial_frame_size_in_bytes() const {
70 return in_bytes(frame_map()->framesize_in_bytes());
71 }
72
73 // Inline cache check: done before the frame is built.
74 // The inline cached class is in Z_inline_cache(Z_R9).
75 // We fetch the class of the receiver and compare it with the cached class.
76 // If they do not match we jump to the slow case.
77 int LIR_Assembler::check_icache() {
78 return __ ic_check(CodeEntryAlignment);
79 }
80
81 void LIR_Assembler::clinit_barrier(ciMethod* method) {
82 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
83
84 Label L_skip_barrier;
85 Register klass = Z_R1_scratch;
86
87 metadata2reg(method->holder()->constant_encoding(), klass);
88 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
89
90 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
91 __ z_br(klass);
92
93 __ bind(L_skip_barrier);
94 }
95
96 void LIR_Assembler::osr_entry() {
97 // On-stack-replacement entry sequence (interpreter frame layout described in frame_s390.hpp):
98 //
99 // 1. Create a new compiled activation.
100 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
101 // at the osr_bci; it is not initialized.
102 // 3. Jump to the continuation address in compiled code to resume execution.
103
104 // OSR entry point
105 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
106 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
107 ValueStack* entry_state = osr_entry->end()->state();
108 int number_of_locks = entry_state->locks_size();
109
110 // Create a frame for the compiled activation.
111 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
112
113 // OSR buffer is
114 //
115 // locals[nlocals-1..0]
116 // monitors[number_of_locks-1..0]
117 //
118 // Locals is a direct copy of the interpreter frame so in the osr buffer
119 // the first slot in the local array is the last local from the interpreter
120 // and the last slot is local[0] (receiver) from the interpreter
121 //
122 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
123 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
124 // in the interpreter frame (the method lock if a sync method)
125
126 // Initialize monitors in the compiled activation.
127 // I0: pointer to osr buffer
128 //
129 // All other registers are dead at this point and the locals will be
130 // copied into place by code emitted in the IR.
131
132 Register OSR_buf = osrBufferPointer()->as_register();
133 {
134 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
135
136 const int locals_space = BytesPerWord * method() -> max_locals();
137 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
138 bool large_offset = !Immediate::is_simm20(monitor_offset + BytesPerWord) && number_of_locks > 0;
139
140 if (large_offset) {
141 // z_lg can only handle displacement upto 20bit signed binary integer
142 __ z_algfi(OSR_buf, locals_space);
143 monitor_offset -= locals_space;
144 }
145
146 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
147 // the OSR buffer using 2 word entries: first the lock and then
148 // the oop.
149 for (int i = 0; i < number_of_locks; i++) {
150 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
151 // Verify the interpreter's monitor has a non-null object.
152 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is null", __LINE__);
153 // Copy the lock field into the compiled activation.
154 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
155 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
156 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
157 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
158 }
159
160 if (large_offset) {
161 __ z_slgfi(OSR_buf, locals_space);
162 }
163 }
164 }
165
166 // --------------------------------------------------------------------------------------------
167
168 address LIR_Assembler::emit_call_c(address a) {
169 __ align_call_far_patchable(__ pc());
170 address call_addr = __ call_c_opt(a);
171 if (call_addr == nullptr) {
172 bailout("const section overflow");
173 }
174 return call_addr;
175 }
176
177 int LIR_Assembler::emit_exception_handler() {
178 // Generate code for exception handler.
179 address handler_base = __ start_a_stub(exception_handler_size());
180 if (handler_base == nullptr) {
181 // Not enough space left for the handler.
182 bailout("exception handler overflow");
183 return -1;
184 }
185
186 int offset = code_offset();
187
188 address a = Runtime1::entry_for (StubId::c1_handle_exception_from_callee_id);
189 address call_addr = emit_call_c(a);
190 CHECK_BAILOUT_(-1);
191 __ should_not_reach_here();
192 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
193 __ end_a_stub();
194
195 return offset;
196 }
197
198 // Emit the code to remove the frame from the stack in the exception
199 // unwind path.
200 int LIR_Assembler::emit_unwind_handler() {
201 #ifndef PRODUCT
202 if (CommentedAssembly) {
203 _masm->block_comment("Unwind handler");
204 }
205 #endif
206
207 int offset = code_offset();
208 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
209 Register Rtmp1 = Z_R11;
210 Register Rtmp2 = Z_R12;
211
212 // Fetch the exception from TLS and clear out exception related thread state.
213 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
214 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
215 __ z_lg(Z_EXC_OOP, exc_oop_addr);
216 __ clear_mem(exc_oop_addr, sizeof(oop));
217 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
218
219 __ bind(_unwind_handler_entry);
220 __ verify_not_null_oop(Z_EXC_OOP);
221 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
222 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
223 }
224
225 // Perform needed unlocking.
226 MonitorExitStub* stub = nullptr;
227 if (method()->is_synchronized()) {
228 // StubId::c1_monitorexit_id expects lock address in Z_R1_scratch.
229 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
230 monitor_address(0, lock);
231 stub = new MonitorExitStub(lock, 0);
232 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
233 __ bind(*stub->continuation());
234 }
235
236 if (compilation()->env()->dtrace_method_probes()) {
237 ShouldNotReachHere(); // Not supported.
238 #if 0
239 __ mov(rdi, r15_thread);
240 __ mov_metadata(rsi, method()->constant_encoding());
241 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
242 #endif
243 }
244
245 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
246 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
247 }
248
249 // Remove the activation and dispatch to the unwind handler.
250 __ pop_frame();
251 __ z_lg(Z_EXC_PC, _z_common_abi(return_pc), Z_SP);
252
253 // Z_EXC_OOP: exception oop
254 // Z_EXC_PC: exception pc
255
256 // Dispatch to the unwind logic.
257 __ load_const_optimized(Z_R5, Runtime1::entry_for (StubId::c1_unwind_exception_id));
258 __ z_br(Z_R5);
259
260 // Emit the slow path assembly.
261 if (stub != nullptr) {
262 stub->emit_code(this);
263 }
264
265 return offset;
266 }
267
268 int LIR_Assembler::emit_deopt_handler() {
269 // Generate code for exception handler.
270 address handler_base = __ start_a_stub(deopt_handler_size());
271 if (handler_base == nullptr) {
272 // Not enough space left for the handler.
273 bailout("deopt handler overflow");
274 return -1;
275 }
276
277 int offset = code_offset();
278
279 Label start;
280 __ bind(start);
281
282 // Size must be constant (see HandlerImpl::emit_deopt_handler).
283 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
284 __ call(Z_R1_scratch);
285
286 int entry_offset = __ offset();
287
288 __ z_bru(start);
289
290 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
291 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
292 "out of bounds read in post-call NOP check");
293 __ end_a_stub();
294
295 return entry_offset;
296 }
297
298 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
299 if (o == nullptr) {
300 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
301 } else {
302 AddressLiteral a = __ allocate_oop_address(o);
303 bool success = __ load_oop_from_toc(reg, a, reg);
304 if (!success) {
305 bailout("const section overflow");
306 }
307 }
308 }
309
310 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
311 // Allocate a new index in table to hold the object once it's been patched.
312 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
313 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
314
315 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
316 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
317 // The null will be dynamically patched later so the sequence to
318 // load the address literal must not be optimized.
319 __ load_const(reg, addrlit);
320
321 patching_epilog(patch, lir_patch_normal, reg, info);
322 }
323
324 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
325 bool success = __ set_metadata_constant(md, reg);
326 if (!success) {
327 bailout("const section overflow");
328 return;
329 }
330 }
331
332 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
333 // Allocate a new index in table to hold the klass once it's been patched.
334 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
335 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
336 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
337 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
338 // The null will be dynamically patched later so the sequence to
339 // load the address literal must not be optimized.
340 __ load_const(reg, addrlit);
341
342 patching_epilog(patch, lir_patch_normal, reg, info);
343 }
344
345 void LIR_Assembler::emit_op3(LIR_Op3* op) {
346 switch (op->code()) {
347 case lir_idiv:
348 case lir_irem:
349 arithmetic_idiv(op->code(),
350 op->in_opr1(),
351 op->in_opr2(),
352 op->in_opr3(),
353 op->result_opr(),
354 op->info());
355 break;
356 case lir_fmad: {
357 const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
358 opr2 = op->in_opr2()->as_double_reg(),
359 opr3 = op->in_opr3()->as_double_reg(),
360 res = op->result_opr()->as_double_reg();
361 __ z_madbr(opr3, opr1, opr2);
362 if (res != opr3) { __ z_ldr(res, opr3); }
363 } break;
364 case lir_fmaf: {
365 const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
366 opr2 = op->in_opr2()->as_float_reg(),
367 opr3 = op->in_opr3()->as_float_reg(),
368 res = op->result_opr()->as_float_reg();
369 __ z_maebr(opr3, opr1, opr2);
370 if (res != opr3) { __ z_ler(res, opr3); }
371 } break;
372 default: ShouldNotReachHere(); break;
373 }
374 }
375
376
377 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
378 #ifdef ASSERT
379 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
380 if (op->block() != nullptr) { _branch_target_blocks.append(op->block()); }
381 if (op->ublock() != nullptr) { _branch_target_blocks.append(op->ublock()); }
382 #endif
383
384 if (op->cond() == lir_cond_always) {
385 if (op->info() != nullptr) { add_debug_info_for_branch(op->info()); }
386 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
387 } else {
388 Assembler::branch_condition acond = Assembler::bcondZero;
389 if (op->code() == lir_cond_float_branch) {
390 assert(op->ublock() != nullptr, "must have unordered successor");
391 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
392 }
393 switch (op->cond()) {
394 case lir_cond_equal: acond = Assembler::bcondEqual; break;
395 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
396 case lir_cond_less: acond = Assembler::bcondLow; break;
397 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
398 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
399 case lir_cond_greater: acond = Assembler::bcondHigh; break;
400 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
401 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
402 default: ShouldNotReachHere();
403 }
404 __ branch_optimized(acond,*(op->label()));
405 }
406 }
407
408
409 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
410 LIR_Opr src = op->in_opr();
411 LIR_Opr dest = op->result_opr();
412
413 switch (op->bytecode()) {
414 case Bytecodes::_i2l:
415 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
416 break;
417
418 case Bytecodes::_l2i:
419 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
420 break;
421
422 case Bytecodes::_i2b:
423 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
424 break;
425
426 case Bytecodes::_i2c:
427 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
428 break;
429
430 case Bytecodes::_i2s:
431 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
432 break;
433
434 case Bytecodes::_f2d:
435 assert(dest->is_double_fpu(), "check");
436 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
437 break;
438
439 case Bytecodes::_d2f:
440 assert(dest->is_single_fpu(), "check");
441 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
442 break;
443
444 case Bytecodes::_i2f:
445 __ z_cefbr(dest->as_float_reg(), src->as_register());
446 break;
447
448 case Bytecodes::_i2d:
449 __ z_cdfbr(dest->as_double_reg(), src->as_register());
450 break;
451
452 case Bytecodes::_l2f:
453 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
454 break;
455 case Bytecodes::_l2d:
456 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
457 break;
458
459 case Bytecodes::_f2i:
460 case Bytecodes::_f2l: {
461 Label done;
462 FloatRegister Rsrc = src->as_float_reg();
463 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
464 __ clear_reg(Rdst, true, false);
465 __ z_cebr(Rsrc, Rsrc);
466 __ z_brno(done); // NaN -> 0
467 if (op->bytecode() == Bytecodes::_f2i) {
468 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
469 } else { // op->bytecode() == Bytecodes::_f2l
470 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
471 }
472 __ bind(done);
473 }
474 break;
475
476 case Bytecodes::_d2i:
477 case Bytecodes::_d2l: {
478 Label done;
479 FloatRegister Rsrc = src->as_double_reg();
480 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
481 __ clear_reg(Rdst, true, false); // Don't set CC.
482 __ z_cdbr(Rsrc, Rsrc);
483 __ z_brno(done); // NaN -> 0
484 if (op->bytecode() == Bytecodes::_d2i) {
485 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
486 } else { // Bytecodes::_d2l
487 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
488 }
489 __ bind(done);
490 }
491 break;
492
493 default: ShouldNotReachHere();
494 }
495 }
496
497 void LIR_Assembler::align_call(LIR_Code code) {
498 // End of call instruction must be 4 byte aligned.
499 int offset = __ offset();
500 switch (code) {
501 case lir_icvirtual_call:
502 offset += MacroAssembler::load_const_from_toc_size();
503 // no break
504 case lir_static_call:
505 case lir_optvirtual_call:
506 case lir_dynamic_call:
507 offset += NativeCall::call_far_pcrelative_displacement_offset;
508 break;
509 default: ShouldNotReachHere();
510 }
511 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
512 __ nop();
513 }
514 }
515
516 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
517 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
518 "must be aligned (offset=%d)", __ offset());
519 assert(rtype == relocInfo::none ||
520 rtype == relocInfo::opt_virtual_call_type ||
521 rtype == relocInfo::static_call_type, "unexpected rtype");
522 // Prepend each BRASL with a nop.
523 __ relocate(rtype);
524 __ z_nop();
525 __ z_brasl(Z_R14, op->addr());
526 add_call_info(code_offset(), op->info());
527 __ post_call_nop();
528 }
529
530 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
531 address virtual_call_oop_addr = nullptr;
532 AddressLiteral empty_ic((address) Universe::non_oop_word());
533 virtual_call_oop_addr = __ pc();
534 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
535 if (!success) {
536 bailout("const section overflow");
537 return;
538 }
539
540 // CALL to fixup routine. Fixup routine uses ScopeDesc info
541 // to determine who we intended to call.
542 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
543 call(op, relocInfo::none); // call will emit a post call nop, see above method.
544 }
545
546 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
547 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
548 }
549
550 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
551 assert(src->is_constant(), "should not call otherwise");
552 assert(dest->is_stack(), "should not call otherwise");
553 LIR_Const* c = src->as_constant_ptr();
554
555 unsigned int lmem = 0;
556 unsigned int lcon = 0;
557 int64_t cbits = 0;
558 Address dest_addr;
559 switch (c->type()) {
560 case T_INT: // fall through
561 case T_FLOAT:
562 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
563 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
564 break;
565
566 case T_ADDRESS:
567 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
568 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
569 break;
570
571 case T_OBJECT:
572 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
573 if (c->as_jobject() == nullptr) {
574 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
575 } else {
576 jobject2reg(c->as_jobject(), Z_R1_scratch);
577 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
578 }
579 return;
580
581 case T_LONG: // fall through
582 case T_DOUBLE:
583 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
584 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
585 break;
586
587 default:
588 ShouldNotReachHere();
589 }
590
591 __ store_const(dest_addr, cbits, lmem, lcon);
592 }
593
594 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
595 assert(src->is_constant(), "should not call otherwise");
596 assert(dest->is_address(), "should not call otherwise");
597
598 LIR_Const* c = src->as_constant_ptr();
599 Address addr = as_Address(dest->as_address_ptr());
600
601 int store_offset = -1;
602
603 if (dest->as_address_ptr()->index()->is_valid()) {
604 switch (type) {
605 case T_INT: // fall through
606 case T_FLOAT:
607 __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
608 store_offset = __ offset();
609 if (Immediate::is_uimm12(addr.disp())) {
610 __ z_st(Z_R0_scratch, addr);
611 } else {
612 __ z_sty(Z_R0_scratch, addr);
613 }
614 break;
615
616 case T_ADDRESS:
617 __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
618 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
619 break;
620
621 case T_OBJECT: // fall through
622 case T_ARRAY:
623 if (c->as_jobject() == nullptr) {
624 if (UseCompressedOops && !wide) {
625 __ clear_reg(Z_R1_scratch, false);
626 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
627 } else {
628 __ clear_reg(Z_R1_scratch, true);
629 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
630 }
631 } else {
632 jobject2reg(c->as_jobject(), Z_R1_scratch);
633 if (UseCompressedOops && !wide) {
634 __ encode_heap_oop(Z_R1_scratch);
635 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
636 } else {
637 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
638 }
639 }
640 assert(store_offset >= 0, "check");
641 break;
642
643 case T_LONG: // fall through
644 case T_DOUBLE:
645 __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
646 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
647 break;
648
649 case T_BOOLEAN: // fall through
650 case T_BYTE:
651 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
652 store_offset = __ offset();
653 if (Immediate::is_uimm12(addr.disp())) {
654 __ z_stc(Z_R0_scratch, addr);
655 } else {
656 __ z_stcy(Z_R0_scratch, addr);
657 }
658 break;
659
660 case T_CHAR: // fall through
661 case T_SHORT:
662 __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
663 store_offset = __ offset();
664 if (Immediate::is_uimm12(addr.disp())) {
665 __ z_sth(Z_R0_scratch, addr);
666 } else {
667 __ z_sthy(Z_R0_scratch, addr);
668 }
669 break;
670
671 default:
672 ShouldNotReachHere();
673 }
674
675 } else { // no index
676
677 unsigned int lmem = 0;
678 unsigned int lcon = 0;
679 int64_t cbits = 0;
680
681 switch (type) {
682 case T_INT: // fall through
683 case T_FLOAT:
684 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
685 break;
686
687 case T_ADDRESS:
688 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
689 break;
690
691 case T_OBJECT: // fall through
692 case T_ARRAY:
693 if (c->as_jobject() == nullptr) {
694 if (UseCompressedOops && !wide) {
695 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
696 } else {
697 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
698 }
699 } else {
700 jobject2reg(c->as_jobject(), Z_R1_scratch);
701 if (UseCompressedOops && !wide) {
702 __ encode_heap_oop(Z_R1_scratch);
703 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
704 } else {
705 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
706 }
707 }
708 assert(store_offset >= 0, "check");
709 break;
710
711 case T_LONG: // fall through
712 case T_DOUBLE:
713 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
714 break;
715
716 case T_BOOLEAN: // fall through
717 case T_BYTE:
718 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
719 break;
720
721 case T_CHAR: // fall through
722 case T_SHORT:
723 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
724 break;
725
726 default:
727 ShouldNotReachHere();
728 }
729
730 if (store_offset == -1) {
731 store_offset = __ store_const(addr, cbits, lmem, lcon);
732 assert(store_offset >= 0, "check");
733 }
734 }
735
736 if (info != nullptr) {
737 add_debug_info_for_null_check(store_offset, info);
738 }
739 }
740
741 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
742 assert(src->is_constant(), "should not call otherwise");
743 assert(dest->is_register(), "should not call otherwise");
744 LIR_Const* c = src->as_constant_ptr();
745
746 switch (c->type()) {
747 case T_INT: {
748 assert(patch_code == lir_patch_none, "no patching handled here");
749 __ load_const_optimized(dest->as_register(), c->as_jint());
750 break;
751 }
752
753 case T_ADDRESS: {
754 assert(patch_code == lir_patch_none, "no patching handled here");
755 __ load_const_optimized(dest->as_register(), c->as_jint());
756 break;
757 }
758
759 case T_LONG: {
760 assert(patch_code == lir_patch_none, "no patching handled here");
761 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
762 break;
763 }
764
765 case T_OBJECT: {
766 if (patch_code != lir_patch_none) {
767 jobject2reg_with_patching(dest->as_register(), info);
768 } else {
769 jobject2reg(c->as_jobject(), dest->as_register());
770 }
771 break;
772 }
773
774 case T_METADATA: {
775 if (patch_code != lir_patch_none) {
776 klass2reg_with_patching(dest->as_register(), info);
777 } else {
778 metadata2reg(c->as_metadata(), dest->as_register());
779 }
780 break;
781 }
782
783 case T_FLOAT: {
784 Register toc_reg = Z_R1_scratch;
785 __ load_toc(toc_reg);
786 address const_addr = __ float_constant(c->as_jfloat());
787 if (const_addr == nullptr) {
788 bailout("const section overflow");
789 break;
790 }
791 int displ = const_addr - _masm->code()->consts()->start();
792 if (dest->is_single_fpu()) {
793 __ z_ley(dest->as_float_reg(), displ, toc_reg);
794 } else {
795 assert(dest->is_single_cpu(), "Must be a cpu register.");
796 __ z_ly(dest->as_register(), displ, toc_reg);
797 }
798 }
799 break;
800
801 case T_DOUBLE: {
802 Register toc_reg = Z_R1_scratch;
803 __ load_toc(toc_reg);
804 address const_addr = __ double_constant(c->as_jdouble());
805 if (const_addr == nullptr) {
806 bailout("const section overflow");
807 break;
808 }
809 int displ = const_addr - _masm->code()->consts()->start();
810 if (dest->is_double_fpu()) {
811 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
812 } else {
813 assert(dest->is_double_cpu(), "Must be a long register.");
814 __ z_lg(dest->as_register_lo(), displ, toc_reg);
815 }
816 }
817 break;
818
819 default:
820 ShouldNotReachHere();
821 }
822 }
823
824 Address LIR_Assembler::as_Address(LIR_Address* addr) {
825 if (addr->base()->is_illegal()) {
826 Unimplemented();
827 }
828
829 Register base = addr->base()->as_pointer_register();
830
831 if (addr->index()->is_illegal()) {
832 return Address(base, addr->disp());
833 } else if (addr->index()->is_cpu_register()) {
834 Register index = addr->index()->as_pointer_register();
835 return Address(base, index, addr->disp());
836 } else if (addr->index()->is_constant()) {
837 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
838 return Address(base, addr_offset);
839 } else {
840 ShouldNotReachHere();
841 return Address();
842 }
843 }
844
845 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
846 switch (type) {
847 case T_INT:
848 case T_FLOAT: {
849 Register tmp = Z_R1_scratch;
850 Address from = frame_map()->address_for_slot(src->single_stack_ix());
851 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
852 __ mem2reg_opt(tmp, from, false);
853 __ reg2mem_opt(tmp, to, false);
854 break;
855 }
856 case T_ADDRESS:
857 case T_OBJECT: {
858 Register tmp = Z_R1_scratch;
859 Address from = frame_map()->address_for_slot(src->single_stack_ix());
860 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
861 __ mem2reg_opt(tmp, from, true);
862 __ reg2mem_opt(tmp, to, true);
863 break;
864 }
865 case T_LONG:
866 case T_DOUBLE: {
867 Register tmp = Z_R1_scratch;
868 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
869 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
870 __ mem2reg_opt(tmp, from, true);
871 __ reg2mem_opt(tmp, to, true);
872 break;
873 }
874
875 default:
876 ShouldNotReachHere();
877 }
878 }
879
880 // 4-byte accesses only! Don't use it to access 8 bytes!
881 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
882 ShouldNotCallThis();
883 return Address(); // unused
884 }
885
886 // 4-byte accesses only! Don't use it to access 8 bytes!
887 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
888 ShouldNotCallThis();
889 return Address(); // unused
890 }
891
892 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
893 CodeEmitInfo* info, bool wide) {
894
895 assert(type != T_METADATA, "load of metadata ptr not supported");
896 LIR_Address* addr = src_opr->as_address_ptr();
897 LIR_Opr to_reg = dest;
898
899 Register src = addr->base()->as_pointer_register();
900 Register disp_reg = Z_R0;
901 int disp_value = addr->disp();
902 bool needs_patching = (patch_code != lir_patch_none);
903
904 if (addr->base()->type() == T_OBJECT) {
905 __ verify_oop(src, FILE_AND_LINE);
906 }
907
908 PatchingStub* patch = nullptr;
909 if (needs_patching) {
910 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
911 assert(!to_reg->is_double_cpu() ||
912 patch_code == lir_patch_none ||
913 patch_code == lir_patch_normal, "patching doesn't match register");
914 }
915
916 if (addr->index()->is_illegal()) {
917 if (!Immediate::is_simm20(disp_value)) {
918 if (needs_patching) {
919 __ load_const(Z_R1_scratch, (intptr_t)0);
920 } else {
921 __ load_const_optimized(Z_R1_scratch, disp_value);
922 }
923 disp_reg = Z_R1_scratch;
924 disp_value = 0;
925 }
926 } else {
927 if (!Immediate::is_simm20(disp_value)) {
928 __ load_const_optimized(Z_R1_scratch, disp_value);
929 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
930 disp_reg = Z_R1_scratch;
931 disp_value = 0;
932 }
933 disp_reg = addr->index()->as_pointer_register();
934 }
935
936 // Remember the offset of the load. The patching_epilog must be done
937 // before the call to add_debug_info, otherwise the PcDescs don't get
938 // entered in increasing order.
939 int offset = code_offset();
940
941 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
942
943 bool short_disp = Immediate::is_uimm12(disp_value);
944
945 switch (type) {
946 case T_BOOLEAN: // fall through
947 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
948 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
949 case T_SHORT :
950 if (short_disp) {
951 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
952 } else {
953 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
954 }
955 break;
956 case T_INT :
957 if (short_disp) {
958 __ z_l(dest->as_register(), disp_value, disp_reg, src);
959 } else {
960 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
961 }
962 break;
963 case T_ADDRESS:
964 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
965 break;
966 case T_ARRAY : // fall through
967 case T_OBJECT:
968 {
969 if (UseCompressedOops && !wide) {
970 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
971 __ oop_decoder(dest->as_register(), dest->as_register(), true);
972 } else {
973 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
974 }
975 __ verify_oop(dest->as_register(), FILE_AND_LINE);
976 break;
977 }
978 case T_FLOAT:
979 if (short_disp) {
980 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
981 } else {
982 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
983 }
984 break;
985 case T_DOUBLE:
986 if (short_disp) {
987 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
988 } else {
989 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
990 }
991 break;
992 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
993 default : ShouldNotReachHere();
994 }
995
996 if (patch != nullptr) {
997 patching_epilog(patch, patch_code, src, info);
998 }
999 if (info != nullptr) add_debug_info_for_null_check(offset, info);
1000 }
1001
1002 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1003 assert(src->is_stack(), "should not call otherwise");
1004 assert(dest->is_register(), "should not call otherwise");
1005
1006 if (dest->is_single_cpu()) {
1007 if (is_reference_type(type)) {
1008 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1009 __ verify_oop(dest->as_register(), FILE_AND_LINE);
1010 } else if (type == T_METADATA || type == T_ADDRESS) {
1011 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1012 } else {
1013 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
1014 }
1015 } else if (dest->is_double_cpu()) {
1016 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
1017 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
1018 } else if (dest->is_single_fpu()) {
1019 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1020 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
1021 } else if (dest->is_double_fpu()) {
1022 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1023 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
1024 } else {
1025 ShouldNotReachHere();
1026 }
1027 }
1028
1029 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1030 assert(src->is_register(), "should not call otherwise");
1031 assert(dest->is_stack(), "should not call otherwise");
1032
1033 if (src->is_single_cpu()) {
1034 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1035 if (is_reference_type(type)) {
1036 __ verify_oop(src->as_register(), FILE_AND_LINE);
1037 __ reg2mem_opt(src->as_register(), dst, true);
1038 } else if (type == T_METADATA || type == T_ADDRESS) {
1039 __ reg2mem_opt(src->as_register(), dst, true);
1040 } else {
1041 __ reg2mem_opt(src->as_register(), dst, false);
1042 }
1043 } else if (src->is_double_cpu()) {
1044 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1045 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1046 } else if (src->is_single_fpu()) {
1047 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1048 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1049 } else if (src->is_double_fpu()) {
1050 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1051 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1052 } else {
1053 ShouldNotReachHere();
1054 }
1055 }
1056
1057 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1058 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1059 if (from_reg->is_double_fpu()) {
1060 // double to double moves
1061 assert(to_reg->is_double_fpu(), "should match");
1062 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1063 } else {
1064 // float to float moves
1065 assert(to_reg->is_single_fpu(), "should match");
1066 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1067 }
1068 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1069 if (from_reg->is_double_cpu()) {
1070 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1071 } else if (to_reg->is_double_cpu()) {
1072 // int to int moves
1073 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1074 } else {
1075 // int to int moves
1076 __ z_lgr(to_reg->as_register(), from_reg->as_register());
1077 }
1078 } else {
1079 ShouldNotReachHere();
1080 }
1081 if (is_reference_type(to_reg->type())) {
1082 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1083 }
1084 }
1085
1086 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1087 LIR_PatchCode patch_code, CodeEmitInfo* info,
1088 bool wide) {
1089 assert(type != T_METADATA, "store of metadata ptr not supported");
1090 LIR_Address* addr = dest_opr->as_address_ptr();
1091
1092 Register dest = addr->base()->as_pointer_register();
1093 Register disp_reg = Z_R0;
1094 int disp_value = addr->disp();
1095 bool needs_patching = (patch_code != lir_patch_none);
1096
1097 if (addr->base()->is_oop_register()) {
1098 __ verify_oop(dest, FILE_AND_LINE);
1099 }
1100
1101 PatchingStub* patch = nullptr;
1102 if (needs_patching) {
1103 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1104 assert(!from->is_double_cpu() ||
1105 patch_code == lir_patch_none ||
1106 patch_code == lir_patch_normal, "patching doesn't match register");
1107 }
1108
1109 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1110 if (addr->index()->is_illegal()) {
1111 if (!Immediate::is_simm20(disp_value)) {
1112 if (needs_patching) {
1113 __ load_const(Z_R1_scratch, (intptr_t)0);
1114 } else {
1115 __ load_const_optimized(Z_R1_scratch, disp_value);
1116 }
1117 disp_reg = Z_R1_scratch;
1118 disp_value = 0;
1119 }
1120 } else {
1121 if (!Immediate::is_simm20(disp_value)) {
1122 __ load_const_optimized(Z_R1_scratch, disp_value);
1123 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1124 disp_reg = Z_R1_scratch;
1125 disp_value = 0;
1126 }
1127 disp_reg = addr->index()->as_pointer_register();
1128 }
1129
1130 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1131
1132 if (is_reference_type(type)) {
1133 __ verify_oop(from->as_register(), FILE_AND_LINE);
1134 }
1135
1136 bool short_disp = Immediate::is_uimm12(disp_value);
1137
1138 // Remember the offset of the store. The patching_epilog must be done
1139 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1140 // entered in increasing order.
1141 int offset = code_offset();
1142 switch (type) {
1143 case T_BOOLEAN: // fall through
1144 case T_BYTE :
1145 if (short_disp) {
1146 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1147 } else {
1148 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1149 }
1150 break;
1151 case T_CHAR : // fall through
1152 case T_SHORT :
1153 if (short_disp) {
1154 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1155 } else {
1156 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1157 }
1158 break;
1159 case T_INT :
1160 if (short_disp) {
1161 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1162 } else {
1163 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1164 }
1165 break;
1166 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1167 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1168 break;
1169 case T_ARRAY : // fall through
1170 case T_OBJECT:
1171 {
1172 if (UseCompressedOops && !wide) {
1173 Register compressed_src = Z_R14;
1174 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1175 offset = code_offset();
1176 if (short_disp) {
1177 __ z_st(compressed_src, disp_value, disp_reg, dest);
1178 } else {
1179 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1180 }
1181 } else {
1182 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1183 }
1184 break;
1185 }
1186 case T_FLOAT :
1187 if (short_disp) {
1188 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1189 } else {
1190 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1191 }
1192 break;
1193 case T_DOUBLE:
1194 if (short_disp) {
1195 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1196 } else {
1197 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1198 }
1199 break;
1200 default: ShouldNotReachHere();
1201 }
1202
1203 if (patch != nullptr) {
1204 patching_epilog(patch, patch_code, dest, info);
1205 }
1206
1207 if (info != nullptr) add_debug_info_for_null_check(offset, info);
1208 }
1209
1210
1211 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1212 assert(result->is_illegal() ||
1213 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1214 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1215 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1216 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1217
1218 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1219
1220 // Pop the frame before the safepoint code.
1221 __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1222
1223 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1224 __ reserved_stack_check(Z_R14);
1225 }
1226
1227 // We need to mark the code position where the load from the safepoint
1228 // polling page was emitted as relocInfo::poll_return_type here.
1229 __ relocate(relocInfo::poll_return_type);
1230 __ load_from_polling_page(Z_R1_scratch);
1231
1232 __ z_br(Z_R14); // Return to caller.
1233 }
1234
1235 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1236 const Register poll_addr = tmp->as_register_lo();
1237 __ z_lg(poll_addr, Address(Z_thread, JavaThread::polling_page_offset()));
1238 guarantee(info != nullptr, "Shouldn't be null");
1239 add_debug_info_for_branch(info);
1240 int offset = __ offset();
1241 __ relocate(relocInfo::poll_type);
1242 __ load_from_polling_page(poll_addr);
1243 return offset;
1244 }
1245
1246 void LIR_Assembler::emit_static_call_stub() {
1247
1248 // Stub is fixed up when the corresponding call is converted from calling
1249 // compiled code to calling interpreted code.
1250
1251 address call_pc = __ pc();
1252 address stub = __ start_a_stub(call_stub_size());
1253 if (stub == nullptr) {
1254 bailout("static call stub overflow");
1255 return;
1256 }
1257
1258 int start = __ offset();
1259
1260 __ relocate(static_stub_Relocation::spec(call_pc));
1261
1262 // See also Matcher::interpreter_method_reg().
1263 AddressLiteral meta = __ allocate_metadata_address(nullptr);
1264 bool success = __ load_const_from_toc(Z_method, meta);
1265
1266 __ set_inst_mark();
1267 AddressLiteral a((address)-1);
1268 success = success && __ load_const_from_toc(Z_R1, a);
1269 if (!success) {
1270 bailout("const section overflow");
1271 return;
1272 }
1273
1274 __ z_br(Z_R1);
1275 assert(__ offset() - start <= call_stub_size(), "stub too big");
1276 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1277 }
1278
1279 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1280 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1281 if (opr1->is_single_cpu()) {
1282 Register reg1 = opr1->as_register();
1283 if (opr2->is_single_cpu()) {
1284 // cpu register - cpu register
1285 if (is_reference_type(opr1->type())) {
1286 __ z_clgr(reg1, opr2->as_register());
1287 } else {
1288 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1289 if (unsigned_comp) {
1290 __ z_clr(reg1, opr2->as_register());
1291 } else {
1292 __ z_cr(reg1, opr2->as_register());
1293 }
1294 }
1295 } else if (opr2->is_stack()) {
1296 // cpu register - stack
1297 if (is_reference_type(opr1->type())) {
1298 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1299 } else {
1300 if (unsigned_comp) {
1301 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1302 } else {
1303 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1304 }
1305 }
1306 } else if (opr2->is_constant()) {
1307 // cpu register - constant
1308 LIR_Const* c = opr2->as_constant_ptr();
1309 if (c->type() == T_INT) {
1310 if (unsigned_comp) {
1311 __ z_clfi(reg1, c->as_jint());
1312 } else {
1313 __ z_cfi(reg1, c->as_jint());
1314 }
1315 } else if (c->type() == T_METADATA) {
1316 // We only need, for now, comparison with null for metadata.
1317 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1318 Metadata* m = c->as_metadata();
1319 if (m == nullptr) {
1320 __ z_cghi(reg1, 0);
1321 } else {
1322 ShouldNotReachHere();
1323 }
1324 } else if (is_reference_type(c->type())) {
1325 // In 64bit oops are single register.
1326 jobject o = c->as_jobject();
1327 if (o == nullptr) {
1328 __ z_ltgr(reg1, reg1);
1329 } else {
1330 jobject2reg(o, Z_R1_scratch);
1331 __ z_cgr(reg1, Z_R1_scratch);
1332 }
1333 } else {
1334 fatal("unexpected type: %s", basictype_to_str(c->type()));
1335 }
1336 // cpu register - address
1337 } else if (opr2->is_address()) {
1338 if (op->info() != nullptr) {
1339 add_debug_info_for_null_check_here(op->info());
1340 }
1341 if (unsigned_comp) {
1342 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1343 } else {
1344 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1345 }
1346 } else {
1347 ShouldNotReachHere();
1348 }
1349
1350 } else if (opr1->is_double_cpu()) {
1351 assert(!unsigned_comp, "unexpected");
1352 Register xlo = opr1->as_register_lo();
1353 Register xhi = opr1->as_register_hi();
1354 if (opr2->is_double_cpu()) {
1355 __ z_cgr(xlo, opr2->as_register_lo());
1356 } else if (opr2->is_constant()) {
1357 // cpu register - constant 0
1358 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1359 __ z_ltgr(xlo, xlo);
1360 } else {
1361 ShouldNotReachHere();
1362 }
1363
1364 } else if (opr1->is_single_fpu()) {
1365 if (opr2->is_single_fpu()) {
1366 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1367 } else {
1368 // stack slot
1369 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1370 if (Immediate::is_uimm12(addr.disp())) {
1371 __ z_ceb(opr1->as_float_reg(), addr);
1372 } else {
1373 __ z_ley(Z_fscratch_1, addr);
1374 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1375 }
1376 }
1377 } else if (opr1->is_double_fpu()) {
1378 if (opr2->is_double_fpu()) {
1379 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1380 } else {
1381 // stack slot
1382 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1383 if (Immediate::is_uimm12(addr.disp())) {
1384 __ z_cdb(opr1->as_double_reg(), addr);
1385 } else {
1386 __ z_ldy(Z_fscratch_1, addr);
1387 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1388 }
1389 }
1390 } else {
1391 ShouldNotReachHere();
1392 }
1393 }
1394
1395 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1396 Label done;
1397 Register dreg = dst->as_register();
1398
1399 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1400 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1401 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1402 bool is_single = left->is_single_fpu();
1403 bool is_unordered_less = (code == lir_ucmp_fd2i);
1404 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1405 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1406 if (is_single) {
1407 __ z_cebr(lreg, rreg);
1408 } else {
1409 __ z_cdbr(lreg, rreg);
1410 }
1411 if (VM_Version::has_LoadStoreConditional()) {
1412 Register one = Z_R0_scratch;
1413 Register minus_one = Z_R1_scratch;
1414 __ z_lghi(minus_one, -1);
1415 __ z_lghi(one, 1);
1416 __ z_lghi(dreg, 0);
1417 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1418 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1419 } else {
1420 __ clear_reg(dreg, true, false);
1421 __ z_bre(done); // if (left == right) dst = 0
1422
1423 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1424 __ z_lhi(dreg, 1);
1425 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1426
1427 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1428 __ z_lhi(dreg, -1);
1429 }
1430 } else {
1431 assert(code == lir_cmp_l2i, "check");
1432 if (VM_Version::has_LoadStoreConditional()) {
1433 Register one = Z_R0_scratch;
1434 Register minus_one = Z_R1_scratch;
1435 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1436 __ z_lghi(minus_one, -1);
1437 __ z_lghi(one, 1);
1438 __ z_lghi(dreg, 0);
1439 __ z_locgr(dreg, one, Assembler::bcondHigh);
1440 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1441 } else {
1442 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1443 __ z_lghi(dreg, 0); // eq value
1444 __ z_bre(done);
1445 __ z_lghi(dreg, 1); // gt value
1446 __ z_brh(done);
1447 __ z_lghi(dreg, -1); // lt value
1448 }
1449 }
1450 __ bind(done);
1451 }
1452
1453 // result = condition ? opr1 : opr2
1454 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1455 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1456 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390");
1457
1458 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1459 switch (condition) {
1460 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1461 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1462 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1463 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1464 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1465 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1466 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1467 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1468 default: ShouldNotReachHere();
1469 }
1470
1471 if (opr1->is_cpu_register()) {
1472 reg2reg(opr1, result);
1473 } else if (opr1->is_stack()) {
1474 stack2reg(opr1, result, result->type());
1475 } else if (opr1->is_constant()) {
1476 const2reg(opr1, result, lir_patch_none, nullptr);
1477 } else {
1478 ShouldNotReachHere();
1479 }
1480
1481 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1482 // Optimized version that does not require a branch.
1483 if (opr2->is_single_cpu()) {
1484 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1485 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1486 } else if (opr2->is_double_cpu()) {
1487 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1488 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1489 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1490 } else if (opr2->is_single_stack()) {
1491 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1492 } else if (opr2->is_double_stack()) {
1493 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1494 } else {
1495 ShouldNotReachHere();
1496 }
1497 } else {
1498 Label skip;
1499 __ z_brc(acond, skip);
1500 if (opr2->is_cpu_register()) {
1501 reg2reg(opr2, result);
1502 } else if (opr2->is_stack()) {
1503 stack2reg(opr2, result, result->type());
1504 } else if (opr2->is_constant()) {
1505 const2reg(opr2, result, lir_patch_none, nullptr);
1506 } else {
1507 ShouldNotReachHere();
1508 }
1509 __ bind(skip);
1510 }
1511 }
1512
1513 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1514 CodeEmitInfo* info) {
1515 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1516
1517 if (left->is_single_cpu()) {
1518 assert(left == dest, "left and dest must be equal");
1519 Register lreg = left->as_register();
1520
1521 if (right->is_single_cpu()) {
1522 // cpu register - cpu register
1523 Register rreg = right->as_register();
1524 switch (code) {
1525 case lir_add: __ z_ar (lreg, rreg); break;
1526 case lir_sub: __ z_sr (lreg, rreg); break;
1527 case lir_mul: __ z_msr(lreg, rreg); break;
1528 default: ShouldNotReachHere();
1529 }
1530
1531 } else if (right->is_stack()) {
1532 // cpu register - stack
1533 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1534 switch (code) {
1535 case lir_add: __ z_ay(lreg, raddr); break;
1536 case lir_sub: __ z_sy(lreg, raddr); break;
1537 default: ShouldNotReachHere();
1538 }
1539
1540 } else if (right->is_constant()) {
1541 // cpu register - constant
1542 jint c = right->as_constant_ptr()->as_jint();
1543 switch (code) {
1544 case lir_add:
1545 __ add2reg_32(lreg, c);
1546 break;
1547 case lir_sub:
1548 __ add2reg_32(lreg, java_negate(c));
1549 break;
1550 case lir_mul: __ z_msfi(lreg, c); break;
1551 default: ShouldNotReachHere();
1552 }
1553
1554 } else {
1555 ShouldNotReachHere();
1556 }
1557
1558 } else if (left->is_double_cpu()) {
1559 assert(left == dest, "left and dest must be equal");
1560 Register lreg_lo = left->as_register_lo();
1561 Register lreg_hi = left->as_register_hi();
1562
1563 if (right->is_double_cpu()) {
1564 // cpu register - cpu register
1565 Register rreg_lo = right->as_register_lo();
1566 Register rreg_hi = right->as_register_hi();
1567 assert_different_registers(lreg_lo, rreg_lo);
1568 switch (code) {
1569 case lir_add:
1570 __ z_agr(lreg_lo, rreg_lo);
1571 break;
1572 case lir_sub:
1573 __ z_sgr(lreg_lo, rreg_lo);
1574 break;
1575 case lir_mul:
1576 __ z_msgr(lreg_lo, rreg_lo);
1577 break;
1578 default:
1579 ShouldNotReachHere();
1580 }
1581
1582 } else if (right->is_constant()) {
1583 // cpu register - constant
1584 jlong c = right->as_constant_ptr()->as_jlong_bits();
1585 switch (code) {
1586 case lir_add: __ z_agfi(lreg_lo, c); break;
1587 case lir_sub:
1588 if (c != min_jint) {
1589 __ z_agfi(lreg_lo, -c);
1590 } else {
1591 // -min_jint cannot be represented as simm32 in z_agfi
1592 // min_jint sign extended: 0xffffffff80000000
1593 // -min_jint as 64 bit integer: 0x0000000080000000
1594 // 0x80000000 can be represented as uimm32 in z_algfi
1595 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1596 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1597 }
1598 break;
1599 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1600 default:
1601 ShouldNotReachHere();
1602 }
1603
1604 } else {
1605 ShouldNotReachHere();
1606 }
1607
1608 } else if (left->is_single_fpu()) {
1609 assert(left == dest, "left and dest must be equal");
1610 FloatRegister lreg = left->as_float_reg();
1611 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1612 Address raddr;
1613
1614 if (rreg == fnoreg) {
1615 assert(right->is_single_stack(), "constants should be loaded into register");
1616 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1617 if (!Immediate::is_uimm12(raddr.disp())) {
1618 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1619 }
1620 }
1621
1622 if (rreg != fnoreg) {
1623 switch (code) {
1624 case lir_add: __ z_aebr(lreg, rreg); break;
1625 case lir_sub: __ z_sebr(lreg, rreg); break;
1626 case lir_mul: __ z_meebr(lreg, rreg); break;
1627 case lir_div: __ z_debr(lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630 } else {
1631 switch (code) {
1632 case lir_add: __ z_aeb(lreg, raddr); break;
1633 case lir_sub: __ z_seb(lreg, raddr); break;
1634 case lir_mul: __ z_meeb(lreg, raddr); break;
1635 case lir_div: __ z_deb(lreg, raddr); break;
1636 default: ShouldNotReachHere();
1637 }
1638 }
1639 } else if (left->is_double_fpu()) {
1640 assert(left == dest, "left and dest must be equal");
1641 FloatRegister lreg = left->as_double_reg();
1642 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1643 Address raddr;
1644
1645 if (rreg == fnoreg) {
1646 assert(right->is_double_stack(), "constants should be loaded into register");
1647 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1648 if (!Immediate::is_uimm12(raddr.disp())) {
1649 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1650 }
1651 }
1652
1653 if (rreg != fnoreg) {
1654 switch (code) {
1655 case lir_add: __ z_adbr(lreg, rreg); break;
1656 case lir_sub: __ z_sdbr(lreg, rreg); break;
1657 case lir_mul: __ z_mdbr(lreg, rreg); break;
1658 case lir_div: __ z_ddbr(lreg, rreg); break;
1659 default: ShouldNotReachHere();
1660 }
1661 } else {
1662 switch (code) {
1663 case lir_add: __ z_adb(lreg, raddr); break;
1664 case lir_sub: __ z_sdb(lreg, raddr); break;
1665 case lir_mul: __ z_mdb(lreg, raddr); break;
1666 case lir_div: __ z_ddb(lreg, raddr); break;
1667 default: ShouldNotReachHere();
1668 }
1669 }
1670 } else if (left->is_address()) {
1671 assert(left == dest, "left and dest must be equal");
1672 assert(code == lir_add, "unsupported operation");
1673 assert(right->is_constant(), "unsupported operand");
1674 jint c = right->as_constant_ptr()->as_jint();
1675 LIR_Address* lir_addr = left->as_address_ptr();
1676 Address addr = as_Address(lir_addr);
1677 switch (lir_addr->type()) {
1678 case T_INT:
1679 __ add2mem_32(addr, c, Z_R1_scratch);
1680 break;
1681 case T_LONG:
1682 __ add2mem_64(addr, c, Z_R1_scratch);
1683 break;
1684 default:
1685 ShouldNotReachHere();
1686 }
1687 } else {
1688 ShouldNotReachHere();
1689 }
1690 }
1691
1692 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1693 switch (code) {
1694 case lir_sqrt: {
1695 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1696 FloatRegister src_reg = value->as_double_reg();
1697 FloatRegister dst_reg = dest->as_double_reg();
1698 __ z_sqdbr(dst_reg, src_reg);
1699 break;
1700 }
1701 case lir_abs: {
1702 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1703 FloatRegister src_reg = value->as_double_reg();
1704 FloatRegister dst_reg = dest->as_double_reg();
1705 __ z_lpdbr(dst_reg, src_reg);
1706 break;
1707 }
1708 default: {
1709 ShouldNotReachHere();
1710 break;
1711 }
1712 }
1713 }
1714
1715 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1716 if (left->is_single_cpu()) {
1717 Register reg = left->as_register();
1718 if (right->is_constant()) {
1719 int val = right->as_constant_ptr()->as_jint();
1720 switch (code) {
1721 case lir_logic_and: __ z_nilf(reg, val); break;
1722 case lir_logic_or: __ z_oilf(reg, val); break;
1723 case lir_logic_xor: __ z_xilf(reg, val); break;
1724 default: ShouldNotReachHere();
1725 }
1726 } else if (right->is_stack()) {
1727 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1728 switch (code) {
1729 case lir_logic_and: __ z_ny(reg, raddr); break;
1730 case lir_logic_or: __ z_oy(reg, raddr); break;
1731 case lir_logic_xor: __ z_xy(reg, raddr); break;
1732 default: ShouldNotReachHere();
1733 }
1734 } else {
1735 Register rright = right->as_register();
1736 switch (code) {
1737 case lir_logic_and: __ z_nr(reg, rright); break;
1738 case lir_logic_or : __ z_or(reg, rright); break;
1739 case lir_logic_xor: __ z_xr(reg, rright); break;
1740 default: ShouldNotReachHere();
1741 }
1742 }
1743 move_regs(reg, dst->as_register());
1744 } else {
1745 Register l_lo = left->as_register_lo();
1746 if (right->is_constant()) {
1747 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1748 switch (code) {
1749 case lir_logic_and:
1750 __ z_ngr(l_lo, Z_R1_scratch);
1751 break;
1752 case lir_logic_or:
1753 __ z_ogr(l_lo, Z_R1_scratch);
1754 break;
1755 case lir_logic_xor:
1756 __ z_xgr(l_lo, Z_R1_scratch);
1757 break;
1758 default: ShouldNotReachHere();
1759 }
1760 } else {
1761 Register r_lo;
1762 if (is_reference_type(right->type())) {
1763 r_lo = right->as_register();
1764 } else {
1765 r_lo = right->as_register_lo();
1766 }
1767 switch (code) {
1768 case lir_logic_and:
1769 __ z_ngr(l_lo, r_lo);
1770 break;
1771 case lir_logic_or:
1772 __ z_ogr(l_lo, r_lo);
1773 break;
1774 case lir_logic_xor:
1775 __ z_xgr(l_lo, r_lo);
1776 break;
1777 default: ShouldNotReachHere();
1778 }
1779 }
1780
1781 Register dst_lo = dst->as_register_lo();
1782
1783 move_regs(l_lo, dst_lo);
1784 }
1785 }
1786
1787 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1788 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1789 if (left->is_double_cpu()) {
1790 // 64 bit integer case
1791 assert(left->is_double_cpu(), "left must be register");
1792 assert(right->is_double_cpu() || is_power_of_2(right->as_jlong()),
1793 "right must be register or power of 2 constant");
1794 assert(result->is_double_cpu(), "result must be register");
1795
1796 Register lreg = left->as_register_lo();
1797 Register dreg = result->as_register_lo();
1798
1799 if (right->is_constant()) {
1800 // Convert division by a power of two into some shifts and logical operations.
1801 Register treg1 = Z_R0_scratch;
1802 Register treg2 = Z_R1_scratch;
1803 jlong divisor = right->as_jlong();
1804 jlong log_divisor = log2i_exact(right->as_jlong());
1805
1806 if (divisor == min_jlong) {
1807 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1808 if (dreg == lreg) {
1809 NearLabel done;
1810 __ load_const_optimized(treg2, min_jlong);
1811 __ z_cgr(lreg, treg2);
1812 __ z_lghi(dreg, 0); // Preserves condition code.
1813 __ z_brne(done);
1814 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1815 __ bind(done);
1816 } else {
1817 assert_different_registers(dreg, lreg);
1818 NearLabel done;
1819 __ z_lghi(dreg, 0);
1820 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1821 __ z_lghi(dreg, 1);
1822 __ bind(done);
1823 }
1824 return;
1825 }
1826 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1827 if (divisor == 2) {
1828 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1829 } else {
1830 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1831 __ and_imm(treg2, divisor - 1, treg1, true);
1832 }
1833 if (code == lir_idiv) {
1834 __ z_agr(dreg, treg2);
1835 __ z_srag(dreg, dreg, log_divisor);
1836 } else {
1837 assert(code == lir_irem, "check");
1838 __ z_agr(treg2, dreg);
1839 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1840 __ z_sgr(dreg, treg2);
1841 }
1842 return;
1843 }
1844
1845 // Divisor is not a power of 2 constant.
1846 Register rreg = right->as_register_lo();
1847 Register treg = temp->as_register_lo();
1848 assert(right->is_double_cpu(), "right must be register");
1849 assert(lreg == Z_R11, "see ldivInOpr()");
1850 assert(rreg != lreg, "right register must not be same as left register");
1851 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1852 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1853
1854 Register R1 = lreg->predecessor();
1855 Register R2 = rreg;
1856 assert(code != lir_idiv || lreg==dreg, "see code below");
1857 if (code == lir_idiv) {
1858 __ z_lcgr(lreg, lreg);
1859 } else {
1860 __ clear_reg(dreg, true, false);
1861 }
1862 NearLabel done;
1863 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1864 if (code == lir_idiv) {
1865 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1866 }
1867 if (ImplicitDiv0Checks) {
1868 // No debug info because the idiv won't trap.
1869 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1870 // which is unnecessary, too.
1871 add_debug_info_for_div0(__ offset(), info);
1872 }
1873 __ z_dsgr(R1, R2);
1874 __ bind(done);
1875 return;
1876 }
1877
1878 // 32 bit integer case
1879
1880 assert(left->is_single_cpu(), "left must be register");
1881 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1882 assert(result->is_single_cpu(), "result must be register");
1883
1884 Register lreg = left->as_register();
1885 Register dreg = result->as_register();
1886
1887 if (right->is_constant()) {
1888 // Convert division by a power of two into some shifts and logical operations.
1889 Register treg1 = Z_R0_scratch;
1890 Register treg2 = Z_R1_scratch;
1891 jlong divisor = right->as_jint();
1892 jlong log_divisor = log2i_exact(right->as_jint());
1893 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1894 if (divisor == 2) {
1895 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1896 } else {
1897 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1898 __ and_imm(treg2, divisor - 1, treg1, true);
1899 }
1900 if (code == lir_idiv) {
1901 __ z_agr(dreg, treg2);
1902 __ z_srag(dreg, dreg, log_divisor);
1903 } else {
1904 assert(code == lir_irem, "check");
1905 __ z_agr(treg2, dreg);
1906 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1907 __ z_sgr(dreg, treg2);
1908 }
1909 return;
1910 }
1911
1912 // Divisor is not a power of 2 constant.
1913 Register rreg = right->as_register();
1914 Register treg = temp->as_register();
1915 assert(right->is_single_cpu(), "right must be register");
1916 assert(lreg == Z_R11, "left register must be rax,");
1917 assert(rreg != lreg, "right register must not be same as left register");
1918 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1919 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1920
1921 Register R1 = lreg->predecessor();
1922 Register R2 = rreg;
1923 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1924 if (ImplicitDiv0Checks) {
1925 // No debug info because the idiv won't trap.
1926 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1927 // which is unnecessary, too.
1928 add_debug_info_for_div0(__ offset(), info);
1929 }
1930 __ z_dsgfr(R1, R2);
1931 }
1932
1933 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1934 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1935 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1936
1937 // Exception object is not added to oop map by LinearScan
1938 // (LinearScan assumes that no oops are in fixed registers).
1939 info->add_register_oop(exceptionOop);
1940
1941 // Reuse the debug info from the safepoint poll for the throw op itself.
1942 __ get_PC(Z_EXC_PC);
1943 add_call_info(__ offset(), info); // for exception handler
1944 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1945 : StubId::c1_handle_exception_nofpu_id);
1946 emit_call_c(stub);
1947 }
1948
1949 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1950 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1951
1952 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1953 }
1954
1955 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1956 ciArrayKlass* default_type = op->expected_type();
1957 Register src = op->src()->as_register();
1958 Register dst = op->dst()->as_register();
1959 Register src_pos = op->src_pos()->as_register();
1960 Register dst_pos = op->dst_pos()->as_register();
1961 Register length = op->length()->as_register();
1962 Register tmp = op->tmp()->as_register();
1963
1964 CodeStub* stub = op->stub();
1965 int flags = op->flags();
1966 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
1967 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1968
1969 // If we don't know anything, just go through the generic arraycopy.
1970 if (default_type == nullptr) {
1971 address copyfunc_addr = StubRoutines::generic_arraycopy();
1972
1973 if (copyfunc_addr == nullptr) {
1974 // Take a slow path for generic arraycopy.
1975 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1976 __ bind(*stub->continuation());
1977 return;
1978 }
1979
1980 // Save outgoing arguments in callee saved registers (C convention) in case
1981 // a call to System.arraycopy is needed.
1982 Register callee_saved_src = Z_R10;
1983 Register callee_saved_src_pos = Z_R11;
1984 Register callee_saved_dst = Z_R12;
1985 Register callee_saved_dst_pos = Z_R13;
1986 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1987
1988 __ lgr_if_needed(callee_saved_src, src);
1989 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1990 __ lgr_if_needed(callee_saved_dst, dst);
1991 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1992 __ lgr_if_needed(callee_saved_length, length);
1993
1994 // C function requires 64 bit values.
1995 __ z_lgfr(src_pos, src_pos);
1996 __ z_lgfr(dst_pos, dst_pos);
1997 __ z_lgfr(length, length);
1998
1999 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
2000
2001 // The arguments are in the corresponding registers.
2002 assert(Z_ARG1 == src, "assumption");
2003 assert(Z_ARG2 == src_pos, "assumption");
2004 assert(Z_ARG3 == dst, "assumption");
2005 assert(Z_ARG4 == dst_pos, "assumption");
2006 assert(Z_ARG5 == length, "assumption");
2007 #ifndef PRODUCT
2008 if (PrintC1Statistics) {
2009 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
2010 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2011 }
2012 #endif
2013 emit_call_c(copyfunc_addr);
2014 CHECK_BAILOUT();
2015
2016 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2017
2018 __ z_lgr(tmp, Z_RET);
2019 __ z_xilf(tmp, -1);
2020
2021 // Restore values from callee saved registers so they are where the stub
2022 // expects them.
2023 __ lgr_if_needed(src, callee_saved_src);
2024 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2025 __ lgr_if_needed(dst, callee_saved_dst);
2026 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2027 __ lgr_if_needed(length, callee_saved_length);
2028
2029 __ z_sr(length, tmp);
2030 __ z_ar(src_pos, tmp);
2031 __ z_ar(dst_pos, tmp);
2032 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2033
2034 __ bind(*stub->continuation());
2035 return;
2036 }
2037
2038 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2039
2040 int elem_size = type2aelembytes(basic_type);
2041 int shift_amount;
2042
2043 switch (elem_size) {
2044 case 1 :
2045 shift_amount = 0;
2046 break;
2047 case 2 :
2048 shift_amount = 1;
2049 break;
2050 case 4 :
2051 shift_amount = 2;
2052 break;
2053 case 8 :
2054 shift_amount = 3;
2055 break;
2056 default:
2057 shift_amount = -1;
2058 ShouldNotReachHere();
2059 }
2060
2061 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2062 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2063
2064 // Length and pos's are all sign extended at this point on 64bit.
2065
2066 // test for null
2067 if (flags & LIR_OpArrayCopy::src_null_check) {
2068 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2069 }
2070 if (flags & LIR_OpArrayCopy::dst_null_check) {
2071 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2072 }
2073
2074 // Check if negative.
2075 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2076 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2077 }
2078 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2079 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2080 }
2081
2082 // If the compiler was not able to prove that exact type of the source or the destination
2083 // of the arraycopy is an array type, check at runtime if the source or the destination is
2084 // an instance type.
2085 if (flags & LIR_OpArrayCopy::type_check) {
2086 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2087
2088 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2089 __ load_klass(tmp, dst);
2090 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2091 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2092 }
2093
2094 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2095 __ load_klass(tmp, src);
2096 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2097 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2098 }
2099 }
2100
2101 if (flags & LIR_OpArrayCopy::src_range_check) {
2102 __ z_la(tmp, Address(src_pos, length));
2103 __ z_cl(tmp, src_length_addr);
2104 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2105 }
2106 if (flags & LIR_OpArrayCopy::dst_range_check) {
2107 __ z_la(tmp, Address(dst_pos, length));
2108 __ z_cl(tmp, dst_length_addr);
2109 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2110 }
2111
2112 if (flags & LIR_OpArrayCopy::length_positive_check) {
2113 __ z_ltr(length, length);
2114 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2115 }
2116
2117 // Stubs require 64 bit values.
2118 __ z_lgfr(src_pos, src_pos); // int -> long
2119 __ z_lgfr(dst_pos, dst_pos); // int -> long
2120 __ z_lgfr(length, length); // int -> long
2121
2122 if (flags & LIR_OpArrayCopy::type_check) {
2123 // We don't know the array types are compatible.
2124 if (basic_type != T_OBJECT) {
2125 // Simple test for basic type arrays.
2126 __ cmp_klasses_from_objects(src, dst, tmp, Z_R1_scratch);
2127 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2128 } else {
2129 // For object arrays, if src is a sub class of dst then we can
2130 // safely do the copy.
2131 NearLabel cont, slow;
2132 Register src_klass = Z_R1_scratch;
2133 Register dst_klass = Z_R10;
2134
2135 __ load_klass(src_klass, src);
2136 __ load_klass(dst_klass, dst);
2137
2138 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, nullptr);
2139
2140 store_parameter(src_klass, 0); // sub
2141 store_parameter(dst_klass, 1); // super
2142 emit_call_c(Runtime1::entry_for (StubId::c1_slow_subtype_check_id));
2143 CHECK_BAILOUT2(cont, slow);
2144 // Sets condition code 0 for match (2 otherwise).
2145 __ branch_optimized(Assembler::bcondEqual, cont);
2146
2147 __ bind(slow);
2148
2149 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2150 if (copyfunc_addr != nullptr) { // use stub if available
2151 // Src is not a sub class of dst so we have to do a
2152 // per-element check.
2153
2154 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2155 if ((flags & mask) != mask) {
2156 // Check that at least both of them object arrays.
2157 assert(flags & mask, "one of the two should be known to be an object array");
2158
2159 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2160 __ load_klass(tmp, src);
2161 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2162 __ load_klass(tmp, dst);
2163 }
2164 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2165 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2166 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2167 __ z_c(Z_R1_scratch, klass_lh_addr);
2168 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2169 }
2170
2171 // Save outgoing arguments in callee saved registers (C convention) in case
2172 // a call to System.arraycopy is needed.
2173 Register callee_saved_src = Z_R10;
2174 Register callee_saved_src_pos = Z_R11;
2175 Register callee_saved_dst = Z_R12;
2176 Register callee_saved_dst_pos = Z_R13;
2177 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2178
2179 __ lgr_if_needed(callee_saved_src, src);
2180 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2181 __ lgr_if_needed(callee_saved_dst, dst);
2182 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2183 __ lgr_if_needed(callee_saved_length, length);
2184
2185 __ z_llgfr(length, length); // Higher 32bits must be null.
2186
2187 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2188 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2189
2190 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2191 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2192 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2193 assert_different_registers(Z_ARG2, dst, length);
2194
2195 __ z_lgr(Z_ARG3, length);
2196 assert_different_registers(Z_ARG3, dst);
2197
2198 __ load_klass(Z_ARG5, dst);
2199 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2200 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2201 emit_call_c(copyfunc_addr);
2202 CHECK_BAILOUT2(cont, slow);
2203
2204 #ifndef PRODUCT
2205 if (PrintC1Statistics) {
2206 NearLabel failed;
2207 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2208 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2209 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2210 __ bind(failed);
2211 }
2212 #endif
2213
2214 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2215
2216 #ifndef PRODUCT
2217 if (PrintC1Statistics) {
2218 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2219 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2220 }
2221 #endif
2222
2223 __ z_lgr(tmp, Z_RET);
2224 __ z_xilf(tmp, -1);
2225
2226 // Restore previously spilled arguments
2227 __ lgr_if_needed(src, callee_saved_src);
2228 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2229 __ lgr_if_needed(dst, callee_saved_dst);
2230 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2231 __ lgr_if_needed(length, callee_saved_length);
2232
2233 __ z_sr(length, tmp);
2234 __ z_ar(src_pos, tmp);
2235 __ z_ar(dst_pos, tmp);
2236 }
2237
2238 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2239
2240 __ bind(cont);
2241 }
2242 }
2243
2244 #ifdef ASSERT
2245 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2246 // Sanity check the known type with the incoming class. For the
2247 // primitive case the types must match exactly with src.klass and
2248 // dst.klass each exactly matching the default type. For the
2249 // object array case, if no type check is needed then either the
2250 // dst type is exactly the expected type and the src type is a
2251 // subtype which we can't check or src is the same array as dst
2252 // but not necessarily exactly of type default_type.
2253 NearLabel known_ok, halt;
2254 metadata2reg(default_type->constant_encoding(), tmp);
2255 __ encode_klass_not_null(tmp);
2256
2257 if (basic_type != T_OBJECT) {
2258 __ cmp_klass(tmp, dst, Z_R1_scratch);
2259 __ branch_optimized(Assembler::bcondNotEqual, halt);
2260
2261 __ cmp_klass(tmp, src, Z_R1_scratch);
2262 __ branch_optimized(Assembler::bcondEqual, known_ok);
2263 } else {
2264 __ cmp_klass(tmp, dst, Z_R1_scratch);
2265 __ branch_optimized(Assembler::bcondEqual, known_ok);
2266 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2267 }
2268 __ bind(halt);
2269 __ stop("incorrect type information in arraycopy");
2270 __ bind(known_ok);
2271 }
2272 #endif
2273
2274 #ifndef PRODUCT
2275 if (PrintC1Statistics) {
2276 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2277 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2278 }
2279 #endif
2280
2281 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2282 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2283
2284 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2285 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2286 assert_different_registers(Z_ARG2, length);
2287 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2288 __ lgr_if_needed(Z_ARG3, length);
2289
2290 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2291 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2292 const char *name;
2293 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2294 __ call_VM_leaf(entry);
2295
2296 if (stub != nullptr) {
2297 __ bind(*stub->continuation());
2298 }
2299 }
2300
2301 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2302 if (dest->is_single_cpu()) {
2303 if (left->type() == T_OBJECT) {
2304 switch (code) {
2305 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2306 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2307 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2308 default: ShouldNotReachHere();
2309 }
2310 } else {
2311 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2312 Register masked_count = Z_R1_scratch;
2313 __ z_lr(masked_count, count->as_register());
2314 __ z_nill(masked_count, 31);
2315 switch (code) {
2316 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2317 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2318 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2319 default: ShouldNotReachHere();
2320 }
2321 }
2322 } else {
2323 switch (code) {
2324 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2325 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2326 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2327 default: ShouldNotReachHere();
2328 }
2329 }
2330 }
2331
2332 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2333 if (left->type() == T_OBJECT) {
2334 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2335 Register l = left->as_register();
2336 Register d = dest->as_register_lo();
2337 switch (code) {
2338 case lir_shl: __ z_sllg (d, l, count); break;
2339 case lir_shr: __ z_srag (d, l, count); break;
2340 case lir_ushr: __ z_srlg (d, l, count); break;
2341 default: ShouldNotReachHere();
2342 }
2343 return;
2344 }
2345 if (dest->is_single_cpu()) {
2346 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2347 count = count & 0x1F; // Java spec
2348 switch (code) {
2349 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2350 case lir_shr: __ z_sra (dest->as_register(), count); break;
2351 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2352 default: ShouldNotReachHere();
2353 }
2354 } else if (dest->is_double_cpu()) {
2355 count = count & 63; // Java spec
2356 Register l = left->as_pointer_register();
2357 Register d = dest->as_pointer_register();
2358 switch (code) {
2359 case lir_shl: __ z_sllg (d, l, count); break;
2360 case lir_shr: __ z_srag (d, l, count); break;
2361 case lir_ushr: __ z_srlg (d, l, count); break;
2362 default: ShouldNotReachHere();
2363 }
2364 } else {
2365 ShouldNotReachHere();
2366 }
2367 }
2368
2369 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2370 if (op->init_check()) {
2371 // Make sure klass is initialized & doesn't have finalizer.
2372 // init_state needs acquire, but S390 is TSO, and so we are already good.
2373 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2374 Register iklass = op->klass()->as_register();
2375 add_debug_info_for_null_check_here(op->stub()->info());
2376 if (Immediate::is_uimm12(state_offset)) {
2377 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2378 } else {
2379 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2380 }
2381 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2382 }
2383 __ allocate_object(op->obj()->as_register(),
2384 op->tmp1()->as_register(),
2385 op->tmp2()->as_register(),
2386 op->header_size(),
2387 op->object_size(),
2388 op->klass()->as_register(),
2389 *op->stub()->entry());
2390 __ bind(*op->stub()->continuation());
2391 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2392 }
2393
2394 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2395 Register len = op->len()->as_register();
2396 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2397
2398 if (UseSlowPath ||
2399 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2400 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2401 __ z_brul(*op->stub()->entry());
2402 } else {
2403 __ allocate_array(op->obj()->as_register(),
2404 op->len()->as_register(),
2405 op->tmp1()->as_register(),
2406 op->tmp2()->as_register(),
2407 arrayOopDesc::base_offset_in_bytes(op->type()),
2408 type2aelembytes(op->type()),
2409 op->klass()->as_register(),
2410 *op->stub()->entry(),
2411 op->zero_array());
2412 }
2413 __ bind(*op->stub()->continuation());
2414 }
2415
2416 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2417 Register recv, Register tmp1) {
2418 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
2419 __ profile_receiver_type(recv, mdo, mdp_offset, tmp1);
2420 }
2421
2422 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2423 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2424 Unimplemented();
2425 }
2426
2427 void LIR_Assembler::store_parameter(Register r, int param_num) {
2428 assert(param_num >= 0, "invalid num");
2429 int offset_in_bytes = param_num * BytesPerWord;
2430 check_reserved_argument_area(offset_in_bytes);
2431 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2432 __ z_stg(r, offset_in_bytes, Z_SP);
2433 }
2434
2435 void LIR_Assembler::store_parameter(jint c, int param_num) {
2436 assert(param_num >= 0, "invalid num");
2437 int offset_in_bytes = param_num * BytesPerWord;
2438 check_reserved_argument_area(offset_in_bytes);
2439 offset_in_bytes += FrameMap::first_available_sp_in_frame;
2440 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2441 }
2442
2443 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2444 // We always need a stub for the failure case.
2445 CodeStub* stub = op->stub();
2446 Register obj = op->object()->as_register();
2447 Register k_RInfo = op->tmp1()->as_register();
2448 Register klass_RInfo = op->tmp2()->as_register();
2449 Register dst = op->result_opr()->as_register();
2450 Register Rtmp1 = Z_R1_scratch;
2451 ciKlass* k = op->klass();
2452
2453 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2454
2455 // Check if it needs to be profiled.
2456 ciMethodData* md = nullptr;
2457 ciProfileData* data = nullptr;
2458
2459 if (op->should_profile()) {
2460 ciMethod* method = op->profiled_method();
2461 assert(method != nullptr, "Should have method");
2462 int bci = op->profiled_bci();
2463 md = method->method_data_or_null();
2464 assert(md != nullptr, "Sanity");
2465 data = md->bci_to_data(bci);
2466 assert(data != nullptr, "need data for type check");
2467 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2468 }
2469
2470 // Temp operands do not overlap with inputs, if this is their last
2471 // use (end of range is exclusive), so a register conflict is possible.
2472 if (obj == k_RInfo) {
2473 k_RInfo = dst;
2474 } else if (obj == klass_RInfo) {
2475 klass_RInfo = dst;
2476 }
2477 assert_different_registers(obj, k_RInfo, klass_RInfo);
2478
2479 if (op->should_profile()) {
2480 Register mdo = klass_RInfo;
2481 metadata2reg(md->constant_encoding(), mdo);
2482 NearLabel not_null;
2483 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2484 // Object is null; update MDO and exit.
2485 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2486 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2487 __ or2mem_8(data_addr, header_bits);
2488 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2489 __ bind(not_null);
2490
2491 Register recv = k_RInfo;
2492 __ load_klass(recv, obj);
2493 type_profile_helper(mdo, md, data, recv, Rtmp1);
2494 } else {
2495 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2496 }
2497
2498 Label *failure_target = failure;
2499 Label *success_target = success;
2500
2501 // Patching may screw with our temporaries,
2502 // so let's do it before loading the class.
2503 if (k->is_loaded()) {
2504 metadata2reg(k->constant_encoding(), k_RInfo);
2505 } else {
2506 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2507 }
2508 assert(obj != k_RInfo, "must be different");
2509
2510 __ verify_oop(obj, FILE_AND_LINE);
2511
2512 // Get object class.
2513 // Not a safepoint as obj null check happens earlier.
2514 if (op->fast_check()) {
2515 __ load_klass(klass_RInfo, obj);
2516 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2517 // Successful cast, fall through to profile or jump.
2518 } else {
2519 bool need_slow_path = !k->is_loaded() ||
2520 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2521 __ load_klass(klass_RInfo, obj);
2522 // Perform the fast part of the checking logic.
2523 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2524 (need_slow_path ? success_target : nullptr),
2525 failure_target, nullptr);
2526 if (need_slow_path) {
2527 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2528 address a = Runtime1::entry_for (StubId::c1_slow_subtype_check_id);
2529 store_parameter(klass_RInfo, 0); // sub
2530 store_parameter(k_RInfo, 1); // super
2531 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2532 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2533 // Fall through to success case.
2534 }
2535 }
2536
2537 __ branch_optimized(Assembler::bcondAlways, *success);
2538 }
2539
2540 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2541 LIR_Code code = op->code();
2542 if (code == lir_store_check) {
2543 Register value = op->object()->as_register();
2544 Register array = op->array()->as_register();
2545 Register k_RInfo = op->tmp1()->as_register();
2546 Register klass_RInfo = op->tmp2()->as_register();
2547 Register Rtmp1 = Z_R1_scratch;
2548
2549 CodeStub* stub = op->stub();
2550
2551 // Check if it needs to be profiled.
2552 ciMethodData* md = nullptr;
2553 ciProfileData* data = nullptr;
2554
2555 assert_different_registers(value, k_RInfo, klass_RInfo);
2556
2557 if (op->should_profile()) {
2558 ciMethod* method = op->profiled_method();
2559 assert(method != nullptr, "Should have method");
2560 int bci = op->profiled_bci();
2561 md = method->method_data_or_null();
2562 assert(md != nullptr, "Sanity");
2563 data = md->bci_to_data(bci);
2564 assert(data != nullptr, "need data for type check");
2565 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2566 }
2567 NearLabel done;
2568 Label *success_target = &done;
2569 Label *failure_target = stub->entry();
2570
2571 if (op->should_profile()) {
2572 Register mdo = klass_RInfo;
2573 metadata2reg(md->constant_encoding(), mdo);
2574 NearLabel not_null;
2575 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2576 // Object is null; update MDO and exit.
2577 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2578 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2579 __ or2mem_8(data_addr, header_bits);
2580 __ branch_optimized(Assembler::bcondAlways, done);
2581 __ bind(not_null);
2582
2583 Register recv = k_RInfo;
2584 __ load_klass(recv, value);
2585 type_profile_helper(mdo, md, data, recv, Rtmp1);
2586 } else {
2587 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2588 }
2589
2590 add_debug_info_for_null_check_here(op->info_for_exception());
2591 __ load_klass(k_RInfo, array);
2592 __ load_klass(klass_RInfo, value);
2593
2594 // Get instance klass (it's already uncompressed).
2595 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2596 // Perform the fast part of the checking logic.
2597 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
2598 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2599 address a = Runtime1::entry_for (StubId::c1_slow_subtype_check_id);
2600 store_parameter(klass_RInfo, 0); // sub
2601 store_parameter(k_RInfo, 1); // super
2602 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2603 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2604 // Fall through to success case.
2605
2606 __ bind(done);
2607 } else {
2608 if (code == lir_checkcast) {
2609 Register obj = op->object()->as_register();
2610 Register dst = op->result_opr()->as_register();
2611 NearLabel success;
2612 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2613 __ bind(success);
2614 __ lgr_if_needed(dst, obj);
2615 } else {
2616 if (code == lir_instanceof) {
2617 Register obj = op->object()->as_register();
2618 Register dst = op->result_opr()->as_register();
2619 NearLabel success, failure, done;
2620 emit_typecheck_helper(op, &success, &failure, &failure);
2621 __ bind(failure);
2622 __ clear_reg(dst);
2623 __ branch_optimized(Assembler::bcondAlways, done);
2624 __ bind(success);
2625 __ load_const_optimized(dst, 1);
2626 __ bind(done);
2627 } else {
2628 ShouldNotReachHere();
2629 }
2630 }
2631 }
2632 }
2633
2634 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2635 Register addr = op->addr()->as_pointer_register();
2636 Register t1_cmp = Z_R1_scratch;
2637 if (op->code() == lir_cas_long) {
2638 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2639 Register new_value_lo = op->new_value()->as_register_lo();
2640 __ z_lgr(t1_cmp, cmp_value_lo);
2641 // Perform the compare and swap operation.
2642 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2643 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2644 Register cmp_value = op->cmp_value()->as_register();
2645 Register new_value = op->new_value()->as_register();
2646 if (op->code() == lir_cas_obj) {
2647 if (UseCompressedOops) {
2648 t1_cmp = op->tmp1()->as_register();
2649 Register t2_new = op->tmp2()->as_register();
2650 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2651 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2652 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2653 __ z_cs(t1_cmp, t2_new, 0, addr);
2654 } else {
2655 __ z_lgr(t1_cmp, cmp_value);
2656 __ z_csg(t1_cmp, new_value, 0, addr);
2657 }
2658 } else {
2659 __ z_lr(t1_cmp, cmp_value);
2660 __ z_cs(t1_cmp, new_value, 0, addr);
2661 }
2662 } else {
2663 ShouldNotReachHere(); // new lir_cas_??
2664 }
2665 }
2666
2667 void LIR_Assembler::breakpoint() {
2668 Unimplemented();
2669 // __ breakpoint_trap();
2670 }
2671
2672 void LIR_Assembler::push(LIR_Opr opr) {
2673 ShouldNotCallThis(); // unused
2674 }
2675
2676 void LIR_Assembler::pop(LIR_Opr opr) {
2677 ShouldNotCallThis(); // unused
2678 }
2679
2680 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2681 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2682 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2683 }
2684
2685 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2686 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2687 Register hdr = op->hdr_opr()->as_register();
2688 Register lock = op->lock_opr()->as_register();
2689 if (op->code() == lir_lock) {
2690 // Add debug info for NullPointerException only if one is possible.
2691 if (op->info() != nullptr) {
2692 add_debug_info_for_null_check_here(op->info());
2693 }
2694 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2695 // done
2696 } else if (op->code() == lir_unlock) {
2697 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2698 } else {
2699 ShouldNotReachHere();
2700 }
2701 __ bind(*op->stub()->continuation());
2702 }
2703
2704 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2705 Register obj = op->obj()->as_pointer_register();
2706 Register result = op->result_opr()->as_pointer_register();
2707
2708 CodeEmitInfo* info = op->info();
2709 if (info != nullptr) {
2710 add_debug_info_for_null_check_here(info);
2711 }
2712
2713 __ load_klass(result, obj);
2714 }
2715 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2716 ciMethod* method = op->profiled_method();
2717 int bci = op->profiled_bci();
2718 ciMethod* callee = op->profiled_callee();
2719
2720 // Update counter for all call types.
2721 ciMethodData* md = method->method_data_or_null();
2722 assert(md != nullptr, "Sanity");
2723 ciProfileData* data = md->bci_to_data(bci);
2724 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2725 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2726 Register mdo = op->mdo()->as_register();
2727 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2728 Register tmp1 = op->tmp1()->as_register_lo();
2729 metadata2reg(md->constant_encoding(), mdo);
2730
2731 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2732 // Perform additional virtual call profiling for invokevirtual and
2733 // invokeinterface bytecodes
2734 if (op->should_profile_receiver_type()) {
2735 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2736 Register recv = op->recv()->as_register();
2737 assert_different_registers(mdo, tmp1, recv);
2738 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2739 ciKlass* known_klass = op->known_holder();
2740 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2741 // We know the type that will be seen at this call site; we can
2742 // statically update the MethodData* rather than needing to do
2743 // dynamic tests on the receiver type.
2744
2745 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2746 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2747 ciKlass* receiver = vc_data->receiver(i);
2748 if (known_klass->equals(receiver)) {
2749 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2750 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2751 return;
2752 }
2753 }
2754 // Receiver type is not found in profile data.
2755 // Fall back to runtime helper to handle the rest at runtime.
2756 metadata2reg(known_klass->constant_encoding(), recv);
2757 } else {
2758 __ load_klass(recv, recv);
2759 }
2760 type_profile_helper(mdo, md, data, recv, tmp1);
2761 } else {
2762 // static call
2763 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2764 }
2765 }
2766
2767 void LIR_Assembler::align_backward_branch_target() {
2768 __ align(OptoLoopAlignment);
2769 }
2770
2771 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2772 // tmp must be unused
2773 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2774 assert(left->is_register(), "can only handle registers");
2775
2776 if (left->is_single_cpu()) {
2777 __ z_lcr(dest->as_register(), left->as_register());
2778 } else if (left->is_single_fpu()) {
2779 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2780 } else if (left->is_double_fpu()) {
2781 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2782 } else {
2783 assert(left->is_double_cpu(), "Must be a long");
2784 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2785 }
2786 }
2787
2788 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2789 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2790 assert(!tmp->is_valid(), "don't need temporary");
2791 emit_call_c(dest);
2792 CHECK_BAILOUT();
2793 if (info != nullptr) {
2794 add_call_info_here(info);
2795 }
2796 __ post_call_nop();
2797 }
2798
2799 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2800 ShouldNotCallThis(); // not needed on ZARCH_64
2801 }
2802
2803 void LIR_Assembler::membar() {
2804 __ z_fence();
2805 }
2806
2807 void LIR_Assembler::membar_acquire() {
2808 __ z_acquire();
2809 }
2810
2811 void LIR_Assembler::membar_release() {
2812 __ z_release();
2813 }
2814
2815 void LIR_Assembler::membar_loadload() {
2816 __ z_acquire();
2817 }
2818
2819 void LIR_Assembler::membar_storestore() {
2820 __ z_release();
2821 }
2822
2823 void LIR_Assembler::membar_loadstore() {
2824 __ z_acquire();
2825 }
2826
2827 void LIR_Assembler::membar_storeload() {
2828 __ z_fence();
2829 }
2830
2831 void LIR_Assembler::on_spin_wait() {
2832 Unimplemented();
2833 }
2834
2835 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2836 assert(addr_opr->is_address(), "must be an address");
2837 assert(dest->is_register(), "must be a register");
2838
2839 LIR_Address* addr = addr_opr->as_address_ptr();
2840 Register reg = dest->as_pointer_register();
2841 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2842
2843 if (addr->index()->is_illegal() && patch_code != lir_patch_none) {
2844 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2845
2846 // TODO: Use load_const_32to64 here by extending NativeMovRegMem to support both instruction patterns.
2847 __ load_const(Z_R0_scratch, (intptr_t)0);
2848 __ z_agrk(reg, addr->base()->as_pointer_register(), Z_R0_scratch);
2849 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2850 } else {
2851 __ load_address(reg, as_Address(addr));
2852 }
2853 }
2854
2855 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2856 ShouldNotCallThis(); // unused
2857 }
2858
2859 #ifdef ASSERT
2860 // Emit run-time assertion.
2861 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2862 Unimplemented();
2863 }
2864 #endif
2865
2866 void LIR_Assembler::peephole(LIR_List*) {
2867 // Do nothing for now.
2868 }
2869
2870 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2871 assert(code == lir_xadd, "lir_xchg not supported");
2872 Address src_addr = as_Address(src->as_address_ptr());
2873 Register base = src_addr.base();
2874 intptr_t disp = src_addr.disp();
2875 if (src_addr.index()->is_valid()) {
2876 // LAA and LAAG do not support index register.
2877 __ load_address(Z_R1_scratch, src_addr);
2878 base = Z_R1_scratch;
2879 disp = 0;
2880 }
2881 if (data->type() == T_INT) {
2882 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2883 } else if (data->type() == T_LONG) {
2884 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2885 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2886 } else {
2887 ShouldNotReachHere();
2888 }
2889 }
2890
2891 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2892 Register obj = op->obj()->as_register();
2893 Register tmp1 = op->tmp()->as_pointer_register();
2894 Register tmp2 = Z_R1_scratch;
2895 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2896 ciKlass* exact_klass = op->exact_klass();
2897 intptr_t current_klass = op->current_klass();
2898 bool not_null = op->not_null();
2899 bool no_conflict = op->no_conflict();
2900
2901 Label update, next, none, null_seen, init_klass;
2902
2903 bool do_null = !not_null;
2904 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2905 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2906
2907 assert(do_null || do_update, "why are we here?");
2908 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2909
2910 __ verify_oop(obj, FILE_AND_LINE);
2911
2912 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2913 __ z_ltgr(tmp1, obj);
2914 }
2915 if (do_null) {
2916 __ z_brnz(update);
2917 if (!TypeEntries::was_null_seen(current_klass)) {
2918 __ z_lg(tmp1, mdo_addr);
2919 __ z_oill(tmp1, TypeEntries::null_seen);
2920 __ z_stg(tmp1, mdo_addr);
2921 }
2922 if (do_update) {
2923 __ z_bru(next);
2924 }
2925 } else {
2926 __ asm_assert(Assembler::bcondNotZero, "unexpected null obj", __LINE__);
2927 }
2928
2929 __ bind(update);
2930
2931 if (do_update) {
2932 #ifdef ASSERT
2933 if (exact_klass != nullptr) {
2934 __ load_klass(tmp1, tmp1);
2935 metadata2reg(exact_klass->constant_encoding(), tmp2);
2936 __ z_cgr(tmp1, tmp2);
2937 __ asm_assert(Assembler::bcondEqual, "exact klass and actual klass differ", __LINE__);
2938 }
2939 #endif
2940
2941 Label do_update;
2942 __ z_lg(tmp2, mdo_addr);
2943
2944 if (!no_conflict) {
2945 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2946 if (exact_klass != nullptr) {
2947 metadata2reg(exact_klass->constant_encoding(), tmp1);
2948 } else {
2949 __ load_klass(tmp1, tmp1);
2950 }
2951
2952 // Klass seen before: nothing to do (regardless of unknown bit).
2953 __ z_lgr(Z_R0_scratch, tmp2);
2954 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2955 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2956 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2957
2958 // Already unknown: Nothing to do anymore.
2959 __ z_tmll(tmp2, TypeEntries::type_unknown);
2960 __ z_brc(Assembler::bcondAllOne, next);
2961
2962 if (TypeEntries::is_type_none(current_klass)) {
2963 __ z_lgr(Z_R0_scratch, tmp2);
2964 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2965 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2966 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
2967 }
2968 } else {
2969 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2970 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2971
2972 // Already unknown: Nothing to do anymore.
2973 __ z_tmll(tmp2, TypeEntries::type_unknown);
2974 __ z_brc(Assembler::bcondAllOne, next);
2975 }
2976
2977 // Different than before. Cannot keep accurate profile.
2978 __ z_oill(tmp2, TypeEntries::type_unknown);
2979 __ z_bru(do_update);
2980 } else {
2981 // There's a single possible klass at this profile point.
2982 assert(exact_klass != nullptr, "should be");
2983 if (TypeEntries::is_type_none(current_klass)) {
2984 metadata2reg(exact_klass->constant_encoding(), tmp1);
2985 __ z_lgr(Z_R0_scratch, tmp2);
2986 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2987 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2988 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2989 #ifdef ASSERT
2990 {
2991 Label ok;
2992 __ z_lgr(Z_R0_scratch, tmp2);
2993 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2994 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2995 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
2996 __ stop("unexpected profiling mismatch");
2997 __ bind(ok);
2998 }
2999 #endif
3000
3001 } else {
3002 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3003 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3004
3005 // Already unknown: Nothing to do anymore.
3006 __ z_tmll(tmp2, TypeEntries::type_unknown);
3007 __ z_brc(Assembler::bcondAllOne, next);
3008 __ z_oill(tmp2, TypeEntries::type_unknown);
3009 __ z_bru(do_update);
3010 }
3011 }
3012
3013 __ bind(init_klass);
3014 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3015 __ z_ogr(tmp2, tmp1);
3016
3017 __ bind(do_update);
3018 __ z_stg(tmp2, mdo_addr);
3019
3020 __ bind(next);
3021 }
3022 }
3023
3024 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3025 assert(op->crc()->is_single_cpu(), "crc must be register");
3026 assert(op->val()->is_single_cpu(), "byte value must be register");
3027 assert(op->result_opr()->is_single_cpu(), "result must be register");
3028 Register crc = op->crc()->as_register();
3029 Register val = op->val()->as_register();
3030 Register res = op->result_opr()->as_register();
3031
3032 assert_different_registers(val, crc, res);
3033
3034 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3035 __ kernel_crc32_singleByteReg(crc, val, res, true);
3036 __ z_lgfr(res, crc);
3037 }
3038
3039 #undef __