1 /*
   2  * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2016, 2019 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/collectedHeap.hpp"
  36 #include "memory/universe.hpp"
  37 #include "nativeInst_s390.hpp"
  38 #include "oops/objArrayKlass.hpp"
  39 #include "runtime/frame.inline.hpp"
  40 #include "runtime/safepointMechanism.inline.hpp"
  41 #include "runtime/sharedRuntime.hpp"
  42 #include "runtime/stubRoutines.hpp"
  43 #include "utilities/macros.hpp"
  44 #include "utilities/powerOfTwo.hpp"
  45 #include "vmreg_s390.inline.hpp"
  46 
  47 #define __ _masm->
  48 
  49 #ifndef PRODUCT
  50 #undef __
  51 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
  52 #endif
  53 
  54 //------------------------------------------------------------
  55 
  56 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  57   // Not used on ZARCH_64
  58   ShouldNotCallThis();
  59   return false;
  60 }
  61 
  62 LIR_Opr LIR_Assembler::receiverOpr() {
  63   return FrameMap::Z_R2_oop_opr;
  64 }
  65 
  66 LIR_Opr LIR_Assembler::osrBufferPointer() {
  67   return FrameMap::Z_R2_opr;
  68 }
  69 
  70 int LIR_Assembler::initial_frame_size_in_bytes() const {
  71   return in_bytes(frame_map()->framesize_in_bytes());
  72 }
  73 
  74 // Inline cache check: done before the frame is built.
  75 // The inline cached class is in Z_inline_cache(Z_R9).
  76 // We fetch the class of the receiver and compare it with the cached class.
  77 // If they do not match we jump to the slow case.
  78 int LIR_Assembler::check_icache() {
  79   Register receiver = receiverOpr()->as_register();
  80   int offset = __ offset();
  81   __ inline_cache_check(receiver, Z_inline_cache);
  82   return offset;
  83 }
  84 
  85 void LIR_Assembler::clinit_barrier(ciMethod* method) {
  86   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
  87 
  88   Label L_skip_barrier;
  89   Register klass = Z_R1_scratch;
  90 
  91   metadata2reg(method->holder()->constant_encoding(), klass);
  92   __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
  93 
  94   __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
  95   __ z_br(klass);
  96 
  97   __ bind(L_skip_barrier);
  98 }
  99 
 100 void LIR_Assembler::osr_entry() {
 101   // On-stack-replacement entry sequence (interpreter frame layout described in frame_s390.hpp):
 102   //
 103   //   1. Create a new compiled activation.
 104   //   2. Initialize local variables in the compiled activation. The expression stack must be empty
 105   //      at the osr_bci; it is not initialized.
 106   //   3. Jump to the continuation address in compiled code to resume execution.
 107 
 108   // OSR entry point
 109   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 110   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 111   ValueStack* entry_state = osr_entry->end()->state();
 112   int number_of_locks = entry_state->locks_size();
 113 
 114   // Create a frame for the compiled activation.
 115   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 116 
 117   // OSR buffer is
 118   //
 119   // locals[nlocals-1..0]
 120   // monitors[number_of_locks-1..0]
 121   //
 122   // Locals is a direct copy of the interpreter frame so in the osr buffer
 123   // the first slot in the local array is the last local from the interpreter
 124   // and the last slot is local[0] (receiver) from the interpreter
 125   //
 126   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 127   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 128   // in the interpreter frame (the method lock if a sync method)
 129 
 130   // Initialize monitors in the compiled activation.
 131   //   I0: pointer to osr buffer
 132   //
 133   // All other registers are dead at this point and the locals will be
 134   // copied into place by code emitted in the IR.
 135 
 136   Register OSR_buf = osrBufferPointer()->as_register();
 137   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 138     int monitor_offset = BytesPerWord * method()->max_locals() +
 139       (2 * BytesPerWord) * (number_of_locks - 1);
 140     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 141     // the OSR buffer using 2 word entries: first the lock and then
 142     // the oop.
 143     for (int i = 0; i < number_of_locks; i++) {
 144       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 145       // Verify the interpreter's monitor has a non-null object.
 146       __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__);
 147       // Copy the lock field into the compiled activation.
 148       __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
 149       __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
 150       __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
 151       __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
 152     }
 153   }
 154 }
 155 
 156 // --------------------------------------------------------------------------------------------
 157 
 158 address LIR_Assembler::emit_call_c(address a) {
 159   __ align_call_far_patchable(__ pc());
 160   address call_addr = __ call_c_opt(a);
 161   if (call_addr == NULL) {
 162     bailout("const section overflow");
 163   }
 164   return call_addr;
 165 }
 166 
 167 int LIR_Assembler::emit_exception_handler() {
 168   // Generate code for exception handler.
 169   address handler_base = __ start_a_stub(exception_handler_size());
 170   if (handler_base == NULL) {
 171     // Not enough space left for the handler.
 172     bailout("exception handler overflow");
 173     return -1;
 174   }
 175 
 176   int offset = code_offset();
 177 
 178   address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id);
 179   address call_addr = emit_call_c(a);
 180   CHECK_BAILOUT_(-1);
 181   __ should_not_reach_here();
 182   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 183   __ end_a_stub();
 184 
 185   return offset;
 186 }
 187 
 188 // Emit the code to remove the frame from the stack in the exception
 189 // unwind path.
 190 int LIR_Assembler::emit_unwind_handler() {
 191 #ifndef PRODUCT
 192   if (CommentedAssembly) {
 193     _masm->block_comment("Unwind handler");
 194   }
 195 #endif
 196 
 197   int offset = code_offset();
 198   Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
 199   Register Rtmp1                      = Z_R11;
 200   Register Rtmp2                      = Z_R12;
 201 
 202   // Fetch the exception from TLS and clear out exception related thread state.
 203   Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
 204   Address exc_pc_addr  = Address(Z_thread, JavaThread::exception_pc_offset());
 205   __ z_lg(Z_EXC_OOP, exc_oop_addr);
 206   __ clear_mem(exc_oop_addr, sizeof(oop));
 207   __ clear_mem(exc_pc_addr, sizeof(intptr_t));
 208 
 209   __ bind(_unwind_handler_entry);
 210   __ verify_not_null_oop(Z_EXC_OOP);
 211   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 212     __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
 213   }
 214 
 215   // Perform needed unlocking.
 216   MonitorExitStub* stub = NULL;
 217   if (method()->is_synchronized()) {
 218     // Runtime1::monitorexit_id expects lock address in Z_R1_scratch.
 219     LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
 220     monitor_address(0, lock);
 221     stub = new MonitorExitStub(lock, true, 0);
 222     __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
 223     __ bind(*stub->continuation());
 224   }
 225 
 226   if (compilation()->env()->dtrace_method_probes()) {
 227     ShouldNotReachHere(); // Not supported.
 228 #if 0
 229     __ mov(rdi, r15_thread);
 230     __ mov_metadata(rsi, method()->constant_encoding());
 231     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 232 #endif
 233   }
 234 
 235   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 236     __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved);  // Restore the exception.
 237   }
 238 
 239   // Remove the activation and dispatch to the unwind handler.
 240   __ pop_frame();
 241   __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP);
 242 
 243   // Z_EXC_OOP: exception oop
 244   // Z_EXC_PC: exception pc
 245 
 246   // Dispatch to the unwind logic.
 247   __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id));
 248   __ z_br(Z_R5);
 249 
 250   // Emit the slow path assembly.
 251   if (stub != NULL) {
 252     stub->emit_code(this);
 253   }
 254 
 255   return offset;
 256 }
 257 
 258 int LIR_Assembler::emit_deopt_handler() {
 259   // Generate code for exception handler.
 260   address handler_base = __ start_a_stub(deopt_handler_size());
 261   if (handler_base == NULL) {
 262     // Not enough space left for the handler.
 263     bailout("deopt handler overflow");
 264     return -1;
 265   }  int offset = code_offset();
 266   // Size must be constant (see HandlerImpl::emit_deopt_handler).
 267   __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
 268   __ call(Z_R1_scratch);
 269   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 270   __ end_a_stub();
 271 
 272   return offset;
 273 }
 274 
 275 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 276   if (o == NULL) {
 277     __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
 278   } else {
 279     AddressLiteral a = __ allocate_oop_address(o);
 280     bool success = __ load_oop_from_toc(reg, a, reg);
 281     if (!success) {
 282       bailout("const section overflow");
 283     }
 284   }
 285 }
 286 
 287 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 288   // Allocate a new index in table to hold the object once it's been patched.
 289   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 290   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 291 
 292   AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
 293   assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
 294   // The NULL will be dynamically patched later so the sequence to
 295   // load the address literal must not be optimized.
 296   __ load_const(reg, addrlit);
 297 
 298   patching_epilog(patch, lir_patch_normal, reg, info);
 299 }
 300 
 301 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
 302   bool success = __ set_metadata_constant(md, reg);
 303   if (!success) {
 304     bailout("const section overflow");
 305     return;
 306   }
 307 }
 308 
 309 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 310   // Allocate a new index in table to hold the klass once it's been patched.
 311   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 312   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 313   AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
 314   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 315   // The NULL will be dynamically patched later so the sequence to
 316   // load the address literal must not be optimized.
 317   __ load_const(reg, addrlit);
 318 
 319   patching_epilog(patch, lir_patch_normal, reg, info);
 320 }
 321 
 322 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 323   switch (op->code()) {
 324     case lir_idiv:
 325     case lir_irem:
 326       arithmetic_idiv(op->code(),
 327                       op->in_opr1(),
 328                       op->in_opr2(),
 329                       op->in_opr3(),
 330                       op->result_opr(),
 331                       op->info());
 332       break;
 333     case lir_fmad: {
 334       const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
 335                           opr2 = op->in_opr2()->as_double_reg(),
 336                           opr3 = op->in_opr3()->as_double_reg(),
 337                           res  = op->result_opr()->as_double_reg();
 338       __ z_madbr(opr3, opr1, opr2);
 339       if (res != opr3) { __ z_ldr(res, opr3); }
 340     } break;
 341     case lir_fmaf: {
 342       const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
 343                           opr2 = op->in_opr2()->as_float_reg(),
 344                           opr3 = op->in_opr3()->as_float_reg(),
 345                           res  = op->result_opr()->as_float_reg();
 346       __ z_maebr(opr3, opr1, opr2);
 347       if (res != opr3) { __ z_ler(res, opr3); }
 348     } break;
 349     default: ShouldNotReachHere(); break;
 350   }
 351 }
 352 
 353 
 354 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 355 #ifdef ASSERT
 356   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 357   if (op->block() != NULL)  { _branch_target_blocks.append(op->block()); }
 358   if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); }
 359 #endif
 360 
 361   if (op->cond() == lir_cond_always) {
 362     if (op->info() != NULL) { add_debug_info_for_branch(op->info()); }
 363     __ branch_optimized(Assembler::bcondAlways, *(op->label()));
 364   } else {
 365     Assembler::branch_condition acond = Assembler::bcondZero;
 366     if (op->code() == lir_cond_float_branch) {
 367       assert(op->ublock() != NULL, "must have unordered successor");
 368       __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
 369     }
 370     switch (op->cond()) {
 371       case lir_cond_equal:        acond = Assembler::bcondEqual;     break;
 372       case lir_cond_notEqual:     acond = Assembler::bcondNotEqual;  break;
 373       case lir_cond_less:         acond = Assembler::bcondLow;       break;
 374       case lir_cond_lessEqual:    acond = Assembler::bcondNotHigh;   break;
 375       case lir_cond_greaterEqual: acond = Assembler::bcondNotLow;    break;
 376       case lir_cond_greater:      acond = Assembler::bcondHigh;      break;
 377       case lir_cond_belowEqual:   acond = Assembler::bcondNotHigh;   break;
 378       case lir_cond_aboveEqual:   acond = Assembler::bcondNotLow;    break;
 379       default:                         ShouldNotReachHere();
 380     }
 381     __ branch_optimized(acond,*(op->label()));
 382   }
 383 }
 384 
 385 
 386 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 387   LIR_Opr src  = op->in_opr();
 388   LIR_Opr dest = op->result_opr();
 389 
 390   switch (op->bytecode()) {
 391     case Bytecodes::_i2l:
 392       __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
 393       break;
 394 
 395     case Bytecodes::_l2i:
 396       __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
 397       break;
 398 
 399     case Bytecodes::_i2b:
 400       __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
 401       break;
 402 
 403     case Bytecodes::_i2c:
 404       __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
 405       break;
 406 
 407     case Bytecodes::_i2s:
 408       __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
 409       break;
 410 
 411     case Bytecodes::_f2d:
 412       assert(dest->is_double_fpu(), "check");
 413       __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
 414       break;
 415 
 416     case Bytecodes::_d2f:
 417       assert(dest->is_single_fpu(), "check");
 418       __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
 419       break;
 420 
 421     case Bytecodes::_i2f:
 422       __ z_cefbr(dest->as_float_reg(), src->as_register());
 423       break;
 424 
 425     case Bytecodes::_i2d:
 426       __ z_cdfbr(dest->as_double_reg(), src->as_register());
 427       break;
 428 
 429     case Bytecodes::_l2f:
 430       __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
 431       break;
 432     case Bytecodes::_l2d:
 433       __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
 434       break;
 435 
 436     case Bytecodes::_f2i:
 437     case Bytecodes::_f2l: {
 438       Label done;
 439       FloatRegister Rsrc = src->as_float_reg();
 440       Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
 441       __ clear_reg(Rdst, true, false);
 442       __ z_cebr(Rsrc, Rsrc);
 443       __ z_brno(done); // NaN -> 0
 444       if (op->bytecode() == Bytecodes::_f2i) {
 445         __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
 446       } else { // op->bytecode() == Bytecodes::_f2l
 447         __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
 448       }
 449       __ bind(done);
 450     }
 451     break;
 452 
 453     case Bytecodes::_d2i:
 454     case Bytecodes::_d2l: {
 455       Label done;
 456       FloatRegister Rsrc = src->as_double_reg();
 457       Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
 458       __ clear_reg(Rdst, true, false);  // Don't set CC.
 459       __ z_cdbr(Rsrc, Rsrc);
 460       __ z_brno(done); // NaN -> 0
 461       if (op->bytecode() == Bytecodes::_d2i) {
 462         __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
 463       } else { // Bytecodes::_d2l
 464         __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
 465       }
 466       __ bind(done);
 467     }
 468     break;
 469 
 470     default: ShouldNotReachHere();
 471   }
 472 }
 473 
 474 void LIR_Assembler::align_call(LIR_Code code) {
 475   // End of call instruction must be 4 byte aligned.
 476   int offset = __ offset();
 477   switch (code) {
 478     case lir_icvirtual_call:
 479       offset += MacroAssembler::load_const_from_toc_size();
 480       // no break
 481     case lir_static_call:
 482     case lir_optvirtual_call:
 483     case lir_dynamic_call:
 484       offset += NativeCall::call_far_pcrelative_displacement_offset;
 485       break;
 486     default: ShouldNotReachHere();
 487   }
 488   if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
 489     __ nop();
 490   }
 491 }
 492 
 493 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 494   assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
 495          "must be aligned (offset=%d)", __ offset());
 496   assert(rtype == relocInfo::none ||
 497          rtype == relocInfo::opt_virtual_call_type ||
 498          rtype == relocInfo::static_call_type, "unexpected rtype");
 499   // Prepend each BRASL with a nop.
 500   __ relocate(rtype);
 501   __ z_nop();
 502   __ z_brasl(Z_R14, op->addr());
 503   add_call_info(code_offset(), op->info());
 504 }
 505 
 506 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 507   address virtual_call_oop_addr = NULL;
 508   AddressLiteral empty_ic((address) Universe::non_oop_word());
 509   virtual_call_oop_addr = __ pc();
 510   bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
 511   if (!success) {
 512     bailout("const section overflow");
 513     return;
 514   }
 515 
 516   // CALL to fixup routine. Fixup routine uses ScopeDesc info
 517   // to determine who we intended to call.
 518   __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
 519   call(op, relocInfo::none);
 520 }
 521 
 522 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 523   if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
 524 }
 525 
 526 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 527   assert(src->is_constant(), "should not call otherwise");
 528   assert(dest->is_stack(), "should not call otherwise");
 529   LIR_Const* c = src->as_constant_ptr();
 530 
 531   unsigned int lmem = 0;
 532   unsigned int lcon = 0;
 533   int64_t cbits = 0;
 534   Address dest_addr;
 535   switch (c->type()) {
 536     case T_INT:  // fall through
 537     case T_FLOAT:
 538       dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 539       lmem = 4; lcon = 4; cbits = c->as_jint_bits();
 540       break;
 541 
 542     case T_ADDRESS:
 543       dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 544       lmem = 8; lcon = 4; cbits = c->as_jint_bits();
 545       break;
 546 
 547     case T_OBJECT:
 548       dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 549       if (c->as_jobject() == NULL) {
 550         __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
 551       } else {
 552         jobject2reg(c->as_jobject(), Z_R1_scratch);
 553         __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
 554       }
 555       return;
 556 
 557     case T_LONG:  // fall through
 558     case T_DOUBLE:
 559       dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 560       lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
 561       break;
 562 
 563     default:
 564       ShouldNotReachHere();
 565   }
 566 
 567   __ store_const(dest_addr, cbits, lmem, lcon);
 568 }
 569 
 570 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 571   assert(src->is_constant(), "should not call otherwise");
 572   assert(dest->is_address(), "should not call otherwise");
 573 
 574   LIR_Const* c = src->as_constant_ptr();
 575   Address addr = as_Address(dest->as_address_ptr());
 576 
 577   int store_offset = -1;
 578 
 579   if (dest->as_address_ptr()->index()->is_valid()) {
 580     switch (type) {
 581       case T_INT:    // fall through
 582       case T_FLOAT:
 583         __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
 584         store_offset = __ offset();
 585         if (Immediate::is_uimm12(addr.disp())) {
 586           __ z_st(Z_R0_scratch, addr);
 587         } else {
 588           __ z_sty(Z_R0_scratch, addr);
 589         }
 590         break;
 591 
 592       case T_ADDRESS:
 593         __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
 594         store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 595         break;
 596 
 597       case T_OBJECT:  // fall through
 598       case T_ARRAY:
 599         if (c->as_jobject() == NULL) {
 600           if (UseCompressedOops && !wide) {
 601             __ clear_reg(Z_R1_scratch, false);
 602             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
 603           } else {
 604             __ clear_reg(Z_R1_scratch, true);
 605             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 606           }
 607         } else {
 608           jobject2reg(c->as_jobject(), Z_R1_scratch);
 609           if (UseCompressedOops && !wide) {
 610             __ encode_heap_oop(Z_R1_scratch);
 611             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
 612           } else {
 613             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 614           }
 615         }
 616         assert(store_offset >= 0, "check");
 617         break;
 618 
 619       case T_LONG:    // fall through
 620       case T_DOUBLE:
 621         __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
 622         store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 623         break;
 624 
 625       case T_BOOLEAN: // fall through
 626       case T_BYTE:
 627         __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
 628         store_offset = __ offset();
 629         if (Immediate::is_uimm12(addr.disp())) {
 630           __ z_stc(Z_R0_scratch, addr);
 631         } else {
 632           __ z_stcy(Z_R0_scratch, addr);
 633         }
 634         break;
 635 
 636       case T_CHAR:    // fall through
 637       case T_SHORT:
 638         __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
 639         store_offset = __ offset();
 640         if (Immediate::is_uimm12(addr.disp())) {
 641           __ z_sth(Z_R0_scratch, addr);
 642         } else {
 643           __ z_sthy(Z_R0_scratch, addr);
 644         }
 645         break;
 646 
 647       default:
 648         ShouldNotReachHere();
 649     }
 650 
 651   } else { // no index
 652 
 653     unsigned int lmem = 0;
 654     unsigned int lcon = 0;
 655     int64_t cbits = 0;
 656 
 657     switch (type) {
 658       case T_INT:    // fall through
 659       case T_FLOAT:
 660         lmem = 4; lcon = 4; cbits = c->as_jint_bits();
 661         break;
 662 
 663       case T_ADDRESS:
 664         lmem = 8; lcon = 4; cbits = c->as_jint_bits();
 665         break;
 666 
 667       case T_OBJECT:  // fall through
 668       case T_ARRAY:
 669         if (c->as_jobject() == NULL) {
 670           if (UseCompressedOops && !wide) {
 671             store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
 672           } else {
 673             store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
 674           }
 675         } else {
 676           jobject2reg(c->as_jobject(), Z_R1_scratch);
 677           if (UseCompressedOops && !wide) {
 678             __ encode_heap_oop(Z_R1_scratch);
 679             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
 680           } else {
 681             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 682           }
 683         }
 684         assert(store_offset >= 0, "check");
 685         break;
 686 
 687       case T_LONG:    // fall through
 688       case T_DOUBLE:
 689         lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
 690         break;
 691 
 692       case T_BOOLEAN: // fall through
 693       case T_BYTE:
 694         lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
 695         break;
 696 
 697       case T_CHAR:    // fall through
 698       case T_SHORT:
 699         lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
 700         break;
 701 
 702       default:
 703         ShouldNotReachHere();
 704     }
 705 
 706     if (store_offset == -1) {
 707       store_offset = __ store_const(addr, cbits, lmem, lcon);
 708       assert(store_offset >= 0, "check");
 709     }
 710   }
 711 
 712   if (info != NULL) {
 713     add_debug_info_for_null_check(store_offset, info);
 714   }
 715 }
 716 
 717 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 718   assert(src->is_constant(), "should not call otherwise");
 719   assert(dest->is_register(), "should not call otherwise");
 720   LIR_Const* c = src->as_constant_ptr();
 721 
 722   switch (c->type()) {
 723     case T_INT: {
 724       assert(patch_code == lir_patch_none, "no patching handled here");
 725       __ load_const_optimized(dest->as_register(), c->as_jint());
 726       break;
 727     }
 728 
 729     case T_ADDRESS: {
 730       assert(patch_code == lir_patch_none, "no patching handled here");
 731       __ load_const_optimized(dest->as_register(), c->as_jint());
 732       break;
 733     }
 734 
 735     case T_LONG: {
 736       assert(patch_code == lir_patch_none, "no patching handled here");
 737       __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
 738       break;
 739     }
 740 
 741     case T_OBJECT: {
 742       if (patch_code != lir_patch_none) {
 743         jobject2reg_with_patching(dest->as_register(), info);
 744       } else {
 745         jobject2reg(c->as_jobject(), dest->as_register());
 746       }
 747       break;
 748     }
 749 
 750     case T_METADATA: {
 751       if (patch_code != lir_patch_none) {
 752         klass2reg_with_patching(dest->as_register(), info);
 753       } else {
 754         metadata2reg(c->as_metadata(), dest->as_register());
 755       }
 756       break;
 757     }
 758 
 759     case T_FLOAT: {
 760       Register toc_reg = Z_R1_scratch;
 761       __ load_toc(toc_reg);
 762       address const_addr = __ float_constant(c->as_jfloat());
 763       if (const_addr == NULL) {
 764         bailout("const section overflow");
 765         break;
 766       }
 767       int displ = const_addr - _masm->code()->consts()->start();
 768       if (dest->is_single_fpu()) {
 769         __ z_ley(dest->as_float_reg(), displ, toc_reg);
 770       } else {
 771         assert(dest->is_single_cpu(), "Must be a cpu register.");
 772         __ z_ly(dest->as_register(), displ, toc_reg);
 773       }
 774     }
 775     break;
 776 
 777     case T_DOUBLE: {
 778       Register toc_reg = Z_R1_scratch;
 779       __ load_toc(toc_reg);
 780       address const_addr = __ double_constant(c->as_jdouble());
 781       if (const_addr == NULL) {
 782         bailout("const section overflow");
 783         break;
 784       }
 785       int displ = const_addr - _masm->code()->consts()->start();
 786       if (dest->is_double_fpu()) {
 787         __ z_ldy(dest->as_double_reg(), displ, toc_reg);
 788       } else {
 789         assert(dest->is_double_cpu(), "Must be a long register.");
 790         __ z_lg(dest->as_register_lo(), displ, toc_reg);
 791       }
 792     }
 793     break;
 794 
 795     default:
 796       ShouldNotReachHere();
 797   }
 798 }
 799 
 800 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 801   if (addr->base()->is_illegal()) {
 802     Unimplemented();
 803   }
 804 
 805   Register base = addr->base()->as_pointer_register();
 806 
 807   if (addr->index()->is_illegal()) {
 808     return Address(base, addr->disp());
 809   } else if (addr->index()->is_cpu_register()) {
 810     Register index = addr->index()->as_pointer_register();
 811     return Address(base, index, addr->disp());
 812   } else if (addr->index()->is_constant()) {
 813     intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
 814     return Address(base, addr_offset);
 815   } else {
 816     ShouldNotReachHere();
 817     return Address();
 818   }
 819 }
 820 
 821 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 822   switch (type) {
 823     case T_INT:
 824     case T_FLOAT: {
 825       Register tmp = Z_R1_scratch;
 826       Address from = frame_map()->address_for_slot(src->single_stack_ix());
 827       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
 828       __ mem2reg_opt(tmp, from, false);
 829       __ reg2mem_opt(tmp, to, false);
 830       break;
 831     }
 832     case T_ADDRESS:
 833     case T_OBJECT: {
 834       Register tmp = Z_R1_scratch;
 835       Address from = frame_map()->address_for_slot(src->single_stack_ix());
 836       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
 837       __ mem2reg_opt(tmp, from, true);
 838       __ reg2mem_opt(tmp, to, true);
 839       break;
 840     }
 841     case T_LONG:
 842     case T_DOUBLE: {
 843       Register tmp = Z_R1_scratch;
 844       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
 845       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
 846       __ mem2reg_opt(tmp, from, true);
 847       __ reg2mem_opt(tmp, to, true);
 848       break;
 849     }
 850 
 851     default:
 852       ShouldNotReachHere();
 853   }
 854 }
 855 
 856 // 4-byte accesses only! Don't use it to access 8 bytes!
 857 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 858   ShouldNotCallThis();
 859   return 0; // unused
 860 }
 861 
 862 // 4-byte accesses only! Don't use it to access 8 bytes!
 863 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 864   ShouldNotCallThis();
 865   return 0; // unused
 866 }
 867 
 868 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
 869                             CodeEmitInfo* info, bool wide) {
 870 
 871   assert(type != T_METADATA, "load of metadata ptr not supported");
 872   LIR_Address* addr = src_opr->as_address_ptr();
 873   LIR_Opr to_reg = dest;
 874 
 875   Register src = addr->base()->as_pointer_register();
 876   Register disp_reg = Z_R0;
 877   int disp_value = addr->disp();
 878   bool needs_patching = (patch_code != lir_patch_none);
 879 
 880   if (addr->base()->type() == T_OBJECT) {
 881     __ verify_oop(src, FILE_AND_LINE);
 882   }
 883 
 884   PatchingStub* patch = NULL;
 885   if (needs_patching) {
 886     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 887     assert(!to_reg->is_double_cpu() ||
 888            patch_code == lir_patch_none ||
 889            patch_code == lir_patch_normal, "patching doesn't match register");
 890   }
 891 
 892   if (addr->index()->is_illegal()) {
 893     if (!Immediate::is_simm20(disp_value)) {
 894       if (needs_patching) {
 895         __ load_const(Z_R1_scratch, (intptr_t)0);
 896       } else {
 897         __ load_const_optimized(Z_R1_scratch, disp_value);
 898       }
 899       disp_reg = Z_R1_scratch;
 900       disp_value = 0;
 901     }
 902   } else {
 903     if (!Immediate::is_simm20(disp_value)) {
 904       __ load_const_optimized(Z_R1_scratch, disp_value);
 905       __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
 906       disp_reg = Z_R1_scratch;
 907       disp_value = 0;
 908     }
 909     disp_reg = addr->index()->as_pointer_register();
 910   }
 911 
 912   // Remember the offset of the load. The patching_epilog must be done
 913   // before the call to add_debug_info, otherwise the PcDescs don't get
 914   // entered in increasing order.
 915   int offset = code_offset();
 916 
 917   assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
 918 
 919   bool short_disp = Immediate::is_uimm12(disp_value);
 920 
 921   switch (type) {
 922     case T_BOOLEAN: // fall through
 923     case T_BYTE  :  __ z_lb(dest->as_register(),   disp_value, disp_reg, src); break;
 924     case T_CHAR  :  __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
 925     case T_SHORT :
 926       if (short_disp) {
 927                     __ z_lh(dest->as_register(),   disp_value, disp_reg, src);
 928       } else {
 929                     __ z_lhy(dest->as_register(),  disp_value, disp_reg, src);
 930       }
 931       break;
 932     case T_INT   :
 933       if (short_disp) {
 934                     __ z_l(dest->as_register(),    disp_value, disp_reg, src);
 935       } else {
 936                     __ z_ly(dest->as_register(),   disp_value, disp_reg, src);
 937       }
 938       break;
 939     case T_ADDRESS:
 940       __ z_lg(dest->as_register(), disp_value, disp_reg, src);
 941       break;
 942     case T_ARRAY : // fall through
 943     case T_OBJECT:
 944     {
 945       if (UseCompressedOops && !wide) {
 946         __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
 947         __ oop_decoder(dest->as_register(), dest->as_register(), true);
 948       } else {
 949         __ z_lg(dest->as_register(), disp_value, disp_reg, src);
 950       }
 951       __ verify_oop(dest->as_register(), FILE_AND_LINE);
 952       break;
 953     }
 954     case T_FLOAT:
 955       if (short_disp) {
 956                     __ z_le(dest->as_float_reg(),  disp_value, disp_reg, src);
 957       } else {
 958                     __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
 959       }
 960       break;
 961     case T_DOUBLE:
 962       if (short_disp) {
 963                     __ z_ld(dest->as_double_reg(),  disp_value, disp_reg, src);
 964       } else {
 965                     __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
 966       }
 967       break;
 968     case T_LONG  :  __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
 969     default      : ShouldNotReachHere();
 970   }
 971 
 972   if (patch != NULL) {
 973     patching_epilog(patch, patch_code, src, info);
 974   }
 975   if (info != NULL) add_debug_info_for_null_check(offset, info);
 976 }
 977 
 978 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 979   assert(src->is_stack(), "should not call otherwise");
 980   assert(dest->is_register(), "should not call otherwise");
 981 
 982   if (dest->is_single_cpu()) {
 983     if (is_reference_type(type)) {
 984       __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
 985       __ verify_oop(dest->as_register(), FILE_AND_LINE);
 986     } else if (type == T_METADATA || type == T_ADDRESS) {
 987       __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
 988     } else {
 989       __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
 990     }
 991   } else if (dest->is_double_cpu()) {
 992     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
 993     __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
 994   } else if (dest->is_single_fpu()) {
 995     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
 996     __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
 997   } else if (dest->is_double_fpu()) {
 998     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
 999     __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
1000   } else {
1001     ShouldNotReachHere();
1002   }
1003 }
1004 
1005 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1006   assert(src->is_register(), "should not call otherwise");
1007   assert(dest->is_stack(), "should not call otherwise");
1008 
1009   if (src->is_single_cpu()) {
1010     const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1011     if (is_reference_type(type)) {
1012       __ verify_oop(src->as_register(), FILE_AND_LINE);
1013       __ reg2mem_opt(src->as_register(), dst, true);
1014     } else if (type == T_METADATA || type == T_ADDRESS) {
1015       __ reg2mem_opt(src->as_register(), dst, true);
1016     } else {
1017       __ reg2mem_opt(src->as_register(), dst, false);
1018     }
1019   } else if (src->is_double_cpu()) {
1020     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1021     __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1022   } else if (src->is_single_fpu()) {
1023     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1024     __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1025   } else if (src->is_double_fpu()) {
1026     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1027     __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1028   } else {
1029     ShouldNotReachHere();
1030   }
1031 }
1032 
1033 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1034   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1035     if (from_reg->is_double_fpu()) {
1036       // double to double moves
1037       assert(to_reg->is_double_fpu(), "should match");
1038       __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1039     } else {
1040       // float to float moves
1041       assert(to_reg->is_single_fpu(), "should match");
1042       __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1043     }
1044   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1045     if (from_reg->is_double_cpu()) {
1046       __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1047     } else if (to_reg->is_double_cpu()) {
1048       // int to int moves
1049       __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1050     } else {
1051       // int to int moves
1052       __ z_lgr(to_reg->as_register(), from_reg->as_register());
1053     }
1054   } else {
1055     ShouldNotReachHere();
1056   }
1057   if (is_reference_type(to_reg->type())) {
1058     __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1059   }
1060 }
1061 
1062 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1063                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1064                             bool wide) {
1065   assert(type != T_METADATA, "store of metadata ptr not supported");
1066   LIR_Address* addr = dest_opr->as_address_ptr();
1067 
1068   Register dest = addr->base()->as_pointer_register();
1069   Register disp_reg = Z_R0;
1070   int disp_value = addr->disp();
1071   bool needs_patching = (patch_code != lir_patch_none);
1072 
1073   if (addr->base()->is_oop_register()) {
1074     __ verify_oop(dest, FILE_AND_LINE);
1075   }
1076 
1077   PatchingStub* patch = NULL;
1078   if (needs_patching) {
1079     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1080     assert(!from->is_double_cpu() ||
1081            patch_code == lir_patch_none ||
1082            patch_code == lir_patch_normal, "patching doesn't match register");
1083   }
1084 
1085   assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1086   if (addr->index()->is_illegal()) {
1087     if (!Immediate::is_simm20(disp_value)) {
1088       if (needs_patching) {
1089         __ load_const(Z_R1_scratch, (intptr_t)0);
1090       } else {
1091         __ load_const_optimized(Z_R1_scratch, disp_value);
1092       }
1093       disp_reg = Z_R1_scratch;
1094       disp_value = 0;
1095     }
1096   } else {
1097     if (!Immediate::is_simm20(disp_value)) {
1098       __ load_const_optimized(Z_R1_scratch, disp_value);
1099       __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1100       disp_reg = Z_R1_scratch;
1101       disp_value = 0;
1102     }
1103     disp_reg = addr->index()->as_pointer_register();
1104   }
1105 
1106   assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1107 
1108   if (is_reference_type(type)) {
1109     __ verify_oop(from->as_register(), FILE_AND_LINE);
1110   }
1111 
1112   bool short_disp = Immediate::is_uimm12(disp_value);
1113 
1114   // Remember the offset of the store. The patching_epilog must be done
1115   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1116   // entered in increasing order.
1117   int offset = code_offset();
1118   switch (type) {
1119     case T_BOOLEAN: // fall through
1120     case T_BYTE  :
1121       if (short_disp) {
1122                     __ z_stc(from->as_register(),  disp_value, disp_reg, dest);
1123       } else {
1124                     __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1125       }
1126       break;
1127     case T_CHAR  : // fall through
1128     case T_SHORT :
1129       if (short_disp) {
1130                     __ z_sth(from->as_register(),  disp_value, disp_reg, dest);
1131       } else {
1132                     __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1133       }
1134       break;
1135     case T_INT   :
1136       if (short_disp) {
1137                     __ z_st(from->as_register(),  disp_value, disp_reg, dest);
1138       } else {
1139                     __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1140       }
1141       break;
1142     case T_LONG  :  __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1143     case T_ADDRESS: __ z_stg(from->as_register(),    disp_value, disp_reg, dest); break;
1144       break;
1145     case T_ARRAY : // fall through
1146     case T_OBJECT:
1147       {
1148         if (UseCompressedOops && !wide) {
1149           Register compressed_src = Z_R14;
1150           __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1151           offset = code_offset();
1152           if (short_disp) {
1153             __ z_st(compressed_src,  disp_value, disp_reg, dest);
1154           } else {
1155             __ z_sty(compressed_src, disp_value, disp_reg, dest);
1156           }
1157         } else {
1158           __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1159         }
1160         break;
1161       }
1162     case T_FLOAT :
1163       if (short_disp) {
1164         __ z_ste(from->as_float_reg(),  disp_value, disp_reg, dest);
1165       } else {
1166         __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1167       }
1168       break;
1169     case T_DOUBLE:
1170       if (short_disp) {
1171         __ z_std(from->as_double_reg(),  disp_value, disp_reg, dest);
1172       } else {
1173         __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1174       }
1175       break;
1176     default: ShouldNotReachHere();
1177   }
1178 
1179   if (patch != NULL) {
1180     patching_epilog(patch, patch_code, dest, info);
1181   }
1182 
1183   if (info != NULL) add_debug_info_for_null_check(offset, info);
1184 }
1185 
1186 
1187 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1188   assert(result->is_illegal() ||
1189          (result->is_single_cpu() && result->as_register() == Z_R2) ||
1190          (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1191          (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1192          (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1193 
1194   __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1195 
1196   // Pop the frame before the safepoint code.
1197   __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1198 
1199   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1200     __ reserved_stack_check(Z_R14);
1201   }
1202 
1203   // We need to mark the code position where the load from the safepoint
1204   // polling page was emitted as relocInfo::poll_return_type here.
1205   __ relocate(relocInfo::poll_return_type);
1206   __ load_from_polling_page(Z_R1_scratch);
1207 
1208   __ z_br(Z_R14); // Return to caller.
1209 }
1210 
1211 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1212   const Register poll_addr = tmp->as_register_lo();
1213   __ z_lg(poll_addr, Address(Z_thread, JavaThread::polling_page_offset()));
1214   guarantee(info != NULL, "Shouldn't be NULL");
1215   add_debug_info_for_branch(info);
1216   int offset = __ offset();
1217   __ relocate(relocInfo::poll_type);
1218   __ load_from_polling_page(poll_addr);
1219   return offset;
1220 }
1221 
1222 void LIR_Assembler::emit_static_call_stub() {
1223 
1224   // Stub is fixed up when the corresponding call is converted from calling
1225   // compiled code to calling interpreted code.
1226 
1227   address call_pc = __ pc();
1228   address stub = __ start_a_stub(call_stub_size());
1229   if (stub == NULL) {
1230     bailout("static call stub overflow");
1231     return;
1232   }
1233 
1234   int start = __ offset();
1235 
1236   __ relocate(static_stub_Relocation::spec(call_pc));
1237 
1238   // See also Matcher::interpreter_method_reg().
1239   AddressLiteral meta = __ allocate_metadata_address(NULL);
1240   bool success = __ load_const_from_toc(Z_method, meta);
1241 
1242   __ set_inst_mark();
1243   AddressLiteral a((address)-1);
1244   success = success && __ load_const_from_toc(Z_R1, a);
1245   if (!success) {
1246     bailout("const section overflow");
1247     return;
1248   }
1249 
1250   __ z_br(Z_R1);
1251   assert(__ offset() - start <= call_stub_size(), "stub too big");
1252   __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1253 }
1254 
1255 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1256   bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1257   if (opr1->is_single_cpu()) {
1258     Register reg1 = opr1->as_register();
1259     if (opr2->is_single_cpu()) {
1260       // cpu register - cpu register
1261       if (is_reference_type(opr1->type())) {
1262         __ z_clgr(reg1, opr2->as_register());
1263       } else {
1264         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1265         if (unsigned_comp) {
1266           __ z_clr(reg1, opr2->as_register());
1267         } else {
1268           __ z_cr(reg1, opr2->as_register());
1269         }
1270       }
1271     } else if (opr2->is_stack()) {
1272       // cpu register - stack
1273       if (is_reference_type(opr1->type())) {
1274         __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1275       } else {
1276         if (unsigned_comp) {
1277           __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1278         } else {
1279           __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1280         }
1281       }
1282     } else if (opr2->is_constant()) {
1283       // cpu register - constant
1284       LIR_Const* c = opr2->as_constant_ptr();
1285       if (c->type() == T_INT) {
1286         if (unsigned_comp) {
1287           __ z_clfi(reg1, c->as_jint());
1288         } else {
1289           __ z_cfi(reg1, c->as_jint());
1290         }
1291       } else if (c->type() == T_METADATA) {
1292         // We only need, for now, comparison with NULL for metadata.
1293         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1294         Metadata* m = c->as_metadata();
1295         if (m == NULL) {
1296           __ z_cghi(reg1, 0);
1297         } else {
1298           ShouldNotReachHere();
1299         }
1300       } else if (is_reference_type(c->type())) {
1301         // In 64bit oops are single register.
1302         jobject o = c->as_jobject();
1303         if (o == NULL) {
1304           __ z_ltgr(reg1, reg1);
1305         } else {
1306           jobject2reg(o, Z_R1_scratch);
1307           __ z_cgr(reg1, Z_R1_scratch);
1308         }
1309       } else {
1310         fatal("unexpected type: %s", basictype_to_str(c->type()));
1311       }
1312       // cpu register - address
1313     } else if (opr2->is_address()) {
1314       if (op->info() != NULL) {
1315         add_debug_info_for_null_check_here(op->info());
1316       }
1317       if (unsigned_comp) {
1318         __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1319       } else {
1320         __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1321       }
1322     } else {
1323       ShouldNotReachHere();
1324     }
1325 
1326   } else if (opr1->is_double_cpu()) {
1327     assert(!unsigned_comp, "unexpected");
1328     Register xlo = opr1->as_register_lo();
1329     Register xhi = opr1->as_register_hi();
1330     if (opr2->is_double_cpu()) {
1331       __ z_cgr(xlo, opr2->as_register_lo());
1332     } else if (opr2->is_constant()) {
1333       // cpu register - constant 0
1334       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1335       __ z_ltgr(xlo, xlo);
1336     } else {
1337       ShouldNotReachHere();
1338     }
1339 
1340   } else if (opr1->is_single_fpu()) {
1341     if (opr2->is_single_fpu()) {
1342       __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1343     } else {
1344       // stack slot
1345       Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1346       if (Immediate::is_uimm12(addr.disp())) {
1347         __ z_ceb(opr1->as_float_reg(), addr);
1348       } else {
1349         __ z_ley(Z_fscratch_1, addr);
1350         __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1351       }
1352     }
1353   } else if (opr1->is_double_fpu()) {
1354     if (opr2->is_double_fpu()) {
1355     __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1356     } else {
1357       // stack slot
1358       Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1359       if (Immediate::is_uimm12(addr.disp())) {
1360         __ z_cdb(opr1->as_double_reg(), addr);
1361       } else {
1362         __ z_ldy(Z_fscratch_1, addr);
1363         __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1364       }
1365     }
1366   } else {
1367     ShouldNotReachHere();
1368   }
1369 }
1370 
1371 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1372   Label    done;
1373   Register dreg = dst->as_register();
1374 
1375   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1376     assert((left->is_single_fpu() && right->is_single_fpu()) ||
1377            (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1378     bool is_single = left->is_single_fpu();
1379     bool is_unordered_less = (code == lir_ucmp_fd2i);
1380     FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1381     FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1382     if (is_single) {
1383       __ z_cebr(lreg, rreg);
1384     } else {
1385       __ z_cdbr(lreg, rreg);
1386     }
1387     if (VM_Version::has_LoadStoreConditional()) {
1388       Register one       = Z_R0_scratch;
1389       Register minus_one = Z_R1_scratch;
1390       __ z_lghi(minus_one, -1);
1391       __ z_lghi(one,  1);
1392       __ z_lghi(dreg, 0);
1393       __ z_locgr(dreg, one,       is_unordered_less ? Assembler::bcondHigh            : Assembler::bcondHighOrNotOrdered);
1394       __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1395     } else {
1396       __ clear_reg(dreg, true, false);
1397       __ z_bre(done); // if (left == right) dst = 0
1398 
1399       // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1400       __ z_lhi(dreg, 1);
1401       __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1402 
1403       // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1404       __ z_lhi(dreg, -1);
1405     }
1406   } else {
1407     assert(code == lir_cmp_l2i, "check");
1408     if (VM_Version::has_LoadStoreConditional()) {
1409       Register one       = Z_R0_scratch;
1410       Register minus_one = Z_R1_scratch;
1411       __ z_cgr(left->as_register_lo(), right->as_register_lo());
1412       __ z_lghi(minus_one, -1);
1413       __ z_lghi(one,  1);
1414       __ z_lghi(dreg, 0);
1415       __ z_locgr(dreg, one, Assembler::bcondHigh);
1416       __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1417     } else {
1418       __ z_cgr(left->as_register_lo(), right->as_register_lo());
1419       __ z_lghi(dreg,  0);     // eq value
1420       __ z_bre(done);
1421       __ z_lghi(dreg,  1);     // gt value
1422       __ z_brh(done);
1423       __ z_lghi(dreg, -1);     // lt value
1424     }
1425   }
1426   __ bind(done);
1427 }
1428 
1429 // result = condition ? opr1 : opr2
1430 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1431                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1432   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390");
1433 
1434   Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1435   switch (condition) {
1436     case lir_cond_equal:        acond = Assembler::bcondEqual;    ncond = Assembler::bcondNotEqual; break;
1437     case lir_cond_notEqual:     acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual;    break;
1438     case lir_cond_less:         acond = Assembler::bcondLow;      ncond = Assembler::bcondNotLow;   break;
1439     case lir_cond_lessEqual:    acond = Assembler::bcondNotHigh;  ncond = Assembler::bcondHigh;     break;
1440     case lir_cond_greaterEqual: acond = Assembler::bcondNotLow;   ncond = Assembler::bcondLow;      break;
1441     case lir_cond_greater:      acond = Assembler::bcondHigh;     ncond = Assembler::bcondNotHigh;  break;
1442     case lir_cond_belowEqual:   acond = Assembler::bcondNotHigh;  ncond = Assembler::bcondHigh;     break;
1443     case lir_cond_aboveEqual:   acond = Assembler::bcondNotLow;   ncond = Assembler::bcondLow;      break;
1444     default:                    ShouldNotReachHere();
1445   }
1446 
1447   if (opr1->is_cpu_register()) {
1448     reg2reg(opr1, result);
1449   } else if (opr1->is_stack()) {
1450     stack2reg(opr1, result, result->type());
1451   } else if (opr1->is_constant()) {
1452     const2reg(opr1, result, lir_patch_none, NULL);
1453   } else {
1454     ShouldNotReachHere();
1455   }
1456 
1457   if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1458     // Optimized version that does not require a branch.
1459     if (opr2->is_single_cpu()) {
1460       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1461       __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1462     } else if (opr2->is_double_cpu()) {
1463       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1464       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1465       __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1466     } else if (opr2->is_single_stack()) {
1467       __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1468     } else if (opr2->is_double_stack()) {
1469       __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1470     } else {
1471       ShouldNotReachHere();
1472     }
1473   } else {
1474     Label skip;
1475     __ z_brc(acond, skip);
1476     if (opr2->is_cpu_register()) {
1477       reg2reg(opr2, result);
1478     } else if (opr2->is_stack()) {
1479       stack2reg(opr2, result, result->type());
1480     } else if (opr2->is_constant()) {
1481       const2reg(opr2, result, lir_patch_none, NULL);
1482     } else {
1483       ShouldNotReachHere();
1484     }
1485     __ bind(skip);
1486   }
1487 }
1488 
1489 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1490                              CodeEmitInfo* info, bool pop_fpu_stack) {
1491   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1492 
1493   if (left->is_single_cpu()) {
1494     assert(left == dest, "left and dest must be equal");
1495     Register lreg = left->as_register();
1496 
1497     if (right->is_single_cpu()) {
1498       // cpu register - cpu register
1499       Register rreg = right->as_register();
1500       switch (code) {
1501         case lir_add: __ z_ar (lreg, rreg); break;
1502         case lir_sub: __ z_sr (lreg, rreg); break;
1503         case lir_mul: __ z_msr(lreg, rreg); break;
1504         default: ShouldNotReachHere();
1505       }
1506 
1507     } else if (right->is_stack()) {
1508       // cpu register - stack
1509       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1510       switch (code) {
1511         case lir_add: __ z_ay(lreg, raddr); break;
1512         case lir_sub: __ z_sy(lreg, raddr); break;
1513         default: ShouldNotReachHere();
1514       }
1515 
1516     } else if (right->is_constant()) {
1517       // cpu register - constant
1518       jint c = right->as_constant_ptr()->as_jint();
1519       switch (code) {
1520         case lir_add: __ z_agfi(lreg, c);  break;
1521         case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
1522         case lir_mul: __ z_msfi(lreg, c);  break;
1523         default: ShouldNotReachHere();
1524       }
1525 
1526     } else {
1527       ShouldNotReachHere();
1528     }
1529 
1530   } else if (left->is_double_cpu()) {
1531     assert(left == dest, "left and dest must be equal");
1532     Register lreg_lo = left->as_register_lo();
1533     Register lreg_hi = left->as_register_hi();
1534 
1535     if (right->is_double_cpu()) {
1536       // cpu register - cpu register
1537       Register rreg_lo = right->as_register_lo();
1538       Register rreg_hi = right->as_register_hi();
1539       assert_different_registers(lreg_lo, rreg_lo);
1540       switch (code) {
1541         case lir_add:
1542           __ z_agr(lreg_lo, rreg_lo);
1543           break;
1544         case lir_sub:
1545           __ z_sgr(lreg_lo, rreg_lo);
1546           break;
1547         case lir_mul:
1548           __ z_msgr(lreg_lo, rreg_lo);
1549           break;
1550         default:
1551           ShouldNotReachHere();
1552       }
1553 
1554     } else if (right->is_constant()) {
1555       // cpu register - constant
1556       jlong c = right->as_constant_ptr()->as_jlong_bits();
1557       switch (code) {
1558         case lir_add: __ z_agfi(lreg_lo, c); break;
1559         case lir_sub:
1560           if (c != min_jint) {
1561                       __ z_agfi(lreg_lo, -c);
1562           } else {
1563             // -min_jint cannot be represented as simm32 in z_agfi
1564             // min_jint sign extended:      0xffffffff80000000
1565             // -min_jint as 64 bit integer: 0x0000000080000000
1566             // 0x80000000 can be represented as uimm32 in z_algfi
1567             // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1568                       __ z_algfi(lreg_lo, UCONST64(0x80000000));
1569           }
1570           break;
1571         case lir_mul: __ z_msgfi(lreg_lo, c); break;
1572         default:
1573           ShouldNotReachHere();
1574       }
1575 
1576     } else {
1577       ShouldNotReachHere();
1578     }
1579 
1580   } else if (left->is_single_fpu()) {
1581     assert(left == dest, "left and dest must be equal");
1582     FloatRegister lreg = left->as_float_reg();
1583     FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1584     Address raddr;
1585 
1586     if (rreg == fnoreg) {
1587       assert(right->is_single_stack(), "constants should be loaded into register");
1588       raddr = frame_map()->address_for_slot(right->single_stack_ix());
1589       if (!Immediate::is_uimm12(raddr.disp())) {
1590         __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1591       }
1592     }
1593 
1594     if (rreg != fnoreg) {
1595       switch (code) {
1596         case lir_add: __ z_aebr(lreg, rreg);  break;
1597         case lir_sub: __ z_sebr(lreg, rreg);  break;
1598         case lir_mul: __ z_meebr(lreg, rreg); break;
1599         case lir_div: __ z_debr(lreg, rreg);  break;
1600         default: ShouldNotReachHere();
1601       }
1602     } else {
1603       switch (code) {
1604         case lir_add: __ z_aeb(lreg, raddr);  break;
1605         case lir_sub: __ z_seb(lreg, raddr);  break;
1606         case lir_mul: __ z_meeb(lreg, raddr);  break;
1607         case lir_div: __ z_deb(lreg, raddr);  break;
1608         default: ShouldNotReachHere();
1609       }
1610     }
1611   } else if (left->is_double_fpu()) {
1612     assert(left == dest, "left and dest must be equal");
1613     FloatRegister lreg = left->as_double_reg();
1614     FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1615     Address raddr;
1616 
1617     if (rreg == fnoreg) {
1618       assert(right->is_double_stack(), "constants should be loaded into register");
1619       raddr = frame_map()->address_for_slot(right->double_stack_ix());
1620       if (!Immediate::is_uimm12(raddr.disp())) {
1621         __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1622       }
1623     }
1624 
1625     if (rreg != fnoreg) {
1626       switch (code) {
1627         case lir_add: __ z_adbr(lreg, rreg); break;
1628         case lir_sub: __ z_sdbr(lreg, rreg); break;
1629         case lir_mul: __ z_mdbr(lreg, rreg); break;
1630         case lir_div: __ z_ddbr(lreg, rreg); break;
1631         default: ShouldNotReachHere();
1632       }
1633     } else {
1634       switch (code) {
1635         case lir_add: __ z_adb(lreg, raddr); break;
1636         case lir_sub: __ z_sdb(lreg, raddr); break;
1637         case lir_mul: __ z_mdb(lreg, raddr); break;
1638         case lir_div: __ z_ddb(lreg, raddr); break;
1639         default: ShouldNotReachHere();
1640       }
1641     }
1642   } else if (left->is_address()) {
1643     assert(left == dest, "left and dest must be equal");
1644     assert(code == lir_add, "unsupported operation");
1645     assert(right->is_constant(), "unsupported operand");
1646     jint c = right->as_constant_ptr()->as_jint();
1647     LIR_Address* lir_addr = left->as_address_ptr();
1648     Address addr = as_Address(lir_addr);
1649     switch (lir_addr->type()) {
1650       case T_INT:
1651         __ add2mem_32(addr, c, Z_R1_scratch);
1652         break;
1653       case T_LONG:
1654         __ add2mem_64(addr, c, Z_R1_scratch);
1655         break;
1656       default:
1657         ShouldNotReachHere();
1658     }
1659   } else {
1660     ShouldNotReachHere();
1661   }
1662 }
1663 
1664 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1665   switch (code) {
1666     case lir_sqrt: {
1667       assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1668       FloatRegister src_reg = value->as_double_reg();
1669       FloatRegister dst_reg = dest->as_double_reg();
1670       __ z_sqdbr(dst_reg, src_reg);
1671       break;
1672     }
1673     case lir_abs: {
1674       assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1675       FloatRegister src_reg = value->as_double_reg();
1676       FloatRegister dst_reg = dest->as_double_reg();
1677       __ z_lpdbr(dst_reg, src_reg);
1678       break;
1679     }
1680     default: {
1681       ShouldNotReachHere();
1682       break;
1683     }
1684   }
1685 }
1686 
1687 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1688   if (left->is_single_cpu()) {
1689     Register reg = left->as_register();
1690     if (right->is_constant()) {
1691       int val = right->as_constant_ptr()->as_jint();
1692       switch (code) {
1693         case lir_logic_and: __ z_nilf(reg, val); break;
1694         case lir_logic_or:  __ z_oilf(reg, val); break;
1695         case lir_logic_xor: __ z_xilf(reg, val); break;
1696         default: ShouldNotReachHere();
1697       }
1698     } else if (right->is_stack()) {
1699       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1700       switch (code) {
1701         case lir_logic_and: __ z_ny(reg, raddr); break;
1702         case lir_logic_or:  __ z_oy(reg, raddr); break;
1703         case lir_logic_xor: __ z_xy(reg, raddr); break;
1704         default: ShouldNotReachHere();
1705       }
1706     } else {
1707       Register rright = right->as_register();
1708       switch (code) {
1709         case lir_logic_and: __ z_nr(reg, rright); break;
1710         case lir_logic_or : __ z_or(reg, rright); break;
1711         case lir_logic_xor: __ z_xr(reg, rright); break;
1712         default: ShouldNotReachHere();
1713       }
1714     }
1715     move_regs(reg, dst->as_register());
1716   } else {
1717     Register l_lo = left->as_register_lo();
1718     if (right->is_constant()) {
1719       __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1720       switch (code) {
1721         case lir_logic_and:
1722           __ z_ngr(l_lo, Z_R1_scratch);
1723           break;
1724         case lir_logic_or:
1725           __ z_ogr(l_lo, Z_R1_scratch);
1726           break;
1727         case lir_logic_xor:
1728           __ z_xgr(l_lo, Z_R1_scratch);
1729           break;
1730         default: ShouldNotReachHere();
1731       }
1732     } else {
1733       Register r_lo;
1734       if (is_reference_type(right->type())) {
1735         r_lo = right->as_register();
1736       } else {
1737         r_lo = right->as_register_lo();
1738       }
1739       switch (code) {
1740         case lir_logic_and:
1741           __ z_ngr(l_lo, r_lo);
1742           break;
1743         case lir_logic_or:
1744           __ z_ogr(l_lo, r_lo);
1745           break;
1746         case lir_logic_xor:
1747           __ z_xgr(l_lo, r_lo);
1748           break;
1749         default: ShouldNotReachHere();
1750       }
1751     }
1752 
1753     Register dst_lo = dst->as_register_lo();
1754 
1755     move_regs(l_lo, dst_lo);
1756   }
1757 }
1758 
1759 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1760 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1761   if (left->is_double_cpu()) {
1762     // 64 bit integer case
1763     assert(left->is_double_cpu(), "left must be register");
1764     assert(right->is_double_cpu() || is_power_of_2(right->as_jlong()),
1765            "right must be register or power of 2 constant");
1766     assert(result->is_double_cpu(), "result must be register");
1767 
1768     Register lreg = left->as_register_lo();
1769     Register dreg = result->as_register_lo();
1770 
1771     if (right->is_constant()) {
1772       // Convert division by a power of two into some shifts and logical operations.
1773       Register treg1 = Z_R0_scratch;
1774       Register treg2 = Z_R1_scratch;
1775       jlong divisor = right->as_jlong();
1776       jlong log_divisor = log2i_exact(right->as_jlong());
1777 
1778       if (divisor == min_jlong) {
1779         // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1780         if (dreg == lreg) {
1781           NearLabel done;
1782           __ load_const_optimized(treg2, min_jlong);
1783           __ z_cgr(lreg, treg2);
1784           __ z_lghi(dreg, 0);           // Preserves condition code.
1785           __ z_brne(done);
1786           __ z_lghi(dreg, 1);           // min_jlong / min_jlong = 1
1787           __ bind(done);
1788         } else {
1789           assert_different_registers(dreg, lreg);
1790           NearLabel done;
1791           __ z_lghi(dreg, 0);
1792           __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1793           __ z_lghi(dreg, 1);
1794           __ bind(done);
1795         }
1796         return;
1797       }
1798       __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1799       if (divisor == 2) {
1800         __ z_srlg(treg2, dreg, 63);     // dividend < 0 ? 1 : 0
1801       } else {
1802         __ z_srag(treg2, dreg, 63);     // dividend < 0 ? -1 : 0
1803         __ and_imm(treg2, divisor - 1, treg1, true);
1804       }
1805       if (code == lir_idiv) {
1806         __ z_agr(dreg, treg2);
1807         __ z_srag(dreg, dreg, log_divisor);
1808       } else {
1809         assert(code == lir_irem, "check");
1810         __ z_agr(treg2, dreg);
1811         __ and_imm(treg2, ~(divisor - 1), treg1, true);
1812         __ z_sgr(dreg, treg2);
1813       }
1814       return;
1815     }
1816 
1817     // Divisor is not a power of 2 constant.
1818     Register rreg = right->as_register_lo();
1819     Register treg = temp->as_register_lo();
1820     assert(right->is_double_cpu(), "right must be register");
1821     assert(lreg == Z_R11, "see ldivInOpr()");
1822     assert(rreg != lreg, "right register must not be same as left register");
1823     assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1824            (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1825 
1826     Register R1 = lreg->predecessor();
1827     Register R2 = rreg;
1828     assert(code != lir_idiv || lreg==dreg, "see code below");
1829     if (code == lir_idiv) {
1830       __ z_lcgr(lreg, lreg);
1831     } else {
1832       __ clear_reg(dreg, true, false);
1833     }
1834     NearLabel done;
1835     __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1836     if (code == lir_idiv) {
1837       __ z_lcgr(lreg, lreg); // Revert lcgr above.
1838     }
1839     if (ImplicitDiv0Checks) {
1840       // No debug info because the idiv won't trap.
1841       // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1842       // which is unnecessary, too.
1843       add_debug_info_for_div0(__ offset(), info);
1844     }
1845     __ z_dsgr(R1, R2);
1846     __ bind(done);
1847     return;
1848   }
1849 
1850   // 32 bit integer case
1851 
1852   assert(left->is_single_cpu(), "left must be register");
1853   assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1854   assert(result->is_single_cpu(), "result must be register");
1855 
1856   Register lreg = left->as_register();
1857   Register dreg = result->as_register();
1858 
1859   if (right->is_constant()) {
1860     // Convert division by a power of two into some shifts and logical operations.
1861     Register treg1 = Z_R0_scratch;
1862     Register treg2 = Z_R1_scratch;
1863     jlong divisor = right->as_jint();
1864     jlong log_divisor = log2i_exact(right->as_jint());
1865     __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1866     if (divisor == 2) {
1867       __ z_srlg(treg2, dreg, 63);     // dividend < 0 ?  1 : 0
1868     } else {
1869       __ z_srag(treg2, dreg, 63);     // dividend < 0 ? -1 : 0
1870       __ and_imm(treg2, divisor - 1, treg1, true);
1871     }
1872     if (code == lir_idiv) {
1873       __ z_agr(dreg, treg2);
1874       __ z_srag(dreg, dreg, log_divisor);
1875     } else {
1876       assert(code == lir_irem, "check");
1877       __ z_agr(treg2, dreg);
1878       __ and_imm(treg2, ~(divisor - 1), treg1, true);
1879       __ z_sgr(dreg, treg2);
1880     }
1881     return;
1882   }
1883 
1884   // Divisor is not a power of 2 constant.
1885   Register rreg = right->as_register();
1886   Register treg = temp->as_register();
1887   assert(right->is_single_cpu(), "right must be register");
1888   assert(lreg == Z_R11, "left register must be rax,");
1889   assert(rreg != lreg, "right register must not be same as left register");
1890   assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1891       || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1892 
1893   Register R1 = lreg->predecessor();
1894   Register R2 = rreg;
1895   __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1896   if (ImplicitDiv0Checks) {
1897     // No debug info because the idiv won't trap.
1898     // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1899     // which is unnecessary, too.
1900     add_debug_info_for_div0(__ offset(), info);
1901   }
1902   __ z_dsgfr(R1, R2);
1903 }
1904 
1905 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1906   assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1907   assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1908 
1909   // Exception object is not added to oop map by LinearScan
1910   // (LinearScan assumes that no oops are in fixed registers).
1911   info->add_register_oop(exceptionOop);
1912 
1913   // Reuse the debug info from the safepoint poll for the throw op itself.
1914   __ get_PC(Z_EXC_PC);
1915   add_call_info(__ offset(), info); // for exception handler
1916   address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1917                                                                     : Runtime1::handle_exception_nofpu_id);
1918   emit_call_c(stub);
1919 }
1920 
1921 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1922   assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1923 
1924   __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1925 }
1926 
1927 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1928   ciArrayKlass* default_type = op->expected_type();
1929   Register src = op->src()->as_register();
1930   Register dst = op->dst()->as_register();
1931   Register src_pos = op->src_pos()->as_register();
1932   Register dst_pos = op->dst_pos()->as_register();
1933   Register length  = op->length()->as_register();
1934   Register tmp = op->tmp()->as_register();
1935 
1936   CodeStub* stub = op->stub();
1937   int flags = op->flags();
1938   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1939   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1940 
1941   // If we don't know anything, just go through the generic arraycopy.
1942   if (default_type == NULL) {
1943     address copyfunc_addr = StubRoutines::generic_arraycopy();
1944 
1945     if (copyfunc_addr == NULL) {
1946       // Take a slow path for generic arraycopy.
1947       __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1948       __ bind(*stub->continuation());
1949       return;
1950     }
1951 
1952     // Save outgoing arguments in callee saved registers (C convention) in case
1953     // a call to System.arraycopy is needed.
1954     Register callee_saved_src     = Z_R10;
1955     Register callee_saved_src_pos = Z_R11;
1956     Register callee_saved_dst     = Z_R12;
1957     Register callee_saved_dst_pos = Z_R13;
1958     Register callee_saved_length  = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1959 
1960     __ lgr_if_needed(callee_saved_src, src);
1961     __ lgr_if_needed(callee_saved_src_pos, src_pos);
1962     __ lgr_if_needed(callee_saved_dst, dst);
1963     __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1964     __ lgr_if_needed(callee_saved_length, length);
1965 
1966     // C function requires 64 bit values.
1967     __ z_lgfr(src_pos, src_pos);
1968     __ z_lgfr(dst_pos, dst_pos);
1969     __ z_lgfr(length, length);
1970 
1971     // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
1972 
1973     // The arguments are in the corresponding registers.
1974     assert(Z_ARG1 == src,     "assumption");
1975     assert(Z_ARG2 == src_pos, "assumption");
1976     assert(Z_ARG3 == dst,     "assumption");
1977     assert(Z_ARG4 == dst_pos, "assumption");
1978     assert(Z_ARG5 == length,  "assumption");
1979 #ifndef PRODUCT
1980     if (PrintC1Statistics) {
1981       __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
1982       __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
1983     }
1984 #endif
1985     emit_call_c(copyfunc_addr);
1986     CHECK_BAILOUT();
1987 
1988     __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
1989 
1990     __ z_lgr(tmp, Z_RET);
1991     __ z_xilf(tmp, -1);
1992 
1993     // Restore values from callee saved registers so they are where the stub
1994     // expects them.
1995     __ lgr_if_needed(src, callee_saved_src);
1996     __ lgr_if_needed(src_pos, callee_saved_src_pos);
1997     __ lgr_if_needed(dst, callee_saved_dst);
1998     __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
1999     __ lgr_if_needed(length, callee_saved_length);
2000 
2001     __ z_sr(length, tmp);
2002     __ z_ar(src_pos, tmp);
2003     __ z_ar(dst_pos, tmp);
2004     __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2005 
2006     __ bind(*stub->continuation());
2007     return;
2008   }
2009 
2010   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2011 
2012   int elem_size = type2aelembytes(basic_type);
2013   int shift_amount;
2014 
2015   switch (elem_size) {
2016     case 1 :
2017       shift_amount = 0;
2018       break;
2019     case 2 :
2020       shift_amount = 1;
2021       break;
2022     case 4 :
2023       shift_amount = 2;
2024       break;
2025     case 8 :
2026       shift_amount = 3;
2027       break;
2028     default:
2029       shift_amount = -1;
2030       ShouldNotReachHere();
2031   }
2032 
2033   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2034   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2035   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2036   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2037 
2038   // Length and pos's are all sign extended at this point on 64bit.
2039 
2040   // test for NULL
2041   if (flags & LIR_OpArrayCopy::src_null_check) {
2042     __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2043   }
2044   if (flags & LIR_OpArrayCopy::dst_null_check) {
2045     __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2046   }
2047 
2048   // Check if negative.
2049   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2050     __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2051   }
2052   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2053     __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2054   }
2055 
2056   // If the compiler was not able to prove that exact type of the source or the destination
2057   // of the arraycopy is an array type, check at runtime if the source or the destination is
2058   // an instance type.
2059   if (flags & LIR_OpArrayCopy::type_check) {
2060     assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2061 
2062     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2063       __ load_klass(tmp, dst);
2064       __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2065       __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2066     }
2067 
2068     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2069       __ load_klass(tmp, src);
2070       __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2071       __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2072     }
2073   }
2074 
2075   if (flags & LIR_OpArrayCopy::src_range_check) {
2076     __ z_la(tmp, Address(src_pos, length));
2077     __ z_cl(tmp, src_length_addr);
2078     __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2079   }
2080   if (flags & LIR_OpArrayCopy::dst_range_check) {
2081     __ z_la(tmp, Address(dst_pos, length));
2082     __ z_cl(tmp, dst_length_addr);
2083     __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2084   }
2085 
2086   if (flags & LIR_OpArrayCopy::length_positive_check) {
2087     __ z_ltr(length, length);
2088     __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2089   }
2090 
2091   // Stubs require 64 bit values.
2092   __ z_lgfr(src_pos, src_pos); // int -> long
2093   __ z_lgfr(dst_pos, dst_pos); // int -> long
2094   __ z_lgfr(length, length);   // int -> long
2095 
2096   if (flags & LIR_OpArrayCopy::type_check) {
2097     // We don't know the array types are compatible.
2098     if (basic_type != T_OBJECT) {
2099       // Simple test for basic type arrays.
2100       if (UseCompressedClassPointers) {
2101         __ z_l(tmp, src_klass_addr);
2102         __ z_c(tmp, dst_klass_addr);
2103       } else {
2104         __ z_lg(tmp, src_klass_addr);
2105         __ z_cg(tmp, dst_klass_addr);
2106       }
2107       __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2108     } else {
2109       // For object arrays, if src is a sub class of dst then we can
2110       // safely do the copy.
2111       NearLabel cont, slow;
2112       Register src_klass = Z_R1_scratch;
2113       Register dst_klass = Z_R10;
2114 
2115       __ load_klass(src_klass, src);
2116       __ load_klass(dst_klass, dst);
2117 
2118       __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL);
2119 
2120       store_parameter(src_klass, 0); // sub
2121       store_parameter(dst_klass, 1); // super
2122       emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id));
2123       CHECK_BAILOUT2(cont, slow);
2124       // Sets condition code 0 for match (2 otherwise).
2125       __ branch_optimized(Assembler::bcondEqual, cont);
2126 
2127       __ bind(slow);
2128 
2129       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2130       if (copyfunc_addr != NULL) { // use stub if available
2131         // Src is not a sub class of dst so we have to do a
2132         // per-element check.
2133 
2134         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2135         if ((flags & mask) != mask) {
2136           // Check that at least both of them object arrays.
2137           assert(flags & mask, "one of the two should be known to be an object array");
2138 
2139           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2140             __ load_klass(tmp, src);
2141           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2142             __ load_klass(tmp, dst);
2143           }
2144           Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2145           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2146           __ load_const_optimized(Z_R1_scratch, objArray_lh);
2147           __ z_c(Z_R1_scratch, klass_lh_addr);
2148           __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2149         }
2150 
2151         // Save outgoing arguments in callee saved registers (C convention) in case
2152         // a call to System.arraycopy is needed.
2153         Register callee_saved_src     = Z_R10;
2154         Register callee_saved_src_pos = Z_R11;
2155         Register callee_saved_dst     = Z_R12;
2156         Register callee_saved_dst_pos = Z_R13;
2157         Register callee_saved_length  = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2158 
2159         __ lgr_if_needed(callee_saved_src, src);
2160         __ lgr_if_needed(callee_saved_src_pos, src_pos);
2161         __ lgr_if_needed(callee_saved_dst, dst);
2162         __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2163         __ lgr_if_needed(callee_saved_length, length);
2164 
2165         __ z_llgfr(length, length); // Higher 32bits must be null.
2166 
2167         __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2168         __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2169 
2170         __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2171         assert_different_registers(Z_ARG1, dst, dst_pos, length);
2172         __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2173         assert_different_registers(Z_ARG2, dst, length);
2174 
2175         __ z_lgr(Z_ARG3, length);
2176         assert_different_registers(Z_ARG3, dst);
2177 
2178         __ load_klass(Z_ARG5, dst);
2179         __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2180         __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2181         emit_call_c(copyfunc_addr);
2182         CHECK_BAILOUT2(cont, slow);
2183 
2184 #ifndef PRODUCT
2185         if (PrintC1Statistics) {
2186           NearLabel failed;
2187           __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2188           __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2189           __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2190           __ bind(failed);
2191         }
2192 #endif
2193 
2194         __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2195 
2196 #ifndef PRODUCT
2197         if (PrintC1Statistics) {
2198           __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2199           __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2200         }
2201 #endif
2202 
2203         __ z_lgr(tmp, Z_RET);
2204         __ z_xilf(tmp, -1);
2205 
2206         // Restore previously spilled arguments
2207         __ lgr_if_needed(src, callee_saved_src);
2208         __ lgr_if_needed(src_pos, callee_saved_src_pos);
2209         __ lgr_if_needed(dst, callee_saved_dst);
2210         __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2211         __ lgr_if_needed(length, callee_saved_length);
2212 
2213         __ z_sr(length, tmp);
2214         __ z_ar(src_pos, tmp);
2215         __ z_ar(dst_pos, tmp);
2216       }
2217 
2218       __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2219 
2220       __ bind(cont);
2221     }
2222   }
2223 
2224 #ifdef ASSERT
2225   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2226     // Sanity check the known type with the incoming class. For the
2227     // primitive case the types must match exactly with src.klass and
2228     // dst.klass each exactly matching the default type. For the
2229     // object array case, if no type check is needed then either the
2230     // dst type is exactly the expected type and the src type is a
2231     // subtype which we can't check or src is the same array as dst
2232     // but not necessarily exactly of type default_type.
2233     NearLabel known_ok, halt;
2234     metadata2reg(default_type->constant_encoding(), tmp);
2235     if (UseCompressedClassPointers) {
2236       __ encode_klass_not_null(tmp);
2237     }
2238 
2239     if (basic_type != T_OBJECT) {
2240       if (UseCompressedClassPointers)         { __ z_c (tmp, dst_klass_addr); }
2241       else                                    { __ z_cg(tmp, dst_klass_addr); }
2242       __ branch_optimized(Assembler::bcondNotEqual, halt);
2243       if (UseCompressedClassPointers)         { __ z_c (tmp, src_klass_addr); }
2244       else                                    { __ z_cg(tmp, src_klass_addr); }
2245       __ branch_optimized(Assembler::bcondEqual, known_ok);
2246     } else {
2247       if (UseCompressedClassPointers)         { __ z_c (tmp, dst_klass_addr); }
2248       else                                    { __ z_cg(tmp, dst_klass_addr); }
2249       __ branch_optimized(Assembler::bcondEqual, known_ok);
2250       __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2251     }
2252     __ bind(halt);
2253     __ stop("incorrect type information in arraycopy");
2254     __ bind(known_ok);
2255   }
2256 #endif
2257 
2258 #ifndef PRODUCT
2259   if (PrintC1Statistics) {
2260     __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2261     __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2262   }
2263 #endif
2264 
2265   __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2266   __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2267 
2268   assert_different_registers(Z_ARG1, dst, dst_pos, length);
2269   __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2270   assert_different_registers(Z_ARG2, length);
2271   __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2272   __ lgr_if_needed(Z_ARG3, length);
2273 
2274   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2275   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2276   const char *name;
2277   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2278   __ call_VM_leaf(entry);
2279 
2280   __ bind(*stub->continuation());
2281 }
2282 
2283 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2284   if (dest->is_single_cpu()) {
2285     if (left->type() == T_OBJECT) {
2286       switch (code) {
2287         case lir_shl:  __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2288         case lir_shr:  __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2289         case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2290         default: ShouldNotReachHere();
2291       }
2292     } else {
2293       assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2294       Register masked_count = Z_R1_scratch;
2295       __ z_lr(masked_count, count->as_register());
2296       __ z_nill(masked_count, 31);
2297       switch (code) {
2298         case lir_shl:  __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2299         case lir_shr:  __ z_sra  (dest->as_register(), 0, masked_count); break;
2300         case lir_ushr: __ z_srl  (dest->as_register(), 0, masked_count); break;
2301         default: ShouldNotReachHere();
2302       }
2303     }
2304   } else {
2305     switch (code) {
2306       case lir_shl:  __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2307       case lir_shr:  __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2308       case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2309       default: ShouldNotReachHere();
2310     }
2311   }
2312 }
2313 
2314 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2315   if (left->type() == T_OBJECT) {
2316     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2317     Register l = left->as_register();
2318     Register d = dest->as_register_lo();
2319     switch (code) {
2320       case lir_shl:  __ z_sllg (d, l, count); break;
2321       case lir_shr:  __ z_srag (d, l, count); break;
2322       case lir_ushr: __ z_srlg (d, l, count); break;
2323       default: ShouldNotReachHere();
2324     }
2325     return;
2326   }
2327   if (dest->is_single_cpu()) {
2328     assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2329     count = count & 0x1F; // Java spec
2330     switch (code) {
2331       case lir_shl:  __ z_sllg (dest->as_register(), left->as_register(), count); break;
2332       case lir_shr:  __ z_sra  (dest->as_register(), count); break;
2333       case lir_ushr: __ z_srl  (dest->as_register(), count); break;
2334       default: ShouldNotReachHere();
2335     }
2336   } else if (dest->is_double_cpu()) {
2337     count = count & 63; // Java spec
2338     Register l = left->as_pointer_register();
2339     Register d = dest->as_pointer_register();
2340     switch (code) {
2341       case lir_shl:  __ z_sllg (d, l, count); break;
2342       case lir_shr:  __ z_srag (d, l, count); break;
2343       case lir_ushr: __ z_srlg (d, l, count); break;
2344       default: ShouldNotReachHere();
2345     }
2346   } else {
2347     ShouldNotReachHere();
2348   }
2349 }
2350 
2351 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2352   if (op->init_check()) {
2353     // Make sure klass is initialized & doesn't have finalizer.
2354     const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2355     Register iklass = op->klass()->as_register();
2356     add_debug_info_for_null_check_here(op->stub()->info());
2357     if (Immediate::is_uimm12(state_offset)) {
2358       __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2359     } else {
2360       __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2361     }
2362     __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2363   }
2364   __ allocate_object(op->obj()->as_register(),
2365                      op->tmp1()->as_register(),
2366                      op->tmp2()->as_register(),
2367                      op->header_size(),
2368                      op->object_size(),
2369                      op->klass()->as_register(),
2370                      *op->stub()->entry());
2371   __ bind(*op->stub()->continuation());
2372   __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2373 }
2374 
2375 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2376   Register len = op->len()->as_register();
2377   __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2378 
2379   if (UseSlowPath ||
2380       (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2381       (!UseFastNewTypeArray   && (!is_reference_type(op->type())))) {
2382     __ z_brul(*op->stub()->entry());
2383   } else {
2384     __ allocate_array(op->obj()->as_register(),
2385                       op->len()->as_register(),
2386                       op->tmp1()->as_register(),
2387                       op->tmp2()->as_register(),
2388                       arrayOopDesc::header_size(op->type()),
2389                       type2aelembytes(op->type()),
2390                       op->klass()->as_register(),
2391                       *op->stub()->entry());
2392   }
2393   __ bind(*op->stub()->continuation());
2394 }
2395 
2396 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2397                                         Register recv, Register tmp1, Label* update_done) {
2398   uint i;
2399   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2400     Label next_test;
2401     // See if the receiver is receiver[n].
2402     Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2403     __ z_cg(recv, receiver_addr);
2404     __ z_brne(next_test);
2405     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2406     __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2407     __ branch_optimized(Assembler::bcondAlways, *update_done);
2408     __ bind(next_test);
2409   }
2410 
2411   // Didn't find receiver; find next empty slot and fill it in.
2412   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2413     Label next_test;
2414     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2415     __ z_ltg(Z_R0_scratch, recv_addr);
2416     __ z_brne(next_test);
2417     __ z_stg(recv, recv_addr);
2418     __ load_const_optimized(tmp1, DataLayout::counter_increment);
2419     __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2420     __ branch_optimized(Assembler::bcondAlways, *update_done);
2421     __ bind(next_test);
2422   }
2423 }
2424 
2425 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2426                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2427   Unimplemented();
2428 }
2429 
2430 void LIR_Assembler::store_parameter(Register r, int param_num) {
2431   assert(param_num >= 0, "invalid num");
2432   int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2433   assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2434   __ z_stg(r, offset_in_bytes, Z_SP);
2435 }
2436 
2437 void LIR_Assembler::store_parameter(jint c, int param_num) {
2438   assert(param_num >= 0, "invalid num");
2439   int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2440   assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2441   __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2442 }
2443 
2444 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2445   // We always need a stub for the failure case.
2446   CodeStub* stub = op->stub();
2447   Register obj = op->object()->as_register();
2448   Register k_RInfo = op->tmp1()->as_register();
2449   Register klass_RInfo = op->tmp2()->as_register();
2450   Register dst = op->result_opr()->as_register();
2451   Register Rtmp1 = Z_R1_scratch;
2452   ciKlass* k = op->klass();
2453 
2454   assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2455 
2456   // Check if it needs to be profiled.
2457   ciMethodData* md = NULL;
2458   ciProfileData* data = NULL;
2459 
2460   if (op->should_profile()) {
2461     ciMethod* method = op->profiled_method();
2462     assert(method != NULL, "Should have method");
2463     int bci = op->profiled_bci();
2464     md = method->method_data_or_null();
2465     assert(md != NULL, "Sanity");
2466     data = md->bci_to_data(bci);
2467     assert(data != NULL,                "need data for type check");
2468     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2469   }
2470 
2471   // Temp operands do not overlap with inputs, if this is their last
2472   // use (end of range is exclusive), so a register conflict is possible.
2473   if (obj == k_RInfo) {
2474     k_RInfo = dst;
2475   } else if (obj == klass_RInfo) {
2476     klass_RInfo = dst;
2477   }
2478   assert_different_registers(obj, k_RInfo, klass_RInfo);
2479 
2480   if (op->should_profile()) {
2481     NearLabel not_null;
2482     __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2483     // Object is null; update MDO and exit.
2484     Register mdo = klass_RInfo;
2485     metadata2reg(md->constant_encoding(), mdo);
2486     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2487     int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2488     __ or2mem_8(data_addr, header_bits);
2489     __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2490     __ bind(not_null);
2491   } else {
2492     __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2493   }
2494 
2495   NearLabel profile_cast_failure, profile_cast_success;
2496   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2497   Label *success_target = op->should_profile() ? &profile_cast_success : success;
2498 
2499   // Patching may screw with our temporaries,
2500   // so let's do it before loading the class.
2501   if (k->is_loaded()) {
2502     metadata2reg(k->constant_encoding(), k_RInfo);
2503   } else {
2504     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2505   }
2506   assert(obj != k_RInfo, "must be different");
2507 
2508   __ verify_oop(obj, FILE_AND_LINE);
2509 
2510   // Get object class.
2511   // Not a safepoint as obj null check happens earlier.
2512   if (op->fast_check()) {
2513     if (UseCompressedClassPointers) {
2514       __ load_klass(klass_RInfo, obj);
2515       __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2516     } else {
2517       __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2518       __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2519     }
2520     // Successful cast, fall through to profile or jump.
2521   } else {
2522     bool need_slow_path = !k->is_loaded() ||
2523                           ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2524     intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L;
2525     __ load_klass(klass_RInfo, obj);
2526     // Perform the fast part of the checking logic.
2527     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2528                                      (need_slow_path ? success_target : NULL),
2529                                      failure_target, NULL,
2530                                      RegisterOrConstant(super_check_offset));
2531     if (need_slow_path) {
2532       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2533       address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2534       store_parameter(klass_RInfo, 0); // sub
2535       store_parameter(k_RInfo, 1);     // super
2536       emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2537       CHECK_BAILOUT2(profile_cast_failure, profile_cast_success);
2538       __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2539       // Fall through to success case.
2540     }
2541   }
2542 
2543   if (op->should_profile()) {
2544     Register mdo = klass_RInfo, recv = k_RInfo;
2545     assert_different_registers(obj, mdo, recv);
2546     __ bind(profile_cast_success);
2547     metadata2reg(md->constant_encoding(), mdo);
2548     __ load_klass(recv, obj);
2549     type_profile_helper(mdo, md, data, recv, Rtmp1, success);
2550     __ branch_optimized(Assembler::bcondAlways, *success);
2551 
2552     __ bind(profile_cast_failure);
2553     metadata2reg(md->constant_encoding(), mdo);
2554     __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2555     __ branch_optimized(Assembler::bcondAlways, *failure);
2556   } else {
2557     __ branch_optimized(Assembler::bcondAlways, *success);
2558   }
2559 }
2560 
2561 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2562   LIR_Code code = op->code();
2563   if (code == lir_store_check) {
2564     Register value = op->object()->as_register();
2565     Register array = op->array()->as_register();
2566     Register k_RInfo = op->tmp1()->as_register();
2567     Register klass_RInfo = op->tmp2()->as_register();
2568     Register Rtmp1 = Z_R1_scratch;
2569 
2570     CodeStub* stub = op->stub();
2571 
2572     // Check if it needs to be profiled.
2573     ciMethodData* md = NULL;
2574     ciProfileData* data = NULL;
2575 
2576     assert_different_registers(value, k_RInfo, klass_RInfo);
2577 
2578     if (op->should_profile()) {
2579       ciMethod* method = op->profiled_method();
2580       assert(method != NULL, "Should have method");
2581       int bci = op->profiled_bci();
2582       md = method->method_data_or_null();
2583       assert(md != NULL, "Sanity");
2584       data = md->bci_to_data(bci);
2585       assert(data != NULL,                "need data for type check");
2586       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2587     }
2588     NearLabel profile_cast_success, profile_cast_failure, done;
2589     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2590     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2591 
2592     if (op->should_profile()) {
2593       NearLabel not_null;
2594       __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2595       // Object is null; update MDO and exit.
2596       Register mdo = klass_RInfo;
2597       metadata2reg(md->constant_encoding(), mdo);
2598       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2599       int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2600       __ or2mem_8(data_addr, header_bits);
2601       __ branch_optimized(Assembler::bcondAlways, done);
2602       __ bind(not_null);
2603     } else {
2604       __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2605     }
2606 
2607     add_debug_info_for_null_check_here(op->info_for_exception());
2608     __ load_klass(k_RInfo, array);
2609     __ load_klass(klass_RInfo, value);
2610 
2611     // Get instance klass (it's already uncompressed).
2612     __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2613     // Perform the fast part of the checking logic.
2614     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
2615     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2616     address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2617     store_parameter(klass_RInfo, 0); // sub
2618     store_parameter(k_RInfo, 1);     // super
2619     emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2620     CHECK_BAILOUT3(profile_cast_success, profile_cast_failure, done);
2621     __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2622     // Fall through to success case.
2623 
2624     if (op->should_profile()) {
2625       Register mdo = klass_RInfo, recv = k_RInfo;
2626       assert_different_registers(value, mdo, recv);
2627       __ bind(profile_cast_success);
2628       metadata2reg(md->constant_encoding(), mdo);
2629       __ load_klass(recv, value);
2630       type_profile_helper(mdo, md, data, recv, Rtmp1, &done);
2631       __ branch_optimized(Assembler::bcondAlways, done);
2632 
2633       __ bind(profile_cast_failure);
2634       metadata2reg(md->constant_encoding(), mdo);
2635       __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2636       __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2637     }
2638 
2639     __ bind(done);
2640   } else {
2641     if (code == lir_checkcast) {
2642       Register obj = op->object()->as_register();
2643       Register dst = op->result_opr()->as_register();
2644       NearLabel success;
2645       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2646       __ bind(success);
2647       __ lgr_if_needed(dst, obj);
2648     } else {
2649       if (code == lir_instanceof) {
2650         Register obj = op->object()->as_register();
2651         Register dst = op->result_opr()->as_register();
2652         NearLabel success, failure, done;
2653         emit_typecheck_helper(op, &success, &failure, &failure);
2654         __ bind(failure);
2655         __ clear_reg(dst);
2656         __ branch_optimized(Assembler::bcondAlways, done);
2657         __ bind(success);
2658         __ load_const_optimized(dst, 1);
2659         __ bind(done);
2660       } else {
2661         ShouldNotReachHere();
2662       }
2663     }
2664   }
2665 }
2666 
2667 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2668   Register addr = op->addr()->as_pointer_register();
2669   Register t1_cmp = Z_R1_scratch;
2670   if (op->code() == lir_cas_long) {
2671     assert(VM_Version::supports_cx8(), "wrong machine");
2672     Register cmp_value_lo = op->cmp_value()->as_register_lo();
2673     Register new_value_lo = op->new_value()->as_register_lo();
2674     __ z_lgr(t1_cmp, cmp_value_lo);
2675     // Perform the compare and swap operation.
2676     __ z_csg(t1_cmp, new_value_lo, 0, addr);
2677   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2678     Register cmp_value = op->cmp_value()->as_register();
2679     Register new_value = op->new_value()->as_register();
2680     if (op->code() == lir_cas_obj) {
2681       if (UseCompressedOops) {
2682                  t1_cmp = op->tmp1()->as_register();
2683         Register t2_new = op->tmp2()->as_register();
2684         assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2685         __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2686         __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2687         __ z_cs(t1_cmp, t2_new, 0, addr);
2688       } else {
2689         __ z_lgr(t1_cmp, cmp_value);
2690         __ z_csg(t1_cmp, new_value, 0, addr);
2691       }
2692     } else {
2693       __ z_lr(t1_cmp, cmp_value);
2694       __ z_cs(t1_cmp, new_value, 0, addr);
2695     }
2696   } else {
2697     ShouldNotReachHere(); // new lir_cas_??
2698   }
2699 }
2700 
2701 void LIR_Assembler::breakpoint() {
2702   Unimplemented();
2703   //  __ breakpoint_trap();
2704 }
2705 
2706 void LIR_Assembler::push(LIR_Opr opr) {
2707   ShouldNotCallThis(); // unused
2708 }
2709 
2710 void LIR_Assembler::pop(LIR_Opr opr) {
2711   ShouldNotCallThis(); // unused
2712 }
2713 
2714 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2715   Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2716   __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2717 }
2718 
2719 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2720   Register obj = op->obj_opr()->as_register();  // May not be an oop.
2721   Register hdr = op->hdr_opr()->as_register();
2722   Register lock = op->lock_opr()->as_register();
2723   if (UseHeavyMonitors) {
2724     if (op->info() != NULL) {
2725       add_debug_info_for_null_check_here(op->info());
2726       __ null_check(obj);
2727     }
2728     __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry());
2729   } else if (op->code() == lir_lock) {
2730     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2731     // Add debug info for NullPointerException only if one is possible.
2732     if (op->info() != NULL) {
2733       add_debug_info_for_null_check_here(op->info());
2734     }
2735     __ lock_object(hdr, obj, lock, *op->stub()->entry());
2736     // done
2737   } else if (op->code() == lir_unlock) {
2738     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2739     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2740   } else {
2741     ShouldNotReachHere();
2742   }
2743   __ bind(*op->stub()->continuation());
2744 }
2745 
2746 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2747   Register obj = op->obj()->as_pointer_register();
2748   Register result = op->result_opr()->as_pointer_register();
2749 
2750   CodeEmitInfo* info = op->info();
2751   if (info != NULL) {
2752     add_debug_info_for_null_check_here(info);
2753   }
2754 
2755   if (UseCompressedClassPointers) {
2756     __ z_llgf(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2757     __ decode_klass_not_null(result);
2758   } else {
2759     __ z_lg(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2760   }
2761 }
2762 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2763   ciMethod* method = op->profiled_method();
2764   int bci          = op->profiled_bci();
2765   ciMethod* callee = op->profiled_callee();
2766 
2767   // Update counter for all call types.
2768   ciMethodData* md = method->method_data_or_null();
2769   assert(md != NULL, "Sanity");
2770   ciProfileData* data = md->bci_to_data(bci);
2771   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2772   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2773   Register mdo  = op->mdo()->as_register();
2774   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2775   Register tmp1 = op->tmp1()->as_register_lo();
2776   metadata2reg(md->constant_encoding(), mdo);
2777 
2778   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2779   // Perform additional virtual call profiling for invokevirtual and
2780   // invokeinterface bytecodes
2781   if (op->should_profile_receiver_type()) {
2782     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2783     Register recv = op->recv()->as_register();
2784     assert_different_registers(mdo, tmp1, recv);
2785     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2786     ciKlass* known_klass = op->known_holder();
2787     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2788       // We know the type that will be seen at this call site; we can
2789       // statically update the MethodData* rather than needing to do
2790       // dynamic tests on the receiver type.
2791 
2792       // NOTE: we should probably put a lock around this search to
2793       // avoid collisions by concurrent compilations.
2794       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2795       uint i;
2796       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2797         ciKlass* receiver = vc_data->receiver(i);
2798         if (known_klass->equals(receiver)) {
2799           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2800           __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2801           return;
2802         }
2803       }
2804 
2805       // Receiver type not found in profile data. Select an empty slot.
2806 
2807       // Note that this is less efficient than it should be because it
2808       // always does a write to the receiver part of the
2809       // VirtualCallData rather than just the first time.
2810       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2811         ciKlass* receiver = vc_data->receiver(i);
2812         if (receiver == NULL) {
2813           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2814           metadata2reg(known_klass->constant_encoding(), tmp1);
2815           __ z_stg(tmp1, recv_addr);
2816           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2817           __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2818           return;
2819         }
2820       }
2821     } else {
2822       __ load_klass(recv, recv);
2823       NearLabel update_done;
2824       type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2825       // Receiver did not match any saved receiver and there is no empty row for it.
2826       // Increment total counter to indicate polymorphic case.
2827       __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2828       __ bind(update_done);
2829     }
2830   } else {
2831     // static call
2832     __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2833   }
2834 }
2835 
2836 void LIR_Assembler::align_backward_branch_target() {
2837   __ align(OptoLoopAlignment);
2838 }
2839 
2840 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2841   ShouldNotCallThis(); // There are no delay slots on ZARCH_64.
2842 }
2843 
2844 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2845   // tmp must be unused
2846   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2847   assert(left->is_register(), "can only handle registers");
2848 
2849   if (left->is_single_cpu()) {
2850     __ z_lcr(dest->as_register(), left->as_register());
2851   } else if (left->is_single_fpu()) {
2852     __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2853   } else if (left->is_double_fpu()) {
2854     __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2855   } else {
2856     assert(left->is_double_cpu(), "Must be a long");
2857     __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2858   }
2859 }
2860 
2861 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2862                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2863   assert(!tmp->is_valid(), "don't need temporary");
2864   emit_call_c(dest);
2865   CHECK_BAILOUT();
2866   if (info != NULL) {
2867     add_call_info_here(info);
2868   }
2869 }
2870 
2871 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2872   ShouldNotCallThis(); // not needed on ZARCH_64
2873 }
2874 
2875 void LIR_Assembler::membar() {
2876   __ z_fence();
2877 }
2878 
2879 void LIR_Assembler::membar_acquire() {
2880   __ z_acquire();
2881 }
2882 
2883 void LIR_Assembler::membar_release() {
2884   __ z_release();
2885 }
2886 
2887 void LIR_Assembler::membar_loadload() {
2888   __ z_acquire();
2889 }
2890 
2891 void LIR_Assembler::membar_storestore() {
2892   __ z_release();
2893 }
2894 
2895 void LIR_Assembler::membar_loadstore() {
2896   __ z_acquire();
2897 }
2898 
2899 void LIR_Assembler::membar_storeload() {
2900   __ z_fence();
2901 }
2902 
2903 void LIR_Assembler::on_spin_wait() {
2904   Unimplemented();
2905 }
2906 
2907 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2908   assert(patch_code == lir_patch_none, "Patch code not supported");
2909   LIR_Address* addr = addr_opr->as_address_ptr();
2910   assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2911   __ load_address(dest->as_pointer_register(), as_Address(addr));
2912 }
2913 
2914 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2915   ShouldNotCallThis(); // unused
2916 }
2917 
2918 #ifdef ASSERT
2919 // Emit run-time assertion.
2920 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2921   Unimplemented();
2922 }
2923 #endif
2924 
2925 void LIR_Assembler::peephole(LIR_List*) {
2926   // Do nothing for now.
2927 }
2928 
2929 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2930   assert(code == lir_xadd, "lir_xchg not supported");
2931   Address src_addr = as_Address(src->as_address_ptr());
2932   Register base = src_addr.base();
2933   intptr_t disp = src_addr.disp();
2934   if (src_addr.index()->is_valid()) {
2935     // LAA and LAAG do not support index register.
2936     __ load_address(Z_R1_scratch, src_addr);
2937     base = Z_R1_scratch;
2938     disp = 0;
2939   }
2940   if (data->type() == T_INT) {
2941     __ z_laa(dest->as_register(), data->as_register(), disp, base);
2942   } else if (data->type() == T_LONG) {
2943     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2944     __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2945   } else {
2946     ShouldNotReachHere();
2947   }
2948 }
2949 
2950 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2951   Register obj = op->obj()->as_register();
2952   Register tmp1 = op->tmp()->as_pointer_register();
2953   Register tmp2 = Z_R1_scratch;
2954   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2955   ciKlass* exact_klass = op->exact_klass();
2956   intptr_t current_klass = op->current_klass();
2957   bool not_null = op->not_null();
2958   bool no_conflict = op->no_conflict();
2959 
2960   Label update, next, none, null_seen, init_klass;
2961 
2962   bool do_null = !not_null;
2963   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2964   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2965 
2966   assert(do_null || do_update, "why are we here?");
2967   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2968 
2969   __ verify_oop(obj, FILE_AND_LINE);
2970 
2971   if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2972     __ z_ltgr(tmp1, obj);
2973   }
2974   if (do_null) {
2975     __ z_brnz(update);
2976     if (!TypeEntries::was_null_seen(current_klass)) {
2977       __ z_lg(tmp1, mdo_addr);
2978       __ z_oill(tmp1, TypeEntries::null_seen);
2979       __ z_stg(tmp1, mdo_addr);
2980     }
2981     if (do_update) {
2982       __ z_bru(next);
2983     }
2984   } else {
2985     __ asm_assert_ne("unexpected null obj", __LINE__);
2986   }
2987 
2988   __ bind(update);
2989 
2990   if (do_update) {
2991 #ifdef ASSERT
2992     if (exact_klass != NULL) {
2993       __ load_klass(tmp1, tmp1);
2994       metadata2reg(exact_klass->constant_encoding(), tmp2);
2995       __ z_cgr(tmp1, tmp2);
2996       __ asm_assert_eq("exact klass and actual klass differ", __LINE__);
2997     }
2998 #endif
2999 
3000     Label do_update;
3001     __ z_lg(tmp2, mdo_addr);
3002 
3003     if (!no_conflict) {
3004       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3005         if (exact_klass != NULL) {
3006           metadata2reg(exact_klass->constant_encoding(), tmp1);
3007         } else {
3008           __ load_klass(tmp1, tmp1);
3009         }
3010 
3011         // Klass seen before: nothing to do (regardless of unknown bit).
3012         __ z_lgr(Z_R0_scratch, tmp2);
3013         assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3014         __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3015         __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3016 
3017         // Already unknown: Nothing to do anymore.
3018         __ z_tmll(tmp2, TypeEntries::type_unknown);
3019         __ z_brc(Assembler::bcondAllOne, next);
3020 
3021         if (TypeEntries::is_type_none(current_klass)) {
3022           __ z_lgr(Z_R0_scratch, tmp2);
3023           assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3024           __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3025           __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
3026         }
3027       } else {
3028         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3029                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3030 
3031         // Already unknown: Nothing to do anymore.
3032         __ z_tmll(tmp2, TypeEntries::type_unknown);
3033         __ z_brc(Assembler::bcondAllOne, next);
3034       }
3035 
3036       // Different than before. Cannot keep accurate profile.
3037       __ z_oill(tmp2, TypeEntries::type_unknown);
3038       __ z_bru(do_update);
3039     } else {
3040       // There's a single possible klass at this profile point.
3041       assert(exact_klass != NULL, "should be");
3042       if (TypeEntries::is_type_none(current_klass)) {
3043         metadata2reg(exact_klass->constant_encoding(), tmp1);
3044         __ z_lgr(Z_R0_scratch, tmp2);
3045         assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3046         __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3047         __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3048 #ifdef ASSERT
3049         {
3050           Label ok;
3051           __ z_lgr(Z_R0_scratch, tmp2);
3052           assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3053           __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3054           __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
3055           __ stop("unexpected profiling mismatch");
3056           __ bind(ok);
3057         }
3058 #endif
3059 
3060       } else {
3061         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3062                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3063 
3064         // Already unknown: Nothing to do anymore.
3065         __ z_tmll(tmp2, TypeEntries::type_unknown);
3066         __ z_brc(Assembler::bcondAllOne, next);
3067         __ z_oill(tmp2, TypeEntries::type_unknown);
3068         __ z_bru(do_update);
3069       }
3070     }
3071 
3072     __ bind(init_klass);
3073     // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3074     __ z_ogr(tmp2, tmp1);
3075 
3076     __ bind(do_update);
3077     __ z_stg(tmp2, mdo_addr);
3078 
3079     __ bind(next);
3080   }
3081 }
3082 
3083 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3084   Unimplemented();
3085 }
3086 
3087 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3088   assert(op->crc()->is_single_cpu(), "crc must be register");
3089   assert(op->val()->is_single_cpu(), "byte value must be register");
3090   assert(op->result_opr()->is_single_cpu(), "result must be register");
3091   Register crc = op->crc()->as_register();
3092   Register val = op->val()->as_register();
3093   Register res = op->result_opr()->as_register();
3094 
3095   assert_different_registers(val, crc, res);
3096 
3097   __ load_const_optimized(res, StubRoutines::crc_table_addr());
3098   __ kernel_crc32_singleByteReg(crc, val, res, true);
3099   __ z_lgfr(res, crc);
3100 }
3101 
3102 #undef __