1 /*
2 * Copyright (c) 2016, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2024 SAP SE. All rights reserved.
4 * Copyright (c) 2024 IBM Corporation. All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_S390_MACROASSEMBLER_S390_HPP
28 #define CPU_S390_MACROASSEMBLER_S390_HPP
29
30 #include "asm/assembler.hpp"
31 #include "oops/accessDecorators.hpp"
32
33 #define MODERN_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)
34 #define CLASSIC_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)
35 #define MODERN_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)
36 #define CLASSIC_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)
37
38 class MacroAssembler: public Assembler {
39 public:
40 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
41
42 //
43 // Optimized instruction emitters
44 //
45
46 // Move register if destination register and target register are different.
47 void lr_if_needed(Register rd, Register rs);
48 void lgr_if_needed(Register rd, Register rs);
49 void llgfr_if_needed(Register rd, Register rs);
50 void ldr_if_needed(FloatRegister rd, FloatRegister rs);
51
52 void move_reg_if_needed(Register dest, BasicType dest_type, Register src, BasicType src_type);
53 void move_freg_if_needed(FloatRegister dest, BasicType dest_type, FloatRegister src, BasicType src_type);
54
55 void freg2mem_opt(FloatRegister reg,
56 int64_t disp,
57 Register index,
58 Register base,
59 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
60 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
61 Register scratch = Z_R0);
62 void freg2mem_opt(FloatRegister reg,
63 const Address &a, bool is_double = true);
64
65 void mem2freg_opt(FloatRegister reg,
66 int64_t disp,
67 Register index,
68 Register base,
69 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
70 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
71 Register scratch = Z_R0);
72 void mem2freg_opt(FloatRegister reg,
73 const Address &a, bool is_double = true);
74
75 void reg2mem_opt(Register reg,
76 int64_t disp,
77 Register index,
78 Register base,
79 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
80 void (MacroAssembler::*classic)(Register, int64_t, Register, Register),
81 Register scratch = Z_R0);
82 // returns offset of the store instruction
83 int reg2mem_opt(Register reg, const Address &a, bool is_double = true);
84
85 void mem2reg_opt(Register reg,
86 int64_t disp,
87 Register index,
88 Register base,
89 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
90 void (MacroAssembler::*classic)(Register, int64_t, Register, Register));
91 void mem2reg_opt(Register reg, const Address &a, bool is_double = true);
92 void mem2reg_signed_opt(Register reg, const Address &a);
93
94 // AND immediate and set condition code, works for 64 bit immediates/operation as well.
95 void and_imm(Register r, long mask, Register tmp = Z_R0, bool wide = false);
96
97 // 1's complement, 32bit or 64bit. Optimized to exploit distinct operands facility.
98 // Note: The condition code is neither preserved nor correctly set by this code!!!
99 // Note: (wide == false) does not protect the high order half of the target register
100 // from alternation. It only serves as optimization hint for 32-bit results.
101 void not_(Register r1, Register r2 = noreg, bool wide = false); // r1 = ~r2
102
103 // Expanded support of all "rotate_then_<logicalOP>" instructions.
104 //
105 // Generalize and centralize rotate_then_<logicalOP> emitter.
106 // Functional description. For details, see Principles of Operation, Chapter 7, "Rotate Then Insert..."
107 // - Bits in a register are numbered left (most significant) to right (least significant), i.e. [0..63].
108 // - Bytes in a register are numbered left (most significant) to right (least significant), i.e. [0..7].
109 // - Register src is rotated to the left by (nRotate&0x3f) positions.
110 // - Negative values for nRotate result in a rotation to the right by abs(nRotate) positions.
111 // - The bits in positions [lBitPos..rBitPos] of the _ROTATED_ src operand take part in the
112 // logical operation performed on the contents (in those positions) of the dst operand.
113 // - The logical operation that is performed on the dst operand is one of
114 // o insert the selected bits (replacing the original contents of those bit positions)
115 // o and the selected bits with the corresponding bits of the dst operand
116 // o or the selected bits with the corresponding bits of the dst operand
117 // o xor the selected bits with the corresponding bits of the dst operand
118 // - For clear_dst == true, the destination register is cleared before the bits are inserted.
119 // For clear_dst == false, only the bit positions that get data inserted from src
120 // are changed. All other bit positions remain unchanged.
121 // - For test_only == true, the result of the logicalOP is only used to set the condition code, dst remains unchanged.
122 // For test_only == false, the result of the logicalOP replaces the selected bits of dst.
123 // - src32bit and dst32bit indicate the respective register is used as 32bit value only.
124 // Knowledge can simplify code generation.
125 //
126 // Here is an important performance note, valid for all <logicalOP>s except "insert":
127 // Due to the too complex nature of the operation, it cannot be done in a single cycle.
128 // Timing constraints require the instructions to be cracked into two micro-ops, taking
129 // one or two cycles each to execute. In some cases, an additional pipeline bubble might get added.
130 // Macroscopically, that makes up for a three- or four-cycle instruction where you would
131 // expect just a single cycle.
132 // It is thus not beneficial from a performance point of view to exploit those instructions.
133 // Other reasons (code compactness, register pressure, ...) might outweigh this penalty.
134 //
135 unsigned long create_mask(int lBitPos, int rBitPos);
136 void rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
137 int nRotate, bool src32bit, bool dst32bit, bool oneBits);
138 void rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
139 bool clear_dst);
140 void rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
141 bool test_only);
142 void rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
143 bool test_onlyt);
144 void rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
145 bool test_only);
146
147 void add64(Register r1, RegisterOrConstant inc);
148
149 // Helper function to multiply the 64bit contents of a register by a 16bit constant.
150 // The optimization tries to avoid the mghi instruction, since it uses the FPU for
151 // calculation and is thus rather slow.
152 //
153 // There is no handling for special cases, e.g. cval==0 or cval==1.
154 //
155 // Returns len of generated code block.
156 unsigned int mul_reg64_const16(Register rval, Register work, int cval);
157
158 // Generic operation r1 := r2 + imm.
159 void add2reg (Register r1, int64_t imm, Register r2 = noreg);
160 void add2reg_32(Register r1, int64_t imm, Register r2 = noreg);
161
162 // Generic operation r := b + x + d.
163 void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg);
164
165 // Add2mem* methods for direct memory increment.
166 void add2mem_32(const Address &a, int64_t imm, Register tmp);
167 void add2mem_64(const Address &a, int64_t imm, Register tmp);
168
169 // *((int8_t*)(dst)) |= imm8
170 inline void or2mem_8(Address& dst, int64_t imm8);
171
172 // Load values by size and signedness.
173 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
174 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
175
176 // Load values with large offsets to base address.
177 private:
178 int split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate);
179 public:
180 void load_long_largeoffset(Register t, int64_t si20, Register a, Register tmp);
181 void load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);
182 void load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);
183
184 private:
185 long toc_distance();
186 public:
187 void load_toc(Register Rtoc);
188 void load_long_pcrelative(Register Rdst, address dataLocation);
189 static int load_long_pcrelative_size() { return 6; }
190 void load_addr_pcrelative(Register Rdst, address dataLocation);
191 static int load_addr_pcrel_size() { return 6; } // Just a LARL.
192
193 // Load a value from memory and test (set CC).
194 void load_and_test_byte (Register dst, const Address &a);
195 void load_and_test_short (Register dst, const Address &a);
196 void load_and_test_int (Register dst, const Address &a);
197 void load_and_test_int2long(Register dst, const Address &a);
198 void load_and_test_long (Register dst, const Address &a);
199
200 // Test a bit in memory. Result is reflected in CC.
201 void testbit(const Address &a, unsigned int bit);
202 void testbit_ushort(const Address &a, unsigned int bit);
203 // Test a bit in a register. Result is reflected in CC.
204 void testbit(Register r, unsigned int bitPos);
205
206 void prefetch_read(Address a);
207 void prefetch_update(Address a);
208
209 // Clear a register, i.e. load const zero into reg. Return len (in bytes) of
210 // generated instruction(s).
211 // whole_reg: Clear 64 bits if true, 32 bits otherwise.
212 // set_cc: Use instruction that sets the condition code, if true.
213 int clear_reg(Register r, bool whole_reg = true, bool set_cc = true);
214
215 #ifdef ASSERT
216 int preset_reg(Register r, unsigned long pattern, int pattern_len);
217 #endif
218
219 // Clear (store zeros) a small piece of memory.
220 // CAUTION: Do not use this for atomic memory clearing. Use store_const() instead.
221 // addr: Address descriptor of memory to clear.
222 // Index register will not be used!
223 // size: Number of bytes to clear.
224 void clear_mem(const Address& addr, unsigned size);
225
226 // Move immediate values to memory. Currently supports 32 and 64 bit stores,
227 // but may be extended to 16 bit store operation, if needed.
228 // For details, see implementation in *.cpp file.
229 int store_const(const Address &dest, long imm,
230 unsigned int lm, unsigned int lc,
231 Register scratch = Z_R0);
232 inline int store_const(const Address &dest, long imm,
233 Register scratch = Z_R0, bool is_long = true);
234
235 // Move/initialize arbitrarily large memory area. No check for destructive overlap.
236 // Being interruptible, these instructions need a retry-loop.
237 void move_long_ext(Register dst, Register src, unsigned int pad);
238
239 void compare_long_ext(Register left, Register right, unsigned int pad);
240 void compare_long_uni(Register left, Register right, unsigned int pad);
241
242 void search_string(Register end, Register start);
243 void search_string_uni(Register end, Register start);
244
245 // Translate instructions
246 // Being interruptible, these instructions need a retry-loop.
247 void translate_oo(Register dst, Register src, uint mask);
248 void translate_ot(Register dst, Register src, uint mask);
249 void translate_to(Register dst, Register src, uint mask);
250 void translate_tt(Register dst, Register src, uint mask);
251
252 // Crypto instructions.
253 // Being interruptible, these instructions need a retry-loop.
254 void cksm(Register crcBuff, Register srcBuff);
255 void km( Register dstBuff, Register srcBuff);
256 void kmc( Register dstBuff, Register srcBuff);
257 void kmctr(Register dstBuff, Register ctrBuff, Register srcBuff);
258 void kimd(Register srcBuff);
259 void klmd(Register srcBuff);
260 void kmac(Register srcBuff);
261
262 // nop padding
263 void align(int modulus);
264 void align(int modulus, int target);
265 void align_address(int modulus);
266
267 //
268 // Constants, loading constants, TOC support
269 //
270
271 // Load generic address: d <- base(a) + index(a) + disp(a).
272 inline void load_address(Register d, const Address &a);
273 // Load absolute address (and try to optimize).
274 void load_absolute_address(Register d, address addr);
275
276 // Address of Z_ARG1 and argument_offset.
277 // If temp_reg == arg_slot, arg_slot will be overwritten.
278 Address argument_address(RegisterOrConstant arg_slot,
279 Register temp_reg = noreg,
280 int64_t extra_slot_offset = 0);
281
282 // Load a narrow ptr constant (oop or klass ptr).
283 void load_narrow_oop( Register t, narrowOop a);
284 void load_narrow_klass(Register t, Klass* k);
285
286 static bool is_load_const_32to64(address pos);
287 static bool is_load_narrow_oop(address pos) { return is_load_const_32to64(pos); }
288 static bool is_load_narrow_klass(address pos) { return is_load_const_32to64(pos); }
289
290 static int load_const_32to64_size() { return 6; }
291 static bool load_narrow_oop_size() { return load_const_32to64_size(); }
292 static bool load_narrow_klass_size() { return load_const_32to64_size(); }
293
294 static int patch_load_const_32to64(address pos, int64_t a);
295 static int patch_load_narrow_oop(address pos, oop o);
296 static int patch_load_narrow_klass(address pos, Klass* k);
297
298 // cOops. CLFI exploit.
299 void compare_immediate_narrow_oop(Register oop1, narrowOop oop2);
300 void compare_immediate_narrow_klass(Register op1, Klass* op2);
301 static bool is_compare_immediate32(address pos);
302 static bool is_compare_immediate_narrow_oop(address pos);
303 static bool is_compare_immediate_narrow_klass(address pos);
304 static int compare_immediate_narrow_size() { return 6; }
305 static int compare_immediate_narrow_oop_size() { return compare_immediate_narrow_size(); }
306 static int compare_immediate_narrow_klass_size() { return compare_immediate_narrow_size(); }
307 static int patch_compare_immediate_32(address pos, int64_t a);
308 static int patch_compare_immediate_narrow_oop(address pos, oop o);
309 static int patch_compare_immediate_narrow_klass(address pos, Klass* k);
310
311 // Load a 32bit constant into a 64bit register.
312 void load_const_32to64(Register t, int64_t x, bool sign_extend=true);
313 // Load a 64 bit constant.
314 void load_const(Register t, long a);
315 inline void load_const(Register t, void* a);
316 inline void load_const(Register t, Label& L);
317 inline void load_const(Register t, const AddressLiteral& a);
318 // Get the 64 bit constant from a `load_const' sequence.
319 static long get_const(address load_const);
320 // Patch the 64 bit constant of a `load_const' sequence. This is a low level
321 // procedure. It neither flushes the instruction cache nor is it atomic.
322 static void patch_const(address load_const, long x);
323 static int load_const_size() { return 12; }
324
325 // Turn a char into boolean. NOTE: destroys r.
326 void c2bool(Register r, Register t = Z_R0);
327
328 // Optimized version of load_const for constants that do not need to be
329 // loaded by a sequence of instructions of fixed length and that do not
330 // need to be patched.
331 int load_const_optimized_rtn_len(Register t, long x, bool emit);
332 inline void load_const_optimized(Register t, long x);
333 inline void load_const_optimized(Register t, void* a);
334 inline void load_const_optimized(Register t, Label& L);
335 inline void load_const_optimized(Register t, const AddressLiteral& a);
336
337 public:
338
339 //----------------------------------------------------------
340 // oops in code -------------
341 // including compressed oops support -------------
342 //----------------------------------------------------------
343
344 // Metadata in code that we have to keep track of.
345 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
346 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
347
348 // allocate_index
349 AddressLiteral allocate_oop_address(jobject obj);
350 // find_index
351 AddressLiteral constant_oop_address(jobject obj);
352 // Uses allocate_oop_address.
353 inline void set_oop (jobject obj, Register d);
354 // Uses constant_oop_address.
355 inline void set_oop_constant(jobject obj, Register d);
356 // Uses constant_metadata_address.
357 inline bool set_metadata_constant(Metadata* md, Register d);
358
359 //
360 // branch, jump
361 //
362
363 // Use one generic function for all branch patches.
364 static unsigned long patched_branch(address dest_pos, unsigned long inst, address inst_pos);
365
366 void pd_patch_instruction(address branch, address target, const char* file, int line);
367
368 // Extract relative address from "relative" instructions.
369 static long get_pcrel_offset(unsigned long inst);
370 static long get_pcrel_offset(address pc);
371 static address get_target_addr_pcrel(address pc);
372
373 static inline bool is_call_pcrelative_short(unsigned long inst);
374 static inline bool is_call_pcrelative_long(unsigned long inst);
375 static inline bool is_branch_pcrelative_short(unsigned long inst);
376 static inline bool is_branch_pcrelative_long(unsigned long inst);
377 static inline bool is_compareandbranch_pcrelative_short(unsigned long inst);
378 static inline bool is_branchoncount_pcrelative_short(unsigned long inst);
379 static inline bool is_branchonindex32_pcrelative_short(unsigned long inst);
380 static inline bool is_branchonindex64_pcrelative_short(unsigned long inst);
381 static inline bool is_branchonindex_pcrelative_short(unsigned long inst);
382 static inline bool is_branch_pcrelative16(unsigned long inst);
383 static inline bool is_branch_pcrelative32(unsigned long inst);
384 static inline bool is_branch_pcrelative(unsigned long inst);
385 static inline bool is_load_pcrelative_long(unsigned long inst);
386 static inline bool is_misc_pcrelative_long(unsigned long inst);
387 static inline bool is_pcrelative_short(unsigned long inst);
388 static inline bool is_pcrelative_long(unsigned long inst);
389 // PCrelative TOC access. Variants with address argument.
390 static inline bool is_load_pcrelative_long(address iLoc);
391 static inline bool is_pcrelative_short(address iLoc);
392 static inline bool is_pcrelative_long(address iLoc);
393
394 static inline bool is_pcrelative_instruction(address iloc);
395 static inline bool is_load_addr_pcrel(address a);
396
397 static void patch_target_addr_pcrel(address pc, address con);
398 static void patch_addr_pcrel(address pc, address con) {
399 patch_target_addr_pcrel(pc, con); // Just delegate. This is only for nativeInst_s390.cpp.
400 }
401
402 //---------------------------------------------------------
403 // Some macros for more comfortable assembler programming.
404 //---------------------------------------------------------
405
406 // NOTE: pass NearLabel T to signal that the branch target T will be bound to a near address.
407
408 void compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
409 void compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
410 void compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
411 void compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
412
413 void branch_optimized(Assembler::branch_condition cond, address branch_target);
414 void branch_optimized(Assembler::branch_condition cond, Label& branch_target);
415 void compare_and_branch_optimized(Register r1,
416 Register r2,
417 Assembler::branch_condition cond,
418 address branch_addr,
419 bool len64,
420 bool has_sign);
421 void compare_and_branch_optimized(Register r1,
422 jlong x2,
423 Assembler::branch_condition cond,
424 Label& branch_target,
425 bool len64,
426 bool has_sign);
427 void compare_and_branch_optimized(Register r1,
428 Register r2,
429 Assembler::branch_condition cond,
430 Label& branch_target,
431 bool len64,
432 bool has_sign);
433
434 //
435 // Support for frame handling
436 //
437 // Specify the register that should be stored as the return pc in the
438 // current frame (default is R14).
439 inline void save_return_pc(Register pc = Z_R14);
440 inline void restore_return_pc();
441
442 // Get current PC.
443 address get_PC(Register result);
444
445 // Get current PC + offset. Offset given in bytes, must be even!
446 address get_PC(Register result, int64_t offset);
447
448 // Get size of instruction at pc (which must point to valid code).
449 void instr_size(Register size, Register pc);
450
451 // Accessing, and in particular modifying, a stack location is only safe if
452 // the stack pointer (Z_SP) is set such that the accessed stack location is
453 // in the reserved range.
454 //
455 // From a performance point of view, it is desirable not to change the SP
456 // first and then immediately use it to access the freshly reserved space.
457 // That opens a small gap, though. If, just after storing some value (the
458 // frame pointer) into the to-be-reserved space, an interrupt is caught,
459 // the handler might use the space beyond Z_SP for it's own purpose.
460 // If that happens, the stored value might get altered.
461
462 // Resize current frame either relatively wrt to current SP or absolute.
463 void resize_frame_sub(Register offset, Register fp, bool load_fp=true);
464 void resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp);
465 void resize_frame_absolute(Register addr, Register fp, bool load_fp);
466 void resize_frame(RegisterOrConstant offset, Register fp, bool load_fp=true);
467
468 // Push a frame of size bytes, if copy_sp is false, old_sp must already
469 // contain a copy of Z_SP.
470 void push_frame(Register bytes, Register old_sp, bool copy_sp = true, bool bytes_with_inverted_sign = false);
471
472 // Push a frame of size `bytes'. no abi space provided.
473 // Don't rely on register locking, instead pass a scratch register
474 // (Z_R0 by default).
475 // CAUTION! passing registers >= Z_R2 may produce bad results on
476 // old CPUs!
477 unsigned int push_frame(unsigned int bytes, Register scratch = Z_R0);
478
479 // Push a frame of size `bytes' with abi160 on top.
480 unsigned int push_frame_abi160(unsigned int bytes);
481
482 // Pop current C frame.
483 void pop_frame();
484 // Pop current C frame and restore return PC register (Z_R14).
485 void pop_frame_restore_retPC(int frame_size_in_bytes);
486
487 #ifdef ASSERT
488 void clobber_volatile_registers(Register excluded_register[], int n);
489 #endif // ASSERT
490
491 //
492 // Calls
493 //
494
495 private:
496 address _last_calls_return_pc;
497
498 public:
499 // Support for VM calls. This is the base routine called by the
500 // different versions of call_VM_leaf. The interpreter may customize
501 // this version by overriding it for its purposes (e.g., to
502 // save/restore additional registers when doing a VM call).
503 void call_VM_leaf_base(address entry_point);
504 void call_VM_leaf_base(address entry_point, bool allow_relocation);
505
506 // It is imperative that all calls into the VM are handled via the
507 // call_VM macros. They make sure that the stack linkage is setup
508 // correctly. Call_VM's correspond to ENTRY/ENTRY_X entry points
509 // while call_VM_leaf's correspond to LEAF entry points.
510 //
511 // This is the base routine called by the different versions of
512 // call_VM. The interpreter may customize this version by overriding
513 // it for its purposes (e.g., to save/restore additional registers
514 // when doing a VM call).
515
516 // If no last_java_sp is specified (noreg) then SP will be used instead.
517
518 virtual void call_VM_base(
519 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise.
520 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
521 address entry_point, // The entry point.
522 bool check_exception); // Flag which indicates if exception should be checked.
523 virtual void call_VM_base(
524 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise.
525 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
526 address entry_point, // The entry point.
527 bool allow_relocation, // Flag to request generation of relocatable code.
528 bool check_exception); // Flag which indicates if exception should be checked.
529
530 // Call into the VM.
531 // Passes the thread pointer (in Z_ARG1) as a prepended argument.
532 // Makes sure oop return values are visible to the GC.
533 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
534 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
535 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
536 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
537 Register arg_3, bool check_exceptions = true);
538
539 void call_VM_static(Register oop_result, address entry_point, bool check_exceptions = true);
540 void call_VM_static(Register oop_result, address entry_point, Register arg_1, Register arg_2,
541 Register arg_3, bool check_exceptions = true);
542
543 // Overloaded with last_java_sp.
544 void call_VM(Register oop_result, Register last_java_sp, address entry_point, bool check_exceptions = true);
545 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
546 Register arg_1, bool check_exceptions = true);
547 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
548 Register arg_1, Register arg_2, bool check_exceptions = true);
549 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
550 Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
551
552 void call_VM_leaf(address entry_point);
553 void call_VM_leaf(address entry_point, Register arg_1);
554 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
555 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
556
557 // Really static VM leaf call (never patched).
558 void call_VM_leaf_static(address entry_point);
559 void call_VM_leaf_static(address entry_point, Register arg_1);
560 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2);
561 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2, Register arg_3);
562
563 // Call a C function via its function entry. Updates and returns _last_calls_return_pc.
564 inline address call(Register function_entry);
565 inline address call_c(Register function_entry);
566 address call_c(address function_entry);
567 // Variant for really static (non-relocatable) calls which are never patched.
568 address call_c_static(address function_entry);
569 // TOC or pc-relative call + emits a runtime_call relocation.
570 address call_c_opt(address function_entry);
571
572 inline address call_stub(Register function_entry);
573 inline address call_stub(address function_entry);
574
575 // Get the pc where the last call will return to. Returns _last_calls_return_pc.
576 inline address last_calls_return_pc();
577
578 static int ic_check_size();
579 int ic_check(int end_alignment);
580
581 private:
582 static bool is_call_far_patchable_variant0_at(address instruction_addr); // Dynamic TOC: load target addr from CP and call.
583 static bool is_call_far_patchable_variant2_at(address instruction_addr); // PC-relative call, prefixed with NOPs.
584
585
586 public:
587 bool call_far_patchable(address target, int64_t toc_offset);
588 static bool is_call_far_patchable_at(address inst_start); // All supported forms of patchable calls.
589 static bool is_call_far_patchable_pcrelative_at(address inst_start); // Pc-relative call with leading nops.
590 static bool is_call_far_pcrelative(address instruction_addr); // Pure far pc-relative call, with one leading size adjustment nop.
591 static void set_dest_of_call_far_patchable_at(address inst_start, address target, int64_t toc_offset);
592 static address get_dest_of_call_far_patchable_at(address inst_start, address toc_start);
593
594 void align_call_far_patchable(address pc);
595
596 // PCrelative TOC access.
597
598 // This value is independent of code position - constant for the lifetime of the VM.
599 static int call_far_patchable_size() {
600 return load_const_from_toc_size() + call_byregister_size();
601 }
602
603 static int call_far_patchable_ret_addr_offset() { return call_far_patchable_size(); }
604
605 static bool call_far_patchable_requires_alignment_nop(address pc) {
606 int size = call_far_patchable_size();
607 return ((intptr_t)(pc + size) & 0x03L) != 0;
608 }
609
610 // END OF PCrelative TOC access.
611
612 static int jump_byregister_size() { return 2; }
613 static int jump_pcrelative_size() { return 4; }
614 static int jump_far_pcrelative_size() { return 6; }
615 static int call_byregister_size() { return 2; }
616 static int call_pcrelative_size() { return 4; }
617 static int call_far_pcrelative_size() { return 2 + 6; } // Prepend each BRASL with a nop.
618 static int call_far_pcrelative_size_raw() { return 6; } // Prepend each BRASL with a nop.
619
620 //
621 // Java utilities
622 //
623
624 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
625 // The implementation is only non-empty for the InterpreterMacroAssembler,
626 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
627 virtual void check_and_handle_popframe(Register java_thread);
628 virtual void check_and_handle_earlyret(Register java_thread);
629
630 // Polling page support.
631 enum poll_mask {
632 mask_stackbang = 0xde, // 222 (dec)
633 mask_safepoint = 0x6f, // 111 (dec)
634 mask_profiling = 0xba // 186 (dec)
635 };
636
637 // Read from the polling page.
638 void load_from_polling_page(Register polling_page_address, int64_t offset = 0);
639
640 // Check if given instruction is a read from the polling page
641 // as emitted by load_from_polling_page.
642 static bool is_load_from_polling_page(address instr_loc);
643 // Extract poll address from instruction and ucontext.
644 static address get_poll_address(address instr_loc, void* ucontext);
645 // Extract poll register from instruction.
646 static uint get_poll_register(address instr_loc);
647
648 // Check if safepoint requested and if so branch
649 void safepoint_poll(Label& slow_path, Register temp_reg);
650
651 // Stack overflow checking
652 void bang_stack_with_offset(int offset);
653
654 // Check for reserved stack access in method being exited. If the reserved
655 // stack area was accessed, protect it again and throw StackOverflowError.
656 // Uses Z_R1.
657 void reserved_stack_check(Register return_pc);
658
659 // Atomics
660 // -- none?
661
662 void tlab_allocate(Register obj, // Result: pointer to object after successful allocation
663 Register var_size_in_bytes, // Object size in bytes if unknown at compile time; invalid otherwise.
664 int con_size_in_bytes, // Object size in bytes if known at compile time.
665 Register t1, // temp register
666 Label& slow_case); // Continuation point if fast allocation fails.
667
668 // Emitter for interface method lookup.
669 // input: recv_klass, intf_klass, itable_index
670 // output: method_result
671 // kills: itable_index, temp1_reg, Z_R0, Z_R1
672 void lookup_interface_method(Register recv_klass,
673 Register intf_klass,
674 RegisterOrConstant itable_index,
675 Register method_result,
676 Register temp1_reg,
677 Label& no_such_interface,
678 bool return_method = true);
679
680 // virtual method calling
681 void lookup_virtual_method(Register recv_klass,
682 RegisterOrConstant vtable_index,
683 Register method_result);
684
685 // Factor out code to call ic_miss_handler.
686 unsigned int call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch);
687 void nmethod_UEP(Label& ic_miss);
688
689 // Emitters for "partial subtype" checks.
690
691 // Test sub_klass against super_klass, with fast and slow paths.
692
693 // The fast path produces a tri-state answer: yes / no / maybe-slow.
694 // One of the three labels can be null, meaning take the fall-through.
695 // If super_check_offset is -1, the value is loaded up from super_klass.
696 // No registers are killed, except temp_reg and temp2_reg.
697 // If super_check_offset is not -1, temp1_reg is not used and can be noreg.
698 void check_klass_subtype_fast_path(Register sub_klass,
699 Register super_klass,
700 Register temp1_reg,
701 Label* L_success,
702 Label* L_failure,
703 Label* L_slow_path,
704 Register super_check_offset = noreg);
705
706 // The rest of the type check; must be wired to a corresponding fast path.
707 // It does not repeat the fast path logic, so don't use it standalone.
708 // The temp_reg can be noreg, if no temps are available.
709 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
710 // Updates the sub's secondary super cache as necessary.
711 void check_klass_subtype_slow_path(Register Rsubklass,
712 Register Rsuperklas,
713 Register Rarray_ptr, // tmp
714 Register Rlength, // tmp
715 Label* L_success,
716 Label* L_failure,
717 bool set_cond_codes = false);
718
719 void check_klass_subtype_slow_path_linear(Register sub_klass,
720 Register super_klass,
721 Register temp_reg,
722 Register temp2_reg,
723 Label* L_success,
724 Label* L_failure,
725 bool set_cond_codes = false);
726
727 void check_klass_subtype_slow_path_table(Register sub_klass,
728 Register super_klass,
729 Register temp_reg,
730 Register temp2_reg,
731 Register temp3_reg,
732 Register temp4_reg,
733 Register result_reg,
734 Label* L_success,
735 Label* L_failure,
736 bool set_cond_codes = false);
737
738 // If r is valid, return r.
739 // If r is invalid, remove a register r2 from available_regs, add r2
740 // to regs_to_push, then return r2.
741 Register allocate_if_noreg(const Register r,
742 RegSetIterator<Register> &available_regs,
743 RegSet ®s_to_push);
744
745 void repne_scan(Register r_addr, Register r_value, Register r_count, Register r_scratch);
746
747 // Secondary subtype checking
748 void lookup_secondary_supers_table_var(Register sub_klass,
749 Register r_super_klass,
750 Register temp1,
751 Register temp2,
752 Register temp3,
753 Register temp4,
754 Register result);
755
756 void lookup_secondary_supers_table_const(Register r_sub_klass,
757 Register r_super_klass,
758 Register r_temp1,
759 Register r_temp2,
760 Register r_temp3,
761 Register r_temp4,
762 Register r_result,
763 u1 super_klass_slot);
764
765 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
766 Register r_array_base,
767 Register r_array_index,
768 Register r_bitmap,
769 Register r_temp,
770 Register r_result,
771 bool is_stub);
772
773 void verify_secondary_supers_table(Register r_sub_klass,
774 Register r_super_klass,
775 Register r_result /* expected */,
776 Register r_temp1,
777 Register r_temp2,
778 Register r_temp3);
779
780 // Simplified, combined version, good for typical uses.
781 // Falls through on failure.
782 void check_klass_subtype(Register sub_klass,
783 Register super_klass,
784 Register temp1_reg,
785 Register temp2_reg,
786 Label& L_success);
787
788 void clinit_barrier(Register klass,
789 Register thread,
790 Label* L_fast_path = nullptr,
791 Label* L_slow_path = nullptr);
792
793 // Increment a counter at counter_address when the eq condition code is set.
794 // Kills registers tmp1_reg and tmp2_reg and preserves the condition code.
795 void increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg);
796
797 void fast_lock(Register basic_lock, Register obj, Register tmp1, Register tmp2, Label& slow);
798 void fast_unlock(Register obj, Register tmp1, Register tmp2, Label& slow);
799 void compiler_fast_lock_object(Register obj, Register box, Register tmp1, Register tmp2);
800 void compiler_fast_unlock_object(Register obj, Register box, Register tmp1, Register tmp2);
801
802 void resolve_jobject(Register value, Register tmp1, Register tmp2);
803 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
804
805 // Support for last Java frame (but use call_VM instead where possible).
806 private:
807 void set_last_Java_frame(Register last_Java_sp, Register last_Java_pc, bool allow_relocation);
808 void reset_last_Java_frame(bool allow_relocation);
809 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, bool allow_relocation);
810 public:
811 inline void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
812 inline void set_last_Java_frame_static(Register last_java_sp, Register last_Java_pc);
813 inline void reset_last_Java_frame(void);
814 inline void reset_last_Java_frame_static(void);
815 inline void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1);
816 inline void set_top_ijava_frame_at_SP_as_last_Java_frame_static(Register sp, Register tmp1);
817
818 void set_thread_state(JavaThreadState new_state);
819
820 // Read vm result from thread.
821 void get_vm_result_oop (Register oop_result);
822 void get_vm_result_metadata(Register result);
823
824 // Vm result is currently getting hijacked to for oop preservation.
825 void set_vm_result(Register oop_result);
826
827 // Support for null-checks
828 //
829 // Generates code that causes a null OS exception if the content of reg is null.
830 // If the accessed location is M[reg + offset] and the offset is known, provide the
831 // offset. No explicit code generation is needed if the offset is within a certain
832 // range (0 <= offset <= page_size).
833 //
834 // %%%%%% Currently not done for z/Architecture
835
836 void null_check(Register reg, Register tmp = Z_R0, int64_t offset = -1);
837 static bool needs_explicit_null_check(intptr_t offset); // Implemented in shared file ?!
838 static bool uses_implicit_null_check(void* address);
839
840 // Klass oop manipulations if compressed.
841 void encode_klass_not_null(Register dst, Register src = noreg);
842 void decode_klass_not_null(Register dst, Register src);
843 void decode_klass_not_null(Register dst);
844 void load_klass(Register klass, Address mem);
845 void load_klass(Register klass, Register src_oop);
846 void store_klass(Register klass, Register dst_oop, Register ck = noreg); // Klass will get compressed if ck not provided.
847 void store_klass_gap(Register s, Register dst_oop);
848 void load_narrow_klass_compact(Register dst, Register src);
849 // Compares the narrow Klass pointer of an object to a given narrow Klass
850 void cmp_klass(Register klass, Register obj, Register tmp);
851 // Compares the Klass pointer of two objects obj1 and obj2. Result is in the condition flags.
852 // Uses tmp1 and tmp2 as temporary registers.
853 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
854
855 // This function calculates the size of the code generated by
856 // decode_klass_not_null(register dst)
857 // when Universe::heap() isn't null. Hence, if the instructions
858 // it generates change, then this method needs to be updated.
859 static int instr_size_for_decode_klass_not_null();
860
861 void encode_heap_oop(Register oop);
862 void encode_heap_oop_not_null(Register oop);
863
864 static int get_oop_base_pow2_offset(uint64_t oop_base);
865 int get_oop_base(Register Rbase, uint64_t oop_base);
866 int get_oop_base_complement(Register Rbase, uint64_t oop_base);
867 void compare_heap_oop(Register Rop1, Address mem, bool maybenull);
868 void compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybenull);
869
870 // Access heap oop, handle encoding and GC barriers.
871 void access_store_at(BasicType type, DecoratorSet decorators,
872 const Address& addr, Register val,
873 Register tmp1, Register tmp2, Register tmp3);
874 void access_load_at(BasicType type, DecoratorSet decorators,
875 const Address& addr, Register dst,
876 Register tmp1, Register tmp2, Label *is_null = nullptr);
877
878 public:
879 // tmp1 and tmp2 are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
880 void load_heap_oop(Register dest, const Address &a,
881 Register tmp1, Register tmp2,
882 DecoratorSet decorators = 0, Label *is_null = nullptr);
883 void store_heap_oop(Register Roop, const Address &a,
884 Register tmp1, Register tmp2, Register tmp3,
885 DecoratorSet decorators = 0);
886
887 void oop_encoder(Register Rdst, Register Rsrc, bool maybenull,
888 Register Rbase = Z_R1, int pow2_offset = -1, bool only32bitValid = false);
889 void oop_decoder(Register Rdst, Register Rsrc, bool maybenull,
890 Register Rbase = Z_R1, int pow2_offset = -1);
891
892 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
893 void load_method_holder(Register holder, Register method);
894
895 //--------------------------
896 //--- Operations on arrays.
897 //--------------------------
898 unsigned int Clear_Array(Register cnt_arg, Register base_pointer_arg, Register odd_tmp_reg);
899 unsigned int Clear_Array_Const(long cnt, Register base);
900 unsigned int Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register odd_tmp_reg);
901 unsigned int CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
902 Register cnt_reg,
903 Register tmp1_reg, Register tmp2_reg);
904
905
906 // Emit an oop const to the constant pool and set a relocation info
907 // with address current_pc. Return the TOC offset of the constant.
908 int store_const_in_toc(AddressLiteral& val);
909 int store_oop_in_toc(AddressLiteral& oop);
910 // Emit an oop const to the constant pool via store_oop_in_toc, or
911 // emit a scalar const to the constant pool via store_const_in_toc,
912 // and load the constant into register dst.
913 bool load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg);
914 // Get CPU version dependent size of load_const sequence.
915 // The returned value is valid only for code sequences
916 // generated by load_const, not load_const_optimized.
917 static int load_const_from_toc_size() {
918 return load_long_pcrelative_size();
919 }
920 bool load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg);
921 static intptr_t get_const_from_toc(address pc);
922 static void set_const_in_toc(address pc, unsigned long new_data, CodeBlob *cb);
923
924 // Dynamic TOC.
925 static bool is_load_const(address a);
926 static bool is_load_const_from_toc_pcrelative(address a);
927 static bool is_load_const_from_toc(address a) { return is_load_const_from_toc_pcrelative(a); }
928
929 // PCrelative TOC access.
930 static bool is_call_byregister(address a) { return is_z_basr(*(short*)a); }
931 static bool is_load_const_from_toc_call(address a);
932 static bool is_load_const_call(address a);
933 static int load_const_call_size() { return load_const_size() + call_byregister_size(); }
934 static int load_const_from_toc_call_size() { return load_const_from_toc_size() + call_byregister_size(); }
935 // Offset is +/- 2**32 -> use long.
936 static long get_load_const_from_toc_offset(address a);
937
938 // Bit operations for single register operands.
939 inline void lshift(Register r, int places, bool doubl = true); // <<
940 inline void rshift(Register r, int places, bool doubl = true); // >>
941
942 //
943 // Debugging
944 //
945
946 // Assert on CC (condition code in CPU state).
947 void asm_assert(branch_condition cond, const char* msg, int id, bool is_static=true);
948 void asm_assert(bool check_equal, const char* msg, int id);
949
950 private:
951 // Emit assertions.
952 void asm_assert_mems_zero(bool check_equal, bool allow_relocation, int size, int64_t mem_offset,
953 Register mem_base, const char* msg, int id);
954
955 public:
956 inline void asm_assert_mem4_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
957 asm_assert_mems_zero(true, true, 4, mem_offset, mem_base, msg, id);
958 }
959 inline void asm_assert_mem8_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
960 asm_assert_mems_zero(true, true, 8, mem_offset, mem_base, msg, id);
961 }
962 inline void asm_assert_mem4_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
963 asm_assert_mems_zero(false, true, 4, mem_offset, mem_base, msg, id);
964 }
965 inline void asm_assert_mem8_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
966 asm_assert_mems_zero(false, true, 8, mem_offset, mem_base, msg, id);
967 }
968 inline void asm_assert_mem4_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
969 asm_assert_mems_zero(true, false, 4, mem_offset, mem_base, msg, id);
970 }
971 inline void asm_assert_mem8_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
972 asm_assert_mems_zero(true, false, 8, mem_offset, mem_base, msg, id);
973 }
974 inline void asm_assert_mem4_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
975 asm_assert_mems_zero(false, false, 4, mem_offset, mem_base, msg, id);
976 }
977 inline void asm_assert_mem8_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
978 asm_assert_mems_zero(false, false, 8, mem_offset, mem_base, msg, id);
979 }
980 void asm_assert_frame_size(Register expected_size, Register tmp, const char* msg, int id);
981
982 // Save and restore functions: Exclude Z_R0.
983 void save_volatile_regs( Register dst, int offset, bool include_fp, bool include_flags);
984 void restore_volatile_regs(Register src, int offset, bool include_fp, bool include_flags);
985
986 // Only if +VerifyOops.
987 // Kills Z_R0.
988 void verify_oop(Register reg, const char* s = "broken oop");
989 // Kills Z_R0, condition code.
990 void verify_oop_addr(Address addr, const char* msg = "contains broken oop");
991
992 // TODO: verify_method and klass metadata (compare against vptr?).
993 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
994 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
995
996 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
997 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
998
999 private:
1000 // Generate printout in stop().
1001 static const char* stop_types[];
1002 enum {
1003 stop_stop = 0,
1004 stop_untested = 1,
1005 stop_unimplemented = 2,
1006 stop_shouldnotreachhere = 3,
1007 stop_end = 4
1008 };
1009 // Prints msg and stops execution.
1010 void stop(int type, const char* msg, int id = 0);
1011 address stop_chain(address reentry, int type, const char* msg, int id, bool allow_relocation); // Non-relocateable code only!!
1012 void stop_static(int type, const char* msg, int id); // Non-relocateable code only!!
1013
1014 public:
1015
1016 // Prints msg and stops.
1017 address stop_chain( address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, true); }
1018 address stop_chain_static(address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, false); }
1019 void stop_static (const char* msg = "", int id = 0) { stop_static(stop_stop, msg, id); }
1020 void stop (const char* msg = "", int id = 0) { stop(stop_stop, msg, id); }
1021 void untested (const char* msg = "", int id = 0) { stop(stop_untested, msg, id); }
1022 void unimplemented(const char* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); }
1023 void should_not_reach_here(const char* msg = "", int id = -1) { stop(stop_shouldnotreachhere, msg, id); }
1024
1025 // Factor out part of stop into subroutine to save space.
1026 void stop_subroutine();
1027
1028 // Prints msg, but don't stop.
1029 void warn(const char* msg);
1030
1031 //-----------------------------
1032 //--- basic block tracing code
1033 //-----------------------------
1034 void trace_basic_block(uint i);
1035 void init_basic_block_trace();
1036 // Number of bytes a basic block gets larger due to the tracing code macro (worst case).
1037 // Currently, worst case is 48 bytes. 64 puts us securely on the safe side.
1038 static int basic_blck_trace_blk_size_incr() { return 64; }
1039
1040 // Write pattern 0x0101010101010101 in region [low-before, high+after].
1041 // Low and high may be the same registers. Before and after are
1042 // the numbers of 8-byte words.
1043 void zap_from_to(Register low, Register high, Register tmp1 = Z_R0, Register tmp2 = Z_R1,
1044 int before = 0, int after = 0) PRODUCT_RETURN;
1045
1046 // Emitters for CRC32 calculation.
1047 // A note on invertCRC:
1048 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
1049 // CRC32 holds it's current crc value in the externally visible representation.
1050 // CRC32C holds it's current crc value in internal format, ready for updating.
1051 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
1052 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
1053 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
1054 private:
1055 void fold_byte_crc32(Register crc, Register table, Register val, Register tmp);
1056 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1057 void update_byte_crc32( Register crc, Register val, Register table);
1058 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
1059 Register data);
1060 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
1061 Register t0, Register t1, Register t2, Register t3);
1062 public:
1063 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
1064 bool invertCRC);
1065 void kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp,
1066 bool invertCRC);
1067 void kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
1068 Register t0, Register t1, Register t2, Register t3,
1069 bool invertCRC);
1070 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
1071 Register t0, Register t1, Register t2, Register t3,
1072 bool invertCRC);
1073
1074 // Emitters for BigInteger.multiplyToLen intrinsic
1075 // note: length of result array (zlen) is passed on the stack
1076 private:
1077 void add2_with_carry(Register dest_hi, Register dest_lo,
1078 Register src1, Register src2);
1079 void multiply_64_x_64_loop(Register x, Register xstart,
1080 Register x_xstart,
1081 Register y, Register y_idx, Register z,
1082 Register carry, Register product,
1083 Register idx, Register kdx);
1084 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1085 Register yz_idx, Register idx,
1086 Register carry, Register product, int offset);
1087 void multiply_128_x_128_loop(Register x_xstart,
1088 Register y, Register z,
1089 Register yz_idx, Register idx,
1090 Register jdx,
1091 Register carry, Register product,
1092 Register carry2);
1093 public:
1094 void multiply_to_len(Register x, Register xlen,
1095 Register y, Register ylen,
1096 Register z,
1097 Register tmp1, Register tmp2,
1098 Register tmp3, Register tmp4, Register tmp5);
1099
1100 // These generate optimized code for all supported s390 implementations, and are preferred for most uses.
1101 void pop_count_int(Register dst, Register src, Register tmp);
1102 void pop_count_long(Register dst, Register src, Register tmp);
1103
1104 // For legacy (pre-z15) use, but will work on all supported s390 implementations.
1105 void pop_count_int_without_ext3(Register dst, Register src, Register tmp);
1106 void pop_count_long_without_ext3(Register dst, Register src, Register tmp);
1107
1108 // Only for use on z15 or later s390 implementations.
1109 void pop_count_int_with_ext3(Register dst, Register src);
1110 void pop_count_long_with_ext3(Register dst, Register src);
1111
1112 void load_on_condition_imm_32(Register dst, int64_t i2, branch_condition cc);
1113 void load_on_condition_imm_64(Register dst, int64_t i2, branch_condition cc);
1114 };
1115
1116 #ifdef ASSERT
1117 // Return false (e.g. important for our impl. of virtual calls).
1118 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1119 #endif
1120
1121 #endif // CPU_S390_MACROASSEMBLER_S390_HPP