1 /*
2 * Copyright (c) 2016, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2024 SAP SE. All rights reserved.
4 * Copyright (c) 2024, 2026, IBM Corporation. All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
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25 */
26
27 #ifndef CPU_S390_MACROASSEMBLER_S390_HPP
28 #define CPU_S390_MACROASSEMBLER_S390_HPP
29
30 #include "asm/assembler.hpp"
31 #include "oops/accessDecorators.hpp"
32
33 class ciInlineKlass;
34 class SigEntry;
35 class VMRegPair;
36
37 #define MODERN_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)
38 #define CLASSIC_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name)
39 #define MODERN_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)
40 #define CLASSIC_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name)
41
42 class MacroAssembler: public Assembler {
43 public:
44 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
45
46 //
47 // Optimized instruction emitters
48 //
49
50 // Move register if destination register and target register are different.
51 void lr_if_needed(Register rd, Register rs);
52 void lgr_if_needed(Register rd, Register rs);
53 void llgfr_if_needed(Register rd, Register rs);
54 void ldr_if_needed(FloatRegister rd, FloatRegister rs);
55
56 void move_reg_if_needed(Register dest, BasicType dest_type, Register src, BasicType src_type);
57 void move_freg_if_needed(FloatRegister dest, BasicType dest_type, FloatRegister src, BasicType src_type);
58
59 void freg2mem_opt(FloatRegister reg,
60 int64_t disp,
61 Register index,
62 Register base,
63 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
64 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
65 Register scratch = Z_R0);
66 void freg2mem_opt(FloatRegister reg,
67 const Address &a, bool is_double = true);
68
69 void mem2freg_opt(FloatRegister reg,
70 int64_t disp,
71 Register index,
72 Register base,
73 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
74 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
75 Register scratch = Z_R0);
76 void mem2freg_opt(FloatRegister reg,
77 const Address &a, bool is_double = true);
78
79 void reg2mem_opt(Register reg,
80 int64_t disp,
81 Register index,
82 Register base,
83 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
84 void (MacroAssembler::*classic)(Register, int64_t, Register, Register),
85 Register scratch = Z_R0);
86 // returns offset of the store instruction
87 int reg2mem_opt(Register reg, const Address &a, bool is_double = true);
88
89 void mem2reg_opt(Register reg,
90 int64_t disp,
91 Register index,
92 Register base,
93 void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
94 void (MacroAssembler::*classic)(Register, int64_t, Register, Register));
95 void mem2reg_opt(Register reg, const Address &a, bool is_double = true);
96 void mem2reg_signed_opt(Register reg, const Address &a);
97
98 // AND immediate and set condition code, works for 64 bit immediates/operation as well.
99 void and_imm(Register r, long mask, Register tmp = Z_R0, bool wide = false);
100
101 // 1's complement, 32bit or 64bit. Optimized to exploit distinct operands facility.
102 // Note: The condition code is neither preserved nor correctly set by this code!!!
103 // Note: (wide == false) does not protect the high order half of the target register
104 // from alternation. It only serves as optimization hint for 32-bit results.
105 void not_(Register r1, Register r2 = noreg, bool wide = false); // r1 = ~r2
106
107 // Expanded support of all "rotate_then_<logicalOP>" instructions.
108 //
109 // Generalize and centralize rotate_then_<logicalOP> emitter.
110 // Functional description. For details, see Principles of Operation, Chapter 7, "Rotate Then Insert..."
111 // - Bits in a register are numbered left (most significant) to right (least significant), i.e. [0..63].
112 // - Bytes in a register are numbered left (most significant) to right (least significant), i.e. [0..7].
113 // - Register src is rotated to the left by (nRotate&0x3f) positions.
114 // - Negative values for nRotate result in a rotation to the right by abs(nRotate) positions.
115 // - The bits in positions [lBitPos..rBitPos] of the _ROTATED_ src operand take part in the
116 // logical operation performed on the contents (in those positions) of the dst operand.
117 // - The logical operation that is performed on the dst operand is one of
118 // o insert the selected bits (replacing the original contents of those bit positions)
119 // o and the selected bits with the corresponding bits of the dst operand
120 // o or the selected bits with the corresponding bits of the dst operand
121 // o xor the selected bits with the corresponding bits of the dst operand
122 // - For clear_dst == true, the destination register is cleared before the bits are inserted.
123 // For clear_dst == false, only the bit positions that get data inserted from src
124 // are changed. All other bit positions remain unchanged.
125 // - For test_only == true, the result of the logicalOP is only used to set the condition code, dst remains unchanged.
126 // For test_only == false, the result of the logicalOP replaces the selected bits of dst.
127 // - src32bit and dst32bit indicate the respective register is used as 32bit value only.
128 // Knowledge can simplify code generation.
129 //
130 // Here is an important performance note, valid for all <logicalOP>s except "insert":
131 // Due to the too complex nature of the operation, it cannot be done in a single cycle.
132 // Timing constraints require the instructions to be cracked into two micro-ops, taking
133 // one or two cycles each to execute. In some cases, an additional pipeline bubble might get added.
134 // Macroscopically, that makes up for a three- or four-cycle instruction where you would
135 // expect just a single cycle.
136 // It is thus not beneficial from a performance point of view to exploit those instructions.
137 // Other reasons (code compactness, register pressure, ...) might outweigh this penalty.
138 //
139 unsigned long create_mask(int lBitPos, int rBitPos);
140 void rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
141 int nRotate, bool src32bit, bool dst32bit, bool oneBits);
142 void rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
143 bool clear_dst);
144 void rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
145 bool test_only);
146 void rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
147 bool test_onlyt);
148 void rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos, int nRotate,
149 bool test_only);
150
151 void add64(Register r1, RegisterOrConstant inc);
152
153 // Helper function to multiply the 64bit contents of a register by a 16bit constant.
154 // The optimization tries to avoid the mghi instruction, since it uses the FPU for
155 // calculation and is thus rather slow.
156 //
157 // There is no handling for special cases, e.g. cval==0 or cval==1.
158 //
159 // Returns len of generated code block.
160 unsigned int mul_reg64_const16(Register rval, Register work, int cval);
161
162 // Generic operation r1 := r2 + imm.
163 void add2reg (Register r1, int64_t imm, Register r2 = noreg);
164 void add2reg_32(Register r1, int64_t imm, Register r2 = noreg);
165
166 // Generic operation r := b + x + d.
167 void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg);
168
169 // Add2mem* methods for direct memory increment.
170 void add2mem_32(const Address &a, int64_t imm, Register tmp);
171 void add2mem_64(const Address &a, int64_t imm, Register tmp);
172
173 // *((int8_t*)(dst)) |= imm8
174 inline void or2mem_8(Address& dst, int64_t imm8);
175
176 // Load values by size and signedness.
177 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
178 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
179
180 // Load values with large offsets to base address.
181 private:
182 int split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate);
183 public:
184 void load_long_largeoffset(Register t, int64_t si20, Register a, Register tmp);
185 void load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);
186 void load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp);
187
188 private:
189 long toc_distance();
190 public:
191 void load_toc(Register Rtoc);
192 void load_long_pcrelative(Register Rdst, address dataLocation);
193 static int load_long_pcrelative_size() { return 6; }
194 void load_addr_pcrelative(Register Rdst, address dataLocation);
195 static int load_addr_pcrel_size() { return 6; } // Just a LARL.
196
197 // Load a value from memory and test (set CC).
198 void load_and_test_byte (Register dst, const Address &a);
199 void load_and_test_short (Register dst, const Address &a);
200 void load_and_test_int (Register dst, const Address &a);
201 void load_and_test_int2long(Register dst, const Address &a);
202 void load_and_test_long (Register dst, const Address &a);
203
204 // Test a bit in memory. Result is reflected in CC.
205 void testbit(const Address &a, unsigned int bit);
206 void testbit_ushort(const Address &a, unsigned int bit);
207 // Test a bit in a register. Result is reflected in CC.
208 void testbit(Register r, unsigned int bitPos);
209
210 void prefetch_read(Address a);
211 void prefetch_update(Address a);
212
213 // Clear a register, i.e. load const zero into reg. Return len (in bytes) of
214 // generated instruction(s).
215 // whole_reg: Clear 64 bits if true, 32 bits otherwise.
216 // set_cc: Use instruction that sets the condition code, if true.
217 int clear_reg(Register r, bool whole_reg = true, bool set_cc = true);
218
219 #ifdef ASSERT
220 int preset_reg(Register r, unsigned long pattern, int pattern_len);
221 #endif
222
223 // Clear (store zeros) a small piece of memory.
224 // CAUTION: Do not use this for atomic memory clearing. Use store_const() instead.
225 // addr: Address descriptor of memory to clear.
226 // Index register will not be used!
227 // size: Number of bytes to clear.
228 void clear_mem(const Address& addr, unsigned size);
229
230 // Move immediate values to memory. Currently supports 32 and 64 bit stores,
231 // but may be extended to 16 bit store operation, if needed.
232 // For details, see implementation in *.cpp file.
233 int store_const(const Address &dest, long imm,
234 unsigned int lm, unsigned int lc,
235 Register scratch = Z_R0);
236 inline int store_const(const Address &dest, long imm,
237 Register scratch = Z_R0, bool is_long = true);
238
239 // Move/initialize arbitrarily large memory area. No check for destructive overlap.
240 // Being interruptible, these instructions need a retry-loop.
241 void move_long_ext(Register dst, Register src, unsigned int pad);
242
243 void compare_long_ext(Register left, Register right, unsigned int pad);
244 void compare_long_uni(Register left, Register right, unsigned int pad);
245
246 void search_string(Register end, Register start);
247 void search_string_uni(Register end, Register start);
248
249 // Translate instructions
250 // Being interruptible, these instructions need a retry-loop.
251 void translate_oo(Register dst, Register src, uint mask);
252 void translate_ot(Register dst, Register src, uint mask);
253 void translate_to(Register dst, Register src, uint mask);
254 void translate_tt(Register dst, Register src, uint mask);
255
256 // Crypto instructions.
257 // Being interruptible, these instructions need a retry-loop.
258 void cksm(Register crcBuff, Register srcBuff);
259 void km( Register dstBuff, Register srcBuff);
260 void kmc( Register dstBuff, Register srcBuff);
261 void kmctr(Register dstBuff, Register ctrBuff, Register srcBuff);
262 void kimd(Register srcBuff);
263 void klmd(Register srcBuff);
264 void kmac(Register srcBuff);
265
266 // nop padding
267 void align(int modulus);
268 void align(int modulus, int target);
269 void align_address(int modulus);
270
271 //
272 // Constants, loading constants, TOC support
273 //
274
275 // Load generic address: d <- base(a) + index(a) + disp(a).
276 inline void load_address(Register d, const Address &a);
277 // Load absolute address (and try to optimize).
278 void load_absolute_address(Register d, address addr);
279
280 // Address of Z_ARG1 and argument_offset.
281 // If temp_reg == arg_slot, arg_slot will be overwritten.
282 Address argument_address(RegisterOrConstant arg_slot,
283 Register temp_reg = noreg,
284 int64_t extra_slot_offset = 0);
285
286 // Load a narrow ptr constant (oop or klass ptr).
287 void load_narrow_oop( Register t, narrowOop a);
288 void load_narrow_klass(Register t, Klass* k);
289
290 static bool is_load_const_32to64(address pos);
291 static bool is_load_narrow_oop(address pos) { return is_load_const_32to64(pos); }
292 static bool is_load_narrow_klass(address pos) { return is_load_const_32to64(pos); }
293
294 static int load_const_32to64_size() { return 6; }
295 static bool load_narrow_oop_size() { return load_const_32to64_size(); }
296 static bool load_narrow_klass_size() { return load_const_32to64_size(); }
297
298 static int patch_load_const_32to64(address pos, int64_t a);
299 static int patch_load_narrow_oop(address pos, oop o);
300 static int patch_load_narrow_klass(address pos, Klass* k);
301
302 // cOops. CLFI exploit.
303 void compare_immediate_narrow_oop(Register oop1, narrowOop oop2);
304 void compare_immediate_narrow_klass(Register op1, Klass* op2);
305 static bool is_compare_immediate32(address pos);
306 static bool is_compare_immediate_narrow_oop(address pos);
307 static bool is_compare_immediate_narrow_klass(address pos);
308 static int compare_immediate_narrow_size() { return 6; }
309 static int compare_immediate_narrow_oop_size() { return compare_immediate_narrow_size(); }
310 static int compare_immediate_narrow_klass_size() { return compare_immediate_narrow_size(); }
311 static int patch_compare_immediate_32(address pos, int64_t a);
312 static int patch_compare_immediate_narrow_oop(address pos, oop o);
313 static int patch_compare_immediate_narrow_klass(address pos, Klass* k);
314
315 // Load a 32bit constant into a 64bit register.
316 void load_const_32to64(Register t, int64_t x, bool sign_extend=true);
317 // Load a 64 bit constant.
318 void load_const(Register t, long a);
319 inline void load_const(Register t, void* a);
320 inline void load_const(Register t, Label& L);
321 inline void load_const(Register t, const AddressLiteral& a);
322 // Get the 64 bit constant from a `load_const' sequence.
323 static long get_const(address load_const);
324 // Patch the 64 bit constant of a `load_const' sequence. This is a low level
325 // procedure. It neither flushes the instruction cache nor is it atomic.
326 static void patch_const(address load_const, long x);
327 static int load_const_size() { return 12; }
328
329 // Turn a char into boolean. NOTE: destroys r.
330 void c2bool(Register r, Register t = Z_R0);
331
332 // Optimized version of load_const for constants that do not need to be
333 // loaded by a sequence of instructions of fixed length and that do not
334 // need to be patched.
335 int load_const_optimized_rtn_len(Register t, long x, bool emit);
336 inline void load_const_optimized(Register t, long x);
337 inline void load_const_optimized(Register t, void* a);
338 inline void load_const_optimized(Register t, Label& L);
339 inline void load_const_optimized(Register t, const AddressLiteral& a);
340
341 public:
342
343 //----------------------------------------------------------
344 // oops in code -------------
345 // including compressed oops support -------------
346 //----------------------------------------------------------
347
348 // Metadata in code that we have to keep track of.
349 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
350 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
351
352 // allocate_index
353 AddressLiteral allocate_oop_address(jobject obj);
354 // find_index
355 AddressLiteral constant_oop_address(jobject obj);
356 // Uses allocate_oop_address.
357 inline void set_oop (jobject obj, Register d);
358 // Uses constant_oop_address.
359 inline void set_oop_constant(jobject obj, Register d);
360 // Uses constant_metadata_address.
361 inline bool set_metadata_constant(Metadata* md, Register d);
362
363 //
364 // branch, jump
365 //
366
367 // Use one generic function for all branch patches.
368 static unsigned long patched_branch(address dest_pos, unsigned long inst, address inst_pos);
369
370 void pd_patch_instruction(address branch, address target, const char* file, int line);
371
372 // Extract relative address from "relative" instructions.
373 static long get_pcrel_offset(unsigned long inst);
374 static long get_pcrel_offset(address pc);
375 static address get_target_addr_pcrel(address pc);
376
377 static inline bool is_call_pcrelative_short(unsigned long inst);
378 static inline bool is_call_pcrelative_long(unsigned long inst);
379 static inline bool is_branch_pcrelative_short(unsigned long inst);
380 static inline bool is_branch_pcrelative_long(unsigned long inst);
381 static inline bool is_compareandbranch_pcrelative_short(unsigned long inst);
382 static inline bool is_branchoncount_pcrelative_short(unsigned long inst);
383 static inline bool is_branchonindex32_pcrelative_short(unsigned long inst);
384 static inline bool is_branchonindex64_pcrelative_short(unsigned long inst);
385 static inline bool is_branchonindex_pcrelative_short(unsigned long inst);
386 static inline bool is_branch_pcrelative16(unsigned long inst);
387 static inline bool is_branch_pcrelative32(unsigned long inst);
388 static inline bool is_branch_pcrelative(unsigned long inst);
389 static inline bool is_load_pcrelative_long(unsigned long inst);
390 static inline bool is_misc_pcrelative_long(unsigned long inst);
391 static inline bool is_pcrelative_short(unsigned long inst);
392 static inline bool is_pcrelative_long(unsigned long inst);
393 // PCrelative TOC access. Variants with address argument.
394 static inline bool is_load_pcrelative_long(address iLoc);
395 static inline bool is_pcrelative_short(address iLoc);
396 static inline bool is_pcrelative_long(address iLoc);
397
398 static inline bool is_pcrelative_instruction(address iloc);
399 static inline bool is_load_addr_pcrel(address a);
400
401 static void patch_target_addr_pcrel(address pc, address con);
402 static void patch_addr_pcrel(address pc, address con) {
403 patch_target_addr_pcrel(pc, con); // Just delegate. This is only for nativeInst_s390.cpp.
404 }
405
406 //---------------------------------------------------------
407 // Some macros for more comfortable assembler programming.
408 //---------------------------------------------------------
409
410 // NOTE: pass NearLabel T to signal that the branch target T will be bound to a near address.
411
412 void compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
413 void compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
414 void compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
415 void compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target);
416
417 void branch_optimized(Assembler::branch_condition cond, address branch_target);
418 void branch_optimized(Assembler::branch_condition cond, Label& branch_target);
419 void compare_and_branch_optimized(Register r1,
420 Register r2,
421 Assembler::branch_condition cond,
422 address branch_addr,
423 bool len64,
424 bool has_sign);
425 void compare_and_branch_optimized(Register r1,
426 jlong x2,
427 Assembler::branch_condition cond,
428 Label& branch_target,
429 bool len64,
430 bool has_sign);
431 void compare_and_branch_optimized(Register r1,
432 Register r2,
433 Assembler::branch_condition cond,
434 Label& branch_target,
435 bool len64,
436 bool has_sign);
437
438 //
439 // Support for frame handling
440 //
441 // Specify the register that should be stored as the return pc in the
442 // current frame (default is R14).
443 inline void save_return_pc(Register pc = Z_R14);
444 inline void restore_return_pc();
445
446 // Get current PC.
447 address get_PC(Register result);
448
449 // Get current PC + offset. Offset given in bytes, must be even!
450 address get_PC(Register result, int64_t offset);
451
452 // Get size of instruction at pc (which must point to valid code).
453 void instr_size(Register size, Register pc);
454
455 // Accessing, and in particular modifying, a stack location is only safe if
456 // the stack pointer (Z_SP) is set such that the accessed stack location is
457 // in the reserved range.
458 //
459 // From a performance point of view, it is desirable not to change the SP
460 // first and then immediately use it to access the freshly reserved space.
461 // That opens a small gap, though. If, just after storing some value (the
462 // frame pointer) into the to-be-reserved space, an interrupt is caught,
463 // the handler might use the space beyond Z_SP for it's own purpose.
464 // If that happens, the stored value might get altered.
465
466 // Resize current frame either relatively wrt to current SP or absolute.
467 void resize_frame_sub(Register offset, Register fp, bool load_fp=true);
468 void resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp);
469 void resize_frame_absolute(Register addr, Register fp, bool load_fp);
470 void resize_frame(RegisterOrConstant offset, Register fp, bool load_fp=true);
471
472 // Push a frame of size bytes, if copy_sp is false, old_sp must already
473 // contain a copy of Z_SP.
474 void push_frame(Register bytes, Register old_sp, bool copy_sp = true, bool bytes_with_inverted_sign = false);
475
476 // Push a frame of size `bytes'. no abi space provided.
477 // Don't rely on register locking, instead pass a scratch register
478 // (Z_R0 by default).
479 // CAUTION! passing registers >= Z_R2 may produce bad results on
480 // old CPUs!
481 unsigned int push_frame(unsigned int bytes, Register scratch = Z_R0);
482
483 // Push a frame of size `bytes' with abi160 on top.
484 unsigned int push_frame_abi160(unsigned int bytes);
485
486 // Pop current C frame.
487 void pop_frame();
488 // Pop current C frame and restore return PC register (Z_R14).
489 void pop_frame_restore_retPC(int frame_size_in_bytes);
490
491 #ifdef ASSERT
492 void clobber_volatile_registers(Register excluded_register[], int n);
493 #endif // ASSERT
494
495 //
496 // Calls
497 //
498
499 private:
500 address _last_calls_return_pc;
501
502 public:
503 // Support for VM calls. This is the base routine called by the
504 // different versions of call_VM_leaf. The interpreter may customize
505 // this version by overriding it for its purposes (e.g., to
506 // save/restore additional registers when doing a VM call).
507 void call_VM_leaf_base(address entry_point);
508 void call_VM_leaf_base(address entry_point, bool allow_relocation);
509
510 // It is imperative that all calls into the VM are handled via the
511 // call_VM macros. They make sure that the stack linkage is setup
512 // correctly. Call_VM's correspond to ENTRY/ENTRY_X entry points
513 // while call_VM_leaf's correspond to LEAF entry points.
514 //
515 // This is the base routine called by the different versions of
516 // call_VM. The interpreter may customize this version by overriding
517 // it for its purposes (e.g., to save/restore additional registers
518 // when doing a VM call).
519
520 // If no last_java_sp is specified (noreg) then SP will be used instead.
521
522 virtual void call_VM_base(
523 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise.
524 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
525 address entry_point, // The entry point.
526 bool check_exception); // Flag which indicates if exception should be checked.
527 virtual void call_VM_base(
528 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise.
529 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
530 address entry_point, // The entry point.
531 bool allow_relocation, // Flag to request generation of relocatable code.
532 bool check_exception, // Flag which indicates if exception should be checked.
533 Label *last_java_pc);
534
535 // Call into the VM.
536 // Passes the thread pointer (in Z_ARG1) as a prepended argument.
537 // Makes sure oop return values are visible to the GC.
538 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true, Label* last_java_pc = nullptr);
539 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
540 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
541 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
542 Register arg_3, bool check_exceptions = true);
543
544 void call_VM_static(Register oop_result, address entry_point, bool check_exceptions = true);
545 void call_VM_static(Register oop_result, address entry_point, Register arg_1, Register arg_2,
546 Register arg_3, bool check_exceptions = true);
547
548 // Overloaded with last_java_sp.
549 void call_VM(Register oop_result, Register last_java_sp, address entry_point, bool check_exceptions = true);
550 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
551 Register arg_1, bool check_exceptions = true);
552 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
553 Register arg_1, Register arg_2, bool check_exceptions = true);
554 void call_VM(Register oop_result, Register last_java_sp, address entry_point,
555 Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
556
557 void call_VM_leaf(address entry_point);
558 void call_VM_leaf(address entry_point, Register arg_1);
559 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
560 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
561
562 // Really static VM leaf call (never patched).
563 void call_VM_leaf_static(address entry_point);
564 void call_VM_leaf_static(address entry_point, Register arg_1);
565 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2);
566 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2, Register arg_3);
567
568 // Call a C function via its function entry. Updates and returns _last_calls_return_pc.
569 inline address call(Register function_entry);
570 inline address call_c(Register function_entry);
571 address call_c(address function_entry);
572 // Variant for really static (non-relocatable) calls which are never patched.
573 address call_c_static(address function_entry);
574 // TOC or pc-relative call + emits a runtime_call relocation.
575 address call_c_opt(address function_entry);
576
577 inline address call_stub(Register function_entry);
578 inline address call_stub(address function_entry);
579
580 // Get the pc where the last call will return to. Returns _last_calls_return_pc.
581 inline address last_calls_return_pc();
582
583 void post_call_nop();
584
585 static int ic_check_size();
586 int ic_check(int end_alignment);
587
588 private:
589 static bool is_call_far_patchable_variant0_at(address instruction_addr); // Dynamic TOC: load target addr from CP and call.
590 static bool is_call_far_patchable_variant2_at(address instruction_addr); // PC-relative call, prefixed with NOPs.
591
592
593 public:
594 bool call_far_patchable(address target, int64_t toc_offset);
595 static bool is_call_far_patchable_at(address inst_start); // All supported forms of patchable calls.
596 static bool is_call_far_patchable_pcrelative_at(address inst_start); // Pc-relative call with leading nops.
597 static bool is_call_far_pcrelative(address instruction_addr); // Pure far pc-relative call, with one leading size adjustment nop.
598 static void set_dest_of_call_far_patchable_at(address inst_start, address target, int64_t toc_offset);
599 static address get_dest_of_call_far_patchable_at(address inst_start, address toc_start);
600
601 void align_call_far_patchable(address pc);
602
603 // PCrelative TOC access.
604
605 // This value is independent of code position - constant for the lifetime of the VM.
606 static int call_far_patchable_size() {
607 return load_const_from_toc_size() + call_byregister_size();
608 }
609
610 static int call_far_patchable_ret_addr_offset() { return call_far_patchable_size(); }
611
612 static bool call_far_patchable_requires_alignment_nop(address pc) {
613 int size = call_far_patchable_size();
614 return ((intptr_t)(pc + size) & 0x03L) != 0;
615 }
616
617 // END OF PCrelative TOC access.
618
619 static int jump_byregister_size() { return 2; }
620 static int jump_pcrelative_size() { return 4; }
621 static int jump_far_pcrelative_size() { return 6; }
622 static int call_byregister_size() { return 2; }
623 static int call_pcrelative_size() { return 4; }
624 static int call_far_pcrelative_size() { return 2 + 6; } // Prepend each BRASL with a nop.
625 static int call_far_pcrelative_size_raw() { return 6; } // Prepend each BRASL with a nop.
626
627 //
628 // Java utilities
629 //
630
631 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
632 // The implementation is only non-empty for the InterpreterMacroAssembler,
633 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
634 virtual void check_and_handle_popframe(Register java_thread);
635 virtual void check_and_handle_earlyret(Register java_thread);
636
637 // Polling page support.
638 enum poll_mask {
639 mask_stackbang = 0xde, // 222 (dec)
640 mask_safepoint = 0x6f, // 111 (dec)
641 mask_profiling = 0xba // 186 (dec)
642 };
643
644 // Read from the polling page.
645 void load_from_polling_page(Register polling_page_address, int64_t offset = 0);
646
647 // Check if given instruction is a read from the polling page
648 // as emitted by load_from_polling_page.
649 static bool is_load_from_polling_page(address instr_loc);
650 // Extract poll address from instruction and ucontext.
651 static address get_poll_address(address instr_loc, void* ucontext);
652 // Extract poll register from instruction.
653 static uint get_poll_register(address instr_loc);
654
655 // Check if safepoint requested and if so branch
656 void safepoint_poll(Label& slow_path, Register temp_reg);
657
658 // Stack overflow checking
659 void bang_stack_with_offset(int offset);
660
661 // Check for reserved stack access in method being exited. If the reserved
662 // stack area was accessed, protect it again and throw StackOverflowError.
663 // Uses Z_R1.
664 void reserved_stack_check(Register return_pc);
665
666 // Atomics
667 // -- none?
668
669 void tlab_allocate(Register obj, // Result: pointer to object after successful allocation
670 Register var_size_in_bytes, // Object size in bytes if unknown at compile time; invalid otherwise.
671 int con_size_in_bytes, // Object size in bytes if known at compile time.
672 Register t1, // temp register
673 Label& slow_case); // Continuation point if fast allocation fails.
674
675 // Emitter for interface method lookup.
676 // input: recv_klass, intf_klass, itable_index
677 // output: method_result
678 // kills: itable_index, temp1_reg, Z_R0, Z_R1
679 void lookup_interface_method(Register recv_klass,
680 Register intf_klass,
681 RegisterOrConstant itable_index,
682 Register method_result,
683 Register temp1_reg,
684 Label& no_such_interface,
685 bool return_method = true);
686
687 // virtual method calling
688 void lookup_virtual_method(Register recv_klass,
689 RegisterOrConstant vtable_index,
690 Register method_result);
691
692 // Factor out code to call ic_miss_handler.
693 unsigned int call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch);
694 void nmethod_UEP(Label& ic_miss);
695
696 // Emitters for "partial subtype" checks.
697
698 // Test sub_klass against super_klass, with fast and slow paths.
699
700 // The fast path produces a tri-state answer: yes / no / maybe-slow.
701 // One of the three labels can be null, meaning take the fall-through.
702 // If super_check_offset is -1, the value is loaded up from super_klass.
703 // No registers are killed, except temp_reg and temp2_reg.
704 // If super_check_offset is not -1, temp1_reg is not used and can be noreg.
705 void check_klass_subtype_fast_path(Register sub_klass,
706 Register super_klass,
707 Register temp1_reg,
708 Label* L_success,
709 Label* L_failure,
710 Label* L_slow_path,
711 Register super_check_offset = noreg);
712
713 // The rest of the type check; must be wired to a corresponding fast path.
714 // It does not repeat the fast path logic, so don't use it standalone.
715 // The temp_reg can be noreg, if no temps are available.
716 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
717 // Updates the sub's secondary super cache as necessary.
718 void check_klass_subtype_slow_path(Register Rsubklass,
719 Register Rsuperklas,
720 Register Rarray_ptr, // tmp
721 Register Rlength, // tmp
722 Label* L_success,
723 Label* L_failure,
724 bool set_cond_codes = false);
725
726 void check_klass_subtype_slow_path_linear(Register sub_klass,
727 Register super_klass,
728 Register temp_reg,
729 Register temp2_reg,
730 Label* L_success,
731 Label* L_failure,
732 bool set_cond_codes = false);
733
734 void check_klass_subtype_slow_path_table(Register sub_klass,
735 Register super_klass,
736 Register temp_reg,
737 Register temp2_reg,
738 Register temp3_reg,
739 Register temp4_reg,
740 Register result_reg,
741 Label* L_success,
742 Label* L_failure,
743 bool set_cond_codes = false);
744
745 // If r is valid, return r.
746 // If r is invalid, remove a register r2 from available_regs, add r2
747 // to regs_to_push, then return r2.
748 Register allocate_if_noreg(const Register r,
749 RegSetIterator<Register> &available_regs,
750 RegSet ®s_to_push);
751
752 void repne_scan(Register r_addr, Register r_value, Register r_count, Register r_scratch);
753
754 // Secondary subtype checking
755 void lookup_secondary_supers_table_var(Register sub_klass,
756 Register r_super_klass,
757 Register temp1,
758 Register temp2,
759 Register temp3,
760 Register temp4,
761 Register result);
762
763 void lookup_secondary_supers_table_const(Register r_sub_klass,
764 Register r_super_klass,
765 Register r_temp1,
766 Register r_temp2,
767 Register r_temp3,
768 Register r_temp4,
769 Register r_result,
770 u1 super_klass_slot);
771
772 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
773 Register r_array_base,
774 Register r_array_index,
775 Register r_bitmap,
776 Register r_temp,
777 Register r_result,
778 bool is_stub);
779
780 void verify_secondary_supers_table(Register r_sub_klass,
781 Register r_super_klass,
782 Register r_result /* expected */,
783 Register r_temp1,
784 Register r_temp2,
785 Register r_temp3);
786
787 // Simplified, combined version, good for typical uses.
788 // Falls through on failure.
789 void check_klass_subtype(Register sub_klass,
790 Register super_klass,
791 Register temp1_reg,
792 Register temp2_reg,
793 Label& L_success);
794
795 void clinit_barrier(Register klass,
796 Register thread,
797 Label* L_fast_path = nullptr,
798 Label* L_slow_path = nullptr);
799
800 // Increment a counter at counter_address when the eq condition code is set.
801 // Kills registers tmp1_reg and tmp2_reg and preserves the condition code.
802 void increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg);
803
804 void fast_lock(Register basic_lock, Register obj, Register tmp1, Register tmp2, Label& slow);
805 void fast_unlock(Register obj, Register tmp1, Register tmp2, Label& slow);
806 void compiler_fast_lock_object(Register obj, Register box, Register tmp1, Register tmp2);
807 void compiler_fast_unlock_object(Register obj, Register box, Register tmp1, Register tmp2);
808
809 void resolve_jobject(Register value, Register tmp1, Register tmp2);
810 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
811
812 // Support for last Java frame (but use call_VM instead where possible).
813 private:
814 void set_last_Java_frame(Register last_Java_sp, Register last_Java_pc, bool allow_relocation);
815 void reset_last_Java_frame(bool check_last_java_sp, bool allow_relocation);
816 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, bool allow_relocation, Label* last_java_pc = nullptr);
817 public:
818 inline void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
819 inline void set_last_Java_frame_static(Register last_java_sp, Register last_Java_pc);
820 inline void reset_last_Java_frame(bool check_last_java_sp = true);
821 inline void reset_last_Java_frame_static(bool check_last_java_sp = true);
822 inline void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, Label* jpc = nullptr);
823 inline void set_top_ijava_frame_at_SP_as_last_Java_frame_static(Register sp, Register tmp1);
824
825 void set_thread_state(JavaThreadState new_state);
826
827 // Read vm result from thread.
828 void get_vm_result_oop (Register oop_result);
829 void get_vm_result_metadata(Register result);
830
831 // Vm result is currently getting hijacked to for oop preservation.
832 void set_vm_result(Register oop_result);
833
834 // Support for null-checks
835 //
836 // Generates code that causes a null OS exception if the content of reg is null.
837 // If the accessed location is M[reg + offset] and the offset is known, provide the
838 // offset. No explicit code generation is needed if the offset is within a certain
839 // range (0 <= offset <= page_size).
840 //
841 // %%%%%% Currently not done for z/Architecture
842
843 void null_check(Register reg, Register tmp = Z_R0, int64_t offset = -1);
844 static bool needs_explicit_null_check(intptr_t offset); // Implemented in shared file ?!
845 static bool uses_implicit_null_check(void* address);
846
847 // Klass oop manipulations if compressed.
848 void encode_klass_not_null(Register dst, Register src = noreg);
849 void decode_klass_not_null(Register dst, Register src);
850 void decode_klass_not_null(Register dst);
851 void load_klass(Register klass, Address mem);
852 void load_klass(Register klass, Register src_oop);
853 void store_klass(Register klass, Register dst_oop, Register ck = noreg); // Klass will get compressed if ck not provided.
854 void store_klass_gap(Register s, Register dst_oop);
855 void load_narrow_klass_compact(Register dst, Register src);
856 // Compares the narrow Klass pointer of an object to a given narrow Klass
857 void cmp_klass(Register klass, Register obj, Register tmp);
858 // Compares the Klass pointer of two objects obj1 and obj2. Result is in the condition flags.
859 // Uses tmp1 and tmp2 as temporary registers.
860 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
861
862 // This function calculates the size of the code generated by
863 // decode_klass_not_null(register dst)
864 // when Universe::heap() isn't null. Hence, if the instructions
865 // it generates change, then this method needs to be updated.
866 static int instr_size_for_decode_klass_not_null();
867
868 void encode_heap_oop(Register oop);
869 void encode_heap_oop_not_null(Register oop);
870
871 static int get_oop_base_pow2_offset(uint64_t oop_base);
872 int get_oop_base(Register Rbase, uint64_t oop_base);
873 int get_oop_base_complement(Register Rbase, uint64_t oop_base);
874 void compare_heap_oop(Register Rop1, Address mem, bool maybenull);
875 void compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybenull);
876
877 // Access heap oop, handle encoding and GC barriers.
878 void access_store_at(BasicType type, DecoratorSet decorators,
879 const Address& addr, Register val,
880 Register tmp1, Register tmp2, Register tmp3);
881 void access_load_at(BasicType type, DecoratorSet decorators,
882 const Address& addr, Register dst,
883 Register tmp1, Register tmp2, Label *is_null = nullptr);
884
885 public:
886 // tmp1 and tmp2 are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
887 void load_heap_oop(Register dest, const Address &a,
888 Register tmp1, Register tmp2,
889 DecoratorSet decorators = 0, Label *is_null = nullptr);
890 void store_heap_oop(Register Roop, const Address &a,
891 Register tmp1, Register tmp2, Register tmp3,
892 DecoratorSet decorators = 0);
893
894 void oop_encoder(Register Rdst, Register Rsrc, bool maybenull,
895 Register Rbase = Z_R1, int pow2_offset = -1, bool only32bitValid = false);
896 void oop_decoder(Register Rdst, Register Rsrc, bool maybenull,
897 Register Rbase = Z_R1, int pow2_offset = -1);
898
899 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
900 void load_method_holder(Register holder, Register method);
901
902 //--------------------------
903 //--- Operations on arrays.
904 //--------------------------
905 unsigned int Clear_Array(Register cnt_arg, Register base_pointer_arg, Register odd_tmp_reg);
906 unsigned int Clear_Array_Const(long cnt, Register base);
907 unsigned int Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register odd_tmp_reg);
908 unsigned int CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
909 Register cnt_reg,
910 Register tmp1_reg, Register tmp2_reg);
911
912
913 // Emit an oop const to the constant pool and set a relocation info
914 // with address current_pc. Return the TOC offset of the constant.
915 int store_const_in_toc(AddressLiteral& val);
916 int store_oop_in_toc(AddressLiteral& oop);
917 // Emit an oop const to the constant pool via store_oop_in_toc, or
918 // emit a scalar const to the constant pool via store_const_in_toc,
919 // and load the constant into register dst.
920 bool load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg);
921 // Get CPU version dependent size of load_const sequence.
922 // The returned value is valid only for code sequences
923 // generated by load_const, not load_const_optimized.
924 static int load_const_from_toc_size() {
925 return load_long_pcrelative_size();
926 }
927 bool load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg);
928 static intptr_t get_const_from_toc(address pc);
929 static void set_const_in_toc(address pc, unsigned long new_data, CodeBlob *cb);
930
931 // Dynamic TOC.
932 static bool is_load_const(address a);
933 static bool is_load_const_from_toc_pcrelative(address a);
934 static bool is_load_const_from_toc(address a) { return is_load_const_from_toc_pcrelative(a); }
935
936 // PCrelative TOC access.
937 static bool is_call_byregister(address a) { return is_z_basr(*(short*)a); }
938 static bool is_load_const_from_toc_call(address a);
939 static bool is_load_const_call(address a);
940 static int load_const_call_size() { return load_const_size() + call_byregister_size(); }
941 static int load_const_from_toc_call_size() { return load_const_from_toc_size() + call_byregister_size(); }
942 // Offset is +/- 2**32 -> use long.
943 static long get_load_const_from_toc_offset(address a);
944
945 // Bit operations for single register operands.
946 inline void lshift(Register r, int places, bool doubl = true); // <<
947 inline void rshift(Register r, int places, bool doubl = true); // >>
948
949 //
950 // Debugging
951 //
952
953 // Assert on CC (condition code in CPU state).
954 void asm_assert(branch_condition cond, const char* msg, int id, bool is_static=true);
955 void asm_assert(bool check_equal, const char* msg, int id);
956
957 private:
958 // Emit assertions.
959 void asm_assert_mems_zero(bool check_equal, bool allow_relocation, int size, int64_t mem_offset,
960 Register mem_base, const char* msg, int id);
961
962 public:
963 inline void asm_assert_mem4_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
964 asm_assert_mems_zero(true, true, 4, mem_offset, mem_base, msg, id);
965 }
966 inline void asm_assert_mem8_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
967 asm_assert_mems_zero(true, true, 8, mem_offset, mem_base, msg, id);
968 }
969 inline void asm_assert_mem4_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
970 asm_assert_mems_zero(false, true, 4, mem_offset, mem_base, msg, id);
971 }
972 inline void asm_assert_mem8_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) {
973 asm_assert_mems_zero(false, true, 8, mem_offset, mem_base, msg, id);
974 }
975 inline void asm_assert_mem4_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
976 asm_assert_mems_zero(true, false, 4, mem_offset, mem_base, msg, id);
977 }
978 inline void asm_assert_mem8_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
979 asm_assert_mems_zero(true, false, 8, mem_offset, mem_base, msg, id);
980 }
981 inline void asm_assert_mem4_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
982 asm_assert_mems_zero(false, false, 4, mem_offset, mem_base, msg, id);
983 }
984 inline void asm_assert_mem8_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) {
985 asm_assert_mems_zero(false, false, 8, mem_offset, mem_base, msg, id);
986 }
987 void asm_assert_frame_size(Register expected_size, Register tmp, const char* msg, int id);
988
989 // Load bad values into registers that are nonvolatile according to the ABI except Z_thread.
990 // This is done after vthread preemption and before vthread resume.
991 void clobber_nonvolatile_registers() NOT_DEBUG_RETURN;
992
993 // Save and restore functions: Exclude Z_R0.
994 void save_volatile_regs( Register dst, int offset, bool include_fp, bool include_flags);
995 void restore_volatile_regs(Register src, int offset, bool include_fp, bool include_flags);
996
997 // Only if +VerifyOops.
998 // Kills Z_R0.
999 void verify_oop(Register reg, const char* s = "broken oop");
1000 // Kills Z_R0, condition code.
1001 void verify_oop_addr(Address addr, const char* msg = "contains broken oop");
1002
1003 // TODO: verify_method and klass metadata (compare against vptr?).
1004 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1005 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
1006
1007 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1008 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1009
1010 private:
1011 // Generate printout in stop().
1012 static const char* stop_types[];
1013 enum {
1014 stop_stop = 0,
1015 stop_untested = 1,
1016 stop_unimplemented = 2,
1017 stop_shouldnotreachhere = 3,
1018 stop_end = 4
1019 };
1020 // Prints msg and stops execution.
1021 void stop(int type, const char* msg, int id = 0);
1022 address stop_chain(address reentry, int type, const char* msg, int id, bool allow_relocation); // Non-relocateable code only!!
1023 void stop_static(int type, const char* msg, int id); // Non-relocateable code only!!
1024
1025 public:
1026
1027 // Prints msg and stops.
1028 address stop_chain( address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, true); }
1029 address stop_chain_static(address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, false); }
1030 void stop_static (const char* msg = "", int id = 0) { stop_static(stop_stop, msg, id); }
1031 void stop (const char* msg = "", int id = 0) { stop(stop_stop, msg, id); }
1032 void untested (const char* msg = "", int id = 0) { stop(stop_untested, msg, id); }
1033 void unimplemented(const char* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); }
1034 void should_not_reach_here(const char* msg = "", int id = -1) { stop(stop_shouldnotreachhere, msg, id); }
1035
1036 // Factor out part of stop into subroutine to save space.
1037 void stop_subroutine();
1038
1039 // Prints msg, but don't stop.
1040 void warn(const char* msg);
1041
1042 //-----------------------------
1043 //--- basic block tracing code
1044 //-----------------------------
1045 void trace_basic_block(uint i);
1046 void init_basic_block_trace();
1047 // Number of bytes a basic block gets larger due to the tracing code macro (worst case).
1048 // Currently, worst case is 48 bytes. 64 puts us securely on the safe side.
1049 static int basic_blck_trace_blk_size_incr() { return 64; }
1050
1051 // Write pattern 0x0101010101010101 in region [low-before, high+after].
1052 // Low and high may be the same registers. Before and after are
1053 // the numbers of 8-byte words.
1054 void zap_from_to(Register low, Register high, Register tmp1 = Z_R0, Register tmp2 = Z_R1,
1055 int before = 0, int after = 0) PRODUCT_RETURN;
1056
1057 // Emitters for CRC32 calculation.
1058 // A note on invertCRC:
1059 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
1060 // CRC32 holds it's current crc value in the externally visible representation.
1061 // CRC32C holds it's current crc value in internal format, ready for updating.
1062 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
1063 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
1064 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
1065 private:
1066 void fold_byte_crc32(Register crc, Register table, Register val, Register tmp);
1067 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1068 void update_byte_crc32( Register crc, Register val, Register table);
1069 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
1070 Register data);
1071 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
1072 Register t0, Register t1, Register t2, Register t3);
1073 public:
1074 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
1075 bool invertCRC);
1076 void kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp,
1077 bool invertCRC);
1078 void kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
1079 Register t0, Register t1, Register t2, Register t3,
1080 bool invertCRC);
1081 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
1082 Register t0, Register t1, Register t2, Register t3,
1083 bool invertCRC);
1084
1085 // Emitters for BigInteger.multiplyToLen intrinsic
1086 // note: length of result array (zlen) is passed on the stack
1087 private:
1088 void add2_with_carry(Register dest_hi, Register dest_lo,
1089 Register src1, Register src2);
1090 void multiply_64_x_64_loop(Register x, Register xstart,
1091 Register x_xstart,
1092 Register y, Register y_idx, Register z,
1093 Register carry, Register product,
1094 Register idx, Register kdx);
1095 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1096 Register yz_idx, Register idx,
1097 Register carry, Register product, int offset);
1098 void multiply_128_x_128_loop(Register x_xstart,
1099 Register y, Register z,
1100 Register yz_idx, Register idx,
1101 Register jdx,
1102 Register carry, Register product,
1103 Register carry2);
1104 public:
1105 void multiply_to_len(Register x, Register xlen,
1106 Register y, Register ylen,
1107 Register z,
1108 Register tmp1, Register tmp2,
1109 Register tmp3, Register tmp4, Register tmp5);
1110
1111 // These generate optimized code for all supported s390 implementations, and are preferred for most uses.
1112 void pop_count_int(Register dst, Register src, Register tmp);
1113 void pop_count_long(Register dst, Register src, Register tmp);
1114
1115 // For legacy (pre-z15) use, but will work on all supported s390 implementations.
1116 void pop_count_int_without_ext3(Register dst, Register src, Register tmp);
1117 void pop_count_long_without_ext3(Register dst, Register src, Register tmp);
1118
1119 // Only for use on z15 or later s390 implementations.
1120 void pop_count_int_with_ext3(Register dst, Register src);
1121 void pop_count_long_with_ext3(Register dst, Register src);
1122
1123 void push_cont_fastpath();
1124 void pop_cont_fastpath();
1125
1126 void load_on_condition_imm_32(Register dst, int64_t i2, branch_condition cc);
1127 void load_on_condition_imm_64(Register dst, int64_t i2, branch_condition cc);
1128
1129 void profile_receiver_type(Register recv, Register mdp, int mdp_offset, Register tmp1);
1130
1131 // Inline type specific methods
1132 #include "asm/macroAssembler_common.hpp"
1133 };
1134
1135 #ifdef ASSERT
1136 // Return false (e.g. important for our impl. of virtual calls).
1137 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1138 #endif
1139
1140 #endif // CPU_S390_MACROASSEMBLER_S390_HPP