1 //
2 // Copyright (c) 2017, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2017, 2024 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alignment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to continue at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // ----------------------------
101 // Integer/Long Registers
102 // ----------------------------
103
104 // z/Architecture has 16 64-bit integer registers.
105
106 // types: v = volatile, nv = non-volatile, s = system
107 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
108 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
109 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
110 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
111 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
112 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
113 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
114 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
115 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
116 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
117 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
118 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
119 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
120 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
121 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
122 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
123 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
124 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
125 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
126 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
127 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
128 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
129 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
130 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
131 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
132 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
133 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
134 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
135 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
136 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
137 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
138 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
139
140 // ----------------------------
141 // Float/Double Registers
142 // ----------------------------
143
144 // The rules of ADL require that double registers be defined in pairs.
145 // Each pair must be two 32-bit values, but not necessarily a pair of
146 // single float registers. In each pair, ADLC-assigned register numbers
147 // must be adjacent, with the lower number even. Finally, when the
148 // CPU stores such a register pair to memory, the word associated with
149 // the lower ADLC-assigned number must be stored to the lower address.
150
151 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
152 // or double precision floating-point value.
153
154 // types: v = volatile, nv = non-volatile, s = system
155 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
156 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
157 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
158 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
159 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
160 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
161 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
162 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
163 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
164 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
165 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
166 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
167 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
168 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
169 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
170 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
171 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
172 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
173 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
174 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
175 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
176 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
177 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
178 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
179 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
180 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
181 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
182 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
183 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
184 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
185 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
186 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
187
188 // ----------------------------
189 // Vector Registers
190 // ----------------------------
191 // 1st 16 VRs are aliases for the FPRs which are already defined above.
192 reg_def Z_VR0 ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
193 reg_def Z_VR0_H ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
194 reg_def Z_VR0_J ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
195 reg_def Z_VR0_K ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
196
197 reg_def Z_VR1 ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
198 reg_def Z_VR1_H ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
199 reg_def Z_VR1_J ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
200 reg_def Z_VR1_K ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
201
202 reg_def Z_VR2 ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
203 reg_def Z_VR2_H ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
204 reg_def Z_VR2_J ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
205 reg_def Z_VR2_K ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
206
207 reg_def Z_VR3 ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
208 reg_def Z_VR3_H ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
209 reg_def Z_VR3_J ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
210 reg_def Z_VR3_K ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
211
212 reg_def Z_VR4 ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
213 reg_def Z_VR4_H ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
214 reg_def Z_VR4_J ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
215 reg_def Z_VR4_K ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
216
217 reg_def Z_VR5 ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
218 reg_def Z_VR5_H ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
219 reg_def Z_VR5_J ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
220 reg_def Z_VR5_K ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
221
222 reg_def Z_VR6 ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
223 reg_def Z_VR6_H ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
224 reg_def Z_VR6_J ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
225 reg_def Z_VR6_K ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
226
227 reg_def Z_VR7 ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
228 reg_def Z_VR7_H ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
229 reg_def Z_VR7_J ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
230 reg_def Z_VR7_K ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
231
232 reg_def Z_VR8 ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
233 reg_def Z_VR8_H ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
234 reg_def Z_VR8_J ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
235 reg_def Z_VR8_K ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
236
237 reg_def Z_VR9 ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
238 reg_def Z_VR9_H ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
239 reg_def Z_VR9_J ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
240 reg_def Z_VR9_K ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
241
242 reg_def Z_VR10 ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
243 reg_def Z_VR10_H ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
244 reg_def Z_VR10_J ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
245 reg_def Z_VR10_K ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
246
247 reg_def Z_VR11 ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
248 reg_def Z_VR11_H ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
249 reg_def Z_VR11_J ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
250 reg_def Z_VR11_K ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
251
252 reg_def Z_VR12 ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
253 reg_def Z_VR12_H ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
254 reg_def Z_VR12_J ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
255 reg_def Z_VR12_K ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
256
257 reg_def Z_VR13 ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
258 reg_def Z_VR13_H ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
259 reg_def Z_VR13_J ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
260 reg_def Z_VR13_K ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
261
262 reg_def Z_VR14 ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
263 reg_def Z_VR14_H ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
264 reg_def Z_VR14_J ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
265 reg_def Z_VR14_K ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
266
267 reg_def Z_VR15 ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
268 reg_def Z_VR15_H ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
269 reg_def Z_VR15_J ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
270 reg_def Z_VR15_K ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
271
272 reg_def Z_VR16 ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg() );
273 reg_def Z_VR16_H ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next() );
274 reg_def Z_VR16_J ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(2) );
275 reg_def Z_VR16_K ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(3) );
276
277 reg_def Z_VR17 ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg() );
278 reg_def Z_VR17_H ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next() );
279 reg_def Z_VR17_J ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(2) );
280 reg_def Z_VR17_K ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(3) );
281
282 reg_def Z_VR18 ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg() );
283 reg_def Z_VR18_H ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next() );
284 reg_def Z_VR18_J ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(2) );
285 reg_def Z_VR18_K ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(3) );
286
287 reg_def Z_VR19 ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg() );
288 reg_def Z_VR19_H ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next() );
289 reg_def Z_VR19_J ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(2) );
290 reg_def Z_VR19_K ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(3) );
291
292 reg_def Z_VR20 ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg() );
293 reg_def Z_VR20_H ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next() );
294 reg_def Z_VR20_J ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(2) );
295 reg_def Z_VR20_K ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(3) );
296
297 reg_def Z_VR21 ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg() );
298 reg_def Z_VR21_H ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next() );
299 reg_def Z_VR21_J ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(2) );
300 reg_def Z_VR21_K ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(3) );
301
302 reg_def Z_VR22 ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg() );
303 reg_def Z_VR22_H ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next() );
304 reg_def Z_VR22_J ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(2) );
305 reg_def Z_VR22_K ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(3) );
306
307 reg_def Z_VR23 ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg() );
308 reg_def Z_VR23_H ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next() );
309 reg_def Z_VR23_J ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(2) );
310 reg_def Z_VR23_K ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(3) );
311
312 reg_def Z_VR24 ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg() );
313 reg_def Z_VR24_H ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next() );
314 reg_def Z_VR24_J ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(2) );
315 reg_def Z_VR24_K ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(3) );
316
317 reg_def Z_VR25 ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg() );
318 reg_def Z_VR25_H ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next() );
319 reg_def Z_VR25_J ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(2) );
320 reg_def Z_VR25_K ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(3) );
321
322 reg_def Z_VR26 ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg() );
323 reg_def Z_VR26_H ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next() );
324 reg_def Z_VR26_J ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(2) );
325 reg_def Z_VR26_K ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(3) );
326
327 reg_def Z_VR27 ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg() );
328 reg_def Z_VR27_H ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next() );
329 reg_def Z_VR27_J ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(2) );
330 reg_def Z_VR27_K ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(3) );
331
332 reg_def Z_VR28 ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg() );
333 reg_def Z_VR28_H ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next() );
334 reg_def Z_VR28_J ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(2) );
335 reg_def Z_VR28_K ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(3) );
336
337 reg_def Z_VR29 ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg() );
338 reg_def Z_VR29_H ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next() );
339 reg_def Z_VR29_J ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(2) );
340 reg_def Z_VR29_K ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(3) );
341
342 reg_def Z_VR30 ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg() );
343 reg_def Z_VR30_H ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next() );
344 reg_def Z_VR30_J ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(2) );
345 reg_def Z_VR30_K ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(3) );
346
347 reg_def Z_VR31 ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg() );
348 reg_def Z_VR31_H ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next() );
349 reg_def Z_VR31_J ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(2) );
350 reg_def Z_VR31_K ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(3) );
351 // Special Registers
352
353 // Condition Codes Flag Registers
354
355 // z/Architecture has the PSW (program status word) that contains
356 // (among other information) the condition code. We treat this
357 // part of the PSW as a condition register CR. It consists of 4
358 // bits. Floating point instructions influence the same condition register CR.
359
360 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
361
362 // Specify priority of register selection within phases of register
363 // allocation. Highest priority is first. A useful heuristic is to
364 // give registers a low priority when they are required by machine
365 // instructions, and choose no-save registers before save-on-call, and
366 // save-on-call before save-on-entry. Registers which participate in
367 // fix calling sequences should come last. Registers which are used
368 // as pairs must fall on an even boundary.
369
370 // It's worth about 1% on SPEC geomean to get this right.
371
372 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
373 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
374 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
375 // the same as Z_R3->encoding()! Furthermore, we cannot make any
376 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
377 // Additionally, the function
378 // static enum RC rc_class(OptoReg::Name reg)
379 // maps a given <register>_num value to its chunk type (except for flags)
380 // and its current implementation relies on chunk0 and chunk1 having a
381 // size of 64 each.
382
383 alloc_class chunk0(
384 // chunk0 contains *all* 32 integer registers halves.
385
386 // potential SOE regs
387 Z_R13,Z_R13_H,
388 Z_R12,Z_R12_H,
389 Z_R11,Z_R11_H,
390 Z_R10,Z_R10_H,
391
392 Z_R9,Z_R9_H,
393 Z_R8,Z_R8_H,
394 Z_R7,Z_R7_H,
395
396 Z_R1,Z_R1_H,
397 Z_R0,Z_R0_H,
398
399 // argument registers
400 Z_R6,Z_R6_H,
401 Z_R5,Z_R5_H,
402 Z_R4,Z_R4_H,
403 Z_R3,Z_R3_H,
404 Z_R2,Z_R2_H,
405
406 // special registers
407 Z_R14,Z_R14_H,
408 Z_R15,Z_R15_H
409 );
410
411 alloc_class chunk1(
412 // Chunk1 contains *all* 64 floating-point registers halves.
413
414 Z_F15,Z_F15_H,
415 Z_F14,Z_F14_H,
416 Z_F13,Z_F13_H,
417 Z_F12,Z_F12_H,
418 Z_F11,Z_F11_H,
419 Z_F10,Z_F10_H,
420 Z_F9,Z_F9_H,
421 Z_F8,Z_F8_H,
422 // scratch register
423 Z_F7,Z_F7_H,
424 Z_F5,Z_F5_H,
425 Z_F3,Z_F3_H,
426 Z_F1,Z_F1_H,
427 // argument registers
428 Z_F6,Z_F6_H,
429 Z_F4,Z_F4_H,
430 Z_F2,Z_F2_H,
431 Z_F0,Z_F0_H
432 );
433
434 alloc_class chunk2(
435 Z_VR0, Z_VR0_H, Z_VR0_J, Z_VR0_K,
436 Z_VR1, Z_VR1_H, Z_VR1_J, Z_VR1_K,
437 Z_VR2, Z_VR2_H, Z_VR2_J, Z_VR2_K,
438 Z_VR3, Z_VR3_H, Z_VR3_J, Z_VR3_K,
439 Z_VR4, Z_VR4_H, Z_VR4_J, Z_VR4_K,
440 Z_VR5, Z_VR5_H, Z_VR5_J, Z_VR5_K,
441 Z_VR6, Z_VR6_H, Z_VR6_J, Z_VR6_K,
442 Z_VR7, Z_VR7_H, Z_VR7_J, Z_VR7_K,
443 Z_VR8, Z_VR8_H, Z_VR8_J, Z_VR8_K,
444 Z_VR9, Z_VR9_H, Z_VR9_J, Z_VR9_K,
445 Z_VR10, Z_VR10_H, Z_VR10_J, Z_VR10_K,
446 Z_VR11, Z_VR11_H, Z_VR11_J, Z_VR11_K,
447 Z_VR12, Z_VR12_H, Z_VR12_J, Z_VR12_K,
448 Z_VR13, Z_VR13_H, Z_VR13_J, Z_VR13_K,
449 Z_VR14, Z_VR14_H, Z_VR14_J, Z_VR14_K,
450 Z_VR15, Z_VR15_H, Z_VR15_J, Z_VR15_K,
451 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
452 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
453 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
454 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
455 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
456 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
457 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
458 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
459 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
460 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
461 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
462 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
463 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
464 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
465 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
466 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
467 );
468
469 alloc_class chunk3(
470 Z_CR
471 );
472
473
474 //-------Architecture Description Register Classes-----------------------
475
476 // Several register classes are automatically defined based upon
477 // information in this architecture description.
478
479 // 1) reg_class inline_cache_reg (as defined in frame section)
480 // 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
481
482 // Integer Register Classes
483 reg_class z_int_reg(
484 /*Z_R0*/ // R0
485 /*Z_R1*/
486 Z_R2,
487 Z_R3,
488 Z_R4,
489 Z_R5,
490 Z_R6,
491 Z_R7,
492 /*Z_R8,*/ // Z_thread
493 Z_R9,
494 Z_R10,
495 Z_R11,
496 Z_R12,
497 Z_R13
498 /*Z_R14*/ // return_pc
499 /*Z_R15*/ // SP
500 );
501
502 reg_class z_no_odd_int_reg(
503 /*Z_R0*/ // R0
504 /*Z_R1*/
505 Z_R2,
506 Z_R3,
507 Z_R4,
508 /*Z_R5,*/ // odd part of fix register pair
509 Z_R6,
510 Z_R7,
511 /*Z_R8,*/ // Z_thread
512 Z_R9,
513 Z_R10,
514 Z_R11,
515 Z_R12,
516 Z_R13
517 /*Z_R14*/ // return_pc
518 /*Z_R15*/ // SP
519 );
520
521 reg_class z_no_arg_int_reg(
522 /*Z_R0*/ // R0
523 /*Z_R1*/ // scratch
524 /*Z_R2*/
525 /*Z_R3*/
526 /*Z_R4*/
527 /*Z_R5*/
528 /*Z_R6*/
529 Z_R7,
530 /*Z_R8*/ // Z_thread
531 Z_R9,
532 Z_R10,
533 Z_R11,
534 Z_R12,
535 Z_R13
536 /*Z_R14*/ // return_pc
537 /*Z_R15*/ // SP
538 );
539
540 reg_class z_rarg1_int_reg(Z_R2);
541 reg_class z_rarg2_int_reg(Z_R3);
542 reg_class z_rarg3_int_reg(Z_R4);
543 reg_class z_rarg4_int_reg(Z_R5);
544 reg_class z_rarg5_int_reg(Z_R6);
545
546 // Pointer Register Classes
547
548 // 64-bit build means 64-bit pointers means hi/lo pairs.
549
550 reg_class z_rarg5_ptrN_reg(Z_R6);
551
552 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
553 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
554 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
555 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
556 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
557 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
558 reg_class z_r10_ptr_reg(Z_R10_H, Z_R10);
559 reg_class z_r11_ptr_reg(Z_R11_H, Z_R11);
560
561 reg_class z_ptr_reg(
562 /*Z_R0_H,Z_R0*/ // R0
563 /*Z_R1_H,Z_R1*/
564 Z_R2_H,Z_R2,
565 Z_R3_H,Z_R3,
566 Z_R4_H,Z_R4,
567 Z_R5_H,Z_R5,
568 Z_R6_H,Z_R6,
569 Z_R7_H,Z_R7,
570 /*Z_R8_H,Z_R8,*/ // Z_thread
571 Z_R9_H,Z_R9,
572 Z_R10_H,Z_R10,
573 Z_R11_H,Z_R11,
574 Z_R12_H,Z_R12,
575 Z_R13_H,Z_R13
576 /*Z_R14_H,Z_R14*/ // return_pc
577 /*Z_R15_H,Z_R15*/ // SP
578 );
579
580 reg_class z_lock_ptr_reg(
581 /*Z_R0_H,Z_R0*/ // R0
582 /*Z_R1_H,Z_R1*/
583 Z_R2_H,Z_R2,
584 Z_R3_H,Z_R3,
585 Z_R4_H,Z_R4,
586 /*Z_R5_H,Z_R5,*/
587 /*Z_R6_H,Z_R6,*/
588 Z_R7_H,Z_R7,
589 /*Z_R8_H,Z_R8,*/ // Z_thread
590 Z_R9_H,Z_R9,
591 Z_R10_H,Z_R10,
592 Z_R11_H,Z_R11,
593 Z_R12_H,Z_R12,
594 Z_R13_H,Z_R13
595 /*Z_R14_H,Z_R14*/ // return_pc
596 /*Z_R15_H,Z_R15*/ // SP
597 );
598
599 reg_class z_no_arg_ptr_reg(
600 /*Z_R0_H,Z_R0*/ // R0
601 /*Z_R1_H,Z_R1*/ // scratch
602 /*Z_R2_H,Z_R2*/
603 /*Z_R3_H,Z_R3*/
604 /*Z_R4_H,Z_R4*/
605 /*Z_R5_H,Z_R5*/
606 /*Z_R6_H,Z_R6*/
607 Z_R7_H, Z_R7,
608 /*Z_R8_H,Z_R8*/ // Z_thread
609 Z_R9_H,Z_R9,
610 Z_R10_H,Z_R10,
611 Z_R11_H,Z_R11,
612 Z_R12_H,Z_R12,
613 Z_R13_H,Z_R13
614 /*Z_R14_H,Z_R14*/ // return_pc
615 /*Z_R15_H,Z_R15*/ // SP
616 );
617
618 // Special class for storeP instructions, which can store SP or RPC to
619 // TLS. (Note: Do not generalize this to "any_reg". If you add
620 // another register, such as FP, to this mask, the allocator may try
621 // to put a temp in it.)
622 // Register class for memory access base registers,
623 // This class is a superset of z_ptr_reg including Z_thread.
624 reg_class z_memory_ptr_reg(
625 /*Z_R0_H,Z_R0*/ // R0
626 /*Z_R1_H,Z_R1*/
627 Z_R2_H,Z_R2,
628 Z_R3_H,Z_R3,
629 Z_R4_H,Z_R4,
630 Z_R5_H,Z_R5,
631 Z_R6_H,Z_R6,
632 Z_R7_H,Z_R7,
633 Z_R8_H,Z_R8, // Z_thread
634 Z_R9_H,Z_R9,
635 Z_R10_H,Z_R10,
636 Z_R11_H,Z_R11,
637 Z_R12_H,Z_R12,
638 Z_R13_H,Z_R13
639 /*Z_R14_H,Z_R14*/ // return_pc
640 /*Z_R15_H,Z_R15*/ // SP
641 );
642
643 // Other special pointer regs.
644 reg_class z_r1_regP(Z_R1_H,Z_R1);
645 reg_class z_r9_regP(Z_R9_H,Z_R9);
646
647
648 // Long Register Classes
649
650 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
651 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
652 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
653 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
654 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
655
656 // Longs in 1 register. Aligned adjacent hi/lo pairs.
657 reg_class z_long_reg(
658 /*Z_R0_H,Z_R0*/ // R0
659 /*Z_R1_H,Z_R1*/
660 Z_R2_H,Z_R2,
661 Z_R3_H,Z_R3,
662 Z_R4_H,Z_R4,
663 Z_R5_H,Z_R5,
664 Z_R6_H,Z_R6,
665 Z_R7_H,Z_R7,
666 /*Z_R8_H,Z_R8,*/ // Z_thread
667 Z_R9_H,Z_R9,
668 Z_R10_H,Z_R10,
669 Z_R11_H,Z_R11,
670 Z_R12_H,Z_R12,
671 Z_R13_H,Z_R13
672 /*Z_R14_H,Z_R14,*/ // return_pc
673 /*Z_R15_H,Z_R15*/ // SP
674 );
675
676 // z_long_reg without even registers
677 reg_class z_long_odd_reg(
678 /*Z_R0_H,Z_R0*/ // R0
679 /*Z_R1_H,Z_R1*/
680 Z_R3_H,Z_R3,
681 Z_R5_H,Z_R5,
682 Z_R7_H,Z_R7,
683 Z_R9_H,Z_R9,
684 Z_R11_H,Z_R11,
685 Z_R13_H,Z_R13
686 /*Z_R14_H,Z_R14,*/ // return_pc
687 /*Z_R15_H,Z_R15*/ // SP
688 );
689
690 // Special Class for Condition Code Flags Register
691
692 reg_class z_condition_reg(
693 Z_CR
694 );
695
696 // Scratch register for late profiling. Callee saved.
697 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
698
699
700 // Float Register Classes
701
702 reg_class z_flt_reg(
703 Z_F0,
704 /*Z_F1,*/ // scratch
705 Z_F2,
706 Z_F3,
707 Z_F4,
708 Z_F5,
709 Z_F6,
710 Z_F7,
711 Z_F8,
712 Z_F9,
713 Z_F10,
714 Z_F11,
715 Z_F12,
716 Z_F13,
717 Z_F14,
718 Z_F15
719 );
720 reg_class z_rscratch1_flt_reg(Z_F1);
721
722 // Double precision float registers have virtual `high halves' that
723 // are needed by the allocator.
724 reg_class z_dbl_reg(
725 Z_F0,Z_F0_H,
726 /*Z_F1,Z_F1_H,*/ // scratch
727 Z_F2,Z_F2_H,
728 Z_F3,Z_F3_H,
729 Z_F4,Z_F4_H,
730 Z_F5,Z_F5_H,
731 Z_F6,Z_F6_H,
732 Z_F7,Z_F7_H,
733 Z_F8,Z_F8_H,
734 Z_F9,Z_F9_H,
735 Z_F10,Z_F10_H,
736 Z_F11,Z_F11_H,
737 Z_F12,Z_F12_H,
738 Z_F13,Z_F13_H,
739 Z_F14,Z_F14_H,
740 Z_F15,Z_F15_H
741 );
742 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
743
744 reg_class z_v_reg(
745 // Attention: Only these ones are saved & restored at safepoint by RegisterSaver.
746 //1st 16 VRs overlaps with 1st 16 FPRs.
747 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
748 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
749 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
750 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
751 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
752 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
753 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
754 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
755 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
756 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
757 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
758 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
759 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
760 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
761 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
762 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
763 );
764
765 // class for vector register v16
766 reg_class z_vreg_16(
767 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K
768 );
769
770 // class for vector register v17
771 reg_class z_vreg_17(
772 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K
773 );
774
775 // class for vector register v18
776 reg_class z_vreg_18(
777 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K
778 );
779
780 // class for vector register v19
781 reg_class z_vreg_19(
782 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K
783 );
784
785 // class for vector register v20
786 reg_class z_vreg_20(
787 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K
788 );
789
790 // class for vector register v21
791 reg_class z_vreg_21(
792 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K
793 );
794
795 // class for vector register v22
796 reg_class z_vreg_22(
797 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K
798 );
799
800 // class for vector register v23
801 reg_class z_vreg_23(
802 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K
803 );
804
805 // class for vector register v24
806 reg_class z_vreg_24(
807 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K
808 );
809
810 // class for vector register v25
811 reg_class z_vreg_25(
812 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K
813 );
814
815 %}
816
817 //----------DEFINITION BLOCK---------------------------------------------------
818 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
819 // Current support includes integer values in the range [0, 0x7FFFFFFF].
820 // Format:
821 // int_def <name> (<int_value>, <expression>);
822 // Generated Code in ad_<arch>.hpp
823 // #define <name> (<expression>)
824 // // value == <int_value>
825 // Generated code in ad_<arch>.cpp adlc_verification()
826 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
827 //
828 definitions %{
829 // The default cost (of an ALU instruction).
830 int_def DEFAULT_COST ( 100, 100);
831 int_def DEFAULT_COST_LOW ( 80, 80);
832 int_def DEFAULT_COST_HIGH ( 120, 120);
833 int_def HUGE_COST (1000000, 1000000);
834
835 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
836 int_def ALU_REG_COST ( 100, DEFAULT_COST);
837 int_def ALU_MEMORY_COST ( 150, 150);
838
839 // Memory refs are twice as expensive as run-of-the-mill.
840 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
841 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
842 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
843
844 // Branches are even more expensive.
845 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
846 int_def CALL_COST ( 300, DEFAULT_COST * 3);
847 %}
848
849 source %{
850
851 #ifdef PRODUCT
852 #define BLOCK_COMMENT(str)
853 #define BIND(label) __ bind(label)
854 #else
855 #define BLOCK_COMMENT(str) __ block_comment(str)
856 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
857 #endif
858
859 #define __ masm->
860
861 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
862 #define Z_DISP3_SIZE 6
863
864 // Tertiary op of a LoadP or StoreP encoding.
865 #define REGP_OP true
866
867 // Given a register encoding, produce an Integer Register object.
868 static Register reg_to_register_object(int register_encoding);
869
870 // ****************************************************************************
871
872 // REQUIRED FUNCTIONALITY
873
874 // !!!!! Special hack to get all type of calls to specify the byte offset
875 // from the start of the call to the point where the return address
876 // will point.
877
878 void PhaseOutput::pd_perform_mach_node_analysis() {
879 }
880
881 int MachNode::pd_alignment_required() const {
882 return 1;
883 }
884
885 int MachNode::compute_padding(int current_offset) const {
886 return 0;
887 }
888
889 int MachCallStaticJavaNode::ret_addr_offset() {
890 if (_method) {
891 return 8;
892 } else {
893 return MacroAssembler::call_far_patchable_ret_addr_offset();
894 }
895 }
896
897 int MachCallDynamicJavaNode::ret_addr_offset() {
898 // Consider size of receiver type profiling (C2 tiers).
899 int profile_receiver_type_size = 0;
900
901 int vtable_index = this->_vtable_index;
902 if (vtable_index == -4) {
903 return 14 + profile_receiver_type_size;
904 } else {
905 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
906 return 36 + profile_receiver_type_size;
907 }
908 }
909
910 int MachCallRuntimeNode::ret_addr_offset() {
911 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
912 }
913
914 // Compute padding required for nodes which need alignment
915 //
916 // The addresses of the call instructions needs to be 4-byte aligned to
917 // ensure that they don't span a cache line so that they are atomically patchable.
918 // The actual calls get emitted at different offsets within the node emitters.
919 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
920
921 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
922 return (0 - current_offset) & 2;
923 }
924
925 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
926 return (6 - current_offset) & 2;
927 }
928
929 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
930 return (12 - current_offset) & 2;
931 }
932
933 int CallLeafDirectNode::compute_padding(int current_offset) const {
934 return (12 - current_offset) & 2;
935 }
936
937 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
938 return (12 - current_offset) & 2;
939 }
940
941 void emit_nop(C2_MacroAssembler *masm) {
942 __ z_nop();
943 }
944
945 // Emit an interrupt that is caught by the debugger (for debugging compiler).
946 void emit_break(C2_MacroAssembler *masm) {
947 __ z_illtrap();
948 }
949
950 #if !defined(PRODUCT)
951 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
952 os->print("TA");
953 }
954 #endif
955
956 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
957 emit_break(masm);
958 }
959
960 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
961 return MachNode::size(ra_);
962 }
963
964 static inline void z_emit16(C2_MacroAssembler *masm, long value) {
965 __ emit_instruction((unsigned long)value, 2);
966 }
967
968 static inline void z_emit32(C2_MacroAssembler *masm, long value) {
969 __ emit_instruction((unsigned long)value, 4);
970 }
971
972 static inline void z_emit48(C2_MacroAssembler *masm, long value) {
973 __ emit_instruction((unsigned long)value, 6);
974 }
975
976 static inline unsigned int z_emit_inst(C2_MacroAssembler *masm, long value) {
977 if (value < 0) {
978 // There obviously has been an unintended sign extension (int->long). Revert it.
979 value = (long)((unsigned long)((unsigned int)value));
980 }
981
982 int len = __ emit_instruction((unsigned long)value, 0);
983 return len;
984 }
985
986 // Check effective address (at runtime) for required alignment.
987 static inline void z_assert_aligned(C2_MacroAssembler *masm, int disp, Register index, Register base, int alignment) {
988 __ z_lay(Z_R0, disp, index, base);
989 __ z_nill(Z_R0, alignment-1);
990 __ z_brc(Assembler::bcondEqual, +3);
991 __ z_illtrap();
992 }
993
994 int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, relocInfo::relocType rtype,
995 PhaseRegAlloc* ra_, bool is_native_call = false) {
996 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
997 address old_mark = __ inst_mark();
998 unsigned int start_off = __ offset();
999
1000 if (is_native_call) {
1001 ShouldNotReachHere();
1002 }
1003
1004 if (rtype == relocInfo::runtime_call_w_cp_type) {
1005 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
1006 address call_addr = __ call_c_opt((address)entry_point);
1007 if (call_addr == nullptr) {
1008 Compile::current()->env()->record_out_of_memory_failure();
1009 return -1;
1010 }
1011 } else {
1012 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
1013 rtype == relocInfo::static_call_type, "unexpected rtype");
1014 __ relocate(rtype);
1015 // BRASL must be prepended with a nop to identify it in the instruction stream.
1016 __ z_nop();
1017 __ z_brasl(Z_R14, (address)entry_point);
1018 }
1019
1020 unsigned int ret_off = __ offset();
1021
1022 return (ret_off - start_off);
1023 }
1024
1025 static int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, RelocationHolder const& rspec) {
1026 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
1027 address old_mark = __ inst_mark();
1028 unsigned int start_off = __ offset();
1029
1030 relocInfo::relocType rtype = rspec.type();
1031 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
1032 "unexpected rtype");
1033
1034 __ relocate(rspec);
1035 __ z_nop();
1036 __ z_brasl(Z_R14, (address)entry_point);
1037
1038 unsigned int ret_off = __ offset();
1039
1040 return (ret_off - start_off);
1041 }
1042
1043 //=============================================================================
1044
1045 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
1046 int ConstantTable::calculate_table_base_offset() const {
1047 return 0; // absolute addressing, no offset
1048 }
1049
1050 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1051 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1052 ShouldNotReachHere();
1053 }
1054
1055 // Even with PC-relative TOC addressing, we still need this node.
1056 // Float loads/stores do not support PC-relative addresses.
1057 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1058 Register Rtoc = as_Register(ra_->get_encode(this));
1059 __ load_toc(Rtoc);
1060 }
1061
1062 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1063 // PCrelative TOC access.
1064 return 6; // sizeof(LARL)
1065 }
1066
1067 #if !defined(PRODUCT)
1068 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1069 Register r = as_Register(ra_->get_encode(this));
1070 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
1071 }
1072 #endif
1073
1074 //=============================================================================
1075
1076 #include "gc/shared/barrierSetAssembler.hpp"
1077
1078 #if !defined(PRODUCT)
1079 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1080 Compile* C = ra_->C;
1081 st->print_cr("--- MachPrologNode ---");
1082 st->print("\t");
1083 for (int i = 0; i < OptoPrologueNops; i++) {
1084 st->print_cr("NOP"); st->print("\t");
1085 }
1086
1087 long framesize = C->output()->frame_size_in_bytes();
1088 int bangsize = C->output()->bang_size_in_bytes();
1089
1090 // Calls to C2R adapters often do not accept exceptional returns.
1091 // We require that their callers must bang for them. But be
1092 // careful, because some VM calls (such as call site linkage) can
1093 // use several kilobytes of stack. But the stack safety zone should
1094 // account for that. See bugs 4446381, 4468289, 4497237.
1095 if (C->output()->need_stack_bang(bangsize)) {
1096 st->print_cr("# stack bang"); st->print("\t");
1097 }
1098 st->print_cr("push_frame %d", (int)-framesize);
1099 st->print("\t");
1100
1101 if (C->stub_function() == nullptr) {
1102 st->print("nmethod entry barrier\n\t");
1103 }
1104 }
1105 #endif
1106
1107 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1108 Compile* C = ra_->C;
1109
1110 size_t framesize = C->output()->frame_size_in_bytes();
1111 size_t bangsize = C->output()->bang_size_in_bytes();
1112
1113 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
1114
1115 if (C->clinit_barrier_on_entry()) {
1116 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1117
1118 Label L_skip_barrier;
1119 Register klass = Z_R1_scratch;
1120
1121 // Notify OOP recorder (don't need the relocation)
1122 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
1123 __ load_const_optimized(klass, md.value());
1124 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
1125
1126 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
1127 __ z_br(klass);
1128
1129 __ bind(L_skip_barrier);
1130 }
1131
1132 // Calls to C2R adapters often do not accept exceptional returns.
1133 // We require that their callers must bang for them. But be
1134 // careful, because some VM calls (such as call site linkage) can
1135 // use several kilobytes of stack. But the stack safety zone should
1136 // account for that. See bugs 4446381, 4468289, 4497237.
1137 if (C->output()->need_stack_bang(bangsize)) {
1138 __ generate_stack_overflow_check(bangsize);
1139 }
1140
1141 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
1142 __ save_return_pc();
1143
1144 // The z/Architecture abi is already accounted for in `framesize' via the
1145 // 'out_preserve_stack_slots' declaration.
1146 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
1147
1148 if (C->has_mach_constant_base_node()) {
1149 // NOTE: We set the table base offset here because users might be
1150 // emitted before MachConstantBaseNode.
1151 ConstantTable& constant_table = C->output()->constant_table();
1152 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1153 }
1154
1155 if (C->stub_function() == nullptr) {
1156 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1157 bs->nmethod_entry_barrier(masm);
1158 }
1159
1160 C->output()->set_frame_complete(__ offset());
1161 }
1162
1163 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1164 // Variable size. Determine dynamically.
1165 return MachNode::size(ra_);
1166 }
1167
1168 int MachPrologNode::reloc() const {
1169 // Return number of relocatable values contained in this instruction.
1170 return 1; // One reloc entry for load_const(toc).
1171 }
1172
1173 //=============================================================================
1174
1175 #if !defined(PRODUCT)
1176 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1177 os->print_cr("epilog");
1178 os->print("\t");
1179 if (do_polling() && ra_->C->is_method_compilation()) {
1180 os->print_cr("load_from_polling_page Z_R1_scratch");
1181 os->print("\t");
1182 }
1183 }
1184 #endif
1185
1186 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1187 Compile* C = ra_->C;
1188
1189 // If this does safepoint polling, then do it here.
1190 bool need_polling = do_polling() && C->is_method_compilation();
1191
1192 // Pop frame, restore return_pc, and all stuff needed by interpreter.
1193 int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
1194 __ pop_frame_restore_retPC(frame_size_in_bytes);
1195
1196 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1197 __ reserved_stack_check(Z_R14);
1198 }
1199
1200 // Touch the polling page.
1201 if (need_polling) {
1202 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1203 // We need to mark the code position where the load from the safepoint
1204 // polling page was emitted as relocInfo::poll_return_type here.
1205 __ relocate(relocInfo::poll_return_type);
1206 __ load_from_polling_page(Z_R1_scratch);
1207 }
1208 }
1209
1210 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1211 // Variable size. determine dynamically.
1212 return MachNode::size(ra_);
1213 }
1214
1215 int MachEpilogNode::reloc() const {
1216 // Return number of relocatable values contained in this instruction.
1217 return 1; // One for load_from_polling_page.
1218 }
1219
1220 const Pipeline * MachEpilogNode::pipeline() const {
1221 return MachNode::pipeline_class();
1222 }
1223
1224 //=============================================================================
1225
1226 // Figure out which register class each belongs in: rc_int, rc_float, rc_vector, rc_stack.
1227 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1228
1229 static enum RC rc_class(OptoReg::Name reg) {
1230 // Return the register class for the given register. The given register
1231 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1232 // enumeration in adGlobals_s390.hpp.
1233
1234 if (reg == OptoReg::Bad) {
1235 return rc_bad;
1236 }
1237
1238 // We have 32 integer register halves, starting at index 0.
1239 if (reg < 32) {
1240 return rc_int;
1241 }
1242
1243 // We have 32 floating-point register halves, starting at index 32.
1244 if (reg < 32+32) {
1245 return rc_float;
1246 }
1247
1248 // we have 128 vector register halves at index 64
1249 if (reg < 32+32+128) {
1250 return rc_vector;
1251 }
1252
1253 // Between float regs & stack are the flags regs.
1254 assert(OptoReg::is_stack(reg) || reg < 32+32+128, "blow up if spilling flags");
1255 return rc_stack;
1256 }
1257
1258 // Returns size as obtained from z_emit_instr.
1259 static unsigned int z_ld_st_helper(C2_MacroAssembler *masm, const char *op_str, unsigned long opcode,
1260 int reg, int offset, bool do_print, outputStream *os) {
1261
1262 if (masm) {
1263 if (opcode > (1L<<32)) {
1264 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1265 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1266 } else {
1267 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1268 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1269 }
1270 }
1271
1272 #if !defined(PRODUCT)
1273 if (do_print) {
1274 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1275 }
1276 #endif
1277 return (opcode > (1L << 32)) ? 6 : 4;
1278 }
1279
1280 static unsigned int z_mvc_helper(C2_MacroAssembler *masm, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1281 if (masm) {
1282 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1283 }
1284
1285 #if !defined(PRODUCT)
1286 else if (do_print) {
1287 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1288 }
1289 #endif
1290
1291 return 6;
1292 }
1293
1294 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1295 // Get registers to move.
1296 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1297 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1298 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1299 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1300
1301 enum RC src_hi_rc = rc_class(src_hi);
1302 enum RC src_lo_rc = rc_class(src_lo);
1303 enum RC dst_hi_rc = rc_class(dst_hi);
1304 enum RC dst_lo_rc = rc_class(dst_lo);
1305
1306 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1307 bool is64 = (src_hi_rc != rc_bad);
1308 assert(!is64 ||
1309 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1310 "expected aligned-adjacent pairs");
1311
1312 // Generate spill code!
1313 int size = 0;
1314 if (src_lo == dst_lo && src_hi == dst_hi) {
1315 return 0; // Self copy, no move.
1316 }
1317
1318 int src_offset = ra_->reg2offset(src_lo);
1319 int dst_offset = ra_->reg2offset(dst_lo);
1320 bool print = !do_size;
1321 bool src12 = Immediate::is_uimm12(src_offset);
1322 bool dst12 = Immediate::is_uimm12(dst_offset);
1323
1324 const char *mnemo = nullptr;
1325 unsigned long opc = 0;
1326
1327 if (bottom_type()->isa_vect() != nullptr && ideal_reg() == Op_VecX) {
1328 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1329 if (masm != nullptr) {
1330 __ z_mvc(Address(Z_SP, 0, dst_offset), Address(Z_SP, 0, src_offset), 16);
1331 }
1332 size += 6;
1333 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1334 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1335 if (masm != nullptr) {
1336 __ z_vst(Rsrc, Address(Z_SP, 0, dst_offset));
1337 }
1338 size += 6;
1339 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1340 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1341 if (masm != nullptr) {
1342 __ z_vl(Rdst, Address(Z_SP, 0, src_offset));
1343 }
1344 size += 6;
1345 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1346 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1347 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1348 if (masm != nullptr) {
1349 __ z_vlr(Rdst, Rsrc);
1350 }
1351 size += 6;
1352 } else {
1353 ShouldNotReachHere();
1354 }
1355 return size;
1356 }
1357
1358 // Memory->Memory Spill. Use Z_R0 to hold the value.
1359 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1360
1361 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1362 "expected same type of move for high parts");
1363
1364 if (src12 && dst12) {
1365 return z_mvc_helper(masm, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1366 }
1367
1368 int r0 = Z_R0_num;
1369 if (is64) {
1370 return z_ld_st_helper(masm, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1371 z_ld_st_helper(masm, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1372 }
1373
1374 return z_ld_st_helper(masm, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1375 z_ld_st_helper(masm, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1376 }
1377
1378 // Check for float->int copy. Requires a trip through memory.
1379 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1380 Unimplemented(); // Unsafe, do not remove!
1381 }
1382
1383 // Check for integer reg-reg copy.
1384 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1385 if (masm) {
1386 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1387 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1388 __ z_lgr(Rdst, Rsrc);
1389 return 4;
1390 }
1391 #if !defined(PRODUCT)
1392 // else
1393 if (print) {
1394 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1395 }
1396 #endif
1397 return 4;
1398 }
1399
1400 // Check for integer store.
1401 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1402 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1403 "expected same type of move for high parts");
1404
1405 if (is64) {
1406 return z_ld_st_helper(masm, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1407 }
1408
1409 // else
1410 mnemo = dst12 ? "ST " : "STY ";
1411 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1412
1413 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1414 }
1415
1416 // Check for integer load
1417 // Always load cOops zero-extended. That doesn't hurt int loads.
1418 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1419
1420 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1421 "expected same type of move for high parts");
1422
1423 mnemo = is64 ? "LG " : "LLGF";
1424 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1425
1426 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1427 }
1428
1429 // Check for float reg-reg copy.
1430 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1431 if (masm) {
1432 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1433 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1434 __ z_ldr(Rdst, Rsrc);
1435 return 2;
1436 }
1437 #if !defined(PRODUCT)
1438 // else
1439 if (print) {
1440 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1441 }
1442 #endif
1443 return 2;
1444 }
1445
1446 // Check for float store.
1447 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1448 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1449 "expected same type of move for high parts");
1450
1451 if (is64) {
1452 mnemo = dst12 ? "STD " : "STDY ";
1453 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1454 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1455 }
1456 // else
1457
1458 mnemo = dst12 ? "STE " : "STEY ";
1459 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1460 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1461 }
1462
1463 // Check for float load.
1464 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1465 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1466 "expected same type of move for high parts");
1467
1468 if (is64) {
1469 mnemo = src12 ? "LD " : "LDY ";
1470 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1471 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1472 }
1473 // else
1474
1475 mnemo = src12 ? "LE " : "LEY ";
1476 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1477 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1478 }
1479
1480 // --------------------------------------------------------------------
1481 // Check for hi bits still needing moving. Only happens for misaligned
1482 // arguments to native calls.
1483 if (src_hi == dst_hi) {
1484 return 0; // Self copy, no move.
1485 }
1486
1487 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1488 Unimplemented(); // Unsafe, do not remove!
1489
1490 return 0; // never reached, but make the compiler shut up!
1491 }
1492
1493 #if !defined(PRODUCT)
1494 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1495 if (ra_ && ra_->node_regs_max_index() > 0) {
1496 implementation(nullptr, ra_, false, os);
1497 } else {
1498 if (req() == 2 && in(1)) {
1499 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1500 } else {
1501 const char *c = "(";
1502 os->print("N%d = ", _idx);
1503 for (uint i = 1; i < req(); ++i) {
1504 os->print("%sN%d", c, in(i)->_idx);
1505 c = ", ";
1506 }
1507 os->print(")");
1508 }
1509 }
1510 }
1511 #endif
1512
1513 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1514 implementation(masm, ra_, false, nullptr);
1515 }
1516
1517 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1518 return implementation(nullptr, ra_, true, nullptr);
1519 }
1520
1521 //=============================================================================
1522
1523 #if !defined(PRODUCT)
1524 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1525 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1526 }
1527 #endif
1528
1529 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc * ra_) const {
1530 int rem_space = 0;
1531 if (!(ra_->C->output()->in_scratch_emit_size())) {
1532 rem_space = __ code()->insts()->remaining();
1533 if (rem_space <= _count*2 + 8) {
1534 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1535 }
1536 }
1537
1538 for (int i = 0; i < _count; i++) {
1539 __ z_nop();
1540 }
1541
1542 if (!(ra_->C->output()->in_scratch_emit_size())) {
1543 if (rem_space <= _count*2 + 8) {
1544 int rem_space2 = __ code()->insts()->remaining();
1545 tty->print_cr(", after = %d", rem_space2);
1546 }
1547 }
1548 }
1549
1550 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1551 return 2 * _count;
1552 }
1553
1554 #if !defined(PRODUCT)
1555 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1556 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1557 if (ra_ && ra_->node_regs_max_index() > 0) {
1558 int reg = ra_->get_reg_first(this);
1559 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1560 } else {
1561 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1562 }
1563 }
1564 #endif
1565
1566 // Take care of the size function, if you make changes here!
1567 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1568 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1569 int reg = ra_->get_encode(this);
1570 __ z_lay(as_Register(reg), offset, Z_SP);
1571 }
1572
1573 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1574 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1575 return 6;
1576 }
1577
1578 %} // end source section
1579
1580 //----------SOURCE BLOCK-------------------------------------------------------
1581 // This is a block of C++ code which provides values, functions, and
1582 // definitions necessary in the rest of the architecture description
1583
1584 source_hpp %{
1585
1586 // Header information of the source block.
1587 // Method declarations/definitions which are used outside
1588 // the ad-scope can conveniently be defined here.
1589 //
1590 // To keep related declarations/definitions/uses close together,
1591 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1592 #include "opto/convertnode.hpp"
1593 #include "oops/klass.inline.hpp"
1594
1595 //--------------------------------------------------------------
1596 // Used for optimization in Compile::Shorten_branches
1597 //--------------------------------------------------------------
1598
1599 class CallStubImpl {
1600 public:
1601
1602 // call trampolines
1603 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1604 static uint size_call_trampoline() {
1605 return 0; // no call trampolines on this platform
1606 }
1607
1608 // call trampolines
1609 // Number of relocations needed by a call trampoline stub.
1610 static uint reloc_call_trampoline() {
1611 return 0; // No call trampolines on this platform.
1612 }
1613 };
1614
1615 %} // end source_hpp section
1616
1617 source %{
1618
1619 #if !defined(PRODUCT)
1620 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1621 os->print_cr("---- MachUEPNode ----");
1622 os->print_cr("\tTA");
1623 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1624 os->print_cr("\tBR(Z_R1)");
1625 os->print_cr("\tTA # pad with illtraps");
1626 os->print_cr("\t...");
1627 os->print_cr("\tTA");
1628 os->print_cr("\tLTGR Z_R2, Z_R2");
1629 os->print_cr("\tBRU ic_miss");
1630 }
1631 #endif
1632
1633 void MachUEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1634 // This is Unverified Entry Point
1635 __ ic_check(CodeEntryAlignment);
1636 }
1637
1638 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1639 // Determine size dynamically.
1640 return MachNode::size(ra_);
1641 }
1642
1643 //=============================================================================
1644
1645 %} // interrupt source section
1646
1647 source_hpp %{ // Header information of the source block.
1648
1649 class HandlerImpl {
1650 public:
1651
1652 static int emit_deopt_handler(C2_MacroAssembler* masm);
1653
1654 static uint size_deopt_handler() {
1655 return NativeCall::max_instruction_size() + MacroAssembler::jump_pcrelative_size();
1656 }
1657 };
1658
1659 class Node::PD {
1660 public:
1661 enum NodeFlags {
1662 _last_flag = Node::_last_flag
1663 };
1664 };
1665
1666 %} // end source_hpp section
1667
1668 source %{
1669
1670 // Emit deopt handler code.
1671 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm) {
1672 address base = __ start_a_stub(size_deopt_handler());
1673
1674 if (base == nullptr) {
1675 ciEnv::current()->record_failure("CodeCache is full");
1676 return 0; // CodeBuffer::expand failed
1677 }
1678
1679 int offset = __ offset();
1680
1681 Label start;
1682 __ bind(start);
1683
1684 // Size_deopt_handler() must be exact on zarch, so for simplicity
1685 // we do not use load_const_opt here.
1686 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1687 __ call(Z_R1);
1688
1689 int entry_offset = __ offset();
1690
1691 __ z_bru(start);
1692
1693 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1694 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1695 "out of bounds read in post-call NOP check");
1696
1697 __ end_a_stub();
1698 return entry_offset;
1699 }
1700
1701 //=============================================================================
1702
1703
1704 // Given a register encoding, produce an Integer Register object.
1705 static Register reg_to_register_object(int register_encoding) {
1706 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1707 return as_Register(register_encoding);
1708 }
1709
1710 bool Matcher::match_rule_supported(int opcode) {
1711 if (!has_match_rule(opcode)) {
1712 return false; // no match rule present
1713 }
1714
1715 switch (opcode) {
1716 case Op_ReverseBytesI:
1717 case Op_ReverseBytesL:
1718 case Op_ReverseBytesS:
1719 case Op_ReverseBytesUS:
1720 return UseByteReverseInstruction;
1721 case Op_PopCountI:
1722 case Op_PopCountL:
1723 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1724 return (UsePopCountInstruction && VM_Version::has_PopCount());
1725 case Op_AddVB:
1726 case Op_AddVS:
1727 case Op_AddVI:
1728 case Op_AddVL:
1729 case Op_AddVD:
1730 case Op_SubVB:
1731 case Op_SubVS:
1732 case Op_SubVI:
1733 case Op_SubVL:
1734 case Op_SubVD:
1735 case Op_MulVB:
1736 case Op_MulVS:
1737 case Op_MulVI:
1738 case Op_MulVD:
1739 case Op_DivVD:
1740 case Op_SqrtVD:
1741 case Op_RoundDoubleModeV:
1742 return SuperwordUseVX;
1743 case Op_AddVF:
1744 case Op_SubVF:
1745 case Op_MulVF:
1746 case Op_DivVF:
1747 case Op_SqrtVF:
1748 //PopCountVI supported by z14 onwards.
1749 case Op_PopCountVI:
1750 return (SuperwordUseVX && UseSFPV);
1751 case Op_FmaF:
1752 case Op_FmaD:
1753 return UseFMA;
1754 }
1755
1756 return true; // Per default match rules are supported.
1757 }
1758
1759 bool Matcher::match_rule_supported_auto_vectorization(int opcode, int vlen, BasicType bt) {
1760 return match_rule_supported_vector(opcode, vlen, bt);
1761 }
1762
1763 bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1764 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1765 return false;
1766 }
1767 return true; // Per default match rules are supported.
1768 }
1769
1770 bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
1771 return false;
1772 }
1773
1774 bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
1775 return false;
1776 }
1777
1778 bool Matcher::vector_rearrange_requires_load_shuffle(BasicType elem_bt, int vlen) {
1779 return false;
1780 }
1781
1782 bool Matcher::mask_op_prefers_predicate(int opcode, const TypeVect* vt) {
1783 return false;
1784 }
1785
1786 const RegMask* Matcher::predicate_reg_mask(void) {
1787 return nullptr;
1788 }
1789
1790 // Vector calling convention not yet implemented.
1791 bool Matcher::supports_vector_calling_convention(void) {
1792 return false;
1793 }
1794
1795 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1796 Unimplemented();
1797 return OptoRegPair(0, 0);
1798 }
1799
1800 //----------SUPERWORD HELPERS----------------------------------------
1801
1802 // Vector width in bytes.
1803 int Matcher::vector_width_in_bytes(BasicType bt) {
1804 if (SuperwordUseVX) {
1805 assert(MaxVectorSize == 16, "");
1806 return 16;
1807 } else {
1808 assert(MaxVectorSize == 8, "");
1809 return 8;
1810 }
1811 }
1812
1813 // Vector ideal reg.
1814 uint Matcher::vector_ideal_reg(int size) {
1815 if (SuperwordUseVX) {
1816 assert(MaxVectorSize == 16 && size == 16, "");
1817 return Op_VecX;
1818 } else {
1819 assert(MaxVectorSize == 8 && size == 8, "");
1820 return Op_RegL;
1821 }
1822 }
1823
1824 // Limits on vector size (number of elements) loaded into vector.
1825 int Matcher::max_vector_size(const BasicType bt) {
1826 assert(is_java_primitive(bt), "only primitive type vectors");
1827 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1828 }
1829
1830 int Matcher::min_vector_size(const BasicType bt) {
1831 return max_vector_size(bt); // Same as max.
1832 }
1833
1834 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
1835 return Matcher::max_vector_size(bt);
1836 }
1837
1838 int Matcher::scalable_vector_reg_size(const BasicType bt) {
1839 return -1;
1840 }
1841
1842 // RETURNS: whether this branch offset is short enough that a short
1843 // branch can be used.
1844 //
1845 // If the platform does not provide any short branch variants, then
1846 // this method should return `false' for offset 0.
1847 //
1848 // `Compile::Fill_buffer' will decide on basis of this information
1849 // whether to do the pass `Compile::Shorten_branches' at all.
1850 //
1851 // And `Compile::Shorten_branches' will decide on basis of this
1852 // information whether to replace particular branch sites by short
1853 // ones.
1854 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1855 // On zarch short branches use a 16 bit signed immediate that
1856 // is the pc-relative offset in halfword (= 2 bytes) units.
1857 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1858 }
1859
1860 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1861 ShouldNotReachHere(); // generic vector operands not supported
1862 return nullptr;
1863 }
1864
1865 bool Matcher::is_reg2reg_move(MachNode* m) {
1866 ShouldNotReachHere(); // generic vector operands not supported
1867 return false;
1868 }
1869
1870 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
1871 return false;
1872 }
1873
1874 bool Matcher::is_generic_vector(MachOper* opnd) {
1875 ShouldNotReachHere(); // generic vector operands not supported
1876 return false;
1877 }
1878
1879 // Constants for c2c and c calling conventions.
1880
1881 const MachRegisterNumbers z_iarg_reg[5] = {
1882 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1883 };
1884
1885 const MachRegisterNumbers z_farg_reg[4] = {
1886 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1887 };
1888
1889 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1890
1891 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1892
1893 #ifdef ASSERT
1894 // Return whether or not this register is ever used as an argument.
1895 bool Matcher::can_be_java_arg(int reg) {
1896 // We return true for all registers contained in z_iarg_reg[] and
1897 // z_farg_reg[] and their virtual halves.
1898 // We must include the virtual halves in order to get STDs and LDs
1899 // instead of STWs and LWs in the trampoline stubs.
1900
1901 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1902 reg == Z_R3_num || reg == Z_R3_H_num ||
1903 reg == Z_R4_num || reg == Z_R4_H_num ||
1904 reg == Z_R5_num || reg == Z_R5_H_num ||
1905 reg == Z_R6_num || reg == Z_R6_H_num) {
1906 return true;
1907 }
1908
1909 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1910 reg == Z_F2_num || reg == Z_F2_H_num ||
1911 reg == Z_F4_num || reg == Z_F4_H_num ||
1912 reg == Z_F6_num || reg == Z_F6_H_num) {
1913 return true;
1914 }
1915
1916 return false;
1917 }
1918 #endif
1919
1920 uint Matcher::int_pressure_limit()
1921 {
1922 // Medium size register set, 6 special purpose regs, 3 SOE regs.
1923 // 10 prevents spill-split-recycle sanity check in JVM2008.xml.transform.
1924 return (INTPRESSURE == -1) ? 10 : INTPRESSURE;
1925 }
1926
1927 uint Matcher::float_pressure_limit()
1928 {
1929 return (FLOATPRESSURE == -1) ? 15 : FLOATPRESSURE;
1930 }
1931
1932 // Register for DIVI projection of divmodI
1933 const RegMask& Matcher::divI_proj_mask() {
1934 return _Z_RARG4_INT_REG_mask;
1935 }
1936
1937 // Register for MODI projection of divmodI
1938 const RegMask& Matcher::modI_proj_mask() {
1939 return _Z_RARG3_INT_REG_mask;
1940 }
1941
1942 // Register for DIVL projection of divmodL
1943 const RegMask& Matcher::divL_proj_mask() {
1944 return _Z_RARG4_LONG_REG_mask;
1945 }
1946
1947 // Register for MODL projection of divmodL
1948 const RegMask& Matcher::modL_proj_mask() {
1949 return _Z_RARG3_LONG_REG_mask;
1950 }
1951
1952 // Should the matcher clone input 'm' of node 'n'?
1953 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
1954 if (is_encode_and_store_pattern(n, m)) {
1955 mstack.push(m, Visit);
1956 return true;
1957 }
1958 return false;
1959 }
1960
1961 // Should the Matcher clone shifts on addressing modes, expecting them
1962 // to be subsumed into complex addressing expressions or compute them
1963 // into registers?
1964 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1965 return clone_base_plus_offset_address(m, mstack, address_visited);
1966 }
1967
1968 %} // source
1969
1970 //----------ENCODING BLOCK-----------------------------------------------------
1971 // This block specifies the encoding classes used by the compiler to output
1972 // byte streams. Encoding classes are parameterized macros used by
1973 // Machine Instruction Nodes in order to generate the bit encoding of the
1974 // instruction. Operands specify their base encoding interface with the
1975 // interface keyword. There are currently supported four interfaces,
1976 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1977 // operand to generate a function which returns its register number when
1978 // queried. CONST_INTER causes an operand to generate a function which
1979 // returns the value of the constant when queried. MEMORY_INTER causes an
1980 // operand to generate four functions which return the Base Register, the
1981 // Index Register, the Scale Value, and the Offset Value of the operand when
1982 // queried. COND_INTER causes an operand to generate six functions which
1983 // return the encoding code (ie - encoding bits for the instruction)
1984 // associated with each basic boolean condition for a conditional instruction.
1985 //
1986 // Instructions specify two basic values for encoding. Again, a function
1987 // is available to check if the constant displacement is an oop. They use the
1988 // ins_encode keyword to specify their encoding classes (which must be
1989 // a sequence of enc_class names, and their parameters, specified in
1990 // the encoding block), and they use the
1991 // opcode keyword to specify, in order, their primary, secondary, and
1992 // tertiary opcode. Only the opcode sections which a particular instruction
1993 // needs for encoding need to be specified.
1994 encode %{
1995 enc_class enc_unimplemented %{
1996 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1997 %}
1998
1999 enc_class enc_untested %{
2000 #ifdef ASSERT
2001 __ untested("Untested mach node encoding in AD file.");
2002 #endif
2003 %}
2004
2005 enc_class z_rrform(iRegI dst, iRegI src) %{
2006 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
2007 assert( ($primary >> 16) == 0, "Instruction format error");
2008 z_emit16(masm, $primary |
2009 Assembler::reg($dst$$reg,8,16) |
2010 Assembler::reg($src$$reg,12,16));
2011 %}
2012
2013 enc_class z_rreform(iRegI dst1, iRegI src2) %{
2014 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2015 z_emit32(masm, $primary |
2016 Assembler::reg($dst1$$reg,24,32) |
2017 Assembler::reg($src2$$reg,28,32));
2018 %}
2019
2020 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
2021 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2022 z_emit32(masm, $primary |
2023 Assembler::reg($dst1$$reg,24,32) |
2024 Assembler::reg($src2$$reg,28,32) |
2025 Assembler::reg($src3$$reg,16,32));
2026 %}
2027
2028 enc_class z_riform_signed(iRegI dst, immI16 src) %{
2029 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2030 z_emit32(masm, $primary |
2031 Assembler::reg($dst$$reg,8,32) |
2032 Assembler::simm16($src$$constant,16,32));
2033 %}
2034
2035 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
2036 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2037 z_emit32(masm, $primary |
2038 Assembler::reg($dst$$reg,8,32) |
2039 Assembler::uimm16($src$$constant,16,32));
2040 %}
2041
2042 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
2043 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2044 z_emit48(masm, $primary |
2045 Assembler::reg($dst1$$reg,8,48) |
2046 Assembler::reg($src3$$reg,12,48) |
2047 Assembler::simm16($src2$$constant,16,48));
2048 %}
2049
2050 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
2051 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2052 z_emit48(masm, $primary |
2053 Assembler::reg($dst$$reg,8,48) |
2054 Assembler::simm32($src$$constant,16,48));
2055 %}
2056
2057 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
2058 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2059 z_emit48(masm, $primary |
2060 Assembler::reg($dst$$reg,8,48) |
2061 Assembler::uimm32($src$$constant,16,48));
2062 %}
2063
2064 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
2065 z_emit48(masm, $primary |
2066 Assembler::reg($dst$$reg,8,48) |
2067 Assembler::reg($src1$$reg,12,48) |
2068 Assembler::simm20($src2$$constant));
2069 %}
2070
2071 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
2072 z_emit48(masm, $primary |
2073 Assembler::reg($dst$$reg,8,48) |
2074 Assembler::reg($src$$reg,12,48) |
2075 Assembler::reg($shft$$reg,16,48) |
2076 Assembler::simm20(0));
2077 %}
2078
2079 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2080 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2081 z_emit32(masm, $primary |
2082 Assembler::reg($dst$$reg,8,32) |
2083 Assembler::reg($src1$$reg,12,32) |
2084 Assembler::reg($src2$$reg,16,32) |
2085 Assembler::uimm12($con$$constant,20,32));
2086 %}
2087
2088 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
2089 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2090 z_emit32(masm, $primary |
2091 Assembler::reg($dst$$reg,8,32) |
2092 Assembler::reg($src$$reg,16,32) |
2093 Assembler::uimm12($con$$constant,20,32));
2094 %}
2095
2096 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2097 z_emit48(masm, $primary |
2098 Assembler::reg($dst$$reg,8,48) |
2099 Assembler::reg($src1$$reg,12,48) |
2100 Assembler::reg($src2$$reg,16,48) |
2101 Assembler::simm20($con$$constant));
2102 %}
2103
2104 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
2105 z_emit48(masm, $primary |
2106 Assembler::reg($dst$$reg,8,48) |
2107 Assembler::reg($src$$reg,16,48) |
2108 Assembler::simm20($con$$constant));
2109 %}
2110
2111 // Direct memory arithmetic.
2112 enc_class z_siyform(memoryRSY mem, immI8 src) %{
2113 int disp = $mem$$disp;
2114 Register base = reg_to_register_object($mem$$base);
2115 int con = $src$$constant;
2116
2117 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
2118 z_emit_inst(masm, $primary |
2119 Assembler::regz(base,16,48) |
2120 Assembler::simm20(disp) |
2121 Assembler::simm8(con,8,48));
2122 %}
2123
2124 enc_class z_silform(memoryRS mem, immI16 src) %{
2125 z_emit_inst(masm, $primary |
2126 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
2127 Assembler::uimm12($mem$$disp,20,48) |
2128 Assembler::simm16($src$$constant,32,48));
2129 %}
2130
2131 // Encoder for FP ALU reg/mem instructions (support only short displacements).
2132 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
2133 Register Ridx = $mem$$index$$Register;
2134 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2135 if ($primary > (1L << 32)) {
2136 z_emit_inst(masm, $primary |
2137 Assembler::reg($dst$$reg, 8, 48) |
2138 Assembler::uimm12($mem$$disp, 20, 48) |
2139 Assembler::reg(Ridx, 12, 48) |
2140 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2141 } else {
2142 z_emit_inst(masm, $primary |
2143 Assembler::reg($dst$$reg, 8, 32) |
2144 Assembler::uimm12($mem$$disp, 20, 32) |
2145 Assembler::reg(Ridx, 12, 32) |
2146 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2147 }
2148 %}
2149
2150 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
2151 Register Ridx = $mem$$index$$Register;
2152 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2153 if ($primary > (1L<<32)) {
2154 z_emit_inst(masm, $primary |
2155 Assembler::reg($dst$$reg, 8, 48) |
2156 Assembler::simm20($mem$$disp) |
2157 Assembler::reg(Ridx, 12, 48) |
2158 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2159 } else {
2160 z_emit_inst(masm, $primary |
2161 Assembler::reg($dst$$reg, 8, 32) |
2162 Assembler::uimm12($mem$$disp, 20, 32) |
2163 Assembler::reg(Ridx, 12, 32) |
2164 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2165 }
2166 %}
2167
2168 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
2169 int isize = $secondary > 1L << 32 ? 48 : 32;
2170 Register Ridx = $mem$$index$$Register;
2171 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2172
2173 if (Displacement::is_shortDisp((long)$mem$$disp)) {
2174 z_emit_inst(masm, $secondary |
2175 Assembler::reg($dst$$reg, 8, isize) |
2176 Assembler::uimm12($mem$$disp, 20, isize) |
2177 Assembler::reg(Ridx, 12, isize) |
2178 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2179 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
2180 z_emit_inst(masm, $primary |
2181 Assembler::reg($dst$$reg, 8, 48) |
2182 Assembler::simm20($mem$$disp) |
2183 Assembler::reg(Ridx, 12, 48) |
2184 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2185 } else {
2186 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2187 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2188 z_emit_inst(masm, $secondary |
2189 Assembler::reg($dst$$reg, 8, isize) |
2190 Assembler::uimm12(0, 20, isize) |
2191 Assembler::reg(Z_R1_scratch, 12, isize) |
2192 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2193 }
2194 %}
2195
2196 enc_class z_enc_brul(Label lbl) %{
2197 Label* p = $lbl$$label;
2198
2199 // 'p' is `nullptr' when this encoding class is used only to
2200 // determine the size of the encoded instruction.
2201 // Use a bound dummy label in that case.
2202 Label d;
2203 __ bind(d);
2204 Label& l = (nullptr == p) ? d : *(p);
2205 __ z_brul(l);
2206 %}
2207
2208 enc_class z_enc_bru(Label lbl) %{
2209 Label* p = $lbl$$label;
2210
2211 // 'p' is `nullptr' when this encoding class is used only to
2212 // determine the size of the encoded instruction.
2213 // Use a bound dummy label in that case.
2214 Label d;
2215 __ bind(d);
2216 Label& l = (nullptr == p) ? d : *(p);
2217 __ z_bru(l);
2218 %}
2219
2220 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2221 Label* p = $lbl$$label;
2222
2223 // 'p' is `nullptr' when this encoding class is used only to
2224 // determine the size of the encoded instruction.
2225 // Use a bound dummy label in that case.
2226 Label d;
2227 __ bind(d);
2228 Label& l = (nullptr == p) ? d : *(p);
2229 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2230 %}
2231
2232 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2233 Label* p = $lbl$$label;
2234
2235 // 'p' is `nullptr' when this encoding class is used only to
2236 // determine the size of the encoded instruction.
2237 // Use a bound dummy label in that case.
2238 Label d;
2239 __ bind(d);
2240 Label& l = (nullptr == p) ? d : *(p);
2241 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2242 %}
2243
2244 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2245 Label* p = $lbl$$label;
2246
2247 // 'p' is `nullptr' when this encoding class is used only to
2248 // determine the size of the encoded instruction.
2249 // Use a bound dummy label in that case.
2250 Label d;
2251 __ bind(d);
2252 Label& l = (nullptr == p) ? d : *(p);
2253 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2254 unsigned long instr = $primary;
2255 if (instr == CRJ_ZOPC) {
2256 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2257 } else if (instr == CLRJ_ZOPC) {
2258 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2259 } else if (instr == CGRJ_ZOPC) {
2260 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2261 } else {
2262 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2263 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2264 }
2265 %}
2266
2267 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2268 Label* p = $lbl$$label;
2269
2270 // 'p' is `nullptr' when this encoding class is used only to
2271 // determine the size of the encoded instruction.
2272 // Use a bound dummy label in that case.
2273 Label d;
2274 __ bind(d);
2275 Label& l = (nullptr == p) ? d : *(p);
2276
2277 unsigned long instr = $primary;
2278 if (instr == CR_ZOPC) {
2279 __ z_cr($src1$$Register, $src2$$Register);
2280 } else if (instr == CLR_ZOPC) {
2281 __ z_clr($src1$$Register, $src2$$Register);
2282 } else if (instr == CGR_ZOPC) {
2283 __ z_cgr($src1$$Register, $src2$$Register);
2284 } else {
2285 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2286 __ z_clgr($src1$$Register, $src2$$Register);
2287 }
2288
2289 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2290 %}
2291
2292 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2293 Label* p = $lbl$$label;
2294
2295 // 'p' is `nullptr' when this encoding class is used only to
2296 // determine the size of the encoded instruction.
2297 // Use a bound dummy label in that case.
2298 Label d;
2299 __ bind(d);
2300 Label& l = (nullptr == p) ? d : *(p);
2301
2302 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2303 unsigned long instr = $primary;
2304 if (instr == CIJ_ZOPC) {
2305 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2306 } else if (instr == CLIJ_ZOPC) {
2307 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2308 } else if (instr == CGIJ_ZOPC) {
2309 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2310 } else {
2311 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2312 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2313 }
2314 %}
2315
2316 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2317 Label* p = $lbl$$label;
2318
2319 // 'p' is `nullptr' when this encoding class is used only to
2320 // determine the size of the encoded instruction.
2321 // Use a bound dummy label in that case.
2322 Label d;
2323 __ bind(d);
2324 Label& l = (nullptr == p) ? d : *(p);
2325
2326 unsigned long instr = $primary;
2327 if (instr == CHI_ZOPC) {
2328 __ z_chi($src1$$Register, $src2$$constant);
2329 } else if (instr == CLFI_ZOPC) {
2330 __ z_clfi($src1$$Register, $src2$$constant);
2331 } else if (instr == CGHI_ZOPC) {
2332 __ z_cghi($src1$$Register, $src2$$constant);
2333 } else {
2334 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2335 __ z_clgfi($src1$$Register, $src2$$constant);
2336 }
2337
2338 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2339 %}
2340
2341 // Call from Java to runtime.
2342 enc_class z_enc_java_to_runtime_call(method meth) %{
2343 // Save return pc before call to the place where we need it, since
2344 // callee doesn't.
2345 unsigned int start_off = __ offset();
2346 // Compute size of "larl + stg + call_c_opt".
2347 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2348 __ get_PC(Z_R14, size_of_code);
2349 __ save_return_pc();
2350 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2351
2352 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2353 address call_addr = __ call_c_opt((address)$meth$$method);
2354 if (call_addr == nullptr) {
2355 Compile::current()->env()->record_out_of_memory_failure();
2356 return;
2357 }
2358
2359 #ifdef ASSERT
2360 // Plausibility check for size_of_code assumptions.
2361 unsigned int actual_ret_off = __ offset();
2362 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2363 #endif
2364 %}
2365
2366 enc_class z_enc_java_static_call(method meth) %{
2367 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2368 // whom we intended to call.
2369 int ret_offset = 0;
2370
2371 if (!_method) {
2372 ret_offset = emit_call_reloc(masm, $meth$$method,
2373 relocInfo::runtime_call_w_cp_type, ra_);
2374 } else {
2375 int method_index = resolved_method_index(masm);
2376 if (_optimized_virtual) {
2377 ret_offset = emit_call_reloc(masm, $meth$$method,
2378 opt_virtual_call_Relocation::spec(method_index));
2379 } else {
2380 ret_offset = emit_call_reloc(masm, $meth$$method,
2381 static_call_Relocation::spec(method_index));
2382 }
2383 }
2384 assert(__ inst_mark() != nullptr, "emit_call_reloc must set_inst_mark()");
2385
2386 if (_method) { // Emit stub for static call.
2387 address stub = CompiledDirectCall::emit_to_interp_stub(masm);
2388 if (stub == nullptr) {
2389 __ clear_inst_mark();
2390 ciEnv::current()->record_failure("CodeCache is full");
2391 return;
2392 }
2393 }
2394
2395 __ clear_inst_mark();
2396 %}
2397
2398 // Java dynamic call
2399 enc_class z_enc_java_dynamic_call(method meth) %{
2400 unsigned int start_off = __ offset();
2401
2402 int vtable_index = this->_vtable_index;
2403 if (vtable_index == -4) {
2404 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2405 address virtual_call_oop_addr = nullptr;
2406
2407 AddressLiteral empty_ic((address) Universe::non_oop_word());
2408 virtual_call_oop_addr = __ pc();
2409 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2410 if (!success) {
2411 Compile::current()->env()->record_out_of_memory_failure();
2412 return;
2413 }
2414
2415 // Call to fixup routine. Fixup routine uses ScopeDesc info
2416 // to determine who we intended to call.
2417 int method_index = resolved_method_index(masm);
2418 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2419 unsigned int ret_off = __ offset();
2420 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2421 ret_off += emit_call_reloc(masm, $meth$$method, relocInfo::none, ra_);
2422 __ clear_inst_mark();
2423 assert(_method, "lazy_constant may be wrong when _method==null");
2424 } else {
2425 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2426 // Go through the vtable. Get receiver klass. Receiver already
2427 // checked for non-null. If we'll go thru a C2I adapter, the
2428 // interpreter expects method in Z_method.
2429 // Use Z_method to temporarily hold the klass oop.
2430 // Z_R1_scratch is destroyed.
2431 __ load_klass(Z_method, Z_R2);
2432
2433 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2434 int v_off = entry_offset + in_bytes(vtableEntry::method_offset());
2435
2436 if (Displacement::is_validDisp(v_off) ) {
2437 // Can use load instruction with large offset.
2438 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2439 } else {
2440 // Worse case, must load offset into register.
2441 __ load_const(Z_R1_scratch, v_off);
2442 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2443 }
2444 // NOTE: for vtable dispatches, the vtable entry will never be
2445 // null. However it may very well end up in handle_wrong_method
2446 // if the method is abstract for the particular class.
2447 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2448 // Call target. Either compiled code or C2I adapter.
2449 __ z_basr(Z_R14, Z_R1_scratch);
2450 unsigned int ret_off = __ offset();
2451 }
2452 %}
2453
2454 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2455 Register Rdst = reg_to_register_object($dst$$reg);
2456 Register Rsrc = reg_to_register_object($src$$reg);
2457
2458 // Don't emit code if operands are identical (same register).
2459 if (Rsrc != Rdst) {
2460 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2461
2462 if (VM_Version::has_LoadStoreConditional()) {
2463 __ z_locgr(Rdst, Rsrc, cc);
2464 } else {
2465 // Branch if not (cmp cr).
2466 Label done;
2467 __ z_brc(Assembler::inverse_condition(cc), done);
2468 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2469 __ bind(done);
2470 }
2471 }
2472 %}
2473
2474 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2475 Register Rdst = reg_to_register_object($dst$$reg);
2476 int Csrc = $src$$constant;
2477 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2478 Label done;
2479 // Branch if not (cmp cr).
2480 __ z_brc(Assembler::inverse_condition(cc), done);
2481 if (Csrc == 0) {
2482 // Don't set CC.
2483 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2484 } else {
2485 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2486 }
2487 __ bind(done);
2488 %}
2489
2490 enc_class z_enc_cctobool(iRegI res) %{
2491 Register Rres = reg_to_register_object($res$$reg);
2492
2493 if (VM_Version::has_LoadStoreConditional()) {
2494 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2495 __ load_const_optimized(Rres, 1L); // true (succeed)
2496 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2497 } else {
2498 Label done;
2499 __ load_const_optimized(Rres, 0L); // false (failed)
2500 __ z_brne(done); // Assume true to be the common case.
2501 __ load_const_optimized(Rres, 1L); // true (succeed)
2502 __ bind(done);
2503 }
2504 %}
2505
2506 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2507 Register Rcomp = reg_to_register_object($compare_value$$reg);
2508 Register Rnew = reg_to_register_object($exchange_value$$reg);
2509 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2510
2511 __ z_cs(Rcomp, Rnew, 0, Raddr);
2512 %}
2513
2514 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2515 Register Rcomp = reg_to_register_object($compare_value$$reg);
2516 Register Rnew = reg_to_register_object($exchange_value$$reg);
2517 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2518
2519 __ z_csg(Rcomp, Rnew, 0, Raddr);
2520 %}
2521
2522 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2523 Register Rdst = reg_to_register_object($dst$$reg);
2524 Register Rtmp = reg_to_register_object($tmp$$reg);
2525 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2526 Label retry;
2527
2528 // Iterate until swap succeeds.
2529 __ z_llgf(Rtmp, $mem$$Address); // current contents
2530 __ bind(retry);
2531 // Calculate incremented value.
2532 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2533 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2534 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2535 %}
2536
2537 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2538 Register Rdst = reg_to_register_object($dst$$reg);
2539 Register Rtmp = reg_to_register_object($tmp$$reg);
2540 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2541 Label retry;
2542
2543 // Iterate until swap succeeds.
2544 __ z_lg(Rtmp, $mem$$Address); // current contents
2545 __ bind(retry);
2546 // Calculate incremented value.
2547 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2548 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2549 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2550 %}
2551
2552 %} // encode
2553
2554 source %{
2555
2556 // Check whether outs are all Stores. If so, we can omit clearing the upper
2557 // 32 bits after encoding.
2558 static bool all_outs_are_Stores(const Node *n) {
2559 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2560 Node *out = n->fast_out(k);
2561 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2562 // Most other outs are SpillCopy, but there are various other.
2563 // jvm98 has arond 9% Encodes where we return false.
2564 return false;
2565 }
2566 }
2567 return true;
2568 }
2569
2570 %} // source
2571
2572
2573 //----------FRAME--------------------------------------------------------------
2574 // Definition of frame structure and management information.
2575
2576 frame %{
2577 // These two registers define part of the calling convention between
2578 // compiled code and the interpreter.
2579
2580 // Inline Cache Register
2581 inline_cache_reg(Z_R9); // Z_inline_cache
2582
2583 // Argument pointer for I2C adapters
2584 //
2585 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2586 // interpreter_arg_ptr_reg(Z_R6);
2587
2588 // Optional: name the operand used by cisc-spilling to access
2589 // [stack_pointer + offset].
2590 cisc_spilling_operand_name(indOffset12);
2591
2592 // Number of stack slots consumed by a Monitor enter.
2593 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2594
2595 // Compiled code's Frame Pointer
2596 //
2597 // z/Architecture stack pointer
2598 frame_pointer(Z_R15); // Z_SP
2599
2600 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2601 stack_alignment(frame::alignment_in_bytes);
2602
2603 // A `slot' is assumed 4 bytes here!
2604 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2605
2606 // Number of outgoing stack slots killed above the
2607 // out_preserve_stack_slots for calls to C. Supports the var-args
2608 // backing area for register parms.
2609 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2610
2611 // The after-PROLOG location of the return address. Location of
2612 // return address specifies a type (REG or STACK) and a number
2613 // representing the register number (i.e. - use a register name) or
2614 // stack slot.
2615 return_addr(REG Z_R14);
2616
2617 // Location of native (C/C++) and interpreter return values. This
2618 // is specified to be the same as Java. In the 32-bit VM, long
2619 // values are actually returned from native calls in O0:O1 and
2620 // returned to the interpreter in I0:I1. The copying to and from
2621 // the register pairs is done by the appropriate call and epilog
2622 // opcodes. This simplifies the register allocator.
2623 //
2624 // Use register pair for c return value.
2625 c_return_value %{
2626 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2627 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2628 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2629 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2630 %}
2631
2632 // Use register pair for return value.
2633 // Location of compiled Java return values. Same as C
2634 return_value %{
2635 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2636 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2637 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2638 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2639 %}
2640 %}
2641
2642
2643 //----------ATTRIBUTES---------------------------------------------------------
2644
2645 //----------Operand Attributes-------------------------------------------------
2646 op_attrib op_cost(1); // Required cost attribute
2647
2648 //----------Instruction Attributes---------------------------------------------
2649
2650 // Cost attribute. required.
2651 ins_attrib ins_cost(DEFAULT_COST);
2652
2653 // Is this instruction a non-matching short branch variant of some
2654 // long branch? Not required.
2655 ins_attrib ins_short_branch(0);
2656
2657 // Indicates this is a trap based check node and final control-flow fixup
2658 // must generate a proper fall through.
2659 ins_attrib ins_is_TrapBasedCheckNode(true);
2660
2661 // Attribute of instruction to tell how many constants the instruction will generate.
2662 // (optional attribute). Default: 0.
2663 ins_attrib ins_num_consts(0);
2664
2665 // Required alignment attribute (must be a power of 2)
2666 // specifies the alignment that some part of the instruction (not
2667 // necessarily the start) requires. If > 1, a compute_padding()
2668 // function must be provided for the instruction.
2669 //
2670 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2671 // instructions which depend on the proper alignment, because the
2672 // desired alignment isn't guaranteed for the call to "emit()" during
2673 // the size computation.
2674 ins_attrib ins_alignment(1);
2675
2676 // Enforce/prohibit rematerializations.
2677 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2678 // then rematerialization of that instruction is prohibited and the
2679 // instruction's value will be spilled if necessary.
2680 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2681 // then rematerialization is enforced and the instruction's value will
2682 // never get spilled. a copy of the instruction will be inserted if
2683 // necessary.
2684 // Note: this may result in rematerializations in front of every use.
2685 // (optional attribute)
2686 ins_attrib ins_cannot_rematerialize(false);
2687 ins_attrib ins_should_rematerialize(false);
2688
2689 //----------OPERANDS-----------------------------------------------------------
2690 // Operand definitions must precede instruction definitions for correct
2691 // parsing in the ADLC because operands constitute user defined types
2692 // which are used in instruction definitions.
2693
2694 //----------Simple Operands----------------------------------------------------
2695 // Immediate Operands
2696 // Please note:
2697 // Formats are generated automatically for constants and base registers.
2698 operand vecX() %{
2699 constraint(ALLOC_IN_RC(z_v_reg));
2700 match(VecX);
2701 match(v16TempReg);
2702 match(v17TempReg);
2703 match(v18TempReg);
2704 match(v19TempReg);
2705 match(v20TempReg);
2706 match(v21TempReg);
2707 match(v22TempReg);
2708 match(v23TempReg);
2709 match(v24TempReg);
2710 match(v25TempReg);
2711 format %{ %}
2712 interface(REG_INTER);
2713 %}
2714
2715 operand v16TempReg() %{
2716 constraint(ALLOC_IN_RC(z_vreg_16));
2717 match(VecX);
2718 format %{ %}
2719 interface(REG_INTER);
2720 %}
2721
2722 operand v17TempReg() %{
2723 constraint(ALLOC_IN_RC(z_vreg_17));
2724 match(VecX);
2725 format %{ %}
2726 interface(REG_INTER);
2727 %}
2728
2729 operand v18TempReg() %{
2730 constraint(ALLOC_IN_RC(z_vreg_18));
2731 match(VecX);
2732 format %{ %}
2733 interface(REG_INTER);
2734 %}
2735
2736 operand v19TempReg() %{
2737 constraint(ALLOC_IN_RC(z_vreg_19));
2738 match(VecX);
2739 format %{ %}
2740 interface(REG_INTER);
2741 %}
2742
2743 operand v20TempReg() %{
2744 constraint(ALLOC_IN_RC(z_vreg_20));
2745 match(VecX);
2746 format %{ %}
2747 interface(REG_INTER);
2748 %}
2749
2750 operand v21TempReg() %{
2751 constraint(ALLOC_IN_RC(z_vreg_21));
2752 match(VecX);
2753 format %{ %}
2754 interface(REG_INTER);
2755 %}
2756
2757 operand v22TempReg() %{
2758 constraint(ALLOC_IN_RC(z_vreg_22));
2759 match(VecX);
2760 format %{ %}
2761 interface(REG_INTER);
2762 %}
2763
2764 operand v23TempReg() %{
2765 constraint(ALLOC_IN_RC(z_vreg_23));
2766 match(VecX);
2767 format %{ %}
2768 interface(REG_INTER);
2769 %}
2770
2771 operand v24TempReg() %{
2772 constraint(ALLOC_IN_RC(z_vreg_24));
2773 match(VecX);
2774 format %{ %}
2775 interface(REG_INTER);
2776 %}
2777
2778 operand v25TempReg() %{
2779 constraint(ALLOC_IN_RC(z_vreg_25));
2780 match(VecX);
2781 format %{ %}
2782 interface(REG_INTER);
2783 %}
2784
2785 //----------------------------------------------
2786 // SIGNED (shorter than INT) immediate operands
2787 //----------------------------------------------
2788
2789 // Byte Immediate: constant 'int -1'
2790 operand immB_minus1() %{
2791 // sign-ext constant zero-ext constant
2792 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2793 match(ConI);
2794 op_cost(1);
2795 format %{ %}
2796 interface(CONST_INTER);
2797 %}
2798
2799 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2800 operand immB_n0m1() %{
2801 // sign-ext constant zero-ext constant
2802 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2803 match(ConI);
2804 op_cost(1);
2805 format %{ %}
2806 interface(CONST_INTER);
2807 %}
2808
2809 // Short Immediate: constant 'int -1'
2810 operand immS_minus1() %{
2811 // sign-ext constant zero-ext constant
2812 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2813 match(ConI);
2814 op_cost(1);
2815 format %{ %}
2816 interface(CONST_INTER);
2817 %}
2818
2819 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2820 operand immS_n0m1() %{
2821 // sign-ext constant zero-ext constant
2822 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2823 match(ConI);
2824 op_cost(1);
2825 format %{ %}
2826 interface(CONST_INTER);
2827 %}
2828
2829 //-----------------------------------------
2830 // SIGNED INT immediate operands
2831 //-----------------------------------------
2832
2833 // Integer Immediate: 32-bit
2834 operand immI() %{
2835 match(ConI);
2836 op_cost(1);
2837 format %{ %}
2838 interface(CONST_INTER);
2839 %}
2840
2841 // Int Immediate: 20-bit
2842 operand immI20() %{
2843 predicate(Immediate::is_simm20(n->get_int()));
2844 match(ConI);
2845 op_cost(1);
2846 format %{ %}
2847 interface(CONST_INTER);
2848 %}
2849
2850 // Integer Immediate: 16-bit
2851 operand immI16() %{
2852 predicate(Immediate::is_simm16(n->get_int()));
2853 match(ConI);
2854 op_cost(1);
2855 format %{ %}
2856 interface(CONST_INTER);
2857 %}
2858
2859 // Integer Immediate: 8-bit
2860 operand immI8() %{
2861 predicate(Immediate::is_simm8(n->get_int()));
2862 match(ConI);
2863 op_cost(1);
2864 format %{ %}
2865 interface(CONST_INTER);
2866 %}
2867
2868 // Integer Immediate: constant 'int 0'
2869 operand immI_0() %{
2870 predicate(n->get_int() == 0);
2871 match(ConI);
2872 op_cost(1);
2873 format %{ %}
2874 interface(CONST_INTER);
2875 %}
2876
2877 // Integer Immediate: constant 'int -1'
2878 operand immI_minus1() %{
2879 predicate(n->get_int() == -1);
2880 match(ConI);
2881 op_cost(1);
2882 format %{ %}
2883 interface(CONST_INTER);
2884 %}
2885
2886 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2887 operand immI_n0m1() %{
2888 predicate(n->get_int() != 0 && n->get_int() != -1);
2889 match(ConI);
2890 op_cost(1);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 //-------------------------------------------
2896 // UNSIGNED INT immediate operands
2897 //-------------------------------------------
2898
2899 // Unsigned Integer Immediate: 32-bit
2900 operand uimmI() %{
2901 match(ConI);
2902 op_cost(1);
2903 format %{ %}
2904 interface(CONST_INTER);
2905 %}
2906
2907 // Unsigned Integer Immediate: 16-bit
2908 operand uimmI16() %{
2909 predicate(Immediate::is_uimm16(n->get_int()));
2910 match(ConI);
2911 op_cost(1);
2912 format %{ %}
2913 interface(CONST_INTER);
2914 %}
2915
2916 // Unsigned Integer Immediate: 12-bit
2917 operand uimmI12() %{
2918 predicate(Immediate::is_uimm12(n->get_int()));
2919 match(ConI);
2920 op_cost(1);
2921 format %{ %}
2922 interface(CONST_INTER);
2923 %}
2924
2925 // Unsigned Integer Immediate: 12-bit
2926 operand uimmI8() %{
2927 predicate(Immediate::is_uimm8(n->get_int()));
2928 match(ConI);
2929 op_cost(1);
2930 format %{ %}
2931 interface(CONST_INTER);
2932 %}
2933
2934 // Length for SS instructions, given in DWs,
2935 // possible range [1..512], i.e. [8..4096] Bytes
2936 // used range [1..256], i.e. [8..2048] Bytes
2937 // operand type int
2938 // Unsigned Integer Immediate: 9-bit
2939 operand SSlenDW() %{
2940 predicate(Immediate::is_uimm8((julong)n->get_long()-1));
2941 match(ConL);
2942 op_cost(1);
2943 format %{ %}
2944 interface(CONST_INTER);
2945 %}
2946
2947 //------------------------------------------
2948 // (UN)SIGNED INT specific values
2949 //------------------------------------------
2950
2951 // Integer Immediate: the value 1
2952 operand immI_1() %{
2953 predicate(n->get_int() == 1);
2954 match(ConI);
2955 op_cost(1);
2956 format %{ %}
2957 interface(CONST_INTER);
2958 %}
2959
2960 // Integer Immediate: the value 16.
2961 operand immI_16() %{
2962 predicate(n->get_int() == 16);
2963 match(ConI);
2964 op_cost(1);
2965 format %{ %}
2966 interface(CONST_INTER);
2967 %}
2968
2969 // Integer Immediate: the value 24.
2970 operand immI_24() %{
2971 predicate(n->get_int() == 24);
2972 match(ConI);
2973 op_cost(1);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 // Integer Immediate: the values 32-63
2979 operand immI_32_63() %{
2980 predicate(n->get_int() >= 32 && n->get_int() <= 63);
2981 match(ConI);
2982 op_cost(1);
2983 format %{ %}
2984 interface(CONST_INTER);
2985 %}
2986
2987 // Unsigned Integer Immediate: LL-part, extended by 1s.
2988 operand uimmI_LL1() %{
2989 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2990 match(ConI);
2991 op_cost(1);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 // Unsigned Integer Immediate: LH-part, extended by 1s.
2997 operand uimmI_LH1() %{
2998 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2999 match(ConI);
3000 op_cost(1);
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 //------------------------------------------
3006 // SIGNED LONG immediate operands
3007 //------------------------------------------
3008
3009 operand immL() %{
3010 match(ConL);
3011 op_cost(1);
3012 format %{ %}
3013 interface(CONST_INTER);
3014 %}
3015
3016 // Long Immediate: 32-bit
3017 operand immL32() %{
3018 predicate(Immediate::is_simm32(n->get_long()));
3019 match(ConL);
3020 op_cost(1);
3021 format %{ %}
3022 interface(CONST_INTER);
3023 %}
3024
3025 // Long Immediate: 20-bit
3026 operand immL20() %{
3027 predicate(Immediate::is_simm20(n->get_long()));
3028 match(ConL);
3029 op_cost(1);
3030 format %{ %}
3031 interface(CONST_INTER);
3032 %}
3033
3034 // Long Immediate: 16-bit
3035 operand immL16() %{
3036 predicate(Immediate::is_simm16(n->get_long()));
3037 match(ConL);
3038 op_cost(1);
3039 format %{ %}
3040 interface(CONST_INTER);
3041 %}
3042
3043 // Long Immediate: 8-bit
3044 operand immL8() %{
3045 predicate(Immediate::is_simm8(n->get_long()));
3046 match(ConL);
3047 op_cost(1);
3048 format %{ %}
3049 interface(CONST_INTER);
3050 %}
3051
3052 //--------------------------------------------
3053 // UNSIGNED LONG immediate operands
3054 //--------------------------------------------
3055
3056 operand uimmL32() %{
3057 predicate(Immediate::is_uimm32(n->get_long()));
3058 match(ConL);
3059 op_cost(1);
3060 format %{ %}
3061 interface(CONST_INTER);
3062 %}
3063
3064 // Unsigned Long Immediate: 16-bit
3065 operand uimmL16() %{
3066 predicate(Immediate::is_uimm16(n->get_long()));
3067 match(ConL);
3068 op_cost(1);
3069 format %{ %}
3070 interface(CONST_INTER);
3071 %}
3072
3073 // Unsigned Long Immediate: 12-bit
3074 operand uimmL12() %{
3075 predicate(Immediate::is_uimm12(n->get_long()));
3076 match(ConL);
3077 op_cost(1);
3078 format %{ %}
3079 interface(CONST_INTER);
3080 %}
3081
3082 //-------------------------------------------
3083 // (UN)SIGNED LONG specific values
3084 //-------------------------------------------
3085
3086 // Long Immediate: the value FFFFFFFF
3087 operand immL_FFFFFFFF() %{
3088 predicate(n->get_long() == 0xFFFFFFFFL);
3089 match(ConL);
3090 op_cost(1);
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095 operand immL_0() %{
3096 predicate(n->get_long() == 0L);
3097 match(ConL);
3098 op_cost(1);
3099 format %{ %}
3100 interface(CONST_INTER);
3101 %}
3102
3103 // Unsigned Long Immediate: LL-part, extended by 1s.
3104 operand uimmL_LL1() %{
3105 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
3106 match(ConL);
3107 op_cost(1);
3108 format %{ %}
3109 interface(CONST_INTER);
3110 %}
3111
3112 // Unsigned Long Immediate: LH-part, extended by 1s.
3113 operand uimmL_LH1() %{
3114 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
3115 match(ConL);
3116 op_cost(1);
3117 format %{ %}
3118 interface(CONST_INTER);
3119 %}
3120
3121 // Unsigned Long Immediate: HL-part, extended by 1s.
3122 operand uimmL_HL1() %{
3123 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
3124 match(ConL);
3125 op_cost(1);
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3129
3130 // Unsigned Long Immediate: HH-part, extended by 1s.
3131 operand uimmL_HH1() %{
3132 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
3133 match(ConL);
3134 op_cost(1);
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // Long Immediate: low 32-bit mask
3140 operand immL_32bits() %{
3141 predicate(n->get_long() == 0xFFFFFFFFL);
3142 match(ConL);
3143 op_cost(1);
3144 format %{ %}
3145 interface(CONST_INTER);
3146 %}
3147
3148 //--------------------------------------
3149 // POINTER immediate operands
3150 //--------------------------------------
3151
3152 // Pointer Immediate: 64-bit
3153 operand immP() %{
3154 match(ConP);
3155 op_cost(1);
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3159
3160 // Pointer Immediate: 16-bit
3161 operand immP16() %{
3162 predicate(Immediate::is_uimm16(n->get_ptr()));
3163 match(ConP);
3164 op_cost(1);
3165 format %{ %}
3166 interface(CONST_INTER);
3167 %}
3168
3169 // Pointer Immediate: 8-bit
3170 operand immP8() %{
3171 predicate(Immediate::is_uimm8(n->get_ptr()));
3172 match(ConP);
3173 op_cost(1);
3174 format %{ %}
3175 interface(CONST_INTER);
3176 %}
3177
3178 //-----------------------------------
3179 // POINTER specific values
3180 //-----------------------------------
3181
3182 // Pointer Immediate: nullptr
3183 operand immP0() %{
3184 predicate(n->get_ptr() == 0);
3185 match(ConP);
3186 op_cost(1);
3187 format %{ %}
3188 interface(CONST_INTER);
3189 %}
3190
3191 //---------------------------------------------
3192 // NARROW POINTER immediate operands
3193 //---------------------------------------------
3194
3195 // Narrow Pointer Immediate
3196 operand immN() %{
3197 match(ConN);
3198 op_cost(1);
3199 format %{ %}
3200 interface(CONST_INTER);
3201 %}
3202
3203 operand immNKlass() %{
3204 match(ConNKlass);
3205 op_cost(1);
3206 format %{ %}
3207 interface(CONST_INTER);
3208 %}
3209
3210 // Narrow Pointer Immediate
3211 operand immN8() %{
3212 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3213 match(ConN);
3214 op_cost(1);
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 // Narrow Null Pointer Immediate
3220 operand immN0() %{
3221 predicate(n->get_narrowcon() == 0);
3222 match(ConN);
3223 op_cost(1);
3224 format %{ %}
3225 interface(CONST_INTER);
3226 %}
3227
3228 // FLOAT and DOUBLE immediate operands
3229
3230 // Double Immediate
3231 operand immD() %{
3232 match(ConD);
3233 op_cost(1);
3234 format %{ %}
3235 interface(CONST_INTER);
3236 %}
3237
3238 // Double Immediate: +-0
3239 operand immDpm0() %{
3240 predicate(n->getd() == 0);
3241 match(ConD);
3242 op_cost(1);
3243 format %{ %}
3244 interface(CONST_INTER);
3245 %}
3246
3247 // Double Immediate: +0
3248 operand immDp0() %{
3249 predicate(jlong_cast(n->getd()) == 0);
3250 match(ConD);
3251 op_cost(1);
3252 format %{ %}
3253 interface(CONST_INTER);
3254 %}
3255
3256 // Float Immediate
3257 operand immF() %{
3258 match(ConF);
3259 op_cost(1);
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // Float Immediate: +-0
3265 operand immFpm0() %{
3266 predicate(n->getf() == 0);
3267 match(ConF);
3268 op_cost(1);
3269 format %{ %}
3270 interface(CONST_INTER);
3271 %}
3272
3273 // Float Immediate: +0
3274 operand immFp0() %{
3275 predicate(jint_cast(n->getf()) == 0);
3276 match(ConF);
3277 op_cost(1);
3278 format %{ %}
3279 interface(CONST_INTER);
3280 %}
3281
3282 // End of Immediate Operands
3283
3284 // Integer Register Operands
3285 // Integer Register
3286 operand iRegI() %{
3287 constraint(ALLOC_IN_RC(z_int_reg));
3288 match(RegI);
3289 match(noArg_iRegI);
3290 match(rarg1RegI);
3291 match(rarg2RegI);
3292 match(rarg3RegI);
3293 match(rarg4RegI);
3294 match(rarg5RegI);
3295 match(noOdd_iRegI);
3296 match(revenRegI);
3297 match(roddRegI);
3298 format %{ %}
3299 interface(REG_INTER);
3300 %}
3301
3302 operand noArg_iRegI() %{
3303 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3304 match(RegI);
3305 format %{ %}
3306 interface(REG_INTER);
3307 %}
3308
3309 // revenRegI and roddRegI constitute and even-odd-pair.
3310 operand revenRegI() %{
3311 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3312 match(iRegI);
3313 format %{ %}
3314 interface(REG_INTER);
3315 %}
3316
3317 // revenRegI and roddRegI constitute and even-odd-pair.
3318 operand roddRegI() %{
3319 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3320 match(iRegI);
3321 format %{ %}
3322 interface(REG_INTER);
3323 %}
3324
3325 operand rarg1RegI() %{
3326 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3327 match(iRegI);
3328 format %{ %}
3329 interface(REG_INTER);
3330 %}
3331
3332 operand rarg2RegI() %{
3333 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3334 match(iRegI);
3335 format %{ %}
3336 interface(REG_INTER);
3337 %}
3338
3339 operand rarg3RegI() %{
3340 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3341 match(iRegI);
3342 format %{ %}
3343 interface(REG_INTER);
3344 %}
3345
3346 operand rarg4RegI() %{
3347 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3348 match(iRegI);
3349 format %{ %}
3350 interface(REG_INTER);
3351 %}
3352
3353 operand rarg5RegI() %{
3354 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3355 match(iRegI);
3356 format %{ %}
3357 interface(REG_INTER);
3358 %}
3359
3360 operand noOdd_iRegI() %{
3361 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3362 match(RegI);
3363 match(revenRegI);
3364 format %{ %}
3365 interface(REG_INTER);
3366 %}
3367
3368 // Pointer Register
3369 operand iRegP() %{
3370 constraint(ALLOC_IN_RC(z_ptr_reg));
3371 match(RegP);
3372 match(noArg_iRegP);
3373 match(rarg1RegP);
3374 match(rarg2RegP);
3375 match(rarg3RegP);
3376 match(rarg4RegP);
3377 match(rarg5RegP);
3378 match(revenRegP);
3379 match(roddRegP);
3380 match(r10TempRegP);
3381 match(r11TempRegP);
3382 format %{ %}
3383 interface(REG_INTER);
3384 %}
3385
3386 // thread operand
3387 operand threadRegP() %{
3388 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3389 match(RegP);
3390 format %{ "Z_THREAD" %}
3391 interface(REG_INTER);
3392 %}
3393
3394 operand r10TempRegP() %{
3395 constraint(ALLOC_IN_RC(z_r10_ptr_reg));
3396 match(iRegP);
3397 format %{ %}
3398 interface(REG_INTER);
3399 %}
3400
3401 operand r11TempRegP() %{
3402 constraint(ALLOC_IN_RC(z_r11_ptr_reg));
3403 match(iRegP);
3404 format %{ %}
3405 interface(REG_INTER);
3406 %}
3407
3408 operand noArg_iRegP() %{
3409 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3410 match(iRegP);
3411 format %{ %}
3412 interface(REG_INTER);
3413 %}
3414
3415 operand rarg1RegP() %{
3416 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3417 match(iRegP);
3418 format %{ %}
3419 interface(REG_INTER);
3420 %}
3421
3422 operand rarg2RegP() %{
3423 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3424 match(iRegP);
3425 format %{ %}
3426 interface(REG_INTER);
3427 %}
3428
3429 operand rarg3RegP() %{
3430 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3431 match(iRegP);
3432 format %{ %}
3433 interface(REG_INTER);
3434 %}
3435
3436 operand rarg4RegP() %{
3437 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3438 match(iRegP);
3439 format %{ %}
3440 interface(REG_INTER);
3441 %}
3442
3443 operand rarg5RegP() %{
3444 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3445 match(iRegP);
3446 format %{ %}
3447 interface(REG_INTER);
3448 %}
3449
3450 operand memoryRegP() %{
3451 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3452 match(RegP);
3453 match(iRegP);
3454 match(threadRegP);
3455 format %{ %}
3456 interface(REG_INTER);
3457 %}
3458
3459 // revenRegP and roddRegP constitute and even-odd-pair.
3460 operand revenRegP() %{
3461 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3462 match(iRegP);
3463 format %{ %}
3464 interface(REG_INTER);
3465 %}
3466
3467 // revenRegP and roddRegP constitute and even-odd-pair.
3468 operand roddRegP() %{
3469 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3470 match(iRegP);
3471 format %{ %}
3472 interface(REG_INTER);
3473 %}
3474
3475 operand iRegN() %{
3476 constraint(ALLOC_IN_RC(z_int_reg));
3477 match(RegN);
3478 match(noArg_iRegN);
3479 match(rarg1RegN);
3480 match(rarg2RegN);
3481 match(rarg3RegN);
3482 match(rarg4RegN);
3483 match(rarg5RegN);
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 operand noArg_iRegN() %{
3489 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3490 match(iRegN);
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3494
3495 operand rarg1RegN() %{
3496 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3497 match(iRegN);
3498 format %{ %}
3499 interface(REG_INTER);
3500 %}
3501
3502 operand rarg2RegN() %{
3503 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3504 match(iRegN);
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 operand rarg3RegN() %{
3510 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3511 match(iRegN);
3512 format %{ %}
3513 interface(REG_INTER);
3514 %}
3515
3516 operand rarg4RegN() %{
3517 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3518 match(iRegN);
3519 format %{ %}
3520 interface(REG_INTER);
3521 %}
3522
3523 operand rarg5RegN() %{
3524 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3525 match(iRegN);
3526 format %{ %}
3527 interface(REG_INTER);
3528 %}
3529
3530 // Long Register
3531 operand iRegL() %{
3532 constraint(ALLOC_IN_RC(z_long_reg));
3533 match(RegL);
3534 match(revenRegL);
3535 match(roddRegL);
3536 match(allRoddRegL);
3537 match(rarg1RegL);
3538 match(rarg5RegL);
3539 format %{ %}
3540 interface(REG_INTER);
3541 %}
3542
3543 // revenRegL and roddRegL constitute and even-odd-pair.
3544 operand revenRegL() %{
3545 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3546 match(iRegL);
3547 format %{ %}
3548 interface(REG_INTER);
3549 %}
3550
3551 // revenRegL and roddRegL constitute and even-odd-pair.
3552 operand roddRegL() %{
3553 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3554 match(iRegL);
3555 format %{ %}
3556 interface(REG_INTER);
3557 %}
3558
3559 // available odd registers for iRegL
3560 operand allRoddRegL() %{
3561 constraint(ALLOC_IN_RC(z_long_odd_reg));
3562 match(iRegL);
3563 format %{ %}
3564 interface(REG_INTER);
3565 %}
3566
3567 operand rarg1RegL() %{
3568 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3569 match(iRegL);
3570 format %{ %}
3571 interface(REG_INTER);
3572 %}
3573
3574 operand rarg5RegL() %{
3575 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3576 match(iRegL);
3577 format %{ %}
3578 interface(REG_INTER);
3579 %}
3580
3581 // Condition Code Flag Registers
3582 operand flagsReg() %{
3583 constraint(ALLOC_IN_RC(z_condition_reg));
3584 match(RegFlags);
3585 format %{ "CR" %}
3586 interface(REG_INTER);
3587 %}
3588
3589 operand regD() %{
3590 constraint(ALLOC_IN_RC(z_dbl_reg));
3591 match(RegD);
3592 format %{ %}
3593 interface(REG_INTER);
3594 %}
3595
3596 operand regF() %{
3597 constraint(ALLOC_IN_RC(z_flt_reg));
3598 match(RegF);
3599 format %{ %}
3600 interface(REG_INTER);
3601 %}
3602
3603 // Special Registers
3604
3605 // Method Register
3606 operand inline_cache_regP(iRegP reg) %{
3607 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3608 match(reg);
3609 format %{ %}
3610 interface(REG_INTER);
3611 %}
3612
3613 //----------Complex Operands---------------------------------------------------
3614
3615 // Indirect Memory Reference
3616 operand indirect(memoryRegP base) %{
3617 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3618 match(base);
3619 op_cost(1);
3620 format %{ "#0[,$base]" %}
3621 interface(MEMORY_INTER) %{
3622 base($base);
3623 index(0xffffFFFF); // noreg
3624 scale(0x0);
3625 disp(0x0);
3626 %}
3627 %}
3628
3629 // Indirect with Offset (long)
3630 operand indOffset20(memoryRegP base, immL20 offset) %{
3631 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3632 match(AddP base offset);
3633 op_cost(1);
3634 format %{ "$offset[,$base]" %}
3635 interface(MEMORY_INTER) %{
3636 base($base);
3637 index(0xffffFFFF); // noreg
3638 scale(0x0);
3639 disp($offset);
3640 %}
3641 %}
3642
3643 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3644 predicate(Matcher::narrow_oop_use_complex_address());
3645 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3646 match(AddP (DecodeN base) offset);
3647 op_cost(1);
3648 format %{ "$offset[,$base]" %}
3649 interface(MEMORY_INTER) %{
3650 base($base);
3651 index(0xffffFFFF); // noreg
3652 scale(0x0);
3653 disp($offset);
3654 %}
3655 %}
3656
3657 // Indirect with Offset (short)
3658 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3659 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3660 match(AddP base offset);
3661 op_cost(1);
3662 format %{ "$offset[[,$base]]" %}
3663 interface(MEMORY_INTER) %{
3664 base($base);
3665 index(0xffffFFFF); // noreg
3666 scale(0x0);
3667 disp($offset);
3668 %}
3669 %}
3670
3671 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3672 predicate(Matcher::narrow_oop_use_complex_address());
3673 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3674 match(AddP (DecodeN base) offset);
3675 op_cost(1);
3676 format %{ "$offset[[,$base]]" %}
3677 interface(MEMORY_INTER) %{
3678 base($base);
3679 index(0xffffFFFF); // noreg
3680 scale(0x0);
3681 disp($offset);
3682 %}
3683 %}
3684
3685 // Indirect with Register Index
3686 operand indIndex(memoryRegP base, iRegL index) %{
3687 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3688 match(AddP base index);
3689 op_cost(1);
3690 format %{ "#0[($index,$base)]" %}
3691 interface(MEMORY_INTER) %{
3692 base($base);
3693 index($index);
3694 scale(0x0);
3695 disp(0x0);
3696 %}
3697 %}
3698
3699 // Indirect with Offset (long) and index
3700 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3701 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3702 match(AddP (AddP base index) offset);
3703 op_cost(1);
3704 format %{ "$offset[($index,$base)]" %}
3705 interface(MEMORY_INTER) %{
3706 base($base);
3707 index($index);
3708 scale(0x0);
3709 disp($offset);
3710 %}
3711 %}
3712
3713 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3714 predicate(Matcher::narrow_oop_use_complex_address());
3715 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3716 match(AddP (AddP (DecodeN base) index) offset);
3717 op_cost(1);
3718 format %{ "$offset[($index,$base)]" %}
3719 interface(MEMORY_INTER) %{
3720 base($base);
3721 index($index);
3722 scale(0x0);
3723 disp($offset);
3724 %}
3725 %}
3726
3727 // Indirect with Offset (short) and index
3728 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3729 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3730 match(AddP (AddP base index) offset);
3731 op_cost(1);
3732 format %{ "$offset[[($index,$base)]]" %}
3733 interface(MEMORY_INTER) %{
3734 base($base);
3735 index($index);
3736 scale(0x0);
3737 disp($offset);
3738 %}
3739 %}
3740
3741 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3742 predicate(Matcher::narrow_oop_use_complex_address());
3743 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3744 match(AddP (AddP (DecodeN base) index) offset);
3745 op_cost(1);
3746 format %{ "$offset[[($index,$base)]]" %}
3747 interface(MEMORY_INTER) %{
3748 base($base);
3749 index($index);
3750 scale(0x0);
3751 disp($offset);
3752 %}
3753 %}
3754
3755 //----------Special Memory Operands--------------------------------------------
3756
3757 // Stack Slot Operand
3758 // This operand is used for loading and storing temporary values on
3759 // the stack where a match requires a value to flow through memory.
3760 operand stackSlotI(sRegI reg) %{
3761 constraint(ALLOC_IN_RC(stack_slots));
3762 op_cost(1);
3763 format %{ "[$reg(stackSlotI)]" %}
3764 interface(MEMORY_INTER) %{
3765 base(0xf); // Z_SP
3766 index(0xffffFFFF); // noreg
3767 scale(0x0);
3768 disp($reg); // stack offset
3769 %}
3770 %}
3771
3772 operand stackSlotP(sRegP reg) %{
3773 constraint(ALLOC_IN_RC(stack_slots));
3774 op_cost(1);
3775 format %{ "[$reg(stackSlotP)]" %}
3776 interface(MEMORY_INTER) %{
3777 base(0xf); // Z_SP
3778 index(0xffffFFFF); // noreg
3779 scale(0x0);
3780 disp($reg); // Stack Offset
3781 %}
3782 %}
3783
3784 operand stackSlotF(sRegF reg) %{
3785 constraint(ALLOC_IN_RC(stack_slots));
3786 op_cost(1);
3787 format %{ "[$reg(stackSlotF)]" %}
3788 interface(MEMORY_INTER) %{
3789 base(0xf); // Z_SP
3790 index(0xffffFFFF); // noreg
3791 scale(0x0);
3792 disp($reg); // Stack Offset
3793 %}
3794 %}
3795
3796 operand stackSlotD(sRegD reg) %{
3797 constraint(ALLOC_IN_RC(stack_slots));
3798 op_cost(1);
3799 //match(RegD);
3800 format %{ "[$reg(stackSlotD)]" %}
3801 interface(MEMORY_INTER) %{
3802 base(0xf); // Z_SP
3803 index(0xffffFFFF); // noreg
3804 scale(0x0);
3805 disp($reg); // Stack Offset
3806 %}
3807 %}
3808
3809 operand stackSlotL(sRegL reg) %{
3810 constraint(ALLOC_IN_RC(stack_slots));
3811 op_cost(1); //match(RegL);
3812 format %{ "[$reg(stackSlotL)]" %}
3813 interface(MEMORY_INTER) %{
3814 base(0xf); // Z_SP
3815 index(0xffffFFFF); // noreg
3816 scale(0x0);
3817 disp($reg); // Stack Offset
3818 %}
3819 %}
3820
3821 // Operands for expressing Control Flow
3822 // NOTE: Label is a predefined operand which should not be redefined in
3823 // the AD file. It is generically handled within the ADLC.
3824
3825 //----------Conditional Branch Operands----------------------------------------
3826 // Comparison Op - This is the operation of the comparison, and is limited to
3827 // the following set of codes:
3828 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3829 //
3830 // Other attributes of the comparison, such as unsignedness, are specified
3831 // by the comparison instruction that sets a condition code flags register.
3832 // That result is represented by a flags operand whose subtype is appropriate
3833 // to the unsignedness (etc.) of the comparison.
3834 //
3835 // Later, the instruction which matches both the Comparison Op (a Bool) and
3836 // the flags (produced by the Cmp) specifies the coding of the comparison op
3837 // by matching a specific subtype of Bool operand below.
3838
3839 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3840 // have mask bit #3 set.
3841 operand cmpOpT() %{
3842 match(Bool);
3843 format %{ "" %}
3844 interface(COND_INTER) %{
3845 equal(0x8); // Assembler::bcondEqual
3846 not_equal(0x6); // Assembler::bcondNotEqual
3847 less(0x4); // Assembler::bcondLow
3848 greater_equal(0xa); // Assembler::bcondNotLow
3849 less_equal(0xc); // Assembler::bcondNotHigh
3850 greater(0x2); // Assembler::bcondHigh
3851 overflow(0x1); // Assembler::bcondOverflow
3852 no_overflow(0xe); // Assembler::bcondNotOverflow
3853 %}
3854 %}
3855
3856 // When used for floating point comparisons: unordered is treated as less.
3857 operand cmpOpF() %{
3858 match(Bool);
3859 format %{ "" %}
3860 interface(COND_INTER) %{
3861 equal(0x8);
3862 not_equal(0x7); // Includes 'unordered'.
3863 less(0x5); // Includes 'unordered'.
3864 greater_equal(0xa);
3865 less_equal(0xd); // Includes 'unordered'.
3866 greater(0x2);
3867 overflow(0x0); // Not meaningful on z/Architecture.
3868 no_overflow(0x0); // leave unchanged (zero) therefore
3869 %}
3870 %}
3871
3872 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3873 operand cmpOp() %{
3874 match(Bool);
3875 format %{ "" %}
3876 interface(COND_INTER) %{
3877 equal(0x8);
3878 not_equal(0x7); // Includes 'unordered'.
3879 less(0x5); // Includes 'unordered'.
3880 greater_equal(0xa);
3881 less_equal(0xd); // Includes 'unordered'.
3882 greater(0x2);
3883 overflow(0x1); // Assembler::bcondOverflow
3884 no_overflow(0xe); // Assembler::bcondNotOverflow
3885 %}
3886 %}
3887
3888 //----------OPERAND CLASSES----------------------------------------------------
3889 // Operand Classes are groups of operands that are used to simplify
3890 // instruction definitions by not requiring the AD writer to specify
3891 // separate instructions for every form of operand when the
3892 // instruction accepts multiple operand types with the same basic
3893 // encoding and format. The classic case of this is memory operands.
3894 // Indirect is not included since its use is limited to Compare & Swap
3895
3896 // Most general memory operand, allows base, index, and long displacement.
3897 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3898 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3899
3900 // General memory operand, allows base, index, and short displacement.
3901 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3902
3903 // Memory operand, allows only base and long displacement.
3904 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3905
3906 // Memory operand, allows only base and short displacement.
3907 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3908
3909 // Operand classes to match encode and decode.
3910 opclass iRegN_P2N(iRegN);
3911 opclass iRegP_N2P(iRegP);
3912
3913
3914 //----------PIPELINE-----------------------------------------------------------
3915 pipeline %{
3916
3917 //----------ATTRIBUTES---------------------------------------------------------
3918 attributes %{
3919 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3920 variable_size_instructions;
3921 instruction_unit_size = 2;
3922
3923 // Meaningless on z/Architecture.
3924 max_instructions_per_bundle = 1;
3925
3926 // The z/Architecture processor fetches 64 bytes...
3927 instruction_fetch_unit_size = 64;
3928
3929 // ...in one line.
3930 instruction_fetch_units = 1
3931 %}
3932
3933 //----------RESOURCES----------------------------------------------------------
3934 // Resources are the functional units available to the machine.
3935 resources(
3936 Z_BR, // branch unit
3937 Z_CR, // condition unit
3938 Z_FX1, // integer arithmetic unit 1
3939 Z_FX2, // integer arithmetic unit 2
3940 Z_LDST1, // load/store unit 1
3941 Z_LDST2, // load/store unit 2
3942 Z_FP1, // float arithmetic unit 1
3943 Z_FP2, // float arithmetic unit 2
3944 Z_LDST = Z_LDST1 | Z_LDST2,
3945 Z_FX = Z_FX1 | Z_FX2,
3946 Z_FP = Z_FP1 | Z_FP2
3947 );
3948
3949 //----------PIPELINE DESCRIPTION-----------------------------------------------
3950 // Pipeline Description specifies the stages in the machine's pipeline.
3951 pipe_desc(
3952 // TODO: adapt
3953 Z_IF, // instruction fetch
3954 Z_IC,
3955 Z_D0, // decode
3956 Z_D1, // decode
3957 Z_D2, // decode
3958 Z_D3, // decode
3959 Z_Xfer1,
3960 Z_GD, // group definition
3961 Z_MP, // map
3962 Z_ISS, // issue
3963 Z_RF, // resource fetch
3964 Z_EX1, // execute (all units)
3965 Z_EX2, // execute (FP, LDST)
3966 Z_EX3, // execute (FP, LDST)
3967 Z_EX4, // execute (FP)
3968 Z_EX5, // execute (FP)
3969 Z_EX6, // execute (FP)
3970 Z_WB, // write back
3971 Z_Xfer2,
3972 Z_CP
3973 );
3974
3975 //----------PIPELINE CLASSES---------------------------------------------------
3976 // Pipeline Classes describe the stages in which input and output are
3977 // referenced by the hardware pipeline.
3978
3979 // Providing the `ins_pipe' declarations in the instruction
3980 // specifications seems to be of little use. So we use
3981 // `pipe_class_dummy' for all our instructions at present.
3982 pipe_class pipe_class_dummy() %{
3983 single_instruction;
3984 fixed_latency(4);
3985 %}
3986
3987 // SIGTRAP based implicit range checks in compiled code.
3988 // Currently, no pipe classes are used on z/Architecture.
3989 pipe_class pipe_class_trap() %{
3990 single_instruction;
3991 %}
3992
3993 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3994 single_instruction;
3995 dst : Z_EX1(write);
3996 src1 : Z_RF(read);
3997 src2 : Z_RF(read);
3998 Z_FX : Z_RF;
3999 %}
4000
4001 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
4002 single_instruction;
4003 mem : Z_RF(read);
4004 dst : Z_WB(write);
4005 Z_LDST : Z_RF;
4006 %}
4007
4008 define %{
4009 MachNop = pipe_class_dummy;
4010 %}
4011
4012 %}
4013
4014 //----------INSTRUCTIONS-------------------------------------------------------
4015
4016 //---------- Chain stack slots between similar types --------
4017
4018 // Load integer from stack slot.
4019 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
4020 match(Set dst src);
4021 ins_cost(MEMORY_REF_COST);
4022 // TODO: s390 port size(FIXED_SIZE);
4023 format %{ "L $dst,$src\t # stk reload int" %}
4024 opcode(L_ZOPC);
4025 ins_encode(z_form_rt_mem(dst, src));
4026 ins_pipe(pipe_class_dummy);
4027 %}
4028
4029 // Store integer to stack slot.
4030 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
4031 match(Set dst src);
4032 ins_cost(MEMORY_REF_COST);
4033 // TODO: s390 port size(FIXED_SIZE);
4034 format %{ "ST $src,$dst\t # stk spill int" %}
4035 opcode(ST_ZOPC);
4036 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4037 ins_pipe(pipe_class_dummy);
4038 %}
4039
4040 // Load long from stack slot.
4041 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
4042 match(Set dst src);
4043 ins_cost(MEMORY_REF_COST);
4044 // TODO: s390 port size(FIXED_SIZE);
4045 format %{ "LG $dst,$src\t # stk reload long" %}
4046 opcode(LG_ZOPC);
4047 ins_encode(z_form_rt_mem(dst, src));
4048 ins_pipe(pipe_class_dummy);
4049 %}
4050
4051 // Store long to stack slot.
4052 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
4053 match(Set dst src);
4054 ins_cost(MEMORY_REF_COST);
4055 size(6);
4056 format %{ "STG $src,$dst\t # stk spill long" %}
4057 opcode(STG_ZOPC);
4058 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4059 ins_pipe(pipe_class_dummy);
4060 %}
4061
4062 // Load pointer from stack slot, 64-bit encoding.
4063 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
4064 match(Set dst src);
4065 ins_cost(MEMORY_REF_COST);
4066 // TODO: s390 port size(FIXED_SIZE);
4067 format %{ "LG $dst,$src\t # stk reload ptr" %}
4068 opcode(LG_ZOPC);
4069 ins_encode(z_form_rt_mem(dst, src));
4070 ins_pipe(pipe_class_dummy);
4071 %}
4072
4073 // Store pointer to stack slot.
4074 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
4075 match(Set dst src);
4076 ins_cost(MEMORY_REF_COST);
4077 // TODO: s390 port size(FIXED_SIZE);
4078 format %{ "STG $src,$dst\t # stk spill ptr" %}
4079 opcode(STG_ZOPC);
4080 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4081 ins_pipe(pipe_class_dummy);
4082 %}
4083
4084 // Float types
4085
4086 // Load float value from stack slot.
4087 instruct stkF_to_regF(regF dst, stackSlotF src) %{
4088 match(Set dst src);
4089 ins_cost(MEMORY_REF_COST);
4090 size(4);
4091 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
4092 opcode(LE_ZOPC);
4093 ins_encode(z_form_rt_mem(dst, src));
4094 ins_pipe(pipe_class_dummy);
4095 %}
4096
4097 // Store float value to stack slot.
4098 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4099 match(Set dst src);
4100 ins_cost(MEMORY_REF_COST);
4101 size(4);
4102 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4103 opcode(STE_ZOPC);
4104 ins_encode(z_form_rt_mem(src, dst));
4105 ins_pipe(pipe_class_dummy);
4106 %}
4107
4108 // Load double value from stack slot.
4109 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4110 match(Set dst src);
4111 ins_cost(MEMORY_REF_COST);
4112 // TODO: s390 port size(FIXED_SIZE);
4113 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4114 opcode(LD_ZOPC);
4115 ins_encode(z_form_rt_mem(dst, src));
4116 ins_pipe(pipe_class_dummy);
4117 %}
4118
4119 // Store double value to stack slot.
4120 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4121 match(Set dst src);
4122 ins_cost(MEMORY_REF_COST);
4123 size(4);
4124 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4125 opcode(STD_ZOPC);
4126 ins_encode(z_form_rt_mem(src, dst));
4127 ins_pipe(pipe_class_dummy);
4128 %}
4129
4130 //----------Load/Store/Move Instructions---------------------------------------
4131
4132 //----------Load Instructions--------------------------------------------------
4133
4134 //------------------
4135 // MEMORY
4136 //------------------
4137
4138 // BYTE
4139 // Load Byte (8bit signed)
4140 instruct loadB(iRegI dst, memory mem) %{
4141 match(Set dst (LoadB mem));
4142 ins_cost(MEMORY_REF_COST);
4143 size(Z_DISP3_SIZE);
4144 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4145 opcode(LB_ZOPC, LB_ZOPC);
4146 ins_encode(z_form_rt_mem_opt(dst, mem));
4147 ins_pipe(pipe_class_dummy);
4148 %}
4149
4150 // Load Byte (8bit signed)
4151 instruct loadB2L(iRegL dst, memory mem) %{
4152 match(Set dst (ConvI2L (LoadB mem)));
4153 ins_cost(MEMORY_REF_COST);
4154 size(Z_DISP3_SIZE);
4155 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4156 opcode(LGB_ZOPC, LGB_ZOPC);
4157 ins_encode(z_form_rt_mem_opt(dst, mem));
4158 ins_pipe(pipe_class_dummy);
4159 %}
4160
4161 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4162 instruct loadUB(iRegI dst, memory mem) %{
4163 match(Set dst (LoadUB mem));
4164 ins_cost(MEMORY_REF_COST);
4165 size(Z_DISP3_SIZE);
4166 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4167 opcode(LLGC_ZOPC, LLGC_ZOPC);
4168 ins_encode(z_form_rt_mem_opt(dst, mem));
4169 ins_pipe(pipe_class_dummy);
4170 %}
4171
4172 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4173 instruct loadUB2L(iRegL dst, memory mem) %{
4174 match(Set dst (ConvI2L (LoadUB mem)));
4175 ins_cost(MEMORY_REF_COST);
4176 size(Z_DISP3_SIZE);
4177 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4178 opcode(LLGC_ZOPC, LLGC_ZOPC);
4179 ins_encode(z_form_rt_mem_opt(dst, mem));
4180 ins_pipe(pipe_class_dummy);
4181 %}
4182
4183 // CHAR/SHORT
4184
4185 // Load Short (16bit signed)
4186 instruct loadS(iRegI dst, memory mem) %{
4187 match(Set dst (LoadS mem));
4188 ins_cost(MEMORY_REF_COST);
4189 size(Z_DISP_SIZE);
4190 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4191 opcode(LHY_ZOPC, LH_ZOPC);
4192 ins_encode(z_form_rt_mem_opt(dst, mem));
4193 ins_pipe(pipe_class_dummy);
4194 %}
4195
4196 // Load Short (16bit signed)
4197 instruct loadS2L(iRegL dst, memory mem) %{
4198 match(Set dst (ConvI2L (LoadS mem)));
4199 ins_cost(MEMORY_REF_COST);
4200 size(Z_DISP3_SIZE);
4201 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4202 opcode(LGH_ZOPC, LGH_ZOPC);
4203 ins_encode(z_form_rt_mem_opt(dst, mem));
4204 ins_pipe(pipe_class_dummy);
4205 %}
4206
4207 // Load Char (16bit Unsigned)
4208 instruct loadUS(iRegI dst, memory mem) %{
4209 match(Set dst (LoadUS mem));
4210 ins_cost(MEMORY_REF_COST);
4211 size(Z_DISP3_SIZE);
4212 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4213 opcode(LLGH_ZOPC, LLGH_ZOPC);
4214 ins_encode(z_form_rt_mem_opt(dst, mem));
4215 ins_pipe(pipe_class_dummy);
4216 %}
4217
4218 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4219 instruct loadUS2L(iRegL dst, memory mem) %{
4220 match(Set dst (ConvI2L (LoadUS mem)));
4221 ins_cost(MEMORY_REF_COST);
4222 size(Z_DISP3_SIZE);
4223 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4224 opcode(LLGH_ZOPC, LLGH_ZOPC);
4225 ins_encode(z_form_rt_mem_opt(dst, mem));
4226 ins_pipe(pipe_class_dummy);
4227 %}
4228
4229 // INT
4230
4231 // Load Integer
4232 instruct loadI(iRegI dst, memory mem) %{
4233 match(Set dst (LoadI mem));
4234 ins_cost(MEMORY_REF_COST);
4235 size(Z_DISP_SIZE);
4236 format %{ "L(Y) $dst,$mem\t #" %}
4237 opcode(LY_ZOPC, L_ZOPC);
4238 ins_encode(z_form_rt_mem_opt(dst, mem));
4239 ins_pipe(pipe_class_dummy);
4240 %}
4241
4242 // Load and convert to long.
4243 instruct loadI2L(iRegL dst, memory mem) %{
4244 match(Set dst (ConvI2L (LoadI mem)));
4245 ins_cost(MEMORY_REF_COST);
4246 size(Z_DISP3_SIZE);
4247 format %{ "LGF $dst,$mem\t #" %}
4248 opcode(LGF_ZOPC, LGF_ZOPC);
4249 ins_encode(z_form_rt_mem_opt(dst, mem));
4250 ins_pipe(pipe_class_dummy);
4251 %}
4252
4253 // Load Unsigned Integer into a Long Register
4254 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4255 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4256 ins_cost(MEMORY_REF_COST);
4257 size(Z_DISP3_SIZE);
4258 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4259 opcode(LLGF_ZOPC, LLGF_ZOPC);
4260 ins_encode(z_form_rt_mem_opt(dst, mem));
4261 ins_pipe(pipe_class_dummy);
4262 %}
4263
4264 // range = array length (=jint)
4265 // Load Range
4266 instruct loadRange(iRegI dst, memory mem) %{
4267 match(Set dst (LoadRange mem));
4268 ins_cost(MEMORY_REF_COST);
4269 size(Z_DISP_SIZE);
4270 format %{ "L(Y) $dst,$mem\t # range" %}
4271 opcode(LY_ZOPC, L_ZOPC);
4272 ins_encode(z_form_rt_mem_opt(dst, mem));
4273 ins_pipe(pipe_class_dummy);
4274 %}
4275
4276 // LONG
4277
4278 // Load Long - aligned
4279 instruct loadL(iRegL dst, memory mem) %{
4280 match(Set dst (LoadL mem));
4281 ins_cost(MEMORY_REF_COST);
4282 size(Z_DISP3_SIZE);
4283 format %{ "LG $dst,$mem\t # long" %}
4284 opcode(LG_ZOPC, LG_ZOPC);
4285 ins_encode(z_form_rt_mem_opt(dst, mem));
4286 ins_pipe(pipe_class_dummy);
4287 %}
4288
4289 // Load Long - UNaligned
4290 instruct loadL_unaligned(iRegL dst, memory mem) %{
4291 match(Set dst (LoadL_unaligned mem));
4292 ins_cost(MEMORY_REF_COST);
4293 size(Z_DISP3_SIZE);
4294 format %{ "LG $dst,$mem\t # unaligned long" %}
4295 opcode(LG_ZOPC, LG_ZOPC);
4296 ins_encode(z_form_rt_mem_opt(dst, mem));
4297 ins_pipe(pipe_class_dummy);
4298 %}
4299
4300
4301 // PTR
4302
4303 // Load Pointer
4304 instruct loadP(iRegP dst, memory mem) %{
4305 match(Set dst (LoadP mem));
4306 predicate(n->as_Load()->barrier_data() == 0);
4307 ins_cost(MEMORY_REF_COST);
4308 size(Z_DISP3_SIZE);
4309 format %{ "LG $dst,$mem\t # ptr" %}
4310 opcode(LG_ZOPC, LG_ZOPC);
4311 ins_encode(z_form_rt_mem_opt(dst, mem));
4312 ins_pipe(pipe_class_dummy);
4313 %}
4314
4315 // LoadP + CastP2L
4316 instruct castP2X_loadP(iRegL dst, memory mem) %{
4317 match(Set dst (CastP2X (LoadP mem)));
4318 predicate(n->as_Load()->barrier_data() == 0);
4319 ins_cost(MEMORY_REF_COST);
4320 size(Z_DISP3_SIZE);
4321 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4322 opcode(LG_ZOPC, LG_ZOPC);
4323 ins_encode(z_form_rt_mem_opt(dst, mem));
4324 ins_pipe(pipe_class_dummy);
4325 %}
4326
4327 // Load Klass Pointer
4328 instruct loadKlass(iRegP dst, memory mem) %{
4329 match(Set dst (LoadKlass mem));
4330 ins_cost(MEMORY_REF_COST);
4331 size(Z_DISP3_SIZE);
4332 format %{ "LG $dst,$mem\t # klass ptr" %}
4333 opcode(LG_ZOPC, LG_ZOPC);
4334 ins_encode(z_form_rt_mem_opt(dst, mem));
4335 ins_pipe(pipe_class_dummy);
4336 %}
4337
4338 instruct loadTOC(iRegL dst) %{
4339 effect(DEF dst);
4340 ins_cost(DEFAULT_COST);
4341 // TODO: s390 port size(FIXED_SIZE);
4342 // TODO: check why this attribute causes many unnecessary rematerializations.
4343 //
4344 // The graphs I saw just had high register pressure. Further the
4345 // register TOC is loaded to is overwritten by the constant short
4346 // after. Here something as round robin register allocation might
4347 // help. But rematerializing seems not to hurt, jack even seems to
4348 // improve slightly.
4349 //
4350 // Without this flag we get spill-split recycle sanity check
4351 // failures in
4352 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4353 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4354 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4355 // stack. Later tlsLoadP is rematerialized, leaving the register
4356 // allocator with TOC on the stack and a badly placed reload.
4357 ins_should_rematerialize(true);
4358 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4359 ins_encode %{ __ load_toc($dst$$Register); %}
4360 ins_pipe(pipe_class_dummy);
4361 %}
4362
4363 // FLOAT
4364
4365 // Load Float
4366 instruct loadF(regF dst, memory mem) %{
4367 match(Set dst (LoadF mem));
4368 ins_cost(MEMORY_REF_COST);
4369 size(Z_DISP_SIZE);
4370 format %{ "LE(Y) $dst,$mem" %}
4371 opcode(LEY_ZOPC, LE_ZOPC);
4372 ins_encode(z_form_rt_mem_opt(dst, mem));
4373 ins_pipe(pipe_class_dummy);
4374 %}
4375
4376 // DOUBLE
4377
4378 // Load Double
4379 instruct loadD(regD dst, memory mem) %{
4380 match(Set dst (LoadD mem));
4381 ins_cost(MEMORY_REF_COST);
4382 size(Z_DISP_SIZE);
4383 format %{ "LD(Y) $dst,$mem" %}
4384 opcode(LDY_ZOPC, LD_ZOPC);
4385 ins_encode(z_form_rt_mem_opt(dst, mem));
4386 ins_pipe(pipe_class_dummy);
4387 %}
4388
4389 // Load Double - UNaligned
4390 instruct loadD_unaligned(regD dst, memory mem) %{
4391 match(Set dst (LoadD_unaligned mem));
4392 ins_cost(MEMORY_REF_COST);
4393 size(Z_DISP_SIZE);
4394 format %{ "LD(Y) $dst,$mem" %}
4395 opcode(LDY_ZOPC, LD_ZOPC);
4396 ins_encode(z_form_rt_mem_opt(dst, mem));
4397 ins_pipe(pipe_class_dummy);
4398 %}
4399
4400
4401 //----------------------
4402 // IMMEDIATES
4403 //----------------------
4404
4405 instruct loadConI(iRegI dst, immI src) %{
4406 match(Set dst src);
4407 ins_cost(DEFAULT_COST);
4408 size(6);
4409 format %{ "LGFI $dst,$src\t # (int)" %}
4410 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4411 ins_pipe(pipe_class_dummy);
4412 %}
4413
4414 instruct loadConI16(iRegI dst, immI16 src) %{
4415 match(Set dst src);
4416 ins_cost(DEFAULT_COST_LOW);
4417 size(4);
4418 format %{ "LGHI $dst,$src\t # (int)" %}
4419 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4420 ins_pipe(pipe_class_dummy);
4421 %}
4422
4423 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4424 match(Set dst src);
4425 effect(KILL cr);
4426 ins_cost(DEFAULT_COST_LOW);
4427 size(4);
4428 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4429 opcode(XGR_ZOPC);
4430 ins_encode(z_rreform(dst, dst));
4431 ins_pipe(pipe_class_dummy);
4432 %}
4433
4434 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4435 match(Set dst src);
4436 // TODO: s390 port size(FIXED_SIZE);
4437 format %{ "LLILL $dst,$src" %}
4438 opcode(LLILL_ZOPC);
4439 ins_encode(z_riform_unsigned(dst, src) );
4440 ins_pipe(pipe_class_dummy);
4441 %}
4442
4443 // Load long constant from TOC with pcrelative address.
4444 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4445 match(Set dst src);
4446 ins_cost(MEMORY_REF_COST_LO);
4447 size(6);
4448 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4449 ins_encode %{
4450 address long_address = __ long_constant($src$$constant);
4451 if (long_address == nullptr) {
4452 Compile::current()->env()->record_out_of_memory_failure();
4453 return;
4454 }
4455 __ load_long_pcrelative($dst$$Register, long_address);
4456 %}
4457 ins_pipe(pipe_class_dummy);
4458 %}
4459
4460 instruct loadConL32(iRegL dst, immL32 src) %{
4461 match(Set dst src);
4462 ins_cost(DEFAULT_COST);
4463 size(6);
4464 format %{ "LGFI $dst,$src\t # (long)" %}
4465 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4466 ins_pipe(pipe_class_dummy);
4467 %}
4468
4469 instruct loadConL16(iRegL dst, immL16 src) %{
4470 match(Set dst src);
4471 ins_cost(DEFAULT_COST_LOW);
4472 size(4);
4473 format %{ "LGHI $dst,$src\t # (long)" %}
4474 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4475 ins_pipe(pipe_class_dummy);
4476 %}
4477
4478 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4479 match(Set dst src);
4480 effect(KILL cr);
4481 ins_cost(DEFAULT_COST_LOW);
4482 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4483 opcode(XGR_ZOPC);
4484 ins_encode(z_rreform(dst, dst));
4485 ins_pipe(pipe_class_dummy);
4486 %}
4487
4488 // Load ptr constant from TOC with pc relative address.
4489 // Special handling for oop constants required.
4490 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4491 match(Set dst src);
4492 ins_cost(MEMORY_REF_COST_LO);
4493 size(6);
4494 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4495 ins_encode %{
4496 relocInfo::relocType constant_reloc = $src->constant_reloc();
4497 if (constant_reloc == relocInfo::oop_type) {
4498 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4499 bool success = __ load_oop_from_toc($dst$$Register, a);
4500 if (!success) {
4501 Compile::current()->env()->record_out_of_memory_failure();
4502 return;
4503 }
4504 } else if (constant_reloc == relocInfo::metadata_type) {
4505 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4506 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4507 if (const_toc_addr == nullptr) {
4508 Compile::current()->env()->record_out_of_memory_failure();
4509 return;
4510 }
4511 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4512 } else { // Non-oop pointers, e.g. card mark base, heap top.
4513 address long_address = __ long_constant((jlong)$src$$constant);
4514 if (long_address == nullptr) {
4515 Compile::current()->env()->record_out_of_memory_failure();
4516 return;
4517 }
4518 __ load_long_pcrelative($dst$$Register, long_address);
4519 }
4520 %}
4521 ins_pipe(pipe_class_dummy);
4522 %}
4523
4524 // We don't use immP16 to avoid problems with oops.
4525 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4526 match(Set dst src);
4527 effect(KILL cr);
4528 size(4);
4529 format %{ "XGR $dst,$dst\t # null pointer" %}
4530 opcode(XGR_ZOPC);
4531 ins_encode(z_rreform(dst, dst));
4532 ins_pipe(pipe_class_dummy);
4533 %}
4534
4535 //----------Load Float Constant Instructions-------------------------------------------------
4536
4537 // We may not specify this instruction via an `expand' rule. If we do,
4538 // code selection will forget that this instruction needs a floating
4539 // point constant inserted into the code buffer. So `Shorten_branches'
4540 // will fail.
4541 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4542 match(Set dst src);
4543 effect(KILL cr);
4544 ins_cost(MEMORY_REF_COST);
4545 size(6);
4546 // If this instruction rematerializes, it prolongs the live range
4547 // of the toc node, causing illegal graphs.
4548 ins_cannot_rematerialize(true);
4549 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4550 ins_encode %{
4551 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4552 %}
4553 ins_pipe(pipe_class_dummy);
4554 %}
4555
4556 // E may not specify this instruction via an `expand' rule. If we do,
4557 // code selection will forget that this instruction needs a floating
4558 // point constant inserted into the code buffer. So `Shorten_branches'
4559 // will fail.
4560 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4561 match(Set dst src);
4562 effect(KILL cr);
4563 ins_cost(MEMORY_REF_COST);
4564 size(6);
4565 // If this instruction rematerializes, it prolongs the live range
4566 // of the toc node, causing illegal graphs.
4567 ins_cannot_rematerialize(true);
4568 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4569 ins_encode %{
4570 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4571 %}
4572 ins_pipe(pipe_class_dummy);
4573 %}
4574
4575 // Special case: Load Const 0.0F
4576
4577 // There's a special instr to clear a FP register.
4578 instruct loadConF0(regF dst, immFp0 src) %{
4579 match(Set dst src);
4580 ins_cost(DEFAULT_COST_LOW);
4581 size(4);
4582 format %{ "LZER $dst,$src\t # clear to zero" %}
4583 opcode(LZER_ZOPC);
4584 ins_encode(z_rreform(dst, Z_F0));
4585 ins_pipe(pipe_class_dummy);
4586 %}
4587
4588 // There's a special instr to clear a FP register.
4589 instruct loadConD0(regD dst, immDp0 src) %{
4590 match(Set dst src);
4591 ins_cost(DEFAULT_COST_LOW);
4592 size(4);
4593 format %{ "LZDR $dst,$src\t # clear to zero" %}
4594 opcode(LZDR_ZOPC);
4595 ins_encode(z_rreform(dst, Z_F0));
4596 ins_pipe(pipe_class_dummy);
4597 %}
4598
4599
4600 //----------Store Instructions-------------------------------------------------
4601
4602 // BYTE
4603
4604 // Store Byte
4605 instruct storeB(memory mem, iRegI src) %{
4606 match(Set mem (StoreB mem src));
4607 ins_cost(MEMORY_REF_COST);
4608 size(Z_DISP_SIZE);
4609 format %{ "STC(Y) $src,$mem\t # byte" %}
4610 opcode(STCY_ZOPC, STC_ZOPC);
4611 ins_encode(z_form_rt_mem_opt(src, mem));
4612 ins_pipe(pipe_class_dummy);
4613 %}
4614
4615 // CHAR/SHORT
4616
4617 // Store Char/Short
4618 instruct storeC(memory mem, iRegI src) %{
4619 match(Set mem (StoreC mem src));
4620 ins_cost(MEMORY_REF_COST);
4621 size(Z_DISP_SIZE);
4622 format %{ "STH(Y) $src,$mem\t # short" %}
4623 opcode(STHY_ZOPC, STH_ZOPC);
4624 ins_encode(z_form_rt_mem_opt(src, mem));
4625 ins_pipe(pipe_class_dummy);
4626 %}
4627
4628 // INT
4629
4630 // Store Integer
4631 instruct storeI(memory mem, iRegI src) %{
4632 match(Set mem (StoreI mem src));
4633 ins_cost(MEMORY_REF_COST);
4634 size(Z_DISP_SIZE);
4635 format %{ "ST(Y) $src,$mem\t # int" %}
4636 opcode(STY_ZOPC, ST_ZOPC);
4637 ins_encode(z_form_rt_mem_opt(src, mem));
4638 ins_pipe(pipe_class_dummy);
4639 %}
4640
4641 // LONG
4642
4643 // Store Long
4644 instruct storeL(memory mem, iRegL src) %{
4645 match(Set mem (StoreL mem src));
4646 ins_cost(MEMORY_REF_COST);
4647 size(Z_DISP3_SIZE);
4648 format %{ "STG $src,$mem\t # long" %}
4649 opcode(STG_ZOPC, STG_ZOPC);
4650 ins_encode(z_form_rt_mem_opt(src, mem));
4651 ins_pipe(pipe_class_dummy);
4652 %}
4653
4654 // PTR
4655
4656 // Store Pointer
4657 instruct storeP(memory dst, memoryRegP src) %{
4658 match(Set dst (StoreP dst src));
4659 predicate(n->as_Store()->barrier_data() == 0);
4660 ins_cost(MEMORY_REF_COST);
4661 size(Z_DISP3_SIZE);
4662 format %{ "STG $src,$dst\t # ptr" %}
4663 opcode(STG_ZOPC, STG_ZOPC);
4664 ins_encode(z_form_rt_mem_opt(src, dst));
4665 ins_pipe(pipe_class_dummy);
4666 %}
4667
4668 // FLOAT
4669
4670 // Store Float
4671 instruct storeF(memory mem, regF src) %{
4672 match(Set mem (StoreF mem src));
4673 ins_cost(MEMORY_REF_COST);
4674 size(Z_DISP_SIZE);
4675 format %{ "STE(Y) $src,$mem\t # float" %}
4676 opcode(STEY_ZOPC, STE_ZOPC);
4677 ins_encode(z_form_rt_mem_opt(src, mem));
4678 ins_pipe(pipe_class_dummy);
4679 %}
4680
4681 // DOUBLE
4682
4683 // Store Double
4684 instruct storeD(memory mem, regD src) %{
4685 match(Set mem (StoreD mem src));
4686 ins_cost(MEMORY_REF_COST);
4687 size(Z_DISP_SIZE);
4688 format %{ "STD(Y) $src,$mem\t # double" %}
4689 opcode(STDY_ZOPC, STD_ZOPC);
4690 ins_encode(z_form_rt_mem_opt(src, mem));
4691 ins_pipe(pipe_class_dummy);
4692 %}
4693
4694 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4695
4696 // Should support match rule for PrefetchAllocation.
4697 // Still needed after 8068977 for PrefetchAllocate.
4698 instruct prefetchAlloc(memory mem) %{
4699 match(PrefetchAllocation mem);
4700 predicate(VM_Version::has_Prefetch());
4701 ins_cost(DEFAULT_COST);
4702 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4703 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4704 ins_pipe(pipe_class_dummy);
4705 %}
4706
4707 //----------Memory init instructions------------------------------------------
4708
4709 // Move Immediate to 1-byte memory.
4710 instruct memInitB(memoryRSY mem, immI8 src) %{
4711 match(Set mem (StoreB mem src));
4712 ins_cost(MEMORY_REF_COST);
4713 // TODO: s390 port size(VARIABLE_SIZE);
4714 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4715 ins_encode %{
4716 if (Immediate::is_uimm12((long)$mem$$disp)) {
4717 __ z_mvi($mem$$Address, $src$$constant);
4718 } else {
4719 __ z_mviy($mem$$Address, $src$$constant);
4720 }
4721 %}
4722 ins_pipe(pipe_class_dummy);
4723 %}
4724
4725 // Move Immediate to 2-byte memory.
4726 instruct memInitC(memoryRS mem, immI16 src) %{
4727 match(Set mem (StoreC mem src));
4728 ins_cost(MEMORY_REF_COST);
4729 size(6);
4730 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4731 opcode(MVHHI_ZOPC);
4732 ins_encode(z_silform(mem, src));
4733 ins_pipe(pipe_class_dummy);
4734 %}
4735
4736 // Move Immediate to 4-byte memory.
4737 instruct memInitI(memoryRS mem, immI16 src) %{
4738 match(Set mem (StoreI mem src));
4739 ins_cost(MEMORY_REF_COST);
4740 size(6);
4741 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4742 opcode(MVHI_ZOPC);
4743 ins_encode(z_silform(mem, src));
4744 ins_pipe(pipe_class_dummy);
4745 %}
4746
4747
4748 // Move Immediate to 8-byte memory.
4749 instruct memInitL(memoryRS mem, immL16 src) %{
4750 match(Set mem (StoreL mem src));
4751 ins_cost(MEMORY_REF_COST);
4752 size(6);
4753 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4754 opcode(MVGHI_ZOPC);
4755 ins_encode(z_silform(mem, src));
4756 ins_pipe(pipe_class_dummy);
4757 %}
4758
4759 // Move Immediate to 8-byte memory.
4760 instruct memInitP(memoryRS mem, immP16 src) %{
4761 match(Set mem (StoreP mem src));
4762 predicate(n->as_Store()->barrier_data() == 0);
4763 ins_cost(MEMORY_REF_COST);
4764 size(6);
4765 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4766 opcode(MVGHI_ZOPC);
4767 ins_encode(z_silform(mem, src));
4768 ins_pipe(pipe_class_dummy);
4769 %}
4770
4771
4772 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4773
4774 // See cOop encoding classes for elaborate comment.
4775
4776 // Moved here because it is needed in expand rules for encode.
4777 // Long negation.
4778 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4779 match(Set dst (SubL zero src));
4780 effect(KILL cr);
4781 size(4);
4782 format %{ "NEG $dst, $src\t # long" %}
4783 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4784 ins_pipe(pipe_class_dummy);
4785 %}
4786
4787 // Load Compressed Pointer
4788
4789 // Load narrow oop
4790 instruct loadN(iRegN dst, memory mem) %{
4791 match(Set dst (LoadN mem));
4792 predicate(n->as_Load()->barrier_data() == 0);
4793 ins_cost(MEMORY_REF_COST);
4794 size(Z_DISP3_SIZE);
4795 format %{ "LoadN $dst,$mem\t # (cOop)" %}
4796 opcode(LLGF_ZOPC, LLGF_ZOPC);
4797 ins_encode(z_form_rt_mem_opt(dst, mem));
4798 ins_pipe(pipe_class_dummy);
4799 %}
4800
4801 // Load narrow Klass Pointer
4802 instruct loadNKlass(iRegN dst, memory mem) %{
4803 predicate(!UseCompactObjectHeaders);
4804 match(Set dst (LoadNKlass mem));
4805 ins_cost(MEMORY_REF_COST);
4806 size(Z_DISP3_SIZE);
4807 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
4808 opcode(LLGF_ZOPC, LLGF_ZOPC);
4809 ins_encode(z_form_rt_mem_opt(dst, mem));
4810 ins_pipe(pipe_class_dummy);
4811 %}
4812
4813 instruct loadNKlassCompactHeaders(iRegN dst, memory mem, flagsReg cr) %{
4814 match(Set dst (LoadNKlass mem));
4815 predicate(UseCompactObjectHeaders);
4816 effect(KILL cr);
4817 ins_cost(MEMORY_REF_COST);
4818 format %{ "load_narrow_klass_compact $dst,$mem \t# compressed class ptr" %}
4819 // TODO: size()
4820 ins_encode %{
4821 __ block_comment("load_narrow_klass_compact_c2 {");
4822 __ load_narrow_klass_compact_c2($dst$$Register, $mem$$Address);
4823 __ block_comment("} load_narrow_klass_compact");
4824 %}
4825 ins_pipe(pipe_class_dummy);
4826 %}
4827
4828 // Load constant Compressed Pointer
4829
4830 instruct loadConN(iRegN dst, immN src) %{
4831 match(Set dst src);
4832 ins_cost(DEFAULT_COST);
4833 size(6);
4834 format %{ "loadConN $dst,$src\t # (cOop)" %}
4835 ins_encode %{
4836 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4837 __ relocate(cOop.rspec(), 1);
4838 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4839 %}
4840 ins_pipe(pipe_class_dummy);
4841 %}
4842
4843 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4844 match(Set dst src);
4845 effect(KILL cr);
4846 ins_cost(DEFAULT_COST_LOW);
4847 size(4);
4848 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4849 opcode(XGR_ZOPC);
4850 ins_encode(z_rreform(dst, dst));
4851 ins_pipe(pipe_class_dummy);
4852 %}
4853
4854 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4855 match(Set dst src);
4856 ins_cost(DEFAULT_COST);
4857 size(6);
4858 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4859 ins_encode %{
4860 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4861 __ relocate(NKlass.rspec(), 1);
4862 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4863 %}
4864 ins_pipe(pipe_class_dummy);
4865 %}
4866
4867 // Load and Decode Compressed Pointer
4868 // optimized variants for Unscaled cOops
4869
4870 instruct decodeLoadN(iRegP dst, memory mem) %{
4871 match(Set dst (DecodeN (LoadN mem)));
4872 predicate(false && (CompressedOops::base()==nullptr) && (CompressedOops::shift()==0));
4873 ins_cost(MEMORY_REF_COST);
4874 size(Z_DISP3_SIZE);
4875 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
4876 opcode(LLGF_ZOPC, LLGF_ZOPC);
4877 ins_encode(z_form_rt_mem_opt(dst, mem));
4878 ins_pipe(pipe_class_dummy);
4879 %}
4880
4881 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4882 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4883 predicate(false && (CompressedKlassPointers::base()==nullptr)&&(CompressedKlassPointers::shift()==0));
4884 ins_cost(MEMORY_REF_COST);
4885 size(Z_DISP3_SIZE);
4886 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
4887 opcode(LLGF_ZOPC, LLGF_ZOPC);
4888 ins_encode(z_form_rt_mem_opt(dst, mem));
4889 ins_pipe(pipe_class_dummy);
4890 %}
4891
4892 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4893 match(Set dst (DecodeNKlass src));
4894 ins_cost(3 * DEFAULT_COST);
4895 size(12);
4896 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4897 ins_encode %{
4898 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4899 __ relocate(NKlass.rspec(), 1);
4900 __ load_const($dst$$Register, (Klass*)NKlass.value());
4901 %}
4902 ins_pipe(pipe_class_dummy);
4903 %}
4904
4905 // Decode Compressed Pointer
4906
4907 // General decoder
4908 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4909 match(Set dst (DecodeN src));
4910 effect(KILL cr);
4911 predicate(CompressedOops::base() == nullptr || !ExpandLoadingBaseDecode);
4912 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4913 // TODO: s390 port size(VARIABLE_SIZE);
4914 format %{ "decodeN $dst,$src\t # (decode cOop)" %}
4915 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4916 ins_pipe(pipe_class_dummy);
4917 %}
4918
4919 // General Klass decoder
4920 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4921 match(Set dst (DecodeNKlass src));
4922 effect(KILL cr);
4923 ins_cost(3 * DEFAULT_COST);
4924 format %{ "decode_klass $dst,$src" %}
4925 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4926 ins_pipe(pipe_class_dummy);
4927 %}
4928
4929 // General decoder
4930 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4931 match(Set dst (DecodeN src));
4932 effect(KILL cr);
4933 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4934 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4935 (CompressedOops::base()== nullptr || !ExpandLoadingBaseDecode_NN));
4936 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4937 // TODO: s390 port size(VARIABLE_SIZE);
4938 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
4939 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4940 ins_pipe(pipe_class_dummy);
4941 %}
4942
4943 instruct loadBase(iRegL dst, immL baseImm) %{
4944 effect(DEF dst, USE baseImm);
4945 predicate(false);
4946 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4947 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4948 ins_pipe(pipe_class_dummy);
4949 %}
4950
4951 // Decoder for heapbased mode peeling off loading the base.
4952 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4953 match(Set dst (DecodeN src base));
4954 // Note: Effect TEMP dst was used with the intention to get
4955 // different regs for dst and base, but this has caused ADLC to
4956 // generate wrong code. Oop_decoder generates additional lgr when
4957 // dst==base.
4958 effect(KILL cr);
4959 predicate(false);
4960 // TODO: s390 port size(VARIABLE_SIZE);
4961 format %{ "decodeN $dst = ($src == 0) ? nullptr : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4962 ins_encode %{
4963 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4964 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4965 %}
4966 ins_pipe(pipe_class_dummy);
4967 %}
4968
4969 // Decoder for heapbased mode peeling off loading the base.
4970 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4971 match(Set dst (DecodeN src base));
4972 effect(KILL cr);
4973 predicate(false);
4974 // TODO: s390 port size(VARIABLE_SIZE);
4975 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4976 ins_encode %{
4977 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4978 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4979 %}
4980 ins_pipe(pipe_class_dummy);
4981 %}
4982
4983 // Decoder for heapbased mode peeling off loading the base.
4984 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4985 match(Set dst (DecodeN src));
4986 predicate(CompressedOops::base() != nullptr && ExpandLoadingBaseDecode);
4987 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4988 // TODO: s390 port size(VARIABLE_SIZE);
4989 expand %{
4990 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
4991 iRegL base;
4992 loadBase(base, baseImm);
4993 decodeN_base(dst, src, base, cr);
4994 %}
4995 %}
4996
4997 // Decoder for heapbased mode peeling off loading the base.
4998 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4999 match(Set dst (DecodeN src));
5000 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
5001 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
5002 CompressedOops::base() != nullptr && ExpandLoadingBaseDecode_NN);
5003 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5004 // TODO: s390 port size(VARIABLE_SIZE);
5005 expand %{
5006 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5007 iRegL base;
5008 loadBase(base, baseImm);
5009 decodeN_NN_base(dst, src, base, cr);
5010 %}
5011 %}
5012
5013 // Encode Compressed Pointer
5014
5015 // General encoder
5016 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
5017 match(Set dst (EncodeP src));
5018 effect(KILL cr);
5019 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5020 (CompressedOops::base() == nullptr ||
5021 CompressedOops::base_disjoint() ||
5022 !ExpandLoadingBaseEncode));
5023 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5024 // TODO: s390 port size(VARIABLE_SIZE);
5025 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5026 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5027 ins_pipe(pipe_class_dummy);
5028 %}
5029
5030 // General class encoder
5031 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
5032 match(Set dst (EncodePKlass src));
5033 effect(KILL cr);
5034 format %{ "encode_klass $dst,$src" %}
5035 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
5036 ins_pipe(pipe_class_dummy);
5037 %}
5038
5039 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
5040 match(Set dst (EncodeP src));
5041 effect(KILL cr);
5042 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5043 (CompressedOops::base() == nullptr ||
5044 CompressedOops::base_disjoint() ||
5045 !ExpandLoadingBaseEncode_NN));
5046 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5047 // TODO: s390 port size(VARIABLE_SIZE);
5048 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5049 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5050 ins_pipe(pipe_class_dummy);
5051 %}
5052
5053 // Encoder for heapbased mode peeling off loading the base.
5054 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
5055 match(Set dst (EncodeP src (Binary base dst)));
5056 effect(TEMP_DEF dst);
5057 predicate(false);
5058 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5059 // TODO: s390 port size(VARIABLE_SIZE);
5060 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
5061 ins_encode %{
5062 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
5063 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
5064 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
5065 %}
5066 ins_pipe(pipe_class_dummy);
5067 %}
5068
5069 // Encoder for heapbased mode peeling off loading the base.
5070 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
5071 match(Set dst (EncodeP src base));
5072 effect(USE pow2_offset);
5073 predicate(false);
5074 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5075 // TODO: s390 port size(VARIABLE_SIZE);
5076 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
5077 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
5078 ins_pipe(pipe_class_dummy);
5079 %}
5080
5081 // Encoder for heapbased mode peeling off loading the base.
5082 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5083 match(Set dst (EncodeP src));
5084 effect(KILL cr);
5085 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5086 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
5087 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5088 // TODO: s390 port size(VARIABLE_SIZE);
5089 expand %{
5090 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
5091 immL_0 zero %{ (0) %}
5092 flagsReg ccr;
5093 iRegL base;
5094 iRegL negBase;
5095 loadBase(base, baseImm);
5096 negL_reg_reg(negBase, zero, base, ccr);
5097 encodeP_base(dst, src, negBase);
5098 %}
5099 %}
5100
5101 // Encoder for heapbased mode peeling off loading the base.
5102 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5103 match(Set dst (EncodeP src));
5104 effect(KILL cr);
5105 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5106 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
5107 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5108 // TODO: s390 port size(VARIABLE_SIZE);
5109 expand %{
5110 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5111 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
5112 immL_0 zero %{ 0 %}
5113 flagsReg ccr;
5114 iRegL base;
5115 iRegL negBase;
5116 loadBase(base, baseImm);
5117 negL_reg_reg(negBase, zero, base, ccr);
5118 encodeP_NN_base(dst, src, negBase, pow2_offset);
5119 %}
5120 %}
5121
5122 // Store Compressed Pointer
5123
5124 // Store Compressed Pointer
5125 instruct storeN(memory mem, iRegN_P2N src) %{
5126 match(Set mem (StoreN mem src));
5127 predicate(n->as_Store()->barrier_data() == 0);
5128 ins_cost(MEMORY_REF_COST);
5129 size(Z_DISP_SIZE);
5130 format %{ "ST $src,$mem\t # (cOop)" %}
5131 opcode(STY_ZOPC, ST_ZOPC);
5132 ins_encode(z_form_rt_mem_opt(src, mem));
5133 ins_pipe(pipe_class_dummy);
5134 %}
5135
5136 // Store Compressed Klass pointer
5137 instruct storeNKlass(memory mem, iRegN src) %{
5138 match(Set mem (StoreNKlass mem src));
5139 ins_cost(MEMORY_REF_COST);
5140 size(Z_DISP_SIZE);
5141 format %{ "ST $src,$mem\t # (cKlass)" %}
5142 opcode(STY_ZOPC, ST_ZOPC);
5143 ins_encode(z_form_rt_mem_opt(src, mem));
5144 ins_pipe(pipe_class_dummy);
5145 %}
5146
5147 // Compare Compressed Pointers
5148
5149 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5150 match(Set cr (CmpN src1 src2));
5151 ins_cost(DEFAULT_COST);
5152 size(2);
5153 format %{ "CLR $src1,$src2\t # (cOop)" %}
5154 opcode(CLR_ZOPC);
5155 ins_encode(z_rrform(src1, src2));
5156 ins_pipe(pipe_class_dummy);
5157 %}
5158
5159 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5160 match(Set cr (CmpN src1 src2));
5161 ins_cost(DEFAULT_COST);
5162 size(6);
5163 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
5164 ins_encode %{
5165 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5166 __ relocate(cOop.rspec(), 1);
5167 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5168 %}
5169 ins_pipe(pipe_class_dummy);
5170 %}
5171
5172 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5173 match(Set cr (CmpN src1 src2));
5174 ins_cost(DEFAULT_COST);
5175 size(6);
5176 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
5177 ins_encode %{
5178 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5179 __ relocate(NKlass.rspec(), 1);
5180 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5181 %}
5182 ins_pipe(pipe_class_dummy);
5183 %}
5184
5185 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5186 match(Set cr (CmpN src1 src2));
5187 ins_cost(DEFAULT_COST);
5188 size(2);
5189 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
5190 opcode(LTR_ZOPC);
5191 ins_encode(z_rrform(src1, src1));
5192 ins_pipe(pipe_class_dummy);
5193 %}
5194
5195
5196 //----------MemBar Instructions-----------------------------------------------
5197
5198 // Memory barrier flavors
5199
5200 instruct membar_acquire() %{
5201 match(MemBarAcquire);
5202 match(LoadFence);
5203 ins_cost(4*MEMORY_REF_COST);
5204 size(0);
5205 format %{ "MEMBAR-acquire" %}
5206 ins_encode %{ __ z_acquire(); %}
5207 ins_pipe(pipe_class_dummy);
5208 %}
5209
5210 instruct membar_acquire_lock() %{
5211 match(MemBarAcquireLock);
5212 ins_cost(0);
5213 size(0);
5214 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5215 ins_encode(/*empty*/);
5216 ins_pipe(pipe_class_dummy);
5217 %}
5218
5219 instruct membar_release() %{
5220 match(MemBarRelease);
5221 match(StoreFence);
5222 ins_cost(4 * MEMORY_REF_COST);
5223 size(0);
5224 format %{ "MEMBAR-release" %}
5225 ins_encode %{ __ z_release(); %}
5226 ins_pipe(pipe_class_dummy);
5227 %}
5228
5229 instruct membar_release_lock() %{
5230 match(MemBarReleaseLock);
5231 ins_cost(0);
5232 size(0);
5233 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5234 ins_encode(/*empty*/);
5235 ins_pipe(pipe_class_dummy);
5236 %}
5237
5238 instruct membar_storeload() %{
5239 match(MemBarStoreLoad);
5240 ins_cost(4 * MEMORY_REF_COST);
5241 size(2);
5242 format %{ "MEMBAR-storeload" %}
5243 ins_encode %{ __ z_fence(); %}
5244 ins_pipe(pipe_class_dummy);
5245 %}
5246
5247 instruct membar_volatile() %{
5248 match(MemBarVolatile);
5249 ins_cost(4 * MEMORY_REF_COST);
5250 size(2);
5251 format %{ "MEMBAR-volatile" %}
5252 ins_encode %{ __ z_fence(); %}
5253 ins_pipe(pipe_class_dummy);
5254 %}
5255
5256 instruct unnecessary_membar_volatile() %{
5257 match(MemBarVolatile);
5258 predicate(Matcher::post_store_load_barrier(n));
5259 ins_cost(0);
5260 size(0);
5261 format %{ "# MEMBAR-volatile (empty)" %}
5262 ins_encode(/*empty*/);
5263 ins_pipe(pipe_class_dummy);
5264 %}
5265
5266 instruct membar_full() %{
5267 match(MemBarFull);
5268 ins_cost(4 * MEMORY_REF_COST);
5269 size(2);
5270 format %{ "MEMBAR-full" %}
5271 ins_encode %{ __ z_fence(); %}
5272 ins_pipe(pipe_class_dummy);
5273 %}
5274
5275 instruct membar_CPUOrder() %{
5276 match(MemBarCPUOrder);
5277 ins_cost(0);
5278 // TODO: s390 port size(FIXED_SIZE);
5279 format %{ "MEMBAR-CPUOrder (empty)" %}
5280 ins_encode(/*empty*/);
5281 ins_pipe(pipe_class_dummy);
5282 %}
5283
5284 instruct membar_storestore() %{
5285 match(MemBarStoreStore);
5286 match(StoreStoreFence);
5287 ins_cost(0);
5288 size(0);
5289 format %{ "MEMBAR-storestore (empty)" %}
5290 ins_encode();
5291 ins_pipe(pipe_class_dummy);
5292 %}
5293
5294
5295 //----------Register Move Instructions-----------------------------------------
5296
5297 // Cast Long to Pointer for unsafe natives.
5298 instruct castX2P(iRegP dst, iRegL src) %{
5299 match(Set dst (CastX2P src));
5300 // TODO: s390 port size(VARIABLE_SIZE);
5301 format %{ "LGR $dst,$src\t # CastX2P" %}
5302 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5303 ins_pipe(pipe_class_dummy);
5304 %}
5305
5306 // Cast Pointer to Long for unsafe natives.
5307 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5308 match(Set dst (CastP2X src));
5309 // TODO: s390 port size(VARIABLE_SIZE);
5310 format %{ "LGR $dst,$src\t # CastP2X" %}
5311 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5312 ins_pipe(pipe_class_dummy);
5313 %}
5314
5315 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5316 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5317 match(Set stkSlot src); // chain rule
5318 ins_cost(MEMORY_REF_COST);
5319 // TODO: s390 port size(FIXED_SIZE);
5320 format %{ " STD $src,$stkSlot\t # stk" %}
5321 opcode(STD_ZOPC);
5322 ins_encode(z_form_rt_mem(src, stkSlot));
5323 ins_pipe(pipe_class_dummy);
5324 %}
5325
5326 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5327 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5328 match(Set stkSlot src); // chain rule
5329 ins_cost(MEMORY_REF_COST);
5330 // TODO: s390 port size(FIXED_SIZE);
5331 format %{ "STE $src,$stkSlot\t # stk" %}
5332 opcode(STE_ZOPC);
5333 ins_encode(z_form_rt_mem(src, stkSlot));
5334 ins_pipe(pipe_class_dummy);
5335 %}
5336
5337 //----------Conditional Move---------------------------------------------------
5338
5339 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5340 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5341 ins_cost(DEFAULT_COST + BRANCH_COST);
5342 // TODO: s390 port size(VARIABLE_SIZE);
5343 format %{ "CMoveN,$cmp $dst,$src" %}
5344 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5345 ins_pipe(pipe_class_dummy);
5346 %}
5347
5348 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5349 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5350 ins_cost(DEFAULT_COST + BRANCH_COST);
5351 // TODO: s390 port size(VARIABLE_SIZE);
5352 format %{ "CMoveN,$cmp $dst,$src" %}
5353 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5354 ins_pipe(pipe_class_dummy);
5355 %}
5356
5357 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5358 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5359 ins_cost(DEFAULT_COST + BRANCH_COST);
5360 // TODO: s390 port size(VARIABLE_SIZE);
5361 format %{ "CMoveI,$cmp $dst,$src" %}
5362 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5363 ins_pipe(pipe_class_dummy);
5364 %}
5365
5366 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5367 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5368 ins_cost(DEFAULT_COST + BRANCH_COST);
5369 // TODO: s390 port size(VARIABLE_SIZE);
5370 format %{ "CMoveI,$cmp $dst,$src" %}
5371 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5372 ins_pipe(pipe_class_dummy);
5373 %}
5374
5375 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5376 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5377 ins_cost(DEFAULT_COST + BRANCH_COST);
5378 // TODO: s390 port size(VARIABLE_SIZE);
5379 format %{ "CMoveP,$cmp $dst,$src" %}
5380 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5381 ins_pipe(pipe_class_dummy);
5382 %}
5383
5384 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5385 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5386 ins_cost(DEFAULT_COST + BRANCH_COST);
5387 // TODO: s390 port size(VARIABLE_SIZE);
5388 format %{ "CMoveP,$cmp $dst,$src" %}
5389 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5390 ins_pipe(pipe_class_dummy);
5391 %}
5392
5393 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5394 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5395 ins_cost(DEFAULT_COST + BRANCH_COST);
5396 // TODO: s390 port size(VARIABLE_SIZE);
5397 format %{ "CMoveF,$cmp $dst,$src" %}
5398 ins_encode %{
5399 // Don't emit code if operands are identical (same register).
5400 if ($dst$$FloatRegister != $src$$FloatRegister) {
5401 Label done;
5402 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5403 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5404 __ bind(done);
5405 }
5406 %}
5407 ins_pipe(pipe_class_dummy);
5408 %}
5409
5410 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5411 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5412 ins_cost(DEFAULT_COST + BRANCH_COST);
5413 // TODO: s390 port size(VARIABLE_SIZE);
5414 format %{ "CMoveD,$cmp $dst,$src" %}
5415 ins_encode %{
5416 // Don't emit code if operands are identical (same register).
5417 if ($dst$$FloatRegister != $src$$FloatRegister) {
5418 Label done;
5419 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5420 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5421 __ bind(done);
5422 }
5423 %}
5424 ins_pipe(pipe_class_dummy);
5425 %}
5426
5427 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5428 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5429 ins_cost(DEFAULT_COST + BRANCH_COST);
5430 // TODO: s390 port size(VARIABLE_SIZE);
5431 format %{ "CMoveL,$cmp $dst,$src" %}
5432 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5433 ins_pipe(pipe_class_dummy);
5434 %}
5435
5436 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5437 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5438 ins_cost(DEFAULT_COST + BRANCH_COST);
5439 // TODO: s390 port size(VARIABLE_SIZE);
5440 format %{ "CMoveL,$cmp $dst,$src" %}
5441 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5442 ins_pipe(pipe_class_dummy);
5443 %}
5444
5445 //----------OS and Locking Instructions----------------------------------------
5446
5447 // This name is KNOWN by the ADLC and cannot be changed.
5448 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5449 // for this guy.
5450 instruct tlsLoadP(threadRegP dst) %{
5451 match(Set dst (ThreadLocal));
5452 ins_cost(0);
5453 size(0);
5454 ins_should_rematerialize(true);
5455 format %{ "# $dst=ThreadLocal" %}
5456 ins_encode(/* empty */);
5457 ins_pipe(pipe_class_dummy);
5458 %}
5459
5460 instruct checkCastPP(iRegP dst) %{
5461 match(Set dst (CheckCastPP dst));
5462 size(0);
5463 format %{ "# checkcastPP of $dst" %}
5464 ins_encode(/*empty*/);
5465 ins_pipe(pipe_class_dummy);
5466 %}
5467
5468 instruct castPP(iRegP dst) %{
5469 match(Set dst (CastPP dst));
5470 size(0);
5471 format %{ "# castPP of $dst" %}
5472 ins_encode(/*empty*/);
5473 ins_pipe(pipe_class_dummy);
5474 %}
5475
5476 instruct castII(iRegI dst) %{
5477 match(Set dst (CastII dst));
5478 size(0);
5479 format %{ "# castII of $dst" %}
5480 ins_encode(/*empty*/);
5481 ins_pipe(pipe_class_dummy);
5482 %}
5483
5484 instruct castLL(iRegL dst) %{
5485 match(Set dst (CastLL dst));
5486 size(0);
5487 format %{ "# castLL of $dst" %}
5488 ins_encode(/*empty*/);
5489 ins_pipe(pipe_class_dummy);
5490 %}
5491
5492 instruct castFF(regF dst) %{
5493 match(Set dst (CastFF dst));
5494 size(0);
5495 format %{ "# castFF of $dst" %}
5496 ins_encode(/*empty*/);
5497 ins_pipe(pipe_class_dummy);
5498 %}
5499
5500 instruct castDD(regD dst) %{
5501 match(Set dst (CastDD dst));
5502 size(0);
5503 format %{ "# castDD of $dst" %}
5504 ins_encode(/*empty*/);
5505 ins_pipe(pipe_class_dummy);
5506 %}
5507
5508 instruct castVV(iRegL dst) %{
5509 match(Set dst (CastVV dst));
5510 size(0);
5511 format %{ "# castVV of $dst" %}
5512 ins_encode(/*empty*/);
5513 ins_pipe(pipe_class_dummy);
5514 %}
5515
5516 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5517
5518 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5519 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5520 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5521 size(16);
5522 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5523 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5524 z_enc_cctobool(res));
5525 ins_pipe(pipe_class_dummy);
5526 %}
5527
5528 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5529 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5530 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5531 size(18);
5532 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5533 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5534 z_enc_cctobool(res));
5535 ins_pipe(pipe_class_dummy);
5536 %}
5537
5538 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5539 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5540 predicate(n->as_LoadStore()->barrier_data() == 0);
5541 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5542 size(18);
5543 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5544 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5545 z_enc_cctobool(res));
5546 ins_pipe(pipe_class_dummy);
5547 %}
5548
5549 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5550 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5551 predicate(n->as_LoadStore()->barrier_data() == 0);
5552 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5553 size(16);
5554 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5555 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5556 z_enc_cctobool(res));
5557 ins_pipe(pipe_class_dummy);
5558 %}
5559
5560 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5561
5562 // Exploit: direct memory arithmetic
5563 // Prereqs: - instructions available
5564 // - instructions guarantee atomicity
5565 // - immediate operand to be added
5566 // - immediate operand is small enough (8-bit signed).
5567 // - result of instruction is not used
5568 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5569 match(Set dummy (GetAndAddI mem src));
5570 effect(KILL cr);
5571 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5572 ins_cost(MEMORY_REF_COST);
5573 size(6);
5574 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5575 opcode(ASI_ZOPC);
5576 ins_encode(z_siyform(mem, src));
5577 ins_pipe(pipe_class_dummy);
5578 %}
5579
5580 // Fallback: direct memory arithmetic not available
5581 // Disadvantages: - CS-Loop required, very expensive.
5582 // - more code generated (26 to xx bytes vs. 6 bytes)
5583 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5584 match(Set dst (GetAndAddI mem src));
5585 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5586 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5587 format %{ "BEGIN ATOMIC {\n\t"
5588 " LGF $dst,[$mem]\n\t"
5589 " AHIK $tmp,$dst,$src\n\t"
5590 " CSY $dst,$tmp,$mem\n\t"
5591 " retry if failed\n\t"
5592 "} END ATOMIC"
5593 %}
5594 ins_encode %{
5595 Register Rdst = $dst$$Register;
5596 Register Rtmp = $tmp$$Register;
5597 int Isrc = $src$$constant;
5598 Label retry;
5599
5600 // Iterate until update with incremented value succeeds.
5601 __ z_lgf(Rdst, $mem$$Address); // current contents
5602 __ bind(retry);
5603 // Calculate incremented value.
5604 if (VM_Version::has_DistinctOpnds()) {
5605 __ z_ahik(Rtmp, Rdst, Isrc);
5606 } else {
5607 __ z_lr(Rtmp, Rdst);
5608 __ z_ahi(Rtmp, Isrc);
5609 }
5610 // Swap into memory location.
5611 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5612 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5613 %}
5614 ins_pipe(pipe_class_dummy);
5615 %}
5616
5617 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5618 match(Set dst (GetAndAddI mem src));
5619 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5620 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5621 format %{ "BEGIN ATOMIC {\n\t"
5622 " LGF $dst,[$mem]\n\t"
5623 " LGR $tmp,$dst\n\t"
5624 " AFI $tmp,$src\n\t"
5625 " CSY $dst,$tmp,$mem\n\t"
5626 " retry if failed\n\t"
5627 "} END ATOMIC"
5628 %}
5629 ins_encode %{
5630 Register Rdst = $dst$$Register;
5631 Register Rtmp = $tmp$$Register;
5632 int Isrc = $src$$constant;
5633 Label retry;
5634
5635 // Iterate until update with incremented value succeeds.
5636 __ z_lgf(Rdst, $mem$$Address); // current contents
5637 __ bind(retry);
5638 // Calculate incremented value.
5639 __ z_lr(Rtmp, Rdst);
5640 __ z_afi(Rtmp, Isrc);
5641 // Swap into memory location.
5642 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5643 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5644 %}
5645 ins_pipe(pipe_class_dummy);
5646 %}
5647
5648 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5649 match(Set dst (GetAndAddI mem src));
5650 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5651 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5652 format %{ "BEGIN ATOMIC {\n\t"
5653 " LGF $dst,[$mem]\n\t"
5654 " ARK $tmp,$dst,$src\n\t"
5655 " CSY $dst,$tmp,$mem\n\t"
5656 " retry if failed\n\t"
5657 "} END ATOMIC"
5658 %}
5659 ins_encode %{
5660 Register Rsrc = $src$$Register;
5661 Register Rdst = $dst$$Register;
5662 Register Rtmp = $tmp$$Register;
5663 Label retry;
5664
5665 // Iterate until update with incremented value succeeds.
5666 __ z_lgf(Rdst, $mem$$Address); // current contents
5667 __ bind(retry);
5668 // Calculate incremented value.
5669 if (VM_Version::has_DistinctOpnds()) {
5670 __ z_ark(Rtmp, Rdst, Rsrc);
5671 } else {
5672 __ z_lr(Rtmp, Rdst);
5673 __ z_ar(Rtmp, Rsrc);
5674 }
5675 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5676 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5677 %}
5678 ins_pipe(pipe_class_dummy);
5679 %}
5680
5681
5682 // Exploit: direct memory arithmetic
5683 // Prereqs: - instructions available
5684 // - instructions guarantee atomicity
5685 // - immediate operand to be added
5686 // - immediate operand is small enough (8-bit signed).
5687 // - result of instruction is not used
5688 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5689 match(Set dummy (GetAndAddL mem src));
5690 effect(KILL cr);
5691 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5692 ins_cost(MEMORY_REF_COST);
5693 size(6);
5694 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5695 opcode(AGSI_ZOPC);
5696 ins_encode(z_siyform(mem, src));
5697 ins_pipe(pipe_class_dummy);
5698 %}
5699
5700 // Fallback: direct memory arithmetic not available
5701 // Disadvantages: - CS-Loop required, very expensive.
5702 // - more code generated (26 to xx bytes vs. 6 bytes)
5703 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5704 match(Set dst (GetAndAddL mem src));
5705 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5706 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5707 format %{ "BEGIN ATOMIC {\n\t"
5708 " LG $dst,[$mem]\n\t"
5709 " AGHIK $tmp,$dst,$src\n\t"
5710 " CSG $dst,$tmp,$mem\n\t"
5711 " retry if failed\n\t"
5712 "} END ATOMIC"
5713 %}
5714 ins_encode %{
5715 Register Rdst = $dst$$Register;
5716 Register Rtmp = $tmp$$Register;
5717 int Isrc = $src$$constant;
5718 Label retry;
5719
5720 // Iterate until update with incremented value succeeds.
5721 __ z_lg(Rdst, $mem$$Address); // current contents
5722 __ bind(retry);
5723 // Calculate incremented value.
5724 if (VM_Version::has_DistinctOpnds()) {
5725 __ z_aghik(Rtmp, Rdst, Isrc);
5726 } else {
5727 __ z_lgr(Rtmp, Rdst);
5728 __ z_aghi(Rtmp, Isrc);
5729 }
5730 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5731 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5732 %}
5733 ins_pipe(pipe_class_dummy);
5734 %}
5735
5736 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5737 match(Set dst (GetAndAddL mem src));
5738 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5739 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5740 format %{ "BEGIN ATOMIC {\n\t"
5741 " LG $dst,[$mem]\n\t"
5742 " LGR $tmp,$dst\n\t"
5743 " AGFI $tmp,$src\n\t"
5744 " CSG $dst,$tmp,$mem\n\t"
5745 " retry if failed\n\t"
5746 "} END ATOMIC"
5747 %}
5748 ins_encode %{
5749 Register Rdst = $dst$$Register;
5750 Register Rtmp = $tmp$$Register;
5751 int Isrc = $src$$constant;
5752 Label retry;
5753
5754 // Iterate until update with incremented value succeeds.
5755 __ z_lg(Rdst, $mem$$Address); // current contents
5756 __ bind(retry);
5757 // Calculate incremented value.
5758 __ z_lgr(Rtmp, Rdst);
5759 __ z_agfi(Rtmp, Isrc);
5760 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5761 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5762 %}
5763 ins_pipe(pipe_class_dummy);
5764 %}
5765
5766 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5767 match(Set dst (GetAndAddL mem src));
5768 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5769 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5770 format %{ "BEGIN ATOMIC {\n\t"
5771 " LG $dst,[$mem]\n\t"
5772 " AGRK $tmp,$dst,$src\n\t"
5773 " CSG $dst,$tmp,$mem\n\t"
5774 " retry if failed\n\t"
5775 "} END ATOMIC"
5776 %}
5777 ins_encode %{
5778 Register Rsrc = $src$$Register;
5779 Register Rdst = $dst$$Register;
5780 Register Rtmp = $tmp$$Register;
5781 Label retry;
5782
5783 // Iterate until update with incremented value succeeds.
5784 __ z_lg(Rdst, $mem$$Address); // current contents
5785 __ bind(retry);
5786 // Calculate incremented value.
5787 if (VM_Version::has_DistinctOpnds()) {
5788 __ z_agrk(Rtmp, Rdst, Rsrc);
5789 } else {
5790 __ z_lgr(Rtmp, Rdst);
5791 __ z_agr(Rtmp, Rsrc);
5792 }
5793 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5794 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5795 %}
5796 ins_pipe(pipe_class_dummy);
5797 %}
5798
5799 // Increment value in memory, save old value in dst.
5800 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5801 match(Set dst (GetAndAddI mem src));
5802 predicate(VM_Version::has_LoadAndALUAtomicV1());
5803 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5804 size(6);
5805 format %{ "LAA $dst,$src,[$mem]" %}
5806 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5807 ins_pipe(pipe_class_dummy);
5808 %}
5809
5810 // Increment value in memory, save old value in dst.
5811 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5812 match(Set dst (GetAndAddL mem src));
5813 predicate(VM_Version::has_LoadAndALUAtomicV1());
5814 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5815 size(6);
5816 format %{ "LAAG $dst,$src,[$mem]" %}
5817 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5818 ins_pipe(pipe_class_dummy);
5819 %}
5820
5821
5822 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5823 match(Set dst (GetAndSetI mem dst));
5824 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5825 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5826 ins_encode(z_enc_SwapI(mem, dst, tmp));
5827 ins_pipe(pipe_class_dummy);
5828 %}
5829
5830 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5831 match(Set dst (GetAndSetL mem dst));
5832 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5833 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5834 ins_encode(z_enc_SwapL(mem, dst, tmp));
5835 ins_pipe(pipe_class_dummy);
5836 %}
5837
5838 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5839 predicate(n->as_LoadStore()->barrier_data() == 0);
5840 match(Set dst (GetAndSetN mem dst));
5841 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5842 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5843 ins_encode(z_enc_SwapI(mem, dst, tmp));
5844 ins_pipe(pipe_class_dummy);
5845 %}
5846
5847 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5848 match(Set dst (GetAndSetP mem dst));
5849 predicate(n->as_LoadStore()->barrier_data() == 0);
5850 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5851 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5852 ins_encode(z_enc_SwapL(mem, dst, tmp));
5853 ins_pipe(pipe_class_dummy);
5854 %}
5855
5856
5857 //----------Arithmetic Instructions--------------------------------------------
5858
5859 // The rules are sorted by right operand type and operand length. Please keep
5860 // it that way.
5861 // Left operand type is always reg. Left operand len is I, L, P
5862 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5863 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5864
5865 // ADD
5866
5867 // REG = REG + REG
5868
5869 // Register Addition
5870 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5871 match(Set dst (AddI dst src));
5872 effect(KILL cr);
5873 // TODO: s390 port size(FIXED_SIZE);
5874 format %{ "AR $dst,$src\t # int CISC ALU" %}
5875 opcode(AR_ZOPC);
5876 ins_encode(z_rrform(dst, src));
5877 ins_pipe(pipe_class_dummy);
5878 %}
5879
5880 // Avoid use of LA(Y) for general ALU operation.
5881 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5882 match(Set dst (AddI src1 src2));
5883 effect(KILL cr);
5884 predicate(VM_Version::has_DistinctOpnds());
5885 ins_cost(DEFAULT_COST);
5886 size(4);
5887 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5888 opcode(ARK_ZOPC);
5889 ins_encode(z_rrfform(dst, src1, src2));
5890 ins_pipe(pipe_class_dummy);
5891 %}
5892
5893 // REG = REG + IMM
5894
5895 // Avoid use of LA(Y) for general ALU operation.
5896 // Immediate Addition
5897 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5898 match(Set dst (AddI dst con));
5899 effect(KILL cr);
5900 ins_cost(DEFAULT_COST);
5901 // TODO: s390 port size(FIXED_SIZE);
5902 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5903 opcode(AHI_ZOPC);
5904 ins_encode(z_riform_signed(dst, con));
5905 ins_pipe(pipe_class_dummy);
5906 %}
5907
5908 // Avoid use of LA(Y) for general ALU operation.
5909 // Immediate Addition
5910 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5911 match(Set dst (AddI src con));
5912 effect(KILL cr);
5913 predicate( VM_Version::has_DistinctOpnds());
5914 ins_cost(DEFAULT_COST);
5915 // TODO: s390 port size(FIXED_SIZE);
5916 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5917 opcode(AHIK_ZOPC);
5918 ins_encode(z_rieform_d(dst, src, con));
5919 ins_pipe(pipe_class_dummy);
5920 %}
5921
5922 // Immediate Addition
5923 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5924 match(Set dst (AddI dst src));
5925 effect(KILL cr);
5926 ins_cost(DEFAULT_COST_HIGH);
5927 size(6);
5928 format %{ "AFI $dst,$src" %}
5929 opcode(AFI_ZOPC);
5930 ins_encode(z_rilform_signed(dst, src));
5931 ins_pipe(pipe_class_dummy);
5932 %}
5933
5934 // Immediate Addition
5935 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5936 match(Set dst (AddI src con));
5937 predicate(PreferLAoverADD);
5938 ins_cost(DEFAULT_COST_LOW);
5939 size(4);
5940 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
5941 opcode(LA_ZOPC);
5942 ins_encode(z_rxform_imm_reg(dst, con, src));
5943 ins_pipe(pipe_class_dummy);
5944 %}
5945
5946 // Immediate Addition
5947 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5948 match(Set dst (AddI src con));
5949 predicate(PreferLAoverADD);
5950 ins_cost(DEFAULT_COST);
5951 size(6);
5952 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
5953 opcode(LAY_ZOPC);
5954 ins_encode(z_rxyform_imm_reg(dst, con, src));
5955 ins_pipe(pipe_class_dummy);
5956 %}
5957
5958 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5959 match(Set dst (AddI (AddI src1 src2) con));
5960 predicate( PreferLAoverADD);
5961 ins_cost(DEFAULT_COST_LOW);
5962 size(4);
5963 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5964 opcode(LA_ZOPC);
5965 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5966 ins_pipe(pipe_class_dummy);
5967 %}
5968
5969 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5970 match(Set dst (AddI (AddI src1 src2) con));
5971 predicate(PreferLAoverADD);
5972 ins_cost(DEFAULT_COST);
5973 size(6);
5974 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5975 opcode(LAY_ZOPC);
5976 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5977 ins_pipe(pipe_class_dummy);
5978 %}
5979
5980 // REG = REG + MEM
5981
5982 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5983 match(Set dst (AddI dst (LoadI src)));
5984 effect(KILL cr);
5985 ins_cost(MEMORY_REF_COST);
5986 // TODO: s390 port size(VARIABLE_SIZE);
5987 format %{ "A(Y) $dst, $src\t # int" %}
5988 opcode(AY_ZOPC, A_ZOPC);
5989 ins_encode(z_form_rt_mem_opt(dst, src));
5990 ins_pipe(pipe_class_dummy);
5991 %}
5992
5993 // MEM = MEM + IMM
5994
5995 // Add Immediate to 4-byte memory operand and result
5996 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5997 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5998 effect(KILL cr);
5999 predicate(VM_Version::has_MemWithImmALUOps());
6000 ins_cost(MEMORY_REF_COST);
6001 size(6);
6002 format %{ "ASI $mem,$src\t # direct mem add 4" %}
6003 opcode(ASI_ZOPC);
6004 ins_encode(z_siyform(mem, src));
6005 ins_pipe(pipe_class_dummy);
6006 %}
6007
6008
6009 //
6010
6011 // REG = REG + REG
6012
6013 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
6014 match(Set dst (AddL dst (ConvI2L src)));
6015 effect(KILL cr);
6016 size(4);
6017 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
6018 opcode(AGFR_ZOPC);
6019 ins_encode(z_rreform(dst, src));
6020 ins_pipe(pipe_class_dummy);
6021 %}
6022
6023 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6024 match(Set dst (AddL dst src));
6025 effect(KILL cr);
6026 // TODO: s390 port size(FIXED_SIZE);
6027 format %{ "AGR $dst, $src\t # long CISC ALU" %}
6028 opcode(AGR_ZOPC);
6029 ins_encode(z_rreform(dst, src));
6030 ins_pipe(pipe_class_dummy);
6031 %}
6032
6033 // Avoid use of LA(Y) for general ALU operation.
6034 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6035 match(Set dst (AddL src1 src2));
6036 effect(KILL cr);
6037 predicate(VM_Version::has_DistinctOpnds());
6038 ins_cost(DEFAULT_COST);
6039 size(4);
6040 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
6041 opcode(AGRK_ZOPC);
6042 ins_encode(z_rrfform(dst, src1, src2));
6043 ins_pipe(pipe_class_dummy);
6044 %}
6045
6046 // REG = REG + IMM
6047
6048 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
6049 match(Set dst (AddL src con));
6050 predicate( PreferLAoverADD);
6051 ins_cost(DEFAULT_COST_LOW);
6052 size(4);
6053 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
6054 opcode(LA_ZOPC);
6055 ins_encode(z_rxform_imm_reg(dst, con, src));
6056 ins_pipe(pipe_class_dummy);
6057 %}
6058
6059 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
6060 match(Set dst (AddL src con));
6061 predicate(PreferLAoverADD);
6062 ins_cost(DEFAULT_COST);
6063 size(6);
6064 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
6065 opcode(LAY_ZOPC);
6066 ins_encode(z_rxyform_imm_reg(dst, con, src));
6067 ins_pipe(pipe_class_dummy);
6068 %}
6069
6070 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
6071 match(Set dst (AddL dst con));
6072 effect(KILL cr);
6073 ins_cost(DEFAULT_COST_HIGH);
6074 size(6);
6075 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
6076 opcode(AGFI_ZOPC);
6077 ins_encode(z_rilform_signed(dst, con));
6078 ins_pipe(pipe_class_dummy);
6079 %}
6080
6081 // Avoid use of LA(Y) for general ALU operation.
6082 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6083 match(Set dst (AddL dst con));
6084 effect(KILL cr);
6085 ins_cost(DEFAULT_COST);
6086 // TODO: s390 port size(FIXED_SIZE);
6087 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6088 opcode(AGHI_ZOPC);
6089 ins_encode(z_riform_signed(dst, con));
6090 ins_pipe(pipe_class_dummy);
6091 %}
6092
6093 // Avoid use of LA(Y) for general ALU operation.
6094 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6095 match(Set dst (AddL src con));
6096 effect(KILL cr);
6097 predicate( VM_Version::has_DistinctOpnds());
6098 ins_cost(DEFAULT_COST);
6099 size(6);
6100 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6101 opcode(AGHIK_ZOPC);
6102 ins_encode(z_rieform_d(dst, src, con));
6103 ins_pipe(pipe_class_dummy);
6104 %}
6105
6106 // REG = REG + MEM
6107
6108 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6109 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6110 effect(KILL cr);
6111 ins_cost(MEMORY_REF_COST);
6112 size(Z_DISP3_SIZE);
6113 format %{ "AGF $dst, $src\t # long/int" %}
6114 opcode(AGF_ZOPC, AGF_ZOPC);
6115 ins_encode(z_form_rt_mem_opt(dst, src));
6116 ins_pipe(pipe_class_dummy);
6117 %}
6118
6119 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6120 match(Set dst (AddL dst (LoadL src)));
6121 effect(KILL cr);
6122 ins_cost(MEMORY_REF_COST);
6123 size(Z_DISP3_SIZE);
6124 format %{ "AG $dst, $src\t # long" %}
6125 opcode(AG_ZOPC, AG_ZOPC);
6126 ins_encode(z_form_rt_mem_opt(dst, src));
6127 ins_pipe(pipe_class_dummy);
6128 %}
6129
6130 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6131 match(Set dst (AddL (AddL src1 src2) con));
6132 predicate( PreferLAoverADD);
6133 ins_cost(DEFAULT_COST_LOW);
6134 size(4);
6135 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6136 opcode(LA_ZOPC);
6137 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6138 ins_pipe(pipe_class_dummy);
6139 %}
6140
6141 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6142 match(Set dst (AddL (AddL src1 src2) con));
6143 predicate(PreferLAoverADD);
6144 ins_cost(DEFAULT_COST);
6145 size(6);
6146 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6147 opcode(LAY_ZOPC);
6148 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6149 ins_pipe(pipe_class_dummy);
6150 %}
6151
6152 // MEM = MEM + IMM
6153
6154 // Add Immediate to 8-byte memory operand and result.
6155 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6156 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6157 effect(KILL cr);
6158 predicate(VM_Version::has_MemWithImmALUOps());
6159 ins_cost(MEMORY_REF_COST);
6160 size(6);
6161 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6162 opcode(AGSI_ZOPC);
6163 ins_encode(z_siyform(mem, src));
6164 ins_pipe(pipe_class_dummy);
6165 %}
6166
6167
6168 // REG = REG + REG
6169
6170 // Ptr Addition
6171 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6172 match(Set dst (AddP src1 src2));
6173 predicate( PreferLAoverADD);
6174 ins_cost(DEFAULT_COST);
6175 size(4);
6176 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6177 opcode(LA_ZOPC);
6178 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6179 ins_pipe(pipe_class_dummy);
6180 %}
6181
6182 // Ptr Addition
6183 // Avoid use of LA(Y) for general ALU operation.
6184 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6185 match(Set dst (AddP dst src));
6186 effect(KILL cr);
6187 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6188 ins_cost(DEFAULT_COST);
6189 // TODO: s390 port size(FIXED_SIZE);
6190 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6191 opcode(ALGR_ZOPC);
6192 ins_encode(z_rreform(dst, src));
6193 ins_pipe(pipe_class_dummy);
6194 %}
6195
6196 // Ptr Addition
6197 // Avoid use of LA(Y) for general ALU operation.
6198 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6199 match(Set dst (AddP src1 src2));
6200 effect(KILL cr);
6201 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6202 ins_cost(DEFAULT_COST);
6203 // TODO: s390 port size(FIXED_SIZE);
6204 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6205 opcode(ALGRK_ZOPC);
6206 ins_encode(z_rrfform(dst, src1, src2));
6207 ins_pipe(pipe_class_dummy);
6208 %}
6209
6210 // REG = REG + IMM
6211
6212 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6213 match(Set dst (AddP src con));
6214 predicate( PreferLAoverADD);
6215 ins_cost(DEFAULT_COST_LOW);
6216 size(4);
6217 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6218 opcode(LA_ZOPC);
6219 ins_encode(z_rxform_imm_reg(dst, con, src));
6220 ins_pipe(pipe_class_dummy);
6221 %}
6222
6223 // Avoid use of LA(Y) for general ALU operation.
6224 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6225 match(Set dst (AddP dst src));
6226 effect(KILL cr);
6227 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6228 ins_cost(DEFAULT_COST);
6229 // TODO: s390 port size(FIXED_SIZE);
6230 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6231 opcode(AGHI_ZOPC);
6232 ins_encode(z_riform_signed(dst, src));
6233 ins_pipe(pipe_class_dummy);
6234 %}
6235
6236 // Avoid use of LA(Y) for general ALU operation.
6237 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6238 match(Set dst (AddP src con));
6239 effect(KILL cr);
6240 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6241 ins_cost(DEFAULT_COST);
6242 // TODO: s390 port size(FIXED_SIZE);
6243 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6244 opcode(ALGHSIK_ZOPC);
6245 ins_encode(z_rieform_d(dst, src, con));
6246 ins_pipe(pipe_class_dummy);
6247 %}
6248
6249 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6250 match(Set dst (AddP src con));
6251 predicate(PreferLAoverADD);
6252 ins_cost(DEFAULT_COST);
6253 size(6);
6254 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6255 opcode(LAY_ZOPC);
6256 ins_encode(z_rxyform_imm_reg(dst, con, src));
6257 ins_pipe(pipe_class_dummy);
6258 %}
6259
6260 // Pointer Immediate Addition
6261 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6262 match(Set dst (AddP dst src));
6263 effect(KILL cr);
6264 ins_cost(DEFAULT_COST_HIGH);
6265 // TODO: s390 port size(FIXED_SIZE);
6266 format %{ "AGFI $dst,$src\t # ptr" %}
6267 opcode(AGFI_ZOPC);
6268 ins_encode(z_rilform_signed(dst, src));
6269 ins_pipe(pipe_class_dummy);
6270 %}
6271
6272 // REG = REG1 + REG2 + IMM
6273
6274 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6275 match(Set dst (AddP (AddP src1 src2) con));
6276 predicate( PreferLAoverADD);
6277 ins_cost(DEFAULT_COST_LOW);
6278 size(4);
6279 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6280 opcode(LA_ZOPC);
6281 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6282 ins_pipe(pipe_class_dummy);
6283 %}
6284
6285 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6286 match(Set dst (AddP (AddP src1 src2) con));
6287 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6288 ins_cost(DEFAULT_COST_LOW);
6289 size(4);
6290 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6291 opcode(LA_ZOPC);
6292 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6293 ins_pipe(pipe_class_dummy);
6294 %}
6295
6296 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6297 match(Set dst (AddP (AddP src1 src2) con));
6298 predicate(PreferLAoverADD);
6299 ins_cost(DEFAULT_COST);
6300 // TODO: s390 port size(FIXED_SIZE);
6301 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6302 opcode(LAY_ZOPC);
6303 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6304 ins_pipe(pipe_class_dummy);
6305 %}
6306
6307 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6308 match(Set dst (AddP (AddP src1 src2) con));
6309 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6310 ins_cost(DEFAULT_COST);
6311 // TODO: s390 port size(FIXED_SIZE);
6312 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6313 opcode(LAY_ZOPC);
6314 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6315 ins_pipe(pipe_class_dummy);
6316 %}
6317
6318 // MEM = MEM + IMM
6319
6320 // Add Immediate to 8-byte memory operand and result
6321 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6322 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6323 effect(KILL cr);
6324 predicate(VM_Version::has_MemWithImmALUOps() && n->as_LoadStore()->barrier_data() == 0);
6325 ins_cost(MEMORY_REF_COST);
6326 size(6);
6327 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6328 opcode(AGSI_ZOPC);
6329 ins_encode(z_siyform(mem, src));
6330 ins_pipe(pipe_class_dummy);
6331 %}
6332
6333 // SUB
6334
6335 // Register Subtraction
6336 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6337 match(Set dst (SubI dst src));
6338 effect(KILL cr);
6339 // TODO: s390 port size(FIXED_SIZE);
6340 format %{ "SR $dst,$src\t # int CISC ALU" %}
6341 opcode(SR_ZOPC);
6342 ins_encode(z_rrform(dst, src));
6343 ins_pipe(pipe_class_dummy);
6344 %}
6345
6346 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6347 match(Set dst (SubI src1 src2));
6348 effect(KILL cr);
6349 predicate(VM_Version::has_DistinctOpnds());
6350 ins_cost(DEFAULT_COST);
6351 size(4);
6352 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6353 opcode(SRK_ZOPC);
6354 ins_encode(z_rrfform(dst, src1, src2));
6355 ins_pipe(pipe_class_dummy);
6356 %}
6357
6358 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6359 match(Set dst (SubI dst (LoadI src)));
6360 effect(KILL cr);
6361 ins_cost(MEMORY_REF_COST);
6362 // TODO: s390 port size(VARIABLE_SIZE);
6363 format %{ "S(Y) $dst, $src\t # int" %}
6364 opcode(SY_ZOPC, S_ZOPC);
6365 ins_encode(z_form_rt_mem_opt(dst, src));
6366 ins_pipe(pipe_class_dummy);
6367 %}
6368
6369 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6370 match(Set dst (SubI zero src));
6371 effect(KILL cr);
6372 size(2);
6373 format %{ "NEG $dst, $src" %}
6374 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6375 ins_pipe(pipe_class_dummy);
6376 %}
6377
6378 //
6379
6380 // Long subtraction
6381 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6382 match(Set dst (SubL dst src));
6383 effect(KILL cr);
6384 // TODO: s390 port size(FIXED_SIZE);
6385 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6386 opcode(SGR_ZOPC);
6387 ins_encode(z_rreform(dst, src));
6388 ins_pipe(pipe_class_dummy);
6389 %}
6390
6391 // Avoid use of LA(Y) for general ALU operation.
6392 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6393 match(Set dst (SubL src1 src2));
6394 effect(KILL cr);
6395 predicate(VM_Version::has_DistinctOpnds());
6396 ins_cost(DEFAULT_COST);
6397 size(4);
6398 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6399 opcode(SGRK_ZOPC);
6400 ins_encode(z_rrfform(dst, src1, src2));
6401 ins_pipe(pipe_class_dummy);
6402 %}
6403
6404 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6405 match(Set dst (SubL dst (ConvI2L src)));
6406 effect(KILL cr);
6407 size(4);
6408 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6409 opcode(SGFR_ZOPC);
6410 ins_encode(z_rreform(dst, src));
6411 ins_pipe(pipe_class_dummy);
6412 %}
6413
6414 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6415 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6416 effect(KILL cr);
6417 ins_cost(MEMORY_REF_COST);
6418 size(Z_DISP3_SIZE);
6419 format %{ "SGF $dst, $src\t # long/int" %}
6420 opcode(SGF_ZOPC, SGF_ZOPC);
6421 ins_encode(z_form_rt_mem_opt(dst, src));
6422 ins_pipe(pipe_class_dummy);
6423 %}
6424
6425 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6426 match(Set dst (SubL dst (LoadL src)));
6427 effect(KILL cr);
6428 ins_cost(MEMORY_REF_COST);
6429 size(Z_DISP3_SIZE);
6430 format %{ "SG $dst, $src\t # long" %}
6431 opcode(SG_ZOPC, SG_ZOPC);
6432 ins_encode(z_form_rt_mem_opt(dst, src));
6433 ins_pipe(pipe_class_dummy);
6434 %}
6435
6436 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6437
6438 // MUL
6439
6440 // Register Multiplication
6441 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6442 match(Set dst (MulI dst src));
6443 ins_cost(DEFAULT_COST);
6444 size(4);
6445 format %{ "MSR $dst, $src" %}
6446 opcode(MSR_ZOPC);
6447 ins_encode(z_rreform(dst, src));
6448 ins_pipe(pipe_class_dummy);
6449 %}
6450
6451 // Immediate Multiplication
6452 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6453 match(Set dst (MulI dst con));
6454 ins_cost(DEFAULT_COST);
6455 // TODO: s390 port size(FIXED_SIZE);
6456 format %{ "MHI $dst,$con" %}
6457 opcode(MHI_ZOPC);
6458 ins_encode(z_riform_signed(dst,con));
6459 ins_pipe(pipe_class_dummy);
6460 %}
6461
6462 // Immediate (32bit) Multiplication
6463 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6464 match(Set dst (MulI dst con));
6465 ins_cost(DEFAULT_COST);
6466 size(6);
6467 format %{ "MSFI $dst,$con" %}
6468 opcode(MSFI_ZOPC);
6469 ins_encode(z_rilform_signed(dst,con));
6470 ins_pipe(pipe_class_dummy);
6471 %}
6472
6473 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6474 match(Set dst (MulI dst (LoadI src)));
6475 ins_cost(MEMORY_REF_COST);
6476 // TODO: s390 port size(VARIABLE_SIZE);
6477 format %{ "MS(Y) $dst, $src\t # int" %}
6478 opcode(MSY_ZOPC, MS_ZOPC);
6479 ins_encode(z_form_rt_mem_opt(dst, src));
6480 ins_pipe(pipe_class_dummy);
6481 %}
6482
6483 //
6484
6485 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6486 match(Set dst (MulL dst (ConvI2L src)));
6487 ins_cost(DEFAULT_COST);
6488 // TODO: s390 port size(FIXED_SIZE);
6489 format %{ "MSGFR $dst $src\t # long/int" %}
6490 opcode(MSGFR_ZOPC);
6491 ins_encode(z_rreform(dst, src));
6492 ins_pipe(pipe_class_dummy);
6493 %}
6494
6495 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6496 match(Set dst (MulL dst src));
6497 ins_cost(DEFAULT_COST);
6498 size(4);
6499 format %{ "MSGR $dst $src\t # long" %}
6500 opcode(MSGR_ZOPC);
6501 ins_encode(z_rreform(dst, src));
6502 ins_pipe(pipe_class_dummy);
6503 %}
6504
6505 // Immediate Multiplication
6506 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6507 match(Set dst (MulL dst src));
6508 ins_cost(DEFAULT_COST);
6509 // TODO: s390 port size(FIXED_SIZE);
6510 format %{ "MGHI $dst,$src\t # long" %}
6511 opcode(MGHI_ZOPC);
6512 ins_encode(z_riform_signed(dst, src));
6513 ins_pipe(pipe_class_dummy);
6514 %}
6515
6516 // Immediate (32bit) Multiplication
6517 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6518 match(Set dst (MulL dst con));
6519 ins_cost(DEFAULT_COST);
6520 size(6);
6521 format %{ "MSGFI $dst,$con" %}
6522 opcode(MSGFI_ZOPC);
6523 ins_encode(z_rilform_signed(dst,con));
6524 ins_pipe(pipe_class_dummy);
6525 %}
6526
6527 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6528 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6529 ins_cost(MEMORY_REF_COST);
6530 size(Z_DISP3_SIZE);
6531 format %{ "MSGF $dst, $src\t # long" %}
6532 opcode(MSGF_ZOPC, MSGF_ZOPC);
6533 ins_encode(z_form_rt_mem_opt(dst, src));
6534 ins_pipe(pipe_class_dummy);
6535 %}
6536
6537 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6538 match(Set dst (MulL dst (LoadL src)));
6539 ins_cost(MEMORY_REF_COST);
6540 size(Z_DISP3_SIZE);
6541 format %{ "MSG $dst, $src\t # long" %}
6542 opcode(MSG_ZOPC, MSG_ZOPC);
6543 ins_encode(z_form_rt_mem_opt(dst, src));
6544 ins_pipe(pipe_class_dummy);
6545 %}
6546
6547 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6548 match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6549 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6550 ins_cost(7*DEFAULT_COST);
6551 // TODO: s390 port size(VARIABLE_SIZE);
6552 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6553 ins_encode%{
6554 Register dst = $Rdst$$Register;
6555 Register src1 = $Rsrc1$$Register;
6556 Register src2 = $Rsrc2$$Register;
6557 Register tmp1 = $Rtmp1$$Register;
6558 Register tmp2 = $Rdst$$Register;
6559 // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6560 // implementing mulhs(a,b) = mulhu(a,b) - (a & (b>>63)) - (b & (a>>63))
6561 __ z_srag(tmp2, src1, 63); // a>>63
6562 __ z_srag(tmp1, src2, 63); // b>>63
6563 __ z_ngr(tmp2, src2); // b & (a>>63)
6564 __ z_ngr(tmp1, src1); // a & (b>>63)
6565 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63)))
6566 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1),
6567 // multiplicand is taken from oddReg (src1), multiplier in src2.
6568 __ z_sgr(dst, tmp1);
6569 %}
6570 ins_pipe(pipe_class_dummy);
6571 %}
6572
6573 // DIV
6574
6575 // Integer DIVMOD with Register, both quotient and mod results
6576 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6577 match(DivModI dst1src1 src2);
6578 effect(KILL cr);
6579 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6580 size((VM_Version::has_CompareBranch() ? 24 : 26));
6581 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6582 ins_encode %{
6583 Register d1s1 = $dst1src1$$Register;
6584 Register d2 = $dst2$$Register;
6585 Register s2 = $src2$$Register;
6586
6587 assert_different_registers(d1s1, s2);
6588
6589 Label do_div, done_div;
6590 if (VM_Version::has_CompareBranch()) {
6591 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6592 } else {
6593 __ z_chi(s2, -1);
6594 __ z_brne(do_div);
6595 }
6596 __ z_lcr(d1s1, d1s1);
6597 __ clear_reg(d2, false, false);
6598 __ z_bru(done_div);
6599 __ bind(do_div);
6600 __ z_lgfr(d1s1, d1s1);
6601 __ z_dsgfr(d2, s2);
6602 __ bind(done_div);
6603 %}
6604 ins_pipe(pipe_class_dummy);
6605 %}
6606
6607
6608 // Register Division
6609 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6610 match(Set dst (DivI src1 src2));
6611 effect(KILL tmp, KILL cr);
6612 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6613 size((VM_Version::has_CompareBranch() ? 20 : 22));
6614 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6615 ins_encode %{
6616 Register a = $src1$$Register;
6617 Register b = $src2$$Register;
6618 Register t = $dst$$Register;
6619
6620 assert_different_registers(t, b);
6621
6622 Label do_div, done_div;
6623 if (VM_Version::has_CompareBranch()) {
6624 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6625 } else {
6626 __ z_chi(b, -1);
6627 __ z_brne(do_div);
6628 }
6629 __ z_lcr(t, a);
6630 __ z_bru(done_div);
6631 __ bind(do_div);
6632 __ z_lgfr(t, a);
6633 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6634 __ bind(done_div);
6635 %}
6636 ins_pipe(pipe_class_dummy);
6637 %}
6638
6639 // Immediate Division
6640 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6641 match(Set dst (DivI src1 src2));
6642 effect(KILL tmp, KILL cr); // R0 is killed, too.
6643 ins_cost(2 * DEFAULT_COST);
6644 // TODO: s390 port size(VARIABLE_SIZE);
6645 format %{ "DIV_const $dst,$src1,$src2" %}
6646 ins_encode %{
6647 // No sign extension of Rdividend needed here.
6648 if ($src2$$constant != -1) {
6649 __ z_lghi(Z_R0_scratch, $src2$$constant);
6650 __ z_lgfr($dst$$Register, $src1$$Register);
6651 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6652 } else {
6653 __ z_lcr($dst$$Register, $src1$$Register);
6654 }
6655 %}
6656 ins_pipe(pipe_class_dummy);
6657 %}
6658
6659 // Unsigned Integer Register Division
6660 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6661 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6662 instruct udivI_reg_reg(roddRegI r5_rodd_dst, iRegI src2, revenRegI r4_reven_tmp, flagsReg cr) %{
6663 match(Set r5_rodd_dst (UDivI r5_rodd_dst src2));
6664 effect(TEMP r4_reven_tmp, KILL cr);
6665 // TODO: size(4);
6666 format %{ "UDIV $r5_rodd_dst,$r5_rodd_dst,$src2" %}
6667 ins_encode %{
6668 Register b = $src2$$Register;
6669 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6670 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6671 assert_different_registers(r4_reven_tmp, r5_rodd_dst, b);
6672 assert(r4_reven_tmp->successor() == r5_rodd_dst, "even-odd pair required for the instruction");
6673
6674 __ block_comment("unsigned_div_int {");
6675 __ z_lhi(r4_reven_tmp, 0); // make upper 32bits 0
6676 __ z_dlr(r4_reven_tmp, b);
6677 __ block_comment("} unsigned_div_int");
6678 %}
6679 ins_pipe(pipe_class_dummy);
6680 %}
6681
6682 // Long DIVMOD with Register, both quotient and mod results
6683 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6684 match(DivModL dst1src1 src2);
6685 effect(KILL cr);
6686 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6687 size((VM_Version::has_CompareBranch() ? 22 : 24));
6688 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6689 ins_encode %{
6690 Register d1s1 = $dst1src1$$Register;
6691 Register d2 = $dst2$$Register;
6692 Register s2 = $src2$$Register;
6693
6694 Label do_div, done_div;
6695 if (VM_Version::has_CompareBranch()) {
6696 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6697 } else {
6698 __ z_cghi(s2, -1);
6699 __ z_brne(do_div);
6700 }
6701 __ z_lcgr(d1s1, d1s1);
6702 // indicate unused result
6703 (void) __ clear_reg(d2, true, false);
6704 __ z_bru(done_div);
6705 __ bind(do_div);
6706 __ z_dsgr(d2, s2);
6707 __ bind(done_div);
6708 %}
6709 ins_pipe(pipe_class_dummy);
6710 %}
6711
6712 // Register Long Division
6713 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6714 match(Set dst (DivL dst src));
6715 effect(KILL tmp, KILL cr);
6716 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6717 size((VM_Version::has_CompareBranch() ? 18 : 20));
6718 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6719 ins_encode %{
6720 Register b = $src$$Register;
6721 Register t = $dst$$Register;
6722
6723 Label done_div;
6724 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6725 if (VM_Version::has_CompareBranch()) {
6726 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6727 } else {
6728 __ z_cghi(b, -1);
6729 __ z_bre(done_div);
6730 }
6731 __ z_lcgr(t, t); // Restore sign.
6732 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6733 __ bind(done_div);
6734 %}
6735 ins_pipe(pipe_class_dummy);
6736 %}
6737
6738 // Register Unsigned Long Division
6739 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6740 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6741 instruct udivL_reg_reg(roddRegL r5_rodd_dst, iRegL src, revenRegL r4_reven_tmp, flagsReg cr) %{
6742 match(Set r5_rodd_dst (UDivL r5_rodd_dst src));
6743 effect(TEMP r4_reven_tmp, KILL cr);
6744 ins_cost(DEFAULT_COST);
6745 // TODO: size(4);
6746 format %{ "UDIVG $r5_rodd_dst,$r5_rodd_dst,$src" %}
6747 ins_encode %{
6748 Register b = $src$$Register;
6749 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6750 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6751 assert_different_registers(r5_rodd_dst, r4_reven_tmp, b);
6752 __ block_comment("unsigned_div_long {");
6753 __ z_lghi(r4_reven_tmp, 0); // make upper 64bits 0
6754 __ z_dlgr(r4_reven_tmp, b);
6755 __ block_comment("} unsigned_div_long");
6756 %}
6757 ins_pipe(pipe_class_dummy);
6758 %}
6759
6760 // Immediate Long Division
6761 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6762 match(Set dst (DivL src1 src2));
6763 effect(KILL tmp, KILL cr); // R0 is killed, too.
6764 ins_cost(2 * DEFAULT_COST);
6765 // TODO: s390 port size(VARIABLE_SIZE);
6766 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6767 ins_encode %{
6768 if ($src2$$constant != -1) {
6769 __ z_lghi(Z_R0_scratch, $src2$$constant);
6770 __ lgr_if_needed($dst$$Register, $src1$$Register);
6771 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6772 } else {
6773 __ z_lcgr($dst$$Register, $src1$$Register);
6774 }
6775 %}
6776 ins_pipe(pipe_class_dummy);
6777 %}
6778
6779 // REM
6780
6781 // Integer Remainder
6782 // Register Remainder
6783 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6784 match(Set dst (ModI src1 src2));
6785 effect(KILL tmp, KILL cr);
6786 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6787 // TODO: s390 port size(VARIABLE_SIZE);
6788 format %{ "MOD_checked $dst,$src1,$src2" %}
6789 ins_encode %{
6790 Register a = $src1$$Register;
6791 Register b = $src2$$Register;
6792 Register t = $dst$$Register;
6793 assert_different_registers(t->successor(), b);
6794
6795 Label do_div, done_div;
6796
6797 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6798 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6799 if (VM_Version::has_CompareBranch()) {
6800 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6801 } else {
6802 __ z_chi(b, -1);
6803 __ z_bre(done_div);
6804 }
6805 __ z_lgfr(t->successor(), a);
6806 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6807 } else {
6808 if (VM_Version::has_CompareBranch()) {
6809 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6810 } else {
6811 __ z_chi(b, -1);
6812 __ z_brne(do_div);
6813 }
6814 __ clear_reg(t, true, false);
6815 __ z_bru(done_div);
6816 __ bind(do_div);
6817 __ z_lgfr(t->successor(), a);
6818 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6819 }
6820 __ bind(done_div);
6821 %}
6822 ins_pipe(pipe_class_dummy);
6823 %}
6824
6825 // Register Unsigned Integer Remainder
6826 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6827 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6828 instruct umodI_reg_reg(revenRegI r4_reven_dst, iRegI src2, roddRegI r5_rodd_tmp, flagsReg cr) %{
6829 match(Set r4_reven_dst (UModI r4_reven_dst src2));
6830 effect(TEMP r5_rodd_tmp, KILL cr);
6831 ins_cost(DEFAULT_COST);
6832 // TODO: s390 port size(VARIABLE_SIZE);
6833 format %{ "UMOD $r4_reven_dst,$r4_reven_dst,$src2" %}
6834 ins_encode %{
6835 Register b = $src2$$Register;
6836 Register r4_reven_dst = $r4_reven_dst$$Register;
6837 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6838 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6839 assert(r4_reven_dst->successor() == r5_rodd_tmp, "must be an even-odd pair");
6840
6841 __ block_comment("unsigned_mod_integer {");
6842 __ z_lr(r5_rodd_tmp, r4_reven_dst); // load lower 32bits in odd register
6843 __ z_lhi(r4_reven_dst, 0); // make upper 32bits 0
6844 __ z_dlr(r4_reven_dst, b);
6845 __ block_comment("} unsigned_mod_integer");
6846 %}
6847 ins_pipe(pipe_class_dummy);
6848 %}
6849
6850 // Immediate Remainder
6851 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6852 match(Set dst (ModI src1 src2));
6853 effect(KILL tmp, KILL cr); // R0 is killed, too.
6854 ins_cost(3 * DEFAULT_COST);
6855 // TODO: s390 port size(VARIABLE_SIZE);
6856 format %{ "MOD_const $dst,src1,$src2" %}
6857 ins_encode %{
6858 assert_different_registers($dst$$Register, $src1$$Register);
6859 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6860 int divisor = $src2$$constant;
6861
6862 if (divisor != -1) {
6863 __ z_lghi(Z_R0_scratch, divisor);
6864 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6865 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6866 } else {
6867 __ clear_reg($dst$$Register, true, false);
6868 }
6869 %}
6870 ins_pipe(pipe_class_dummy);
6871 %}
6872
6873 // Register Long Remainder
6874 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6875 match(Set dst (ModL src1 src2));
6876 effect(KILL src1, KILL cr); // R0 is killed, too.
6877 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6878 // TODO: s390 port size(VARIABLE_SIZE);
6879 format %{ "MODG_checked $dst,$src1,$src2" %}
6880 ins_encode %{
6881 Register a = $src1$$Register;
6882 Register b = $src2$$Register;
6883 Register t = $dst$$Register;
6884 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6885
6886 Label do_div, done_div;
6887 if (t->encoding() != b->encoding()) {
6888 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6889 if (VM_Version::has_CompareBranch()) {
6890 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6891 } else {
6892 __ z_cghi(b, -1);
6893 __ z_bre(done_div);
6894 }
6895 __ z_dsgr(t, b);
6896 } else {
6897 if (VM_Version::has_CompareBranch()) {
6898 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6899 } else {
6900 __ z_cghi(b, -1);
6901 __ z_brne(do_div);
6902 }
6903 __ clear_reg(t, true, false);
6904 __ z_bru(done_div);
6905 __ bind(do_div);
6906 __ z_dsgr(t, b);
6907 }
6908 __ bind(done_div);
6909 %}
6910 ins_pipe(pipe_class_dummy);
6911 %}
6912
6913 // Register Unsigned Long Remainder
6914 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6915 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6916 instruct umodL_reg_reg(revenRegL r4_reven_dst, roddRegL r5_rodd_tmp, iRegL src2, flagsReg cr) %{
6917 match(Set r4_reven_dst (UModL r4_reven_dst src2));
6918 effect(TEMP r5_rodd_tmp, KILL cr);
6919 ins_cost(DEFAULT_COST);
6920 // TODO: s390 port size(VARIABLE_SIZE);
6921 format %{ "UMODG $r4_reven_dst,$r4_reven_dst,$src2" %}
6922 ins_encode %{
6923 Register b = $src2$$Register;
6924 Register r4_reven_dst = $r4_reven_dst$$Register;
6925 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6926 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6927 assert(r4_reven_dst->successor() == r5_rodd_tmp, "instruction requires an even-odd pair" );
6928
6929 __ block_comment("unsigned_mod_long {");
6930 __ z_lgr(r5_rodd_tmp, r4_reven_dst); // load lower 64bits in even register
6931 __ z_lghi(r4_reven_dst, 0); // make upper 64bits 0
6932 __ z_dlgr(r4_reven_dst, b);
6933 __ block_comment("} unsigned_mod_long");
6934 %}
6935 ins_pipe(pipe_class_dummy);
6936 %}
6937
6938 // Register Long Remainder
6939 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6940 match(Set dst (ModL src1 src2));
6941 effect(KILL tmp, KILL cr); // R0 is killed, too.
6942 ins_cost(3 * DEFAULT_COST);
6943 // TODO: s390 port size(VARIABLE_SIZE);
6944 format %{ "MODG_const $dst,src1,$src2\t # long" %}
6945 ins_encode %{
6946 int divisor = $src2$$constant;
6947 if (divisor != -1) {
6948 __ z_lghi(Z_R0_scratch, divisor);
6949 __ z_lgr($dst$$Register->successor(), $src1$$Register);
6950 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6951 } else {
6952 __ clear_reg($dst$$Register, true, false);
6953 }
6954 %}
6955 ins_pipe(pipe_class_dummy);
6956 %}
6957
6958 // SHIFT
6959
6960 // Shift left logical
6961
6962 // Register Shift Left variable
6963 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6964 match(Set dst (LShiftI src nbits));
6965 effect(KILL cr); // R1 is killed, too.
6966 ins_cost(3 * DEFAULT_COST);
6967 size(14);
6968 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
6969 ins_encode %{
6970 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6971 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6972 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6973 %}
6974 ins_pipe(pipe_class_dummy);
6975 %}
6976
6977 // Register Shift Left Immediate
6978 // Constant shift count is masked in ideal graph already.
6979 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6980 match(Set dst (LShiftI src nbits));
6981 size(6);
6982 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
6983 ins_encode %{
6984 int Nbit = $nbits$$constant;
6985 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6986 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6987 %}
6988 ins_pipe(pipe_class_dummy);
6989 %}
6990
6991 // Register Shift Left Immediate by 1bit
6992 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6993 match(Set dst (LShiftI src nbits));
6994 predicate(PreferLAoverADD);
6995 ins_cost(DEFAULT_COST_LOW);
6996 size(4);
6997 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6998 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6999 ins_pipe(pipe_class_dummy);
7000 %}
7001
7002 // Register Shift Left Long
7003 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
7004 match(Set dst (LShiftL src1 nbits));
7005 size(6);
7006 format %{ "SLLG $dst,$src1,[$nbits]" %}
7007 opcode(SLLG_ZOPC);
7008 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
7009 ins_pipe(pipe_class_dummy);
7010 %}
7011
7012 // Register Shift Left Long Immediate
7013 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
7014 match(Set dst (LShiftL src1 nbits));
7015 size(6);
7016 format %{ "SLLG $dst,$src1,$nbits" %}
7017 opcode(SLLG_ZOPC);
7018 ins_encode(z_rsyform_const(dst, src1, nbits));
7019 ins_pipe(pipe_class_dummy);
7020 %}
7021
7022 // Register Shift Left Long Immediate by 1bit
7023 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
7024 match(Set dst (LShiftL src1 nbits));
7025 predicate(PreferLAoverADD);
7026 ins_cost(DEFAULT_COST_LOW);
7027 size(4);
7028 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
7029 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
7030 ins_pipe(pipe_class_dummy);
7031 %}
7032
7033 // Shift right arithmetic
7034
7035 // Register Arithmetic Shift Right
7036 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7037 match(Set dst (RShiftI dst src));
7038 effect(KILL cr); // R1 is killed, too.
7039 ins_cost(3 * DEFAULT_COST);
7040 size(12);
7041 format %{ "SRA $dst,[$src] & 31" %}
7042 ins_encode %{
7043 __ z_lgr(Z_R1_scratch, $src$$Register);
7044 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7045 __ z_sra($dst$$Register, 0, Z_R1_scratch);
7046 %}
7047 ins_pipe(pipe_class_dummy);
7048 %}
7049
7050 // Register Arithmetic Shift Right Immediate
7051 // Constant shift count is masked in ideal graph already.
7052 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
7053 match(Set dst (RShiftI dst src));
7054 effect(KILL cr);
7055 size(4);
7056 format %{ "SRA $dst,$src" %}
7057 ins_encode %{
7058 int Nbit = $src$$constant;
7059 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7060 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7061 %}
7062 ins_pipe(pipe_class_dummy);
7063 %}
7064
7065 // Register Arithmetic Shift Right Long
7066 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
7067 match(Set dst (RShiftL src1 src2));
7068 effect(KILL cr);
7069 size(6);
7070 format %{ "SRAG $dst,$src1,[$src2]" %}
7071 opcode(SRAG_ZOPC);
7072 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7073 ins_pipe(pipe_class_dummy);
7074 %}
7075
7076 // Register Arithmetic Shift Right Long Immediate
7077 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
7078 match(Set dst (RShiftL src1 src2));
7079 effect(KILL cr);
7080 size(6);
7081 format %{ "SRAG $dst,$src1,$src2" %}
7082 opcode(SRAG_ZOPC);
7083 ins_encode(z_rsyform_const(dst, src1, src2));
7084 ins_pipe(pipe_class_dummy);
7085 %}
7086
7087 // Shift right logical
7088
7089 // Register Shift Right
7090 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7091 match(Set dst (URShiftI dst src));
7092 effect(KILL cr); // R1 is killed, too.
7093 ins_cost(3 * DEFAULT_COST);
7094 size(12);
7095 format %{ "SRL $dst,[$src] & 31" %}
7096 ins_encode %{
7097 __ z_lgr(Z_R1_scratch, $src$$Register);
7098 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7099 __ z_srl($dst$$Register, 0, Z_R1_scratch);
7100 %}
7101 ins_pipe(pipe_class_dummy);
7102 %}
7103
7104 // Register Shift Right Immediate
7105 // Constant shift count is masked in ideal graph already.
7106 instruct srlI_reg_imm(iRegI dst, immI src) %{
7107 match(Set dst (URShiftI dst src));
7108 size(4);
7109 format %{ "SRL $dst,$src" %}
7110 ins_encode %{
7111 int Nbit = $src$$constant;
7112 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7113 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7114 %}
7115 ins_pipe(pipe_class_dummy);
7116 %}
7117
7118 // Register Shift Right Long
7119 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7120 match(Set dst (URShiftL src1 src2));
7121 size(6);
7122 format %{ "SRLG $dst,$src1,[$src2]" %}
7123 opcode(SRLG_ZOPC);
7124 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7125 ins_pipe(pipe_class_dummy);
7126 %}
7127
7128 // Register Shift Right Long Immediate
7129 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
7130 match(Set dst (URShiftL src1 src2));
7131 size(6);
7132 format %{ "SRLG $dst,$src1,$src2" %}
7133 opcode(SRLG_ZOPC);
7134 ins_encode(z_rsyform_const(dst, src1, src2));
7135 ins_pipe(pipe_class_dummy);
7136 %}
7137
7138 // Register Shift Right Immediate with a CastP2X
7139 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
7140 match(Set dst (URShiftL (CastP2X src1) src2));
7141 size(6);
7142 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
7143 opcode(SRLG_ZOPC);
7144 ins_encode(z_rsyform_const(dst, src1, src2));
7145 ins_pipe(pipe_class_dummy);
7146 %}
7147
7148 //----------Rotate Instructions------------------------------------------------
7149
7150 // Rotate left 32bit.
7151 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
7152 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
7153 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7154 size(6);
7155 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
7156 opcode(RLL_ZOPC);
7157 ins_encode(z_rsyform_const(dst, src, lshift));
7158 ins_pipe(pipe_class_dummy);
7159 %}
7160
7161 // Rotate left 64bit.
7162 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
7163 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
7164 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7165 size(6);
7166 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
7167 opcode(RLLG_ZOPC);
7168 ins_encode(z_rsyform_const(dst, src, lshift));
7169 ins_pipe(pipe_class_dummy);
7170 %}
7171
7172 // Rotate right 32bit.
7173 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
7174 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
7175 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7176 // TODO: s390 port size(FIXED_SIZE);
7177 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
7178 opcode(RLL_ZOPC);
7179 ins_encode(z_rsyform_const(dst, src, rshift));
7180 ins_pipe(pipe_class_dummy);
7181 %}
7182
7183 // Rotate right 64bit.
7184 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7185 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7186 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7187 // TODO: s390 port size(FIXED_SIZE);
7188 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
7189 opcode(RLLG_ZOPC);
7190 ins_encode(z_rsyform_const(dst, src, rshift));
7191 ins_pipe(pipe_class_dummy);
7192 %}
7193
7194
7195 //----------Overflow Math Instructions-----------------------------------------
7196
7197 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7198 match(Set cr (OverflowAddI op1 op2));
7199 effect(DEF cr, USE op1, USE op2);
7200 // TODO: s390 port size(FIXED_SIZE);
7201 format %{ "AR $op1,$op2\t # overflow check int" %}
7202 ins_encode %{
7203 __ z_lr(Z_R0_scratch, $op1$$Register);
7204 __ z_ar(Z_R0_scratch, $op2$$Register);
7205 %}
7206 ins_pipe(pipe_class_dummy);
7207 %}
7208
7209 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7210 match(Set cr (OverflowAddI op1 op2));
7211 effect(DEF cr, USE op1, USE op2);
7212 // TODO: s390 port size(VARIABLE_SIZE);
7213 format %{ "AR $op1,$op2\t # overflow check int" %}
7214 ins_encode %{
7215 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7216 __ z_ar(Z_R0_scratch, $op1$$Register);
7217 %}
7218 ins_pipe(pipe_class_dummy);
7219 %}
7220
7221 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7222 match(Set cr (OverflowAddL op1 op2));
7223 effect(DEF cr, USE op1, USE op2);
7224 // TODO: s390 port size(FIXED_SIZE);
7225 format %{ "AGR $op1,$op2\t # overflow check long" %}
7226 ins_encode %{
7227 __ z_lgr(Z_R0_scratch, $op1$$Register);
7228 __ z_agr(Z_R0_scratch, $op2$$Register);
7229 %}
7230 ins_pipe(pipe_class_dummy);
7231 %}
7232
7233 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7234 match(Set cr (OverflowAddL op1 op2));
7235 effect(DEF cr, USE op1, USE op2);
7236 // TODO: s390 port size(VARIABLE_SIZE);
7237 format %{ "AGR $op1,$op2\t # overflow check long" %}
7238 ins_encode %{
7239 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7240 __ z_agr(Z_R0_scratch, $op1$$Register);
7241 %}
7242 ins_pipe(pipe_class_dummy);
7243 %}
7244
7245 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7246 match(Set cr (OverflowSubI op1 op2));
7247 effect(DEF cr, USE op1, USE op2);
7248 // TODO: s390 port size(FIXED_SIZE);
7249 format %{ "SR $op1,$op2\t # overflow check int" %}
7250 ins_encode %{
7251 __ z_lr(Z_R0_scratch, $op1$$Register);
7252 __ z_sr(Z_R0_scratch, $op2$$Register);
7253 %}
7254 ins_pipe(pipe_class_dummy);
7255 %}
7256
7257 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7258 match(Set cr (OverflowSubI op1 op2));
7259 effect(DEF cr, USE op1, USE op2);
7260 // TODO: s390 port size(VARIABLE_SIZE);
7261 format %{ "SR $op1,$op2\t # overflow check int" %}
7262 ins_encode %{
7263 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7264 __ z_lr(Z_R0_scratch, $op1$$Register);
7265 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7266 %}
7267 ins_pipe(pipe_class_dummy);
7268 %}
7269
7270 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7271 match(Set cr (OverflowSubL op1 op2));
7272 effect(DEF cr, USE op1, USE op2);
7273 // TODO: s390 port size(FIXED_SIZE);
7274 format %{ "SGR $op1,$op2\t # overflow check long" %}
7275 ins_encode %{
7276 __ z_lgr(Z_R0_scratch, $op1$$Register);
7277 __ z_sgr(Z_R0_scratch, $op2$$Register);
7278 %}
7279 ins_pipe(pipe_class_dummy);
7280 %}
7281
7282 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7283 match(Set cr (OverflowSubL op1 op2));
7284 effect(DEF cr, USE op1, USE op2);
7285 // TODO: s390 port size(VARIABLE_SIZE);
7286 format %{ "SGR $op1,$op2\t # overflow check long" %}
7287 ins_encode %{
7288 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7289 __ z_lgr(Z_R0_scratch, $op1$$Register);
7290 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7291 %}
7292 ins_pipe(pipe_class_dummy);
7293 %}
7294
7295 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7296 match(Set cr (OverflowSubI zero op2));
7297 effect(DEF cr, USE op2);
7298 format %{ "NEG $op2\t # overflow check int" %}
7299 ins_encode %{
7300 __ clear_reg(Z_R0_scratch, false, false);
7301 __ z_sr(Z_R0_scratch, $op2$$Register);
7302 %}
7303 ins_pipe(pipe_class_dummy);
7304 %}
7305
7306 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7307 match(Set cr (OverflowSubL zero op2));
7308 effect(DEF cr, USE op2);
7309 format %{ "NEGG $op2\t # overflow check long" %}
7310 ins_encode %{
7311 __ clear_reg(Z_R0_scratch, true, false);
7312 __ z_sgr(Z_R0_scratch, $op2$$Register);
7313 %}
7314 ins_pipe(pipe_class_dummy);
7315 %}
7316
7317 // No intrinsics for multiplication, since there is no easy way
7318 // to check for overflow.
7319
7320
7321 //----------Floating Point Arithmetic Instructions-----------------------------
7322
7323 // ADD
7324
7325 // Add float single precision
7326 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7327 match(Set dst (AddF dst src));
7328 effect(KILL cr);
7329 ins_cost(ALU_REG_COST);
7330 size(4);
7331 format %{ "AEBR $dst,$src" %}
7332 opcode(AEBR_ZOPC);
7333 ins_encode(z_rreform(dst, src));
7334 ins_pipe(pipe_class_dummy);
7335 %}
7336
7337 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7338 match(Set dst (AddF dst (LoadF src)));
7339 effect(KILL cr);
7340 ins_cost(ALU_MEMORY_COST);
7341 size(6);
7342 format %{ "AEB $dst,$src\t # floatMemory" %}
7343 opcode(AEB_ZOPC);
7344 ins_encode(z_form_rt_memFP(dst, src));
7345 ins_pipe(pipe_class_dummy);
7346 %}
7347
7348 // Add float double precision
7349 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7350 match(Set dst (AddD dst src));
7351 effect(KILL cr);
7352 ins_cost(ALU_REG_COST);
7353 size(4);
7354 format %{ "ADBR $dst,$src" %}
7355 opcode(ADBR_ZOPC);
7356 ins_encode(z_rreform(dst, src));
7357 ins_pipe(pipe_class_dummy);
7358 %}
7359
7360 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7361 match(Set dst (AddD dst (LoadD src)));
7362 effect(KILL cr);
7363 ins_cost(ALU_MEMORY_COST);
7364 size(6);
7365 format %{ "ADB $dst,$src\t # doubleMemory" %}
7366 opcode(ADB_ZOPC);
7367 ins_encode(z_form_rt_memFP(dst, src));
7368 ins_pipe(pipe_class_dummy);
7369 %}
7370
7371 // SUB
7372
7373 // Sub float single precision
7374 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7375 match(Set dst (SubF dst src));
7376 effect(KILL cr);
7377 ins_cost(ALU_REG_COST);
7378 size(4);
7379 format %{ "SEBR $dst,$src" %}
7380 opcode(SEBR_ZOPC);
7381 ins_encode(z_rreform(dst, src));
7382 ins_pipe(pipe_class_dummy);
7383 %}
7384
7385 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7386 match(Set dst (SubF dst (LoadF src)));
7387 effect(KILL cr);
7388 ins_cost(ALU_MEMORY_COST);
7389 size(6);
7390 format %{ "SEB $dst,$src\t # floatMemory" %}
7391 opcode(SEB_ZOPC);
7392 ins_encode(z_form_rt_memFP(dst, src));
7393 ins_pipe(pipe_class_dummy);
7394 %}
7395
7396 // Sub float double precision
7397 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7398 match(Set dst (SubD dst src));
7399 effect(KILL cr);
7400 ins_cost(ALU_REG_COST);
7401 size(4);
7402 format %{ "SDBR $dst,$src" %}
7403 opcode(SDBR_ZOPC);
7404 ins_encode(z_rreform(dst, src));
7405 ins_pipe(pipe_class_dummy);
7406 %}
7407
7408 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7409 match(Set dst (SubD dst (LoadD src)));
7410 effect(KILL cr);
7411 ins_cost(ALU_MEMORY_COST);
7412 size(6);
7413 format %{ "SDB $dst,$src\t # doubleMemory" %}
7414 opcode(SDB_ZOPC);
7415 ins_encode(z_form_rt_memFP(dst, src));
7416 ins_pipe(pipe_class_dummy);
7417 %}
7418
7419 // MUL
7420
7421 // Mul float single precision
7422 instruct mulF_reg_reg(regF dst, regF src) %{
7423 match(Set dst (MulF dst src));
7424 // CC unchanged by MUL.
7425 ins_cost(ALU_REG_COST);
7426 size(4);
7427 format %{ "MEEBR $dst,$src" %}
7428 opcode(MEEBR_ZOPC);
7429 ins_encode(z_rreform(dst, src));
7430 ins_pipe(pipe_class_dummy);
7431 %}
7432
7433 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7434 match(Set dst (MulF dst (LoadF src)));
7435 // CC unchanged by MUL.
7436 ins_cost(ALU_MEMORY_COST);
7437 size(6);
7438 format %{ "MEEB $dst,$src\t # floatMemory" %}
7439 opcode(MEEB_ZOPC);
7440 ins_encode(z_form_rt_memFP(dst, src));
7441 ins_pipe(pipe_class_dummy);
7442 %}
7443
7444 // Mul float double precision
7445 instruct mulD_reg_reg(regD dst, regD src) %{
7446 match(Set dst (MulD dst src));
7447 // CC unchanged by MUL.
7448 ins_cost(ALU_REG_COST);
7449 size(4);
7450 format %{ "MDBR $dst,$src" %}
7451 opcode(MDBR_ZOPC);
7452 ins_encode(z_rreform(dst, src));
7453 ins_pipe(pipe_class_dummy);
7454 %}
7455
7456 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7457 match(Set dst (MulD dst (LoadD src)));
7458 // CC unchanged by MUL.
7459 ins_cost(ALU_MEMORY_COST);
7460 size(6);
7461 format %{ "MDB $dst,$src\t # doubleMemory" %}
7462 opcode(MDB_ZOPC);
7463 ins_encode(z_form_rt_memFP(dst, src));
7464 ins_pipe(pipe_class_dummy);
7465 %}
7466
7467 // Multiply-Accumulate
7468 // src1 * src2 + dst
7469 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7470 match(Set dst (FmaF dst (Binary src1 src2)));
7471 // CC unchanged by MUL-ADD.
7472 ins_cost(ALU_REG_COST);
7473 size(4);
7474 format %{ "MAEBR $dst, $src1, $src2" %}
7475 ins_encode %{
7476 assert(UseFMA, "Needs FMA instructions support.");
7477 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7478 %}
7479 ins_pipe(pipe_class_dummy);
7480 %}
7481
7482 // src1 * src2 + dst
7483 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7484 match(Set dst (FmaD dst (Binary src1 src2)));
7485 // CC unchanged by MUL-ADD.
7486 ins_cost(ALU_REG_COST);
7487 size(4);
7488 format %{ "MADBR $dst, $src1, $src2" %}
7489 ins_encode %{
7490 assert(UseFMA, "Needs FMA instructions support.");
7491 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7492 %}
7493 ins_pipe(pipe_class_dummy);
7494 %}
7495
7496 // src1 * src2 - dst
7497 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7498 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7499 // CC unchanged by MUL-SUB.
7500 ins_cost(ALU_REG_COST);
7501 size(4);
7502 format %{ "MSEBR $dst, $src1, $src2" %}
7503 ins_encode %{
7504 assert(UseFMA, "Needs FMA instructions support.");
7505 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7506 %}
7507 ins_pipe(pipe_class_dummy);
7508 %}
7509
7510 // src1 * src2 - dst
7511 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7512 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7513 // CC unchanged by MUL-SUB.
7514 ins_cost(ALU_REG_COST);
7515 size(4);
7516 format %{ "MSDBR $dst, $src1, $src2" %}
7517 ins_encode %{
7518 assert(UseFMA, "Needs FMA instructions support.");
7519 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7520 %}
7521 ins_pipe(pipe_class_dummy);
7522 %}
7523
7524 // src1 * src2 + dst
7525 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7526 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7527 // CC unchanged by MUL-ADD.
7528 ins_cost(ALU_MEMORY_COST);
7529 size(6);
7530 format %{ "MAEB $dst, $src1, $src2" %}
7531 ins_encode %{
7532 assert(UseFMA, "Needs FMA instructions support.");
7533 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7534 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7535 %}
7536 ins_pipe(pipe_class_dummy);
7537 %}
7538
7539 // src1 * src2 + dst
7540 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7541 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7542 // CC unchanged by MUL-ADD.
7543 ins_cost(ALU_MEMORY_COST);
7544 size(6);
7545 format %{ "MADB $dst, $src1, $src2" %}
7546 ins_encode %{
7547 assert(UseFMA, "Needs FMA instructions support.");
7548 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7549 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7550 %}
7551 ins_pipe(pipe_class_dummy);
7552 %}
7553
7554 // src1 * src2 - dst
7555 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7556 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7557 // CC unchanged by MUL-SUB.
7558 ins_cost(ALU_MEMORY_COST);
7559 size(6);
7560 format %{ "MSEB $dst, $src1, $src2" %}
7561 ins_encode %{
7562 assert(UseFMA, "Needs FMA instructions support.");
7563 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7564 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7565 %}
7566 ins_pipe(pipe_class_dummy);
7567 %}
7568
7569 // src1 * src2 - dst
7570 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7571 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7572 // CC unchanged by MUL-SUB.
7573 ins_cost(ALU_MEMORY_COST);
7574 size(6);
7575 format %{ "MSDB $dst, $src1, $src2" %}
7576 ins_encode %{
7577 assert(UseFMA, "Needs FMA instructions support.");
7578 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7579 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7580 %}
7581 ins_pipe(pipe_class_dummy);
7582 %}
7583
7584 // src1 * src2 + dst
7585 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7586 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7587 // CC unchanged by MUL-ADD.
7588 ins_cost(ALU_MEMORY_COST);
7589 size(6);
7590 format %{ "MAEB $dst, $src1, $src2" %}
7591 ins_encode %{
7592 assert(UseFMA, "Needs FMA instructions support.");
7593 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7594 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7595 %}
7596 ins_pipe(pipe_class_dummy);
7597 %}
7598
7599 // src1 * src2 + dst
7600 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7601 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7602 // CC unchanged by MUL-ADD.
7603 ins_cost(ALU_MEMORY_COST);
7604 size(6);
7605 format %{ "MADB $dst, $src1, $src2" %}
7606 ins_encode %{
7607 assert(UseFMA, "Needs FMA instructions support.");
7608 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7609 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7610 %}
7611 ins_pipe(pipe_class_dummy);
7612 %}
7613
7614 // src1 * src2 - dst
7615 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7616 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7617 // CC unchanged by MUL-SUB.
7618 ins_cost(ALU_MEMORY_COST);
7619 size(6);
7620 format %{ "MSEB $dst, $src1, $src2" %}
7621 ins_encode %{
7622 assert(UseFMA, "Needs FMA instructions support.");
7623 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7624 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7625 %}
7626 ins_pipe(pipe_class_dummy);
7627 %}
7628
7629 // src1 * src2 - dst
7630 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7631 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7632 // CC unchanged by MUL-SUB.
7633 ins_cost(ALU_MEMORY_COST);
7634 size(6);
7635 format %{ "MSDB $dst, $src1, $src2" %}
7636 ins_encode %{
7637 assert(UseFMA, "Needs FMA instructions support.");
7638 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7639 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7640 %}
7641 ins_pipe(pipe_class_dummy);
7642 %}
7643
7644 // DIV
7645
7646 // Div float single precision
7647 instruct divF_reg_reg(regF dst, regF src) %{
7648 match(Set dst (DivF dst src));
7649 // CC unchanged by DIV.
7650 ins_cost(ALU_REG_COST);
7651 size(4);
7652 format %{ "DEBR $dst,$src" %}
7653 opcode(DEBR_ZOPC);
7654 ins_encode(z_rreform(dst, src));
7655 ins_pipe(pipe_class_dummy);
7656 %}
7657
7658 instruct divF_reg_mem(regF dst, memoryRX src)%{
7659 match(Set dst (DivF dst (LoadF src)));
7660 // CC unchanged by DIV.
7661 ins_cost(ALU_MEMORY_COST);
7662 size(6);
7663 format %{ "DEB $dst,$src\t # floatMemory" %}
7664 opcode(DEB_ZOPC);
7665 ins_encode(z_form_rt_memFP(dst, src));
7666 ins_pipe(pipe_class_dummy);
7667 %}
7668
7669 // Div float double precision
7670 instruct divD_reg_reg(regD dst, regD src) %{
7671 match(Set dst (DivD dst src));
7672 // CC unchanged by DIV.
7673 ins_cost(ALU_REG_COST);
7674 size(4);
7675 format %{ "DDBR $dst,$src" %}
7676 opcode(DDBR_ZOPC);
7677 ins_encode(z_rreform(dst, src));
7678 ins_pipe(pipe_class_dummy);
7679 %}
7680
7681 instruct divD_reg_mem(regD dst, memoryRX src)%{
7682 match(Set dst (DivD dst (LoadD src)));
7683 // CC unchanged by DIV.
7684 ins_cost(ALU_MEMORY_COST);
7685 size(6);
7686 format %{ "DDB $dst,$src\t # doubleMemory" %}
7687 opcode(DDB_ZOPC);
7688 ins_encode(z_form_rt_memFP(dst, src));
7689 ins_pipe(pipe_class_dummy);
7690 %}
7691
7692 // ABS
7693
7694 // Absolute float single precision
7695 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7696 match(Set dst (AbsF src));
7697 effect(KILL cr);
7698 size(4);
7699 format %{ "LPEBR $dst,$src\t float" %}
7700 opcode(LPEBR_ZOPC);
7701 ins_encode(z_rreform(dst, src));
7702 ins_pipe(pipe_class_dummy);
7703 %}
7704
7705 // Absolute float double precision
7706 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7707 match(Set dst (AbsD src));
7708 effect(KILL cr);
7709 size(4);
7710 format %{ "LPDBR $dst,$src\t double" %}
7711 opcode(LPDBR_ZOPC);
7712 ins_encode(z_rreform(dst, src));
7713 ins_pipe(pipe_class_dummy);
7714 %}
7715
7716 // NEG(ABS)
7717
7718 // Negative absolute float single precision
7719 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7720 match(Set dst (NegF (AbsF src)));
7721 effect(KILL cr);
7722 size(4);
7723 format %{ "LNEBR $dst,$src\t float" %}
7724 opcode(LNEBR_ZOPC);
7725 ins_encode(z_rreform(dst, src));
7726 ins_pipe(pipe_class_dummy);
7727 %}
7728
7729 // Negative absolute float double precision
7730 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7731 match(Set dst (NegD (AbsD src)));
7732 effect(KILL cr);
7733 size(4);
7734 format %{ "LNDBR $dst,$src\t double" %}
7735 opcode(LNDBR_ZOPC);
7736 ins_encode(z_rreform(dst, src));
7737 ins_pipe(pipe_class_dummy);
7738 %}
7739
7740 // NEG
7741
7742 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7743 match(Set dst (NegF src));
7744 effect(KILL cr);
7745 size(4);
7746 format %{ "NegF $dst,$src\t float" %}
7747 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7748 ins_pipe(pipe_class_dummy);
7749 %}
7750
7751 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7752 match(Set dst (NegD src));
7753 effect(KILL cr);
7754 size(4);
7755 format %{ "NegD $dst,$src\t double" %}
7756 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7757 ins_pipe(pipe_class_dummy);
7758 %}
7759
7760 // SQRT
7761
7762 // Sqrt float precision
7763 instruct sqrtF_reg(regF dst, regF src) %{
7764 match(Set dst (SqrtF src));
7765 // CC remains unchanged.
7766 ins_cost(ALU_REG_COST);
7767 size(4);
7768 format %{ "SQEBR $dst,$src" %}
7769 opcode(SQEBR_ZOPC);
7770 ins_encode(z_rreform(dst, src));
7771 ins_pipe(pipe_class_dummy);
7772 %}
7773
7774 // Sqrt double precision
7775 instruct sqrtD_reg(regD dst, regD src) %{
7776 match(Set dst (SqrtD src));
7777 // CC remains unchanged.
7778 ins_cost(ALU_REG_COST);
7779 size(4);
7780 format %{ "SQDBR $dst,$src" %}
7781 opcode(SQDBR_ZOPC);
7782 ins_encode(z_rreform(dst, src));
7783 ins_pipe(pipe_class_dummy);
7784 %}
7785
7786 instruct sqrtF_mem(regF dst, memoryRX src) %{
7787 match(Set dst (SqrtF src));
7788 // CC remains unchanged.
7789 ins_cost(ALU_MEMORY_COST);
7790 size(6);
7791 format %{ "SQEB $dst,$src\t # floatMemory" %}
7792 opcode(SQEB_ZOPC);
7793 ins_encode(z_form_rt_memFP(dst, src));
7794 ins_pipe(pipe_class_dummy);
7795 %}
7796
7797 instruct sqrtD_mem(regD dst, memoryRX src) %{
7798 match(Set dst (SqrtD src));
7799 // CC remains unchanged.
7800 ins_cost(ALU_MEMORY_COST);
7801 // TODO: s390 port size(FIXED_SIZE);
7802 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7803 opcode(SQDB_ZOPC);
7804 ins_encode(z_form_rt_memFP(dst, src));
7805 ins_pipe(pipe_class_dummy);
7806 %}
7807
7808 //----------Logical Instructions-----------------------------------------------
7809
7810 // Register And
7811 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7812 match(Set dst (AndI dst src));
7813 effect(KILL cr);
7814 ins_cost(DEFAULT_COST_LOW);
7815 size(2);
7816 format %{ "NR $dst,$src\t # int" %}
7817 opcode(NR_ZOPC);
7818 ins_encode(z_rrform(dst, src));
7819 ins_pipe(pipe_class_dummy);
7820 %}
7821
7822 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7823 match(Set dst (AndI dst (LoadI src)));
7824 effect(KILL cr);
7825 ins_cost(MEMORY_REF_COST);
7826 // TODO: s390 port size(VARIABLE_SIZE);
7827 format %{ "N(Y) $dst, $src\t # int" %}
7828 opcode(NY_ZOPC, N_ZOPC);
7829 ins_encode(z_form_rt_mem_opt(dst, src));
7830 ins_pipe(pipe_class_dummy);
7831 %}
7832
7833 // Immediate And
7834 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7835 match(Set dst (AndI dst src));
7836 effect(KILL cr);
7837 ins_cost(DEFAULT_COST_HIGH);
7838 size(6);
7839 format %{ "NILF $dst,$src" %}
7840 opcode(NILF_ZOPC);
7841 ins_encode(z_rilform_unsigned(dst, src));
7842 ins_pipe(pipe_class_dummy);
7843 %}
7844
7845 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7846 match(Set dst (AndI dst src));
7847 effect(KILL cr);
7848 ins_cost(DEFAULT_COST);
7849 size(4);
7850 format %{ "NILH $dst,$src" %}
7851 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7852 ins_pipe(pipe_class_dummy);
7853 %}
7854
7855 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7856 match(Set dst (AndI dst src));
7857 effect(KILL cr);
7858 ins_cost(DEFAULT_COST);
7859 size(4);
7860 format %{ "NILL $dst,$src" %}
7861 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7862 ins_pipe(pipe_class_dummy);
7863 %}
7864
7865 // Register And Long
7866 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7867 match(Set dst (AndL dst src));
7868 effect(KILL cr);
7869 ins_cost(DEFAULT_COST);
7870 size(4);
7871 format %{ "NGR $dst,$src\t # long" %}
7872 opcode(NGR_ZOPC);
7873 ins_encode(z_rreform(dst, src));
7874 ins_pipe(pipe_class_dummy);
7875 %}
7876
7877 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7878 match(Set dst (AndL dst (LoadL src)));
7879 effect(KILL cr);
7880 ins_cost(MEMORY_REF_COST);
7881 size(Z_DISP3_SIZE);
7882 format %{ "NG $dst, $src\t # long" %}
7883 opcode(NG_ZOPC, NG_ZOPC);
7884 ins_encode(z_form_rt_mem_opt(dst, src));
7885 ins_pipe(pipe_class_dummy);
7886 %}
7887
7888 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7889 match(Set dst (AndL dst src));
7890 effect(KILL cr);
7891 ins_cost(DEFAULT_COST);
7892 size(4);
7893 format %{ "NILL $dst,$src\t # long" %}
7894 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7895 ins_pipe(pipe_class_dummy);
7896 %}
7897
7898 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7899 match(Set dst (AndL dst src));
7900 effect(KILL cr);
7901 ins_cost(DEFAULT_COST);
7902 size(4);
7903 format %{ "NILH $dst,$src\t # long" %}
7904 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7905 ins_pipe(pipe_class_dummy);
7906 %}
7907
7908 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7909 match(Set dst (AndL dst src));
7910 effect(KILL cr);
7911 ins_cost(DEFAULT_COST);
7912 size(4);
7913 format %{ "NIHL $dst,$src\t # long" %}
7914 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7915 ins_pipe(pipe_class_dummy);
7916 %}
7917
7918 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7919 match(Set dst (AndL dst src));
7920 effect(KILL cr);
7921 ins_cost(DEFAULT_COST);
7922 size(4);
7923 format %{ "NIHH $dst,$src\t # long" %}
7924 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7925 ins_pipe(pipe_class_dummy);
7926 %}
7927
7928 // OR
7929
7930 // Or Instructions
7931 // Register Or
7932 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7933 match(Set dst (OrI dst src));
7934 effect(KILL cr);
7935 size(2);
7936 format %{ "OR $dst,$src" %}
7937 opcode(OR_ZOPC);
7938 ins_encode(z_rrform(dst, src));
7939 ins_pipe(pipe_class_dummy);
7940 %}
7941
7942 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7943 match(Set dst (OrI dst (LoadI src)));
7944 effect(KILL cr);
7945 ins_cost(MEMORY_REF_COST);
7946 // TODO: s390 port size(VARIABLE_SIZE);
7947 format %{ "O(Y) $dst, $src\t # int" %}
7948 opcode(OY_ZOPC, O_ZOPC);
7949 ins_encode(z_form_rt_mem_opt(dst, src));
7950 ins_pipe(pipe_class_dummy);
7951 %}
7952
7953 // Immediate Or
7954 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7955 match(Set dst (OrI dst con));
7956 effect(KILL cr);
7957 size(4);
7958 format %{ "OILL $dst,$con" %}
7959 opcode(OILL_ZOPC);
7960 ins_encode(z_riform_unsigned(dst,con));
7961 ins_pipe(pipe_class_dummy);
7962 %}
7963
7964 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7965 match(Set dst (OrI dst con));
7966 effect(KILL cr);
7967 ins_cost(DEFAULT_COST_HIGH);
7968 size(6);
7969 format %{ "OILF $dst,$con" %}
7970 opcode(OILF_ZOPC);
7971 ins_encode(z_rilform_unsigned(dst,con));
7972 ins_pipe(pipe_class_dummy);
7973 %}
7974
7975 // Register Or Long
7976 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7977 match(Set dst (OrL dst src));
7978 effect(KILL cr);
7979 ins_cost(DEFAULT_COST);
7980 size(4);
7981 format %{ "OGR $dst,$src\t # long" %}
7982 opcode(OGR_ZOPC);
7983 ins_encode(z_rreform(dst, src));
7984 ins_pipe(pipe_class_dummy);
7985 %}
7986
7987 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7988 match(Set dst (OrL dst (LoadL src)));
7989 effect(KILL cr);
7990 ins_cost(MEMORY_REF_COST);
7991 size(Z_DISP3_SIZE);
7992 format %{ "OG $dst, $src\t # long" %}
7993 opcode(OG_ZOPC, OG_ZOPC);
7994 ins_encode(z_form_rt_mem_opt(dst, src));
7995 ins_pipe(pipe_class_dummy);
7996 %}
7997
7998 // Immediate Or long
7999 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
8000 match(Set dst (OrL dst con));
8001 effect(KILL cr);
8002 ins_cost(DEFAULT_COST);
8003 size(4);
8004 format %{ "OILL $dst,$con\t # long" %}
8005 opcode(OILL_ZOPC);
8006 ins_encode(z_riform_unsigned(dst,con));
8007 ins_pipe(pipe_class_dummy);
8008 %}
8009
8010 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
8011 match(Set dst (OrI dst con));
8012 effect(KILL cr);
8013 ins_cost(DEFAULT_COST_HIGH);
8014 // TODO: s390 port size(FIXED_SIZE);
8015 format %{ "OILF $dst,$con\t # long" %}
8016 opcode(OILF_ZOPC);
8017 ins_encode(z_rilform_unsigned(dst,con));
8018 ins_pipe(pipe_class_dummy);
8019 %}
8020
8021 // XOR
8022
8023 // Register Xor
8024 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8025 match(Set dst (XorI dst src));
8026 effect(KILL cr);
8027 size(2);
8028 format %{ "XR $dst,$src" %}
8029 opcode(XR_ZOPC);
8030 ins_encode(z_rrform(dst, src));
8031 ins_pipe(pipe_class_dummy);
8032 %}
8033
8034 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
8035 match(Set dst (XorI dst (LoadI src)));
8036 effect(KILL cr);
8037 ins_cost(MEMORY_REF_COST);
8038 // TODO: s390 port size(VARIABLE_SIZE);
8039 format %{ "X(Y) $dst, $src\t # int" %}
8040 opcode(XY_ZOPC, X_ZOPC);
8041 ins_encode(z_form_rt_mem_opt(dst, src));
8042 ins_pipe(pipe_class_dummy);
8043 %}
8044
8045 // Immediate Xor
8046 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
8047 match(Set dst (XorI dst src));
8048 effect(KILL cr);
8049 ins_cost(DEFAULT_COST_HIGH);
8050 size(6);
8051 format %{ "XILF $dst,$src" %}
8052 opcode(XILF_ZOPC);
8053 ins_encode(z_rilform_unsigned(dst, src));
8054 ins_pipe(pipe_class_dummy);
8055 %}
8056
8057 // Register Xor Long
8058 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
8059 match(Set dst (XorL dst src));
8060 effect(KILL cr);
8061 ins_cost(DEFAULT_COST);
8062 size(4);
8063 format %{ "XGR $dst,$src\t # long" %}
8064 opcode(XGR_ZOPC);
8065 ins_encode(z_rreform(dst, src));
8066 ins_pipe(pipe_class_dummy);
8067 %}
8068
8069 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
8070 match(Set dst (XorL dst (LoadL src)));
8071 effect(KILL cr);
8072 ins_cost(MEMORY_REF_COST);
8073 size(Z_DISP3_SIZE);
8074 format %{ "XG $dst, $src\t # long" %}
8075 opcode(XG_ZOPC, XG_ZOPC);
8076 ins_encode(z_form_rt_mem_opt(dst, src));
8077 ins_pipe(pipe_class_dummy);
8078 %}
8079
8080 // Immediate Xor Long
8081 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
8082 match(Set dst (XorL dst con));
8083 effect(KILL cr);
8084 ins_cost(DEFAULT_COST_HIGH);
8085 size(6);
8086 format %{ "XILF $dst,$con\t # long" %}
8087 opcode(XILF_ZOPC);
8088 ins_encode(z_rilform_unsigned(dst,con));
8089 ins_pipe(pipe_class_dummy);
8090 %}
8091
8092 //----------Convert to Boolean-------------------------------------------------
8093
8094 // Convert integer to boolean.
8095 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
8096 match(Set dst (Conv2B src));
8097 effect(KILL cr);
8098 ins_cost(3 * DEFAULT_COST);
8099 size(6);
8100 format %{ "convI2B $dst,$src" %}
8101 ins_encode %{
8102 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
8103 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
8104 %}
8105 ins_pipe(pipe_class_dummy);
8106 %}
8107
8108 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
8109 match(Set dst (Conv2B src));
8110 effect(KILL cr);
8111 ins_cost(3 * DEFAULT_COST);
8112 size(10);
8113 format %{ "convP2B $dst,$src" %}
8114 ins_encode %{
8115 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
8116 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
8117 %}
8118 ins_pipe(pipe_class_dummy);
8119 %}
8120
8121 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8122 match(Set dst (CmpLTMask dst src));
8123 effect(KILL cr);
8124 ins_cost(2 * DEFAULT_COST);
8125 size(18);
8126 format %{ "Set $dst CmpLTMask $dst,$src" %}
8127 ins_encode %{
8128 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
8129 __ z_lgfr(Z_R0_scratch, $src$$Register);
8130 __ z_lgfr($dst$$Register, $dst$$Register);
8131 __ z_sgr($dst$$Register, Z_R0_scratch);
8132 __ z_srag($dst$$Register, $dst$$Register, 63);
8133 %}
8134 ins_pipe(pipe_class_dummy);
8135 %}
8136
8137 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
8138 match(Set dst (CmpLTMask dst zero));
8139 effect(KILL cr);
8140 ins_cost(DEFAULT_COST);
8141 size(4);
8142 format %{ "Set $dst CmpLTMask $dst,$zero" %}
8143 ins_encode %{ __ z_sra($dst$$Register, 31); %}
8144 ins_pipe(pipe_class_dummy);
8145 %}
8146
8147
8148 //----------Arithmetic Conversion Instructions---------------------------------
8149 // The conversions operations are all Alpha sorted. Please keep it that way!
8150
8151 instruct convD2F_reg(regF dst, regD src) %{
8152 match(Set dst (ConvD2F src));
8153 // CC remains unchanged.
8154 size(4);
8155 format %{ "LEDBR $dst,$src" %}
8156 opcode(LEDBR_ZOPC);
8157 ins_encode(z_rreform(dst, src));
8158 ins_pipe(pipe_class_dummy);
8159 %}
8160
8161 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
8162 match(Set dst (ConvF2I src));
8163 effect(KILL cr);
8164 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8165 size(16);
8166 format %{ "convF2I $dst,$src" %}
8167 ins_encode %{
8168 Label done;
8169 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8170 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8171 __ z_brno(done); // Result is zero if unordered argument.
8172 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8173 __ bind(done);
8174 %}
8175 ins_pipe(pipe_class_dummy);
8176 %}
8177
8178 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
8179 match(Set dst (ConvD2I src));
8180 effect(KILL cr);
8181 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8182 size(16);
8183 format %{ "convD2I $dst,$src" %}
8184 ins_encode %{
8185 Label done;
8186 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8187 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8188 __ z_brno(done); // Result is zero if unordered argument.
8189 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8190 __ bind(done);
8191 %}
8192 ins_pipe(pipe_class_dummy);
8193 %}
8194
8195 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8196 match(Set dst (ConvF2L src));
8197 effect(KILL cr);
8198 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8199 size(16);
8200 format %{ "convF2L $dst,$src" %}
8201 ins_encode %{
8202 Label done;
8203 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8204 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8205 __ z_brno(done); // Result is zero if unordered argument.
8206 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8207 __ bind(done);
8208 %}
8209 ins_pipe(pipe_class_dummy);
8210 %}
8211
8212 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8213 match(Set dst (ConvD2L src));
8214 effect(KILL cr);
8215 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8216 size(16);
8217 format %{ "convD2L $dst,$src" %}
8218 ins_encode %{
8219 Label done;
8220 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8221 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8222 __ z_brno(done); // Result is zero if unordered argument.
8223 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8224 __ bind(done);
8225 %}
8226 ins_pipe(pipe_class_dummy);
8227 %}
8228
8229 instruct convF2D_reg(regD dst, regF src) %{
8230 match(Set dst (ConvF2D src));
8231 // CC remains unchanged.
8232 size(4);
8233 format %{ "LDEBR $dst,$src" %}
8234 opcode(LDEBR_ZOPC);
8235 ins_encode(z_rreform(dst, src));
8236 ins_pipe(pipe_class_dummy);
8237 %}
8238
8239 instruct convF2D_mem(regD dst, memoryRX src) %{
8240 match(Set dst (ConvF2D src));
8241 // CC remains unchanged.
8242 size(6);
8243 format %{ "LDEB $dst,$src" %}
8244 opcode(LDEB_ZOPC);
8245 ins_encode(z_form_rt_memFP(dst, src));
8246 ins_pipe(pipe_class_dummy);
8247 %}
8248
8249 instruct convI2D_reg(regD dst, iRegI src) %{
8250 match(Set dst (ConvI2D src));
8251 // CC remains unchanged.
8252 ins_cost(DEFAULT_COST);
8253 size(4);
8254 format %{ "CDFBR $dst,$src" %}
8255 opcode(CDFBR_ZOPC);
8256 ins_encode(z_rreform(dst, src));
8257 ins_pipe(pipe_class_dummy);
8258 %}
8259
8260 // Optimization that saves up to two memory operations for each conversion.
8261 instruct convI2F_ireg(regF dst, iRegI src) %{
8262 match(Set dst (ConvI2F src));
8263 // CC remains unchanged.
8264 ins_cost(DEFAULT_COST);
8265 size(4);
8266 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8267 opcode(CEFBR_ZOPC);
8268 ins_encode(z_rreform(dst, src));
8269 ins_pipe(pipe_class_dummy);
8270 %}
8271
8272 instruct convI2L_reg(iRegL dst, iRegI src) %{
8273 match(Set dst (ConvI2L src));
8274 size(4);
8275 format %{ "LGFR $dst,$src\t # int->long" %}
8276 opcode(LGFR_ZOPC);
8277 ins_encode(z_rreform(dst, src));
8278 ins_pipe(pipe_class_dummy);
8279 %}
8280
8281 // Zero-extend convert int to long.
8282 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8283 match(Set dst (AndL (ConvI2L src) mask));
8284 size(4);
8285 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8286 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8287 ins_pipe(pipe_class_dummy);
8288 %}
8289
8290 // Zero-extend convert int to long.
8291 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8292 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8293 // Uses load_const_optmized, so size can vary.
8294 // TODO: s390 port size(VARIABLE_SIZE);
8295 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8296 opcode(LLGF_ZOPC, LLGF_ZOPC);
8297 ins_encode(z_form_rt_mem_opt(dst, src));
8298 ins_pipe(pipe_class_dummy);
8299 %}
8300
8301 // Zero-extend long
8302 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8303 match(Set dst (AndL src mask));
8304 size(4);
8305 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8306 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8307 ins_pipe(pipe_class_dummy);
8308 %}
8309
8310 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8311 match(Set dst (RShiftI (LShiftI src amount) amount));
8312 size(4);
8313 format %{ "LHR $dst,$src\t short->int" %}
8314 opcode(LHR_ZOPC);
8315 ins_encode(z_rreform(dst, src));
8316 ins_pipe(pipe_class_dummy);
8317 %}
8318
8319 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8320 match(Set dst (RShiftI (LShiftI src amount) amount));
8321 size(4);
8322 format %{ "LBR $dst,$src\t byte->int" %}
8323 opcode(LBR_ZOPC);
8324 ins_encode(z_rreform(dst, src));
8325 ins_pipe(pipe_class_dummy);
8326 %}
8327
8328 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8329 match(Set dst (MoveF2I src));
8330 ins_cost(MEMORY_REF_COST);
8331 size(4);
8332 format %{ "L $dst,$src\t # MoveF2I" %}
8333 opcode(L_ZOPC);
8334 ins_encode(z_form_rt_mem(dst, src));
8335 ins_pipe(pipe_class_dummy);
8336 %}
8337
8338 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8339 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8340 match(Set dst (MoveI2F src));
8341 ins_cost(MEMORY_REF_COST);
8342 // TODO: s390 port size(FIXED_SIZE);
8343 format %{ "LE $dst,$src\t # MoveI2F" %}
8344 opcode(LE_ZOPC);
8345 ins_encode(z_form_rt_mem(dst, src));
8346 ins_pipe(pipe_class_dummy);
8347 %}
8348
8349 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8350 match(Set dst (MoveD2L src));
8351 ins_cost(MEMORY_REF_COST);
8352 size(6);
8353 format %{ "LG $src,$dst\t # MoveD2L" %}
8354 opcode(LG_ZOPC);
8355 ins_encode(z_form_rt_mem(dst, src));
8356 ins_pipe(pipe_class_dummy);
8357 %}
8358
8359 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8360 match(Set dst (MoveL2D src));
8361 ins_cost(MEMORY_REF_COST);
8362 size(4);
8363 format %{ "LD $dst,$src\t # MoveL2D" %}
8364 opcode(LD_ZOPC);
8365 ins_encode(z_form_rt_mem(dst, src));
8366 ins_pipe(pipe_class_dummy);
8367 %}
8368
8369 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8370 match(Set dst (MoveI2F src));
8371 ins_cost(MEMORY_REF_COST);
8372 size(4);
8373 format %{ "ST $src,$dst\t # MoveI2F" %}
8374 opcode(ST_ZOPC);
8375 ins_encode(z_form_rt_mem(src, dst));
8376 ins_pipe(pipe_class_dummy);
8377 %}
8378
8379 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8380 match(Set dst (MoveD2L src));
8381 effect(DEF dst, USE src);
8382 ins_cost(MEMORY_REF_COST);
8383 size(4);
8384 format %{ "STD $src,$dst\t # MoveD2L" %}
8385 opcode(STD_ZOPC);
8386 ins_encode(z_form_rt_mem(src,dst));
8387 ins_pipe(pipe_class_dummy);
8388 %}
8389
8390 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8391 match(Set dst (MoveL2D src));
8392 ins_cost(MEMORY_REF_COST);
8393 size(6);
8394 format %{ "STG $src,$dst\t # MoveL2D" %}
8395 opcode(STG_ZOPC);
8396 ins_encode(z_form_rt_mem(src,dst));
8397 ins_pipe(pipe_class_dummy);
8398 %}
8399
8400 instruct convL2F_reg(regF dst, iRegL src) %{
8401 match(Set dst (ConvL2F src));
8402 // CC remains unchanged.
8403 ins_cost(DEFAULT_COST);
8404 size(4);
8405 format %{ "CEGBR $dst,$src" %}
8406 opcode(CEGBR_ZOPC);
8407 ins_encode(z_rreform(dst, src));
8408 ins_pipe(pipe_class_dummy);
8409 %}
8410
8411 instruct convL2D_reg(regD dst, iRegL src) %{
8412 match(Set dst (ConvL2D src));
8413 // CC remains unchanged.
8414 ins_cost(DEFAULT_COST);
8415 size(4);
8416 format %{ "CDGBR $dst,$src" %}
8417 opcode(CDGBR_ZOPC);
8418 ins_encode(z_rreform(dst, src));
8419 ins_pipe(pipe_class_dummy);
8420 %}
8421
8422 instruct convL2I_reg(iRegI dst, iRegL src) %{
8423 match(Set dst (ConvL2I src));
8424 // TODO: s390 port size(VARIABLE_SIZE);
8425 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8426 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8427 ins_pipe(pipe_class_dummy);
8428 %}
8429
8430 // Register Shift Right Immediate
8431 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8432 match(Set dst (ConvL2I (RShiftL src cnt)));
8433 effect(KILL cr);
8434 size(6);
8435 format %{ "SRAG $dst,$src,$cnt" %}
8436 opcode(SRAG_ZOPC);
8437 ins_encode(z_rsyform_const(dst, src, cnt));
8438 ins_pipe(pipe_class_dummy);
8439 %}
8440
8441 //----------TRAP based zero checks and range checks----------------------------
8442
8443 // SIGTRAP based implicit range checks in compiled code.
8444 // A range check in the ideal world has one of the following shapes:
8445 // - (If le (CmpU length index)), (IfTrue throw exception)
8446 // - (If lt (CmpU index length)), (IfFalse throw exception)
8447 //
8448 // Match range check 'If le (CmpU length index)'
8449 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8450 match(If cmp (CmpU length index));
8451 effect(USE labl);
8452 predicate(TrapBasedRangeChecks &&
8453 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8454 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8455 Matcher::branches_to_uncommon_trap(_leaf));
8456 ins_cost(1);
8457 // TODO: s390 port size(FIXED_SIZE);
8458
8459 ins_is_TrapBasedCheckNode(true);
8460
8461 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8462 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8463 ins_pipe(pipe_class_trap);
8464 %}
8465
8466 // Match range check 'If lt (CmpU index length)'
8467 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8468 match(If cmp (CmpU index length));
8469 effect(USE labl, KILL cr);
8470 predicate(TrapBasedRangeChecks &&
8471 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8472 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8473 Matcher::branches_to_uncommon_trap(_leaf));
8474 ins_cost(1);
8475 // TODO: s390 port size(FIXED_SIZE);
8476
8477 ins_is_TrapBasedCheckNode(true);
8478
8479 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8480 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8481 ins_pipe(pipe_class_trap);
8482 %}
8483
8484 // Match range check 'If lt (CmpU index length)'
8485 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8486 match(If cmp (CmpU index length));
8487 effect(USE labl);
8488 predicate(TrapBasedRangeChecks &&
8489 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8490 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8491 Matcher::branches_to_uncommon_trap(_leaf));
8492 ins_cost(1);
8493 // TODO: s390 port size(FIXED_SIZE);
8494
8495 ins_is_TrapBasedCheckNode(true);
8496
8497 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8498 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8499 ins_pipe(pipe_class_trap);
8500 %}
8501
8502 // Implicit zero checks (more implicit null checks).
8503 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8504 match(If cmp (CmpP value zero));
8505 effect(USE labl);
8506 predicate(TrapBasedNullChecks &&
8507 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8508 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8509 Matcher::branches_to_uncommon_trap(_leaf));
8510 size(6);
8511
8512 ins_is_TrapBasedCheckNode(true);
8513
8514 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8515 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8516 ins_pipe(pipe_class_trap);
8517 %}
8518
8519 // Implicit zero checks (more implicit null checks).
8520 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8521 match(If cmp (CmpN value zero));
8522 effect(USE labl);
8523 predicate(TrapBasedNullChecks &&
8524 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8525 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8526 Matcher::branches_to_uncommon_trap(_leaf));
8527 size(6);
8528
8529 ins_is_TrapBasedCheckNode(true);
8530
8531 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8532 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8533 ins_pipe(pipe_class_trap);
8534 %}
8535
8536 //----------Compare instructions-----------------------------------------------
8537
8538 // INT signed
8539
8540 // Compare Integers
8541 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8542 match(Set cr (CmpI op1 op2));
8543 size(2);
8544 format %{ "CR $op1,$op2" %}
8545 opcode(CR_ZOPC);
8546 ins_encode(z_rrform(op1, op2));
8547 ins_pipe(pipe_class_dummy);
8548 %}
8549
8550 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8551 match(Set cr (CmpI op1 op2));
8552 size(6);
8553 format %{ "CFI $op1,$op2" %}
8554 opcode(CFI_ZOPC);
8555 ins_encode(z_rilform_signed(op1, op2));
8556 ins_pipe(pipe_class_dummy);
8557 %}
8558
8559 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8560 match(Set cr (CmpI op1 op2));
8561 size(4);
8562 format %{ "CHI $op1,$op2" %}
8563 opcode(CHI_ZOPC);
8564 ins_encode(z_riform_signed(op1, op2));
8565 ins_pipe(pipe_class_dummy);
8566 %}
8567
8568 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8569 match(Set cr (CmpI op1 zero));
8570 ins_cost(DEFAULT_COST_LOW);
8571 size(2);
8572 format %{ "LTR $op1,$op1" %}
8573 opcode(LTR_ZOPC);
8574 ins_encode(z_rrform(op1, op1));
8575 ins_pipe(pipe_class_dummy);
8576 %}
8577
8578 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8579 match(Set cr (CmpI op1 (LoadI op2)));
8580 ins_cost(MEMORY_REF_COST);
8581 // TODO: s390 port size(VARIABLE_SIZE);
8582 format %{ "C(Y) $op1, $op2\t # int" %}
8583 opcode(CY_ZOPC, C_ZOPC);
8584 ins_encode(z_form_rt_mem_opt(op1, op2));
8585 ins_pipe(pipe_class_dummy);
8586 %}
8587
8588 // INT unsigned
8589
8590 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8591 match(Set cr (CmpU op1 op2));
8592 size(2);
8593 format %{ "CLR $op1,$op2\t # unsigned" %}
8594 opcode(CLR_ZOPC);
8595 ins_encode(z_rrform(op1, op2));
8596 ins_pipe(pipe_class_dummy);
8597 %}
8598
8599 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8600 match(Set cr (CmpU op1 op2));
8601 size(6);
8602 format %{ "CLFI $op1,$op2\t # unsigned" %}
8603 opcode(CLFI_ZOPC);
8604 ins_encode(z_rilform_unsigned(op1, op2));
8605 ins_pipe(pipe_class_dummy);
8606 %}
8607
8608 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8609 match(Set cr (CmpU op1 (LoadI op2)));
8610 ins_cost(MEMORY_REF_COST);
8611 // TODO: s390 port size(VARIABLE_SIZE);
8612 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8613 opcode(CLY_ZOPC, CL_ZOPC);
8614 ins_encode(z_form_rt_mem_opt(op1, op2));
8615 ins_pipe(pipe_class_dummy);
8616 %}
8617
8618 // LONG signed
8619
8620 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8621 match(Set cr (CmpL op1 op2));
8622 size(4);
8623 format %{ "CGR $op1,$op2\t # long" %}
8624 opcode(CGR_ZOPC);
8625 ins_encode(z_rreform(op1, op2));
8626 ins_pipe(pipe_class_dummy);
8627 %}
8628
8629 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8630 match(Set cr (CmpL op1 (ConvI2L op2)));
8631 size(4);
8632 format %{ "CGFR $op1,$op2\t # long/int" %}
8633 opcode(CGFR_ZOPC);
8634 ins_encode(z_rreform(op1, op2));
8635 ins_pipe(pipe_class_dummy);
8636 %}
8637
8638 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8639 match(Set cr (CmpL op1 con));
8640 size(6);
8641 format %{ "CGFI $op1,$con" %}
8642 opcode(CGFI_ZOPC);
8643 ins_encode(z_rilform_signed(op1, con));
8644 ins_pipe(pipe_class_dummy);
8645 %}
8646
8647 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8648 match(Set cr (CmpL op1 con));
8649 size(4);
8650 format %{ "CGHI $op1,$con" %}
8651 opcode(CGHI_ZOPC);
8652 ins_encode(z_riform_signed(op1, con));
8653 ins_pipe(pipe_class_dummy);
8654 %}
8655
8656 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8657 match(Set cr (CmpL op1 con));
8658 ins_cost(DEFAULT_COST_LOW);
8659 size(4);
8660 format %{ "LTGR $op1,$op1" %}
8661 opcode(LTGR_ZOPC);
8662 ins_encode(z_rreform(op1, op1));
8663 ins_pipe(pipe_class_dummy);
8664 %}
8665
8666 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8667 match(Set cr (CmpL (ConvI2L op1) con));
8668 ins_cost(DEFAULT_COST_LOW);
8669 size(4);
8670 format %{ "LTGFR $op1,$op1" %}
8671 opcode(LTGFR_ZOPC);
8672 ins_encode(z_rreform(op1, op1));
8673 ins_pipe(pipe_class_dummy);
8674 %}
8675
8676 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8677 match(Set cr (CmpL dst (LoadL src)));
8678 ins_cost(MEMORY_REF_COST);
8679 size(Z_DISP3_SIZE);
8680 format %{ "CG $dst, $src\t # long" %}
8681 opcode(CG_ZOPC, CG_ZOPC);
8682 ins_encode(z_form_rt_mem_opt(dst, src));
8683 ins_pipe(pipe_class_dummy);
8684 %}
8685
8686 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8687 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8688 ins_cost(MEMORY_REF_COST);
8689 size(Z_DISP3_SIZE);
8690 format %{ "CGF $dst, $src\t # long/int" %}
8691 opcode(CGF_ZOPC, CGF_ZOPC);
8692 ins_encode(z_form_rt_mem_opt(dst, src));
8693 ins_pipe(pipe_class_dummy);
8694 %}
8695
8696 // LONG unsigned
8697 // Added CmpUL for LoopPredicate.
8698 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8699 match(Set cr (CmpUL op1 op2));
8700 size(4);
8701 format %{ "CLGR $op1,$op2\t # long" %}
8702 opcode(CLGR_ZOPC);
8703 ins_encode(z_rreform(op1, op2));
8704 ins_pipe(pipe_class_dummy);
8705 %}
8706
8707 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8708 match(Set cr (CmpUL op1 con));
8709 size(6);
8710 format %{ "CLGFI $op1,$con" %}
8711 opcode(CLGFI_ZOPC);
8712 ins_encode(z_rilform_unsigned(op1, con));
8713 ins_pipe(pipe_class_dummy);
8714 %}
8715
8716 // PTR unsigned
8717
8718 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8719 match(Set cr (CmpP op1 op2));
8720 size(4);
8721 format %{ "CLGR $op1,$op2\t # ptr" %}
8722 opcode(CLGR_ZOPC);
8723 ins_encode(z_rreform(op1, op2));
8724 ins_pipe(pipe_class_dummy);
8725 %}
8726
8727 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8728 match(Set cr (CmpP op1 op2));
8729 ins_cost(DEFAULT_COST_LOW);
8730 size(4);
8731 format %{ "LTGR $op1, $op1\t # ptr" %}
8732 opcode(LTGR_ZOPC);
8733 ins_encode(z_rreform(op1, op1));
8734 ins_pipe(pipe_class_dummy);
8735 %}
8736
8737 // Don't use LTGFR which performs sign extend.
8738 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8739 match(Set cr (CmpP (DecodeN op1) op2));
8740 predicate(CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
8741 ins_cost(DEFAULT_COST_LOW);
8742 size(2);
8743 format %{ "LTR $op1, $op1\t # ptr" %}
8744 opcode(LTR_ZOPC);
8745 ins_encode(z_rrform(op1, op1));
8746 ins_pipe(pipe_class_dummy);
8747 %}
8748
8749 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8750 match(Set cr (CmpP dst (LoadP src)));
8751 ins_cost(MEMORY_REF_COST);
8752 size(Z_DISP3_SIZE);
8753 format %{ "CLG $dst, $src\t # ptr" %}
8754 opcode(CLG_ZOPC, CLG_ZOPC);
8755 ins_encode(z_form_rt_mem_opt(dst, src));
8756 ins_pipe(pipe_class_dummy);
8757 %}
8758
8759 //----------Max and Min--------------------------------------------------------
8760
8761 // Max Register with Register
8762 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8763 match(Set dst (MinI src1 src2));
8764 effect(KILL cr);
8765 predicate(VM_Version::has_LoadStoreConditional());
8766 ins_cost(3 * DEFAULT_COST);
8767 // TODO: s390 port size(VARIABLE_SIZE);
8768 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8769 ins_encode %{
8770 Register Rdst = $dst$$Register;
8771 Register Rsrc1 = $src1$$Register;
8772 Register Rsrc2 = $src2$$Register;
8773
8774 if (Rsrc1 == Rsrc2) {
8775 if (Rdst != Rsrc1) {
8776 __ z_lgfr(Rdst, Rsrc1);
8777 }
8778 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8779 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8780 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8781 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8782 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8783 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8784 } else {
8785 // Rdst is disjoint from operands, move in either case.
8786 __ z_cr(Rsrc1, Rsrc2);
8787 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8788 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8789 }
8790 %}
8791 ins_pipe(pipe_class_dummy);
8792 %}
8793
8794 // Min Register with Register.
8795 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8796 match(Set dst (MinI src1 src2));
8797 effect(KILL cr);
8798 predicate(VM_Version::has_CompareBranch());
8799 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8800 // TODO: s390 port size(VARIABLE_SIZE);
8801 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8802 ins_encode %{
8803 Register Rdst = $dst$$Register;
8804 Register Rsrc1 = $src1$$Register;
8805 Register Rsrc2 = $src2$$Register;
8806 Label done;
8807
8808 if (Rsrc1 == Rsrc2) {
8809 if (Rdst != Rsrc1) {
8810 __ z_lgfr(Rdst, Rsrc1);
8811 }
8812 } else if (Rdst == Rsrc1) {
8813 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8814 __ z_lgfr(Rdst, Rsrc2);
8815 } else if (Rdst == Rsrc2) {
8816 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8817 __ z_lgfr(Rdst, Rsrc1);
8818 } else {
8819 __ z_lgfr(Rdst, Rsrc1);
8820 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8821 __ z_lgfr(Rdst, Rsrc2);
8822 }
8823 __ bind(done);
8824 %}
8825 ins_pipe(pipe_class_dummy);
8826 %}
8827
8828 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8829 match(Set dst (MinI src1 src2));
8830 effect(KILL cr);
8831 predicate(!VM_Version::has_CompareBranch());
8832 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8833 // TODO: s390 port size(VARIABLE_SIZE);
8834 format %{ "MinI $dst $src1,$src2\t MinI" %}
8835 ins_encode %{
8836 Register Rdst = $dst$$Register;
8837 Register Rsrc1 = $src1$$Register;
8838 Register Rsrc2 = $src2$$Register;
8839 Label done;
8840
8841 if (Rsrc1 == Rsrc2) {
8842 if (Rdst != Rsrc1) {
8843 __ z_lgfr(Rdst, Rsrc1);
8844 }
8845 } else if (Rdst == Rsrc1) {
8846 __ z_cr(Rsrc1, Rsrc2);
8847 __ z_brl(done);
8848 __ z_lgfr(Rdst, Rsrc2);
8849 } else if (Rdst == Rsrc2) {
8850 __ z_cr(Rsrc2, Rsrc1);
8851 __ z_brl(done);
8852 __ z_lgfr(Rdst, Rsrc1);
8853 } else {
8854 __ z_lgfr(Rdst, Rsrc1);
8855 __ z_cr(Rsrc1, Rsrc2);
8856 __ z_brl(done);
8857 __ z_lgfr(Rdst, Rsrc2);
8858 }
8859 __ bind(done);
8860 %}
8861 ins_pipe(pipe_class_dummy);
8862 %}
8863
8864 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8865 match(Set dst (MinI src1 src2));
8866 effect(KILL cr);
8867 predicate(VM_Version::has_LoadStoreConditional());
8868 ins_cost(3 * DEFAULT_COST);
8869 // TODO: s390 port size(VARIABLE_SIZE);
8870 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8871 ins_encode %{
8872 Register Rdst = $dst$$Register;
8873 Register Rsrc1 = $src1$$Register;
8874 int Isrc2 = $src2$$constant;
8875
8876 if (Rdst == Rsrc1) {
8877 __ load_const_optimized(Z_R0_scratch, Isrc2);
8878 __ z_cfi(Rsrc1, Isrc2);
8879 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8880 } else {
8881 __ load_const_optimized(Rdst, Isrc2);
8882 __ z_cfi(Rsrc1, Isrc2);
8883 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8884 }
8885 %}
8886 ins_pipe(pipe_class_dummy);
8887 %}
8888
8889 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8890 match(Set dst (MinI src1 src2));
8891 effect(KILL cr);
8892 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8893 // TODO: s390 port size(VARIABLE_SIZE);
8894 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8895 ins_encode %{
8896 Label done;
8897 if ($dst$$Register != $src1$$Register) {
8898 __ z_lgfr($dst$$Register, $src1$$Register);
8899 }
8900 __ z_cfi($src1$$Register, $src2$$constant);
8901 __ z_brl(done);
8902 __ z_lgfi($dst$$Register, $src2$$constant);
8903 __ bind(done);
8904 %}
8905 ins_pipe(pipe_class_dummy);
8906 %}
8907
8908 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8909 match(Set dst (MinI src1 src2));
8910 effect(KILL cr);
8911 predicate(VM_Version::has_LoadStoreConditional());
8912 ins_cost(3 * DEFAULT_COST);
8913 // TODO: s390 port size(VARIABLE_SIZE);
8914 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8915 ins_encode %{
8916 Register Rdst = $dst$$Register;
8917 Register Rsrc1 = $src1$$Register;
8918 int Isrc2 = $src2$$constant;
8919
8920 if (Rdst == Rsrc1) {
8921 __ load_const_optimized(Z_R0_scratch, Isrc2);
8922 __ z_chi(Rsrc1, Isrc2);
8923 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8924 } else {
8925 __ load_const_optimized(Rdst, Isrc2);
8926 __ z_chi(Rsrc1, Isrc2);
8927 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8928 }
8929 %}
8930 ins_pipe(pipe_class_dummy);
8931 %}
8932
8933 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8934 match(Set dst (MinI src1 src2));
8935 effect(KILL cr);
8936 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8937 // TODO: s390 port size(VARIABLE_SIZE);
8938 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8939 ins_encode %{
8940 Label done;
8941 if ($dst$$Register != $src1$$Register) {
8942 __ z_lgfr($dst$$Register, $src1$$Register);
8943 }
8944 __ z_chi($src1$$Register, $src2$$constant);
8945 __ z_brl(done);
8946 __ z_lghi($dst$$Register, $src2$$constant);
8947 __ bind(done);
8948 %}
8949 ins_pipe(pipe_class_dummy);
8950 %}
8951
8952 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8953 match(Set dst (MinI src1 src2));
8954 effect(KILL cr);
8955 predicate(VM_Version::has_CompareBranch());
8956 ins_cost(DEFAULT_COST + BRANCH_COST);
8957 // TODO: s390 port size(VARIABLE_SIZE);
8958 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8959 ins_encode %{
8960 Label done;
8961 if ($dst$$Register != $src1$$Register) {
8962 __ z_lgfr($dst$$Register, $src1$$Register);
8963 }
8964 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8965 __ z_lghi($dst$$Register, $src2$$constant);
8966 __ bind(done);
8967 %}
8968 ins_pipe(pipe_class_dummy);
8969 %}
8970
8971 // Max Register with Register
8972 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8973 match(Set dst (MaxI src1 src2));
8974 effect(KILL cr);
8975 predicate(VM_Version::has_LoadStoreConditional());
8976 ins_cost(3 * DEFAULT_COST);
8977 // TODO: s390 port size(VARIABLE_SIZE);
8978 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8979 ins_encode %{
8980 Register Rdst = $dst$$Register;
8981 Register Rsrc1 = $src1$$Register;
8982 Register Rsrc2 = $src2$$Register;
8983
8984 if (Rsrc1 == Rsrc2) {
8985 if (Rdst != Rsrc1) {
8986 __ z_lgfr(Rdst, Rsrc1);
8987 }
8988 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8989 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
8990 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8991 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8992 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
8993 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8994 } else { // Rdst is disjoint from operands, move in either case.
8995 __ z_cr(Rsrc1, Rsrc2);
8996 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8997 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8998 }
8999 %}
9000 ins_pipe(pipe_class_dummy);
9001 %}
9002
9003 // Max Register with Register
9004 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9005 match(Set dst (MaxI src1 src2));
9006 effect(KILL cr);
9007 predicate(VM_Version::has_CompareBranch());
9008 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9009 // TODO: s390 port size(VARIABLE_SIZE);
9010 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
9011 ins_encode %{
9012 Register Rdst = $dst$$Register;
9013 Register Rsrc1 = $src1$$Register;
9014 Register Rsrc2 = $src2$$Register;
9015 Label done;
9016
9017 if (Rsrc1 == Rsrc2) {
9018 if (Rdst != Rsrc1) {
9019 __ z_lgfr(Rdst, Rsrc1);
9020 }
9021 } else if (Rdst == Rsrc1) {
9022 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9023 __ z_lgfr(Rdst, Rsrc2);
9024 } else if (Rdst == Rsrc2) {
9025 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
9026 __ z_lgfr(Rdst, Rsrc1);
9027 } else {
9028 __ z_lgfr(Rdst, Rsrc1);
9029 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9030 __ z_lgfr(Rdst, Rsrc2);
9031 }
9032 __ bind(done);
9033 %}
9034 ins_pipe(pipe_class_dummy);
9035 %}
9036
9037 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9038 match(Set dst (MaxI src1 src2));
9039 effect(KILL cr);
9040 predicate(!VM_Version::has_CompareBranch());
9041 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
9042 // TODO: s390 port size(VARIABLE_SIZE);
9043 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
9044 ins_encode %{
9045 Register Rdst = $dst$$Register;
9046 Register Rsrc1 = $src1$$Register;
9047 Register Rsrc2 = $src2$$Register;
9048 Label done;
9049
9050 if (Rsrc1 == Rsrc2) {
9051 if (Rdst != Rsrc1) {
9052 __ z_lgfr(Rdst, Rsrc1);
9053 }
9054 } else if (Rdst == Rsrc1) {
9055 __ z_cr(Rsrc1, Rsrc2);
9056 __ z_brh(done);
9057 __ z_lgfr(Rdst, Rsrc2);
9058 } else if (Rdst == Rsrc2) {
9059 __ z_cr(Rsrc2, Rsrc1);
9060 __ z_brh(done);
9061 __ z_lgfr(Rdst, Rsrc1);
9062 } else {
9063 __ z_lgfr(Rdst, Rsrc1);
9064 __ z_cr(Rsrc1, Rsrc2);
9065 __ z_brh(done);
9066 __ z_lgfr(Rdst, Rsrc2);
9067 }
9068
9069 __ bind(done);
9070 %}
9071
9072 ins_pipe(pipe_class_dummy);
9073 %}
9074
9075 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9076 match(Set dst (MaxI src1 src2));
9077 effect(KILL cr);
9078 predicate(VM_Version::has_LoadStoreConditional());
9079 ins_cost(3 * DEFAULT_COST);
9080 // TODO: s390 port size(VARIABLE_SIZE);
9081 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
9082 ins_encode %{
9083 Register Rdst = $dst$$Register;
9084 Register Rsrc1 = $src1$$Register;
9085 int Isrc2 = $src2$$constant;
9086
9087 if (Rdst == Rsrc1) {
9088 __ load_const_optimized(Z_R0_scratch, Isrc2);
9089 __ z_cfi(Rsrc1, Isrc2);
9090 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9091 } else {
9092 __ load_const_optimized(Rdst, Isrc2);
9093 __ z_cfi(Rsrc1, Isrc2);
9094 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9095 }
9096 %}
9097 ins_pipe(pipe_class_dummy);
9098 %}
9099
9100 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9101 match(Set dst (MaxI src1 src2));
9102 effect(KILL cr);
9103 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9104 // TODO: s390 port size(VARIABLE_SIZE);
9105 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
9106 ins_encode %{
9107 Label done;
9108 if ($dst$$Register != $src1$$Register) {
9109 __ z_lgfr($dst$$Register, $src1$$Register);
9110 }
9111 __ z_cfi($src1$$Register, $src2$$constant);
9112 __ z_brh(done);
9113 __ z_lgfi($dst$$Register, $src2$$constant);
9114 __ bind(done);
9115 %}
9116 ins_pipe(pipe_class_dummy);
9117 %}
9118
9119 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9120 match(Set dst (MaxI src1 src2));
9121 effect(KILL cr);
9122 predicate(VM_Version::has_LoadStoreConditional());
9123 ins_cost(3 * DEFAULT_COST);
9124 // TODO: s390 port size(VARIABLE_SIZE);
9125 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
9126 ins_encode %{
9127 Register Rdst = $dst$$Register;
9128 Register Rsrc1 = $src1$$Register;
9129 int Isrc2 = $src2$$constant;
9130 if (Rdst == Rsrc1) {
9131 __ load_const_optimized(Z_R0_scratch, Isrc2);
9132 __ z_chi(Rsrc1, Isrc2);
9133 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9134 } else {
9135 __ load_const_optimized(Rdst, Isrc2);
9136 __ z_chi(Rsrc1, Isrc2);
9137 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9138 }
9139 %}
9140 ins_pipe(pipe_class_dummy);
9141 %}
9142
9143 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9144 match(Set dst (MaxI src1 src2));
9145 effect(KILL cr);
9146 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9147 // TODO: s390 port size(VARIABLE_SIZE);
9148 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
9149 ins_encode %{
9150 Label done;
9151 if ($dst$$Register != $src1$$Register) {
9152 __ z_lgfr($dst$$Register, $src1$$Register);
9153 }
9154 __ z_chi($src1$$Register, $src2$$constant);
9155 __ z_brh(done);
9156 __ z_lghi($dst$$Register, $src2$$constant);
9157 __ bind(done);
9158 %}
9159 ins_pipe(pipe_class_dummy);
9160 %}
9161
9162 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
9163 match(Set dst (MaxI src1 src2));
9164 effect(KILL cr);
9165 predicate(VM_Version::has_CompareBranch());
9166 ins_cost(DEFAULT_COST + BRANCH_COST);
9167 // TODO: s390 port size(VARIABLE_SIZE);
9168 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
9169 ins_encode %{
9170 Label done;
9171 if ($dst$$Register != $src1$$Register) {
9172 __ z_lgfr($dst$$Register, $src1$$Register);
9173 }
9174 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
9175 __ z_lghi($dst$$Register, $src2$$constant);
9176 __ bind(done);
9177 %}
9178 ins_pipe(pipe_class_dummy);
9179 %}
9180
9181 //----------Abs---------------------------------------------------------------
9182
9183 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
9184 match(Set dst (AbsI src));
9185 effect(KILL cr);
9186 ins_cost(DEFAULT_COST_LOW);
9187 // TODO: s390 port size(FIXED_SIZE);
9188 format %{ "LPR $dst, $src" %}
9189 opcode(LPR_ZOPC);
9190 ins_encode(z_rrform(dst, src));
9191 ins_pipe(pipe_class_dummy);
9192 %}
9193
9194 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
9195 match(Set dst (AbsL src));
9196 effect(KILL cr);
9197 ins_cost(DEFAULT_COST_LOW);
9198 // TODO: s390 port size(FIXED_SIZE);
9199 format %{ "LPGR $dst, $src" %}
9200 opcode(LPGR_ZOPC);
9201 ins_encode(z_rreform(dst, src));
9202 ins_pipe(pipe_class_dummy);
9203 %}
9204
9205 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9206 match(Set dst (SubI zero (AbsI src)));
9207 effect(KILL cr);
9208 ins_cost(DEFAULT_COST_LOW);
9209 // TODO: s390 port size(FIXED_SIZE);
9210 format %{ "LNR $dst, $src" %}
9211 opcode(LNR_ZOPC);
9212 ins_encode(z_rrform(dst, src));
9213 ins_pipe(pipe_class_dummy);
9214 %}
9215
9216 //----------Float Compares----------------------------------------------------
9217
9218 // Compare floating, generate condition code.
9219 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9220 match(Set cr (CmpF src1 src2));
9221 ins_cost(ALU_REG_COST);
9222 size(4);
9223 format %{ "FCMPcc $src1,$src2\t # float" %}
9224 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9225 ins_pipe(pipe_class_dummy);
9226 %}
9227
9228 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9229 match(Set cr (CmpD src1 src2));
9230 ins_cost(ALU_REG_COST);
9231 size(4);
9232 format %{ "FCMPcc $src1,$src2 \t # double" %}
9233 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9234 ins_pipe(pipe_class_dummy);
9235 %}
9236
9237 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9238 match(Set cr (CmpF src1 (LoadF src2)));
9239 ins_cost(ALU_MEMORY_COST);
9240 size(6);
9241 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9242 opcode(CEB_ZOPC);
9243 ins_encode(z_form_rt_memFP(src1, src2));
9244 ins_pipe(pipe_class_dummy);
9245 %}
9246
9247 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9248 match(Set cr (CmpD src1 (LoadD src2)));
9249 ins_cost(ALU_MEMORY_COST);
9250 size(6);
9251 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9252 opcode(CDB_ZOPC);
9253 ins_encode(z_form_rt_memFP(src1, src2));
9254 ins_pipe(pipe_class_dummy);
9255 %}
9256
9257 // Compare floating, generate condition code
9258 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9259 match(Set cr (CmpF src1 src2));
9260 ins_cost(DEFAULT_COST);
9261 size(4);
9262 format %{ "LTEBR $src1,$src1\t # float" %}
9263 opcode(LTEBR_ZOPC);
9264 ins_encode(z_rreform(src1, src1));
9265 ins_pipe(pipe_class_dummy);
9266 %}
9267
9268 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9269 match(Set cr (CmpD src1 src2));
9270 ins_cost(DEFAULT_COST);
9271 size(4);
9272 format %{ "LTDBR $src1,$src1 \t # double" %}
9273 opcode(LTDBR_ZOPC);
9274 ins_encode(z_rreform(src1, src1));
9275 ins_pipe(pipe_class_dummy);
9276 %}
9277
9278 // Compare floating, generate -1,0,1
9279 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9280 match(Set dst (CmpF3 src1 src2));
9281 effect(KILL cr);
9282 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9283 size(24);
9284 format %{ "CmpF3 $dst,$src1,$src2" %}
9285 ins_encode %{
9286 // compare registers
9287 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9288 // Convert condition code into -1,0,1, where
9289 // -1 means unordered or less
9290 // 0 means equal
9291 // 1 means greater.
9292 if (VM_Version::has_LoadStoreConditional()) {
9293 Register one = Z_R0_scratch;
9294 Register minus_one = Z_R1_scratch;
9295 __ z_lghi(minus_one, -1);
9296 __ z_lghi(one, 1);
9297 __ z_lghi( $dst$$Register, 0);
9298 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9299 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9300 } else {
9301 Label done;
9302 __ clear_reg($dst$$Register, true, false);
9303 __ z_bre(done);
9304 __ z_lhi($dst$$Register, 1);
9305 __ z_brh(done);
9306 __ z_lhi($dst$$Register, -1);
9307 __ bind(done);
9308 }
9309 %}
9310 ins_pipe(pipe_class_dummy);
9311 %}
9312
9313 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9314 match(Set dst (CmpD3 src1 src2));
9315 effect(KILL cr);
9316 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9317 size(24);
9318 format %{ "CmpD3 $dst,$src1,$src2" %}
9319 ins_encode %{
9320 // compare registers
9321 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9322 // Convert condition code into -1,0,1, where
9323 // -1 means unordered or less
9324 // 0 means equal
9325 // 1 means greater.
9326 if (VM_Version::has_LoadStoreConditional()) {
9327 Register one = Z_R0_scratch;
9328 Register minus_one = Z_R1_scratch;
9329 __ z_lghi(minus_one, -1);
9330 __ z_lghi(one, 1);
9331 __ z_lghi( $dst$$Register, 0);
9332 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9333 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9334 } else {
9335 Label done;
9336 // indicate unused result
9337 (void) __ clear_reg($dst$$Register, true, false);
9338 __ z_bre(done);
9339 __ z_lhi($dst$$Register, 1);
9340 __ z_brh(done);
9341 __ z_lhi($dst$$Register, -1);
9342 __ bind(done);
9343 }
9344 %}
9345 ins_pipe(pipe_class_dummy);
9346 %}
9347
9348 //----------Branches---------------------------------------------------------
9349 // Jump
9350
9351 // Direct Branch.
9352 instruct branch(label labl) %{
9353 match(Goto);
9354 effect(USE labl);
9355 ins_cost(BRANCH_COST);
9356 size(4);
9357 format %{ "BRU $labl" %}
9358 ins_encode(z_enc_bru(labl));
9359 ins_pipe(pipe_class_dummy);
9360 // If set to 1 this indicates that the current instruction is a
9361 // short variant of a long branch. This avoids using this
9362 // instruction in first-pass matching. It will then only be used in
9363 // the `Shorten_branches' pass.
9364 ins_short_branch(1);
9365 %}
9366
9367 // Direct Branch.
9368 instruct branchFar(label labl) %{
9369 match(Goto);
9370 effect(USE labl);
9371 ins_cost(BRANCH_COST);
9372 size(6);
9373 format %{ "BRUL $labl" %}
9374 ins_encode(z_enc_brul(labl));
9375 ins_pipe(pipe_class_dummy);
9376 // This is not a short variant of a branch, but the long variant.
9377 ins_short_branch(0);
9378 %}
9379
9380 // Conditional Near Branch
9381 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9382 // Same match rule as `branchConFar'.
9383 match(If cmp cr);
9384 effect(USE lbl);
9385 ins_cost(BRANCH_COST);
9386 size(4);
9387 format %{ "branch_con_short,$cmp $lbl" %}
9388 ins_encode(z_enc_branch_con_short(cmp, lbl));
9389 ins_pipe(pipe_class_dummy);
9390 // If set to 1 this indicates that the current instruction is a
9391 // short variant of a long branch. This avoids using this
9392 // instruction in first-pass matching. It will then only be used in
9393 // the `Shorten_branches' pass.
9394 ins_short_branch(1);
9395 %}
9396
9397 // This is for cases when the z/Architecture conditional branch instruction
9398 // does not reach far enough. So we emit a far branch here, which is
9399 // more expensive.
9400 //
9401 // Conditional Far Branch
9402 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9403 // Same match rule as `branchCon'.
9404 match(If cmp cr);
9405 effect(USE cr, USE lbl);
9406 // Make more expensive to prefer compare_and_branch over separate instructions.
9407 ins_cost(2 * BRANCH_COST);
9408 size(6);
9409 format %{ "branch_con_far,$cmp $lbl" %}
9410 ins_encode(z_enc_branch_con_far(cmp, lbl));
9411 ins_pipe(pipe_class_dummy);
9412 // This is not a short variant of a branch, but the long variant..
9413 ins_short_branch(0);
9414 %}
9415
9416 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9417 match(CountedLoopEnd cmp cr);
9418 effect(USE labl);
9419 ins_cost(BRANCH_COST);
9420 size(4);
9421 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9422 ins_encode(z_enc_branch_con_short(cmp, labl));
9423 ins_pipe(pipe_class_dummy);
9424 // If set to 1 this indicates that the current instruction is a
9425 // short variant of a long branch. This avoids using this
9426 // instruction in first-pass matching. It will then only be used in
9427 // the `Shorten_branches' pass.
9428 ins_short_branch(1);
9429 %}
9430
9431 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9432 match(CountedLoopEnd cmp cr);
9433 effect(USE labl);
9434 ins_cost(BRANCH_COST);
9435 size(6);
9436 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9437 ins_encode(z_enc_branch_con_far(cmp, labl));
9438 ins_pipe(pipe_class_dummy);
9439 // This is not a short variant of a branch, but the long variant.
9440 ins_short_branch(0);
9441 %}
9442
9443 //----------Compare and Branch (short distance)------------------------------
9444
9445 // INT REG operands for loop counter processing.
9446 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9447 match(CountedLoopEnd boolnode (CmpI src1 src2));
9448 effect(USE labl, KILL cr);
9449 predicate(VM_Version::has_CompareBranch());
9450 ins_cost(BRANCH_COST);
9451 // TODO: s390 port size(FIXED_SIZE);
9452 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9453 opcode(CRJ_ZOPC);
9454 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9455 ins_pipe(pipe_class_dummy);
9456 ins_short_branch(1);
9457 %}
9458
9459 // INT REG operands.
9460 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9461 match(If boolnode (CmpI src1 src2));
9462 effect(USE labl, KILL cr);
9463 predicate(VM_Version::has_CompareBranch());
9464 ins_cost(BRANCH_COST);
9465 // TODO: s390 port size(FIXED_SIZE);
9466 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9467 opcode(CRJ_ZOPC);
9468 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9469 ins_pipe(pipe_class_dummy);
9470 ins_short_branch(1);
9471 %}
9472
9473 // Unsigned INT REG operands
9474 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9475 match(If boolnode (CmpU src1 src2));
9476 effect(USE labl, KILL cr);
9477 predicate(VM_Version::has_CompareBranch());
9478 ins_cost(BRANCH_COST);
9479 // TODO: s390 port size(FIXED_SIZE);
9480 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9481 opcode(CLRJ_ZOPC);
9482 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9483 ins_pipe(pipe_class_dummy);
9484 ins_short_branch(1);
9485 %}
9486
9487 // LONG REG operands
9488 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9489 match(If boolnode (CmpL src1 src2));
9490 effect(USE labl, KILL cr);
9491 predicate(VM_Version::has_CompareBranch());
9492 ins_cost(BRANCH_COST);
9493 // TODO: s390 port size(FIXED_SIZE);
9494 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9495 opcode(CGRJ_ZOPC);
9496 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9497 ins_pipe(pipe_class_dummy);
9498 ins_short_branch(1);
9499 %}
9500
9501 // PTR REG operands
9502
9503 // Separate rules for regular and narrow oops. ADLC can't recognize
9504 // rules with polymorphic operands to be sisters -> shorten_branches
9505 // will not shorten.
9506
9507 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9508 match(If boolnode (CmpP src1 src2));
9509 effect(USE labl, KILL cr);
9510 predicate(VM_Version::has_CompareBranch());
9511 ins_cost(BRANCH_COST);
9512 // TODO: s390 port size(FIXED_SIZE);
9513 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9514 opcode(CLGRJ_ZOPC);
9515 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9516 ins_pipe(pipe_class_dummy);
9517 ins_short_branch(1);
9518 %}
9519
9520 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9521 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9522 effect(USE labl, KILL cr);
9523 predicate(VM_Version::has_CompareBranch());
9524 ins_cost(BRANCH_COST);
9525 // TODO: s390 port size(FIXED_SIZE);
9526 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9527 opcode(CLGRJ_ZOPC);
9528 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9529 ins_pipe(pipe_class_dummy);
9530 ins_short_branch(1);
9531 %}
9532
9533 // INT REG/IMM operands for loop counter processing
9534 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9535 match(CountedLoopEnd boolnode (CmpI src1 src2));
9536 effect(USE labl, KILL cr);
9537 predicate(VM_Version::has_CompareBranch());
9538 ins_cost(BRANCH_COST);
9539 // TODO: s390 port size(FIXED_SIZE);
9540 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9541 opcode(CIJ_ZOPC);
9542 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9543 ins_pipe(pipe_class_dummy);
9544 ins_short_branch(1);
9545 %}
9546
9547 // INT REG/IMM operands
9548 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9549 match(If boolnode (CmpI src1 src2));
9550 effect(USE labl, KILL cr);
9551 predicate(VM_Version::has_CompareBranch());
9552 ins_cost(BRANCH_COST);
9553 // TODO: s390 port size(FIXED_SIZE);
9554 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9555 opcode(CIJ_ZOPC);
9556 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9557 ins_pipe(pipe_class_dummy);
9558 ins_short_branch(1);
9559 %}
9560
9561 // INT REG/IMM operands
9562 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9563 match(If boolnode (CmpU src1 src2));
9564 effect(USE labl, KILL cr);
9565 predicate(VM_Version::has_CompareBranch());
9566 ins_cost(BRANCH_COST);
9567 // TODO: s390 port size(FIXED_SIZE);
9568 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9569 opcode(CLIJ_ZOPC);
9570 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9571 ins_pipe(pipe_class_dummy);
9572 ins_short_branch(1);
9573 %}
9574
9575 // LONG REG/IMM operands
9576 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9577 match(If boolnode (CmpL src1 src2));
9578 effect(USE labl, KILL cr);
9579 predicate(VM_Version::has_CompareBranch());
9580 ins_cost(BRANCH_COST);
9581 // TODO: s390 port size(FIXED_SIZE);
9582 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9583 opcode(CGIJ_ZOPC);
9584 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9585 ins_pipe(pipe_class_dummy);
9586 ins_short_branch(1);
9587 %}
9588
9589 // PTR REG-imm operands
9590
9591 // Separate rules for regular and narrow oops. ADLC can't recognize
9592 // rules with polymorphic operands to be sisters -> shorten_branches
9593 // will not shorten.
9594
9595 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9596 match(If boolnode (CmpP src1 src2));
9597 effect(USE labl, KILL cr);
9598 predicate(VM_Version::has_CompareBranch());
9599 ins_cost(BRANCH_COST);
9600 // TODO: s390 port size(FIXED_SIZE);
9601 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9602 opcode(CLGIJ_ZOPC);
9603 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9604 ins_pipe(pipe_class_dummy);
9605 ins_short_branch(1);
9606 %}
9607
9608 // Compare against zero only, do not mix N and P oops (encode/decode required).
9609 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9610 match(If boolnode (CmpP (DecodeN src1) src2));
9611 effect(USE labl, KILL cr);
9612 predicate(VM_Version::has_CompareBranch());
9613 ins_cost(BRANCH_COST);
9614 // TODO: s390 port size(FIXED_SIZE);
9615 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9616 opcode(CLGIJ_ZOPC);
9617 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9618 ins_pipe(pipe_class_dummy);
9619 ins_short_branch(1);
9620 %}
9621
9622 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9623 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9624 effect(USE labl, KILL cr);
9625 predicate(VM_Version::has_CompareBranch());
9626 ins_cost(BRANCH_COST);
9627 // TODO: s390 port size(FIXED_SIZE);
9628 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9629 opcode(CLGIJ_ZOPC);
9630 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9631 ins_pipe(pipe_class_dummy);
9632 ins_short_branch(1);
9633 %}
9634
9635
9636 //----------Compare and Branch (far distance)------------------------------
9637
9638 // INT REG operands for loop counter processing
9639 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9640 match(CountedLoopEnd boolnode (CmpI src1 src2));
9641 effect(USE labl, KILL cr);
9642 predicate(VM_Version::has_CompareBranch());
9643 ins_cost(BRANCH_COST+DEFAULT_COST);
9644 // TODO: s390 port size(FIXED_SIZE);
9645 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9646 opcode(CR_ZOPC, BRCL_ZOPC);
9647 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9648 ins_pipe(pipe_class_dummy);
9649 ins_short_branch(0);
9650 %}
9651
9652 // INT REG operands
9653 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9654 match(If boolnode (CmpI src1 src2));
9655 effect(USE labl, KILL cr);
9656 predicate(VM_Version::has_CompareBranch());
9657 ins_cost(BRANCH_COST+DEFAULT_COST);
9658 // TODO: s390 port size(FIXED_SIZE);
9659 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9660 opcode(CR_ZOPC, BRCL_ZOPC);
9661 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9662 ins_pipe(pipe_class_dummy);
9663 ins_short_branch(0);
9664 %}
9665
9666 // INT REG operands
9667 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9668 match(If boolnode (CmpU src1 src2));
9669 effect(USE labl, KILL cr);
9670 predicate(VM_Version::has_CompareBranch());
9671 ins_cost(BRANCH_COST+DEFAULT_COST);
9672 // TODO: s390 port size(FIXED_SIZE);
9673 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9674 opcode(CLR_ZOPC, BRCL_ZOPC);
9675 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9676 ins_pipe(pipe_class_dummy);
9677 ins_short_branch(0);
9678 %}
9679
9680 // LONG REG operands
9681 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9682 match(If boolnode (CmpL src1 src2));
9683 effect(USE labl, KILL cr);
9684 predicate(VM_Version::has_CompareBranch());
9685 ins_cost(BRANCH_COST+DEFAULT_COST);
9686 // TODO: s390 port size(FIXED_SIZE);
9687 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9688 opcode(CGR_ZOPC, BRCL_ZOPC);
9689 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9690 ins_pipe(pipe_class_dummy);
9691 ins_short_branch(0);
9692 %}
9693
9694 // PTR REG operands
9695
9696 // Separate rules for regular and narrow oops. ADLC can't recognize
9697 // rules with polymorphic operands to be sisters -> shorten_branches
9698 // will not shorten.
9699
9700 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9701 match(If boolnode (CmpP src1 src2));
9702 effect(USE labl, KILL cr);
9703 predicate(VM_Version::has_CompareBranch());
9704 ins_cost(BRANCH_COST+DEFAULT_COST);
9705 // TODO: s390 port size(FIXED_SIZE);
9706 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9707 opcode(CLGR_ZOPC, BRCL_ZOPC);
9708 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9709 ins_pipe(pipe_class_dummy);
9710 ins_short_branch(0);
9711 %}
9712
9713 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9714 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9715 effect(USE labl, KILL cr);
9716 predicate(VM_Version::has_CompareBranch());
9717 ins_cost(BRANCH_COST+DEFAULT_COST);
9718 // TODO: s390 port size(FIXED_SIZE);
9719 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9720 opcode(CLGR_ZOPC, BRCL_ZOPC);
9721 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9722 ins_pipe(pipe_class_dummy);
9723 ins_short_branch(0);
9724 %}
9725
9726 // INT REG/IMM operands for loop counter processing
9727 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9728 match(CountedLoopEnd boolnode (CmpI src1 src2));
9729 effect(USE labl, KILL cr);
9730 predicate(VM_Version::has_CompareBranch());
9731 ins_cost(BRANCH_COST+DEFAULT_COST);
9732 // TODO: s390 port size(FIXED_SIZE);
9733 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9734 opcode(CHI_ZOPC, BRCL_ZOPC);
9735 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9736 ins_pipe(pipe_class_dummy);
9737 ins_short_branch(0);
9738 %}
9739
9740 // INT REG/IMM operands
9741 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9742 match(If boolnode (CmpI src1 src2));
9743 effect(USE labl, KILL cr);
9744 predicate(VM_Version::has_CompareBranch());
9745 ins_cost(BRANCH_COST+DEFAULT_COST);
9746 // TODO: s390 port size(FIXED_SIZE);
9747 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9748 opcode(CHI_ZOPC, BRCL_ZOPC);
9749 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9750 ins_pipe(pipe_class_dummy);
9751 ins_short_branch(0);
9752 %}
9753
9754 // INT REG/IMM operands
9755 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9756 match(If boolnode (CmpU src1 src2));
9757 effect(USE labl, KILL cr);
9758 predicate(VM_Version::has_CompareBranch());
9759 ins_cost(BRANCH_COST+DEFAULT_COST);
9760 // TODO: s390 port size(FIXED_SIZE);
9761 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9762 opcode(CLFI_ZOPC, BRCL_ZOPC);
9763 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9764 ins_pipe(pipe_class_dummy);
9765 ins_short_branch(0);
9766 %}
9767
9768 // LONG REG/IMM operands
9769 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9770 match(If boolnode (CmpL src1 src2));
9771 effect(USE labl, KILL cr);
9772 predicate(VM_Version::has_CompareBranch());
9773 ins_cost(BRANCH_COST+DEFAULT_COST);
9774 // TODO: s390 port size(FIXED_SIZE);
9775 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9776 opcode(CGHI_ZOPC, BRCL_ZOPC);
9777 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9778 ins_pipe(pipe_class_dummy);
9779 ins_short_branch(0);
9780 %}
9781
9782 // PTR REG-imm operands
9783
9784 // Separate rules for regular and narrow oops. ADLC can't recognize
9785 // rules with polymorphic operands to be sisters -> shorten_branches
9786 // will not shorten.
9787
9788 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9789 match(If boolnode (CmpP src1 src2));
9790 effect(USE labl, KILL cr);
9791 predicate(VM_Version::has_CompareBranch());
9792 ins_cost(BRANCH_COST+DEFAULT_COST);
9793 // TODO: s390 port size(FIXED_SIZE);
9794 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9795 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9796 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9797 ins_pipe(pipe_class_dummy);
9798 ins_short_branch(0);
9799 %}
9800
9801 // Compare against zero only, do not mix N and P oops (encode/decode required).
9802 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9803 match(If boolnode (CmpP (DecodeN src1) src2));
9804 effect(USE labl, KILL cr);
9805 predicate(VM_Version::has_CompareBranch());
9806 ins_cost(BRANCH_COST+DEFAULT_COST);
9807 // TODO: s390 port size(FIXED_SIZE);
9808 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9809 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9810 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9811 ins_pipe(pipe_class_dummy);
9812 ins_short_branch(0);
9813 %}
9814
9815 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9816 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9817 effect(USE labl, KILL cr);
9818 predicate(VM_Version::has_CompareBranch());
9819 ins_cost(BRANCH_COST+DEFAULT_COST);
9820 // TODO: s390 port size(FIXED_SIZE);
9821 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9822 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9823 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9824 ins_pipe(pipe_class_dummy);
9825 ins_short_branch(0);
9826 %}
9827
9828 // ============================================================================
9829 // Long Compare
9830
9831 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9832 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9833 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9834 // are collapsed internally in the ADLC's dfa-gen code. The match for
9835 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9836 // foo match ends up with the wrong leaf. One fix is to not match both
9837 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9838 // both forms beat the trinary form of long-compare and both are very useful
9839 // on platforms which have few registers.
9840
9841 // Manifest a CmpL3 result in an integer register. Very painful.
9842 // This is the test to avoid.
9843 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9844 match(Set dst (CmpL3 src1 src2));
9845 effect(KILL cr);
9846 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9847 size(24);
9848 format %{ "CmpL3 $dst,$src1,$src2" %}
9849 ins_encode %{
9850 Label done;
9851 // compare registers
9852 __ z_cgr($src1$$Register, $src2$$Register);
9853 // Convert condition code into -1,0,1, where
9854 // -1 means less
9855 // 0 means equal
9856 // 1 means greater.
9857 if (VM_Version::has_LoadStoreConditional()) {
9858 Register one = Z_R0_scratch;
9859 Register minus_one = Z_R1_scratch;
9860 __ z_lghi(minus_one, -1);
9861 __ z_lghi(one, 1);
9862 __ z_lghi( $dst$$Register, 0);
9863 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9864 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9865 } else {
9866 __ clear_reg($dst$$Register, true, false);
9867 __ z_bre(done);
9868 __ z_lhi($dst$$Register, 1);
9869 __ z_brh(done);
9870 __ z_lhi($dst$$Register, -1);
9871 }
9872 __ bind(done);
9873 %}
9874 ins_pipe(pipe_class_dummy);
9875 %}
9876
9877 // ============================================================================
9878 // Safepoint Instruction
9879
9880 instruct safePoint() %{
9881 match(SafePoint);
9882 predicate(false);
9883 // TODO: s390 port size(FIXED_SIZE);
9884 format %{ "UNIMPLEMENTED Safepoint_ " %}
9885 ins_encode(enc_unimplemented());
9886 ins_pipe(pipe_class_dummy);
9887 %}
9888
9889 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9890 match(SafePoint poll);
9891 effect(USE poll, KILL cr); // R0 is killed, too.
9892 // TODO: s390 port size(FIXED_SIZE);
9893 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9894 ins_encode %{
9895 // Mark the code position where the load from the safepoint
9896 // polling page was emitted as relocInfo::poll_type.
9897 __ relocate(relocInfo::poll_type);
9898 __ load_from_polling_page($poll$$Register);
9899 %}
9900 ins_pipe(pipe_class_dummy);
9901 %}
9902
9903 // ============================================================================
9904
9905 // Call Instructions
9906
9907 // Call Java Static Instruction
9908 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9909 match(CallStaticJava);
9910 effect(USE meth);
9911 ins_cost(CALL_COST);
9912 // TODO: s390 port size(VARIABLE_SIZE);
9913 format %{ "CALL,static dynTOC $meth; ==> " %}
9914 ins_encode( z_enc_java_static_call(meth) );
9915 ins_pipe(pipe_class_dummy);
9916 ins_alignment(2);
9917 %}
9918
9919 // Call Java Dynamic Instruction
9920 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9921 match(CallDynamicJava);
9922 effect(USE meth);
9923 ins_cost(CALL_COST);
9924 // TODO: s390 port size(VARIABLE_SIZE);
9925 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9926 ins_encode(z_enc_java_dynamic_call(meth));
9927 ins_pipe(pipe_class_dummy);
9928 ins_alignment(2);
9929 %}
9930
9931 // Call Runtime Instruction
9932 instruct CallRuntimeDirect(method meth) %{
9933 match(CallRuntime);
9934 effect(USE meth);
9935 ins_cost(CALL_COST);
9936 // TODO: s390 port size(VARIABLE_SIZE);
9937 ins_num_consts(1);
9938 ins_alignment(2);
9939 format %{ "CALL,runtime" %}
9940 ins_encode( z_enc_java_to_runtime_call(meth) );
9941 ins_pipe(pipe_class_dummy);
9942 %}
9943
9944 // Call runtime without safepoint - same as CallRuntime
9945 instruct CallLeafDirect(method meth) %{
9946 match(CallLeaf);
9947 effect(USE meth);
9948 ins_cost(CALL_COST);
9949 // TODO: s390 port size(VARIABLE_SIZE);
9950 ins_num_consts(1);
9951 ins_alignment(2);
9952 format %{ "CALL,runtime leaf $meth" %}
9953 ins_encode( z_enc_java_to_runtime_call(meth) );
9954 ins_pipe(pipe_class_dummy);
9955 %}
9956
9957 // Call runtime without safepoint - same as CallLeaf
9958 instruct CallLeafNoFPDirect(method meth) %{
9959 match(CallLeafNoFP);
9960 effect(USE meth);
9961 ins_cost(CALL_COST);
9962 // TODO: s390 port size(VARIABLE_SIZE);
9963 ins_num_consts(1);
9964 format %{ "CALL,runtime leaf nofp $meth" %}
9965 ins_encode( z_enc_java_to_runtime_call(meth) );
9966 ins_pipe(pipe_class_dummy);
9967 ins_alignment(2);
9968 %}
9969
9970 // Tail Call; Jump from runtime stub to Java code.
9971 // Also known as an 'interprocedural jump'.
9972 // Target of jump will eventually return to caller.
9973 // TailJump below removes the return address.
9974 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{
9975 match(TailCall jump_target method_ptr);
9976 ins_cost(CALL_COST);
9977 size(2);
9978 format %{ "Jmp $jump_target\t # $method_ptr holds method" %}
9979 ins_encode %{ __ z_br($jump_target$$Register); %}
9980 ins_pipe(pipe_class_dummy);
9981 %}
9982
9983 // Return Instruction
9984 instruct Ret() %{
9985 match(Return);
9986 size(2);
9987 format %{ "BR(Z_R14) // branch to link register" %}
9988 ins_encode %{ __ z_br(Z_R14); %}
9989 ins_pipe(pipe_class_dummy);
9990 %}
9991
9992 // Tail Jump; remove the return address; jump to target.
9993 // TailCall above leaves the return address around.
9994 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9995 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9996 // "restore" before this instruction (in Epilogue), we need to materialize it
9997 // in %i0.
9998 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9999 match(TailJump jump_target ex_oop);
10000 ins_cost(CALL_COST);
10001 size(8);
10002 format %{ "TailJump $jump_target" %}
10003 ins_encode %{
10004 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
10005 __ z_br($jump_target$$Register);
10006 %}
10007 ins_pipe(pipe_class_dummy);
10008 %}
10009
10010 // Forward exception.
10011 instruct ForwardExceptionjmp() %{
10012 match(ForwardException);
10013 ins_cost(CALL_COST);
10014 format %{ "Jmp forward_exception_stub" %}
10015 ins_encode %{
10016 __ set_inst_mark();
10017 __ load_const_optimized(Z_R1_scratch, (address)StubRoutines::forward_exception_entry());
10018 __ z_br(Z_R1_scratch);
10019 __ clear_inst_mark();
10020 %}
10021 ins_pipe(pipe_class_dummy);
10022 %}
10023
10024 // Create exception oop: created by stack-crawling runtime code.
10025 // Created exception is now available to this handler, and is setup
10026 // just prior to jumping to this handler. No code emitted.
10027 instruct CreateException(rarg1RegP ex_oop) %{
10028 match(Set ex_oop (CreateEx));
10029 ins_cost(0);
10030 size(0);
10031 format %{ "# exception oop; no code emitted" %}
10032 ins_encode(/*empty*/);
10033 ins_pipe(pipe_class_dummy);
10034 %}
10035
10036 // Rethrow exception: The exception oop will come in the first
10037 // argument position. Then JUMP (not call) to the rethrow stub code.
10038 instruct RethrowException() %{
10039 match(Rethrow);
10040 ins_cost(CALL_COST);
10041 // TODO: s390 port size(VARIABLE_SIZE);
10042 format %{ "Jmp rethrow_stub" %}
10043 ins_encode %{
10044 __ set_inst_mark();
10045 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
10046 __ z_br(Z_R1_scratch);
10047 __ clear_inst_mark();
10048 %}
10049 ins_pipe(pipe_class_dummy);
10050 %}
10051
10052 // Die now.
10053 instruct ShouldNotReachHere() %{
10054 match(Halt);
10055 ins_cost(CALL_COST);
10056 format %{ "ILLTRAP; ShouldNotReachHere" %}
10057 ins_encode %{
10058 if (is_reachable()) {
10059 const char* str = __ code_string(_halt_reason);
10060 __ stop(str);
10061 }
10062 %}
10063 ins_pipe(pipe_class_dummy);
10064 %}
10065
10066 // ============================================================================
10067 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10068 // array for an instance of the superklass. Set a hidden internal cache on a
10069 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10070 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10071 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
10072 rarg4RegP scratch1, rarg5RegP scratch2) %{
10073 match(Set index (PartialSubtypeCheck sub super));
10074 predicate(!UseSecondarySupersTable);
10075 effect(KILL pcc, KILL scratch1, KILL scratch2);
10076 ins_cost(20 * DEFAULT_COST); // slightly larger than the next version
10077 // TODO: s390 port size(FIXED_SIZE);
10078 format %{ " CALL PartialSubtypeCheck\n" %}
10079 ins_encode %{
10080 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
10081 __ load_const_optimized(Z_ARG4, stub_address);
10082 __ z_basr(Z_R14, Z_ARG4);
10083 %}
10084 ins_pipe(pipe_class_dummy);
10085 %}
10086
10087 // Two versions of partialSubtypeCheck, both used when we need to
10088 // search for a super class in the secondary supers array. The first
10089 // is used when we don't know _a priori_ the class being searched
10090 // for. The second, far more common, is used when we do know: this is
10091 // used for instanceof, checkcast, and any case where C2 can determine
10092 // it by constant propagation.
10093 instruct partialSubtypeCheckVarSuper(rarg2RegP sub, rarg3RegP super,
10094 r11TempRegP result,
10095 rarg1RegP temp1, rarg4RegP temp2, rarg5RegP temp3, r10TempRegP temp4,
10096 flagsReg pcc) %{
10097 match(Set result (PartialSubtypeCheck sub super));
10098 predicate(UseSecondarySupersTable);
10099 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10100 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10101 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10102 ins_encode %{
10103 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register,
10104 $temp1$$Register, $temp2$$Register, $temp3$$Register, $temp4$$Register,
10105 $result$$Register);
10106 %}
10107 ins_pipe(pipe_class_dummy);
10108 %}
10109
10110
10111 instruct partialSubtypeCheckConstSuper(rarg2RegP sub, rarg1RegP super, immP super_con,
10112 r11TempRegP result, rarg5RegP temp1, rarg4RegP temp2,
10113 rarg3RegP temp3, r10TempRegP temp4, flagsReg pcc) %{
10114 match(Set result (PartialSubtypeCheck sub (Binary super super_con)));
10115 predicate(UseSecondarySupersTable);
10116 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10117 ins_cost(5 * DEFAULT_COST); // smaller than the next version
10118 format %{ "partialSubtypeCheck $result, $sub, $super, $super_con" %}
10119
10120 ins_encode %{
10121 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10122 if (InlineSecondarySupersTest) {
10123 __ lookup_secondary_supers_table_const($sub$$Register, $super$$Register,
10124 $temp1$$Register, $temp2$$Register, $temp3$$Register,
10125 $temp4$$Register, $result$$Register, super_klass_slot);
10126 } else {
10127 AddressLiteral stub_address(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot));
10128 __ load_const_optimized(Z_ARG4, stub_address);
10129 __ z_basr(Z_R14, Z_ARG4);
10130 }
10131
10132 %}
10133
10134 ins_pipe(pipe_class_dummy);
10135 %}
10136
10137 // ============================================================================
10138 // inlined locking and unlocking
10139
10140 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10141 match(Set pcc (FastLock oop box));
10142 effect(TEMP tmp1, TEMP tmp2);
10143 ins_cost(100);
10144 // TODO: s390 port size(VARIABLE_SIZE);
10145 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10146 ins_encode %{
10147 __ fast_lock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10148 // If locking was successful, cc should indicate 'EQ'.
10149 // The compiler generates a branch to the runtime call to
10150 // _complete_monitor_locking_Java for the case where cc is 'NE'.
10151 %}
10152 ins_pipe(pipe_class_dummy);
10153 %}
10154
10155 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10156 match(Set pcc (FastUnlock oop box));
10157 effect(TEMP tmp1, TEMP tmp2);
10158 ins_cost(100);
10159 // TODO: s390 port size(FIXED_SIZE);
10160 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10161 ins_encode %{
10162 __ fast_unlock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10163 // If unlocking was successful, cc should indicate 'EQ'.
10164 // The compiler generates a branch to the runtime call to
10165 // _complete_monitor_unlocking_Java for the case where cc is 'NE'.
10166 %}
10167 ins_pipe(pipe_class_dummy);
10168 %}
10169
10170 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
10171 match(Set dummy (ClearArray cnt base));
10172 effect(KILL cr);
10173 ins_cost(100);
10174 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
10175 format %{ "ClearArrayConst $cnt,$base" %}
10176 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
10177 ins_pipe(pipe_class_dummy);
10178 %}
10179
10180 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10181 match(Set dummy (ClearArray cnt base));
10182 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10183 ins_cost(200);
10184 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
10185 format %{ "ClearArrayConstBig $cnt,$base" %}
10186 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
10187 ins_pipe(pipe_class_dummy);
10188 %}
10189
10190 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10191 match(Set dummy (ClearArray cnt base));
10192 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10193 ins_cost(300);
10194 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
10195 format %{ "ClearArrayVar $cnt,$base" %}
10196 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
10197 ins_pipe(pipe_class_dummy);
10198 %}
10199
10200 // ============================================================================
10201 // CompactStrings
10202
10203 // String equals
10204 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10205 match(Set result (StrEquals (Binary str1 str2) cnt));
10206 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10207 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10208 ins_cost(300);
10209 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10210 ins_encode %{
10211 __ array_equals(false, $str1$$Register, $str2$$Register,
10212 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
10213 $result$$Register, true /* byte */);
10214 %}
10215 ins_pipe(pipe_class_dummy);
10216 %}
10217
10218 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
10219 match(Set result (StrEquals (Binary str1 str2) cnt));
10220 effect(KILL cr); // R0 is killed, too.
10221 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10222 ins_cost(100);
10223 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10224 ins_encode %{
10225 const int cnt_imm = $cnt$$constant;
10226 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
10227 __ z_lhi($result$$Register, 1);
10228 if (cnt_imm) {
10229 if (VM_Version::has_LoadStoreConditional()) {
10230 __ z_lhi(Z_R0_scratch, 0);
10231 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10232 } else {
10233 Label Lskip;
10234 __ z_bre(Lskip);
10235 __ clear_reg($result$$Register);
10236 __ bind(Lskip);
10237 }
10238 }
10239 %}
10240 ins_pipe(pipe_class_dummy);
10241 %}
10242
10243 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
10244 match(Set result (StrEquals (Binary str1 str2) cnt));
10245 effect(KILL cr); // R0 is killed, too.
10246 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
10247 ins_cost(100);
10248 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10249 ins_encode %{
10250 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10251 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10252 __ z_lhi($result$$Register, 1);
10253 if (cnt_imm) {
10254 if (VM_Version::has_LoadStoreConditional()) {
10255 __ z_lhi(Z_R0_scratch, 0);
10256 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10257 } else {
10258 Label Lskip;
10259 __ z_bre(Lskip);
10260 __ clear_reg($result$$Register);
10261 __ bind(Lskip);
10262 }
10263 }
10264 %}
10265 ins_pipe(pipe_class_dummy);
10266 %}
10267
10268 // Array equals
10269 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10270 match(Set result (AryEq ary1 ary2));
10271 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10272 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10273 ins_cost(300);
10274 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10275 ins_encode %{
10276 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10277 noreg, $oddReg$$Register, $evenReg$$Register,
10278 $result$$Register, true /* byte */);
10279 %}
10280 ins_pipe(pipe_class_dummy);
10281 %}
10282
10283 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10284 match(Set result (AryEq ary1 ary2));
10285 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10286 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10287 ins_cost(300);
10288 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10289 ins_encode %{
10290 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10291 noreg, $oddReg$$Register, $evenReg$$Register,
10292 $result$$Register, false /* byte */);
10293 %}
10294 ins_pipe(pipe_class_dummy);
10295 %}
10296
10297 // String CompareTo
10298 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10299 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10300 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10301 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10302 ins_cost(300);
10303 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10304 ins_encode %{
10305 __ string_compare($str1$$Register, $str2$$Register,
10306 $cnt1$$Register, $cnt2$$Register,
10307 $oddReg$$Register, $evenReg$$Register,
10308 $result$$Register, StrIntrinsicNode::LL);
10309 %}
10310 ins_pipe(pipe_class_dummy);
10311 %}
10312
10313 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10314 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10315 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10316 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10317 ins_cost(300);
10318 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10319 ins_encode %{
10320 __ string_compare($str1$$Register, $str2$$Register,
10321 $cnt1$$Register, $cnt2$$Register,
10322 $oddReg$$Register, $evenReg$$Register,
10323 $result$$Register, StrIntrinsicNode::UU);
10324 %}
10325 ins_pipe(pipe_class_dummy);
10326 %}
10327
10328 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10329 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10330 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10331 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10332 ins_cost(300);
10333 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10334 ins_encode %{
10335 __ string_compare($str1$$Register, $str2$$Register,
10336 $cnt1$$Register, $cnt2$$Register,
10337 $oddReg$$Register, $evenReg$$Register,
10338 $result$$Register, StrIntrinsicNode::LU);
10339 %}
10340 ins_pipe(pipe_class_dummy);
10341 %}
10342
10343 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10344 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10345 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10346 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10347 ins_cost(300);
10348 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10349 ins_encode %{
10350 __ string_compare($str2$$Register, $str1$$Register,
10351 $cnt2$$Register, $cnt1$$Register,
10352 $oddReg$$Register, $evenReg$$Register,
10353 $result$$Register, StrIntrinsicNode::UL);
10354 %}
10355 ins_pipe(pipe_class_dummy);
10356 %}
10357
10358 // String IndexOfChar
10359 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10360 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10361 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10362 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
10363 ins_cost(200);
10364 format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10365 ins_encode %{
10366 __ string_indexof_char($result$$Register,
10367 $haystack$$Register, $haycnt$$Register,
10368 $ch$$Register, 0 /* unused, ch is in register */,
10369 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10370 %}
10371 ins_pipe(pipe_class_dummy);
10372 %}
10373
10374 instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10375 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10376 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10377 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
10378 ins_cost(200);
10379 format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10380 ins_encode %{
10381 __ string_indexof_char($result$$Register,
10382 $haystack$$Register, $haycnt$$Register,
10383 $ch$$Register, 0 /* unused, ch is in register */,
10384 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10385 %}
10386 ins_pipe(pipe_class_dummy);
10387 %}
10388
10389 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10390 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10391 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10392 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10393 ins_cost(200);
10394 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10395 ins_encode %{
10396 immPOper *needleOper = (immPOper *)$needle;
10397 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10398 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10399 jchar chr;
10400 #ifdef VM_LITTLE_ENDIAN
10401 Unimplemented();
10402 #else
10403 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10404 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10405 #endif
10406 __ string_indexof_char($result$$Register,
10407 $haystack$$Register, $haycnt$$Register,
10408 noreg, chr,
10409 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10410 %}
10411 ins_pipe(pipe_class_dummy);
10412 %}
10413
10414 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10415 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10416 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10417 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10418 ins_cost(200);
10419 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10420 ins_encode %{
10421 immPOper *needleOper = (immPOper *)$needle;
10422 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10423 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10424 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10425 __ string_indexof_char($result$$Register,
10426 $haystack$$Register, $haycnt$$Register,
10427 noreg, chr,
10428 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10429 %}
10430 ins_pipe(pipe_class_dummy);
10431 %}
10432
10433 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10434 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10435 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10436 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10437 ins_cost(200);
10438 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10439 ins_encode %{
10440 immPOper *needleOper = (immPOper *)$needle;
10441 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10442 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10443 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10444 __ string_indexof_char($result$$Register,
10445 $haystack$$Register, $haycnt$$Register,
10446 noreg, chr,
10447 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10448 %}
10449 ins_pipe(pipe_class_dummy);
10450 %}
10451
10452 // String IndexOf
10453 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10454 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10455 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10456 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10457 ins_cost(250);
10458 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10459 ins_encode %{
10460 __ string_indexof($result$$Register,
10461 $haystack$$Register, $haycnt$$Register,
10462 $needle$$Register, noreg, $needlecntImm$$constant,
10463 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10464 %}
10465 ins_pipe(pipe_class_dummy);
10466 %}
10467
10468 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10469 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10470 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10471 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10472 ins_cost(250);
10473 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10474 ins_encode %{
10475 __ string_indexof($result$$Register,
10476 $haystack$$Register, $haycnt$$Register,
10477 $needle$$Register, noreg, $needlecntImm$$constant,
10478 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10479 %}
10480 ins_pipe(pipe_class_dummy);
10481 %}
10482
10483 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10484 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10485 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10486 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10487 ins_cost(250);
10488 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10489 ins_encode %{
10490 __ string_indexof($result$$Register,
10491 $haystack$$Register, $haycnt$$Register,
10492 $needle$$Register, noreg, $needlecntImm$$constant,
10493 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10494 %}
10495 ins_pipe(pipe_class_dummy);
10496 %}
10497
10498 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10499 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10500 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10501 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10502 ins_cost(300);
10503 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10504 ins_encode %{
10505 __ string_indexof($result$$Register,
10506 $haystack$$Register, $haycnt$$Register,
10507 $needle$$Register, $needlecnt$$Register, 0,
10508 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10509 %}
10510 ins_pipe(pipe_class_dummy);
10511 %}
10512
10513 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10514 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10515 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10516 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10517 ins_cost(300);
10518 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10519 ins_encode %{
10520 __ string_indexof($result$$Register,
10521 $haystack$$Register, $haycnt$$Register,
10522 $needle$$Register, $needlecnt$$Register, 0,
10523 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10524 %}
10525 ins_pipe(pipe_class_dummy);
10526 %}
10527
10528 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10529 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10530 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10531 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10532 ins_cost(300);
10533 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10534 ins_encode %{
10535 __ string_indexof($result$$Register,
10536 $haystack$$Register, $haycnt$$Register,
10537 $needle$$Register, $needlecnt$$Register, 0,
10538 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10539 %}
10540 ins_pipe(pipe_class_dummy);
10541 %}
10542
10543 // char[] to byte[] compression
10544 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18,
10545 v19TempReg v19, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10546 match(Set result (StrCompressedCopy src (Binary dst len)));
10547 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19, TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10548 ins_cost(300);
10549 format %{ "String Compress $src->$dst($len) -> $result" %}
10550 ins_encode %{
10551 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10552 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10553 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10554 $v23$$VectorRegister);
10555 %}
10556 ins_pipe(pipe_class_dummy);
10557 %}
10558
10559 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10560 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10561 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10562 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10563 // predicate(VM_Version::has_ETF2Enhancements());
10564 // ins_cost(300);
10565 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10566 // ins_encode %{
10567 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10568 // %}
10569 // ins_pipe(pipe_class_dummy);
10570 //%}
10571
10572 // byte[] to char[] inflation
10573 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10574 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10575 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10576 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10577 ins_cost(300);
10578 format %{ "String Inflate $src->$dst($len)" %}
10579 ins_encode %{
10580 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, $v20$$VectorRegister,
10581 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10582 $v25$$VectorRegister);
10583 %}
10584 ins_pipe(pipe_class_dummy);
10585 %}
10586
10587 // byte[] to char[] inflation
10588 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10589 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10590 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10591 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10592 ins_cost(300);
10593 format %{ "String Inflate (constLen) $src->$dst($len)" %}
10594 ins_encode %{
10595 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant , $v20$$VectorRegister,
10596 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10597 $v25$$VectorRegister);
10598 %}
10599 ins_pipe(pipe_class_dummy);
10600 %}
10601
10602 // StringCoding.java intrinsics
10603 instruct count_positives(iRegP ary1, iRegI len, iRegI result, iRegI tmp, flagsReg cr) %{
10604 match(Set result (CountPositives ary1 len));
10605 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10606 ins_cost(300);
10607 format %{ "count positives byte[] $ary1($len) -> $result" %}
10608 ins_encode %{
10609 __ count_positives($result$$Register, $ary1$$Register, $len$$Register, $tmp$$Register);
10610 %}
10611 ins_pipe(pipe_class_dummy);
10612 %}
10613
10614 // encode char[] to byte[] in ISO_8859_1
10615 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10616 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10617 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
10618 match(Set result (EncodeISOArray src (Binary dst len)));
10619 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10620 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10621 ins_cost(300);
10622 format %{ "Encode iso array $src->$dst($len) -> $result" %}
10623 ins_encode %{
10624 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10625 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10626 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10627 $v23$$VectorRegister);
10628 %}
10629 ins_pipe(pipe_class_dummy);
10630 %}
10631
10632 // encode char[] to byte[] in ASCII
10633 instruct encode_ascii_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10634 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10635 predicate(((EncodeISOArrayNode*)n)->is_ascii());
10636 match(Set result (EncodeISOArray src (Binary dst len)));
10637 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10638 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10639 ins_cost(300);
10640 format %{ "Encode ascii array $src->$dst($len) -> $result" %}
10641 ins_encode %{
10642 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10643 $tmp$$Register, true, true, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10644 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10645 $v23$$VectorRegister);
10646 %}
10647 ins_pipe(pipe_class_dummy);
10648 %}
10649
10650
10651 //----------PEEPHOLE RULES-----------------------------------------------------
10652 // These must follow all instruction definitions as they use the names
10653 // defined in the instructions definitions.
10654 //
10655 // peepmatch (root_instr_name [preceeding_instruction]*);
10656 //
10657 // peepconstraint %{
10658 // (instruction_number.operand_name relational_op instruction_number.operand_name
10659 // [, ...]);
10660 // // instruction numbers are zero-based using left to right order in peepmatch
10661 //
10662 // peepreplace (instr_name([instruction_number.operand_name]*));
10663 // // provide an instruction_number.operand_name for each operand that appears
10664 // // in the replacement instruction's match rule
10665 //
10666 // ---------VM FLAGS---------------------------------------------------------
10667 //
10668 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10669 //
10670 // Each peephole rule is given an identifying number starting with zero and
10671 // increasing by one in the order seen by the parser. An individual peephole
10672 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10673 // on the command-line.
10674 //
10675 // ---------CURRENT LIMITATIONS----------------------------------------------
10676 //
10677 // Only match adjacent instructions in same basic block
10678 // Only equality constraints
10679 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10680 // Only one replacement instruction
10681 //
10682 // ---------EXAMPLE----------------------------------------------------------
10683 //
10684 // // pertinent parts of existing instructions in architecture description
10685 // instruct movI(eRegI dst, eRegI src) %{
10686 // match(Set dst (CopyI src));
10687 // %}
10688 //
10689 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10690 // match(Set dst (AddI dst src));
10691 // effect(KILL cr);
10692 // %}
10693 //
10694 // // Change (inc mov) to lea
10695 // peephole %{
10696 // // increment preceded by register-register move
10697 // peepmatch (incI_eReg movI);
10698 // // require that the destination register of the increment
10699 // // match the destination register of the move
10700 // peepconstraint (0.dst == 1.dst);
10701 // // construct a replacement instruction that sets
10702 // // the destination to (move's source register + one)
10703 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10704 // %}
10705 //
10706 // Implementation no longer uses movX instructions since
10707 // machine-independent system no longer uses CopyX nodes.
10708 //
10709 // peephole %{
10710 // peepmatch (incI_eReg movI);
10711 // peepconstraint (0.dst == 1.dst);
10712 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10713 // %}
10714 //
10715 // peephole %{
10716 // peepmatch (decI_eReg movI);
10717 // peepconstraint (0.dst == 1.dst);
10718 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10719 // %}
10720 //
10721 // peephole %{
10722 // peepmatch (addI_eReg_imm movI);
10723 // peepconstraint (0.dst == 1.dst);
10724 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10725 // %}
10726 //
10727 // peephole %{
10728 // peepmatch (addP_eReg_imm movP);
10729 // peepconstraint (0.dst == 1.dst);
10730 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10731 // %}
10732
10733
10734 // This peephole rule does not work, probably because ADLC can't handle two effects:
10735 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10736 // condense a load from memory and subsequent test for zero
10737 // into a single, more efficient ICM instruction.
10738 // peephole %{
10739 // peepmatch (compI_iReg_imm0 loadI);
10740 // peepconstraint (1.dst == 0.op1);
10741 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10742 // %}
10743
10744 // // Change load of spilled value to only a spill
10745 // instruct storeI(memory mem, eRegI src) %{
10746 // match(Set mem (StoreI mem src));
10747 // %}
10748 //
10749 // instruct loadI(eRegI dst, memory mem) %{
10750 // match(Set dst (LoadI mem));
10751 // %}
10752 //
10753 peephole %{
10754 peepmatch (loadI storeI);
10755 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10756 peepreplace (storeI(1.mem 1.mem 1.src));
10757 %}
10758
10759 peephole %{
10760 peepmatch (loadL storeL);
10761 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10762 peepreplace (storeL(1.mem 1.mem 1.src));
10763 %}
10764
10765 peephole %{
10766 peepmatch (loadP storeP);
10767 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10768 peepreplace (storeP(1.dst 1.dst 1.src));
10769 %}
10770
10771 //----------SUPERWORD RULES---------------------------------------------------
10772
10773 // Expand rules for special cases
10774
10775 instruct expand_storeF(stackSlotF mem, regF src) %{
10776 // No match rule, false predicate, for expand only.
10777 effect(DEF mem, USE src);
10778 predicate(false);
10779 ins_cost(MEMORY_REF_COST);
10780 // TODO: s390 port size(FIXED_SIZE);
10781 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10782 opcode(STE_ZOPC, STE_ZOPC);
10783 ins_encode(z_form_rt_mem(src, mem));
10784 ins_pipe(pipe_class_dummy);
10785 %}
10786
10787 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10788 // No match rule, false predicate, for expand only.
10789 effect(DEF dst, USE mem);
10790 predicate(false);
10791 ins_cost(MEMORY_REF_COST);
10792 // TODO: s390 port size(FIXED_SIZE);
10793 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10794 opcode(LLGF_ZOPC, LLGF_ZOPC);
10795 ins_encode(z_form_rt_mem(dst, mem));
10796 ins_pipe(pipe_class_dummy);
10797 %}
10798
10799 // Replicate scalar int to packed int values (8 Bytes)
10800 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10801 // Dummy match rule, false predicate, for expand only.
10802 match(Set dst (ConvI2L src));
10803 predicate(false);
10804 ins_cost(DEFAULT_COST);
10805 // TODO: s390 port size(FIXED_SIZE);
10806 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10807 ins_encode %{
10808 if ($dst$$Register == $src$$Register) {
10809 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10810 __ z_ogr($dst$$Register, Z_R0_scratch);
10811 } else {
10812 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10813 __ z_ogr( $dst$$Register, $src$$Register);
10814 }
10815 %}
10816 ins_pipe(pipe_class_dummy);
10817 %}
10818
10819 // Replication
10820
10821 // Exploit rotate_then_insert, if available
10822 // Replicate scalar byte to packed byte values (8 Bytes).
10823 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10824 match(Set dst (Replicate src));
10825 effect(KILL cr);
10826 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10827 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10828 ins_encode %{
10829 if ($dst$$Register != $src$$Register) {
10830 __ z_lgr($dst$$Register, $src$$Register);
10831 }
10832 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10833 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10834 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10835 %}
10836 ins_pipe(pipe_class_dummy);
10837 %}
10838
10839 // Replicate scalar byte to packed byte values (8 Bytes).
10840 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10841 match(Set dst (Replicate src));
10842 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10843 ins_should_rematerialize(true);
10844 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10845 ins_encode %{
10846 int64_t Isrc8 = $src$$constant & 0x000000ff;
10847 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10848 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10849 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10850
10851 __ z_llilf($dst$$Register, Isrc32);
10852 __ z_iihf($dst$$Register, Isrc32);
10853 %}
10854 ins_pipe(pipe_class_dummy);
10855 %}
10856
10857 // Replicate scalar byte to packed byte values (8 Bytes).
10858 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10859 match(Set dst (Replicate src));
10860 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10861 ins_should_rematerialize(true);
10862 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10863 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10864 ins_pipe(pipe_class_dummy);
10865 %}
10866
10867 // Replicate scalar byte to packed byte values (8 Bytes).
10868 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10869 match(Set dst (Replicate src));
10870 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10871 ins_should_rematerialize(true);
10872 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10873 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10874 ins_pipe(pipe_class_dummy);
10875 %}
10876
10877 // Exploit rotate_then_insert, if available
10878 // Replicate scalar short to packed short values (8 Bytes).
10879 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10880 match(Set dst (Replicate src));
10881 effect(KILL cr);
10882 predicate((n->as_Vector()->length() == 4) && Matcher::vector_element_basic_type(n) == T_SHORT);
10883 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10884 ins_encode %{
10885 if ($dst$$Register != $src$$Register) {
10886 __ z_lgr($dst$$Register, $src$$Register);
10887 }
10888 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10889 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10890 %}
10891 ins_pipe(pipe_class_dummy);
10892 %}
10893
10894 // Replicate scalar short to packed short values (8 Bytes).
10895 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10896 match(Set dst (Replicate src));
10897 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10898 ins_should_rematerialize(true);
10899 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10900 ins_encode %{
10901 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10902 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10903 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10904 ") should be handled by other match rules.", $src$$constant);
10905
10906 __ z_llilf($dst$$Register, Isrc32);
10907 __ z_iihf($dst$$Register, Isrc32);
10908 %}
10909 ins_pipe(pipe_class_dummy);
10910 %}
10911
10912 // Replicate scalar short to packed short values (8 Bytes).
10913 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10914 match(Set dst (Replicate src));
10915 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10916 ins_should_rematerialize(true);
10917 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10918 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10919 ins_pipe(pipe_class_dummy);
10920 %}
10921
10922 // Replicate scalar short to packed short values (8 Bytes).
10923 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10924 match(Set dst (Replicate src));
10925 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10926 ins_should_rematerialize(true);
10927 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10928 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10929 ins_pipe(pipe_class_dummy);
10930 %}
10931
10932 instruct repl8S_reg_Ex(vecX dst, iRegI src) %{
10933 match(Set dst (Replicate src));
10934 predicate(n->as_Vector()->length() == 8 &&
10935 Matcher::vector_element_basic_type(n) == T_SHORT);
10936
10937 size(12);
10938 ins_encode %{
10939 __ z_vlvgh($dst$$VectorRegister, $src$$Register, 0);
10940 __ z_vreph($dst$$VectorRegister, $dst$$VectorRegister, 0);
10941 %}
10942 ins_pipe(pipe_class_dummy);
10943 %}
10944
10945 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
10946 match(Set dst (Replicate src));
10947 predicate(n->as_Vector()->length() == 8 &&
10948 Matcher::vector_element_basic_type(n) == T_SHORT);
10949
10950 format %{ "VONE $dst, $src \t// replicate8S" %}
10951 size(6);
10952 ins_encode %{
10953 __ z_vone($dst$$VectorRegister);
10954 %}
10955 ins_pipe(pipe_class_dummy);
10956 %}
10957
10958 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
10959 match(Set dst (Replicate zero));
10960 predicate(n->as_Vector()->length() == 8 &&
10961 Matcher::vector_element_basic_type(n) == T_SHORT);
10962
10963 format %{ "VZERO $dst, $zero \t// replicate8S" %}
10964 size(6);
10965 ins_encode %{
10966 __ z_vzero($dst$$VectorRegister);
10967 %}
10968 ins_pipe(pipe_class_dummy);
10969 %}
10970
10971 // Exploit rotate_then_insert, if available.
10972 // Replicate scalar int to packed int values (8 Bytes).
10973 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10974 match(Set dst (Replicate src));
10975 effect(KILL cr);
10976 predicate((n->as_Vector()->length() == 2) && Matcher::vector_element_basic_type(n) == T_INT);
10977 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10978 ins_encode %{
10979 if ($dst$$Register != $src$$Register) {
10980 __ z_lgr($dst$$Register, $src$$Register);
10981 }
10982 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10983 %}
10984 ins_pipe(pipe_class_dummy);
10985 %}
10986
10987 // Replicate scalar int to packed int values (8 Bytes).
10988 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10989 match(Set dst (Replicate src));
10990 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
10991 ins_should_rematerialize(true);
10992 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10993 ins_encode %{
10994 int64_t Isrc32 = $src$$constant;
10995 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10996
10997 __ z_llilf($dst$$Register, Isrc32);
10998 __ z_iihf($dst$$Register, Isrc32);
10999 %}
11000 ins_pipe(pipe_class_dummy);
11001 %}
11002
11003 // Replicate scalar int to packed int values (8 Bytes).
11004 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
11005 match(Set dst (Replicate src));
11006 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11007 ins_should_rematerialize(true);
11008 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
11009 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11010 ins_pipe(pipe_class_dummy);
11011 %}
11012
11013 // Replicate scalar int to packed int values (8 Bytes).
11014 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
11015 match(Set dst (Replicate src));
11016 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11017 ins_should_rematerialize(true);
11018 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
11019 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
11020 ins_pipe(pipe_class_dummy);
11021 %}
11022
11023 instruct repl4I_reg_Ex(vecX dst, iRegI src) %{
11024 match(Set dst (Replicate src));
11025 predicate(n->as_Vector()->length() == 4 &&
11026 Matcher::vector_element_basic_type(n) == T_INT);
11027
11028 size(12);
11029 ins_encode %{
11030 __ z_vlvgf($dst$$VectorRegister, $src$$Register, 0);
11031 __ z_vrepf($dst$$VectorRegister, $dst$$VectorRegister, 0);
11032 %}
11033 ins_pipe(pipe_class_dummy);
11034 %}
11035
11036 instruct repl4I_immI0(vecX dst, immI_0 zero) %{
11037 match(Set dst (Replicate zero));
11038 predicate(n->as_Vector()->length() == 4 &&
11039 Matcher::vector_element_basic_type(n) == T_INT);
11040
11041 format %{ "VZERO $dst, $zero \t// replicate4I" %}
11042 size(6);
11043 ins_encode %{
11044 __ z_vzero($dst$$VectorRegister);
11045 %}
11046 ins_pipe(pipe_class_dummy);
11047 %}
11048
11049 instruct repl4I_immIminus1(vecX dst, immI_minus1 src) %{
11050 match(Set dst (Replicate src));
11051 predicate(n->as_Vector()->length() == 4 &&
11052 Matcher::vector_element_basic_type(n) == T_INT);
11053
11054 format %{ "VONE $dst, $dst, $dst \t// replicate4I" %}
11055 size(6);
11056 ins_encode %{
11057 __ z_vone($dst$$VectorRegister);
11058 %}
11059 ins_pipe(pipe_class_dummy);
11060 %}
11061
11062 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
11063 match(Set dst (Replicate src));
11064 effect(KILL cr);
11065 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11066 Matcher::vector_element_basic_type(n) == T_FLOAT);
11067 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
11068 expand %{
11069 stackSlotF tmp;
11070 iRegL tmp2;
11071 expand_storeF(tmp, src);
11072 expand_LoadLogical_I2L(tmp2, tmp);
11073 expand_Repl2I_reg(dst, tmp2);
11074 %}
11075 %}
11076
11077 // Replicate scalar float to packed float values in GREG (8 Bytes).
11078 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
11079 match(Set dst (Replicate src));
11080 effect(KILL cr);
11081 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11082 Matcher::vector_element_basic_type(n) == T_FLOAT);
11083 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
11084 ins_encode %{
11085 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
11086 __ z_lgdr($dst$$Register, $src$$FloatRegister);
11087
11088 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
11089 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
11090 __ z_ogr($dst$$Register, Z_R0_scratch);
11091 %}
11092 ins_pipe(pipe_class_dummy);
11093 %}
11094
11095 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
11096 instruct Repl2F_imm(iRegL dst, immF src) %{
11097 match(Set dst (Replicate src));
11098 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11099 ins_should_rematerialize(true);
11100 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
11101 ins_encode %{
11102 union {
11103 int Isrc32;
11104 float Fsrc32;
11105 };
11106 Fsrc32 = $src$$constant;
11107 __ z_llilf($dst$$Register, Isrc32);
11108 __ z_iihf($dst$$Register, Isrc32);
11109 %}
11110 ins_pipe(pipe_class_dummy);
11111 %}
11112
11113 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
11114 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
11115 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
11116 match(Set dst (Replicate src));
11117 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11118 ins_should_rematerialize(true);
11119 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
11120 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11121 ins_pipe(pipe_class_dummy);
11122 %}
11123
11124 instruct repl4F_reg_Ex(vecX dst, regF src) %{
11125 match(Set dst (Replicate src));
11126 predicate(n->as_Vector()->length() == 4 &&
11127 Matcher::vector_element_basic_type(n) == T_FLOAT);
11128
11129 format %{ "VREP $dst, $src \t// replicate4F" %}
11130 size(6);
11131
11132 ins_encode %{
11133 __ z_vrepf($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11134 %}
11135 ins_pipe(pipe_class_dummy);
11136 %}
11137
11138 instruct repl4F_immF0(vecX dst, immFp0 zero) %{
11139 match(Set dst (Replicate zero));
11140 predicate(n->as_Vector()->length() == 4 &&
11141 Matcher::vector_element_basic_type(n) == T_FLOAT);
11142
11143 format %{ "VZERO $dst, $zero \t// replicate4F" %}
11144 size(6);
11145 ins_encode %{
11146 __ z_vzero($dst$$VectorRegister);
11147 %}
11148 ins_pipe(pipe_class_dummy);
11149 %}
11150
11151 instruct repl2D_reg_Ex(vecX dst, regD src) %{
11152 match(Set dst (Replicate src));
11153 predicate(n->as_Vector()->length() == 2 &&
11154 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11155
11156 format %{ "VREP $dst, $src \t// replicate2D" %}
11157 size(6);
11158
11159 ins_encode %{
11160 __ z_vrepg($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11161 %}
11162 ins_pipe(pipe_class_dummy);
11163 %}
11164
11165 instruct repl2D_immD0(vecX dst, immDp0 zero) %{
11166 match(Set dst (Replicate zero));
11167 predicate(n->as_Vector()->length() == 2 &&
11168 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11169
11170 format %{ "VZERO $dst, $zero \t// replicate2D" %}
11171 size(6);
11172 ins_encode %{
11173 __ z_vzero($dst$$VectorRegister);
11174 %}
11175 ins_pipe(pipe_class_dummy);
11176 %}
11177
11178 instruct repl16B_reg_Ex(vecX dst, iRegI src) %{
11179 match(Set dst (Replicate src));
11180 predicate(n->as_Vector()->length() == 16 &&
11181 Matcher::vector_element_basic_type(n) == T_BYTE);
11182
11183 size(12);
11184 ins_encode %{
11185 __ z_vlvgb($dst$$VectorRegister, $src$$Register, 0);
11186 __ z_vrepb($dst$$VectorRegister, $dst$$VectorRegister, 0);
11187 %}
11188 ins_pipe(pipe_class_dummy);
11189 %}
11190
11191 instruct repl16B_immIminus1(vecX dst, immI_minus1 src) %{
11192 match(Set dst (Replicate src));
11193 predicate(n->as_Vector()->length() == 16 &&
11194 Matcher::vector_element_basic_type(n) == T_BYTE);
11195
11196 format %{ "VONE $dst, $src \t// replicate16B" %}
11197 size(6);
11198 ins_encode %{
11199 __ z_vone($dst$$VectorRegister);
11200 %}
11201 ins_pipe(pipe_class_dummy);
11202 %}
11203
11204 instruct repl16B_immI0(vecX dst, immI_0 zero) %{
11205 match(Set dst (Replicate zero));
11206 predicate(n->as_Vector()->length() == 16 &&
11207 Matcher::vector_element_basic_type(n) == T_BYTE);
11208
11209 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11210 size(6);
11211 ins_encode %{
11212 __ z_vzero($dst$$VectorRegister);
11213 %}
11214 ins_pipe(pipe_class_dummy);
11215 %}
11216
11217 instruct repl2L_reg_Ex(vecX dst, iRegL src) %{
11218 match(Set dst (Replicate src));
11219 predicate(n->as_Vector()->length() == 2 &&
11220 Matcher::vector_element_basic_type(n) == T_LONG);
11221
11222 size(12);
11223 ins_encode %{
11224 __ z_vlvgg($dst$$VectorRegister, $src$$Register, 0);
11225 __ z_vrepg($dst$$VectorRegister, $dst$$VectorRegister, 0);
11226 %}
11227 ins_pipe(pipe_class_dummy);
11228 %}
11229
11230 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
11231 match(Set dst (Replicate src));
11232 predicate(n->as_Vector()->length() == 2 &&
11233 Matcher::vector_element_basic_type(n) == T_LONG);
11234
11235 format %{ "VONE $dst, $src \t// replicate2L" %}
11236 size(6);
11237 ins_encode %{
11238 __ z_vone($dst$$VectorRegister);
11239 %}
11240 ins_pipe(pipe_class_dummy);
11241 %}
11242
11243 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
11244 match(Set dst (Replicate zero));
11245 predicate(n->as_Vector()->length() == 2 &&
11246 Matcher::vector_element_basic_type(n) == T_LONG);
11247
11248 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11249 size(6);
11250 ins_encode %{
11251 __ z_vzero($dst$$VectorRegister);
11252 %}
11253 ins_pipe(pipe_class_dummy);
11254 %}
11255
11256
11257 // Load/Store vector
11258
11259 // Store Aligned Packed Byte register to memory (8 Bytes).
11260 instruct storeA8B(memory mem, iRegL src) %{
11261 match(Set mem (StoreVector mem src));
11262 predicate(n->as_StoreVector()->memory_size() == 8);
11263 ins_cost(MEMORY_REF_COST);
11264 // TODO: s390 port size(VARIABLE_SIZE);
11265 format %{ "STG $src,$mem\t # ST(packed8B)" %}
11266 opcode(STG_ZOPC, STG_ZOPC);
11267 ins_encode(z_form_rt_mem_opt(src, mem));
11268 ins_pipe(pipe_class_dummy);
11269 %}
11270
11271 // Store Packed Byte long register to memory
11272 instruct storeV16(memoryRX mem, vecX src) %{
11273 predicate(n->as_StoreVector()->memory_size() == 16);
11274 match(Set mem (StoreVector mem src));
11275 ins_cost(MEMORY_REF_COST);
11276
11277 format %{ "VST $mem, $src \t// store 16-byte Vector" %}
11278 size(6);
11279 ins_encode %{
11280 __ z_vst($src$$VectorRegister,
11281 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11282 %}
11283 ins_pipe(pipe_class_dummy);
11284 %}
11285
11286 instruct loadV8(iRegL dst, memory mem) %{
11287 match(Set dst (LoadVector mem));
11288 predicate(n->as_LoadVector()->memory_size() == 8);
11289 ins_cost(MEMORY_REF_COST);
11290 // TODO: s390 port size(VARIABLE_SIZE);
11291 format %{ "LG $dst,$mem\t # L(packed8B)" %}
11292 opcode(LG_ZOPC, LG_ZOPC);
11293 ins_encode(z_form_rt_mem_opt(dst, mem));
11294 ins_pipe(pipe_class_dummy);
11295 %}
11296
11297 // Load Aligned Packed Byte
11298 instruct loadV16(vecX dst, memoryRX mem) %{
11299 predicate(n->as_LoadVector()->memory_size() == 16);
11300 match(Set dst (LoadVector mem));
11301 ins_cost(MEMORY_REF_COST);
11302
11303 format %{ "VL $dst, $mem \t// load 16-byte Vector" %}
11304 size(6);
11305 ins_encode %{
11306 __ z_vl($dst$$VectorRegister,
11307 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11308 %}
11309 ins_pipe(pipe_class_dummy);
11310 %}
11311
11312 // Reinterpret: only one vector size used
11313 instruct reinterpret(iRegL dst) %{
11314 match(Set dst (VectorReinterpret dst));
11315 ins_cost(0);
11316 format %{ "reinterpret $dst" %}
11317 ins_encode( /*empty*/ );
11318 ins_pipe(pipe_class_dummy);
11319 %}
11320
11321 instruct reinterpretX(vecX dst) %{
11322 match(Set dst (VectorReinterpret dst));
11323 ins_cost(0);
11324 format %{ "reinterpret $dst" %}
11325 ins_encode( /*empty*/ );
11326 ins_pipe(pipe_class_dummy);
11327 %}
11328
11329 //----------Vector Arithmetic Instructions--------------------------------------
11330
11331 // Vector Addition Instructions
11332
11333 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
11334 match(Set dst (AddVB src1 src2));
11335 predicate(n->as_Vector()->length() == 16);
11336 format %{ "VAB $dst,$src1,$src2\t// add packed16B" %}
11337 size(6);
11338 ins_encode %{
11339 __ z_vab($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11340 %}
11341 ins_pipe(pipe_class_dummy);
11342 %}
11343
11344 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
11345 match(Set dst (AddVS src1 src2));
11346 predicate(n->as_Vector()->length() == 8);
11347 format %{ "VAH $dst,$src1,$src2\t// add packed8S" %}
11348 size(6);
11349 ins_encode %{
11350 __ z_vah($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11351 %}
11352 ins_pipe(pipe_class_dummy);
11353 %}
11354
11355 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
11356 match(Set dst (AddVI src1 src2));
11357 predicate(n->as_Vector()->length() == 4);
11358 format %{ "VAF $dst,$src1,$src2\t// add packed4I" %}
11359 size(6);
11360 ins_encode %{
11361 __ z_vaf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11362 %}
11363 ins_pipe(pipe_class_dummy);
11364 %}
11365
11366 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
11367 match(Set dst (AddVL src1 src2));
11368 predicate(n->as_Vector()->length() == 2);
11369 format %{ "VAG $dst,$src1,$src2\t// add packed2L" %}
11370 size(6);
11371 ins_encode %{
11372 __ z_vag($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11373 %}
11374 ins_pipe(pipe_class_dummy);
11375 %}
11376
11377 instruct vmul16B_reg(vecX dst, vecX src1, vecX src2) %{
11378 match(Set dst (MulVB src1 src2));
11379 predicate(n->as_Vector()->length() == 16);
11380 format %{ "VMLB $dst,$src1,$src2\t// mul packed16B" %}
11381 size(6);
11382 ins_encode %{
11383 __ z_vmlb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11384 %}
11385 ins_pipe(pipe_class_dummy);
11386 %}
11387
11388 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2) %{
11389 match(Set dst (MulVS src1 src2));
11390 predicate(n->as_Vector()->length() == 8);
11391 format %{ "VMLHW $dst,$src1,$src2\t// mul packed8S" %}
11392 size(6);
11393 ins_encode %{
11394 __ z_vmlhw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11395 %}
11396 ins_pipe(pipe_class_dummy);
11397 %}
11398
11399 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
11400 match(Set dst (MulVI src1 src2));
11401 predicate(n->as_Vector()->length() == 4);
11402 format %{ "VMLF $dst,$src1,$src2\t// mul packed4I" %}
11403 size(6);
11404 ins_encode %{
11405 __ z_vmlf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11406 %}
11407 ins_pipe(pipe_class_dummy);
11408 %}
11409
11410 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
11411 match(Set dst (SubVB src1 src2));
11412 predicate(n->as_Vector()->length() == 16);
11413 format %{ "VSB $dst,$src1,$src2\t// sub packed16B" %}
11414 size(6);
11415 ins_encode %{
11416 __ z_vsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11417 %}
11418 ins_pipe(pipe_class_dummy);
11419 %}
11420
11421 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
11422 match(Set dst (SubVS src1 src2));
11423 predicate(n->as_Vector()->length() == 8);
11424 format %{ "VSH $dst,$src1,$src2\t// sub packed8S" %}
11425 size(6);
11426 ins_encode %{
11427 __ z_vsh($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11428 %}
11429 ins_pipe(pipe_class_dummy);
11430 %}
11431
11432 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
11433 match(Set dst (SubVI src1 src2));
11434 predicate(n->as_Vector()->length() == 4);
11435 format %{ "VSF $dst,$src1,$src2\t// sub packed4I" %}
11436 size(6);
11437 ins_encode %{
11438 __ z_vsf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11439 %}
11440 ins_pipe(pipe_class_dummy);
11441 %}
11442
11443 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
11444 match(Set dst (SubVL src1 src2));
11445 predicate(n->as_Vector()->length() == 2);
11446 format %{ "VSG $dst,$src1,$src2\t// sub packed2L" %}
11447 size(6);
11448 ins_encode %{
11449 __ z_vsg($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11450 %}
11451 ins_pipe(pipe_class_dummy);
11452 %}
11453
11454 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
11455 match(Set dst (AddVF src1 src2));
11456 predicate(n->as_Vector()->length() == 4);
11457 format %{ "VFASB $dst,$src1,$src2\t// add packed4F" %}
11458 size(6);
11459 ins_encode %{
11460 __ z_vfasb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11461 %}
11462 ins_pipe(pipe_class_dummy);
11463 %}
11464
11465 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
11466 match(Set dst (AddVD src1 src2));
11467 predicate(n->as_Vector()->length() == 2);
11468 format %{ "VFADB $dst,$src1,$src2\t// add packed2D" %}
11469 size(6);
11470 ins_encode %{
11471 __ z_vfadb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11472 %}
11473 ins_pipe(pipe_class_dummy);
11474 %}
11475
11476 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
11477 match(Set dst (SubVF src1 src2));
11478 predicate(n->as_Vector()->length() == 4);
11479 format %{ "VFSSB $dst,$src1,$src2\t// sub packed4F" %}
11480 size(6);
11481 ins_encode %{
11482 __ z_vfssb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11483 %}
11484 ins_pipe(pipe_class_dummy);
11485 %}
11486
11487 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
11488 match(Set dst (SubVD src1 src2));
11489 predicate(n->as_Vector()->length() == 2);
11490 format %{ "VFSDB $dst,$src1,$src2\t// sub packed2D" %}
11491 size(6);
11492 ins_encode %{
11493 __ z_vfsdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11494 %}
11495 ins_pipe(pipe_class_dummy);
11496 %}
11497
11498 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
11499 match(Set dst (MulVF src1 src2));
11500 predicate(n->as_Vector()->length() == 4);
11501 format %{ "VFMSB $dst,$src1,$src2\t// mul packed4F" %}
11502 size(6);
11503 ins_encode %{
11504 __ z_vfmsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11505 %}
11506 ins_pipe(pipe_class_dummy);
11507 %}
11508
11509 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
11510 match(Set dst (MulVD src1 src2));
11511 predicate(n->as_Vector()->length() == 2);
11512 format %{ "VFMDB $dst,$src1,$src2\t// mul packed2D" %}
11513 size(6);
11514 ins_encode %{
11515 __ z_vfmdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11516 %}
11517 ins_pipe(pipe_class_dummy);
11518 %}
11519
11520 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
11521 match(Set dst (DivVF src1 src2));
11522 predicate(n->as_Vector()->length() == 4);
11523 format %{ "VFDSB $dst,$src1,$src2\t// div packed4F" %}
11524 size(6);
11525 ins_encode %{
11526 __ z_vfdsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11527 %}
11528 ins_pipe(pipe_class_dummy);
11529 %}
11530
11531 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
11532 match(Set dst (DivVD src1 src2));
11533 predicate(n->as_Vector()->length() == 2);
11534 format %{ "VFDDB $dst,$src1,$src2\t// div packed2D" %}
11535 size(6);
11536 ins_encode %{
11537 __ z_vfddb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11538 %}
11539 ins_pipe(pipe_class_dummy);
11540 %}
11541
11542 // Vector Square Root Instructions
11543
11544 instruct vsqrt4F_reg(vecX dst, vecX src) %{
11545 match(Set dst (SqrtVF src));
11546 predicate(n->as_Vector()->length() == 4);
11547 format %{ "VFSQSB $dst,$src\t// sqrt packed4F" %}
11548 size(6);
11549 ins_encode %{
11550 __ z_vfsqsb($dst$$VectorRegister, $src$$VectorRegister);
11551 %}
11552 ins_pipe(pipe_class_dummy);
11553 %}
11554
11555 instruct vsqrt2D_reg(vecX dst, vecX src) %{
11556 match(Set dst (SqrtVD src));
11557 predicate(n->as_Vector()->length() == 2);
11558 format %{ "VFSQDB $dst,$src\t// sqrt packed2D" %}
11559 size(6);
11560 ins_encode %{
11561 __ z_vfsqdb($dst$$VectorRegister, $src$$VectorRegister);
11562 %}
11563 ins_pipe(pipe_class_dummy);
11564 %}
11565
11566 // Vector Population Count Instructions
11567
11568 instruct vpopcnt_reg(vecX dst, vecX src) %{
11569 match(Set dst (PopCountVI src));
11570 format %{ "VPOPCT $dst,$src\t// pop count packed" %}
11571 size(6);
11572 ins_encode %{
11573 BasicType bt = Matcher::vector_element_basic_type(this);
11574 switch (bt) {
11575 case T_BYTE:
11576 __ z_vpopctb($dst$$VectorRegister, $src$$VectorRegister);
11577 break;
11578 case T_SHORT:
11579 __ z_vpopcth($dst$$VectorRegister, $src$$VectorRegister);
11580 break;
11581 case T_INT:
11582 __ z_vpopctf($dst$$VectorRegister, $src$$VectorRegister);
11583 break;
11584 case T_LONG:
11585 __ z_vpopctg($dst$$VectorRegister, $src$$VectorRegister);
11586 break;
11587 default:
11588 ShouldNotReachHere();
11589 }
11590 %}
11591 ins_pipe(pipe_class_dummy);
11592 %}
11593
11594 // Vector Round Instructions
11595 instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
11596 match(Set dst (RoundDoubleModeV src rmode));
11597 predicate(n->as_Vector()->length() == 2);
11598 format %{ "RoundDoubleModeV $src,$rmode" %}
11599 size(6);
11600 ins_encode %{
11601 switch ($rmode$$constant) {
11602 case RoundDoubleModeNode::rmode_rint:
11603 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 0);
11604 break;
11605 case RoundDoubleModeNode::rmode_floor:
11606 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 7);
11607 break;
11608 case RoundDoubleModeNode::rmode_ceil:
11609 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 6);
11610 break;
11611 default:
11612 ShouldNotReachHere();
11613 }
11614 %}
11615 ins_pipe(pipe_class_dummy);
11616 %}
11617
11618 //----------POPULATION COUNT RULES--------------------------------------------
11619
11620 // Byte reverse
11621
11622 instruct bytes_reverse_short(iRegI dst, iRegI src) %{
11623 match(Set dst (ReverseBytesS src));
11624 predicate(UseByteReverseInstruction);
11625 ins_cost(2 * DEFAULT_COST);
11626 size(8);
11627
11628 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11629 "SRA $dst, 0x0010\t # right shift by 16, sign extended" %}
11630
11631 ins_encode %{
11632 __ z_lrvr($dst$$Register, $src$$Register);
11633 __ z_sra($dst$$Register, 0x0010);
11634 %}
11635 ins_pipe(pipe_class_dummy);
11636 %}
11637
11638 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
11639 match(Set dst (ReverseBytesUS src));
11640 predicate(UseByteReverseInstruction);
11641 ins_cost(2 * DEFAULT_COST);
11642 size(8);
11643
11644 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11645 "SRL $dst, 0x0010\t # right shift by 16, zero extended" %}
11646
11647 ins_encode %{
11648 __ z_lrvr($dst$$Register, $src$$Register);
11649 __ z_srl($dst$$Register, 0x0010);
11650 %}
11651 ins_pipe(pipe_class_dummy);
11652 %}
11653
11654 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
11655 match(Set dst (ReverseBytesI src));
11656 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11657 ins_cost(DEFAULT_COST);
11658 size(4);
11659 format %{ "LRVR $dst,$src\t # byte reverse int" %}
11660 opcode(LRVR_ZOPC);
11661 ins_encode(z_rreform(dst, src));
11662 ins_pipe(pipe_class_dummy);
11663 %}
11664
11665 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
11666 match(Set dst (ReverseBytesL src));
11667 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11668 ins_cost(DEFAULT_COST);
11669 // TODO: s390 port size(FIXED_SIZE);
11670 format %{ "LRVGR $dst,$src\t # byte reverse long" %}
11671 opcode(LRVGR_ZOPC);
11672 ins_encode(z_rreform(dst, src));
11673 ins_pipe(pipe_class_dummy);
11674 %}
11675
11676 // Leading zeroes
11677
11678 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
11679 // returns the bit position of the leftmost 1 in the 64bit source register.
11680 // As the bits are numbered from left to right (0..63), the returned
11681 // position index is equivalent to the number of leading zeroes.
11682 // If no 1-bit is found (i.e. the register contains zero), the instruction
11683 // returns position 64. That's exactly what we need.
11684
11685 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11686 match(Set dst (CountLeadingZerosI src));
11687 effect(KILL tmp, KILL cr);
11688 ins_cost(3 * DEFAULT_COST);
11689 size(14);
11690 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
11691 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
11692 "FLOGR $dst,$dst"
11693 %}
11694 ins_encode %{
11695 // Performance experiments indicate that "FLOGR" is using some kind of
11696 // iteration to find the leftmost "1" bit.
11697 //
11698 // The prior implementation zero-extended the 32-bit argument to 64 bit,
11699 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
11700 // We could gain measurable speedup in micro benchmark:
11701 //
11702 // leading trailing
11703 // z10: int 2.04 1.68
11704 // long 1.00 1.02
11705 // z196: int 0.99 1.23
11706 // long 1.00 1.11
11707 //
11708 // By shifting the argument into the high-word instead of zero-extending it.
11709 // The add'l branch on condition (taken for a zero argument, very infrequent,
11710 // good prediction) is well compensated for by the savings.
11711 //
11712 // We leave the previous implementation in for some time in the future when
11713 // the "FLOGR" instruction may become less iterative.
11714
11715 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
11716 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
11717 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
11718 __ z_flogr($dst$$Register, $dst$$Register);
11719 %}
11720 ins_pipe(pipe_class_dummy);
11721 %}
11722
11723 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
11724 match(Set dst (CountLeadingZerosL src));
11725 effect(KILL tmp, KILL cr);
11726 ins_cost(DEFAULT_COST);
11727 size(4);
11728 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
11729 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
11730 ins_pipe(pipe_class_dummy);
11731 %}
11732
11733 // trailing zeroes
11734
11735 // We transform the trailing zeroes problem to a leading zeroes problem
11736 // such that can use the FLOGR instruction to our advantage.
11737
11738 // With
11739 // tmp1 = src - 1
11740 // we flip all trailing zeroes to ones and the rightmost one to zero.
11741 // All other bits remain unchanged.
11742 // With the complement
11743 // tmp2 = ~src
11744 // we get all ones in the trailing zeroes positions. Thus,
11745 // tmp3 = tmp1 & tmp2
11746 // yields ones in the trailing zeroes positions and zeroes elsewhere.
11747 // Now we can apply FLOGR and get 64-(trailing zeroes).
11748 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11749 match(Set dst (CountTrailingZerosI src));
11750 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11751 ins_cost(8 * DEFAULT_COST);
11752 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11753 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
11754 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t"
11755 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11756 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t"
11757 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t"
11758 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t"
11759 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11760 "LCR $dst,$dst \t # res = -tmp4"
11761 %}
11762 ins_encode %{
11763 Register Rdst = $dst$$Register;
11764 Register Rsrc = $src$$Register;
11765 // Rtmp only needed for for zero-argument shortcut. With kill effect in
11766 // match rule Rsrc = roddReg would be possible, saving one register.
11767 Register Rtmp = $tmp$$Register;
11768
11769 assert_different_registers(Rdst, Rsrc, Rtmp);
11770
11771 // Algorithm:
11772 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
11773 // All other bits in the result are zero.
11774 // - Find the "leftmost one" bit position in the single-bit result from previous step.
11775 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
11776
11777 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
11778 Label done;
11779 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
11780 __ z_lcgfr(Rtmp, Rsrc);
11781 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
11782
11783 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
11784 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
11785 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
11786 // into upper half of reg. Not relevant with sllg below.
11787 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
11788 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
11789 // Depends on CC set by ahi above.
11790 // Taken very infrequently, good prediction, no BHT entry.
11791 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
11792 // after SLLG Rdst == 0(64bit)).
11793 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11794 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
11795 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11796 __ bind(done);
11797 %}
11798 ins_pipe(pipe_class_dummy);
11799 %}
11800
11801 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
11802 match(Set dst (CountTrailingZerosL src));
11803 effect(TEMP_DEF dst, KILL tmp, KILL cr);
11804 ins_cost(8 * DEFAULT_COST);
11805 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11806 format %{ "LCGR $dst,$src \t # preserve src\n\t"
11807 "NGR $dst,$src \t #\n\t"
11808 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11809 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t"
11810 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11811 "LCR $dst,$dst \t #"
11812 %}
11813 ins_encode %{
11814 Register Rdst = $dst$$Register;
11815 Register Rsrc = $src$$Register;
11816 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
11817
11818 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
11819 __ z_lcgr(Rdst, Rsrc);
11820 __ z_ngr(Rdst, Rsrc);
11821 __ add2reg(Rdst, -1);
11822 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11823 __ add2reg(Rdst, -64);
11824 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11825 %}
11826 ins_pipe(pipe_class_dummy);
11827 %}
11828
11829
11830 // bit count
11831
11832 instruct popCountI_Ext3(iRegI dst, iRegI src, flagsReg cr) %{
11833 match(Set dst (PopCountI src));
11834 effect(TEMP_DEF dst, KILL cr);
11835 predicate(UsePopCountInstruction &&
11836 VM_Version::has_PopCount() &&
11837 VM_Version::has_MiscInstrExt3());
11838 ins_cost(DEFAULT_COST);
11839 size(8); // popcnt + llgfr
11840 format %{ "POPCNT $dst,$src\t # pop count int" %}
11841 ins_encode %{
11842 Register Rdst = $dst$$Register;
11843 Register Rsrc = $src$$Register;
11844
11845 __ pop_count_int_with_ext3(Rdst, Rsrc);
11846
11847 %}
11848 ins_pipe(pipe_class_dummy);
11849 %}
11850
11851 instruct popCountL_Ext3(iRegI dst, iRegL src, flagsReg cr) %{
11852 match(Set dst (PopCountL src));
11853 effect(TEMP_DEF dst, KILL cr);
11854 predicate(UsePopCountInstruction &&
11855 VM_Version::has_PopCount() &&
11856 VM_Version::has_MiscInstrExt3());
11857 ins_cost(DEFAULT_COST);
11858 size(4); // popcnt
11859 format %{ "POPCNT $dst,$src\t # pop count long" %}
11860 ins_encode %{
11861 Register Rdst = $dst$$Register;
11862 Register Rsrc = $src$$Register;
11863
11864 __ pop_count_long_with_ext3(Rdst, Rsrc);
11865 %}
11866 ins_pipe(pipe_class_dummy);
11867 %}
11868
11869 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
11870 match(Set dst (PopCountI src));
11871 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11872 predicate(UsePopCountInstruction &&
11873 VM_Version::has_PopCount() &&
11874 (!VM_Version::has_MiscInstrExt3()));
11875 ins_cost(DEFAULT_COST);
11876 size(24);
11877 format %{ "POPCNT $dst,$src\t # pop count int" %}
11878 ins_encode %{
11879 Register Rdst = $dst$$Register;
11880 Register Rsrc = $src$$Register;
11881 Register Rtmp = $tmp$$Register;
11882
11883 __ pop_count_int_without_ext3(Rdst, Rsrc, Rtmp);
11884
11885 %}
11886 ins_pipe(pipe_class_dummy);
11887 %}
11888
11889 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
11890 match(Set dst (PopCountL src));
11891 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11892 predicate(UsePopCountInstruction &&
11893 VM_Version::has_PopCount() &&
11894 (!VM_Version::has_MiscInstrExt3()));
11895 ins_cost(DEFAULT_COST);
11896 size(34);
11897 format %{ "POPCNT $dst,$src\t # pop count long" %}
11898 ins_encode %{
11899 Register Rdst = $dst$$Register;
11900 Register Rsrc = $src$$Register;
11901 Register Rtmp = $tmp$$Register;
11902
11903 __ pop_count_long_without_ext3(Rdst, Rsrc, Rtmp);
11904 %}
11905 ins_pipe(pipe_class_dummy);
11906 %}
11907
11908 //----------SMARTSPILL RULES---------------------------------------------------
11909 // These must follow all instruction definitions as they use the names
11910 // defined in the instructions definitions.
11911
11912 // ============================================================================
11913 // TYPE PROFILING RULES