1 //
2 // Copyright (c) 2017, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2017, 2024 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alignment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to continue at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // ----------------------------
101 // Integer/Long Registers
102 // ----------------------------
103
104 // z/Architecture has 16 64-bit integer registers.
105
106 // types: v = volatile, nv = non-volatile, s = system
107 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
108 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
109 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
110 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
111 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
112 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
113 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
114 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
115 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
116 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
117 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
118 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
119 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
120 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
121 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
122 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
123 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
124 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
125 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
126 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
127 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
128 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
129 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
130 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
131 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
132 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
133 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
134 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
135 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
136 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
137 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
138 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
139
140 // ----------------------------
141 // Float/Double Registers
142 // ----------------------------
143
144 // The rules of ADL require that double registers be defined in pairs.
145 // Each pair must be two 32-bit values, but not necessarily a pair of
146 // single float registers. In each pair, ADLC-assigned register numbers
147 // must be adjacent, with the lower number even. Finally, when the
148 // CPU stores such a register pair to memory, the word associated with
149 // the lower ADLC-assigned number must be stored to the lower address.
150
151 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
152 // or double precision floating-point value.
153
154 // types: v = volatile, nv = non-volatile, s = system
155 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
156 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
157 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
158 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
159 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
160 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
161 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
162 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
163 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
164 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
165 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
166 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
167 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
168 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
169 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
170 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
171 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
172 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
173 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
174 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
175 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
176 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
177 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
178 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
179 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
180 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
181 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
182 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
183 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
184 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
185 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
186 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
187
188 // ----------------------------
189 // Vector Registers
190 // ----------------------------
191 // 1st 16 VRs are aliases for the FPRs which are already defined above.
192 reg_def Z_VR0 ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
193 reg_def Z_VR0_H ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
194 reg_def Z_VR0_J ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
195 reg_def Z_VR0_K ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
196
197 reg_def Z_VR1 ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
198 reg_def Z_VR1_H ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
199 reg_def Z_VR1_J ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
200 reg_def Z_VR1_K ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
201
202 reg_def Z_VR2 ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
203 reg_def Z_VR2_H ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
204 reg_def Z_VR2_J ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
205 reg_def Z_VR2_K ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
206
207 reg_def Z_VR3 ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
208 reg_def Z_VR3_H ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
209 reg_def Z_VR3_J ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
210 reg_def Z_VR3_K ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
211
212 reg_def Z_VR4 ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
213 reg_def Z_VR4_H ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
214 reg_def Z_VR4_J ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
215 reg_def Z_VR4_K ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
216
217 reg_def Z_VR5 ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
218 reg_def Z_VR5_H ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
219 reg_def Z_VR5_J ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
220 reg_def Z_VR5_K ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
221
222 reg_def Z_VR6 ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
223 reg_def Z_VR6_H ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
224 reg_def Z_VR6_J ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
225 reg_def Z_VR6_K ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
226
227 reg_def Z_VR7 ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
228 reg_def Z_VR7_H ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
229 reg_def Z_VR7_J ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
230 reg_def Z_VR7_K ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
231
232 reg_def Z_VR8 ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
233 reg_def Z_VR8_H ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
234 reg_def Z_VR8_J ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
235 reg_def Z_VR8_K ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
236
237 reg_def Z_VR9 ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
238 reg_def Z_VR9_H ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
239 reg_def Z_VR9_J ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
240 reg_def Z_VR9_K ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
241
242 reg_def Z_VR10 ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
243 reg_def Z_VR10_H ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
244 reg_def Z_VR10_J ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
245 reg_def Z_VR10_K ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
246
247 reg_def Z_VR11 ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
248 reg_def Z_VR11_H ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
249 reg_def Z_VR11_J ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
250 reg_def Z_VR11_K ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
251
252 reg_def Z_VR12 ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
253 reg_def Z_VR12_H ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
254 reg_def Z_VR12_J ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
255 reg_def Z_VR12_K ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
256
257 reg_def Z_VR13 ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
258 reg_def Z_VR13_H ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
259 reg_def Z_VR13_J ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
260 reg_def Z_VR13_K ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
261
262 reg_def Z_VR14 ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
263 reg_def Z_VR14_H ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
264 reg_def Z_VR14_J ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
265 reg_def Z_VR14_K ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
266
267 reg_def Z_VR15 ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
268 reg_def Z_VR15_H ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
269 reg_def Z_VR15_J ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
270 reg_def Z_VR15_K ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
271
272 reg_def Z_VR16 ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg() );
273 reg_def Z_VR16_H ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next() );
274 reg_def Z_VR16_J ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(2) );
275 reg_def Z_VR16_K ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(3) );
276
277 reg_def Z_VR17 ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg() );
278 reg_def Z_VR17_H ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next() );
279 reg_def Z_VR17_J ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(2) );
280 reg_def Z_VR17_K ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(3) );
281
282 reg_def Z_VR18 ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg() );
283 reg_def Z_VR18_H ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next() );
284 reg_def Z_VR18_J ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(2) );
285 reg_def Z_VR18_K ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(3) );
286
287 reg_def Z_VR19 ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg() );
288 reg_def Z_VR19_H ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next() );
289 reg_def Z_VR19_J ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(2) );
290 reg_def Z_VR19_K ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(3) );
291
292 reg_def Z_VR20 ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg() );
293 reg_def Z_VR20_H ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next() );
294 reg_def Z_VR20_J ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(2) );
295 reg_def Z_VR20_K ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(3) );
296
297 reg_def Z_VR21 ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg() );
298 reg_def Z_VR21_H ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next() );
299 reg_def Z_VR21_J ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(2) );
300 reg_def Z_VR21_K ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(3) );
301
302 reg_def Z_VR22 ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg() );
303 reg_def Z_VR22_H ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next() );
304 reg_def Z_VR22_J ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(2) );
305 reg_def Z_VR22_K ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(3) );
306
307 reg_def Z_VR23 ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg() );
308 reg_def Z_VR23_H ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next() );
309 reg_def Z_VR23_J ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(2) );
310 reg_def Z_VR23_K ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(3) );
311
312 reg_def Z_VR24 ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg() );
313 reg_def Z_VR24_H ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next() );
314 reg_def Z_VR24_J ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(2) );
315 reg_def Z_VR24_K ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(3) );
316
317 reg_def Z_VR25 ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg() );
318 reg_def Z_VR25_H ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next() );
319 reg_def Z_VR25_J ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(2) );
320 reg_def Z_VR25_K ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(3) );
321
322 reg_def Z_VR26 ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg() );
323 reg_def Z_VR26_H ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next() );
324 reg_def Z_VR26_J ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(2) );
325 reg_def Z_VR26_K ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(3) );
326
327 reg_def Z_VR27 ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg() );
328 reg_def Z_VR27_H ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next() );
329 reg_def Z_VR27_J ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(2) );
330 reg_def Z_VR27_K ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(3) );
331
332 reg_def Z_VR28 ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg() );
333 reg_def Z_VR28_H ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next() );
334 reg_def Z_VR28_J ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(2) );
335 reg_def Z_VR28_K ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(3) );
336
337 reg_def Z_VR29 ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg() );
338 reg_def Z_VR29_H ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next() );
339 reg_def Z_VR29_J ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(2) );
340 reg_def Z_VR29_K ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(3) );
341
342 reg_def Z_VR30 ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg() );
343 reg_def Z_VR30_H ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next() );
344 reg_def Z_VR30_J ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(2) );
345 reg_def Z_VR30_K ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(3) );
346
347 reg_def Z_VR31 ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg() );
348 reg_def Z_VR31_H ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next() );
349 reg_def Z_VR31_J ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(2) );
350 reg_def Z_VR31_K ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(3) );
351 // Special Registers
352
353 // Condition Codes Flag Registers
354
355 // z/Architecture has the PSW (program status word) that contains
356 // (among other information) the condition code. We treat this
357 // part of the PSW as a condition register CR. It consists of 4
358 // bits. Floating point instructions influence the same condition register CR.
359
360 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
361
362 // Specify priority of register selection within phases of register
363 // allocation. Highest priority is first. A useful heuristic is to
364 // give registers a low priority when they are required by machine
365 // instructions, and choose no-save registers before save-on-call, and
366 // save-on-call before save-on-entry. Registers which participate in
367 // fix calling sequences should come last. Registers which are used
368 // as pairs must fall on an even boundary.
369
370 // It's worth about 1% on SPEC geomean to get this right.
371
372 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
373 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
374 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
375 // the same as Z_R3->encoding()! Furthermore, we cannot make any
376 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
377 // Additionally, the function
378 // static enum RC rc_class(OptoReg::Name reg)
379 // maps a given <register>_num value to its chunk type (except for flags)
380 // and its current implementation relies on chunk0 and chunk1 having a
381 // size of 64 each.
382
383 alloc_class chunk0(
384 // chunk0 contains *all* 32 integer registers halves.
385
386 // potential SOE regs
387 Z_R13,Z_R13_H,
388 Z_R12,Z_R12_H,
389 Z_R11,Z_R11_H,
390 Z_R10,Z_R10_H,
391
392 Z_R9,Z_R9_H,
393 Z_R8,Z_R8_H,
394 Z_R7,Z_R7_H,
395
396 Z_R1,Z_R1_H,
397 Z_R0,Z_R0_H,
398
399 // argument registers
400 Z_R6,Z_R6_H,
401 Z_R5,Z_R5_H,
402 Z_R4,Z_R4_H,
403 Z_R3,Z_R3_H,
404 Z_R2,Z_R2_H,
405
406 // special registers
407 Z_R14,Z_R14_H,
408 Z_R15,Z_R15_H
409 );
410
411 alloc_class chunk1(
412 // Chunk1 contains *all* 64 floating-point registers halves.
413
414 Z_F15,Z_F15_H,
415 Z_F14,Z_F14_H,
416 Z_F13,Z_F13_H,
417 Z_F12,Z_F12_H,
418 Z_F11,Z_F11_H,
419 Z_F10,Z_F10_H,
420 Z_F9,Z_F9_H,
421 Z_F8,Z_F8_H,
422 // scratch register
423 Z_F7,Z_F7_H,
424 Z_F5,Z_F5_H,
425 Z_F3,Z_F3_H,
426 Z_F1,Z_F1_H,
427 // argument registers
428 Z_F6,Z_F6_H,
429 Z_F4,Z_F4_H,
430 Z_F2,Z_F2_H,
431 Z_F0,Z_F0_H
432 );
433
434 alloc_class chunk2(
435 Z_VR0, Z_VR0_H, Z_VR0_J, Z_VR0_K,
436 Z_VR1, Z_VR1_H, Z_VR1_J, Z_VR1_K,
437 Z_VR2, Z_VR2_H, Z_VR2_J, Z_VR2_K,
438 Z_VR3, Z_VR3_H, Z_VR3_J, Z_VR3_K,
439 Z_VR4, Z_VR4_H, Z_VR4_J, Z_VR4_K,
440 Z_VR5, Z_VR5_H, Z_VR5_J, Z_VR5_K,
441 Z_VR6, Z_VR6_H, Z_VR6_J, Z_VR6_K,
442 Z_VR7, Z_VR7_H, Z_VR7_J, Z_VR7_K,
443 Z_VR8, Z_VR8_H, Z_VR8_J, Z_VR8_K,
444 Z_VR9, Z_VR9_H, Z_VR9_J, Z_VR9_K,
445 Z_VR10, Z_VR10_H, Z_VR10_J, Z_VR10_K,
446 Z_VR11, Z_VR11_H, Z_VR11_J, Z_VR11_K,
447 Z_VR12, Z_VR12_H, Z_VR12_J, Z_VR12_K,
448 Z_VR13, Z_VR13_H, Z_VR13_J, Z_VR13_K,
449 Z_VR14, Z_VR14_H, Z_VR14_J, Z_VR14_K,
450 Z_VR15, Z_VR15_H, Z_VR15_J, Z_VR15_K,
451 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
452 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
453 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
454 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
455 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
456 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
457 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
458 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
459 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
460 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
461 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
462 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
463 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
464 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
465 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
466 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
467 );
468
469 alloc_class chunk3(
470 Z_CR
471 );
472
473
474 //-------Architecture Description Register Classes-----------------------
475
476 // Several register classes are automatically defined based upon
477 // information in this architecture description.
478
479 // 1) reg_class inline_cache_reg (as defined in frame section)
480 // 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
481
482 // Integer Register Classes
483 reg_class z_int_reg(
484 /*Z_R0*/ // R0
485 /*Z_R1*/
486 Z_R2,
487 Z_R3,
488 Z_R4,
489 Z_R5,
490 Z_R6,
491 Z_R7,
492 /*Z_R8,*/ // Z_thread
493 Z_R9,
494 Z_R10,
495 Z_R11,
496 Z_R12,
497 Z_R13
498 /*Z_R14*/ // return_pc
499 /*Z_R15*/ // SP
500 );
501
502 reg_class z_no_odd_int_reg(
503 /*Z_R0*/ // R0
504 /*Z_R1*/
505 Z_R2,
506 Z_R3,
507 Z_R4,
508 /*Z_R5,*/ // odd part of fix register pair
509 Z_R6,
510 Z_R7,
511 /*Z_R8,*/ // Z_thread
512 Z_R9,
513 Z_R10,
514 Z_R11,
515 Z_R12,
516 Z_R13
517 /*Z_R14*/ // return_pc
518 /*Z_R15*/ // SP
519 );
520
521 reg_class z_no_arg_int_reg(
522 /*Z_R0*/ // R0
523 /*Z_R1*/ // scratch
524 /*Z_R2*/
525 /*Z_R3*/
526 /*Z_R4*/
527 /*Z_R5*/
528 /*Z_R6*/
529 Z_R7,
530 /*Z_R8*/ // Z_thread
531 Z_R9,
532 Z_R10,
533 Z_R11,
534 Z_R12,
535 Z_R13
536 /*Z_R14*/ // return_pc
537 /*Z_R15*/ // SP
538 );
539
540 reg_class z_rarg1_int_reg(Z_R2);
541 reg_class z_rarg2_int_reg(Z_R3);
542 reg_class z_rarg3_int_reg(Z_R4);
543 reg_class z_rarg4_int_reg(Z_R5);
544 reg_class z_rarg5_int_reg(Z_R6);
545
546 // Pointer Register Classes
547
548 // 64-bit build means 64-bit pointers means hi/lo pairs.
549
550 reg_class z_rarg5_ptrN_reg(Z_R6);
551
552 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
553 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
554 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
555 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
556 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
557 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
558 reg_class z_r10_ptr_reg(Z_R10_H, Z_R10);
559 reg_class z_r11_ptr_reg(Z_R11_H, Z_R11);
560
561 reg_class z_ptr_reg(
562 /*Z_R0_H,Z_R0*/ // R0
563 /*Z_R1_H,Z_R1*/
564 Z_R2_H,Z_R2,
565 Z_R3_H,Z_R3,
566 Z_R4_H,Z_R4,
567 Z_R5_H,Z_R5,
568 Z_R6_H,Z_R6,
569 Z_R7_H,Z_R7,
570 /*Z_R8_H,Z_R8,*/ // Z_thread
571 Z_R9_H,Z_R9,
572 Z_R10_H,Z_R10,
573 Z_R11_H,Z_R11,
574 Z_R12_H,Z_R12,
575 Z_R13_H,Z_R13
576 /*Z_R14_H,Z_R14*/ // return_pc
577 /*Z_R15_H,Z_R15*/ // SP
578 );
579
580 reg_class z_lock_ptr_reg(
581 /*Z_R0_H,Z_R0*/ // R0
582 /*Z_R1_H,Z_R1*/
583 Z_R2_H,Z_R2,
584 Z_R3_H,Z_R3,
585 Z_R4_H,Z_R4,
586 /*Z_R5_H,Z_R5,*/
587 /*Z_R6_H,Z_R6,*/
588 Z_R7_H,Z_R7,
589 /*Z_R8_H,Z_R8,*/ // Z_thread
590 Z_R9_H,Z_R9,
591 Z_R10_H,Z_R10,
592 Z_R11_H,Z_R11,
593 Z_R12_H,Z_R12,
594 Z_R13_H,Z_R13
595 /*Z_R14_H,Z_R14*/ // return_pc
596 /*Z_R15_H,Z_R15*/ // SP
597 );
598
599 reg_class z_no_arg_ptr_reg(
600 /*Z_R0_H,Z_R0*/ // R0
601 /*Z_R1_H,Z_R1*/ // scratch
602 /*Z_R2_H,Z_R2*/
603 /*Z_R3_H,Z_R3*/
604 /*Z_R4_H,Z_R4*/
605 /*Z_R5_H,Z_R5*/
606 /*Z_R6_H,Z_R6*/
607 Z_R7_H, Z_R7,
608 /*Z_R8_H,Z_R8*/ // Z_thread
609 Z_R9_H,Z_R9,
610 Z_R10_H,Z_R10,
611 Z_R11_H,Z_R11,
612 Z_R12_H,Z_R12,
613 Z_R13_H,Z_R13
614 /*Z_R14_H,Z_R14*/ // return_pc
615 /*Z_R15_H,Z_R15*/ // SP
616 );
617
618 // Special class for storeP instructions, which can store SP or RPC to
619 // TLS. (Note: Do not generalize this to "any_reg". If you add
620 // another register, such as FP, to this mask, the allocator may try
621 // to put a temp in it.)
622 // Register class for memory access base registers,
623 // This class is a superset of z_ptr_reg including Z_thread.
624 reg_class z_memory_ptr_reg(
625 /*Z_R0_H,Z_R0*/ // R0
626 /*Z_R1_H,Z_R1*/
627 Z_R2_H,Z_R2,
628 Z_R3_H,Z_R3,
629 Z_R4_H,Z_R4,
630 Z_R5_H,Z_R5,
631 Z_R6_H,Z_R6,
632 Z_R7_H,Z_R7,
633 Z_R8_H,Z_R8, // Z_thread
634 Z_R9_H,Z_R9,
635 Z_R10_H,Z_R10,
636 Z_R11_H,Z_R11,
637 Z_R12_H,Z_R12,
638 Z_R13_H,Z_R13
639 /*Z_R14_H,Z_R14*/ // return_pc
640 /*Z_R15_H,Z_R15*/ // SP
641 );
642
643 // Other special pointer regs.
644 reg_class z_r1_regP(Z_R1_H,Z_R1);
645 reg_class z_r9_regP(Z_R9_H,Z_R9);
646
647
648 // Long Register Classes
649
650 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
651 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
652 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
653 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
654 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
655
656 // Longs in 1 register. Aligned adjacent hi/lo pairs.
657 reg_class z_long_reg(
658 /*Z_R0_H,Z_R0*/ // R0
659 /*Z_R1_H,Z_R1*/
660 Z_R2_H,Z_R2,
661 Z_R3_H,Z_R3,
662 Z_R4_H,Z_R4,
663 Z_R5_H,Z_R5,
664 Z_R6_H,Z_R6,
665 Z_R7_H,Z_R7,
666 /*Z_R8_H,Z_R8,*/ // Z_thread
667 Z_R9_H,Z_R9,
668 Z_R10_H,Z_R10,
669 Z_R11_H,Z_R11,
670 Z_R12_H,Z_R12,
671 Z_R13_H,Z_R13
672 /*Z_R14_H,Z_R14,*/ // return_pc
673 /*Z_R15_H,Z_R15*/ // SP
674 );
675
676 // z_long_reg without even registers
677 reg_class z_long_odd_reg(
678 /*Z_R0_H,Z_R0*/ // R0
679 /*Z_R1_H,Z_R1*/
680 Z_R3_H,Z_R3,
681 Z_R5_H,Z_R5,
682 Z_R7_H,Z_R7,
683 Z_R9_H,Z_R9,
684 Z_R11_H,Z_R11,
685 Z_R13_H,Z_R13
686 /*Z_R14_H,Z_R14,*/ // return_pc
687 /*Z_R15_H,Z_R15*/ // SP
688 );
689
690 // Special Class for Condition Code Flags Register
691
692 reg_class z_condition_reg(
693 Z_CR
694 );
695
696 // Scratch register for late profiling. Callee saved.
697 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
698
699
700 // Float Register Classes
701
702 reg_class z_flt_reg(
703 Z_F0,
704 /*Z_F1,*/ // scratch
705 Z_F2,
706 Z_F3,
707 Z_F4,
708 Z_F5,
709 Z_F6,
710 Z_F7,
711 Z_F8,
712 Z_F9,
713 Z_F10,
714 Z_F11,
715 Z_F12,
716 Z_F13,
717 Z_F14,
718 Z_F15
719 );
720 reg_class z_rscratch1_flt_reg(Z_F1);
721
722 // Double precision float registers have virtual `high halves' that
723 // are needed by the allocator.
724 reg_class z_dbl_reg(
725 Z_F0,Z_F0_H,
726 /*Z_F1,Z_F1_H,*/ // scratch
727 Z_F2,Z_F2_H,
728 Z_F3,Z_F3_H,
729 Z_F4,Z_F4_H,
730 Z_F5,Z_F5_H,
731 Z_F6,Z_F6_H,
732 Z_F7,Z_F7_H,
733 Z_F8,Z_F8_H,
734 Z_F9,Z_F9_H,
735 Z_F10,Z_F10_H,
736 Z_F11,Z_F11_H,
737 Z_F12,Z_F12_H,
738 Z_F13,Z_F13_H,
739 Z_F14,Z_F14_H,
740 Z_F15,Z_F15_H
741 );
742 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
743
744 reg_class z_v_reg(
745 // Attention: Only these ones are saved & restored at safepoint by RegisterSaver.
746 //1st 16 VRs overlaps with 1st 16 FPRs.
747 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
748 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
749 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
750 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
751 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
752 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
753 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
754 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
755 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
756 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
757 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
758 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
759 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
760 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
761 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
762 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
763 );
764
765 // class for vector register v16
766 reg_class z_vreg_16(
767 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K
768 );
769
770 // class for vector register v17
771 reg_class z_vreg_17(
772 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K
773 );
774
775 // class for vector register v18
776 reg_class z_vreg_18(
777 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K
778 );
779
780 // class for vector register v19
781 reg_class z_vreg_19(
782 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K
783 );
784
785 // class for vector register v20
786 reg_class z_vreg_20(
787 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K
788 );
789
790 // class for vector register v21
791 reg_class z_vreg_21(
792 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K
793 );
794
795 // class for vector register v22
796 reg_class z_vreg_22(
797 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K
798 );
799
800 // class for vector register v23
801 reg_class z_vreg_23(
802 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K
803 );
804
805 // class for vector register v24
806 reg_class z_vreg_24(
807 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K
808 );
809
810 // class for vector register v25
811 reg_class z_vreg_25(
812 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K
813 );
814
815 %}
816
817 //----------DEFINITION BLOCK---------------------------------------------------
818 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
819 // Current support includes integer values in the range [0, 0x7FFFFFFF].
820 // Format:
821 // int_def <name> (<int_value>, <expression>);
822 // Generated Code in ad_<arch>.hpp
823 // #define <name> (<expression>)
824 // // value == <int_value>
825 // Generated code in ad_<arch>.cpp adlc_verification()
826 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
827 //
828 definitions %{
829 // The default cost (of an ALU instruction).
830 int_def DEFAULT_COST ( 100, 100);
831 int_def DEFAULT_COST_LOW ( 80, 80);
832 int_def DEFAULT_COST_HIGH ( 120, 120);
833 int_def HUGE_COST (1000000, 1000000);
834
835 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
836 int_def ALU_REG_COST ( 100, DEFAULT_COST);
837 int_def ALU_MEMORY_COST ( 150, 150);
838
839 // Memory refs are twice as expensive as run-of-the-mill.
840 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
841 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
842 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
843
844 // Branches are even more expensive.
845 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
846 int_def CALL_COST ( 300, DEFAULT_COST * 3);
847 %}
848
849 source %{
850
851 #ifdef PRODUCT
852 #define BLOCK_COMMENT(str)
853 #define BIND(label) __ bind(label)
854 #else
855 #define BLOCK_COMMENT(str) __ block_comment(str)
856 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
857 #endif
858
859 #define __ masm->
860
861 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
862 #define Z_DISP3_SIZE 6
863
864 // Tertiary op of a LoadP or StoreP encoding.
865 #define REGP_OP true
866
867 // Given a register encoding, produce an Integer Register object.
868 static Register reg_to_register_object(int register_encoding);
869
870 // ****************************************************************************
871
872 // REQUIRED FUNCTIONALITY
873
874 // !!!!! Special hack to get all type of calls to specify the byte offset
875 // from the start of the call to the point where the return address
876 // will point.
877
878 void PhaseOutput::pd_perform_mach_node_analysis() {
879 }
880
881 int MachNode::pd_alignment_required() const {
882 return 1;
883 }
884
885 int MachNode::compute_padding(int current_offset) const {
886 return 0;
887 }
888
889 int MachCallStaticJavaNode::ret_addr_offset() const {
890 if (_method) {
891 return MacroAssembler::call_far_pcrelative_size();
892 } else {
893 return MacroAssembler::call_far_patchable_ret_addr_offset();
894 }
895 }
896
897 int MachCallDynamicJavaNode::ret_addr_offset() const {
898 // Consider size of receiver type profiling (C2 tiers).
899
900 int vtable_index = this->_vtable_index;
901 if (vtable_index == -4) {
902 return MacroAssembler::load_const_from_toc_size()
903 + MacroAssembler::call_far_pcrelative_size();
904 } else {
905 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
906 // This should return the size of instructions in vtable dispatch
907 // branch of z_enc_java_dynamic_call
908 int offset = 0;
909
910 // __ load_klass(Z_method, Z_R2);
911 if (UseCompactObjectHeaders) {
912 // load_narrow_klass_compact (z_lg z_srlg)
913 offset += 6 // z_lg
914 + 6; // z_srlg;
915 } else {
916 offset += 6; // z_llgf
917 }
918 offset += MacroAssembler::instr_size_for_decode_klass_not_null();
919
920 // check if displacement is valid, as it will generate different
921 // instructions:
922 int entry_offset = in_bytes(Klass::vtable_start_offset()) +
923 vtable_index * vtableEntry::size_in_bytes();
924 int v_off = entry_offset + in_bytes(vtableEntry::method_offset());
925 if (!Displacement::is_validDisp(v_off)) {
926 offset += MacroAssembler::load_const_size(); // emits iihf + iilf
927 }
928 // both generate z_lg
929 offset += 6; // z_lg (z_method, v_off | Address(Z_method, Z_R1_scratch))
930 // common footer
931 offset += 6; // z_lg(Z_R1_scratch, Method::from_compiled_offset())
932 offset += 2; // z_basr
933
934 return offset;
935 }
936 }
937
938 int MachCallRuntimeNode::ret_addr_offset() const {
939 return 6 // get_PC() (LARL)
940 + 6 // save_return_pc() (STG)
941 + MacroAssembler::call_far_patchable_ret_addr_offset();
942 }
943
944 // Compute padding required for nodes which need alignment
945 //
946 // The addresses of the call instructions needs to be 4-byte aligned to
947 // ensure that they don't span a cache line so that they are atomically patchable.
948 // The actual calls get emitted at different offsets within the node emitters.
949 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
950
951 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
952 return (0 - current_offset) & 2;
953 }
954
955 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
956 return (6 - current_offset) & 2;
957 }
958
959 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
960 return (12 - current_offset) & 2;
961 }
962
963 int CallLeafDirectNode::compute_padding(int current_offset) const {
964 return (12 - current_offset) & 2;
965 }
966
967 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
968 return (12 - current_offset) & 2;
969 }
970
971 void emit_nop(C2_MacroAssembler *masm) {
972 __ z_nop();
973 }
974
975 // Emit an interrupt that is caught by the debugger (for debugging compiler).
976 void emit_break(C2_MacroAssembler *masm) {
977 __ z_illtrap();
978 }
979
980 #if !defined(PRODUCT)
981 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
982 os->print("TA");
983 }
984 #endif
985
986 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
987 emit_break(masm);
988 }
989
990 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
991 return MachNode::size(ra_);
992 }
993
994 static inline void z_emit16(C2_MacroAssembler *masm, long value) {
995 __ emit_instruction((unsigned long)value, 2);
996 }
997
998 static inline void z_emit32(C2_MacroAssembler *masm, long value) {
999 __ emit_instruction((unsigned long)value, 4);
1000 }
1001
1002 static inline void z_emit48(C2_MacroAssembler *masm, long value) {
1003 __ emit_instruction((unsigned long)value, 6);
1004 }
1005
1006 static inline unsigned int z_emit_inst(C2_MacroAssembler *masm, long value) {
1007 if (value < 0) {
1008 // There obviously has been an unintended sign extension (int->long). Revert it.
1009 value = (long)((unsigned long)((unsigned int)value));
1010 }
1011
1012 int len = __ emit_instruction((unsigned long)value, 0);
1013 return len;
1014 }
1015
1016 // Check effective address (at runtime) for required alignment.
1017 static inline void z_assert_aligned(C2_MacroAssembler *masm, int disp, Register index, Register base, int alignment) {
1018 __ z_lay(Z_R0, disp, index, base);
1019 __ z_nill(Z_R0, alignment-1);
1020 __ z_brc(Assembler::bcondEqual, +3);
1021 __ z_illtrap();
1022 }
1023
1024 int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, relocInfo::relocType rtype,
1025 PhaseRegAlloc* ra_, bool is_native_call = false) {
1026 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
1027 unsigned int start_off = __ offset();
1028
1029 if (is_native_call) {
1030 ShouldNotReachHere();
1031 }
1032
1033 if (rtype == relocInfo::runtime_call_w_cp_type) {
1034 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
1035 address call_addr = __ call_c_opt((address)entry_point);
1036 if (call_addr == nullptr) {
1037 Compile::current()->env()->record_out_of_memory_failure();
1038 return -1;
1039 }
1040 } else {
1041 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
1042 rtype == relocInfo::static_call_type, "unexpected rtype");
1043 __ relocate(rtype);
1044 // BRASL must be prepended with a nop to identify it in the instruction stream.
1045 __ z_nop();
1046 __ z_brasl(Z_R14, (address)entry_point);
1047 }
1048
1049 unsigned int ret_off = __ offset();
1050
1051 return (ret_off - start_off);
1052 }
1053
1054 static int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, RelocationHolder const& rspec) {
1055 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
1056 unsigned int start_off = __ offset();
1057
1058 relocInfo::relocType rtype = rspec.type();
1059 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
1060 "unexpected rtype");
1061
1062 __ relocate(rspec);
1063 __ z_nop();
1064 __ z_brasl(Z_R14, (address)entry_point);
1065
1066 unsigned int ret_off = __ offset();
1067
1068 return (ret_off - start_off);
1069 }
1070
1071 //=============================================================================
1072
1073 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
1074 int ConstantTable::calculate_table_base_offset() const {
1075 return 0; // absolute addressing, no offset
1076 }
1077
1078 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1079 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1080 ShouldNotReachHere();
1081 }
1082
1083 // Even with PC-relative TOC addressing, we still need this node.
1084 // Float loads/stores do not support PC-relative addresses.
1085 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1086 Register Rtoc = as_Register(ra_->get_encode(this));
1087 __ load_toc(Rtoc);
1088 }
1089
1090 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1091 // PCrelative TOC access.
1092 return 6; // sizeof(LARL)
1093 }
1094
1095 #if !defined(PRODUCT)
1096 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1097 Register r = as_Register(ra_->get_encode(this));
1098 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
1099 }
1100 #endif
1101
1102 //=============================================================================
1103
1104 #include "gc/shared/barrierSetAssembler.hpp"
1105
1106 #if !defined(PRODUCT)
1107 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1108 Compile* C = ra_->C;
1109 st->print_cr("--- MachPrologNode ---");
1110 st->print("\t");
1111 for (int i = 0; i < OptoPrologueNops; i++) {
1112 st->print_cr("NOP"); st->print("\t");
1113 }
1114
1115 long framesize = C->output()->frame_size_in_bytes();
1116 int bangsize = C->output()->bang_size_in_bytes();
1117
1118 // Calls to C2R adapters often do not accept exceptional returns.
1119 // We require that their callers must bang for them. But be
1120 // careful, because some VM calls (such as call site linkage) can
1121 // use several kilobytes of stack. But the stack safety zone should
1122 // account for that. See bugs 4446381, 4468289, 4497237.
1123 if (C->output()->need_stack_bang(bangsize)) {
1124 st->print_cr("# stack bang"); st->print("\t");
1125 }
1126 st->print_cr("push_frame %d", (int)-framesize);
1127 st->print("\t");
1128
1129 if (C->stub_function() == nullptr) {
1130 st->print("nmethod entry barrier\n\t");
1131 }
1132 }
1133 #endif
1134
1135 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1136 Compile* C = ra_->C;
1137
1138 size_t framesize = C->output()->frame_size_in_bytes();
1139 size_t bangsize = C->output()->bang_size_in_bytes();
1140
1141 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
1142
1143 if (C->clinit_barrier_on_entry()) {
1144 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1145
1146 Label L_skip_barrier;
1147 Register klass = Z_R1_scratch;
1148
1149 // Notify OOP recorder (don't need the relocation)
1150 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
1151 __ load_const_optimized(klass, md.value());
1152 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
1153
1154 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
1155 __ z_br(klass);
1156
1157 __ bind(L_skip_barrier);
1158 }
1159
1160 // Calls to C2R adapters often do not accept exceptional returns.
1161 // We require that their callers must bang for them. But be
1162 // careful, because some VM calls (such as call site linkage) can
1163 // use several kilobytes of stack. But the stack safety zone should
1164 // account for that. See bugs 4446381, 4468289, 4497237.
1165 if (C->output()->need_stack_bang(bangsize)) {
1166 __ generate_stack_overflow_check(bangsize);
1167 }
1168
1169 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
1170 __ save_return_pc();
1171
1172 // The z/Architecture abi is already accounted for in `framesize' via the
1173 // 'out_preserve_stack_slots' declaration.
1174 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
1175
1176 if (C->has_mach_constant_base_node()) {
1177 // NOTE: We set the table base offset here because users might be
1178 // emitted before MachConstantBaseNode.
1179 ConstantTable& constant_table = C->output()->constant_table();
1180 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1181 }
1182
1183 if (C->stub_function() == nullptr) {
1184 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1185 bs->nmethod_entry_barrier(masm);
1186 }
1187
1188 C->output()->set_frame_complete(__ offset());
1189 }
1190
1191 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1192 // Variable size. Determine dynamically.
1193 return MachNode::size(ra_);
1194 }
1195
1196 int MachPrologNode::reloc() const {
1197 // Return number of relocatable values contained in this instruction.
1198 return 1; // One reloc entry for load_const(toc).
1199 }
1200
1201 //=============================================================================
1202
1203 #if !defined(PRODUCT)
1204 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1205 os->print_cr("epilog");
1206 os->print("\t");
1207 if (do_polling() && ra_->C->is_method_compilation()) {
1208 os->print_cr("load_from_polling_page Z_R1_scratch");
1209 os->print("\t");
1210 }
1211 }
1212 #endif
1213
1214 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1215 Compile* C = ra_->C;
1216
1217 // If this does safepoint polling, then do it here.
1218 bool need_polling = do_polling() && C->is_method_compilation();
1219
1220 // Pop frame, restore return_pc, and all stuff needed by interpreter.
1221 int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
1222 __ pop_frame_restore_retPC(frame_size_in_bytes);
1223
1224 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1225 __ reserved_stack_check(Z_R14);
1226 }
1227
1228 // Touch the polling page.
1229 if (need_polling) {
1230 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1231 // We need to mark the code position where the load from the safepoint
1232 // polling page was emitted as relocInfo::poll_return_type here.
1233 __ relocate(relocInfo::poll_return_type);
1234 __ load_from_polling_page(Z_R1_scratch);
1235 }
1236 }
1237
1238 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1239 // Variable size. determine dynamically.
1240 return MachNode::size(ra_);
1241 }
1242
1243 int MachEpilogNode::reloc() const {
1244 // Return number of relocatable values contained in this instruction.
1245 return 1; // One for load_from_polling_page.
1246 }
1247
1248 const Pipeline * MachEpilogNode::pipeline() const {
1249 return MachNode::pipeline_class();
1250 }
1251
1252 //=============================================================================
1253
1254 // Figure out which register class each belongs in: rc_int, rc_float, rc_vector, rc_stack.
1255 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1256
1257 static enum RC rc_class(OptoReg::Name reg) {
1258 // Return the register class for the given register. The given register
1259 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1260 // enumeration in adGlobals_s390.hpp.
1261
1262 if (reg == OptoReg::Bad) {
1263 return rc_bad;
1264 }
1265
1266 // We have 32 integer register halves, starting at index 0.
1267 if (reg < 32) {
1268 return rc_int;
1269 }
1270
1271 // We have 32 floating-point register halves, starting at index 32.
1272 if (reg < 32+32) {
1273 return rc_float;
1274 }
1275
1276 // we have 128 vector register halves at index 64
1277 if (reg < 32+32+128) {
1278 return rc_vector;
1279 }
1280
1281 // Between float regs & stack are the flags regs.
1282 assert(OptoReg::is_stack(reg) || reg < 32+32+128, "blow up if spilling flags");
1283 return rc_stack;
1284 }
1285
1286 // Returns size as obtained from z_emit_instr.
1287 static unsigned int z_ld_st_helper(C2_MacroAssembler *masm, const char *op_str, unsigned long opcode,
1288 int reg, int offset, bool do_print, outputStream *os) {
1289
1290 if (masm) {
1291 if (opcode > (1L<<32)) {
1292 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1293 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1294 } else {
1295 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1296 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1297 }
1298 }
1299
1300 #if !defined(PRODUCT)
1301 if (do_print) {
1302 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1303 }
1304 #endif
1305 return (opcode > (1L << 32)) ? 6 : 4;
1306 }
1307
1308 static unsigned int z_mvc_helper(C2_MacroAssembler *masm, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1309 if (masm) {
1310 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1311 }
1312
1313 #if !defined(PRODUCT)
1314 else if (do_print) {
1315 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1316 }
1317 #endif
1318
1319 return 6;
1320 }
1321
1322 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1323 // Get registers to move.
1324 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1325 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1326 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1327 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1328
1329 enum RC src_hi_rc = rc_class(src_hi);
1330 enum RC src_lo_rc = rc_class(src_lo);
1331 enum RC dst_hi_rc = rc_class(dst_hi);
1332 enum RC dst_lo_rc = rc_class(dst_lo);
1333
1334 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1335 bool is64 = (src_hi_rc != rc_bad);
1336 assert(!is64 ||
1337 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1338 "expected aligned-adjacent pairs");
1339
1340 // Generate spill code!
1341 int size = 0;
1342 if (src_lo == dst_lo && src_hi == dst_hi) {
1343 return 0; // Self copy, no move.
1344 }
1345
1346 int src_offset = ra_->reg2offset(src_lo);
1347 int dst_offset = ra_->reg2offset(dst_lo);
1348 bool print = !do_size;
1349 bool src12 = Immediate::is_uimm12(src_offset);
1350 bool dst12 = Immediate::is_uimm12(dst_offset);
1351
1352 const char *mnemo = nullptr;
1353 unsigned long opc = 0;
1354
1355 if (bottom_type()->isa_vect() != nullptr && ideal_reg() == Op_VecX) {
1356 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1357 if (masm != nullptr) {
1358 __ z_mvc(Address(Z_SP, 0, dst_offset), Address(Z_SP, 0, src_offset), 16);
1359 }
1360 size += 6;
1361 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1362 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1363 if (masm != nullptr) {
1364 __ z_vst(Rsrc, Address(Z_SP, 0, dst_offset));
1365 }
1366 size += 6;
1367 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1368 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1369 if (masm != nullptr) {
1370 __ z_vl(Rdst, Address(Z_SP, 0, src_offset));
1371 }
1372 size += 6;
1373 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1374 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1375 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1376 if (masm != nullptr) {
1377 __ z_vlr(Rdst, Rsrc);
1378 }
1379 size += 6;
1380 } else {
1381 ShouldNotReachHere();
1382 }
1383 return size;
1384 }
1385
1386 // Memory->Memory Spill. Use Z_R0 to hold the value.
1387 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1388
1389 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1390 "expected same type of move for high parts");
1391
1392 if (src12 && dst12) {
1393 return z_mvc_helper(masm, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1394 }
1395
1396 int r0 = Z_R0_num;
1397 if (is64) {
1398 return z_ld_st_helper(masm, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1399 z_ld_st_helper(masm, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1400 }
1401
1402 return z_ld_st_helper(masm, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1403 z_ld_st_helper(masm, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1404 }
1405
1406 // Check for float->int copy. Requires a trip through memory.
1407 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1408 Unimplemented(); // Unsafe, do not remove!
1409 }
1410
1411 // Check for integer reg-reg copy.
1412 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1413 if (masm) {
1414 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1415 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1416 __ z_lgr(Rdst, Rsrc);
1417 return 4;
1418 }
1419 #if !defined(PRODUCT)
1420 // else
1421 if (print) {
1422 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1423 }
1424 #endif
1425 return 4;
1426 }
1427
1428 // Check for integer store.
1429 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1430 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1431 "expected same type of move for high parts");
1432
1433 if (is64) {
1434 return z_ld_st_helper(masm, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1435 }
1436
1437 // else
1438 mnemo = dst12 ? "ST " : "STY ";
1439 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1440
1441 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1442 }
1443
1444 // Check for integer load
1445 // Always load cOops zero-extended. That doesn't hurt int loads.
1446 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1447
1448 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1449 "expected same type of move for high parts");
1450
1451 mnemo = is64 ? "LG " : "LLGF";
1452 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1453
1454 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1455 }
1456
1457 // Check for float reg-reg copy.
1458 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1459 if (masm) {
1460 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1461 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1462 __ z_ldr(Rdst, Rsrc);
1463 return 2;
1464 }
1465 #if !defined(PRODUCT)
1466 // else
1467 if (print) {
1468 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1469 }
1470 #endif
1471 return 2;
1472 }
1473
1474 // Check for float store.
1475 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1476 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1477 "expected same type of move for high parts");
1478
1479 if (is64) {
1480 mnemo = dst12 ? "STD " : "STDY ";
1481 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1482 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1483 }
1484 // else
1485
1486 mnemo = dst12 ? "STE " : "STEY ";
1487 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1488 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1489 }
1490
1491 // Check for float load.
1492 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1493 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1494 "expected same type of move for high parts");
1495
1496 if (is64) {
1497 mnemo = src12 ? "LD " : "LDY ";
1498 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1499 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1500 }
1501 // else
1502
1503 mnemo = src12 ? "LE " : "LEY ";
1504 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1505 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1506 }
1507
1508 // --------------------------------------------------------------------
1509 // Check for hi bits still needing moving. Only happens for misaligned
1510 // arguments to native calls.
1511 if (src_hi == dst_hi) {
1512 return 0; // Self copy, no move.
1513 }
1514
1515 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1516 Unimplemented(); // Unsafe, do not remove!
1517
1518 return 0; // never reached, but make the compiler shut up!
1519 }
1520
1521 #if !defined(PRODUCT)
1522 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1523 if (ra_ && ra_->node_regs_max_index() > 0) {
1524 implementation(nullptr, ra_, false, os);
1525 } else {
1526 if (req() == 2 && in(1)) {
1527 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1528 } else {
1529 const char *c = "(";
1530 os->print("N%d = ", _idx);
1531 for (uint i = 1; i < req(); ++i) {
1532 os->print("%sN%d", c, in(i)->_idx);
1533 c = ", ";
1534 }
1535 os->print(")");
1536 }
1537 }
1538 }
1539 #endif
1540
1541 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1542 implementation(masm, ra_, false, nullptr);
1543 }
1544
1545 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1546 return implementation(nullptr, ra_, true, nullptr);
1547 }
1548
1549 //=============================================================================
1550
1551 #if !defined(PRODUCT)
1552 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1553 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1554 }
1555 #endif
1556
1557 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc * ra_) const {
1558 int rem_space = 0;
1559 if (!(ra_->C->output()->in_scratch_emit_size())) {
1560 rem_space = __ code()->insts()->remaining();
1561 if (rem_space <= _count*2 + 8) {
1562 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1563 }
1564 }
1565
1566 for (int i = 0; i < _count; i++) {
1567 __ z_nop();
1568 }
1569
1570 if (!(ra_->C->output()->in_scratch_emit_size())) {
1571 if (rem_space <= _count*2 + 8) {
1572 int rem_space2 = __ code()->insts()->remaining();
1573 tty->print_cr(", after = %d", rem_space2);
1574 }
1575 }
1576 }
1577
1578 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1579 return 2 * _count;
1580 }
1581
1582 #if !defined(PRODUCT)
1583 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1584 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1585 if (ra_ && ra_->node_regs_max_index() > 0) {
1586 int reg = ra_->get_reg_first(this);
1587 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1588 } else {
1589 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1590 }
1591 }
1592 #endif
1593
1594 // Take care of the size function, if you make changes here!
1595 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1596 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1597 int reg = ra_->get_encode(this);
1598 __ z_lay(as_Register(reg), offset, Z_SP);
1599 }
1600
1601 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1602 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1603 return 6;
1604 }
1605
1606 %} // end source section
1607
1608 //----------SOURCE BLOCK-------------------------------------------------------
1609 // This is a block of C++ code which provides values, functions, and
1610 // definitions necessary in the rest of the architecture description
1611
1612 source_hpp %{
1613
1614 // Header information of the source block.
1615 // Method declarations/definitions which are used outside
1616 // the ad-scope can conveniently be defined here.
1617 //
1618 // To keep related declarations/definitions/uses close together,
1619 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1620 #include "opto/convertnode.hpp"
1621 #include "oops/klass.inline.hpp"
1622
1623 //--------------------------------------------------------------
1624 // Used for optimization in Compile::Shorten_branches
1625 //--------------------------------------------------------------
1626
1627 class CallStubImpl {
1628 public:
1629
1630 // call trampolines
1631 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1632 static uint size_call_trampoline() {
1633 return 0; // no call trampolines on this platform
1634 }
1635
1636 // call trampolines
1637 // Number of relocations needed by a call trampoline stub.
1638 static uint reloc_call_trampoline() {
1639 return 0; // No call trampolines on this platform.
1640 }
1641 };
1642
1643 %} // end source_hpp section
1644
1645 source %{
1646
1647 #if !defined(PRODUCT)
1648 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1649 os->print_cr("---- MachUEPNode ----");
1650 os->print_cr("\tTA");
1651 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1652 os->print_cr("\tBR(Z_R1)");
1653 os->print_cr("\tTA # pad with illtraps");
1654 os->print_cr("\t...");
1655 os->print_cr("\tTA");
1656 os->print_cr("\tLTGR Z_R2, Z_R2");
1657 os->print_cr("\tBRU ic_miss");
1658 }
1659 #endif
1660
1661 void MachUEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1662 // This is Unverified Entry Point
1663 __ ic_check(CodeEntryAlignment);
1664 }
1665
1666 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1667 // Determine size dynamically.
1668 return MachNode::size(ra_);
1669 }
1670
1671 //=============================================================================
1672
1673 %} // interrupt source section
1674
1675 source_hpp %{ // Header information of the source block.
1676
1677 class HandlerImpl {
1678 public:
1679
1680 static int emit_deopt_handler(C2_MacroAssembler* masm);
1681
1682 static uint size_deopt_handler() {
1683 return NativeCall::max_instruction_size() + MacroAssembler::jump_pcrelative_size();
1684 }
1685 };
1686
1687 class Node::PD {
1688 public:
1689 enum NodeFlags {
1690 _last_flag = Node::_last_flag
1691 };
1692 };
1693
1694 %} // end source_hpp section
1695
1696 source %{
1697
1698 // Emit deopt handler code.
1699 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm) {
1700 address base = __ start_a_stub(size_deopt_handler());
1701
1702 if (base == nullptr) {
1703 ciEnv::current()->record_failure("CodeCache is full");
1704 return 0; // CodeBuffer::expand failed
1705 }
1706
1707 int offset = __ offset();
1708
1709 Label start;
1710 __ bind(start);
1711
1712 // Size_deopt_handler() must be exact on zarch, so for simplicity
1713 // we do not use load_const_opt here.
1714 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1715 __ call(Z_R1);
1716
1717 int entry_offset = __ offset();
1718
1719 __ z_bru(start);
1720
1721 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1722 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1723 "out of bounds read in post-call NOP check");
1724
1725 __ end_a_stub();
1726 return entry_offset;
1727 }
1728
1729 //=============================================================================
1730
1731
1732 // Given a register encoding, produce an Integer Register object.
1733 static Register reg_to_register_object(int register_encoding) {
1734 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1735 return as_Register(register_encoding);
1736 }
1737
1738 bool Matcher::match_rule_supported(int opcode) {
1739 if (!has_match_rule(opcode)) {
1740 return false; // no match rule present
1741 }
1742
1743 switch (opcode) {
1744 case Op_ReverseBytesI:
1745 case Op_ReverseBytesL:
1746 case Op_ReverseBytesS:
1747 case Op_ReverseBytesUS:
1748 return UseByteReverseInstruction;
1749 case Op_PopCountI:
1750 case Op_PopCountL:
1751 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1752 return (UsePopCountInstruction && VM_Version::has_PopCount());
1753 case Op_AddVB:
1754 case Op_AddVS:
1755 case Op_AddVI:
1756 case Op_AddVL:
1757 case Op_AddVD:
1758 case Op_SubVB:
1759 case Op_SubVS:
1760 case Op_SubVI:
1761 case Op_SubVL:
1762 case Op_SubVD:
1763 case Op_MulVB:
1764 case Op_MulVS:
1765 case Op_MulVI:
1766 case Op_MulVD:
1767 case Op_DivVD:
1768 case Op_SqrtVD:
1769 case Op_RoundDoubleModeV:
1770 return SuperwordUseVX;
1771 case Op_AddVF:
1772 case Op_SubVF:
1773 case Op_MulVF:
1774 case Op_DivVF:
1775 case Op_SqrtVF:
1776 //PopCountVI supported by z14 onwards.
1777 case Op_PopCountVI:
1778 return (SuperwordUseVX && UseSFPV);
1779 case Op_FmaF:
1780 case Op_FmaD:
1781 return UseFMA;
1782 }
1783
1784 return true; // Per default match rules are supported.
1785 }
1786
1787 bool Matcher::match_rule_supported_auto_vectorization(int opcode, int vlen, BasicType bt) {
1788 return match_rule_supported_vector(opcode, vlen, bt);
1789 }
1790
1791 bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1792 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1793 return false;
1794 }
1795 return true; // Per default match rules are supported.
1796 }
1797
1798 bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
1799 return false;
1800 }
1801
1802 bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
1803 return false;
1804 }
1805
1806 bool Matcher::vector_rearrange_requires_load_shuffle(BasicType elem_bt, int vlen) {
1807 return false;
1808 }
1809
1810 bool Matcher::mask_op_prefers_predicate(int opcode, const TypeVect* vt) {
1811 return false;
1812 }
1813
1814 const RegMask* Matcher::predicate_reg_mask(void) {
1815 return nullptr;
1816 }
1817
1818 // Vector calling convention not yet implemented.
1819 bool Matcher::supports_vector_calling_convention(void) {
1820 return false;
1821 }
1822
1823 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1824 Unimplemented();
1825 return OptoRegPair(0, 0);
1826 }
1827
1828 //----------SUPERWORD HELPERS----------------------------------------
1829
1830 // Vector width in bytes.
1831 int Matcher::vector_width_in_bytes(BasicType bt) {
1832 if (SuperwordUseVX) {
1833 assert(MaxVectorSize == 16, "");
1834 return 16;
1835 } else {
1836 assert(MaxVectorSize == 8, "");
1837 return 8;
1838 }
1839 }
1840
1841 // Vector ideal reg.
1842 uint Matcher::vector_ideal_reg(int size) {
1843 if (SuperwordUseVX) {
1844 assert(MaxVectorSize == 16 && size == 16, "");
1845 return Op_VecX;
1846 } else {
1847 assert(MaxVectorSize == 8 && size == 8, "");
1848 return Op_RegL;
1849 }
1850 }
1851
1852 // Limits on vector size (number of elements) loaded into vector.
1853 int Matcher::max_vector_size(const BasicType bt) {
1854 assert(is_java_primitive(bt), "only primitive type vectors");
1855 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1856 }
1857
1858 int Matcher::min_vector_size(const BasicType bt) {
1859 return max_vector_size(bt); // Same as max.
1860 }
1861
1862 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
1863 return Matcher::max_vector_size(bt);
1864 }
1865
1866 int Matcher::scalable_vector_reg_size(const BasicType bt) {
1867 return -1;
1868 }
1869
1870 // RETURNS: whether this branch offset is short enough that a short
1871 // branch can be used.
1872 //
1873 // If the platform does not provide any short branch variants, then
1874 // this method should return `false' for offset 0.
1875 //
1876 // `Compile::Fill_buffer' will decide on basis of this information
1877 // whether to do the pass `Compile::Shorten_branches' at all.
1878 //
1879 // And `Compile::Shorten_branches' will decide on basis of this
1880 // information whether to replace particular branch sites by short
1881 // ones.
1882 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1883 // On zarch short branches use a 16 bit signed immediate that
1884 // is the pc-relative offset in halfword (= 2 bytes) units.
1885 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1886 }
1887
1888 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1889 ShouldNotReachHere(); // generic vector operands not supported
1890 return nullptr;
1891 }
1892
1893 bool Matcher::is_reg2reg_move(MachNode* m) {
1894 ShouldNotReachHere(); // generic vector operands not supported
1895 return false;
1896 }
1897
1898 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
1899 return false;
1900 }
1901
1902 bool Matcher::is_generic_vector(MachOper* opnd) {
1903 ShouldNotReachHere(); // generic vector operands not supported
1904 return false;
1905 }
1906
1907 // Constants for c2c and c calling conventions.
1908
1909 const MachRegisterNumbers z_iarg_reg[5] = {
1910 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1911 };
1912
1913 const MachRegisterNumbers z_farg_reg[4] = {
1914 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1915 };
1916
1917 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1918
1919 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1920
1921 #ifdef ASSERT
1922 // Return whether or not this register is ever used as an argument.
1923 bool Matcher::can_be_java_arg(int reg) {
1924 // We return true for all registers contained in z_iarg_reg[] and
1925 // z_farg_reg[] and their virtual halves.
1926 // We must include the virtual halves in order to get STDs and LDs
1927 // instead of STWs and LWs in the trampoline stubs.
1928
1929 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1930 reg == Z_R3_num || reg == Z_R3_H_num ||
1931 reg == Z_R4_num || reg == Z_R4_H_num ||
1932 reg == Z_R5_num || reg == Z_R5_H_num ||
1933 reg == Z_R6_num || reg == Z_R6_H_num) {
1934 return true;
1935 }
1936
1937 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1938 reg == Z_F2_num || reg == Z_F2_H_num ||
1939 reg == Z_F4_num || reg == Z_F4_H_num ||
1940 reg == Z_F6_num || reg == Z_F6_H_num) {
1941 return true;
1942 }
1943
1944 return false;
1945 }
1946 #endif
1947
1948 uint Matcher::int_pressure_limit()
1949 {
1950 // Medium size register set, 6 special purpose regs, 3 SOE regs.
1951 // 10 prevents spill-split-recycle sanity check in JVM2008.xml.transform.
1952 return (INTPRESSURE == -1) ? 10 : INTPRESSURE;
1953 }
1954
1955 uint Matcher::float_pressure_limit()
1956 {
1957 return (FLOATPRESSURE == -1) ? 15 : FLOATPRESSURE;
1958 }
1959
1960 // Register for the first projection of an int pair
1961 const RegMask& Matcher::firstI_proj_mask() {
1962 return _Z_RARG4_INT_REG_mask;
1963 }
1964
1965 // Register for the second projection of an int pair
1966 const RegMask& Matcher::secondI_proj_mask() {
1967 return _Z_RARG3_INT_REG_mask;
1968 }
1969
1970 // Register for the first projection of a long pair
1971 const RegMask& Matcher::firstL_proj_mask() {
1972 return _Z_RARG4_LONG_REG_mask;
1973 }
1974
1975 // Register for the second projection of a long pair
1976 const RegMask& Matcher::secondL_proj_mask() {
1977 return _Z_RARG3_LONG_REG_mask;
1978 }
1979
1980 // Should the matcher clone input 'm' of node 'n'?
1981 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
1982 if (is_encode_and_store_pattern(n, m)) {
1983 mstack.push(m, Visit);
1984 return true;
1985 }
1986 return false;
1987 }
1988
1989 // Should the Matcher clone shifts on addressing modes, expecting them
1990 // to be subsumed into complex addressing expressions or compute them
1991 // into registers?
1992 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1993 return clone_base_plus_offset_address(m, mstack, address_visited);
1994 }
1995
1996 %} // source
1997
1998 //----------ENCODING BLOCK-----------------------------------------------------
1999 // This block specifies the encoding classes used by the compiler to output
2000 // byte streams. Encoding classes are parameterized macros used by
2001 // Machine Instruction Nodes in order to generate the bit encoding of the
2002 // instruction. Operands specify their base encoding interface with the
2003 // interface keyword. There are currently supported four interfaces,
2004 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2005 // operand to generate a function which returns its register number when
2006 // queried. CONST_INTER causes an operand to generate a function which
2007 // returns the value of the constant when queried. MEMORY_INTER causes an
2008 // operand to generate four functions which return the Base Register, the
2009 // Index Register, the Scale Value, and the Offset Value of the operand when
2010 // queried. COND_INTER causes an operand to generate six functions which
2011 // return the encoding code (ie - encoding bits for the instruction)
2012 // associated with each basic boolean condition for a conditional instruction.
2013 //
2014 // Instructions specify two basic values for encoding. Again, a function
2015 // is available to check if the constant displacement is an oop. They use the
2016 // ins_encode keyword to specify their encoding classes (which must be
2017 // a sequence of enc_class names, and their parameters, specified in
2018 // the encoding block), and they use the
2019 // opcode keyword to specify, in order, their primary, secondary, and
2020 // tertiary opcode. Only the opcode sections which a particular instruction
2021 // needs for encoding need to be specified.
2022 encode %{
2023 enc_class enc_unimplemented %{
2024 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2025 %}
2026
2027 enc_class enc_untested %{
2028 #ifdef ASSERT
2029 __ untested("Untested mach node encoding in AD file.");
2030 #endif
2031 %}
2032
2033 enc_class z_rrform(iRegI dst, iRegI src) %{
2034 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
2035 assert( ($primary >> 16) == 0, "Instruction format error");
2036 z_emit16(masm, $primary |
2037 Assembler::reg($dst$$reg,8,16) |
2038 Assembler::reg($src$$reg,12,16));
2039 %}
2040
2041 enc_class z_rreform(iRegI dst1, iRegI src2) %{
2042 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2043 z_emit32(masm, $primary |
2044 Assembler::reg($dst1$$reg,24,32) |
2045 Assembler::reg($src2$$reg,28,32));
2046 %}
2047
2048 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
2049 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2050 z_emit32(masm, $primary |
2051 Assembler::reg($dst1$$reg,24,32) |
2052 Assembler::reg($src2$$reg,28,32) |
2053 Assembler::reg($src3$$reg,16,32));
2054 %}
2055
2056 enc_class z_riform_signed(iRegI dst, immI16 src) %{
2057 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2058 z_emit32(masm, $primary |
2059 Assembler::reg($dst$$reg,8,32) |
2060 Assembler::simm16($src$$constant,16,32));
2061 %}
2062
2063 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
2064 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2065 z_emit32(masm, $primary |
2066 Assembler::reg($dst$$reg,8,32) |
2067 Assembler::uimm16($src$$constant,16,32));
2068 %}
2069
2070 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
2071 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2072 z_emit48(masm, $primary |
2073 Assembler::reg($dst1$$reg,8,48) |
2074 Assembler::reg($src3$$reg,12,48) |
2075 Assembler::simm16($src2$$constant,16,48));
2076 %}
2077
2078 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
2079 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2080 z_emit48(masm, $primary |
2081 Assembler::reg($dst$$reg,8,48) |
2082 Assembler::simm32($src$$constant,16,48));
2083 %}
2084
2085 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
2086 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2087 z_emit48(masm, $primary |
2088 Assembler::reg($dst$$reg,8,48) |
2089 Assembler::uimm32($src$$constant,16,48));
2090 %}
2091
2092 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
2093 z_emit48(masm, $primary |
2094 Assembler::reg($dst$$reg,8,48) |
2095 Assembler::reg($src1$$reg,12,48) |
2096 Assembler::simm20($src2$$constant));
2097 %}
2098
2099 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
2100 z_emit48(masm, $primary |
2101 Assembler::reg($dst$$reg,8,48) |
2102 Assembler::reg($src$$reg,12,48) |
2103 Assembler::reg($shft$$reg,16,48) |
2104 Assembler::simm20(0));
2105 %}
2106
2107 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2108 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2109 z_emit32(masm, $primary |
2110 Assembler::reg($dst$$reg,8,32) |
2111 Assembler::reg($src1$$reg,12,32) |
2112 Assembler::reg($src2$$reg,16,32) |
2113 Assembler::uimm12($con$$constant,20,32));
2114 %}
2115
2116 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
2117 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2118 z_emit32(masm, $primary |
2119 Assembler::reg($dst$$reg,8,32) |
2120 Assembler::reg($src$$reg,16,32) |
2121 Assembler::uimm12($con$$constant,20,32));
2122 %}
2123
2124 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2125 z_emit48(masm, $primary |
2126 Assembler::reg($dst$$reg,8,48) |
2127 Assembler::reg($src1$$reg,12,48) |
2128 Assembler::reg($src2$$reg,16,48) |
2129 Assembler::simm20($con$$constant));
2130 %}
2131
2132 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
2133 z_emit48(masm, $primary |
2134 Assembler::reg($dst$$reg,8,48) |
2135 Assembler::reg($src$$reg,16,48) |
2136 Assembler::simm20($con$$constant));
2137 %}
2138
2139 // Direct memory arithmetic.
2140 enc_class z_siyform(memoryRSY mem, immI8 src) %{
2141 int disp = $mem$$disp;
2142 Register base = reg_to_register_object($mem$$base);
2143 int con = $src$$constant;
2144
2145 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
2146 z_emit_inst(masm, $primary |
2147 Assembler::regz(base,16,48) |
2148 Assembler::simm20(disp) |
2149 Assembler::simm8(con,8,48));
2150 %}
2151
2152 enc_class z_silform(memoryRS mem, immI16 src) %{
2153 z_emit_inst(masm, $primary |
2154 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
2155 Assembler::uimm12($mem$$disp,20,48) |
2156 Assembler::simm16($src$$constant,32,48));
2157 %}
2158
2159 // Encoder for FP ALU reg/mem instructions (support only short displacements).
2160 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
2161 Register Ridx = $mem$$index$$Register;
2162 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2163 if ($primary > (1L << 32)) {
2164 z_emit_inst(masm, $primary |
2165 Assembler::reg($dst$$reg, 8, 48) |
2166 Assembler::uimm12($mem$$disp, 20, 48) |
2167 Assembler::reg(Ridx, 12, 48) |
2168 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2169 } else {
2170 z_emit_inst(masm, $primary |
2171 Assembler::reg($dst$$reg, 8, 32) |
2172 Assembler::uimm12($mem$$disp, 20, 32) |
2173 Assembler::reg(Ridx, 12, 32) |
2174 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2175 }
2176 %}
2177
2178 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
2179 Register Ridx = $mem$$index$$Register;
2180 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2181 if ($primary > (1L<<32)) {
2182 z_emit_inst(masm, $primary |
2183 Assembler::reg($dst$$reg, 8, 48) |
2184 Assembler::simm20($mem$$disp) |
2185 Assembler::reg(Ridx, 12, 48) |
2186 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2187 } else {
2188 z_emit_inst(masm, $primary |
2189 Assembler::reg($dst$$reg, 8, 32) |
2190 Assembler::uimm12($mem$$disp, 20, 32) |
2191 Assembler::reg(Ridx, 12, 32) |
2192 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2193 }
2194 %}
2195
2196 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
2197 int isize = $secondary > 1L << 32 ? 48 : 32;
2198 Register Ridx = $mem$$index$$Register;
2199 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2200
2201 if (Displacement::is_shortDisp((long)$mem$$disp)) {
2202 z_emit_inst(masm, $secondary |
2203 Assembler::reg($dst$$reg, 8, isize) |
2204 Assembler::uimm12($mem$$disp, 20, isize) |
2205 Assembler::reg(Ridx, 12, isize) |
2206 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2207 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
2208 z_emit_inst(masm, $primary |
2209 Assembler::reg($dst$$reg, 8, 48) |
2210 Assembler::simm20($mem$$disp) |
2211 Assembler::reg(Ridx, 12, 48) |
2212 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2213 } else {
2214 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2215 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2216 z_emit_inst(masm, $secondary |
2217 Assembler::reg($dst$$reg, 8, isize) |
2218 Assembler::uimm12(0, 20, isize) |
2219 Assembler::reg(Z_R1_scratch, 12, isize) |
2220 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2221 }
2222 %}
2223
2224 enc_class z_enc_brul(Label lbl) %{
2225 Label* p = $lbl$$label;
2226
2227 // 'p' is `nullptr' when this encoding class is used only to
2228 // determine the size of the encoded instruction.
2229 // Use a bound dummy label in that case.
2230 Label d;
2231 __ bind(d);
2232 Label& l = (nullptr == p) ? d : *(p);
2233 __ z_brul(l);
2234 %}
2235
2236 enc_class z_enc_bru(Label lbl) %{
2237 Label* p = $lbl$$label;
2238
2239 // 'p' is `nullptr' when this encoding class is used only to
2240 // determine the size of the encoded instruction.
2241 // Use a bound dummy label in that case.
2242 Label d;
2243 __ bind(d);
2244 Label& l = (nullptr == p) ? d : *(p);
2245 __ z_bru(l);
2246 %}
2247
2248 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2249 Label* p = $lbl$$label;
2250
2251 // 'p' is `nullptr' when this encoding class is used only to
2252 // determine the size of the encoded instruction.
2253 // Use a bound dummy label in that case.
2254 Label d;
2255 __ bind(d);
2256 Label& l = (nullptr == p) ? d : *(p);
2257 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2258 %}
2259
2260 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2261 Label* p = $lbl$$label;
2262
2263 // 'p' is `nullptr' when this encoding class is used only to
2264 // determine the size of the encoded instruction.
2265 // Use a bound dummy label in that case.
2266 Label d;
2267 __ bind(d);
2268 Label& l = (nullptr == p) ? d : *(p);
2269 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2270 %}
2271
2272 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2273 Label* p = $lbl$$label;
2274
2275 // 'p' is `nullptr' when this encoding class is used only to
2276 // determine the size of the encoded instruction.
2277 // Use a bound dummy label in that case.
2278 Label d;
2279 __ bind(d);
2280 Label& l = (nullptr == p) ? d : *(p);
2281 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2282 unsigned long instr = $primary;
2283 if (instr == CRJ_ZOPC) {
2284 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2285 } else if (instr == CLRJ_ZOPC) {
2286 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2287 } else if (instr == CGRJ_ZOPC) {
2288 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2289 } else {
2290 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2291 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2292 }
2293 %}
2294
2295 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2296 Label* p = $lbl$$label;
2297
2298 // 'p' is `nullptr' when this encoding class is used only to
2299 // determine the size of the encoded instruction.
2300 // Use a bound dummy label in that case.
2301 Label d;
2302 __ bind(d);
2303 Label& l = (nullptr == p) ? d : *(p);
2304
2305 unsigned long instr = $primary;
2306 if (instr == CR_ZOPC) {
2307 __ z_cr($src1$$Register, $src2$$Register);
2308 } else if (instr == CLR_ZOPC) {
2309 __ z_clr($src1$$Register, $src2$$Register);
2310 } else if (instr == CGR_ZOPC) {
2311 __ z_cgr($src1$$Register, $src2$$Register);
2312 } else {
2313 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2314 __ z_clgr($src1$$Register, $src2$$Register);
2315 }
2316
2317 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2318 %}
2319
2320 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2321 Label* p = $lbl$$label;
2322
2323 // 'p' is `nullptr' when this encoding class is used only to
2324 // determine the size of the encoded instruction.
2325 // Use a bound dummy label in that case.
2326 Label d;
2327 __ bind(d);
2328 Label& l = (nullptr == p) ? d : *(p);
2329
2330 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2331 unsigned long instr = $primary;
2332 if (instr == CIJ_ZOPC) {
2333 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2334 } else if (instr == CLIJ_ZOPC) {
2335 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2336 } else if (instr == CGIJ_ZOPC) {
2337 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2338 } else {
2339 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2340 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2341 }
2342 %}
2343
2344 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2345 Label* p = $lbl$$label;
2346
2347 // 'p' is `nullptr' when this encoding class is used only to
2348 // determine the size of the encoded instruction.
2349 // Use a bound dummy label in that case.
2350 Label d;
2351 __ bind(d);
2352 Label& l = (nullptr == p) ? d : *(p);
2353
2354 unsigned long instr = $primary;
2355 if (instr == CHI_ZOPC) {
2356 __ z_chi($src1$$Register, $src2$$constant);
2357 } else if (instr == CLFI_ZOPC) {
2358 __ z_clfi($src1$$Register, $src2$$constant);
2359 } else if (instr == CGHI_ZOPC) {
2360 __ z_cghi($src1$$Register, $src2$$constant);
2361 } else {
2362 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2363 __ z_clgfi($src1$$Register, $src2$$constant);
2364 }
2365
2366 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2367 %}
2368
2369 // Call from Java to runtime.
2370 enc_class z_enc_java_to_runtime_call(method meth) %{
2371 // Save return pc before call to the place where we need it, since
2372 // callee doesn't.
2373 unsigned int start_off = __ offset();
2374 // Compute size of "larl + stg + call_c_opt".
2375 __ get_PC(Z_R14, ret_addr_offset());
2376 __ save_return_pc();
2377 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2378
2379 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2380 address call_addr = __ call_c_opt((address)$meth$$method);
2381 if (call_addr == nullptr) {
2382 Compile::current()->env()->record_out_of_memory_failure();
2383 return;
2384 }
2385
2386 assert(__ offset() - start_off == (uint)ret_addr_offset(),
2387 "z_enc_java_to_runtime_call return offset mismatch: emitted %d bytes, ret_addr_offset()=%d",
2388 __ offset() - start_off, ret_addr_offset());
2389 __ post_call_nop();
2390 %}
2391
2392 enc_class z_enc_java_static_call(method meth) %{
2393 unsigned int start_off = __ offset();
2394 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2395 // whom we intended to call.
2396
2397 if (!_method) {
2398 emit_call_reloc(masm, $meth$$method,
2399 relocInfo::runtime_call_w_cp_type, ra_);
2400 } else {
2401 int method_index = resolved_method_index(masm);
2402 if (_optimized_virtual) {
2403 emit_call_reloc(masm, $meth$$method,
2404 opt_virtual_call_Relocation::spec(method_index));
2405 } else {
2406 emit_call_reloc(masm, $meth$$method,
2407 static_call_Relocation::spec(method_index));
2408 }
2409 }
2410 assert(__ inst_mark() != nullptr, "emit_call_reloc must set_inst_mark()");
2411
2412 if (_method) { // Emit stub for static call.
2413 address stub = CompiledDirectCall::emit_to_interp_stub(masm);
2414 if (stub == nullptr) {
2415 __ clear_inst_mark();
2416 ciEnv::current()->record_failure("CodeCache is full");
2417 return;
2418 }
2419 }
2420
2421 __ clear_inst_mark();
2422 assert(__ offset() - start_off == (uint)ret_addr_offset(),
2423 "z_enc_java_static_call return offset mismatch: emitted %d bytes, ret_addr_offset()=%d",
2424 __ offset() - start_off, ret_addr_offset());
2425 __ post_call_nop();
2426 %}
2427
2428 // Java dynamic call
2429 enc_class z_enc_java_dynamic_call(method meth) %{
2430 unsigned int start_off = __ offset();
2431
2432 int vtable_index = this->_vtable_index;
2433 if (vtable_index == -4) {
2434 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2435 address virtual_call_oop_addr = nullptr;
2436
2437 AddressLiteral empty_ic((address) Universe::non_oop_word());
2438 virtual_call_oop_addr = __ pc();
2439 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2440 if (!success) {
2441 Compile::current()->env()->record_out_of_memory_failure();
2442 return;
2443 }
2444
2445 // Call to fixup routine. Fixup routine uses ScopeDesc info
2446 // to determine who we intended to call.
2447 int method_index = resolved_method_index(masm);
2448 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2449 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2450 emit_call_reloc(masm, $meth$$method, relocInfo::none, ra_);
2451 __ clear_inst_mark();
2452 assert(_method, "lazy_constant may be wrong when _method==null");
2453 } else {
2454 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2455 // Go through the vtable. Get receiver klass. Receiver already
2456 // checked for non-null. If we'll go thru a C2I adapter, the
2457 // interpreter expects method in Z_method.
2458 // Use Z_method to temporarily hold the klass oop.
2459 // Z_R1_scratch is destroyed.
2460 __ load_klass(Z_method, Z_R2);
2461
2462 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2463 int v_off = entry_offset + in_bytes(vtableEntry::method_offset());
2464
2465 if (Displacement::is_validDisp(v_off) ) {
2466 // Can use load instruction with large offset.
2467 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2468 } else {
2469 // Worse case, must load offset into register.
2470 __ load_const(Z_R1_scratch, v_off);
2471 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2472 }
2473 // NOTE: for vtable dispatches, the vtable entry will never be
2474 // null. However it may very well end up in handle_wrong_method
2475 // if the method is abstract for the particular class.
2476 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2477 // Call target. Either compiled code or C2I adapter.
2478 __ z_basr(Z_R14, Z_R1_scratch);
2479 }
2480 assert(__ offset() - start_off == (uint)ret_addr_offset(),
2481 "z_enc_java_dynamic_call return offset mismatch: emitted %d bytes, ret_addr_offset()=%d",
2482 __ offset() - start_off, ret_addr_offset());
2483
2484 __ post_call_nop();
2485 %}
2486
2487 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2488 Register Rdst = reg_to_register_object($dst$$reg);
2489 Register Rsrc = reg_to_register_object($src$$reg);
2490
2491 // Don't emit code if operands are identical (same register).
2492 if (Rsrc != Rdst) {
2493 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2494
2495 if (VM_Version::has_LoadStoreConditional()) {
2496 __ z_locgr(Rdst, Rsrc, cc);
2497 } else {
2498 // Branch if not (cmp cr).
2499 Label done;
2500 __ z_brc(Assembler::inverse_condition(cc), done);
2501 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2502 __ bind(done);
2503 }
2504 }
2505 %}
2506
2507 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2508 Register Rdst = reg_to_register_object($dst$$reg);
2509 int Csrc = $src$$constant;
2510 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2511 Label done;
2512 // Branch if not (cmp cr).
2513 __ z_brc(Assembler::inverse_condition(cc), done);
2514 if (Csrc == 0) {
2515 // Don't set CC.
2516 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2517 } else {
2518 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2519 }
2520 __ bind(done);
2521 %}
2522
2523 enc_class z_enc_cctobool(iRegI res) %{
2524 Register Rres = reg_to_register_object($res$$reg);
2525
2526 if (VM_Version::has_LoadStoreConditional()) {
2527 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2528 __ load_const_optimized(Rres, 1L); // true (succeed)
2529 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2530 } else {
2531 Label done;
2532 __ load_const_optimized(Rres, 0L); // false (failed)
2533 __ z_brne(done); // Assume true to be the common case.
2534 __ load_const_optimized(Rres, 1L); // true (succeed)
2535 __ bind(done);
2536 }
2537 %}
2538
2539 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2540 Register Rcomp = reg_to_register_object($compare_value$$reg);
2541 Register Rnew = reg_to_register_object($exchange_value$$reg);
2542 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2543
2544 __ z_cs(Rcomp, Rnew, 0, Raddr);
2545 %}
2546
2547 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2548 Register Rcomp = reg_to_register_object($compare_value$$reg);
2549 Register Rnew = reg_to_register_object($exchange_value$$reg);
2550 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2551
2552 __ z_csg(Rcomp, Rnew, 0, Raddr);
2553 %}
2554
2555 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2556 Register Rdst = reg_to_register_object($dst$$reg);
2557 Register Rtmp = reg_to_register_object($tmp$$reg);
2558 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2559 Label retry;
2560
2561 // Iterate until swap succeeds.
2562 __ z_llgf(Rtmp, $mem$$Address); // current contents
2563 __ bind(retry);
2564 // Calculate incremented value.
2565 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2566 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2567 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2568 %}
2569
2570 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2571 Register Rdst = reg_to_register_object($dst$$reg);
2572 Register Rtmp = reg_to_register_object($tmp$$reg);
2573 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2574 Label retry;
2575
2576 // Iterate until swap succeeds.
2577 __ z_lg(Rtmp, $mem$$Address); // current contents
2578 __ bind(retry);
2579 // Calculate incremented value.
2580 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2581 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2582 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2583 %}
2584
2585 %} // encode
2586
2587 source %{
2588
2589 // Check whether outs are all Stores. If so, we can omit clearing the upper
2590 // 32 bits after encoding.
2591 static bool all_outs_are_Stores(const Node *n) {
2592 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2593 Node *out = n->fast_out(k);
2594 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2595 // Most other outs are SpillCopy, but there are various other.
2596 // jvm98 has arond 9% Encodes where we return false.
2597 return false;
2598 }
2599 }
2600 return true;
2601 }
2602
2603 %} // source
2604
2605
2606 //----------FRAME--------------------------------------------------------------
2607 // Definition of frame structure and management information.
2608
2609 frame %{
2610 // These two registers define part of the calling convention between
2611 // compiled code and the interpreter.
2612
2613 // Inline Cache Register
2614 inline_cache_reg(Z_R9); // Z_inline_cache
2615
2616 // Argument pointer for I2C adapters
2617 //
2618 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2619 // interpreter_arg_ptr_reg(Z_R6);
2620
2621 // Optional: name the operand used by cisc-spilling to access
2622 // [stack_pointer + offset].
2623 cisc_spilling_operand_name(indOffset12);
2624
2625 // Number of stack slots consumed by a Monitor enter.
2626 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2627
2628 // Compiled code's Frame Pointer
2629 //
2630 // z/Architecture stack pointer
2631 frame_pointer(Z_R15); // Z_SP
2632
2633 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2634 stack_alignment(frame::alignment_in_bytes);
2635
2636 // A `slot' is assumed 4 bytes here!
2637 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2638
2639 // Number of outgoing stack slots killed above the
2640 // out_preserve_stack_slots for calls to C. Supports the var-args
2641 // backing area for register parms.
2642 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2643
2644 // The after-PROLOG location of the return address. Location of
2645 // return address specifies a type (REG or STACK) and a number
2646 // representing the register number (i.e. - use a register name) or
2647 // stack slot.
2648 return_addr(REG Z_R14);
2649
2650 // Use register pair for return value.
2651 // Location of compiled Java return values. Same as C
2652 return_value %{
2653 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2654 static const int lo[Op_RegL + 1] = {
2655 0,
2656 0,
2657 Z_R2_num, // Op_RegN
2658 Z_R2_num, // Op_RegI
2659 Z_R2_num, // Op_RegP
2660 Z_F0_num, // Op_RegF
2661 Z_F0_num, // Op_RegD
2662 Z_R2_num // Op_RegL
2663 };
2664 static const int hi[Op_RegL + 1] = {
2665 0,
2666 0,
2667 OptoReg::Bad, // Op_RegN
2668 OptoReg::Bad, // Op_RegI
2669 Z_R2_H_num, // Op_RegP
2670 OptoReg::Bad, // Op_RegF
2671 Z_F0_H_num, // Op_RegD
2672 Z_R2_H_num // Op_RegL
2673 };
2674 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2675 %}
2676 %}
2677
2678
2679 //----------ATTRIBUTES---------------------------------------------------------
2680
2681 //----------Operand Attributes-------------------------------------------------
2682 op_attrib op_cost(1); // Required cost attribute
2683
2684 //----------Instruction Attributes---------------------------------------------
2685
2686 // Cost attribute. required.
2687 ins_attrib ins_cost(DEFAULT_COST);
2688
2689 // Is this instruction a non-matching short branch variant of some
2690 // long branch? Not required.
2691 ins_attrib ins_short_branch(0);
2692
2693 // Indicates this is a trap based check node and final control-flow fixup
2694 // must generate a proper fall through.
2695 ins_attrib ins_is_TrapBasedCheckNode(true);
2696
2697 // Attribute of instruction to tell how many constants the instruction will generate.
2698 // (optional attribute). Default: 0.
2699 ins_attrib ins_num_consts(0);
2700
2701 // Required alignment attribute (must be a power of 2)
2702 // specifies the alignment that some part of the instruction (not
2703 // necessarily the start) requires. If > 1, a compute_padding()
2704 // function must be provided for the instruction.
2705 //
2706 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2707 // instructions which depend on the proper alignment, because the
2708 // desired alignment isn't guaranteed for the call to "emit()" during
2709 // the size computation.
2710 ins_attrib ins_alignment(1);
2711
2712 // Enforce/prohibit rematerializations.
2713 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2714 // then rematerialization of that instruction is prohibited and the
2715 // instruction's value will be spilled if necessary.
2716 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2717 // then rematerialization is enforced and the instruction's value will
2718 // never get spilled. a copy of the instruction will be inserted if
2719 // necessary.
2720 // Note: this may result in rematerializations in front of every use.
2721 // (optional attribute)
2722 ins_attrib ins_cannot_rematerialize(false);
2723 ins_attrib ins_should_rematerialize(false);
2724
2725 //----------OPERANDS-----------------------------------------------------------
2726 // Operand definitions must precede instruction definitions for correct
2727 // parsing in the ADLC because operands constitute user defined types
2728 // which are used in instruction definitions.
2729
2730 //----------Simple Operands----------------------------------------------------
2731 // Immediate Operands
2732 // Please note:
2733 // Formats are generated automatically for constants and base registers.
2734 operand vecX() %{
2735 constraint(ALLOC_IN_RC(z_v_reg));
2736 match(VecX);
2737 match(v16TempReg);
2738 match(v17TempReg);
2739 match(v18TempReg);
2740 match(v19TempReg);
2741 match(v20TempReg);
2742 match(v21TempReg);
2743 match(v22TempReg);
2744 match(v23TempReg);
2745 match(v24TempReg);
2746 match(v25TempReg);
2747 format %{ %}
2748 interface(REG_INTER);
2749 %}
2750
2751 operand v16TempReg() %{
2752 constraint(ALLOC_IN_RC(z_vreg_16));
2753 match(VecX);
2754 format %{ %}
2755 interface(REG_INTER);
2756 %}
2757
2758 operand v17TempReg() %{
2759 constraint(ALLOC_IN_RC(z_vreg_17));
2760 match(VecX);
2761 format %{ %}
2762 interface(REG_INTER);
2763 %}
2764
2765 operand v18TempReg() %{
2766 constraint(ALLOC_IN_RC(z_vreg_18));
2767 match(VecX);
2768 format %{ %}
2769 interface(REG_INTER);
2770 %}
2771
2772 operand v19TempReg() %{
2773 constraint(ALLOC_IN_RC(z_vreg_19));
2774 match(VecX);
2775 format %{ %}
2776 interface(REG_INTER);
2777 %}
2778
2779 operand v20TempReg() %{
2780 constraint(ALLOC_IN_RC(z_vreg_20));
2781 match(VecX);
2782 format %{ %}
2783 interface(REG_INTER);
2784 %}
2785
2786 operand v21TempReg() %{
2787 constraint(ALLOC_IN_RC(z_vreg_21));
2788 match(VecX);
2789 format %{ %}
2790 interface(REG_INTER);
2791 %}
2792
2793 operand v22TempReg() %{
2794 constraint(ALLOC_IN_RC(z_vreg_22));
2795 match(VecX);
2796 format %{ %}
2797 interface(REG_INTER);
2798 %}
2799
2800 operand v23TempReg() %{
2801 constraint(ALLOC_IN_RC(z_vreg_23));
2802 match(VecX);
2803 format %{ %}
2804 interface(REG_INTER);
2805 %}
2806
2807 operand v24TempReg() %{
2808 constraint(ALLOC_IN_RC(z_vreg_24));
2809 match(VecX);
2810 format %{ %}
2811 interface(REG_INTER);
2812 %}
2813
2814 operand v25TempReg() %{
2815 constraint(ALLOC_IN_RC(z_vreg_25));
2816 match(VecX);
2817 format %{ %}
2818 interface(REG_INTER);
2819 %}
2820
2821 //----------------------------------------------
2822 // SIGNED (shorter than INT) immediate operands
2823 //----------------------------------------------
2824
2825 // Byte Immediate: constant 'int -1'
2826 operand immB_minus1() %{
2827 // sign-ext constant zero-ext constant
2828 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2829 match(ConI);
2830 op_cost(1);
2831 format %{ %}
2832 interface(CONST_INTER);
2833 %}
2834
2835 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2836 operand immB_n0m1() %{
2837 // sign-ext constant zero-ext constant
2838 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2839 match(ConI);
2840 op_cost(1);
2841 format %{ %}
2842 interface(CONST_INTER);
2843 %}
2844
2845 // Short Immediate: constant 'int -1'
2846 operand immS_minus1() %{
2847 // sign-ext constant zero-ext constant
2848 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2849 match(ConI);
2850 op_cost(1);
2851 format %{ %}
2852 interface(CONST_INTER);
2853 %}
2854
2855 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2856 operand immS_n0m1() %{
2857 // sign-ext constant zero-ext constant
2858 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2859 match(ConI);
2860 op_cost(1);
2861 format %{ %}
2862 interface(CONST_INTER);
2863 %}
2864
2865 //-----------------------------------------
2866 // SIGNED INT immediate operands
2867 //-----------------------------------------
2868
2869 // Integer Immediate: 32-bit
2870 operand immI() %{
2871 match(ConI);
2872 op_cost(1);
2873 format %{ %}
2874 interface(CONST_INTER);
2875 %}
2876
2877 // Int Immediate: 20-bit
2878 operand immI20() %{
2879 predicate(Immediate::is_simm20(n->get_int()));
2880 match(ConI);
2881 op_cost(1);
2882 format %{ %}
2883 interface(CONST_INTER);
2884 %}
2885
2886 // Integer Immediate: 16-bit
2887 operand immI16() %{
2888 predicate(Immediate::is_simm16(n->get_int()));
2889 match(ConI);
2890 op_cost(1);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 // Integer Immediate: 8-bit
2896 operand immI8() %{
2897 predicate(Immediate::is_simm8(n->get_int()));
2898 match(ConI);
2899 op_cost(1);
2900 format %{ %}
2901 interface(CONST_INTER);
2902 %}
2903
2904 // Integer Immediate: constant 'int 0'
2905 operand immI_0() %{
2906 predicate(n->get_int() == 0);
2907 match(ConI);
2908 op_cost(1);
2909 format %{ %}
2910 interface(CONST_INTER);
2911 %}
2912
2913 // Integer Immediate: constant 'int -1'
2914 operand immI_minus1() %{
2915 predicate(n->get_int() == -1);
2916 match(ConI);
2917 op_cost(1);
2918 format %{ %}
2919 interface(CONST_INTER);
2920 %}
2921
2922 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2923 operand immI_n0m1() %{
2924 predicate(n->get_int() != 0 && n->get_int() != -1);
2925 match(ConI);
2926 op_cost(1);
2927 format %{ %}
2928 interface(CONST_INTER);
2929 %}
2930
2931 //-------------------------------------------
2932 // UNSIGNED INT immediate operands
2933 //-------------------------------------------
2934
2935 // Unsigned Integer Immediate: 32-bit
2936 operand uimmI() %{
2937 match(ConI);
2938 op_cost(1);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 // Unsigned Integer Immediate: 16-bit
2944 operand uimmI16() %{
2945 predicate(Immediate::is_uimm16(n->get_int()));
2946 match(ConI);
2947 op_cost(1);
2948 format %{ %}
2949 interface(CONST_INTER);
2950 %}
2951
2952 // Unsigned Integer Immediate: 12-bit
2953 operand uimmI12() %{
2954 predicate(Immediate::is_uimm12(n->get_int()));
2955 match(ConI);
2956 op_cost(1);
2957 format %{ %}
2958 interface(CONST_INTER);
2959 %}
2960
2961 // Unsigned Integer Immediate: 12-bit
2962 operand uimmI8() %{
2963 predicate(Immediate::is_uimm8(n->get_int()));
2964 match(ConI);
2965 op_cost(1);
2966 format %{ %}
2967 interface(CONST_INTER);
2968 %}
2969
2970 // Length for SS instructions, given in DWs,
2971 // possible range [1..512], i.e. [8..4096] Bytes
2972 // used range [1..256], i.e. [8..2048] Bytes
2973 // operand type int
2974 // Unsigned Integer Immediate: 9-bit
2975 operand SSlenDW() %{
2976 predicate(Immediate::is_uimm8((julong)n->get_long()-1));
2977 match(ConL);
2978 op_cost(1);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 //------------------------------------------
2984 // (UN)SIGNED INT specific values
2985 //------------------------------------------
2986
2987 // Integer Immediate: the value 1
2988 operand immI_1() %{
2989 predicate(n->get_int() == 1);
2990 match(ConI);
2991 op_cost(1);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 // Integer Immediate: the value 16.
2997 operand immI_16() %{
2998 predicate(n->get_int() == 16);
2999 match(ConI);
3000 op_cost(1);
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 // Integer Immediate: the value 24.
3006 operand immI_24() %{
3007 predicate(n->get_int() == 24);
3008 match(ConI);
3009 op_cost(1);
3010 format %{ %}
3011 interface(CONST_INTER);
3012 %}
3013
3014 // Integer Immediate: the values 32-63
3015 operand immI_32_63() %{
3016 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3017 match(ConI);
3018 op_cost(1);
3019 format %{ %}
3020 interface(CONST_INTER);
3021 %}
3022
3023 // Unsigned Integer Immediate: LL-part, extended by 1s.
3024 operand uimmI_LL1() %{
3025 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
3026 match(ConI);
3027 op_cost(1);
3028 format %{ %}
3029 interface(CONST_INTER);
3030 %}
3031
3032 // Unsigned Integer Immediate: LH-part, extended by 1s.
3033 operand uimmI_LH1() %{
3034 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
3035 match(ConI);
3036 op_cost(1);
3037 format %{ %}
3038 interface(CONST_INTER);
3039 %}
3040
3041 //------------------------------------------
3042 // SIGNED LONG immediate operands
3043 //------------------------------------------
3044
3045 operand immL() %{
3046 match(ConL);
3047 op_cost(1);
3048 format %{ %}
3049 interface(CONST_INTER);
3050 %}
3051
3052 // Long Immediate: 32-bit
3053 operand immL32() %{
3054 predicate(Immediate::is_simm32(n->get_long()));
3055 match(ConL);
3056 op_cost(1);
3057 format %{ %}
3058 interface(CONST_INTER);
3059 %}
3060
3061 // Long Immediate: 20-bit
3062 operand immL20() %{
3063 predicate(Immediate::is_simm20(n->get_long()));
3064 match(ConL);
3065 op_cost(1);
3066 format %{ %}
3067 interface(CONST_INTER);
3068 %}
3069
3070 // Long Immediate: 16-bit
3071 operand immL16() %{
3072 predicate(Immediate::is_simm16(n->get_long()));
3073 match(ConL);
3074 op_cost(1);
3075 format %{ %}
3076 interface(CONST_INTER);
3077 %}
3078
3079 // Long Immediate: 8-bit
3080 operand immL8() %{
3081 predicate(Immediate::is_simm8(n->get_long()));
3082 match(ConL);
3083 op_cost(1);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3087
3088 //--------------------------------------------
3089 // UNSIGNED LONG immediate operands
3090 //--------------------------------------------
3091
3092 operand uimmL32() %{
3093 predicate(Immediate::is_uimm32(n->get_long()));
3094 match(ConL);
3095 op_cost(1);
3096 format %{ %}
3097 interface(CONST_INTER);
3098 %}
3099
3100 // Unsigned Long Immediate: 16-bit
3101 operand uimmL16() %{
3102 predicate(Immediate::is_uimm16(n->get_long()));
3103 match(ConL);
3104 op_cost(1);
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3108
3109 // Unsigned Long Immediate: 12-bit
3110 operand uimmL12() %{
3111 predicate(Immediate::is_uimm12(n->get_long()));
3112 match(ConL);
3113 op_cost(1);
3114 format %{ %}
3115 interface(CONST_INTER);
3116 %}
3117
3118 //-------------------------------------------
3119 // (UN)SIGNED LONG specific values
3120 //-------------------------------------------
3121
3122 // Long Immediate: the value FFFFFFFF
3123 operand immL_FFFFFFFF() %{
3124 predicate(n->get_long() == 0xFFFFFFFFL);
3125 match(ConL);
3126 op_cost(1);
3127 format %{ %}
3128 interface(CONST_INTER);
3129 %}
3130
3131 operand immL_0() %{
3132 predicate(n->get_long() == 0L);
3133 match(ConL);
3134 op_cost(1);
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // Unsigned Long Immediate: LL-part, extended by 1s.
3140 operand uimmL_LL1() %{
3141 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
3142 match(ConL);
3143 op_cost(1);
3144 format %{ %}
3145 interface(CONST_INTER);
3146 %}
3147
3148 // Unsigned Long Immediate: LH-part, extended by 1s.
3149 operand uimmL_LH1() %{
3150 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
3151 match(ConL);
3152 op_cost(1);
3153 format %{ %}
3154 interface(CONST_INTER);
3155 %}
3156
3157 // Unsigned Long Immediate: HL-part, extended by 1s.
3158 operand uimmL_HL1() %{
3159 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
3160 match(ConL);
3161 op_cost(1);
3162 format %{ %}
3163 interface(CONST_INTER);
3164 %}
3165
3166 // Unsigned Long Immediate: HH-part, extended by 1s.
3167 operand uimmL_HH1() %{
3168 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
3169 match(ConL);
3170 op_cost(1);
3171 format %{ %}
3172 interface(CONST_INTER);
3173 %}
3174
3175 // Long Immediate: low 32-bit mask
3176 operand immL_32bits() %{
3177 predicate(n->get_long() == 0xFFFFFFFFL);
3178 match(ConL);
3179 op_cost(1);
3180 format %{ %}
3181 interface(CONST_INTER);
3182 %}
3183
3184 //--------------------------------------
3185 // POINTER immediate operands
3186 //--------------------------------------
3187
3188 // Pointer Immediate: 64-bit
3189 operand immP() %{
3190 match(ConP);
3191 op_cost(1);
3192 format %{ %}
3193 interface(CONST_INTER);
3194 %}
3195
3196 // Pointer Immediate: 16-bit
3197 operand immP16() %{
3198 predicate(Immediate::is_uimm16(n->get_ptr()));
3199 match(ConP);
3200 op_cost(1);
3201 format %{ %}
3202 interface(CONST_INTER);
3203 %}
3204
3205 // Pointer Immediate: 8-bit
3206 operand immP8() %{
3207 predicate(Immediate::is_uimm8(n->get_ptr()));
3208 match(ConP);
3209 op_cost(1);
3210 format %{ %}
3211 interface(CONST_INTER);
3212 %}
3213
3214 //-----------------------------------
3215 // POINTER specific values
3216 //-----------------------------------
3217
3218 // Pointer Immediate: nullptr
3219 operand immP0() %{
3220 predicate(n->get_ptr() == 0);
3221 match(ConP);
3222 op_cost(1);
3223 format %{ %}
3224 interface(CONST_INTER);
3225 %}
3226
3227 //---------------------------------------------
3228 // NARROW POINTER immediate operands
3229 //---------------------------------------------
3230
3231 // Narrow Pointer Immediate
3232 operand immN() %{
3233 match(ConN);
3234 op_cost(1);
3235 format %{ %}
3236 interface(CONST_INTER);
3237 %}
3238
3239 operand immNKlass() %{
3240 match(ConNKlass);
3241 op_cost(1);
3242 format %{ %}
3243 interface(CONST_INTER);
3244 %}
3245
3246 // Narrow Pointer Immediate
3247 operand immN8() %{
3248 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3249 match(ConN);
3250 op_cost(1);
3251 format %{ %}
3252 interface(CONST_INTER);
3253 %}
3254
3255 // Narrow Null Pointer Immediate
3256 operand immN0() %{
3257 predicate(n->get_narrowcon() == 0);
3258 match(ConN);
3259 op_cost(1);
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // FLOAT and DOUBLE immediate operands
3265
3266 // Double Immediate
3267 operand immD() %{
3268 match(ConD);
3269 op_cost(1);
3270 format %{ %}
3271 interface(CONST_INTER);
3272 %}
3273
3274 // Double Immediate: +-0
3275 operand immDpm0() %{
3276 predicate(n->getd() == 0);
3277 match(ConD);
3278 op_cost(1);
3279 format %{ %}
3280 interface(CONST_INTER);
3281 %}
3282
3283 // Double Immediate: +0
3284 operand immDp0() %{
3285 predicate(jlong_cast(n->getd()) == 0);
3286 match(ConD);
3287 op_cost(1);
3288 format %{ %}
3289 interface(CONST_INTER);
3290 %}
3291
3292 // Float Immediate
3293 operand immF() %{
3294 match(ConF);
3295 op_cost(1);
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3299
3300 // Float Immediate: +-0
3301 operand immFpm0() %{
3302 predicate(n->getf() == 0);
3303 match(ConF);
3304 op_cost(1);
3305 format %{ %}
3306 interface(CONST_INTER);
3307 %}
3308
3309 // Float Immediate: +0
3310 operand immFp0() %{
3311 predicate(jint_cast(n->getf()) == 0);
3312 match(ConF);
3313 op_cost(1);
3314 format %{ %}
3315 interface(CONST_INTER);
3316 %}
3317
3318 // End of Immediate Operands
3319
3320 // Integer Register Operands
3321 // Integer Register
3322 operand iRegI() %{
3323 constraint(ALLOC_IN_RC(z_int_reg));
3324 match(RegI);
3325 match(noArg_iRegI);
3326 match(rarg1RegI);
3327 match(rarg2RegI);
3328 match(rarg3RegI);
3329 match(rarg4RegI);
3330 match(rarg5RegI);
3331 match(noOdd_iRegI);
3332 match(revenRegI);
3333 match(roddRegI);
3334 format %{ %}
3335 interface(REG_INTER);
3336 %}
3337
3338 operand noArg_iRegI() %{
3339 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3340 match(RegI);
3341 format %{ %}
3342 interface(REG_INTER);
3343 %}
3344
3345 // revenRegI and roddRegI constitute and even-odd-pair.
3346 operand revenRegI() %{
3347 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3348 match(iRegI);
3349 format %{ %}
3350 interface(REG_INTER);
3351 %}
3352
3353 // revenRegI and roddRegI constitute and even-odd-pair.
3354 operand roddRegI() %{
3355 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3356 match(iRegI);
3357 format %{ %}
3358 interface(REG_INTER);
3359 %}
3360
3361 operand rarg1RegI() %{
3362 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3363 match(iRegI);
3364 format %{ %}
3365 interface(REG_INTER);
3366 %}
3367
3368 operand rarg2RegI() %{
3369 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3370 match(iRegI);
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 operand rarg3RegI() %{
3376 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3377 match(iRegI);
3378 format %{ %}
3379 interface(REG_INTER);
3380 %}
3381
3382 operand rarg4RegI() %{
3383 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3384 match(iRegI);
3385 format %{ %}
3386 interface(REG_INTER);
3387 %}
3388
3389 operand rarg5RegI() %{
3390 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3391 match(iRegI);
3392 format %{ %}
3393 interface(REG_INTER);
3394 %}
3395
3396 operand noOdd_iRegI() %{
3397 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3398 match(RegI);
3399 match(revenRegI);
3400 format %{ %}
3401 interface(REG_INTER);
3402 %}
3403
3404 // Pointer Register
3405 operand iRegP() %{
3406 constraint(ALLOC_IN_RC(z_ptr_reg));
3407 match(RegP);
3408 match(noArg_iRegP);
3409 match(rarg1RegP);
3410 match(rarg2RegP);
3411 match(rarg3RegP);
3412 match(rarg4RegP);
3413 match(rarg5RegP);
3414 match(revenRegP);
3415 match(roddRegP);
3416 match(r10TempRegP);
3417 match(r11TempRegP);
3418 format %{ %}
3419 interface(REG_INTER);
3420 %}
3421
3422 // thread operand
3423 operand threadRegP() %{
3424 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3425 match(RegP);
3426 format %{ "Z_THREAD" %}
3427 interface(REG_INTER);
3428 %}
3429
3430 operand r10TempRegP() %{
3431 constraint(ALLOC_IN_RC(z_r10_ptr_reg));
3432 match(iRegP);
3433 format %{ %}
3434 interface(REG_INTER);
3435 %}
3436
3437 operand r11TempRegP() %{
3438 constraint(ALLOC_IN_RC(z_r11_ptr_reg));
3439 match(iRegP);
3440 format %{ %}
3441 interface(REG_INTER);
3442 %}
3443
3444 operand noArg_iRegP() %{
3445 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3446 match(iRegP);
3447 format %{ %}
3448 interface(REG_INTER);
3449 %}
3450
3451 operand rarg1RegP() %{
3452 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3453 match(iRegP);
3454 format %{ %}
3455 interface(REG_INTER);
3456 %}
3457
3458 operand rarg2RegP() %{
3459 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3460 match(iRegP);
3461 format %{ %}
3462 interface(REG_INTER);
3463 %}
3464
3465 operand rarg3RegP() %{
3466 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3467 match(iRegP);
3468 format %{ %}
3469 interface(REG_INTER);
3470 %}
3471
3472 operand rarg4RegP() %{
3473 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3474 match(iRegP);
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand rarg5RegP() %{
3480 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3481 match(iRegP);
3482 format %{ %}
3483 interface(REG_INTER);
3484 %}
3485
3486 operand memoryRegP() %{
3487 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3488 match(RegP);
3489 match(iRegP);
3490 match(threadRegP);
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3494
3495 // revenRegP and roddRegP constitute and even-odd-pair.
3496 operand revenRegP() %{
3497 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3498 match(iRegP);
3499 format %{ %}
3500 interface(REG_INTER);
3501 %}
3502
3503 // revenRegP and roddRegP constitute and even-odd-pair.
3504 operand roddRegP() %{
3505 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3506 match(iRegP);
3507 format %{ %}
3508 interface(REG_INTER);
3509 %}
3510
3511 operand iRegN() %{
3512 constraint(ALLOC_IN_RC(z_int_reg));
3513 match(RegN);
3514 match(noArg_iRegN);
3515 match(rarg1RegN);
3516 match(rarg2RegN);
3517 match(rarg3RegN);
3518 match(rarg4RegN);
3519 match(rarg5RegN);
3520 format %{ %}
3521 interface(REG_INTER);
3522 %}
3523
3524 operand noArg_iRegN() %{
3525 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3526 match(iRegN);
3527 format %{ %}
3528 interface(REG_INTER);
3529 %}
3530
3531 operand rarg1RegN() %{
3532 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3533 match(iRegN);
3534 format %{ %}
3535 interface(REG_INTER);
3536 %}
3537
3538 operand rarg2RegN() %{
3539 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3540 match(iRegN);
3541 format %{ %}
3542 interface(REG_INTER);
3543 %}
3544
3545 operand rarg3RegN() %{
3546 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3547 match(iRegN);
3548 format %{ %}
3549 interface(REG_INTER);
3550 %}
3551
3552 operand rarg4RegN() %{
3553 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3554 match(iRegN);
3555 format %{ %}
3556 interface(REG_INTER);
3557 %}
3558
3559 operand rarg5RegN() %{
3560 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3561 match(iRegN);
3562 format %{ %}
3563 interface(REG_INTER);
3564 %}
3565
3566 // Long Register
3567 operand iRegL() %{
3568 constraint(ALLOC_IN_RC(z_long_reg));
3569 match(RegL);
3570 match(revenRegL);
3571 match(roddRegL);
3572 match(allRoddRegL);
3573 match(rarg1RegL);
3574 match(rarg5RegL);
3575 format %{ %}
3576 interface(REG_INTER);
3577 %}
3578
3579 // revenRegL and roddRegL constitute and even-odd-pair.
3580 operand revenRegL() %{
3581 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3582 match(iRegL);
3583 format %{ %}
3584 interface(REG_INTER);
3585 %}
3586
3587 // revenRegL and roddRegL constitute and even-odd-pair.
3588 operand roddRegL() %{
3589 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3590 match(iRegL);
3591 format %{ %}
3592 interface(REG_INTER);
3593 %}
3594
3595 // available odd registers for iRegL
3596 operand allRoddRegL() %{
3597 constraint(ALLOC_IN_RC(z_long_odd_reg));
3598 match(iRegL);
3599 format %{ %}
3600 interface(REG_INTER);
3601 %}
3602
3603 operand rarg1RegL() %{
3604 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3605 match(iRegL);
3606 format %{ %}
3607 interface(REG_INTER);
3608 %}
3609
3610 operand rarg5RegL() %{
3611 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3612 match(iRegL);
3613 format %{ %}
3614 interface(REG_INTER);
3615 %}
3616
3617 // Condition Code Flag Registers
3618 operand flagsReg() %{
3619 constraint(ALLOC_IN_RC(z_condition_reg));
3620 match(RegFlags);
3621 format %{ "CR" %}
3622 interface(REG_INTER);
3623 %}
3624
3625 operand regD() %{
3626 constraint(ALLOC_IN_RC(z_dbl_reg));
3627 match(RegD);
3628 format %{ %}
3629 interface(REG_INTER);
3630 %}
3631
3632 operand regF() %{
3633 constraint(ALLOC_IN_RC(z_flt_reg));
3634 match(RegF);
3635 format %{ %}
3636 interface(REG_INTER);
3637 %}
3638
3639 // Special Registers
3640
3641 // Method Register
3642 operand inline_cache_regP(iRegP reg) %{
3643 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3644 match(reg);
3645 format %{ %}
3646 interface(REG_INTER);
3647 %}
3648
3649 //----------Complex Operands---------------------------------------------------
3650
3651 // Indirect Memory Reference
3652 operand indirect(memoryRegP base) %{
3653 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3654 match(base);
3655 op_cost(1);
3656 format %{ "#0[,$base]" %}
3657 interface(MEMORY_INTER) %{
3658 base($base);
3659 index(0xffffFFFF); // noreg
3660 scale(0x0);
3661 disp(0x0);
3662 %}
3663 %}
3664
3665 // Indirect with Offset (long)
3666 operand indOffset20(memoryRegP base, immL20 offset) %{
3667 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3668 match(AddP base offset);
3669 op_cost(1);
3670 format %{ "$offset[,$base]" %}
3671 interface(MEMORY_INTER) %{
3672 base($base);
3673 index(0xffffFFFF); // noreg
3674 scale(0x0);
3675 disp($offset);
3676 %}
3677 %}
3678
3679 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3680 predicate(Matcher::narrow_oop_use_complex_address());
3681 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3682 match(AddP (DecodeN base) offset);
3683 op_cost(1);
3684 format %{ "$offset[,$base]" %}
3685 interface(MEMORY_INTER) %{
3686 base($base);
3687 index(0xffffFFFF); // noreg
3688 scale(0x0);
3689 disp($offset);
3690 %}
3691 %}
3692
3693 // Indirect with Offset (short)
3694 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3695 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3696 match(AddP base offset);
3697 op_cost(1);
3698 format %{ "$offset[[,$base]]" %}
3699 interface(MEMORY_INTER) %{
3700 base($base);
3701 index(0xffffFFFF); // noreg
3702 scale(0x0);
3703 disp($offset);
3704 %}
3705 %}
3706
3707 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3708 predicate(Matcher::narrow_oop_use_complex_address());
3709 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3710 match(AddP (DecodeN base) offset);
3711 op_cost(1);
3712 format %{ "$offset[[,$base]]" %}
3713 interface(MEMORY_INTER) %{
3714 base($base);
3715 index(0xffffFFFF); // noreg
3716 scale(0x0);
3717 disp($offset);
3718 %}
3719 %}
3720
3721 // Indirect with Register Index
3722 operand indIndex(memoryRegP base, iRegL index) %{
3723 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3724 match(AddP base index);
3725 op_cost(1);
3726 format %{ "#0[($index,$base)]" %}
3727 interface(MEMORY_INTER) %{
3728 base($base);
3729 index($index);
3730 scale(0x0);
3731 disp(0x0);
3732 %}
3733 %}
3734
3735 // Indirect with Offset (long) and index
3736 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3737 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3738 match(AddP (AddP base index) offset);
3739 op_cost(1);
3740 format %{ "$offset[($index,$base)]" %}
3741 interface(MEMORY_INTER) %{
3742 base($base);
3743 index($index);
3744 scale(0x0);
3745 disp($offset);
3746 %}
3747 %}
3748
3749 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3750 predicate(Matcher::narrow_oop_use_complex_address());
3751 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3752 match(AddP (AddP (DecodeN base) index) offset);
3753 op_cost(1);
3754 format %{ "$offset[($index,$base)]" %}
3755 interface(MEMORY_INTER) %{
3756 base($base);
3757 index($index);
3758 scale(0x0);
3759 disp($offset);
3760 %}
3761 %}
3762
3763 // Indirect with Offset (short) and index
3764 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3765 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3766 match(AddP (AddP base index) offset);
3767 op_cost(1);
3768 format %{ "$offset[[($index,$base)]]" %}
3769 interface(MEMORY_INTER) %{
3770 base($base);
3771 index($index);
3772 scale(0x0);
3773 disp($offset);
3774 %}
3775 %}
3776
3777 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3778 predicate(Matcher::narrow_oop_use_complex_address());
3779 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3780 match(AddP (AddP (DecodeN base) index) offset);
3781 op_cost(1);
3782 format %{ "$offset[[($index,$base)]]" %}
3783 interface(MEMORY_INTER) %{
3784 base($base);
3785 index($index);
3786 scale(0x0);
3787 disp($offset);
3788 %}
3789 %}
3790
3791 //----------Special Memory Operands--------------------------------------------
3792
3793 // Stack Slot Operand
3794 // This operand is used for loading and storing temporary values on
3795 // the stack where a match requires a value to flow through memory.
3796 operand stackSlotI(sRegI reg) %{
3797 constraint(ALLOC_IN_RC(stack_slots));
3798 op_cost(1);
3799 format %{ "[$reg(stackSlotI)]" %}
3800 interface(MEMORY_INTER) %{
3801 base(0xf); // Z_SP
3802 index(0xffffFFFF); // noreg
3803 scale(0x0);
3804 disp($reg); // stack offset
3805 %}
3806 %}
3807
3808 operand stackSlotP(sRegP reg) %{
3809 constraint(ALLOC_IN_RC(stack_slots));
3810 op_cost(1);
3811 format %{ "[$reg(stackSlotP)]" %}
3812 interface(MEMORY_INTER) %{
3813 base(0xf); // Z_SP
3814 index(0xffffFFFF); // noreg
3815 scale(0x0);
3816 disp($reg); // Stack Offset
3817 %}
3818 %}
3819
3820 operand stackSlotF(sRegF reg) %{
3821 constraint(ALLOC_IN_RC(stack_slots));
3822 op_cost(1);
3823 format %{ "[$reg(stackSlotF)]" %}
3824 interface(MEMORY_INTER) %{
3825 base(0xf); // Z_SP
3826 index(0xffffFFFF); // noreg
3827 scale(0x0);
3828 disp($reg); // Stack Offset
3829 %}
3830 %}
3831
3832 operand stackSlotD(sRegD reg) %{
3833 constraint(ALLOC_IN_RC(stack_slots));
3834 op_cost(1);
3835 //match(RegD);
3836 format %{ "[$reg(stackSlotD)]" %}
3837 interface(MEMORY_INTER) %{
3838 base(0xf); // Z_SP
3839 index(0xffffFFFF); // noreg
3840 scale(0x0);
3841 disp($reg); // Stack Offset
3842 %}
3843 %}
3844
3845 operand stackSlotL(sRegL reg) %{
3846 constraint(ALLOC_IN_RC(stack_slots));
3847 op_cost(1); //match(RegL);
3848 format %{ "[$reg(stackSlotL)]" %}
3849 interface(MEMORY_INTER) %{
3850 base(0xf); // Z_SP
3851 index(0xffffFFFF); // noreg
3852 scale(0x0);
3853 disp($reg); // Stack Offset
3854 %}
3855 %}
3856
3857 // Operands for expressing Control Flow
3858 // NOTE: Label is a predefined operand which should not be redefined in
3859 // the AD file. It is generically handled within the ADLC.
3860
3861 //----------Conditional Branch Operands----------------------------------------
3862 // Comparison Op - This is the operation of the comparison, and is limited to
3863 // the following set of codes:
3864 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3865 //
3866 // Other attributes of the comparison, such as unsignedness, are specified
3867 // by the comparison instruction that sets a condition code flags register.
3868 // That result is represented by a flags operand whose subtype is appropriate
3869 // to the unsignedness (etc.) of the comparison.
3870 //
3871 // Later, the instruction which matches both the Comparison Op (a Bool) and
3872 // the flags (produced by the Cmp) specifies the coding of the comparison op
3873 // by matching a specific subtype of Bool operand below.
3874
3875 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3876 // have mask bit #3 set.
3877 operand cmpOpT() %{
3878 match(Bool);
3879 format %{ "" %}
3880 interface(COND_INTER) %{
3881 equal(0x8); // Assembler::bcondEqual
3882 not_equal(0x6); // Assembler::bcondNotEqual
3883 less(0x4); // Assembler::bcondLow
3884 greater_equal(0xa); // Assembler::bcondNotLow
3885 less_equal(0xc); // Assembler::bcondNotHigh
3886 greater(0x2); // Assembler::bcondHigh
3887 overflow(0x1); // Assembler::bcondOverflow
3888 no_overflow(0xe); // Assembler::bcondNotOverflow
3889 %}
3890 %}
3891
3892 // When used for floating point comparisons: unordered is treated as less.
3893 operand cmpOpF() %{
3894 match(Bool);
3895 format %{ "" %}
3896 interface(COND_INTER) %{
3897 equal(0x8);
3898 not_equal(0x7); // Includes 'unordered'.
3899 less(0x5); // Includes 'unordered'.
3900 greater_equal(0xa);
3901 less_equal(0xd); // Includes 'unordered'.
3902 greater(0x2);
3903 overflow(0x0); // Not meaningful on z/Architecture.
3904 no_overflow(0x0); // leave unchanged (zero) therefore
3905 %}
3906 %}
3907
3908 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3909 operand cmpOp() %{
3910 match(Bool);
3911 format %{ "" %}
3912 interface(COND_INTER) %{
3913 equal(0x8);
3914 not_equal(0x7); // Includes 'unordered'.
3915 less(0x5); // Includes 'unordered'.
3916 greater_equal(0xa);
3917 less_equal(0xd); // Includes 'unordered'.
3918 greater(0x2);
3919 overflow(0x1); // Assembler::bcondOverflow
3920 no_overflow(0xe); // Assembler::bcondNotOverflow
3921 %}
3922 %}
3923
3924 //----------OPERAND CLASSES----------------------------------------------------
3925 // Operand Classes are groups of operands that are used to simplify
3926 // instruction definitions by not requiring the AD writer to specify
3927 // separate instructions for every form of operand when the
3928 // instruction accepts multiple operand types with the same basic
3929 // encoding and format. The classic case of this is memory operands.
3930 // Indirect is not included since its use is limited to Compare & Swap
3931
3932 // Most general memory operand, allows base, index, and long displacement.
3933 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3934 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3935
3936 // General memory operand, allows base, index, and short displacement.
3937 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3938
3939 // Memory operand, allows only base and long displacement.
3940 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3941
3942 // Memory operand, allows only base and short displacement.
3943 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3944
3945 // Operand classes to match encode and decode.
3946 opclass iRegN_P2N(iRegN);
3947 opclass iRegP_N2P(iRegP);
3948
3949
3950 //----------PIPELINE-----------------------------------------------------------
3951 pipeline %{
3952
3953 //----------ATTRIBUTES---------------------------------------------------------
3954 attributes %{
3955 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3956 variable_size_instructions;
3957 instruction_unit_size = 2;
3958
3959 // Meaningless on z/Architecture.
3960 max_instructions_per_bundle = 1;
3961
3962 // The z/Architecture processor fetches 64 bytes...
3963 instruction_fetch_unit_size = 64;
3964
3965 // ...in one line.
3966 instruction_fetch_units = 1
3967 %}
3968
3969 //----------RESOURCES----------------------------------------------------------
3970 // Resources are the functional units available to the machine.
3971 resources(
3972 Z_BR, // branch unit
3973 Z_CR, // condition unit
3974 Z_FX1, // integer arithmetic unit 1
3975 Z_FX2, // integer arithmetic unit 2
3976 Z_LDST1, // load/store unit 1
3977 Z_LDST2, // load/store unit 2
3978 Z_FP1, // float arithmetic unit 1
3979 Z_FP2, // float arithmetic unit 2
3980 Z_LDST = Z_LDST1 | Z_LDST2,
3981 Z_FX = Z_FX1 | Z_FX2,
3982 Z_FP = Z_FP1 | Z_FP2
3983 );
3984
3985 //----------PIPELINE DESCRIPTION-----------------------------------------------
3986 // Pipeline Description specifies the stages in the machine's pipeline.
3987 pipe_desc(
3988 // TODO: adapt
3989 Z_IF, // instruction fetch
3990 Z_IC,
3991 Z_D0, // decode
3992 Z_D1, // decode
3993 Z_D2, // decode
3994 Z_D3, // decode
3995 Z_Xfer1,
3996 Z_GD, // group definition
3997 Z_MP, // map
3998 Z_ISS, // issue
3999 Z_RF, // resource fetch
4000 Z_EX1, // execute (all units)
4001 Z_EX2, // execute (FP, LDST)
4002 Z_EX3, // execute (FP, LDST)
4003 Z_EX4, // execute (FP)
4004 Z_EX5, // execute (FP)
4005 Z_EX6, // execute (FP)
4006 Z_WB, // write back
4007 Z_Xfer2,
4008 Z_CP
4009 );
4010
4011 //----------PIPELINE CLASSES---------------------------------------------------
4012 // Pipeline Classes describe the stages in which input and output are
4013 // referenced by the hardware pipeline.
4014
4015 // Providing the `ins_pipe' declarations in the instruction
4016 // specifications seems to be of little use. So we use
4017 // `pipe_class_dummy' for all our instructions at present.
4018 pipe_class pipe_class_dummy() %{
4019 single_instruction;
4020 fixed_latency(4);
4021 %}
4022
4023 // SIGTRAP based implicit range checks in compiled code.
4024 // Currently, no pipe classes are used on z/Architecture.
4025 pipe_class pipe_class_trap() %{
4026 single_instruction;
4027 %}
4028
4029 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4030 single_instruction;
4031 dst : Z_EX1(write);
4032 src1 : Z_RF(read);
4033 src2 : Z_RF(read);
4034 Z_FX : Z_RF;
4035 %}
4036
4037 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
4038 single_instruction;
4039 mem : Z_RF(read);
4040 dst : Z_WB(write);
4041 Z_LDST : Z_RF;
4042 %}
4043
4044 define %{
4045 MachNop = pipe_class_dummy;
4046 %}
4047
4048 %}
4049
4050 //----------INSTRUCTIONS-------------------------------------------------------
4051
4052 //---------- Chain stack slots between similar types --------
4053
4054 // Load integer from stack slot.
4055 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
4056 match(Set dst src);
4057 ins_cost(MEMORY_REF_COST);
4058 // TODO: s390 port size(FIXED_SIZE);
4059 format %{ "L $dst,$src\t # stk reload int" %}
4060 opcode(L_ZOPC);
4061 ins_encode(z_form_rt_mem(dst, src));
4062 ins_pipe(pipe_class_dummy);
4063 %}
4064
4065 // Store integer to stack slot.
4066 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
4067 match(Set dst src);
4068 ins_cost(MEMORY_REF_COST);
4069 // TODO: s390 port size(FIXED_SIZE);
4070 format %{ "ST $src,$dst\t # stk spill int" %}
4071 opcode(ST_ZOPC);
4072 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4073 ins_pipe(pipe_class_dummy);
4074 %}
4075
4076 // Load long from stack slot.
4077 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
4078 match(Set dst src);
4079 ins_cost(MEMORY_REF_COST);
4080 // TODO: s390 port size(FIXED_SIZE);
4081 format %{ "LG $dst,$src\t # stk reload long" %}
4082 opcode(LG_ZOPC);
4083 ins_encode(z_form_rt_mem(dst, src));
4084 ins_pipe(pipe_class_dummy);
4085 %}
4086
4087 // Store long to stack slot.
4088 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
4089 match(Set dst src);
4090 ins_cost(MEMORY_REF_COST);
4091 size(6);
4092 format %{ "STG $src,$dst\t # stk spill long" %}
4093 opcode(STG_ZOPC);
4094 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4095 ins_pipe(pipe_class_dummy);
4096 %}
4097
4098 // Load pointer from stack slot, 64-bit encoding.
4099 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
4100 match(Set dst src);
4101 ins_cost(MEMORY_REF_COST);
4102 // TODO: s390 port size(FIXED_SIZE);
4103 format %{ "LG $dst,$src\t # stk reload ptr" %}
4104 opcode(LG_ZOPC);
4105 ins_encode(z_form_rt_mem(dst, src));
4106 ins_pipe(pipe_class_dummy);
4107 %}
4108
4109 // Store pointer to stack slot.
4110 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
4111 match(Set dst src);
4112 ins_cost(MEMORY_REF_COST);
4113 // TODO: s390 port size(FIXED_SIZE);
4114 format %{ "STG $src,$dst\t # stk spill ptr" %}
4115 opcode(STG_ZOPC);
4116 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4117 ins_pipe(pipe_class_dummy);
4118 %}
4119
4120 // Float types
4121
4122 // Load float value from stack slot.
4123 instruct stkF_to_regF(regF dst, stackSlotF src) %{
4124 match(Set dst src);
4125 ins_cost(MEMORY_REF_COST);
4126 size(4);
4127 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
4128 opcode(LE_ZOPC);
4129 ins_encode(z_form_rt_mem(dst, src));
4130 ins_pipe(pipe_class_dummy);
4131 %}
4132
4133 // Store float value to stack slot.
4134 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4135 match(Set dst src);
4136 ins_cost(MEMORY_REF_COST);
4137 size(4);
4138 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4139 opcode(STE_ZOPC);
4140 ins_encode(z_form_rt_mem(src, dst));
4141 ins_pipe(pipe_class_dummy);
4142 %}
4143
4144 // Load double value from stack slot.
4145 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4146 match(Set dst src);
4147 ins_cost(MEMORY_REF_COST);
4148 // TODO: s390 port size(FIXED_SIZE);
4149 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4150 opcode(LD_ZOPC);
4151 ins_encode(z_form_rt_mem(dst, src));
4152 ins_pipe(pipe_class_dummy);
4153 %}
4154
4155 // Store double value to stack slot.
4156 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4157 match(Set dst src);
4158 ins_cost(MEMORY_REF_COST);
4159 size(4);
4160 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4161 opcode(STD_ZOPC);
4162 ins_encode(z_form_rt_mem(src, dst));
4163 ins_pipe(pipe_class_dummy);
4164 %}
4165
4166 //----------Load/Store/Move Instructions---------------------------------------
4167
4168 //----------Load Instructions--------------------------------------------------
4169
4170 //------------------
4171 // MEMORY
4172 //------------------
4173
4174 // BYTE
4175 // Load Byte (8bit signed)
4176 instruct loadB(iRegI dst, memory mem) %{
4177 match(Set dst (LoadB mem));
4178 ins_cost(MEMORY_REF_COST);
4179 size(Z_DISP3_SIZE);
4180 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4181 opcode(LB_ZOPC, LB_ZOPC);
4182 ins_encode(z_form_rt_mem_opt(dst, mem));
4183 ins_pipe(pipe_class_dummy);
4184 %}
4185
4186 // Load Byte (8bit signed)
4187 instruct loadB2L(iRegL dst, memory mem) %{
4188 match(Set dst (ConvI2L (LoadB mem)));
4189 ins_cost(MEMORY_REF_COST);
4190 size(Z_DISP3_SIZE);
4191 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4192 opcode(LGB_ZOPC, LGB_ZOPC);
4193 ins_encode(z_form_rt_mem_opt(dst, mem));
4194 ins_pipe(pipe_class_dummy);
4195 %}
4196
4197 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4198 instruct loadUB(iRegI dst, memory mem) %{
4199 match(Set dst (LoadUB mem));
4200 ins_cost(MEMORY_REF_COST);
4201 size(Z_DISP3_SIZE);
4202 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4203 opcode(LLGC_ZOPC, LLGC_ZOPC);
4204 ins_encode(z_form_rt_mem_opt(dst, mem));
4205 ins_pipe(pipe_class_dummy);
4206 %}
4207
4208 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4209 instruct loadUB2L(iRegL dst, memory mem) %{
4210 match(Set dst (ConvI2L (LoadUB mem)));
4211 ins_cost(MEMORY_REF_COST);
4212 size(Z_DISP3_SIZE);
4213 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4214 opcode(LLGC_ZOPC, LLGC_ZOPC);
4215 ins_encode(z_form_rt_mem_opt(dst, mem));
4216 ins_pipe(pipe_class_dummy);
4217 %}
4218
4219 // CHAR/SHORT
4220
4221 // Load Short (16bit signed)
4222 instruct loadS(iRegI dst, memory mem) %{
4223 match(Set dst (LoadS mem));
4224 ins_cost(MEMORY_REF_COST);
4225 size(Z_DISP_SIZE);
4226 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4227 opcode(LHY_ZOPC, LH_ZOPC);
4228 ins_encode(z_form_rt_mem_opt(dst, mem));
4229 ins_pipe(pipe_class_dummy);
4230 %}
4231
4232 // Load Short (16bit signed)
4233 instruct loadS2L(iRegL dst, memory mem) %{
4234 match(Set dst (ConvI2L (LoadS mem)));
4235 ins_cost(MEMORY_REF_COST);
4236 size(Z_DISP3_SIZE);
4237 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4238 opcode(LGH_ZOPC, LGH_ZOPC);
4239 ins_encode(z_form_rt_mem_opt(dst, mem));
4240 ins_pipe(pipe_class_dummy);
4241 %}
4242
4243 // Load Char (16bit Unsigned)
4244 instruct loadUS(iRegI dst, memory mem) %{
4245 match(Set dst (LoadUS mem));
4246 ins_cost(MEMORY_REF_COST);
4247 size(Z_DISP3_SIZE);
4248 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4249 opcode(LLGH_ZOPC, LLGH_ZOPC);
4250 ins_encode(z_form_rt_mem_opt(dst, mem));
4251 ins_pipe(pipe_class_dummy);
4252 %}
4253
4254 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4255 instruct loadUS2L(iRegL dst, memory mem) %{
4256 match(Set dst (ConvI2L (LoadUS mem)));
4257 ins_cost(MEMORY_REF_COST);
4258 size(Z_DISP3_SIZE);
4259 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4260 opcode(LLGH_ZOPC, LLGH_ZOPC);
4261 ins_encode(z_form_rt_mem_opt(dst, mem));
4262 ins_pipe(pipe_class_dummy);
4263 %}
4264
4265 // INT
4266
4267 // Load Integer
4268 instruct loadI(iRegI dst, memory mem) %{
4269 match(Set dst (LoadI mem));
4270 ins_cost(MEMORY_REF_COST);
4271 size(Z_DISP_SIZE);
4272 format %{ "L(Y) $dst,$mem\t #" %}
4273 opcode(LY_ZOPC, L_ZOPC);
4274 ins_encode(z_form_rt_mem_opt(dst, mem));
4275 ins_pipe(pipe_class_dummy);
4276 %}
4277
4278 // Load and convert to long.
4279 instruct loadI2L(iRegL dst, memory mem) %{
4280 match(Set dst (ConvI2L (LoadI mem)));
4281 ins_cost(MEMORY_REF_COST);
4282 size(Z_DISP3_SIZE);
4283 format %{ "LGF $dst,$mem\t #" %}
4284 opcode(LGF_ZOPC, LGF_ZOPC);
4285 ins_encode(z_form_rt_mem_opt(dst, mem));
4286 ins_pipe(pipe_class_dummy);
4287 %}
4288
4289 // Load Unsigned Integer into a Long Register
4290 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4291 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4292 ins_cost(MEMORY_REF_COST);
4293 size(Z_DISP3_SIZE);
4294 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4295 opcode(LLGF_ZOPC, LLGF_ZOPC);
4296 ins_encode(z_form_rt_mem_opt(dst, mem));
4297 ins_pipe(pipe_class_dummy);
4298 %}
4299
4300 // range = array length (=jint)
4301 // Load Range
4302 instruct loadRange(iRegI dst, memory mem) %{
4303 match(Set dst (LoadRange mem));
4304 ins_cost(MEMORY_REF_COST);
4305 size(Z_DISP_SIZE);
4306 format %{ "L(Y) $dst,$mem\t # range" %}
4307 opcode(LY_ZOPC, L_ZOPC);
4308 ins_encode(z_form_rt_mem_opt(dst, mem));
4309 ins_pipe(pipe_class_dummy);
4310 %}
4311
4312 // LONG
4313
4314 // Load Long - aligned
4315 instruct loadL(iRegL dst, memory mem) %{
4316 match(Set dst (LoadL mem));
4317 ins_cost(MEMORY_REF_COST);
4318 size(Z_DISP3_SIZE);
4319 format %{ "LG $dst,$mem\t # long" %}
4320 opcode(LG_ZOPC, LG_ZOPC);
4321 ins_encode(z_form_rt_mem_opt(dst, mem));
4322 ins_pipe(pipe_class_dummy);
4323 %}
4324
4325 // Load Long - UNaligned
4326 instruct loadL_unaligned(iRegL dst, memory mem) %{
4327 match(Set dst (LoadL_unaligned mem));
4328 ins_cost(MEMORY_REF_COST);
4329 size(Z_DISP3_SIZE);
4330 format %{ "LG $dst,$mem\t # unaligned long" %}
4331 opcode(LG_ZOPC, LG_ZOPC);
4332 ins_encode(z_form_rt_mem_opt(dst, mem));
4333 ins_pipe(pipe_class_dummy);
4334 %}
4335
4336
4337 // PTR
4338
4339 // Load Pointer
4340 instruct loadP(iRegP dst, memory mem) %{
4341 match(Set dst (LoadP mem));
4342 predicate(n->as_Load()->barrier_data() == 0);
4343 ins_cost(MEMORY_REF_COST);
4344 size(Z_DISP3_SIZE);
4345 format %{ "LG $dst,$mem\t # ptr" %}
4346 opcode(LG_ZOPC, LG_ZOPC);
4347 ins_encode(z_form_rt_mem_opt(dst, mem));
4348 ins_pipe(pipe_class_dummy);
4349 %}
4350
4351 // LoadP + CastP2L
4352 instruct castP2X_loadP(iRegL dst, memory mem) %{
4353 match(Set dst (CastP2X (LoadP mem)));
4354 predicate(n->as_Load()->barrier_data() == 0);
4355 ins_cost(MEMORY_REF_COST);
4356 size(Z_DISP3_SIZE);
4357 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4358 opcode(LG_ZOPC, LG_ZOPC);
4359 ins_encode(z_form_rt_mem_opt(dst, mem));
4360 ins_pipe(pipe_class_dummy);
4361 %}
4362
4363 // Load Klass Pointer
4364 instruct loadKlass(iRegP dst, memory mem) %{
4365 match(Set dst (LoadKlass mem));
4366 ins_cost(MEMORY_REF_COST);
4367 size(Z_DISP3_SIZE);
4368 format %{ "LG $dst,$mem\t # klass ptr" %}
4369 opcode(LG_ZOPC, LG_ZOPC);
4370 ins_encode(z_form_rt_mem_opt(dst, mem));
4371 ins_pipe(pipe_class_dummy);
4372 %}
4373
4374 instruct loadTOC(iRegL dst) %{
4375 effect(DEF dst);
4376 ins_cost(DEFAULT_COST);
4377 // TODO: s390 port size(FIXED_SIZE);
4378 // TODO: check why this attribute causes many unnecessary rematerializations.
4379 //
4380 // The graphs I saw just had high register pressure. Further the
4381 // register TOC is loaded to is overwritten by the constant short
4382 // after. Here something as round robin register allocation might
4383 // help. But rematerializing seems not to hurt, jack even seems to
4384 // improve slightly.
4385 //
4386 // Without this flag we get spill-split recycle sanity check
4387 // failures in
4388 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4389 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4390 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4391 // stack. Later tlsLoadP is rematerialized, leaving the register
4392 // allocator with TOC on the stack and a badly placed reload.
4393 ins_should_rematerialize(true);
4394 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4395 ins_encode %{ __ load_toc($dst$$Register); %}
4396 ins_pipe(pipe_class_dummy);
4397 %}
4398
4399 // FLOAT
4400
4401 // Load Float
4402 instruct loadF(regF dst, memory mem) %{
4403 match(Set dst (LoadF mem));
4404 ins_cost(MEMORY_REF_COST);
4405 size(Z_DISP_SIZE);
4406 format %{ "LE(Y) $dst,$mem" %}
4407 opcode(LEY_ZOPC, LE_ZOPC);
4408 ins_encode(z_form_rt_mem_opt(dst, mem));
4409 ins_pipe(pipe_class_dummy);
4410 %}
4411
4412 // DOUBLE
4413
4414 // Load Double
4415 instruct loadD(regD dst, memory mem) %{
4416 match(Set dst (LoadD mem));
4417 ins_cost(MEMORY_REF_COST);
4418 size(Z_DISP_SIZE);
4419 format %{ "LD(Y) $dst,$mem" %}
4420 opcode(LDY_ZOPC, LD_ZOPC);
4421 ins_encode(z_form_rt_mem_opt(dst, mem));
4422 ins_pipe(pipe_class_dummy);
4423 %}
4424
4425 // Load Double - UNaligned
4426 instruct loadD_unaligned(regD dst, memory mem) %{
4427 match(Set dst (LoadD_unaligned mem));
4428 ins_cost(MEMORY_REF_COST);
4429 size(Z_DISP_SIZE);
4430 format %{ "LD(Y) $dst,$mem" %}
4431 opcode(LDY_ZOPC, LD_ZOPC);
4432 ins_encode(z_form_rt_mem_opt(dst, mem));
4433 ins_pipe(pipe_class_dummy);
4434 %}
4435
4436
4437 //----------------------
4438 // IMMEDIATES
4439 //----------------------
4440
4441 instruct loadConI(iRegI dst, immI src) %{
4442 match(Set dst src);
4443 ins_cost(DEFAULT_COST);
4444 size(6);
4445 format %{ "LGFI $dst,$src\t # (int)" %}
4446 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4447 ins_pipe(pipe_class_dummy);
4448 %}
4449
4450 instruct loadConI16(iRegI dst, immI16 src) %{
4451 match(Set dst src);
4452 ins_cost(DEFAULT_COST_LOW);
4453 size(4);
4454 format %{ "LGHI $dst,$src\t # (int)" %}
4455 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4456 ins_pipe(pipe_class_dummy);
4457 %}
4458
4459 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4460 match(Set dst src);
4461 effect(KILL cr);
4462 ins_cost(DEFAULT_COST_LOW);
4463 size(4);
4464 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4465 opcode(XGR_ZOPC);
4466 ins_encode(z_rreform(dst, dst));
4467 ins_pipe(pipe_class_dummy);
4468 %}
4469
4470 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4471 match(Set dst src);
4472 // TODO: s390 port size(FIXED_SIZE);
4473 format %{ "LLILL $dst,$src" %}
4474 opcode(LLILL_ZOPC);
4475 ins_encode(z_riform_unsigned(dst, src) );
4476 ins_pipe(pipe_class_dummy);
4477 %}
4478
4479 // Load long constant from TOC with pcrelative address.
4480 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4481 match(Set dst src);
4482 ins_cost(MEMORY_REF_COST_LO);
4483 size(6);
4484 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4485 ins_encode %{
4486 address long_address = __ long_constant($src$$constant);
4487 if (long_address == nullptr) {
4488 Compile::current()->env()->record_out_of_memory_failure();
4489 return;
4490 }
4491 __ load_long_pcrelative($dst$$Register, long_address);
4492 %}
4493 ins_pipe(pipe_class_dummy);
4494 %}
4495
4496 instruct loadConL32(iRegL dst, immL32 src) %{
4497 match(Set dst src);
4498 ins_cost(DEFAULT_COST);
4499 size(6);
4500 format %{ "LGFI $dst,$src\t # (long)" %}
4501 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4502 ins_pipe(pipe_class_dummy);
4503 %}
4504
4505 instruct loadConL16(iRegL dst, immL16 src) %{
4506 match(Set dst src);
4507 ins_cost(DEFAULT_COST_LOW);
4508 size(4);
4509 format %{ "LGHI $dst,$src\t # (long)" %}
4510 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4511 ins_pipe(pipe_class_dummy);
4512 %}
4513
4514 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4515 match(Set dst src);
4516 effect(KILL cr);
4517 ins_cost(DEFAULT_COST_LOW);
4518 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4519 opcode(XGR_ZOPC);
4520 ins_encode(z_rreform(dst, dst));
4521 ins_pipe(pipe_class_dummy);
4522 %}
4523
4524 // Load ptr constant from TOC with pc relative address.
4525 // Special handling for oop constants required.
4526 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4527 match(Set dst src);
4528 ins_cost(MEMORY_REF_COST_LO);
4529 size(6);
4530 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4531 ins_encode %{
4532 relocInfo::relocType constant_reloc = $src->constant_reloc();
4533 if (constant_reloc == relocInfo::oop_type) {
4534 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4535 bool success = __ load_oop_from_toc($dst$$Register, a);
4536 if (!success) {
4537 Compile::current()->env()->record_out_of_memory_failure();
4538 return;
4539 }
4540 } else if (constant_reloc == relocInfo::metadata_type) {
4541 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4542 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4543 if (const_toc_addr == nullptr) {
4544 Compile::current()->env()->record_out_of_memory_failure();
4545 return;
4546 }
4547 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4548 } else { // Non-oop pointers, e.g. card mark base, heap top.
4549 address long_address = __ long_constant((jlong)$src$$constant);
4550 if (long_address == nullptr) {
4551 Compile::current()->env()->record_out_of_memory_failure();
4552 return;
4553 }
4554 __ load_long_pcrelative($dst$$Register, long_address);
4555 }
4556 %}
4557 ins_pipe(pipe_class_dummy);
4558 %}
4559
4560 // We don't use immP16 to avoid problems with oops.
4561 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4562 match(Set dst src);
4563 effect(KILL cr);
4564 size(4);
4565 format %{ "XGR $dst,$dst\t # null pointer" %}
4566 opcode(XGR_ZOPC);
4567 ins_encode(z_rreform(dst, dst));
4568 ins_pipe(pipe_class_dummy);
4569 %}
4570
4571 //----------Load Float Constant Instructions-------------------------------------------------
4572
4573 // We may not specify this instruction via an `expand' rule. If we do,
4574 // code selection will forget that this instruction needs a floating
4575 // point constant inserted into the code buffer. So `Shorten_branches'
4576 // will fail.
4577 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4578 match(Set dst src);
4579 effect(KILL cr);
4580 ins_cost(MEMORY_REF_COST);
4581 size(6);
4582 // If this instruction rematerializes, it prolongs the live range
4583 // of the toc node, causing illegal graphs.
4584 ins_cannot_rematerialize(true);
4585 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4586 ins_encode %{
4587 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4588 %}
4589 ins_pipe(pipe_class_dummy);
4590 %}
4591
4592 // E may not specify this instruction via an `expand' rule. If we do,
4593 // code selection will forget that this instruction needs a floating
4594 // point constant inserted into the code buffer. So `Shorten_branches'
4595 // will fail.
4596 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4597 match(Set dst src);
4598 effect(KILL cr);
4599 ins_cost(MEMORY_REF_COST);
4600 size(6);
4601 // If this instruction rematerializes, it prolongs the live range
4602 // of the toc node, causing illegal graphs.
4603 ins_cannot_rematerialize(true);
4604 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4605 ins_encode %{
4606 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4607 %}
4608 ins_pipe(pipe_class_dummy);
4609 %}
4610
4611 // Special case: Load Const 0.0F
4612
4613 // There's a special instr to clear a FP register.
4614 instruct loadConF0(regF dst, immFp0 src) %{
4615 match(Set dst src);
4616 ins_cost(DEFAULT_COST_LOW);
4617 size(4);
4618 format %{ "LZER $dst,$src\t # clear to zero" %}
4619 opcode(LZER_ZOPC);
4620 ins_encode(z_rreform(dst, Z_F0));
4621 ins_pipe(pipe_class_dummy);
4622 %}
4623
4624 // There's a special instr to clear a FP register.
4625 instruct loadConD0(regD dst, immDp0 src) %{
4626 match(Set dst src);
4627 ins_cost(DEFAULT_COST_LOW);
4628 size(4);
4629 format %{ "LZDR $dst,$src\t # clear to zero" %}
4630 opcode(LZDR_ZOPC);
4631 ins_encode(z_rreform(dst, Z_F0));
4632 ins_pipe(pipe_class_dummy);
4633 %}
4634
4635
4636 //----------Store Instructions-------------------------------------------------
4637
4638 // BYTE
4639
4640 // Store Byte
4641 instruct storeB(memory mem, iRegI src) %{
4642 match(Set mem (StoreB mem src));
4643 ins_cost(MEMORY_REF_COST);
4644 size(Z_DISP_SIZE);
4645 format %{ "STC(Y) $src,$mem\t # byte" %}
4646 opcode(STCY_ZOPC, STC_ZOPC);
4647 ins_encode(z_form_rt_mem_opt(src, mem));
4648 ins_pipe(pipe_class_dummy);
4649 %}
4650
4651 // CHAR/SHORT
4652
4653 // Store Char/Short
4654 instruct storeC(memory mem, iRegI src) %{
4655 match(Set mem (StoreC mem src));
4656 ins_cost(MEMORY_REF_COST);
4657 size(Z_DISP_SIZE);
4658 format %{ "STH(Y) $src,$mem\t # short" %}
4659 opcode(STHY_ZOPC, STH_ZOPC);
4660 ins_encode(z_form_rt_mem_opt(src, mem));
4661 ins_pipe(pipe_class_dummy);
4662 %}
4663
4664 // INT
4665
4666 // Store Integer
4667 instruct storeI(memory mem, iRegI src) %{
4668 match(Set mem (StoreI mem src));
4669 ins_cost(MEMORY_REF_COST);
4670 size(Z_DISP_SIZE);
4671 format %{ "ST(Y) $src,$mem\t # int" %}
4672 opcode(STY_ZOPC, ST_ZOPC);
4673 ins_encode(z_form_rt_mem_opt(src, mem));
4674 ins_pipe(pipe_class_dummy);
4675 %}
4676
4677 // LONG
4678
4679 // Store Long
4680 instruct storeL(memory mem, iRegL src) %{
4681 match(Set mem (StoreL mem src));
4682 ins_cost(MEMORY_REF_COST);
4683 size(Z_DISP3_SIZE);
4684 format %{ "STG $src,$mem\t # long" %}
4685 opcode(STG_ZOPC, STG_ZOPC);
4686 ins_encode(z_form_rt_mem_opt(src, mem));
4687 ins_pipe(pipe_class_dummy);
4688 %}
4689
4690 // PTR
4691
4692 // Store Pointer
4693 instruct storeP(memory dst, memoryRegP src) %{
4694 match(Set dst (StoreP dst src));
4695 predicate(n->as_Store()->barrier_data() == 0);
4696 ins_cost(MEMORY_REF_COST);
4697 size(Z_DISP3_SIZE);
4698 format %{ "STG $src,$dst\t # ptr" %}
4699 opcode(STG_ZOPC, STG_ZOPC);
4700 ins_encode(z_form_rt_mem_opt(src, dst));
4701 ins_pipe(pipe_class_dummy);
4702 %}
4703
4704 // FLOAT
4705
4706 // Store Float
4707 instruct storeF(memory mem, regF src) %{
4708 match(Set mem (StoreF mem src));
4709 ins_cost(MEMORY_REF_COST);
4710 size(Z_DISP_SIZE);
4711 format %{ "STE(Y) $src,$mem\t # float" %}
4712 opcode(STEY_ZOPC, STE_ZOPC);
4713 ins_encode(z_form_rt_mem_opt(src, mem));
4714 ins_pipe(pipe_class_dummy);
4715 %}
4716
4717 // DOUBLE
4718
4719 // Store Double
4720 instruct storeD(memory mem, regD src) %{
4721 match(Set mem (StoreD mem src));
4722 ins_cost(MEMORY_REF_COST);
4723 size(Z_DISP_SIZE);
4724 format %{ "STD(Y) $src,$mem\t # double" %}
4725 opcode(STDY_ZOPC, STD_ZOPC);
4726 ins_encode(z_form_rt_mem_opt(src, mem));
4727 ins_pipe(pipe_class_dummy);
4728 %}
4729
4730 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4731
4732 // Should support match rule for PrefetchAllocation.
4733 // Still needed after 8068977 for PrefetchAllocate.
4734 instruct prefetchAlloc(memory mem) %{
4735 match(PrefetchAllocation mem);
4736 predicate(VM_Version::has_Prefetch());
4737 ins_cost(DEFAULT_COST);
4738 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4739 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4740 ins_pipe(pipe_class_dummy);
4741 %}
4742
4743 //----------Memory init instructions------------------------------------------
4744
4745 // Move Immediate to 1-byte memory.
4746 instruct memInitB(memoryRSY mem, immI8 src) %{
4747 match(Set mem (StoreB mem src));
4748 ins_cost(MEMORY_REF_COST);
4749 // TODO: s390 port size(VARIABLE_SIZE);
4750 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4751 ins_encode %{
4752 if (Immediate::is_uimm12((long)$mem$$disp)) {
4753 __ z_mvi($mem$$Address, $src$$constant);
4754 } else {
4755 __ z_mviy($mem$$Address, $src$$constant);
4756 }
4757 %}
4758 ins_pipe(pipe_class_dummy);
4759 %}
4760
4761 // Move Immediate to 2-byte memory.
4762 instruct memInitC(memoryRS mem, immI16 src) %{
4763 match(Set mem (StoreC mem src));
4764 ins_cost(MEMORY_REF_COST);
4765 size(6);
4766 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4767 opcode(MVHHI_ZOPC);
4768 ins_encode(z_silform(mem, src));
4769 ins_pipe(pipe_class_dummy);
4770 %}
4771
4772 // Move Immediate to 4-byte memory.
4773 instruct memInitI(memoryRS mem, immI16 src) %{
4774 match(Set mem (StoreI mem src));
4775 ins_cost(MEMORY_REF_COST);
4776 size(6);
4777 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4778 opcode(MVHI_ZOPC);
4779 ins_encode(z_silform(mem, src));
4780 ins_pipe(pipe_class_dummy);
4781 %}
4782
4783
4784 // Move Immediate to 8-byte memory.
4785 instruct memInitL(memoryRS mem, immL16 src) %{
4786 match(Set mem (StoreL mem src));
4787 ins_cost(MEMORY_REF_COST);
4788 size(6);
4789 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4790 opcode(MVGHI_ZOPC);
4791 ins_encode(z_silform(mem, src));
4792 ins_pipe(pipe_class_dummy);
4793 %}
4794
4795 // Move Immediate to 8-byte memory.
4796 instruct memInitP(memoryRS mem, immP16 src) %{
4797 match(Set mem (StoreP mem src));
4798 predicate(n->as_Store()->barrier_data() == 0);
4799 ins_cost(MEMORY_REF_COST);
4800 size(6);
4801 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4802 opcode(MVGHI_ZOPC);
4803 ins_encode(z_silform(mem, src));
4804 ins_pipe(pipe_class_dummy);
4805 %}
4806
4807
4808 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4809
4810 // See cOop encoding classes for elaborate comment.
4811
4812 // Moved here because it is needed in expand rules for encode.
4813 // Long negation.
4814 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4815 match(Set dst (SubL zero src));
4816 effect(KILL cr);
4817 size(4);
4818 format %{ "NEG $dst, $src\t # long" %}
4819 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4820 ins_pipe(pipe_class_dummy);
4821 %}
4822
4823 // Load Compressed Pointer
4824
4825 // Load narrow oop
4826 instruct loadN(iRegN dst, memory mem) %{
4827 match(Set dst (LoadN mem));
4828 predicate(n->as_Load()->barrier_data() == 0);
4829 ins_cost(MEMORY_REF_COST);
4830 size(Z_DISP3_SIZE);
4831 format %{ "LoadN $dst,$mem\t # (cOop)" %}
4832 opcode(LLGF_ZOPC, LLGF_ZOPC);
4833 ins_encode(z_form_rt_mem_opt(dst, mem));
4834 ins_pipe(pipe_class_dummy);
4835 %}
4836
4837 // Load narrow Klass Pointer
4838 instruct loadNKlass(iRegN dst, memory mem) %{
4839 predicate(!UseCompactObjectHeaders);
4840 match(Set dst (LoadNKlass mem));
4841 ins_cost(MEMORY_REF_COST);
4842 size(Z_DISP3_SIZE);
4843 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
4844 opcode(LLGF_ZOPC, LLGF_ZOPC);
4845 ins_encode(z_form_rt_mem_opt(dst, mem));
4846 ins_pipe(pipe_class_dummy);
4847 %}
4848
4849 instruct loadNKlassCompactHeaders(iRegN dst, memory mem) %{
4850 match(Set dst (LoadNKlass mem));
4851 predicate(UseCompactObjectHeaders);
4852 ins_cost(MEMORY_REF_COST);
4853 format %{ "load_narrow_klass_compact $dst,$mem \t# compressed class ptr" %}
4854 // z_lg (6 bytes) + z_srlg (6 bytes); neither instruction modifies the CC.
4855 size(12);
4856 ins_encode %{
4857 __ load_narrow_klass_compact_c2($dst$$Register, $mem$$Address);
4858 %}
4859 ins_pipe(pipe_class_dummy);
4860 %}
4861
4862 // Load constant Compressed Pointer
4863
4864 instruct loadConN(iRegN dst, immN src) %{
4865 match(Set dst src);
4866 ins_cost(DEFAULT_COST);
4867 size(6);
4868 format %{ "loadConN $dst,$src\t # (cOop)" %}
4869 ins_encode %{
4870 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4871 __ relocate(cOop.rspec(), 1);
4872 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4873 %}
4874 ins_pipe(pipe_class_dummy);
4875 %}
4876
4877 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4878 match(Set dst src);
4879 effect(KILL cr);
4880 ins_cost(DEFAULT_COST_LOW);
4881 size(4);
4882 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4883 opcode(XGR_ZOPC);
4884 ins_encode(z_rreform(dst, dst));
4885 ins_pipe(pipe_class_dummy);
4886 %}
4887
4888 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4889 match(Set dst src);
4890 ins_cost(DEFAULT_COST);
4891 size(6);
4892 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4893 ins_encode %{
4894 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4895 __ relocate(NKlass.rspec(), 1);
4896 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4897 %}
4898 ins_pipe(pipe_class_dummy);
4899 %}
4900
4901 // Load and Decode Compressed Pointer
4902 // optimized variants for Unscaled cOops
4903
4904 instruct decodeLoadN(iRegP dst, memory mem) %{
4905 match(Set dst (DecodeN (LoadN mem)));
4906 predicate(false && (CompressedOops::base()==nullptr) && (CompressedOops::shift()==0));
4907 ins_cost(MEMORY_REF_COST);
4908 size(Z_DISP3_SIZE);
4909 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
4910 opcode(LLGF_ZOPC, LLGF_ZOPC);
4911 ins_encode(z_form_rt_mem_opt(dst, mem));
4912 ins_pipe(pipe_class_dummy);
4913 %}
4914
4915 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4916 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4917 predicate(false && (CompressedKlassPointers::base()==nullptr)&&(CompressedKlassPointers::shift()==0));
4918 ins_cost(MEMORY_REF_COST);
4919 size(Z_DISP3_SIZE);
4920 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
4921 opcode(LLGF_ZOPC, LLGF_ZOPC);
4922 ins_encode(z_form_rt_mem_opt(dst, mem));
4923 ins_pipe(pipe_class_dummy);
4924 %}
4925
4926 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4927 match(Set dst (DecodeNKlass src));
4928 ins_cost(3 * DEFAULT_COST);
4929 size(12);
4930 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4931 ins_encode %{
4932 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4933 __ relocate(NKlass.rspec(), 1);
4934 __ load_const($dst$$Register, (Klass*)NKlass.value());
4935 %}
4936 ins_pipe(pipe_class_dummy);
4937 %}
4938
4939 // Decode Compressed Pointer
4940
4941 // General decoder
4942 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4943 match(Set dst (DecodeN src));
4944 effect(KILL cr);
4945 predicate(CompressedOops::base() == nullptr || !ExpandLoadingBaseDecode);
4946 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4947 // TODO: s390 port size(VARIABLE_SIZE);
4948 format %{ "decodeN $dst,$src\t # (decode cOop)" %}
4949 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4950 ins_pipe(pipe_class_dummy);
4951 %}
4952
4953 // General Klass decoder
4954 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4955 match(Set dst (DecodeNKlass src));
4956 effect(KILL cr);
4957 ins_cost(3 * DEFAULT_COST);
4958 format %{ "decode_klass $dst,$src" %}
4959 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4960 ins_pipe(pipe_class_dummy);
4961 %}
4962
4963 // General decoder
4964 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4965 match(Set dst (DecodeN src));
4966 effect(KILL cr);
4967 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4968 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4969 (CompressedOops::base()== nullptr || !ExpandLoadingBaseDecode_NN));
4970 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4971 // TODO: s390 port size(VARIABLE_SIZE);
4972 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
4973 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4974 ins_pipe(pipe_class_dummy);
4975 %}
4976
4977 instruct loadBase(iRegL dst, immL baseImm) %{
4978 effect(DEF dst, USE baseImm);
4979 predicate(false);
4980 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4981 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4982 ins_pipe(pipe_class_dummy);
4983 %}
4984
4985 // Decoder for heapbased mode peeling off loading the base.
4986 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4987 match(Set dst (DecodeN src base));
4988 // Note: Effect TEMP dst was used with the intention to get
4989 // different regs for dst and base, but this has caused ADLC to
4990 // generate wrong code. Oop_decoder generates additional lgr when
4991 // dst==base.
4992 effect(KILL cr);
4993 predicate(false);
4994 // TODO: s390 port size(VARIABLE_SIZE);
4995 format %{ "decodeN $dst = ($src == 0) ? nullptr : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4996 ins_encode %{
4997 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4998 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4999 %}
5000 ins_pipe(pipe_class_dummy);
5001 %}
5002
5003 // Decoder for heapbased mode peeling off loading the base.
5004 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
5005 match(Set dst (DecodeN src base));
5006 effect(KILL cr);
5007 predicate(false);
5008 // TODO: s390 port size(VARIABLE_SIZE);
5009 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
5010 ins_encode %{
5011 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
5012 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
5013 %}
5014 ins_pipe(pipe_class_dummy);
5015 %}
5016
5017 // Decoder for heapbased mode peeling off loading the base.
5018 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
5019 match(Set dst (DecodeN src));
5020 predicate(CompressedOops::base() != nullptr && ExpandLoadingBaseDecode);
5021 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
5022 // TODO: s390 port size(VARIABLE_SIZE);
5023 expand %{
5024 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5025 iRegL base;
5026 loadBase(base, baseImm);
5027 decodeN_base(dst, src, base, cr);
5028 %}
5029 %}
5030
5031 // Decoder for heapbased mode peeling off loading the base.
5032 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
5033 match(Set dst (DecodeN src));
5034 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
5035 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
5036 CompressedOops::base() != nullptr && ExpandLoadingBaseDecode_NN);
5037 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5038 // TODO: s390 port size(VARIABLE_SIZE);
5039 expand %{
5040 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5041 iRegL base;
5042 loadBase(base, baseImm);
5043 decodeN_NN_base(dst, src, base, cr);
5044 %}
5045 %}
5046
5047 // Encode Compressed Pointer
5048
5049 // General encoder
5050 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
5051 match(Set dst (EncodeP src));
5052 effect(KILL cr);
5053 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5054 (CompressedOops::base() == nullptr ||
5055 CompressedOops::base_disjoint() ||
5056 !ExpandLoadingBaseEncode));
5057 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5058 // TODO: s390 port size(VARIABLE_SIZE);
5059 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5060 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5061 ins_pipe(pipe_class_dummy);
5062 %}
5063
5064 // General class encoder
5065 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
5066 match(Set dst (EncodePKlass src));
5067 effect(KILL cr);
5068 format %{ "encode_klass $dst,$src" %}
5069 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
5070 ins_pipe(pipe_class_dummy);
5071 %}
5072
5073 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
5074 match(Set dst (EncodeP src));
5075 effect(KILL cr);
5076 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5077 (CompressedOops::base() == nullptr ||
5078 CompressedOops::base_disjoint() ||
5079 !ExpandLoadingBaseEncode_NN));
5080 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5081 // TODO: s390 port size(VARIABLE_SIZE);
5082 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5083 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5084 ins_pipe(pipe_class_dummy);
5085 %}
5086
5087 // Encoder for heapbased mode peeling off loading the base.
5088 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
5089 match(Set dst (EncodeP src (Binary base dst)));
5090 effect(TEMP_DEF dst);
5091 predicate(false);
5092 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5093 // TODO: s390 port size(VARIABLE_SIZE);
5094 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
5095 ins_encode %{
5096 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
5097 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
5098 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
5099 %}
5100 ins_pipe(pipe_class_dummy);
5101 %}
5102
5103 // Encoder for heapbased mode peeling off loading the base.
5104 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
5105 match(Set dst (EncodeP src base));
5106 effect(USE pow2_offset);
5107 predicate(false);
5108 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5109 // TODO: s390 port size(VARIABLE_SIZE);
5110 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
5111 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
5112 ins_pipe(pipe_class_dummy);
5113 %}
5114
5115 // Encoder for heapbased mode peeling off loading the base.
5116 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5117 match(Set dst (EncodeP src));
5118 effect(KILL cr);
5119 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5120 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
5121 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5122 // TODO: s390 port size(VARIABLE_SIZE);
5123 expand %{
5124 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
5125 immL_0 zero %{ (0) %}
5126 flagsReg ccr;
5127 iRegL base;
5128 iRegL negBase;
5129 loadBase(base, baseImm);
5130 negL_reg_reg(negBase, zero, base, ccr);
5131 encodeP_base(dst, src, negBase);
5132 %}
5133 %}
5134
5135 // Encoder for heapbased mode peeling off loading the base.
5136 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5137 match(Set dst (EncodeP src));
5138 effect(KILL cr);
5139 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5140 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
5141 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5142 // TODO: s390 port size(VARIABLE_SIZE);
5143 expand %{
5144 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5145 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
5146 immL_0 zero %{ 0 %}
5147 flagsReg ccr;
5148 iRegL base;
5149 iRegL negBase;
5150 loadBase(base, baseImm);
5151 negL_reg_reg(negBase, zero, base, ccr);
5152 encodeP_NN_base(dst, src, negBase, pow2_offset);
5153 %}
5154 %}
5155
5156 // Store Compressed Pointer
5157
5158 // Store Compressed Pointer
5159 instruct storeN(memory mem, iRegN_P2N src) %{
5160 match(Set mem (StoreN mem src));
5161 predicate(n->as_Store()->barrier_data() == 0);
5162 ins_cost(MEMORY_REF_COST);
5163 size(Z_DISP_SIZE);
5164 format %{ "ST $src,$mem\t # (cOop)" %}
5165 opcode(STY_ZOPC, ST_ZOPC);
5166 ins_encode(z_form_rt_mem_opt(src, mem));
5167 ins_pipe(pipe_class_dummy);
5168 %}
5169
5170 // Store Compressed Klass pointer
5171 instruct storeNKlass(memory mem, iRegN src) %{
5172 match(Set mem (StoreNKlass mem src));
5173 ins_cost(MEMORY_REF_COST);
5174 size(Z_DISP_SIZE);
5175 format %{ "ST $src,$mem\t # (cKlass)" %}
5176 opcode(STY_ZOPC, ST_ZOPC);
5177 ins_encode(z_form_rt_mem_opt(src, mem));
5178 ins_pipe(pipe_class_dummy);
5179 %}
5180
5181 // Compare Compressed Pointers
5182
5183 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5184 match(Set cr (CmpN src1 src2));
5185 ins_cost(DEFAULT_COST);
5186 size(2);
5187 format %{ "CLR $src1,$src2\t # (cOop)" %}
5188 opcode(CLR_ZOPC);
5189 ins_encode(z_rrform(src1, src2));
5190 ins_pipe(pipe_class_dummy);
5191 %}
5192
5193 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5194 match(Set cr (CmpN src1 src2));
5195 ins_cost(DEFAULT_COST);
5196 size(6);
5197 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
5198 ins_encode %{
5199 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5200 __ relocate(cOop.rspec(), 1);
5201 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5202 %}
5203 ins_pipe(pipe_class_dummy);
5204 %}
5205
5206 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5207 match(Set cr (CmpN src1 src2));
5208 ins_cost(DEFAULT_COST);
5209 size(6);
5210 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
5211 ins_encode %{
5212 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5213 __ relocate(NKlass.rspec(), 1);
5214 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5215 %}
5216 ins_pipe(pipe_class_dummy);
5217 %}
5218
5219 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5220 match(Set cr (CmpN src1 src2));
5221 ins_cost(DEFAULT_COST);
5222 size(2);
5223 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
5224 opcode(LTR_ZOPC);
5225 ins_encode(z_rrform(src1, src1));
5226 ins_pipe(pipe_class_dummy);
5227 %}
5228
5229
5230 //----------MemBar Instructions-----------------------------------------------
5231
5232 // Memory barrier flavors
5233
5234 instruct membar_acquire() %{
5235 match(MemBarAcquire);
5236 match(LoadFence);
5237 ins_cost(4*MEMORY_REF_COST);
5238 size(0);
5239 format %{ "MEMBAR-acquire" %}
5240 ins_encode %{ __ z_acquire(); %}
5241 ins_pipe(pipe_class_dummy);
5242 %}
5243
5244 instruct membar_acquire_lock() %{
5245 match(MemBarAcquireLock);
5246 ins_cost(0);
5247 size(0);
5248 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5249 ins_encode(/*empty*/);
5250 ins_pipe(pipe_class_dummy);
5251 %}
5252
5253 instruct membar_release() %{
5254 match(MemBarRelease);
5255 match(StoreFence);
5256 ins_cost(4 * MEMORY_REF_COST);
5257 size(0);
5258 format %{ "MEMBAR-release" %}
5259 ins_encode %{ __ z_release(); %}
5260 ins_pipe(pipe_class_dummy);
5261 %}
5262
5263 instruct membar_release_lock() %{
5264 match(MemBarReleaseLock);
5265 ins_cost(0);
5266 size(0);
5267 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5268 ins_encode(/*empty*/);
5269 ins_pipe(pipe_class_dummy);
5270 %}
5271
5272 instruct membar_storeload() %{
5273 match(MemBarStoreLoad);
5274 ins_cost(4 * MEMORY_REF_COST);
5275 size(2);
5276 format %{ "MEMBAR-storeload" %}
5277 ins_encode %{ __ z_fence(); %}
5278 ins_pipe(pipe_class_dummy);
5279 %}
5280
5281 instruct membar_volatile() %{
5282 match(MemBarVolatile);
5283 ins_cost(4 * MEMORY_REF_COST);
5284 size(2);
5285 format %{ "MEMBAR-volatile" %}
5286 ins_encode %{ __ z_fence(); %}
5287 ins_pipe(pipe_class_dummy);
5288 %}
5289
5290 instruct unnecessary_membar_volatile() %{
5291 match(MemBarVolatile);
5292 predicate(Matcher::post_store_load_barrier(n));
5293 ins_cost(0);
5294 size(0);
5295 format %{ "# MEMBAR-volatile (empty)" %}
5296 ins_encode(/*empty*/);
5297 ins_pipe(pipe_class_dummy);
5298 %}
5299
5300 instruct membar_full() %{
5301 match(MemBarFull);
5302 ins_cost(4 * MEMORY_REF_COST);
5303 size(2);
5304 format %{ "MEMBAR-full" %}
5305 ins_encode %{ __ z_fence(); %}
5306 ins_pipe(pipe_class_dummy);
5307 %}
5308
5309 instruct membar_CPUOrder() %{
5310 match(MemBarCPUOrder);
5311 ins_cost(0);
5312 // TODO: s390 port size(FIXED_SIZE);
5313 format %{ "MEMBAR-CPUOrder (empty)" %}
5314 ins_encode(/*empty*/);
5315 ins_pipe(pipe_class_dummy);
5316 %}
5317
5318 instruct membar_storestore() %{
5319 match(MemBarStoreStore);
5320 match(StoreStoreFence);
5321 ins_cost(0);
5322 size(0);
5323 format %{ "MEMBAR-storestore (empty)" %}
5324 ins_encode();
5325 ins_pipe(pipe_class_dummy);
5326 %}
5327
5328
5329 //----------Register Move Instructions-----------------------------------------
5330
5331 // Cast Long to Pointer for unsafe natives.
5332 instruct castX2P(iRegP dst, iRegL src) %{
5333 match(Set dst (CastX2P src));
5334 // TODO: s390 port size(VARIABLE_SIZE);
5335 format %{ "LGR $dst,$src\t # CastX2P" %}
5336 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5337 ins_pipe(pipe_class_dummy);
5338 %}
5339
5340 // Cast Pointer to Long for unsafe natives.
5341 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5342 match(Set dst (CastP2X src));
5343 // TODO: s390 port size(VARIABLE_SIZE);
5344 format %{ "LGR $dst,$src\t # CastP2X" %}
5345 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5346 ins_pipe(pipe_class_dummy);
5347 %}
5348
5349 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5350 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5351 match(Set stkSlot src); // chain rule
5352 ins_cost(MEMORY_REF_COST);
5353 // TODO: s390 port size(FIXED_SIZE);
5354 format %{ " STD $src,$stkSlot\t # stk" %}
5355 opcode(STD_ZOPC);
5356 ins_encode(z_form_rt_mem(src, stkSlot));
5357 ins_pipe(pipe_class_dummy);
5358 %}
5359
5360 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5361 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5362 match(Set stkSlot src); // chain rule
5363 ins_cost(MEMORY_REF_COST);
5364 // TODO: s390 port size(FIXED_SIZE);
5365 format %{ "STE $src,$stkSlot\t # stk" %}
5366 opcode(STE_ZOPC);
5367 ins_encode(z_form_rt_mem(src, stkSlot));
5368 ins_pipe(pipe_class_dummy);
5369 %}
5370
5371 //----------Conditional Move---------------------------------------------------
5372
5373 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5374 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5375 ins_cost(DEFAULT_COST + BRANCH_COST);
5376 // TODO: s390 port size(VARIABLE_SIZE);
5377 format %{ "CMoveN,$cmp $dst,$src" %}
5378 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5379 ins_pipe(pipe_class_dummy);
5380 %}
5381
5382 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5383 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5384 ins_cost(DEFAULT_COST + BRANCH_COST);
5385 // TODO: s390 port size(VARIABLE_SIZE);
5386 format %{ "CMoveN,$cmp $dst,$src" %}
5387 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5388 ins_pipe(pipe_class_dummy);
5389 %}
5390
5391 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5392 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5393 ins_cost(DEFAULT_COST + BRANCH_COST);
5394 // TODO: s390 port size(VARIABLE_SIZE);
5395 format %{ "CMoveI,$cmp $dst,$src" %}
5396 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5397 ins_pipe(pipe_class_dummy);
5398 %}
5399
5400 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5401 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5402 ins_cost(DEFAULT_COST + BRANCH_COST);
5403 // TODO: s390 port size(VARIABLE_SIZE);
5404 format %{ "CMoveI,$cmp $dst,$src" %}
5405 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5406 ins_pipe(pipe_class_dummy);
5407 %}
5408
5409 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5410 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5411 ins_cost(DEFAULT_COST + BRANCH_COST);
5412 // TODO: s390 port size(VARIABLE_SIZE);
5413 format %{ "CMoveP,$cmp $dst,$src" %}
5414 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5415 ins_pipe(pipe_class_dummy);
5416 %}
5417
5418 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5419 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5420 ins_cost(DEFAULT_COST + BRANCH_COST);
5421 // TODO: s390 port size(VARIABLE_SIZE);
5422 format %{ "CMoveP,$cmp $dst,$src" %}
5423 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5424 ins_pipe(pipe_class_dummy);
5425 %}
5426
5427 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5428 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5429 ins_cost(DEFAULT_COST + BRANCH_COST);
5430 // TODO: s390 port size(VARIABLE_SIZE);
5431 format %{ "CMoveF,$cmp $dst,$src" %}
5432 ins_encode %{
5433 // Don't emit code if operands are identical (same register).
5434 if ($dst$$FloatRegister != $src$$FloatRegister) {
5435 Label done;
5436 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5437 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5438 __ bind(done);
5439 }
5440 %}
5441 ins_pipe(pipe_class_dummy);
5442 %}
5443
5444 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5445 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5446 ins_cost(DEFAULT_COST + BRANCH_COST);
5447 // TODO: s390 port size(VARIABLE_SIZE);
5448 format %{ "CMoveD,$cmp $dst,$src" %}
5449 ins_encode %{
5450 // Don't emit code if operands are identical (same register).
5451 if ($dst$$FloatRegister != $src$$FloatRegister) {
5452 Label done;
5453 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5454 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5455 __ bind(done);
5456 }
5457 %}
5458 ins_pipe(pipe_class_dummy);
5459 %}
5460
5461 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5462 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5463 ins_cost(DEFAULT_COST + BRANCH_COST);
5464 // TODO: s390 port size(VARIABLE_SIZE);
5465 format %{ "CMoveL,$cmp $dst,$src" %}
5466 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5467 ins_pipe(pipe_class_dummy);
5468 %}
5469
5470 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5471 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5472 ins_cost(DEFAULT_COST + BRANCH_COST);
5473 // TODO: s390 port size(VARIABLE_SIZE);
5474 format %{ "CMoveL,$cmp $dst,$src" %}
5475 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5476 ins_pipe(pipe_class_dummy);
5477 %}
5478
5479 //----------OS and Locking Instructions----------------------------------------
5480
5481 // This name is KNOWN by the ADLC and cannot be changed.
5482 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5483 // for this guy.
5484 instruct tlsLoadP(threadRegP dst) %{
5485 match(Set dst (ThreadLocal));
5486 ins_cost(0);
5487 size(0);
5488 ins_should_rematerialize(true);
5489 format %{ "# $dst=ThreadLocal" %}
5490 ins_encode(/* empty */);
5491 ins_pipe(pipe_class_dummy);
5492 %}
5493
5494 instruct checkCastPP(iRegP dst) %{
5495 match(Set dst (CheckCastPP dst));
5496 size(0);
5497 format %{ "# checkcastPP of $dst" %}
5498 ins_encode(/*empty*/);
5499 ins_pipe(pipe_class_dummy);
5500 %}
5501
5502 instruct castPP(iRegP dst) %{
5503 match(Set dst (CastPP dst));
5504 size(0);
5505 format %{ "# castPP of $dst" %}
5506 ins_encode(/*empty*/);
5507 ins_pipe(pipe_class_dummy);
5508 %}
5509
5510 instruct castII(iRegI dst) %{
5511 match(Set dst (CastII dst));
5512 size(0);
5513 format %{ "# castII of $dst" %}
5514 ins_encode(/*empty*/);
5515 ins_pipe(pipe_class_dummy);
5516 %}
5517
5518 instruct castLL(iRegL dst) %{
5519 match(Set dst (CastLL dst));
5520 size(0);
5521 format %{ "# castLL of $dst" %}
5522 ins_encode(/*empty*/);
5523 ins_pipe(pipe_class_dummy);
5524 %}
5525
5526 instruct castFF(regF dst) %{
5527 match(Set dst (CastFF dst));
5528 size(0);
5529 format %{ "# castFF of $dst" %}
5530 ins_encode(/*empty*/);
5531 ins_pipe(pipe_class_dummy);
5532 %}
5533
5534 instruct castDD(regD dst) %{
5535 match(Set dst (CastDD dst));
5536 size(0);
5537 format %{ "# castDD of $dst" %}
5538 ins_encode(/*empty*/);
5539 ins_pipe(pipe_class_dummy);
5540 %}
5541
5542 instruct castVV(iRegL dst) %{
5543 match(Set dst (CastVV dst));
5544 size(0);
5545 format %{ "# castVV of $dst" %}
5546 ins_encode(/*empty*/);
5547 ins_pipe(pipe_class_dummy);
5548 %}
5549
5550 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5551
5552 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5553 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5554 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5555 size(16);
5556 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5557 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5558 z_enc_cctobool(res));
5559 ins_pipe(pipe_class_dummy);
5560 %}
5561
5562 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5563 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5564 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5565 size(18);
5566 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5567 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5568 z_enc_cctobool(res));
5569 ins_pipe(pipe_class_dummy);
5570 %}
5571
5572 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5573 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5574 predicate(n->as_LoadStore()->barrier_data() == 0);
5575 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5576 size(18);
5577 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5578 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5579 z_enc_cctobool(res));
5580 ins_pipe(pipe_class_dummy);
5581 %}
5582
5583 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5584 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5585 predicate(n->as_LoadStore()->barrier_data() == 0);
5586 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5587 size(16);
5588 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5589 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5590 z_enc_cctobool(res));
5591 ins_pipe(pipe_class_dummy);
5592 %}
5593
5594 instruct compareAndExchangeN(iRegN res, iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, flagsReg cr) %{
5595 match(Set res (CompareAndExchangeN mem_ptr (Binary oldval newval)));
5596 predicate(n->as_LoadStore()->barrier_data() == 0);
5597 effect(TEMP_DEF res, USE mem_ptr, USE_KILL oldval, KILL cr);
5598 format %{ "$res = CompareAndExchangeN $oldval,$newval,$mem_ptr" %}
5599 ins_encode %{
5600 Register Rcomp = reg_to_register_object($oldval$$reg);
5601 Register Rnew = reg_to_register_object($newval$$reg);
5602 Register Raddr = reg_to_register_object($mem_ptr$$reg);
5603 Register Rres = reg_to_register_object($res$$reg);
5604 __ z_lr(Rres, Rcomp);
5605 __ z_cs(Rres, Rnew, 0, Raddr);
5606 %}
5607 ins_pipe(pipe_class_dummy);
5608 %}
5609
5610 instruct compareAndExchangeP(iRegP res, iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5611 match(Set res (CompareAndExchangeP mem_ptr (Binary oldval newval)));
5612 predicate(n->as_LoadStore()->barrier_data() == 0);
5613 effect(TEMP_DEF res, USE mem_ptr, USE_KILL oldval, KILL cr);
5614 format %{ "$res = CompareAndExchangeP $oldval,$newval,$mem_ptr" %}
5615 ins_encode %{
5616 Register Rcomp = reg_to_register_object($oldval$$reg);
5617 Register Rnew = reg_to_register_object($newval$$reg);
5618 Register Raddr = reg_to_register_object($mem_ptr$$reg);
5619 Register Rres = reg_to_register_object($res$$reg);
5620 __ z_lgr(Rres, Rcomp);
5621 __ z_csg(Rres, Rnew, 0, Raddr);
5622 %}
5623 ins_pipe(pipe_class_dummy);
5624 %}
5625
5626 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5627
5628 // Exploit: direct memory arithmetic
5629 // Prereqs: - instructions available
5630 // - instructions guarantee atomicity
5631 // - immediate operand to be added
5632 // - immediate operand is small enough (8-bit signed).
5633 // - result of instruction is not used
5634 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5635 match(Set dummy (GetAndAddI mem src));
5636 effect(KILL cr);
5637 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5638 ins_cost(MEMORY_REF_COST);
5639 size(6);
5640 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5641 opcode(ASI_ZOPC);
5642 ins_encode(z_siyform(mem, src));
5643 ins_pipe(pipe_class_dummy);
5644 %}
5645
5646 // Fallback: direct memory arithmetic not available
5647 // Disadvantages: - CS-Loop required, very expensive.
5648 // - more code generated (26 to xx bytes vs. 6 bytes)
5649 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5650 match(Set dst (GetAndAddI mem src));
5651 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5652 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5653 format %{ "BEGIN ATOMIC {\n\t"
5654 " LGF $dst,[$mem]\n\t"
5655 " AHIK $tmp,$dst,$src\n\t"
5656 " CSY $dst,$tmp,$mem\n\t"
5657 " retry if failed\n\t"
5658 "} END ATOMIC"
5659 %}
5660 ins_encode %{
5661 Register Rdst = $dst$$Register;
5662 Register Rtmp = $tmp$$Register;
5663 int Isrc = $src$$constant;
5664 Label retry;
5665
5666 // Iterate until update with incremented value succeeds.
5667 __ z_lgf(Rdst, $mem$$Address); // current contents
5668 __ bind(retry);
5669 // Calculate incremented value.
5670 if (VM_Version::has_DistinctOpnds()) {
5671 __ z_ahik(Rtmp, Rdst, Isrc);
5672 } else {
5673 __ z_lr(Rtmp, Rdst);
5674 __ z_ahi(Rtmp, Isrc);
5675 }
5676 // Swap into memory location.
5677 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5678 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5679 %}
5680 ins_pipe(pipe_class_dummy);
5681 %}
5682
5683 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5684 match(Set dst (GetAndAddI mem src));
5685 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5686 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5687 format %{ "BEGIN ATOMIC {\n\t"
5688 " LGF $dst,[$mem]\n\t"
5689 " LGR $tmp,$dst\n\t"
5690 " AFI $tmp,$src\n\t"
5691 " CSY $dst,$tmp,$mem\n\t"
5692 " retry if failed\n\t"
5693 "} END ATOMIC"
5694 %}
5695 ins_encode %{
5696 Register Rdst = $dst$$Register;
5697 Register Rtmp = $tmp$$Register;
5698 int Isrc = $src$$constant;
5699 Label retry;
5700
5701 // Iterate until update with incremented value succeeds.
5702 __ z_lgf(Rdst, $mem$$Address); // current contents
5703 __ bind(retry);
5704 // Calculate incremented value.
5705 __ z_lr(Rtmp, Rdst);
5706 __ z_afi(Rtmp, Isrc);
5707 // Swap into memory location.
5708 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5709 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5710 %}
5711 ins_pipe(pipe_class_dummy);
5712 %}
5713
5714 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5715 match(Set dst (GetAndAddI mem src));
5716 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5717 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5718 format %{ "BEGIN ATOMIC {\n\t"
5719 " LGF $dst,[$mem]\n\t"
5720 " ARK $tmp,$dst,$src\n\t"
5721 " CSY $dst,$tmp,$mem\n\t"
5722 " retry if failed\n\t"
5723 "} END ATOMIC"
5724 %}
5725 ins_encode %{
5726 Register Rsrc = $src$$Register;
5727 Register Rdst = $dst$$Register;
5728 Register Rtmp = $tmp$$Register;
5729 Label retry;
5730
5731 // Iterate until update with incremented value succeeds.
5732 __ z_lgf(Rdst, $mem$$Address); // current contents
5733 __ bind(retry);
5734 // Calculate incremented value.
5735 if (VM_Version::has_DistinctOpnds()) {
5736 __ z_ark(Rtmp, Rdst, Rsrc);
5737 } else {
5738 __ z_lr(Rtmp, Rdst);
5739 __ z_ar(Rtmp, Rsrc);
5740 }
5741 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5742 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5743 %}
5744 ins_pipe(pipe_class_dummy);
5745 %}
5746
5747
5748 // Exploit: direct memory arithmetic
5749 // Prereqs: - instructions available
5750 // - instructions guarantee atomicity
5751 // - immediate operand to be added
5752 // - immediate operand is small enough (8-bit signed).
5753 // - result of instruction is not used
5754 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5755 match(Set dummy (GetAndAddL mem src));
5756 effect(KILL cr);
5757 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5758 ins_cost(MEMORY_REF_COST);
5759 size(6);
5760 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5761 opcode(AGSI_ZOPC);
5762 ins_encode(z_siyform(mem, src));
5763 ins_pipe(pipe_class_dummy);
5764 %}
5765
5766 // Fallback: direct memory arithmetic not available
5767 // Disadvantages: - CS-Loop required, very expensive.
5768 // - more code generated (26 to xx bytes vs. 6 bytes)
5769 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5770 match(Set dst (GetAndAddL mem src));
5771 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5772 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5773 format %{ "BEGIN ATOMIC {\n\t"
5774 " LG $dst,[$mem]\n\t"
5775 " AGHIK $tmp,$dst,$src\n\t"
5776 " CSG $dst,$tmp,$mem\n\t"
5777 " retry if failed\n\t"
5778 "} END ATOMIC"
5779 %}
5780 ins_encode %{
5781 Register Rdst = $dst$$Register;
5782 Register Rtmp = $tmp$$Register;
5783 int Isrc = $src$$constant;
5784 Label retry;
5785
5786 // Iterate until update with incremented value succeeds.
5787 __ z_lg(Rdst, $mem$$Address); // current contents
5788 __ bind(retry);
5789 // Calculate incremented value.
5790 if (VM_Version::has_DistinctOpnds()) {
5791 __ z_aghik(Rtmp, Rdst, Isrc);
5792 } else {
5793 __ z_lgr(Rtmp, Rdst);
5794 __ z_aghi(Rtmp, Isrc);
5795 }
5796 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5797 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5798 %}
5799 ins_pipe(pipe_class_dummy);
5800 %}
5801
5802 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5803 match(Set dst (GetAndAddL mem src));
5804 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5805 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5806 format %{ "BEGIN ATOMIC {\n\t"
5807 " LG $dst,[$mem]\n\t"
5808 " LGR $tmp,$dst\n\t"
5809 " AGFI $tmp,$src\n\t"
5810 " CSG $dst,$tmp,$mem\n\t"
5811 " retry if failed\n\t"
5812 "} END ATOMIC"
5813 %}
5814 ins_encode %{
5815 Register Rdst = $dst$$Register;
5816 Register Rtmp = $tmp$$Register;
5817 int Isrc = $src$$constant;
5818 Label retry;
5819
5820 // Iterate until update with incremented value succeeds.
5821 __ z_lg(Rdst, $mem$$Address); // current contents
5822 __ bind(retry);
5823 // Calculate incremented value.
5824 __ z_lgr(Rtmp, Rdst);
5825 __ z_agfi(Rtmp, Isrc);
5826 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5827 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5828 %}
5829 ins_pipe(pipe_class_dummy);
5830 %}
5831
5832 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5833 match(Set dst (GetAndAddL mem src));
5834 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5835 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5836 format %{ "BEGIN ATOMIC {\n\t"
5837 " LG $dst,[$mem]\n\t"
5838 " AGRK $tmp,$dst,$src\n\t"
5839 " CSG $dst,$tmp,$mem\n\t"
5840 " retry if failed\n\t"
5841 "} END ATOMIC"
5842 %}
5843 ins_encode %{
5844 Register Rsrc = $src$$Register;
5845 Register Rdst = $dst$$Register;
5846 Register Rtmp = $tmp$$Register;
5847 Label retry;
5848
5849 // Iterate until update with incremented value succeeds.
5850 __ z_lg(Rdst, $mem$$Address); // current contents
5851 __ bind(retry);
5852 // Calculate incremented value.
5853 if (VM_Version::has_DistinctOpnds()) {
5854 __ z_agrk(Rtmp, Rdst, Rsrc);
5855 } else {
5856 __ z_lgr(Rtmp, Rdst);
5857 __ z_agr(Rtmp, Rsrc);
5858 }
5859 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5860 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5861 %}
5862 ins_pipe(pipe_class_dummy);
5863 %}
5864
5865 // Increment value in memory, save old value in dst.
5866 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5867 match(Set dst (GetAndAddI mem src));
5868 predicate(VM_Version::has_LoadAndALUAtomicV1());
5869 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5870 size(6);
5871 format %{ "LAA $dst,$src,[$mem]" %}
5872 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5873 ins_pipe(pipe_class_dummy);
5874 %}
5875
5876 // Increment value in memory, save old value in dst.
5877 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5878 match(Set dst (GetAndAddL mem src));
5879 predicate(VM_Version::has_LoadAndALUAtomicV1());
5880 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5881 size(6);
5882 format %{ "LAAG $dst,$src,[$mem]" %}
5883 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5884 ins_pipe(pipe_class_dummy);
5885 %}
5886
5887
5888 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5889 match(Set dst (GetAndSetI mem dst));
5890 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5891 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5892 ins_encode(z_enc_SwapI(mem, dst, tmp));
5893 ins_pipe(pipe_class_dummy);
5894 %}
5895
5896 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5897 match(Set dst (GetAndSetL mem dst));
5898 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5899 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5900 ins_encode(z_enc_SwapL(mem, dst, tmp));
5901 ins_pipe(pipe_class_dummy);
5902 %}
5903
5904 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5905 predicate(n->as_LoadStore()->barrier_data() == 0);
5906 match(Set dst (GetAndSetN mem dst));
5907 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5908 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5909 ins_encode(z_enc_SwapI(mem, dst, tmp));
5910 ins_pipe(pipe_class_dummy);
5911 %}
5912
5913 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5914 match(Set dst (GetAndSetP mem dst));
5915 predicate(n->as_LoadStore()->barrier_data() == 0);
5916 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5917 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5918 ins_encode(z_enc_SwapL(mem, dst, tmp));
5919 ins_pipe(pipe_class_dummy);
5920 %}
5921
5922
5923 //----------Arithmetic Instructions--------------------------------------------
5924
5925 // The rules are sorted by right operand type and operand length. Please keep
5926 // it that way.
5927 // Left operand type is always reg. Left operand len is I, L, P
5928 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5929 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5930
5931 // ADD
5932
5933 // REG = REG + REG
5934
5935 // Register Addition
5936 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5937 match(Set dst (AddI dst src));
5938 effect(KILL cr);
5939 // TODO: s390 port size(FIXED_SIZE);
5940 format %{ "AR $dst,$src\t # int CISC ALU" %}
5941 opcode(AR_ZOPC);
5942 ins_encode(z_rrform(dst, src));
5943 ins_pipe(pipe_class_dummy);
5944 %}
5945
5946 // Avoid use of LA(Y) for general ALU operation.
5947 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5948 match(Set dst (AddI src1 src2));
5949 effect(KILL cr);
5950 predicate(VM_Version::has_DistinctOpnds());
5951 ins_cost(DEFAULT_COST);
5952 size(4);
5953 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5954 opcode(ARK_ZOPC);
5955 ins_encode(z_rrfform(dst, src1, src2));
5956 ins_pipe(pipe_class_dummy);
5957 %}
5958
5959 // REG = REG + IMM
5960
5961 // Avoid use of LA(Y) for general ALU operation.
5962 // Immediate Addition
5963 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5964 match(Set dst (AddI dst con));
5965 effect(KILL cr);
5966 ins_cost(DEFAULT_COST);
5967 // TODO: s390 port size(FIXED_SIZE);
5968 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5969 opcode(AHI_ZOPC);
5970 ins_encode(z_riform_signed(dst, con));
5971 ins_pipe(pipe_class_dummy);
5972 %}
5973
5974 // Avoid use of LA(Y) for general ALU operation.
5975 // Immediate Addition
5976 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5977 match(Set dst (AddI src con));
5978 effect(KILL cr);
5979 predicate( VM_Version::has_DistinctOpnds());
5980 ins_cost(DEFAULT_COST);
5981 // TODO: s390 port size(FIXED_SIZE);
5982 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5983 opcode(AHIK_ZOPC);
5984 ins_encode(z_rieform_d(dst, src, con));
5985 ins_pipe(pipe_class_dummy);
5986 %}
5987
5988 // Immediate Addition
5989 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5990 match(Set dst (AddI dst src));
5991 effect(KILL cr);
5992 ins_cost(DEFAULT_COST_HIGH);
5993 size(6);
5994 format %{ "AFI $dst,$src" %}
5995 opcode(AFI_ZOPC);
5996 ins_encode(z_rilform_signed(dst, src));
5997 ins_pipe(pipe_class_dummy);
5998 %}
5999
6000 // Immediate Addition
6001 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
6002 match(Set dst (AddI src con));
6003 predicate(PreferLAoverADD);
6004 ins_cost(DEFAULT_COST_LOW);
6005 size(4);
6006 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
6007 opcode(LA_ZOPC);
6008 ins_encode(z_rxform_imm_reg(dst, con, src));
6009 ins_pipe(pipe_class_dummy);
6010 %}
6011
6012 // Immediate Addition
6013 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
6014 match(Set dst (AddI src con));
6015 predicate(PreferLAoverADD);
6016 ins_cost(DEFAULT_COST);
6017 size(6);
6018 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
6019 opcode(LAY_ZOPC);
6020 ins_encode(z_rxyform_imm_reg(dst, con, src));
6021 ins_pipe(pipe_class_dummy);
6022 %}
6023
6024 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
6025 match(Set dst (AddI (AddI src1 src2) con));
6026 predicate( PreferLAoverADD);
6027 ins_cost(DEFAULT_COST_LOW);
6028 size(4);
6029 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
6030 opcode(LA_ZOPC);
6031 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6032 ins_pipe(pipe_class_dummy);
6033 %}
6034
6035 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
6036 match(Set dst (AddI (AddI src1 src2) con));
6037 predicate(PreferLAoverADD);
6038 ins_cost(DEFAULT_COST);
6039 size(6);
6040 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
6041 opcode(LAY_ZOPC);
6042 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6043 ins_pipe(pipe_class_dummy);
6044 %}
6045
6046 // REG = REG + MEM
6047
6048 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6049 match(Set dst (AddI dst (LoadI src)));
6050 effect(KILL cr);
6051 ins_cost(MEMORY_REF_COST);
6052 // TODO: s390 port size(VARIABLE_SIZE);
6053 format %{ "A(Y) $dst, $src\t # int" %}
6054 opcode(AY_ZOPC, A_ZOPC);
6055 ins_encode(z_form_rt_mem_opt(dst, src));
6056 ins_pipe(pipe_class_dummy);
6057 %}
6058
6059 // MEM = MEM + IMM
6060
6061 // Add Immediate to 4-byte memory operand and result
6062 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
6063 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
6064 effect(KILL cr);
6065 predicate(VM_Version::has_MemWithImmALUOps());
6066 ins_cost(MEMORY_REF_COST);
6067 size(6);
6068 format %{ "ASI $mem,$src\t # direct mem add 4" %}
6069 opcode(ASI_ZOPC);
6070 ins_encode(z_siyform(mem, src));
6071 ins_pipe(pipe_class_dummy);
6072 %}
6073
6074
6075 //
6076
6077 // REG = REG + REG
6078
6079 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
6080 match(Set dst (AddL dst (ConvI2L src)));
6081 effect(KILL cr);
6082 size(4);
6083 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
6084 opcode(AGFR_ZOPC);
6085 ins_encode(z_rreform(dst, src));
6086 ins_pipe(pipe_class_dummy);
6087 %}
6088
6089 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6090 match(Set dst (AddL dst src));
6091 effect(KILL cr);
6092 // TODO: s390 port size(FIXED_SIZE);
6093 format %{ "AGR $dst, $src\t # long CISC ALU" %}
6094 opcode(AGR_ZOPC);
6095 ins_encode(z_rreform(dst, src));
6096 ins_pipe(pipe_class_dummy);
6097 %}
6098
6099 // Avoid use of LA(Y) for general ALU operation.
6100 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6101 match(Set dst (AddL src1 src2));
6102 effect(KILL cr);
6103 predicate(VM_Version::has_DistinctOpnds());
6104 ins_cost(DEFAULT_COST);
6105 size(4);
6106 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
6107 opcode(AGRK_ZOPC);
6108 ins_encode(z_rrfform(dst, src1, src2));
6109 ins_pipe(pipe_class_dummy);
6110 %}
6111
6112 // REG = REG + IMM
6113
6114 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
6115 match(Set dst (AddL src con));
6116 predicate( PreferLAoverADD);
6117 ins_cost(DEFAULT_COST_LOW);
6118 size(4);
6119 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
6120 opcode(LA_ZOPC);
6121 ins_encode(z_rxform_imm_reg(dst, con, src));
6122 ins_pipe(pipe_class_dummy);
6123 %}
6124
6125 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
6126 match(Set dst (AddL src con));
6127 predicate(PreferLAoverADD);
6128 ins_cost(DEFAULT_COST);
6129 size(6);
6130 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
6131 opcode(LAY_ZOPC);
6132 ins_encode(z_rxyform_imm_reg(dst, con, src));
6133 ins_pipe(pipe_class_dummy);
6134 %}
6135
6136 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
6137 match(Set dst (AddL dst con));
6138 effect(KILL cr);
6139 ins_cost(DEFAULT_COST_HIGH);
6140 size(6);
6141 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
6142 opcode(AGFI_ZOPC);
6143 ins_encode(z_rilform_signed(dst, con));
6144 ins_pipe(pipe_class_dummy);
6145 %}
6146
6147 // Avoid use of LA(Y) for general ALU operation.
6148 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6149 match(Set dst (AddL dst con));
6150 effect(KILL cr);
6151 ins_cost(DEFAULT_COST);
6152 // TODO: s390 port size(FIXED_SIZE);
6153 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6154 opcode(AGHI_ZOPC);
6155 ins_encode(z_riform_signed(dst, con));
6156 ins_pipe(pipe_class_dummy);
6157 %}
6158
6159 // Avoid use of LA(Y) for general ALU operation.
6160 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6161 match(Set dst (AddL src con));
6162 effect(KILL cr);
6163 predicate( VM_Version::has_DistinctOpnds());
6164 ins_cost(DEFAULT_COST);
6165 size(6);
6166 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6167 opcode(AGHIK_ZOPC);
6168 ins_encode(z_rieform_d(dst, src, con));
6169 ins_pipe(pipe_class_dummy);
6170 %}
6171
6172 // REG = REG + MEM
6173
6174 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6175 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6176 effect(KILL cr);
6177 ins_cost(MEMORY_REF_COST);
6178 size(Z_DISP3_SIZE);
6179 format %{ "AGF $dst, $src\t # long/int" %}
6180 opcode(AGF_ZOPC, AGF_ZOPC);
6181 ins_encode(z_form_rt_mem_opt(dst, src));
6182 ins_pipe(pipe_class_dummy);
6183 %}
6184
6185 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6186 match(Set dst (AddL dst (LoadL src)));
6187 effect(KILL cr);
6188 ins_cost(MEMORY_REF_COST);
6189 size(Z_DISP3_SIZE);
6190 format %{ "AG $dst, $src\t # long" %}
6191 opcode(AG_ZOPC, AG_ZOPC);
6192 ins_encode(z_form_rt_mem_opt(dst, src));
6193 ins_pipe(pipe_class_dummy);
6194 %}
6195
6196 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6197 match(Set dst (AddL (AddL src1 src2) con));
6198 predicate( PreferLAoverADD);
6199 ins_cost(DEFAULT_COST_LOW);
6200 size(4);
6201 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6202 opcode(LA_ZOPC);
6203 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6204 ins_pipe(pipe_class_dummy);
6205 %}
6206
6207 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6208 match(Set dst (AddL (AddL src1 src2) con));
6209 predicate(PreferLAoverADD);
6210 ins_cost(DEFAULT_COST);
6211 size(6);
6212 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6213 opcode(LAY_ZOPC);
6214 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6215 ins_pipe(pipe_class_dummy);
6216 %}
6217
6218 // MEM = MEM + IMM
6219
6220 // Add Immediate to 8-byte memory operand and result.
6221 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6222 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6223 effect(KILL cr);
6224 predicate(VM_Version::has_MemWithImmALUOps());
6225 ins_cost(MEMORY_REF_COST);
6226 size(6);
6227 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6228 opcode(AGSI_ZOPC);
6229 ins_encode(z_siyform(mem, src));
6230 ins_pipe(pipe_class_dummy);
6231 %}
6232
6233
6234 // REG = REG + REG
6235
6236 // Ptr Addition
6237 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6238 match(Set dst (AddP src1 src2));
6239 predicate( PreferLAoverADD);
6240 ins_cost(DEFAULT_COST);
6241 size(4);
6242 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6243 opcode(LA_ZOPC);
6244 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6245 ins_pipe(pipe_class_dummy);
6246 %}
6247
6248 // Ptr Addition
6249 // Avoid use of LA(Y) for general ALU operation.
6250 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6251 match(Set dst (AddP dst src));
6252 effect(KILL cr);
6253 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6254 ins_cost(DEFAULT_COST);
6255 // TODO: s390 port size(FIXED_SIZE);
6256 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6257 opcode(ALGR_ZOPC);
6258 ins_encode(z_rreform(dst, src));
6259 ins_pipe(pipe_class_dummy);
6260 %}
6261
6262 // Ptr Addition
6263 // Avoid use of LA(Y) for general ALU operation.
6264 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6265 match(Set dst (AddP src1 src2));
6266 effect(KILL cr);
6267 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6268 ins_cost(DEFAULT_COST);
6269 // TODO: s390 port size(FIXED_SIZE);
6270 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6271 opcode(ALGRK_ZOPC);
6272 ins_encode(z_rrfform(dst, src1, src2));
6273 ins_pipe(pipe_class_dummy);
6274 %}
6275
6276 // REG = REG + IMM
6277
6278 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6279 match(Set dst (AddP src con));
6280 predicate( PreferLAoverADD);
6281 ins_cost(DEFAULT_COST_LOW);
6282 size(4);
6283 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6284 opcode(LA_ZOPC);
6285 ins_encode(z_rxform_imm_reg(dst, con, src));
6286 ins_pipe(pipe_class_dummy);
6287 %}
6288
6289 // Avoid use of LA(Y) for general ALU operation.
6290 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6291 match(Set dst (AddP dst src));
6292 effect(KILL cr);
6293 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6294 ins_cost(DEFAULT_COST);
6295 // TODO: s390 port size(FIXED_SIZE);
6296 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6297 opcode(AGHI_ZOPC);
6298 ins_encode(z_riform_signed(dst, src));
6299 ins_pipe(pipe_class_dummy);
6300 %}
6301
6302 // Avoid use of LA(Y) for general ALU operation.
6303 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6304 match(Set dst (AddP src con));
6305 effect(KILL cr);
6306 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6307 ins_cost(DEFAULT_COST);
6308 // TODO: s390 port size(FIXED_SIZE);
6309 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6310 opcode(ALGHSIK_ZOPC);
6311 ins_encode(z_rieform_d(dst, src, con));
6312 ins_pipe(pipe_class_dummy);
6313 %}
6314
6315 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6316 match(Set dst (AddP src con));
6317 predicate(PreferLAoverADD);
6318 ins_cost(DEFAULT_COST);
6319 size(6);
6320 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6321 opcode(LAY_ZOPC);
6322 ins_encode(z_rxyform_imm_reg(dst, con, src));
6323 ins_pipe(pipe_class_dummy);
6324 %}
6325
6326 // Pointer Immediate Addition
6327 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6328 match(Set dst (AddP dst src));
6329 effect(KILL cr);
6330 ins_cost(DEFAULT_COST_HIGH);
6331 // TODO: s390 port size(FIXED_SIZE);
6332 format %{ "AGFI $dst,$src\t # ptr" %}
6333 opcode(AGFI_ZOPC);
6334 ins_encode(z_rilform_signed(dst, src));
6335 ins_pipe(pipe_class_dummy);
6336 %}
6337
6338 // REG = REG1 + REG2 + IMM
6339
6340 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6341 match(Set dst (AddP (AddP src1 src2) con));
6342 predicate( PreferLAoverADD);
6343 ins_cost(DEFAULT_COST_LOW);
6344 size(4);
6345 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6346 opcode(LA_ZOPC);
6347 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6348 ins_pipe(pipe_class_dummy);
6349 %}
6350
6351 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6352 match(Set dst (AddP (AddP src1 src2) con));
6353 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6354 ins_cost(DEFAULT_COST_LOW);
6355 size(4);
6356 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6357 opcode(LA_ZOPC);
6358 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6359 ins_pipe(pipe_class_dummy);
6360 %}
6361
6362 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6363 match(Set dst (AddP (AddP src1 src2) con));
6364 predicate(PreferLAoverADD);
6365 ins_cost(DEFAULT_COST);
6366 // TODO: s390 port size(FIXED_SIZE);
6367 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6368 opcode(LAY_ZOPC);
6369 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6370 ins_pipe(pipe_class_dummy);
6371 %}
6372
6373 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6374 match(Set dst (AddP (AddP src1 src2) con));
6375 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6376 ins_cost(DEFAULT_COST);
6377 // TODO: s390 port size(FIXED_SIZE);
6378 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6379 opcode(LAY_ZOPC);
6380 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6381 ins_pipe(pipe_class_dummy);
6382 %}
6383
6384 // MEM = MEM + IMM
6385
6386 // Add Immediate to 8-byte memory operand and result
6387 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6388 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6389 effect(KILL cr);
6390 predicate(VM_Version::has_MemWithImmALUOps() && n->as_LoadStore()->barrier_data() == 0);
6391 ins_cost(MEMORY_REF_COST);
6392 size(6);
6393 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6394 opcode(AGSI_ZOPC);
6395 ins_encode(z_siyform(mem, src));
6396 ins_pipe(pipe_class_dummy);
6397 %}
6398
6399 // SUB
6400
6401 // Register Subtraction
6402 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6403 match(Set dst (SubI dst src));
6404 effect(KILL cr);
6405 // TODO: s390 port size(FIXED_SIZE);
6406 format %{ "SR $dst,$src\t # int CISC ALU" %}
6407 opcode(SR_ZOPC);
6408 ins_encode(z_rrform(dst, src));
6409 ins_pipe(pipe_class_dummy);
6410 %}
6411
6412 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6413 match(Set dst (SubI src1 src2));
6414 effect(KILL cr);
6415 predicate(VM_Version::has_DistinctOpnds());
6416 ins_cost(DEFAULT_COST);
6417 size(4);
6418 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6419 opcode(SRK_ZOPC);
6420 ins_encode(z_rrfform(dst, src1, src2));
6421 ins_pipe(pipe_class_dummy);
6422 %}
6423
6424 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6425 match(Set dst (SubI dst (LoadI src)));
6426 effect(KILL cr);
6427 ins_cost(MEMORY_REF_COST);
6428 // TODO: s390 port size(VARIABLE_SIZE);
6429 format %{ "S(Y) $dst, $src\t # int" %}
6430 opcode(SY_ZOPC, S_ZOPC);
6431 ins_encode(z_form_rt_mem_opt(dst, src));
6432 ins_pipe(pipe_class_dummy);
6433 %}
6434
6435 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6436 match(Set dst (SubI zero src));
6437 effect(KILL cr);
6438 size(2);
6439 format %{ "NEG $dst, $src" %}
6440 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6441 ins_pipe(pipe_class_dummy);
6442 %}
6443
6444 //
6445
6446 // Long subtraction
6447 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6448 match(Set dst (SubL dst src));
6449 effect(KILL cr);
6450 // TODO: s390 port size(FIXED_SIZE);
6451 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6452 opcode(SGR_ZOPC);
6453 ins_encode(z_rreform(dst, src));
6454 ins_pipe(pipe_class_dummy);
6455 %}
6456
6457 // Avoid use of LA(Y) for general ALU operation.
6458 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6459 match(Set dst (SubL src1 src2));
6460 effect(KILL cr);
6461 predicate(VM_Version::has_DistinctOpnds());
6462 ins_cost(DEFAULT_COST);
6463 size(4);
6464 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6465 opcode(SGRK_ZOPC);
6466 ins_encode(z_rrfform(dst, src1, src2));
6467 ins_pipe(pipe_class_dummy);
6468 %}
6469
6470 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6471 match(Set dst (SubL dst (ConvI2L src)));
6472 effect(KILL cr);
6473 size(4);
6474 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6475 opcode(SGFR_ZOPC);
6476 ins_encode(z_rreform(dst, src));
6477 ins_pipe(pipe_class_dummy);
6478 %}
6479
6480 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6481 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6482 effect(KILL cr);
6483 ins_cost(MEMORY_REF_COST);
6484 size(Z_DISP3_SIZE);
6485 format %{ "SGF $dst, $src\t # long/int" %}
6486 opcode(SGF_ZOPC, SGF_ZOPC);
6487 ins_encode(z_form_rt_mem_opt(dst, src));
6488 ins_pipe(pipe_class_dummy);
6489 %}
6490
6491 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6492 match(Set dst (SubL dst (LoadL src)));
6493 effect(KILL cr);
6494 ins_cost(MEMORY_REF_COST);
6495 size(Z_DISP3_SIZE);
6496 format %{ "SG $dst, $src\t # long" %}
6497 opcode(SG_ZOPC, SG_ZOPC);
6498 ins_encode(z_form_rt_mem_opt(dst, src));
6499 ins_pipe(pipe_class_dummy);
6500 %}
6501
6502 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6503
6504 // MUL
6505
6506 // Register Multiplication
6507 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6508 match(Set dst (MulI dst src));
6509 ins_cost(DEFAULT_COST);
6510 size(4);
6511 format %{ "MSR $dst, $src" %}
6512 opcode(MSR_ZOPC);
6513 ins_encode(z_rreform(dst, src));
6514 ins_pipe(pipe_class_dummy);
6515 %}
6516
6517 // Immediate Multiplication
6518 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6519 match(Set dst (MulI dst con));
6520 ins_cost(DEFAULT_COST);
6521 // TODO: s390 port size(FIXED_SIZE);
6522 format %{ "MHI $dst,$con" %}
6523 opcode(MHI_ZOPC);
6524 ins_encode(z_riform_signed(dst,con));
6525 ins_pipe(pipe_class_dummy);
6526 %}
6527
6528 // Immediate (32bit) Multiplication
6529 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6530 match(Set dst (MulI dst con));
6531 ins_cost(DEFAULT_COST);
6532 size(6);
6533 format %{ "MSFI $dst,$con" %}
6534 opcode(MSFI_ZOPC);
6535 ins_encode(z_rilform_signed(dst,con));
6536 ins_pipe(pipe_class_dummy);
6537 %}
6538
6539 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6540 match(Set dst (MulI dst (LoadI src)));
6541 ins_cost(MEMORY_REF_COST);
6542 // TODO: s390 port size(VARIABLE_SIZE);
6543 format %{ "MS(Y) $dst, $src\t # int" %}
6544 opcode(MSY_ZOPC, MS_ZOPC);
6545 ins_encode(z_form_rt_mem_opt(dst, src));
6546 ins_pipe(pipe_class_dummy);
6547 %}
6548
6549 //
6550
6551 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6552 match(Set dst (MulL dst (ConvI2L src)));
6553 ins_cost(DEFAULT_COST);
6554 // TODO: s390 port size(FIXED_SIZE);
6555 format %{ "MSGFR $dst $src\t # long/int" %}
6556 opcode(MSGFR_ZOPC);
6557 ins_encode(z_rreform(dst, src));
6558 ins_pipe(pipe_class_dummy);
6559 %}
6560
6561 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6562 match(Set dst (MulL dst src));
6563 ins_cost(DEFAULT_COST);
6564 size(4);
6565 format %{ "MSGR $dst $src\t # long" %}
6566 opcode(MSGR_ZOPC);
6567 ins_encode(z_rreform(dst, src));
6568 ins_pipe(pipe_class_dummy);
6569 %}
6570
6571 // Immediate Multiplication
6572 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6573 match(Set dst (MulL dst src));
6574 ins_cost(DEFAULT_COST);
6575 // TODO: s390 port size(FIXED_SIZE);
6576 format %{ "MGHI $dst,$src\t # long" %}
6577 opcode(MGHI_ZOPC);
6578 ins_encode(z_riform_signed(dst, src));
6579 ins_pipe(pipe_class_dummy);
6580 %}
6581
6582 // Immediate (32bit) Multiplication
6583 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6584 match(Set dst (MulL dst con));
6585 ins_cost(DEFAULT_COST);
6586 size(6);
6587 format %{ "MSGFI $dst,$con" %}
6588 opcode(MSGFI_ZOPC);
6589 ins_encode(z_rilform_signed(dst,con));
6590 ins_pipe(pipe_class_dummy);
6591 %}
6592
6593 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6594 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6595 ins_cost(MEMORY_REF_COST);
6596 size(Z_DISP3_SIZE);
6597 format %{ "MSGF $dst, $src\t # long" %}
6598 opcode(MSGF_ZOPC, MSGF_ZOPC);
6599 ins_encode(z_form_rt_mem_opt(dst, src));
6600 ins_pipe(pipe_class_dummy);
6601 %}
6602
6603 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6604 match(Set dst (MulL dst (LoadL src)));
6605 ins_cost(MEMORY_REF_COST);
6606 size(Z_DISP3_SIZE);
6607 format %{ "MSG $dst, $src\t # long" %}
6608 opcode(MSG_ZOPC, MSG_ZOPC);
6609 ins_encode(z_form_rt_mem_opt(dst, src));
6610 ins_pipe(pipe_class_dummy);
6611 %}
6612
6613 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6614 match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6615 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6616 ins_cost(7*DEFAULT_COST);
6617 // TODO: s390 port size(VARIABLE_SIZE);
6618 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6619 ins_encode%{
6620 Register dst = $Rdst$$Register;
6621 Register src1 = $Rsrc1$$Register;
6622 Register src2 = $Rsrc2$$Register;
6623 Register tmp1 = $Rtmp1$$Register;
6624 Register tmp2 = $Rdst$$Register;
6625 // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6626 // implementing mulhs(a,b) = mulhu(a,b) - (a & (b>>63)) - (b & (a>>63))
6627 __ z_srag(tmp2, src1, 63); // a>>63
6628 __ z_srag(tmp1, src2, 63); // b>>63
6629 __ z_ngr(tmp2, src2); // b & (a>>63)
6630 __ z_ngr(tmp1, src1); // a & (b>>63)
6631 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63)))
6632 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1),
6633 // multiplicand is taken from oddReg (src1), multiplier in src2.
6634 __ z_sgr(dst, tmp1);
6635 %}
6636 ins_pipe(pipe_class_dummy);
6637 %}
6638
6639 // DIV
6640
6641 // Integer DIVMOD with Register, both quotient and mod results
6642 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6643 match(DivModI dst1src1 src2);
6644 effect(KILL cr);
6645 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6646 size((VM_Version::has_CompareBranch() ? 24 : 26));
6647 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6648 ins_encode %{
6649 Register d1s1 = $dst1src1$$Register;
6650 Register d2 = $dst2$$Register;
6651 Register s2 = $src2$$Register;
6652
6653 assert_different_registers(d1s1, s2);
6654
6655 Label do_div, done_div;
6656 if (VM_Version::has_CompareBranch()) {
6657 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6658 } else {
6659 __ z_chi(s2, -1);
6660 __ z_brne(do_div);
6661 }
6662 __ z_lcr(d1s1, d1s1);
6663 __ clear_reg(d2, false, false);
6664 __ z_bru(done_div);
6665 __ bind(do_div);
6666 __ z_lgfr(d1s1, d1s1);
6667 __ z_dsgfr(d2, s2);
6668 __ bind(done_div);
6669 %}
6670 ins_pipe(pipe_class_dummy);
6671 %}
6672
6673
6674 // Register Division
6675 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6676 match(Set dst (DivI src1 src2));
6677 effect(KILL tmp, KILL cr);
6678 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6679 size((VM_Version::has_CompareBranch() ? 20 : 22));
6680 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6681 ins_encode %{
6682 Register a = $src1$$Register;
6683 Register b = $src2$$Register;
6684 Register t = $dst$$Register;
6685
6686 assert_different_registers(t, b);
6687
6688 Label do_div, done_div;
6689 if (VM_Version::has_CompareBranch()) {
6690 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6691 } else {
6692 __ z_chi(b, -1);
6693 __ z_brne(do_div);
6694 }
6695 __ z_lcr(t, a);
6696 __ z_bru(done_div);
6697 __ bind(do_div);
6698 __ z_lgfr(t, a);
6699 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6700 __ bind(done_div);
6701 %}
6702 ins_pipe(pipe_class_dummy);
6703 %}
6704
6705 // Immediate Division
6706 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6707 match(Set dst (DivI src1 src2));
6708 effect(KILL tmp, KILL cr); // R0 is killed, too.
6709 ins_cost(2 * DEFAULT_COST);
6710 // TODO: s390 port size(VARIABLE_SIZE);
6711 format %{ "DIV_const $dst,$src1,$src2" %}
6712 ins_encode %{
6713 // No sign extension of Rdividend needed here.
6714 if ($src2$$constant != -1) {
6715 __ z_lghi(Z_R0_scratch, $src2$$constant);
6716 __ z_lgfr($dst$$Register, $src1$$Register);
6717 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6718 } else {
6719 __ z_lcr($dst$$Register, $src1$$Register);
6720 }
6721 %}
6722 ins_pipe(pipe_class_dummy);
6723 %}
6724
6725 // Unsigned Integer Register Division
6726 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6727 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6728 instruct udivI_reg_reg(roddRegI r5_rodd_dst, iRegI src2, revenRegI r4_reven_tmp, flagsReg cr) %{
6729 match(Set r5_rodd_dst (UDivI r5_rodd_dst src2));
6730 effect(TEMP r4_reven_tmp, KILL cr);
6731 // TODO: size(4);
6732 format %{ "UDIV $r5_rodd_dst,$r5_rodd_dst,$src2" %}
6733 ins_encode %{
6734 Register b = $src2$$Register;
6735 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6736 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6737 assert_different_registers(r4_reven_tmp, r5_rodd_dst, b);
6738 assert(r4_reven_tmp->successor() == r5_rodd_dst, "even-odd pair required for the instruction");
6739
6740 __ block_comment("unsigned_div_int {");
6741 __ z_lhi(r4_reven_tmp, 0); // make upper 32bits 0
6742 __ z_dlr(r4_reven_tmp, b);
6743 __ block_comment("} unsigned_div_int");
6744 %}
6745 ins_pipe(pipe_class_dummy);
6746 %}
6747
6748 // Long DIVMOD with Register, both quotient and mod results
6749 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6750 match(DivModL dst1src1 src2);
6751 effect(KILL cr);
6752 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6753 size((VM_Version::has_CompareBranch() ? 22 : 24));
6754 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6755 ins_encode %{
6756 Register d1s1 = $dst1src1$$Register;
6757 Register d2 = $dst2$$Register;
6758 Register s2 = $src2$$Register;
6759
6760 Label do_div, done_div;
6761 if (VM_Version::has_CompareBranch()) {
6762 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6763 } else {
6764 __ z_cghi(s2, -1);
6765 __ z_brne(do_div);
6766 }
6767 __ z_lcgr(d1s1, d1s1);
6768 // indicate unused result
6769 (void) __ clear_reg(d2, true, false);
6770 __ z_bru(done_div);
6771 __ bind(do_div);
6772 __ z_dsgr(d2, s2);
6773 __ bind(done_div);
6774 %}
6775 ins_pipe(pipe_class_dummy);
6776 %}
6777
6778 // Register Long Division
6779 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6780 match(Set dst (DivL dst src));
6781 effect(KILL tmp, KILL cr);
6782 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6783 size((VM_Version::has_CompareBranch() ? 18 : 20));
6784 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6785 ins_encode %{
6786 Register b = $src$$Register;
6787 Register t = $dst$$Register;
6788
6789 Label done_div;
6790 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6791 if (VM_Version::has_CompareBranch()) {
6792 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6793 } else {
6794 __ z_cghi(b, -1);
6795 __ z_bre(done_div);
6796 }
6797 __ z_lcgr(t, t); // Restore sign.
6798 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6799 __ bind(done_div);
6800 %}
6801 ins_pipe(pipe_class_dummy);
6802 %}
6803
6804 // Register Unsigned Long Division
6805 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6806 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6807 instruct udivL_reg_reg(roddRegL r5_rodd_dst, iRegL src, revenRegL r4_reven_tmp, flagsReg cr) %{
6808 match(Set r5_rodd_dst (UDivL r5_rodd_dst src));
6809 effect(TEMP r4_reven_tmp, KILL cr);
6810 ins_cost(DEFAULT_COST);
6811 // TODO: size(4);
6812 format %{ "UDIVG $r5_rodd_dst,$r5_rodd_dst,$src" %}
6813 ins_encode %{
6814 Register b = $src$$Register;
6815 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6816 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6817 assert_different_registers(r5_rodd_dst, r4_reven_tmp, b);
6818 __ block_comment("unsigned_div_long {");
6819 __ z_lghi(r4_reven_tmp, 0); // make upper 64bits 0
6820 __ z_dlgr(r4_reven_tmp, b);
6821 __ block_comment("} unsigned_div_long");
6822 %}
6823 ins_pipe(pipe_class_dummy);
6824 %}
6825
6826 // Immediate Long Division
6827 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6828 match(Set dst (DivL src1 src2));
6829 effect(KILL tmp, KILL cr); // R0 is killed, too.
6830 ins_cost(2 * DEFAULT_COST);
6831 // TODO: s390 port size(VARIABLE_SIZE);
6832 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6833 ins_encode %{
6834 if ($src2$$constant != -1) {
6835 __ z_lghi(Z_R0_scratch, $src2$$constant);
6836 __ lgr_if_needed($dst$$Register, $src1$$Register);
6837 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6838 } else {
6839 __ z_lcgr($dst$$Register, $src1$$Register);
6840 }
6841 %}
6842 ins_pipe(pipe_class_dummy);
6843 %}
6844
6845 // REM
6846
6847 // Integer Remainder
6848 // Register Remainder
6849 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6850 match(Set dst (ModI src1 src2));
6851 effect(KILL tmp, KILL cr);
6852 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6853 // TODO: s390 port size(VARIABLE_SIZE);
6854 format %{ "MOD_checked $dst,$src1,$src2" %}
6855 ins_encode %{
6856 Register a = $src1$$Register;
6857 Register b = $src2$$Register;
6858 Register t = $dst$$Register;
6859 assert_different_registers(t->successor(), b);
6860
6861 Label do_div, done_div;
6862
6863 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6864 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6865 if (VM_Version::has_CompareBranch()) {
6866 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6867 } else {
6868 __ z_chi(b, -1);
6869 __ z_bre(done_div);
6870 }
6871 __ z_lgfr(t->successor(), a);
6872 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6873 } else {
6874 if (VM_Version::has_CompareBranch()) {
6875 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6876 } else {
6877 __ z_chi(b, -1);
6878 __ z_brne(do_div);
6879 }
6880 __ clear_reg(t, true, false);
6881 __ z_bru(done_div);
6882 __ bind(do_div);
6883 __ z_lgfr(t->successor(), a);
6884 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6885 }
6886 __ bind(done_div);
6887 %}
6888 ins_pipe(pipe_class_dummy);
6889 %}
6890
6891 // Register Unsigned Integer Remainder
6892 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6893 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6894 instruct umodI_reg_reg(revenRegI r4_reven_dst, iRegI src2, roddRegI r5_rodd_tmp, flagsReg cr) %{
6895 match(Set r4_reven_dst (UModI r4_reven_dst src2));
6896 effect(TEMP r5_rodd_tmp, KILL cr);
6897 ins_cost(DEFAULT_COST);
6898 // TODO: s390 port size(VARIABLE_SIZE);
6899 format %{ "UMOD $r4_reven_dst,$r4_reven_dst,$src2" %}
6900 ins_encode %{
6901 Register b = $src2$$Register;
6902 Register r4_reven_dst = $r4_reven_dst$$Register;
6903 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6904 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6905 assert(r4_reven_dst->successor() == r5_rodd_tmp, "must be an even-odd pair");
6906
6907 __ block_comment("unsigned_mod_integer {");
6908 __ z_lr(r5_rodd_tmp, r4_reven_dst); // load lower 32bits in odd register
6909 __ z_lhi(r4_reven_dst, 0); // make upper 32bits 0
6910 __ z_dlr(r4_reven_dst, b);
6911 __ block_comment("} unsigned_mod_integer");
6912 %}
6913 ins_pipe(pipe_class_dummy);
6914 %}
6915
6916 // Immediate Remainder
6917 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6918 match(Set dst (ModI src1 src2));
6919 effect(KILL tmp, KILL cr); // R0 is killed, too.
6920 ins_cost(3 * DEFAULT_COST);
6921 // TODO: s390 port size(VARIABLE_SIZE);
6922 format %{ "MOD_const $dst,src1,$src2" %}
6923 ins_encode %{
6924 assert_different_registers($dst$$Register, $src1$$Register);
6925 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6926 int divisor = $src2$$constant;
6927
6928 if (divisor != -1) {
6929 __ z_lghi(Z_R0_scratch, divisor);
6930 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6931 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6932 } else {
6933 __ clear_reg($dst$$Register, true, false);
6934 }
6935 %}
6936 ins_pipe(pipe_class_dummy);
6937 %}
6938
6939 // Register Long Remainder
6940 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6941 match(Set dst (ModL src1 src2));
6942 effect(KILL src1, KILL cr); // R0 is killed, too.
6943 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6944 // TODO: s390 port size(VARIABLE_SIZE);
6945 format %{ "MODG_checked $dst,$src1,$src2" %}
6946 ins_encode %{
6947 Register a = $src1$$Register;
6948 Register b = $src2$$Register;
6949 Register t = $dst$$Register;
6950 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6951
6952 Label do_div, done_div;
6953 if (t->encoding() != b->encoding()) {
6954 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6955 if (VM_Version::has_CompareBranch()) {
6956 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6957 } else {
6958 __ z_cghi(b, -1);
6959 __ z_bre(done_div);
6960 }
6961 __ z_dsgr(t, b);
6962 } else {
6963 if (VM_Version::has_CompareBranch()) {
6964 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6965 } else {
6966 __ z_cghi(b, -1);
6967 __ z_brne(do_div);
6968 }
6969 __ clear_reg(t, true, false);
6970 __ z_bru(done_div);
6971 __ bind(do_div);
6972 __ z_dsgr(t, b);
6973 }
6974 __ bind(done_div);
6975 %}
6976 ins_pipe(pipe_class_dummy);
6977 %}
6978
6979 // Register Unsigned Long Remainder
6980 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6981 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6982 instruct umodL_reg_reg(revenRegL r4_reven_dst, roddRegL r5_rodd_tmp, iRegL src2, flagsReg cr) %{
6983 match(Set r4_reven_dst (UModL r4_reven_dst src2));
6984 effect(TEMP r5_rodd_tmp, KILL cr);
6985 ins_cost(DEFAULT_COST);
6986 // TODO: s390 port size(VARIABLE_SIZE);
6987 format %{ "UMODG $r4_reven_dst,$r4_reven_dst,$src2" %}
6988 ins_encode %{
6989 Register b = $src2$$Register;
6990 Register r4_reven_dst = $r4_reven_dst$$Register;
6991 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6992 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6993 assert(r4_reven_dst->successor() == r5_rodd_tmp, "instruction requires an even-odd pair" );
6994
6995 __ block_comment("unsigned_mod_long {");
6996 __ z_lgr(r5_rodd_tmp, r4_reven_dst); // load lower 64bits in even register
6997 __ z_lghi(r4_reven_dst, 0); // make upper 64bits 0
6998 __ z_dlgr(r4_reven_dst, b);
6999 __ block_comment("} unsigned_mod_long");
7000 %}
7001 ins_pipe(pipe_class_dummy);
7002 %}
7003
7004 // Register Long Remainder
7005 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
7006 match(Set dst (ModL src1 src2));
7007 effect(KILL tmp, KILL cr); // R0 is killed, too.
7008 ins_cost(3 * DEFAULT_COST);
7009 // TODO: s390 port size(VARIABLE_SIZE);
7010 format %{ "MODG_const $dst,src1,$src2\t # long" %}
7011 ins_encode %{
7012 int divisor = $src2$$constant;
7013 if (divisor != -1) {
7014 __ z_lghi(Z_R0_scratch, divisor);
7015 __ z_lgr($dst$$Register->successor(), $src1$$Register);
7016 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
7017 } else {
7018 __ clear_reg($dst$$Register, true, false);
7019 }
7020 %}
7021 ins_pipe(pipe_class_dummy);
7022 %}
7023
7024 // SHIFT
7025
7026 // Shift left logical
7027
7028 // Register Shift Left variable
7029 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
7030 match(Set dst (LShiftI src nbits));
7031 effect(KILL cr); // R1 is killed, too.
7032 ins_cost(3 * DEFAULT_COST);
7033 size(14);
7034 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
7035 ins_encode %{
7036 __ z_lgr(Z_R1_scratch, $nbits$$Register);
7037 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7038 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
7039 %}
7040 ins_pipe(pipe_class_dummy);
7041 %}
7042
7043 // Register Shift Left Immediate
7044 // Constant shift count is masked in ideal graph already.
7045 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
7046 match(Set dst (LShiftI src nbits));
7047 size(6);
7048 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
7049 ins_encode %{
7050 int Nbit = $nbits$$constant;
7051 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7052 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7053 %}
7054 ins_pipe(pipe_class_dummy);
7055 %}
7056
7057 // Register Shift Left Immediate by 1bit
7058 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
7059 match(Set dst (LShiftI src nbits));
7060 predicate(PreferLAoverADD);
7061 ins_cost(DEFAULT_COST_LOW);
7062 size(4);
7063 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
7064 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
7065 ins_pipe(pipe_class_dummy);
7066 %}
7067
7068 // Register Shift Left Long
7069 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
7070 match(Set dst (LShiftL src1 nbits));
7071 size(6);
7072 format %{ "SLLG $dst,$src1,[$nbits]" %}
7073 opcode(SLLG_ZOPC);
7074 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
7075 ins_pipe(pipe_class_dummy);
7076 %}
7077
7078 // Register Shift Left Long Immediate
7079 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
7080 match(Set dst (LShiftL src1 nbits));
7081 size(6);
7082 format %{ "SLLG $dst,$src1,$nbits" %}
7083 opcode(SLLG_ZOPC);
7084 ins_encode(z_rsyform_const(dst, src1, nbits));
7085 ins_pipe(pipe_class_dummy);
7086 %}
7087
7088 // Register Shift Left Long Immediate by 1bit
7089 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
7090 match(Set dst (LShiftL src1 nbits));
7091 predicate(PreferLAoverADD);
7092 ins_cost(DEFAULT_COST_LOW);
7093 size(4);
7094 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
7095 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
7096 ins_pipe(pipe_class_dummy);
7097 %}
7098
7099 // Shift right arithmetic
7100
7101 // Register Arithmetic Shift Right
7102 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7103 match(Set dst (RShiftI dst src));
7104 effect(KILL cr); // R1 is killed, too.
7105 ins_cost(3 * DEFAULT_COST);
7106 size(12);
7107 format %{ "SRA $dst,[$src] & 31" %}
7108 ins_encode %{
7109 __ z_lgr(Z_R1_scratch, $src$$Register);
7110 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7111 __ z_sra($dst$$Register, 0, Z_R1_scratch);
7112 %}
7113 ins_pipe(pipe_class_dummy);
7114 %}
7115
7116 // Register Arithmetic Shift Right Immediate
7117 // Constant shift count is masked in ideal graph already.
7118 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
7119 match(Set dst (RShiftI dst src));
7120 effect(KILL cr);
7121 size(4);
7122 format %{ "SRA $dst,$src" %}
7123 ins_encode %{
7124 int Nbit = $src$$constant;
7125 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7126 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7127 %}
7128 ins_pipe(pipe_class_dummy);
7129 %}
7130
7131 // Register Arithmetic Shift Right Long
7132 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
7133 match(Set dst (RShiftL src1 src2));
7134 effect(KILL cr);
7135 size(6);
7136 format %{ "SRAG $dst,$src1,[$src2]" %}
7137 opcode(SRAG_ZOPC);
7138 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7139 ins_pipe(pipe_class_dummy);
7140 %}
7141
7142 // Register Arithmetic Shift Right Long Immediate
7143 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
7144 match(Set dst (RShiftL src1 src2));
7145 effect(KILL cr);
7146 size(6);
7147 format %{ "SRAG $dst,$src1,$src2" %}
7148 opcode(SRAG_ZOPC);
7149 ins_encode(z_rsyform_const(dst, src1, src2));
7150 ins_pipe(pipe_class_dummy);
7151 %}
7152
7153 // Shift right logical
7154
7155 // Register Shift Right
7156 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7157 match(Set dst (URShiftI dst src));
7158 effect(KILL cr); // R1 is killed, too.
7159 ins_cost(3 * DEFAULT_COST);
7160 size(12);
7161 format %{ "SRL $dst,[$src] & 31" %}
7162 ins_encode %{
7163 __ z_lgr(Z_R1_scratch, $src$$Register);
7164 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7165 __ z_srl($dst$$Register, 0, Z_R1_scratch);
7166 %}
7167 ins_pipe(pipe_class_dummy);
7168 %}
7169
7170 // Register Shift Right Immediate
7171 // Constant shift count is masked in ideal graph already.
7172 instruct srlI_reg_imm(iRegI dst, immI src) %{
7173 match(Set dst (URShiftI dst src));
7174 size(4);
7175 format %{ "SRL $dst,$src" %}
7176 ins_encode %{
7177 int Nbit = $src$$constant;
7178 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7179 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7180 %}
7181 ins_pipe(pipe_class_dummy);
7182 %}
7183
7184 // Register Shift Right Long
7185 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7186 match(Set dst (URShiftL src1 src2));
7187 size(6);
7188 format %{ "SRLG $dst,$src1,[$src2]" %}
7189 opcode(SRLG_ZOPC);
7190 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7191 ins_pipe(pipe_class_dummy);
7192 %}
7193
7194 // Register Shift Right Long Immediate
7195 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
7196 match(Set dst (URShiftL src1 src2));
7197 size(6);
7198 format %{ "SRLG $dst,$src1,$src2" %}
7199 opcode(SRLG_ZOPC);
7200 ins_encode(z_rsyform_const(dst, src1, src2));
7201 ins_pipe(pipe_class_dummy);
7202 %}
7203
7204 // Register Shift Right Immediate with a CastP2X
7205 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
7206 match(Set dst (URShiftL (CastP2X src1) src2));
7207 size(6);
7208 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
7209 opcode(SRLG_ZOPC);
7210 ins_encode(z_rsyform_const(dst, src1, src2));
7211 ins_pipe(pipe_class_dummy);
7212 %}
7213
7214 //----------Rotate Instructions------------------------------------------------
7215
7216 // Rotate left 32bit.
7217 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
7218 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
7219 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7220 size(6);
7221 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
7222 opcode(RLL_ZOPC);
7223 ins_encode(z_rsyform_const(dst, src, lshift));
7224 ins_pipe(pipe_class_dummy);
7225 %}
7226
7227 // Rotate left 64bit.
7228 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
7229 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
7230 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7231 size(6);
7232 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
7233 opcode(RLLG_ZOPC);
7234 ins_encode(z_rsyform_const(dst, src, lshift));
7235 ins_pipe(pipe_class_dummy);
7236 %}
7237
7238 // Rotate right 32bit.
7239 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
7240 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
7241 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7242 // TODO: s390 port size(FIXED_SIZE);
7243 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
7244 opcode(RLL_ZOPC);
7245 ins_encode(z_rsyform_const(dst, src, rshift));
7246 ins_pipe(pipe_class_dummy);
7247 %}
7248
7249 // Rotate right 64bit.
7250 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7251 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7252 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7253 // TODO: s390 port size(FIXED_SIZE);
7254 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
7255 opcode(RLLG_ZOPC);
7256 ins_encode(z_rsyform_const(dst, src, rshift));
7257 ins_pipe(pipe_class_dummy);
7258 %}
7259
7260
7261 //----------Overflow Math Instructions-----------------------------------------
7262
7263 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7264 match(Set cr (OverflowAddI op1 op2));
7265 effect(DEF cr, USE op1, USE op2);
7266 // TODO: s390 port size(FIXED_SIZE);
7267 format %{ "AR $op1,$op2\t # overflow check int" %}
7268 ins_encode %{
7269 __ z_lr(Z_R0_scratch, $op1$$Register);
7270 __ z_ar(Z_R0_scratch, $op2$$Register);
7271 %}
7272 ins_pipe(pipe_class_dummy);
7273 %}
7274
7275 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7276 match(Set cr (OverflowAddI op1 op2));
7277 effect(DEF cr, USE op1, USE op2);
7278 // TODO: s390 port size(VARIABLE_SIZE);
7279 format %{ "AR $op1,$op2\t # overflow check int" %}
7280 ins_encode %{
7281 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7282 __ z_ar(Z_R0_scratch, $op1$$Register);
7283 %}
7284 ins_pipe(pipe_class_dummy);
7285 %}
7286
7287 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7288 match(Set cr (OverflowAddL op1 op2));
7289 effect(DEF cr, USE op1, USE op2);
7290 // TODO: s390 port size(FIXED_SIZE);
7291 format %{ "AGR $op1,$op2\t # overflow check long" %}
7292 ins_encode %{
7293 __ z_lgr(Z_R0_scratch, $op1$$Register);
7294 __ z_agr(Z_R0_scratch, $op2$$Register);
7295 %}
7296 ins_pipe(pipe_class_dummy);
7297 %}
7298
7299 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7300 match(Set cr (OverflowAddL op1 op2));
7301 effect(DEF cr, USE op1, USE op2);
7302 // TODO: s390 port size(VARIABLE_SIZE);
7303 format %{ "AGR $op1,$op2\t # overflow check long" %}
7304 ins_encode %{
7305 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7306 __ z_agr(Z_R0_scratch, $op1$$Register);
7307 %}
7308 ins_pipe(pipe_class_dummy);
7309 %}
7310
7311 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7312 match(Set cr (OverflowSubI op1 op2));
7313 effect(DEF cr, USE op1, USE op2);
7314 // TODO: s390 port size(FIXED_SIZE);
7315 format %{ "SR $op1,$op2\t # overflow check int" %}
7316 ins_encode %{
7317 __ z_lr(Z_R0_scratch, $op1$$Register);
7318 __ z_sr(Z_R0_scratch, $op2$$Register);
7319 %}
7320 ins_pipe(pipe_class_dummy);
7321 %}
7322
7323 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7324 match(Set cr (OverflowSubI op1 op2));
7325 effect(DEF cr, USE op1, USE op2);
7326 // TODO: s390 port size(VARIABLE_SIZE);
7327 format %{ "SR $op1,$op2\t # overflow check int" %}
7328 ins_encode %{
7329 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7330 __ z_lr(Z_R0_scratch, $op1$$Register);
7331 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7332 %}
7333 ins_pipe(pipe_class_dummy);
7334 %}
7335
7336 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7337 match(Set cr (OverflowSubL op1 op2));
7338 effect(DEF cr, USE op1, USE op2);
7339 // TODO: s390 port size(FIXED_SIZE);
7340 format %{ "SGR $op1,$op2\t # overflow check long" %}
7341 ins_encode %{
7342 __ z_lgr(Z_R0_scratch, $op1$$Register);
7343 __ z_sgr(Z_R0_scratch, $op2$$Register);
7344 %}
7345 ins_pipe(pipe_class_dummy);
7346 %}
7347
7348 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7349 match(Set cr (OverflowSubL op1 op2));
7350 effect(DEF cr, USE op1, USE op2);
7351 // TODO: s390 port size(VARIABLE_SIZE);
7352 format %{ "SGR $op1,$op2\t # overflow check long" %}
7353 ins_encode %{
7354 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7355 __ z_lgr(Z_R0_scratch, $op1$$Register);
7356 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7357 %}
7358 ins_pipe(pipe_class_dummy);
7359 %}
7360
7361 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7362 match(Set cr (OverflowSubI zero op2));
7363 effect(DEF cr, USE op2);
7364 format %{ "NEG $op2\t # overflow check int" %}
7365 ins_encode %{
7366 __ clear_reg(Z_R0_scratch, false, false);
7367 __ z_sr(Z_R0_scratch, $op2$$Register);
7368 %}
7369 ins_pipe(pipe_class_dummy);
7370 %}
7371
7372 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7373 match(Set cr (OverflowSubL zero op2));
7374 effect(DEF cr, USE op2);
7375 format %{ "NEGG $op2\t # overflow check long" %}
7376 ins_encode %{
7377 __ clear_reg(Z_R0_scratch, true, false);
7378 __ z_sgr(Z_R0_scratch, $op2$$Register);
7379 %}
7380 ins_pipe(pipe_class_dummy);
7381 %}
7382
7383 // No intrinsics for multiplication, since there is no easy way
7384 // to check for overflow.
7385
7386
7387 //----------Floating Point Arithmetic Instructions-----------------------------
7388
7389 // ADD
7390
7391 // Add float single precision
7392 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7393 match(Set dst (AddF dst src));
7394 effect(KILL cr);
7395 ins_cost(ALU_REG_COST);
7396 size(4);
7397 format %{ "AEBR $dst,$src" %}
7398 opcode(AEBR_ZOPC);
7399 ins_encode(z_rreform(dst, src));
7400 ins_pipe(pipe_class_dummy);
7401 %}
7402
7403 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7404 match(Set dst (AddF dst (LoadF src)));
7405 effect(KILL cr);
7406 ins_cost(ALU_MEMORY_COST);
7407 size(6);
7408 format %{ "AEB $dst,$src\t # floatMemory" %}
7409 opcode(AEB_ZOPC);
7410 ins_encode(z_form_rt_memFP(dst, src));
7411 ins_pipe(pipe_class_dummy);
7412 %}
7413
7414 // Add float double precision
7415 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7416 match(Set dst (AddD dst src));
7417 effect(KILL cr);
7418 ins_cost(ALU_REG_COST);
7419 size(4);
7420 format %{ "ADBR $dst,$src" %}
7421 opcode(ADBR_ZOPC);
7422 ins_encode(z_rreform(dst, src));
7423 ins_pipe(pipe_class_dummy);
7424 %}
7425
7426 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7427 match(Set dst (AddD dst (LoadD src)));
7428 effect(KILL cr);
7429 ins_cost(ALU_MEMORY_COST);
7430 size(6);
7431 format %{ "ADB $dst,$src\t # doubleMemory" %}
7432 opcode(ADB_ZOPC);
7433 ins_encode(z_form_rt_memFP(dst, src));
7434 ins_pipe(pipe_class_dummy);
7435 %}
7436
7437 // SUB
7438
7439 // Sub float single precision
7440 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7441 match(Set dst (SubF dst src));
7442 effect(KILL cr);
7443 ins_cost(ALU_REG_COST);
7444 size(4);
7445 format %{ "SEBR $dst,$src" %}
7446 opcode(SEBR_ZOPC);
7447 ins_encode(z_rreform(dst, src));
7448 ins_pipe(pipe_class_dummy);
7449 %}
7450
7451 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7452 match(Set dst (SubF dst (LoadF src)));
7453 effect(KILL cr);
7454 ins_cost(ALU_MEMORY_COST);
7455 size(6);
7456 format %{ "SEB $dst,$src\t # floatMemory" %}
7457 opcode(SEB_ZOPC);
7458 ins_encode(z_form_rt_memFP(dst, src));
7459 ins_pipe(pipe_class_dummy);
7460 %}
7461
7462 // Sub float double precision
7463 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7464 match(Set dst (SubD dst src));
7465 effect(KILL cr);
7466 ins_cost(ALU_REG_COST);
7467 size(4);
7468 format %{ "SDBR $dst,$src" %}
7469 opcode(SDBR_ZOPC);
7470 ins_encode(z_rreform(dst, src));
7471 ins_pipe(pipe_class_dummy);
7472 %}
7473
7474 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7475 match(Set dst (SubD dst (LoadD src)));
7476 effect(KILL cr);
7477 ins_cost(ALU_MEMORY_COST);
7478 size(6);
7479 format %{ "SDB $dst,$src\t # doubleMemory" %}
7480 opcode(SDB_ZOPC);
7481 ins_encode(z_form_rt_memFP(dst, src));
7482 ins_pipe(pipe_class_dummy);
7483 %}
7484
7485 // MUL
7486
7487 // Mul float single precision
7488 instruct mulF_reg_reg(regF dst, regF src) %{
7489 match(Set dst (MulF dst src));
7490 // CC unchanged by MUL.
7491 ins_cost(ALU_REG_COST);
7492 size(4);
7493 format %{ "MEEBR $dst,$src" %}
7494 opcode(MEEBR_ZOPC);
7495 ins_encode(z_rreform(dst, src));
7496 ins_pipe(pipe_class_dummy);
7497 %}
7498
7499 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7500 match(Set dst (MulF dst (LoadF src)));
7501 // CC unchanged by MUL.
7502 ins_cost(ALU_MEMORY_COST);
7503 size(6);
7504 format %{ "MEEB $dst,$src\t # floatMemory" %}
7505 opcode(MEEB_ZOPC);
7506 ins_encode(z_form_rt_memFP(dst, src));
7507 ins_pipe(pipe_class_dummy);
7508 %}
7509
7510 // Mul float double precision
7511 instruct mulD_reg_reg(regD dst, regD src) %{
7512 match(Set dst (MulD dst src));
7513 // CC unchanged by MUL.
7514 ins_cost(ALU_REG_COST);
7515 size(4);
7516 format %{ "MDBR $dst,$src" %}
7517 opcode(MDBR_ZOPC);
7518 ins_encode(z_rreform(dst, src));
7519 ins_pipe(pipe_class_dummy);
7520 %}
7521
7522 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7523 match(Set dst (MulD dst (LoadD src)));
7524 // CC unchanged by MUL.
7525 ins_cost(ALU_MEMORY_COST);
7526 size(6);
7527 format %{ "MDB $dst,$src\t # doubleMemory" %}
7528 opcode(MDB_ZOPC);
7529 ins_encode(z_form_rt_memFP(dst, src));
7530 ins_pipe(pipe_class_dummy);
7531 %}
7532
7533 // Multiply-Accumulate
7534 // src1 * src2 + dst
7535 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7536 match(Set dst (FmaF dst (Binary src1 src2)));
7537 // CC unchanged by MUL-ADD.
7538 ins_cost(ALU_REG_COST);
7539 size(4);
7540 format %{ "MAEBR $dst, $src1, $src2" %}
7541 ins_encode %{
7542 assert(UseFMA, "Needs FMA instructions support.");
7543 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7544 %}
7545 ins_pipe(pipe_class_dummy);
7546 %}
7547
7548 // src1 * src2 + dst
7549 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7550 match(Set dst (FmaD dst (Binary src1 src2)));
7551 // CC unchanged by MUL-ADD.
7552 ins_cost(ALU_REG_COST);
7553 size(4);
7554 format %{ "MADBR $dst, $src1, $src2" %}
7555 ins_encode %{
7556 assert(UseFMA, "Needs FMA instructions support.");
7557 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7558 %}
7559 ins_pipe(pipe_class_dummy);
7560 %}
7561
7562 // src1 * src2 - dst
7563 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7564 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7565 // CC unchanged by MUL-SUB.
7566 ins_cost(ALU_REG_COST);
7567 size(4);
7568 format %{ "MSEBR $dst, $src1, $src2" %}
7569 ins_encode %{
7570 assert(UseFMA, "Needs FMA instructions support.");
7571 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7572 %}
7573 ins_pipe(pipe_class_dummy);
7574 %}
7575
7576 // src1 * src2 - dst
7577 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7578 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7579 // CC unchanged by MUL-SUB.
7580 ins_cost(ALU_REG_COST);
7581 size(4);
7582 format %{ "MSDBR $dst, $src1, $src2" %}
7583 ins_encode %{
7584 assert(UseFMA, "Needs FMA instructions support.");
7585 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7586 %}
7587 ins_pipe(pipe_class_dummy);
7588 %}
7589
7590 // src1 * src2 + dst
7591 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7592 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7593 // CC unchanged by MUL-ADD.
7594 ins_cost(ALU_MEMORY_COST);
7595 size(6);
7596 format %{ "MAEB $dst, $src1, $src2" %}
7597 ins_encode %{
7598 assert(UseFMA, "Needs FMA instructions support.");
7599 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7600 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7601 %}
7602 ins_pipe(pipe_class_dummy);
7603 %}
7604
7605 // src1 * src2 + dst
7606 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7607 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7608 // CC unchanged by MUL-ADD.
7609 ins_cost(ALU_MEMORY_COST);
7610 size(6);
7611 format %{ "MADB $dst, $src1, $src2" %}
7612 ins_encode %{
7613 assert(UseFMA, "Needs FMA instructions support.");
7614 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7615 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7616 %}
7617 ins_pipe(pipe_class_dummy);
7618 %}
7619
7620 // src1 * src2 - dst
7621 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7622 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7623 // CC unchanged by MUL-SUB.
7624 ins_cost(ALU_MEMORY_COST);
7625 size(6);
7626 format %{ "MSEB $dst, $src1, $src2" %}
7627 ins_encode %{
7628 assert(UseFMA, "Needs FMA instructions support.");
7629 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7630 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7631 %}
7632 ins_pipe(pipe_class_dummy);
7633 %}
7634
7635 // src1 * src2 - dst
7636 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7637 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7638 // CC unchanged by MUL-SUB.
7639 ins_cost(ALU_MEMORY_COST);
7640 size(6);
7641 format %{ "MSDB $dst, $src1, $src2" %}
7642 ins_encode %{
7643 assert(UseFMA, "Needs FMA instructions support.");
7644 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7645 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7646 %}
7647 ins_pipe(pipe_class_dummy);
7648 %}
7649
7650 // src1 * src2 + dst
7651 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7652 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7653 // CC unchanged by MUL-ADD.
7654 ins_cost(ALU_MEMORY_COST);
7655 size(6);
7656 format %{ "MAEB $dst, $src1, $src2" %}
7657 ins_encode %{
7658 assert(UseFMA, "Needs FMA instructions support.");
7659 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7660 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7661 %}
7662 ins_pipe(pipe_class_dummy);
7663 %}
7664
7665 // src1 * src2 + dst
7666 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7667 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7668 // CC unchanged by MUL-ADD.
7669 ins_cost(ALU_MEMORY_COST);
7670 size(6);
7671 format %{ "MADB $dst, $src1, $src2" %}
7672 ins_encode %{
7673 assert(UseFMA, "Needs FMA instructions support.");
7674 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7675 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7676 %}
7677 ins_pipe(pipe_class_dummy);
7678 %}
7679
7680 // src1 * src2 - dst
7681 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7682 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7683 // CC unchanged by MUL-SUB.
7684 ins_cost(ALU_MEMORY_COST);
7685 size(6);
7686 format %{ "MSEB $dst, $src1, $src2" %}
7687 ins_encode %{
7688 assert(UseFMA, "Needs FMA instructions support.");
7689 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7690 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7691 %}
7692 ins_pipe(pipe_class_dummy);
7693 %}
7694
7695 // src1 * src2 - dst
7696 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7697 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7698 // CC unchanged by MUL-SUB.
7699 ins_cost(ALU_MEMORY_COST);
7700 size(6);
7701 format %{ "MSDB $dst, $src1, $src2" %}
7702 ins_encode %{
7703 assert(UseFMA, "Needs FMA instructions support.");
7704 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7705 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7706 %}
7707 ins_pipe(pipe_class_dummy);
7708 %}
7709
7710 // DIV
7711
7712 // Div float single precision
7713 instruct divF_reg_reg(regF dst, regF src) %{
7714 match(Set dst (DivF dst src));
7715 // CC unchanged by DIV.
7716 ins_cost(ALU_REG_COST);
7717 size(4);
7718 format %{ "DEBR $dst,$src" %}
7719 opcode(DEBR_ZOPC);
7720 ins_encode(z_rreform(dst, src));
7721 ins_pipe(pipe_class_dummy);
7722 %}
7723
7724 instruct divF_reg_mem(regF dst, memoryRX src)%{
7725 match(Set dst (DivF dst (LoadF src)));
7726 // CC unchanged by DIV.
7727 ins_cost(ALU_MEMORY_COST);
7728 size(6);
7729 format %{ "DEB $dst,$src\t # floatMemory" %}
7730 opcode(DEB_ZOPC);
7731 ins_encode(z_form_rt_memFP(dst, src));
7732 ins_pipe(pipe_class_dummy);
7733 %}
7734
7735 // Div float double precision
7736 instruct divD_reg_reg(regD dst, regD src) %{
7737 match(Set dst (DivD dst src));
7738 // CC unchanged by DIV.
7739 ins_cost(ALU_REG_COST);
7740 size(4);
7741 format %{ "DDBR $dst,$src" %}
7742 opcode(DDBR_ZOPC);
7743 ins_encode(z_rreform(dst, src));
7744 ins_pipe(pipe_class_dummy);
7745 %}
7746
7747 instruct divD_reg_mem(regD dst, memoryRX src)%{
7748 match(Set dst (DivD dst (LoadD src)));
7749 // CC unchanged by DIV.
7750 ins_cost(ALU_MEMORY_COST);
7751 size(6);
7752 format %{ "DDB $dst,$src\t # doubleMemory" %}
7753 opcode(DDB_ZOPC);
7754 ins_encode(z_form_rt_memFP(dst, src));
7755 ins_pipe(pipe_class_dummy);
7756 %}
7757
7758 // ABS
7759
7760 // Absolute float single precision
7761 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7762 match(Set dst (AbsF src));
7763 effect(KILL cr);
7764 size(4);
7765 format %{ "LPEBR $dst,$src\t float" %}
7766 opcode(LPEBR_ZOPC);
7767 ins_encode(z_rreform(dst, src));
7768 ins_pipe(pipe_class_dummy);
7769 %}
7770
7771 // Absolute float double precision
7772 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7773 match(Set dst (AbsD src));
7774 effect(KILL cr);
7775 size(4);
7776 format %{ "LPDBR $dst,$src\t double" %}
7777 opcode(LPDBR_ZOPC);
7778 ins_encode(z_rreform(dst, src));
7779 ins_pipe(pipe_class_dummy);
7780 %}
7781
7782 // NEG(ABS)
7783
7784 // Negative absolute float single precision
7785 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7786 match(Set dst (NegF (AbsF src)));
7787 effect(KILL cr);
7788 size(4);
7789 format %{ "LNEBR $dst,$src\t float" %}
7790 opcode(LNEBR_ZOPC);
7791 ins_encode(z_rreform(dst, src));
7792 ins_pipe(pipe_class_dummy);
7793 %}
7794
7795 // Negative absolute float double precision
7796 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7797 match(Set dst (NegD (AbsD src)));
7798 effect(KILL cr);
7799 size(4);
7800 format %{ "LNDBR $dst,$src\t double" %}
7801 opcode(LNDBR_ZOPC);
7802 ins_encode(z_rreform(dst, src));
7803 ins_pipe(pipe_class_dummy);
7804 %}
7805
7806 // NEG
7807
7808 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7809 match(Set dst (NegF src));
7810 effect(KILL cr);
7811 size(4);
7812 format %{ "NegF $dst,$src\t float" %}
7813 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7814 ins_pipe(pipe_class_dummy);
7815 %}
7816
7817 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7818 match(Set dst (NegD src));
7819 effect(KILL cr);
7820 size(4);
7821 format %{ "NegD $dst,$src\t double" %}
7822 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7823 ins_pipe(pipe_class_dummy);
7824 %}
7825
7826 // SQRT
7827
7828 // Sqrt float precision
7829 instruct sqrtF_reg(regF dst, regF src) %{
7830 match(Set dst (SqrtF src));
7831 // CC remains unchanged.
7832 ins_cost(ALU_REG_COST);
7833 size(4);
7834 format %{ "SQEBR $dst,$src" %}
7835 opcode(SQEBR_ZOPC);
7836 ins_encode(z_rreform(dst, src));
7837 ins_pipe(pipe_class_dummy);
7838 %}
7839
7840 // Sqrt double precision
7841 instruct sqrtD_reg(regD dst, regD src) %{
7842 match(Set dst (SqrtD src));
7843 // CC remains unchanged.
7844 ins_cost(ALU_REG_COST);
7845 size(4);
7846 format %{ "SQDBR $dst,$src" %}
7847 opcode(SQDBR_ZOPC);
7848 ins_encode(z_rreform(dst, src));
7849 ins_pipe(pipe_class_dummy);
7850 %}
7851
7852 instruct sqrtF_mem(regF dst, memoryRX src) %{
7853 match(Set dst (SqrtF src));
7854 // CC remains unchanged.
7855 ins_cost(ALU_MEMORY_COST);
7856 size(6);
7857 format %{ "SQEB $dst,$src\t # floatMemory" %}
7858 opcode(SQEB_ZOPC);
7859 ins_encode(z_form_rt_memFP(dst, src));
7860 ins_pipe(pipe_class_dummy);
7861 %}
7862
7863 instruct sqrtD_mem(regD dst, memoryRX src) %{
7864 match(Set dst (SqrtD src));
7865 // CC remains unchanged.
7866 ins_cost(ALU_MEMORY_COST);
7867 // TODO: s390 port size(FIXED_SIZE);
7868 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7869 opcode(SQDB_ZOPC);
7870 ins_encode(z_form_rt_memFP(dst, src));
7871 ins_pipe(pipe_class_dummy);
7872 %}
7873
7874 //----------Logical Instructions-----------------------------------------------
7875
7876 // Register And
7877 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7878 match(Set dst (AndI dst src));
7879 effect(KILL cr);
7880 ins_cost(DEFAULT_COST_LOW);
7881 size(2);
7882 format %{ "NR $dst,$src\t # int" %}
7883 opcode(NR_ZOPC);
7884 ins_encode(z_rrform(dst, src));
7885 ins_pipe(pipe_class_dummy);
7886 %}
7887
7888 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7889 match(Set dst (AndI dst (LoadI src)));
7890 effect(KILL cr);
7891 ins_cost(MEMORY_REF_COST);
7892 // TODO: s390 port size(VARIABLE_SIZE);
7893 format %{ "N(Y) $dst, $src\t # int" %}
7894 opcode(NY_ZOPC, N_ZOPC);
7895 ins_encode(z_form_rt_mem_opt(dst, src));
7896 ins_pipe(pipe_class_dummy);
7897 %}
7898
7899 // Immediate And
7900 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7901 match(Set dst (AndI dst src));
7902 effect(KILL cr);
7903 ins_cost(DEFAULT_COST_HIGH);
7904 size(6);
7905 format %{ "NILF $dst,$src" %}
7906 opcode(NILF_ZOPC);
7907 ins_encode(z_rilform_unsigned(dst, src));
7908 ins_pipe(pipe_class_dummy);
7909 %}
7910
7911 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7912 match(Set dst (AndI dst src));
7913 effect(KILL cr);
7914 ins_cost(DEFAULT_COST);
7915 size(4);
7916 format %{ "NILH $dst,$src" %}
7917 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7918 ins_pipe(pipe_class_dummy);
7919 %}
7920
7921 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7922 match(Set dst (AndI dst src));
7923 effect(KILL cr);
7924 ins_cost(DEFAULT_COST);
7925 size(4);
7926 format %{ "NILL $dst,$src" %}
7927 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7928 ins_pipe(pipe_class_dummy);
7929 %}
7930
7931 // Register And Long
7932 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7933 match(Set dst (AndL dst src));
7934 effect(KILL cr);
7935 ins_cost(DEFAULT_COST);
7936 size(4);
7937 format %{ "NGR $dst,$src\t # long" %}
7938 opcode(NGR_ZOPC);
7939 ins_encode(z_rreform(dst, src));
7940 ins_pipe(pipe_class_dummy);
7941 %}
7942
7943 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7944 match(Set dst (AndL dst (LoadL src)));
7945 effect(KILL cr);
7946 ins_cost(MEMORY_REF_COST);
7947 size(Z_DISP3_SIZE);
7948 format %{ "NG $dst, $src\t # long" %}
7949 opcode(NG_ZOPC, NG_ZOPC);
7950 ins_encode(z_form_rt_mem_opt(dst, src));
7951 ins_pipe(pipe_class_dummy);
7952 %}
7953
7954 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7955 match(Set dst (AndL dst src));
7956 effect(KILL cr);
7957 ins_cost(DEFAULT_COST);
7958 size(4);
7959 format %{ "NILL $dst,$src\t # long" %}
7960 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7961 ins_pipe(pipe_class_dummy);
7962 %}
7963
7964 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7965 match(Set dst (AndL dst src));
7966 effect(KILL cr);
7967 ins_cost(DEFAULT_COST);
7968 size(4);
7969 format %{ "NILH $dst,$src\t # long" %}
7970 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7971 ins_pipe(pipe_class_dummy);
7972 %}
7973
7974 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7975 match(Set dst (AndL dst src));
7976 effect(KILL cr);
7977 ins_cost(DEFAULT_COST);
7978 size(4);
7979 format %{ "NIHL $dst,$src\t # long" %}
7980 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7981 ins_pipe(pipe_class_dummy);
7982 %}
7983
7984 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7985 match(Set dst (AndL dst src));
7986 effect(KILL cr);
7987 ins_cost(DEFAULT_COST);
7988 size(4);
7989 format %{ "NIHH $dst,$src\t # long" %}
7990 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7991 ins_pipe(pipe_class_dummy);
7992 %}
7993
7994 // OR
7995
7996 // Or Instructions
7997 // Register Or
7998 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7999 match(Set dst (OrI dst src));
8000 effect(KILL cr);
8001 size(2);
8002 format %{ "OR $dst,$src" %}
8003 opcode(OR_ZOPC);
8004 ins_encode(z_rrform(dst, src));
8005 ins_pipe(pipe_class_dummy);
8006 %}
8007
8008 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
8009 match(Set dst (OrI dst (LoadI src)));
8010 effect(KILL cr);
8011 ins_cost(MEMORY_REF_COST);
8012 // TODO: s390 port size(VARIABLE_SIZE);
8013 format %{ "O(Y) $dst, $src\t # int" %}
8014 opcode(OY_ZOPC, O_ZOPC);
8015 ins_encode(z_form_rt_mem_opt(dst, src));
8016 ins_pipe(pipe_class_dummy);
8017 %}
8018
8019 // Immediate Or
8020 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
8021 match(Set dst (OrI dst con));
8022 effect(KILL cr);
8023 size(4);
8024 format %{ "OILL $dst,$con" %}
8025 opcode(OILL_ZOPC);
8026 ins_encode(z_riform_unsigned(dst,con));
8027 ins_pipe(pipe_class_dummy);
8028 %}
8029
8030 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
8031 match(Set dst (OrI dst con));
8032 effect(KILL cr);
8033 ins_cost(DEFAULT_COST_HIGH);
8034 size(6);
8035 format %{ "OILF $dst,$con" %}
8036 opcode(OILF_ZOPC);
8037 ins_encode(z_rilform_unsigned(dst,con));
8038 ins_pipe(pipe_class_dummy);
8039 %}
8040
8041 // Register Or Long
8042 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
8043 match(Set dst (OrL dst src));
8044 effect(KILL cr);
8045 ins_cost(DEFAULT_COST);
8046 size(4);
8047 format %{ "OGR $dst,$src\t # long" %}
8048 opcode(OGR_ZOPC);
8049 ins_encode(z_rreform(dst, src));
8050 ins_pipe(pipe_class_dummy);
8051 %}
8052
8053 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
8054 match(Set dst (OrL dst (LoadL src)));
8055 effect(KILL cr);
8056 ins_cost(MEMORY_REF_COST);
8057 size(Z_DISP3_SIZE);
8058 format %{ "OG $dst, $src\t # long" %}
8059 opcode(OG_ZOPC, OG_ZOPC);
8060 ins_encode(z_form_rt_mem_opt(dst, src));
8061 ins_pipe(pipe_class_dummy);
8062 %}
8063
8064 // Immediate Or long
8065 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
8066 match(Set dst (OrL dst con));
8067 effect(KILL cr);
8068 ins_cost(DEFAULT_COST);
8069 size(4);
8070 format %{ "OILL $dst,$con\t # long" %}
8071 opcode(OILL_ZOPC);
8072 ins_encode(z_riform_unsigned(dst,con));
8073 ins_pipe(pipe_class_dummy);
8074 %}
8075
8076 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
8077 match(Set dst (OrI dst con));
8078 effect(KILL cr);
8079 ins_cost(DEFAULT_COST_HIGH);
8080 // TODO: s390 port size(FIXED_SIZE);
8081 format %{ "OILF $dst,$con\t # long" %}
8082 opcode(OILF_ZOPC);
8083 ins_encode(z_rilform_unsigned(dst,con));
8084 ins_pipe(pipe_class_dummy);
8085 %}
8086
8087 // XOR
8088
8089 // Register Xor
8090 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8091 match(Set dst (XorI dst src));
8092 effect(KILL cr);
8093 size(2);
8094 format %{ "XR $dst,$src" %}
8095 opcode(XR_ZOPC);
8096 ins_encode(z_rrform(dst, src));
8097 ins_pipe(pipe_class_dummy);
8098 %}
8099
8100 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
8101 match(Set dst (XorI dst (LoadI src)));
8102 effect(KILL cr);
8103 ins_cost(MEMORY_REF_COST);
8104 // TODO: s390 port size(VARIABLE_SIZE);
8105 format %{ "X(Y) $dst, $src\t # int" %}
8106 opcode(XY_ZOPC, X_ZOPC);
8107 ins_encode(z_form_rt_mem_opt(dst, src));
8108 ins_pipe(pipe_class_dummy);
8109 %}
8110
8111 // Immediate Xor
8112 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
8113 match(Set dst (XorI dst src));
8114 effect(KILL cr);
8115 ins_cost(DEFAULT_COST_HIGH);
8116 size(6);
8117 format %{ "XILF $dst,$src" %}
8118 opcode(XILF_ZOPC);
8119 ins_encode(z_rilform_unsigned(dst, src));
8120 ins_pipe(pipe_class_dummy);
8121 %}
8122
8123 // Register Xor Long
8124 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
8125 match(Set dst (XorL dst src));
8126 effect(KILL cr);
8127 ins_cost(DEFAULT_COST);
8128 size(4);
8129 format %{ "XGR $dst,$src\t # long" %}
8130 opcode(XGR_ZOPC);
8131 ins_encode(z_rreform(dst, src));
8132 ins_pipe(pipe_class_dummy);
8133 %}
8134
8135 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
8136 match(Set dst (XorL dst (LoadL src)));
8137 effect(KILL cr);
8138 ins_cost(MEMORY_REF_COST);
8139 size(Z_DISP3_SIZE);
8140 format %{ "XG $dst, $src\t # long" %}
8141 opcode(XG_ZOPC, XG_ZOPC);
8142 ins_encode(z_form_rt_mem_opt(dst, src));
8143 ins_pipe(pipe_class_dummy);
8144 %}
8145
8146 // Immediate Xor Long
8147 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
8148 match(Set dst (XorL dst con));
8149 effect(KILL cr);
8150 ins_cost(DEFAULT_COST_HIGH);
8151 size(6);
8152 format %{ "XILF $dst,$con\t # long" %}
8153 opcode(XILF_ZOPC);
8154 ins_encode(z_rilform_unsigned(dst,con));
8155 ins_pipe(pipe_class_dummy);
8156 %}
8157
8158 //----------Convert to Boolean-------------------------------------------------
8159
8160 // Convert integer to boolean.
8161 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
8162 match(Set dst (Conv2B src));
8163 effect(KILL cr);
8164 ins_cost(3 * DEFAULT_COST);
8165 size(6);
8166 format %{ "convI2B $dst,$src" %}
8167 ins_encode %{
8168 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
8169 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
8170 %}
8171 ins_pipe(pipe_class_dummy);
8172 %}
8173
8174 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
8175 match(Set dst (Conv2B src));
8176 effect(KILL cr);
8177 ins_cost(3 * DEFAULT_COST);
8178 size(10);
8179 format %{ "convP2B $dst,$src" %}
8180 ins_encode %{
8181 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
8182 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
8183 %}
8184 ins_pipe(pipe_class_dummy);
8185 %}
8186
8187 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8188 match(Set dst (CmpLTMask dst src));
8189 effect(KILL cr);
8190 ins_cost(2 * DEFAULT_COST);
8191 size(18);
8192 format %{ "Set $dst CmpLTMask $dst,$src" %}
8193 ins_encode %{
8194 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
8195 __ z_lgfr(Z_R0_scratch, $src$$Register);
8196 __ z_lgfr($dst$$Register, $dst$$Register);
8197 __ z_sgr($dst$$Register, Z_R0_scratch);
8198 __ z_srag($dst$$Register, $dst$$Register, 63);
8199 %}
8200 ins_pipe(pipe_class_dummy);
8201 %}
8202
8203 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
8204 match(Set dst (CmpLTMask dst zero));
8205 effect(KILL cr);
8206 ins_cost(DEFAULT_COST);
8207 size(4);
8208 format %{ "Set $dst CmpLTMask $dst,$zero" %}
8209 ins_encode %{ __ z_sra($dst$$Register, 31); %}
8210 ins_pipe(pipe_class_dummy);
8211 %}
8212
8213
8214 //----------Arithmetic Conversion Instructions---------------------------------
8215 // The conversions operations are all Alpha sorted. Please keep it that way!
8216
8217 instruct convD2F_reg(regF dst, regD src) %{
8218 match(Set dst (ConvD2F src));
8219 // CC remains unchanged.
8220 size(4);
8221 format %{ "LEDBR $dst,$src" %}
8222 opcode(LEDBR_ZOPC);
8223 ins_encode(z_rreform(dst, src));
8224 ins_pipe(pipe_class_dummy);
8225 %}
8226
8227 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
8228 match(Set dst (ConvF2I src));
8229 effect(KILL cr);
8230 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8231 size(16);
8232 format %{ "convF2I $dst,$src" %}
8233 ins_encode %{
8234 Label done;
8235 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8236 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8237 __ z_brno(done); // Result is zero if unordered argument.
8238 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8239 __ bind(done);
8240 %}
8241 ins_pipe(pipe_class_dummy);
8242 %}
8243
8244 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
8245 match(Set dst (ConvD2I src));
8246 effect(KILL cr);
8247 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8248 size(16);
8249 format %{ "convD2I $dst,$src" %}
8250 ins_encode %{
8251 Label done;
8252 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8253 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8254 __ z_brno(done); // Result is zero if unordered argument.
8255 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8256 __ bind(done);
8257 %}
8258 ins_pipe(pipe_class_dummy);
8259 %}
8260
8261 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8262 match(Set dst (ConvF2L src));
8263 effect(KILL cr);
8264 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8265 size(16);
8266 format %{ "convF2L $dst,$src" %}
8267 ins_encode %{
8268 Label done;
8269 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8270 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8271 __ z_brno(done); // Result is zero if unordered argument.
8272 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8273 __ bind(done);
8274 %}
8275 ins_pipe(pipe_class_dummy);
8276 %}
8277
8278 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8279 match(Set dst (ConvD2L src));
8280 effect(KILL cr);
8281 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8282 size(16);
8283 format %{ "convD2L $dst,$src" %}
8284 ins_encode %{
8285 Label done;
8286 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8287 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8288 __ z_brno(done); // Result is zero if unordered argument.
8289 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8290 __ bind(done);
8291 %}
8292 ins_pipe(pipe_class_dummy);
8293 %}
8294
8295 instruct convF2D_reg(regD dst, regF src) %{
8296 match(Set dst (ConvF2D src));
8297 // CC remains unchanged.
8298 size(4);
8299 format %{ "LDEBR $dst,$src" %}
8300 opcode(LDEBR_ZOPC);
8301 ins_encode(z_rreform(dst, src));
8302 ins_pipe(pipe_class_dummy);
8303 %}
8304
8305 instruct convF2D_mem(regD dst, memoryRX src) %{
8306 match(Set dst (ConvF2D src));
8307 // CC remains unchanged.
8308 size(6);
8309 format %{ "LDEB $dst,$src" %}
8310 opcode(LDEB_ZOPC);
8311 ins_encode(z_form_rt_memFP(dst, src));
8312 ins_pipe(pipe_class_dummy);
8313 %}
8314
8315 instruct convI2D_reg(regD dst, iRegI src) %{
8316 match(Set dst (ConvI2D src));
8317 // CC remains unchanged.
8318 ins_cost(DEFAULT_COST);
8319 size(4);
8320 format %{ "CDFBR $dst,$src" %}
8321 opcode(CDFBR_ZOPC);
8322 ins_encode(z_rreform(dst, src));
8323 ins_pipe(pipe_class_dummy);
8324 %}
8325
8326 // Optimization that saves up to two memory operations for each conversion.
8327 instruct convI2F_ireg(regF dst, iRegI src) %{
8328 match(Set dst (ConvI2F src));
8329 // CC remains unchanged.
8330 ins_cost(DEFAULT_COST);
8331 size(4);
8332 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8333 opcode(CEFBR_ZOPC);
8334 ins_encode(z_rreform(dst, src));
8335 ins_pipe(pipe_class_dummy);
8336 %}
8337
8338 instruct convI2L_reg(iRegL dst, iRegI src) %{
8339 match(Set dst (ConvI2L src));
8340 size(4);
8341 format %{ "LGFR $dst,$src\t # int->long" %}
8342 opcode(LGFR_ZOPC);
8343 ins_encode(z_rreform(dst, src));
8344 ins_pipe(pipe_class_dummy);
8345 %}
8346
8347 // Zero-extend convert int to long.
8348 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8349 match(Set dst (AndL (ConvI2L src) mask));
8350 size(4);
8351 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8352 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8353 ins_pipe(pipe_class_dummy);
8354 %}
8355
8356 // Zero-extend convert int to long.
8357 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8358 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8359 // Uses load_const_optmized, so size can vary.
8360 // TODO: s390 port size(VARIABLE_SIZE);
8361 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8362 opcode(LLGF_ZOPC, LLGF_ZOPC);
8363 ins_encode(z_form_rt_mem_opt(dst, src));
8364 ins_pipe(pipe_class_dummy);
8365 %}
8366
8367 // Zero-extend long
8368 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8369 match(Set dst (AndL src mask));
8370 size(4);
8371 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8372 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8373 ins_pipe(pipe_class_dummy);
8374 %}
8375
8376 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8377 match(Set dst (RShiftI (LShiftI src amount) amount));
8378 size(4);
8379 format %{ "LHR $dst,$src\t short->int" %}
8380 opcode(LHR_ZOPC);
8381 ins_encode(z_rreform(dst, src));
8382 ins_pipe(pipe_class_dummy);
8383 %}
8384
8385 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8386 match(Set dst (RShiftI (LShiftI src amount) amount));
8387 size(4);
8388 format %{ "LBR $dst,$src\t byte->int" %}
8389 opcode(LBR_ZOPC);
8390 ins_encode(z_rreform(dst, src));
8391 ins_pipe(pipe_class_dummy);
8392 %}
8393
8394 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8395 match(Set dst (MoveF2I src));
8396 ins_cost(MEMORY_REF_COST);
8397 size(4);
8398 format %{ "L $dst,$src\t # MoveF2I" %}
8399 opcode(L_ZOPC);
8400 ins_encode(z_form_rt_mem(dst, src));
8401 ins_pipe(pipe_class_dummy);
8402 %}
8403
8404 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8405 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8406 match(Set dst (MoveI2F src));
8407 ins_cost(MEMORY_REF_COST);
8408 // TODO: s390 port size(FIXED_SIZE);
8409 format %{ "LE $dst,$src\t # MoveI2F" %}
8410 opcode(LE_ZOPC);
8411 ins_encode(z_form_rt_mem(dst, src));
8412 ins_pipe(pipe_class_dummy);
8413 %}
8414
8415 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8416 match(Set dst (MoveD2L src));
8417 ins_cost(MEMORY_REF_COST);
8418 size(6);
8419 format %{ "LG $src,$dst\t # MoveD2L" %}
8420 opcode(LG_ZOPC);
8421 ins_encode(z_form_rt_mem(dst, src));
8422 ins_pipe(pipe_class_dummy);
8423 %}
8424
8425 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8426 match(Set dst (MoveL2D src));
8427 ins_cost(MEMORY_REF_COST);
8428 size(4);
8429 format %{ "LD $dst,$src\t # MoveL2D" %}
8430 opcode(LD_ZOPC);
8431 ins_encode(z_form_rt_mem(dst, src));
8432 ins_pipe(pipe_class_dummy);
8433 %}
8434
8435 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8436 match(Set dst (MoveI2F src));
8437 ins_cost(MEMORY_REF_COST);
8438 size(4);
8439 format %{ "ST $src,$dst\t # MoveI2F" %}
8440 opcode(ST_ZOPC);
8441 ins_encode(z_form_rt_mem(src, dst));
8442 ins_pipe(pipe_class_dummy);
8443 %}
8444
8445 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8446 match(Set dst (MoveD2L src));
8447 effect(DEF dst, USE src);
8448 ins_cost(MEMORY_REF_COST);
8449 size(4);
8450 format %{ "STD $src,$dst\t # MoveD2L" %}
8451 opcode(STD_ZOPC);
8452 ins_encode(z_form_rt_mem(src,dst));
8453 ins_pipe(pipe_class_dummy);
8454 %}
8455
8456 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8457 match(Set dst (MoveL2D src));
8458 ins_cost(MEMORY_REF_COST);
8459 size(6);
8460 format %{ "STG $src,$dst\t # MoveL2D" %}
8461 opcode(STG_ZOPC);
8462 ins_encode(z_form_rt_mem(src,dst));
8463 ins_pipe(pipe_class_dummy);
8464 %}
8465
8466 instruct convL2F_reg(regF dst, iRegL src) %{
8467 match(Set dst (ConvL2F src));
8468 // CC remains unchanged.
8469 ins_cost(DEFAULT_COST);
8470 size(4);
8471 format %{ "CEGBR $dst,$src" %}
8472 opcode(CEGBR_ZOPC);
8473 ins_encode(z_rreform(dst, src));
8474 ins_pipe(pipe_class_dummy);
8475 %}
8476
8477 instruct convL2D_reg(regD dst, iRegL src) %{
8478 match(Set dst (ConvL2D src));
8479 // CC remains unchanged.
8480 ins_cost(DEFAULT_COST);
8481 size(4);
8482 format %{ "CDGBR $dst,$src" %}
8483 opcode(CDGBR_ZOPC);
8484 ins_encode(z_rreform(dst, src));
8485 ins_pipe(pipe_class_dummy);
8486 %}
8487
8488 instruct convL2I_reg(iRegI dst, iRegL src) %{
8489 match(Set dst (ConvL2I src));
8490 // TODO: s390 port size(VARIABLE_SIZE);
8491 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8492 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8493 ins_pipe(pipe_class_dummy);
8494 %}
8495
8496 // Register Shift Right Immediate
8497 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8498 match(Set dst (ConvL2I (RShiftL src cnt)));
8499 effect(KILL cr);
8500 size(6);
8501 format %{ "SRAG $dst,$src,$cnt" %}
8502 opcode(SRAG_ZOPC);
8503 ins_encode(z_rsyform_const(dst, src, cnt));
8504 ins_pipe(pipe_class_dummy);
8505 %}
8506
8507 //----------TRAP based zero checks and range checks----------------------------
8508
8509 // SIGTRAP based implicit range checks in compiled code.
8510 // A range check in the ideal world has one of the following shapes:
8511 // - (If le (CmpU length index)), (IfTrue throw exception)
8512 // - (If lt (CmpU index length)), (IfFalse throw exception)
8513 //
8514 // Match range check 'If le (CmpU length index)'
8515 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8516 match(If cmp (CmpU length index));
8517 effect(USE labl);
8518 predicate(TrapBasedRangeChecks &&
8519 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8520 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8521 Matcher::branches_to_uncommon_trap(_leaf));
8522 ins_cost(1);
8523 // TODO: s390 port size(FIXED_SIZE);
8524
8525 ins_is_TrapBasedCheckNode(true);
8526
8527 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8528 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8529 ins_pipe(pipe_class_trap);
8530 %}
8531
8532 // Match range check 'If lt (CmpU index length)'
8533 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8534 match(If cmp (CmpU index length));
8535 effect(USE labl, KILL cr);
8536 predicate(TrapBasedRangeChecks &&
8537 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8538 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8539 Matcher::branches_to_uncommon_trap(_leaf));
8540 ins_cost(1);
8541 // TODO: s390 port size(FIXED_SIZE);
8542
8543 ins_is_TrapBasedCheckNode(true);
8544
8545 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8546 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8547 ins_pipe(pipe_class_trap);
8548 %}
8549
8550 // Match range check 'If lt (CmpU index length)'
8551 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8552 match(If cmp (CmpU index length));
8553 effect(USE labl);
8554 predicate(TrapBasedRangeChecks &&
8555 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8556 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8557 Matcher::branches_to_uncommon_trap(_leaf));
8558 ins_cost(1);
8559 // TODO: s390 port size(FIXED_SIZE);
8560
8561 ins_is_TrapBasedCheckNode(true);
8562
8563 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8564 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8565 ins_pipe(pipe_class_trap);
8566 %}
8567
8568 // Implicit zero checks (more implicit null checks).
8569 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8570 match(If cmp (CmpP value zero));
8571 effect(USE labl);
8572 predicate(TrapBasedNullChecks &&
8573 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8574 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8575 Matcher::branches_to_uncommon_trap(_leaf));
8576 size(6);
8577
8578 ins_is_TrapBasedCheckNode(true);
8579
8580 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8581 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8582 ins_pipe(pipe_class_trap);
8583 %}
8584
8585 // Implicit zero checks (more implicit null checks).
8586 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8587 match(If cmp (CmpN value zero));
8588 effect(USE labl);
8589 predicate(TrapBasedNullChecks &&
8590 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8591 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8592 Matcher::branches_to_uncommon_trap(_leaf));
8593 size(6);
8594
8595 ins_is_TrapBasedCheckNode(true);
8596
8597 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8598 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8599 ins_pipe(pipe_class_trap);
8600 %}
8601
8602 //----------Compare instructions-----------------------------------------------
8603
8604 // INT signed
8605
8606 // Compare Integers
8607 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8608 match(Set cr (CmpI op1 op2));
8609 size(2);
8610 format %{ "CR $op1,$op2" %}
8611 opcode(CR_ZOPC);
8612 ins_encode(z_rrform(op1, op2));
8613 ins_pipe(pipe_class_dummy);
8614 %}
8615
8616 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8617 match(Set cr (CmpI op1 op2));
8618 size(6);
8619 format %{ "CFI $op1,$op2" %}
8620 opcode(CFI_ZOPC);
8621 ins_encode(z_rilform_signed(op1, op2));
8622 ins_pipe(pipe_class_dummy);
8623 %}
8624
8625 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8626 match(Set cr (CmpI op1 op2));
8627 size(4);
8628 format %{ "CHI $op1,$op2" %}
8629 opcode(CHI_ZOPC);
8630 ins_encode(z_riform_signed(op1, op2));
8631 ins_pipe(pipe_class_dummy);
8632 %}
8633
8634 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8635 match(Set cr (CmpI op1 zero));
8636 ins_cost(DEFAULT_COST_LOW);
8637 size(2);
8638 format %{ "LTR $op1,$op1" %}
8639 opcode(LTR_ZOPC);
8640 ins_encode(z_rrform(op1, op1));
8641 ins_pipe(pipe_class_dummy);
8642 %}
8643
8644 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8645 match(Set cr (CmpI op1 (LoadI op2)));
8646 ins_cost(MEMORY_REF_COST);
8647 // TODO: s390 port size(VARIABLE_SIZE);
8648 format %{ "C(Y) $op1, $op2\t # int" %}
8649 opcode(CY_ZOPC, C_ZOPC);
8650 ins_encode(z_form_rt_mem_opt(op1, op2));
8651 ins_pipe(pipe_class_dummy);
8652 %}
8653
8654 // INT unsigned
8655
8656 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8657 match(Set cr (CmpU op1 op2));
8658 size(2);
8659 format %{ "CLR $op1,$op2\t # unsigned" %}
8660 opcode(CLR_ZOPC);
8661 ins_encode(z_rrform(op1, op2));
8662 ins_pipe(pipe_class_dummy);
8663 %}
8664
8665 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8666 match(Set cr (CmpU op1 op2));
8667 size(6);
8668 format %{ "CLFI $op1,$op2\t # unsigned" %}
8669 opcode(CLFI_ZOPC);
8670 ins_encode(z_rilform_unsigned(op1, op2));
8671 ins_pipe(pipe_class_dummy);
8672 %}
8673
8674 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8675 match(Set cr (CmpU op1 (LoadI op2)));
8676 ins_cost(MEMORY_REF_COST);
8677 // TODO: s390 port size(VARIABLE_SIZE);
8678 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8679 opcode(CLY_ZOPC, CL_ZOPC);
8680 ins_encode(z_form_rt_mem_opt(op1, op2));
8681 ins_pipe(pipe_class_dummy);
8682 %}
8683
8684 // LONG signed
8685
8686 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8687 match(Set cr (CmpL op1 op2));
8688 size(4);
8689 format %{ "CGR $op1,$op2\t # long" %}
8690 opcode(CGR_ZOPC);
8691 ins_encode(z_rreform(op1, op2));
8692 ins_pipe(pipe_class_dummy);
8693 %}
8694
8695 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8696 match(Set cr (CmpL op1 (ConvI2L op2)));
8697 size(4);
8698 format %{ "CGFR $op1,$op2\t # long/int" %}
8699 opcode(CGFR_ZOPC);
8700 ins_encode(z_rreform(op1, op2));
8701 ins_pipe(pipe_class_dummy);
8702 %}
8703
8704 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8705 match(Set cr (CmpL op1 con));
8706 size(6);
8707 format %{ "CGFI $op1,$con" %}
8708 opcode(CGFI_ZOPC);
8709 ins_encode(z_rilform_signed(op1, con));
8710 ins_pipe(pipe_class_dummy);
8711 %}
8712
8713 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8714 match(Set cr (CmpL op1 con));
8715 size(4);
8716 format %{ "CGHI $op1,$con" %}
8717 opcode(CGHI_ZOPC);
8718 ins_encode(z_riform_signed(op1, con));
8719 ins_pipe(pipe_class_dummy);
8720 %}
8721
8722 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8723 match(Set cr (CmpL op1 con));
8724 ins_cost(DEFAULT_COST_LOW);
8725 size(4);
8726 format %{ "LTGR $op1,$op1" %}
8727 opcode(LTGR_ZOPC);
8728 ins_encode(z_rreform(op1, op1));
8729 ins_pipe(pipe_class_dummy);
8730 %}
8731
8732 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8733 match(Set cr (CmpL (ConvI2L op1) con));
8734 ins_cost(DEFAULT_COST_LOW);
8735 size(4);
8736 format %{ "LTGFR $op1,$op1" %}
8737 opcode(LTGFR_ZOPC);
8738 ins_encode(z_rreform(op1, op1));
8739 ins_pipe(pipe_class_dummy);
8740 %}
8741
8742 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8743 match(Set cr (CmpL dst (LoadL src)));
8744 ins_cost(MEMORY_REF_COST);
8745 size(Z_DISP3_SIZE);
8746 format %{ "CG $dst, $src\t # long" %}
8747 opcode(CG_ZOPC, CG_ZOPC);
8748 ins_encode(z_form_rt_mem_opt(dst, src));
8749 ins_pipe(pipe_class_dummy);
8750 %}
8751
8752 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8753 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8754 ins_cost(MEMORY_REF_COST);
8755 size(Z_DISP3_SIZE);
8756 format %{ "CGF $dst, $src\t # long/int" %}
8757 opcode(CGF_ZOPC, CGF_ZOPC);
8758 ins_encode(z_form_rt_mem_opt(dst, src));
8759 ins_pipe(pipe_class_dummy);
8760 %}
8761
8762 // LONG unsigned
8763 // Added CmpUL for LoopPredicate.
8764 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8765 match(Set cr (CmpUL op1 op2));
8766 size(4);
8767 format %{ "CLGR $op1,$op2\t # long" %}
8768 opcode(CLGR_ZOPC);
8769 ins_encode(z_rreform(op1, op2));
8770 ins_pipe(pipe_class_dummy);
8771 %}
8772
8773 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8774 match(Set cr (CmpUL op1 con));
8775 size(6);
8776 format %{ "CLGFI $op1,$con" %}
8777 opcode(CLGFI_ZOPC);
8778 ins_encode(z_rilform_unsigned(op1, con));
8779 ins_pipe(pipe_class_dummy);
8780 %}
8781
8782 // PTR unsigned
8783
8784 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8785 match(Set cr (CmpP op1 op2));
8786 size(4);
8787 format %{ "CLGR $op1,$op2\t # ptr" %}
8788 opcode(CLGR_ZOPC);
8789 ins_encode(z_rreform(op1, op2));
8790 ins_pipe(pipe_class_dummy);
8791 %}
8792
8793 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8794 match(Set cr (CmpP op1 op2));
8795 ins_cost(DEFAULT_COST_LOW);
8796 size(4);
8797 format %{ "LTGR $op1, $op1\t # ptr" %}
8798 opcode(LTGR_ZOPC);
8799 ins_encode(z_rreform(op1, op1));
8800 ins_pipe(pipe_class_dummy);
8801 %}
8802
8803 // Don't use LTGFR which performs sign extend.
8804 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8805 match(Set cr (CmpP (DecodeN op1) op2));
8806 predicate(CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
8807 ins_cost(DEFAULT_COST_LOW);
8808 size(2);
8809 format %{ "LTR $op1, $op1\t # ptr" %}
8810 opcode(LTR_ZOPC);
8811 ins_encode(z_rrform(op1, op1));
8812 ins_pipe(pipe_class_dummy);
8813 %}
8814
8815 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8816 match(Set cr (CmpP dst (LoadP src)));
8817 predicate(n->in(2)->as_Load()->barrier_data() == 0);
8818 ins_cost(MEMORY_REF_COST);
8819 size(Z_DISP3_SIZE);
8820 format %{ "CLG $dst, $src\t # ptr" %}
8821 opcode(CLG_ZOPC, CLG_ZOPC);
8822 ins_encode(z_form_rt_mem_opt(dst, src));
8823 ins_pipe(pipe_class_dummy);
8824 %}
8825
8826 //----------Max and Min--------------------------------------------------------
8827
8828 // Max Register with Register
8829 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8830 match(Set dst (MinI src1 src2));
8831 effect(KILL cr);
8832 predicate(VM_Version::has_LoadStoreConditional());
8833 ins_cost(3 * DEFAULT_COST);
8834 // TODO: s390 port size(VARIABLE_SIZE);
8835 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8836 ins_encode %{
8837 Register Rdst = $dst$$Register;
8838 Register Rsrc1 = $src1$$Register;
8839 Register Rsrc2 = $src2$$Register;
8840
8841 if (Rsrc1 == Rsrc2) {
8842 if (Rdst != Rsrc1) {
8843 __ z_lgfr(Rdst, Rsrc1);
8844 }
8845 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8846 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8847 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8848 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8849 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8850 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8851 } else {
8852 // Rdst is disjoint from operands, move in either case.
8853 __ z_cr(Rsrc1, Rsrc2);
8854 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8855 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8856 }
8857 %}
8858 ins_pipe(pipe_class_dummy);
8859 %}
8860
8861 // Min Register with Register.
8862 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8863 match(Set dst (MinI src1 src2));
8864 effect(KILL cr);
8865 predicate(VM_Version::has_CompareBranch());
8866 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8867 // TODO: s390 port size(VARIABLE_SIZE);
8868 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8869 ins_encode %{
8870 Register Rdst = $dst$$Register;
8871 Register Rsrc1 = $src1$$Register;
8872 Register Rsrc2 = $src2$$Register;
8873 Label done;
8874
8875 if (Rsrc1 == Rsrc2) {
8876 if (Rdst != Rsrc1) {
8877 __ z_lgfr(Rdst, Rsrc1);
8878 }
8879 } else if (Rdst == Rsrc1) {
8880 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8881 __ z_lgfr(Rdst, Rsrc2);
8882 } else if (Rdst == Rsrc2) {
8883 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8884 __ z_lgfr(Rdst, Rsrc1);
8885 } else {
8886 __ z_lgfr(Rdst, Rsrc1);
8887 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8888 __ z_lgfr(Rdst, Rsrc2);
8889 }
8890 __ bind(done);
8891 %}
8892 ins_pipe(pipe_class_dummy);
8893 %}
8894
8895 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8896 match(Set dst (MinI src1 src2));
8897 effect(KILL cr);
8898 predicate(!VM_Version::has_CompareBranch());
8899 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8900 // TODO: s390 port size(VARIABLE_SIZE);
8901 format %{ "MinI $dst $src1,$src2\t MinI" %}
8902 ins_encode %{
8903 Register Rdst = $dst$$Register;
8904 Register Rsrc1 = $src1$$Register;
8905 Register Rsrc2 = $src2$$Register;
8906 Label done;
8907
8908 if (Rsrc1 == Rsrc2) {
8909 if (Rdst != Rsrc1) {
8910 __ z_lgfr(Rdst, Rsrc1);
8911 }
8912 } else if (Rdst == Rsrc1) {
8913 __ z_cr(Rsrc1, Rsrc2);
8914 __ z_brl(done);
8915 __ z_lgfr(Rdst, Rsrc2);
8916 } else if (Rdst == Rsrc2) {
8917 __ z_cr(Rsrc2, Rsrc1);
8918 __ z_brl(done);
8919 __ z_lgfr(Rdst, Rsrc1);
8920 } else {
8921 __ z_lgfr(Rdst, Rsrc1);
8922 __ z_cr(Rsrc1, Rsrc2);
8923 __ z_brl(done);
8924 __ z_lgfr(Rdst, Rsrc2);
8925 }
8926 __ bind(done);
8927 %}
8928 ins_pipe(pipe_class_dummy);
8929 %}
8930
8931 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8932 match(Set dst (MinI src1 src2));
8933 effect(KILL cr);
8934 predicate(VM_Version::has_LoadStoreConditional());
8935 ins_cost(3 * DEFAULT_COST);
8936 // TODO: s390 port size(VARIABLE_SIZE);
8937 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8938 ins_encode %{
8939 Register Rdst = $dst$$Register;
8940 Register Rsrc1 = $src1$$Register;
8941 int Isrc2 = $src2$$constant;
8942
8943 if (Rdst == Rsrc1) {
8944 __ load_const_optimized(Z_R0_scratch, Isrc2);
8945 __ z_cfi(Rsrc1, Isrc2);
8946 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8947 } else {
8948 __ load_const_optimized(Rdst, Isrc2);
8949 __ z_cfi(Rsrc1, Isrc2);
8950 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8951 }
8952 %}
8953 ins_pipe(pipe_class_dummy);
8954 %}
8955
8956 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8957 match(Set dst (MinI src1 src2));
8958 effect(KILL cr);
8959 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8960 // TODO: s390 port size(VARIABLE_SIZE);
8961 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8962 ins_encode %{
8963 Label done;
8964 if ($dst$$Register != $src1$$Register) {
8965 __ z_lgfr($dst$$Register, $src1$$Register);
8966 }
8967 __ z_cfi($src1$$Register, $src2$$constant);
8968 __ z_brl(done);
8969 __ z_lgfi($dst$$Register, $src2$$constant);
8970 __ bind(done);
8971 %}
8972 ins_pipe(pipe_class_dummy);
8973 %}
8974
8975 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8976 match(Set dst (MinI src1 src2));
8977 effect(KILL cr);
8978 predicate(VM_Version::has_LoadStoreConditional());
8979 ins_cost(3 * DEFAULT_COST);
8980 // TODO: s390 port size(VARIABLE_SIZE);
8981 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8982 ins_encode %{
8983 Register Rdst = $dst$$Register;
8984 Register Rsrc1 = $src1$$Register;
8985 int Isrc2 = $src2$$constant;
8986
8987 if (Rdst == Rsrc1) {
8988 __ load_const_optimized(Z_R0_scratch, Isrc2);
8989 __ z_chi(Rsrc1, Isrc2);
8990 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8991 } else {
8992 __ load_const_optimized(Rdst, Isrc2);
8993 __ z_chi(Rsrc1, Isrc2);
8994 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8995 }
8996 %}
8997 ins_pipe(pipe_class_dummy);
8998 %}
8999
9000 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9001 match(Set dst (MinI src1 src2));
9002 effect(KILL cr);
9003 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9004 // TODO: s390 port size(VARIABLE_SIZE);
9005 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
9006 ins_encode %{
9007 Label done;
9008 if ($dst$$Register != $src1$$Register) {
9009 __ z_lgfr($dst$$Register, $src1$$Register);
9010 }
9011 __ z_chi($src1$$Register, $src2$$constant);
9012 __ z_brl(done);
9013 __ z_lghi($dst$$Register, $src2$$constant);
9014 __ bind(done);
9015 %}
9016 ins_pipe(pipe_class_dummy);
9017 %}
9018
9019 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
9020 match(Set dst (MinI src1 src2));
9021 effect(KILL cr);
9022 predicate(VM_Version::has_CompareBranch());
9023 ins_cost(DEFAULT_COST + BRANCH_COST);
9024 // TODO: s390 port size(VARIABLE_SIZE);
9025 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
9026 ins_encode %{
9027 Label done;
9028 if ($dst$$Register != $src1$$Register) {
9029 __ z_lgfr($dst$$Register, $src1$$Register);
9030 }
9031 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
9032 __ z_lghi($dst$$Register, $src2$$constant);
9033 __ bind(done);
9034 %}
9035 ins_pipe(pipe_class_dummy);
9036 %}
9037
9038 // Max Register with Register
9039 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9040 match(Set dst (MaxI src1 src2));
9041 effect(KILL cr);
9042 predicate(VM_Version::has_LoadStoreConditional());
9043 ins_cost(3 * DEFAULT_COST);
9044 // TODO: s390 port size(VARIABLE_SIZE);
9045 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
9046 ins_encode %{
9047 Register Rdst = $dst$$Register;
9048 Register Rsrc1 = $src1$$Register;
9049 Register Rsrc2 = $src2$$Register;
9050
9051 if (Rsrc1 == Rsrc2) {
9052 if (Rdst != Rsrc1) {
9053 __ z_lgfr(Rdst, Rsrc1);
9054 }
9055 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
9056 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
9057 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
9058 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
9059 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
9060 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
9061 } else { // Rdst is disjoint from operands, move in either case.
9062 __ z_cr(Rsrc1, Rsrc2);
9063 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
9064 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9065 }
9066 %}
9067 ins_pipe(pipe_class_dummy);
9068 %}
9069
9070 // Max Register with Register
9071 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9072 match(Set dst (MaxI src1 src2));
9073 effect(KILL cr);
9074 predicate(VM_Version::has_CompareBranch());
9075 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9076 // TODO: s390 port size(VARIABLE_SIZE);
9077 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
9078 ins_encode %{
9079 Register Rdst = $dst$$Register;
9080 Register Rsrc1 = $src1$$Register;
9081 Register Rsrc2 = $src2$$Register;
9082 Label done;
9083
9084 if (Rsrc1 == Rsrc2) {
9085 if (Rdst != Rsrc1) {
9086 __ z_lgfr(Rdst, Rsrc1);
9087 }
9088 } else if (Rdst == Rsrc1) {
9089 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9090 __ z_lgfr(Rdst, Rsrc2);
9091 } else if (Rdst == Rsrc2) {
9092 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
9093 __ z_lgfr(Rdst, Rsrc1);
9094 } else {
9095 __ z_lgfr(Rdst, Rsrc1);
9096 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9097 __ z_lgfr(Rdst, Rsrc2);
9098 }
9099 __ bind(done);
9100 %}
9101 ins_pipe(pipe_class_dummy);
9102 %}
9103
9104 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9105 match(Set dst (MaxI src1 src2));
9106 effect(KILL cr);
9107 predicate(!VM_Version::has_CompareBranch());
9108 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
9109 // TODO: s390 port size(VARIABLE_SIZE);
9110 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
9111 ins_encode %{
9112 Register Rdst = $dst$$Register;
9113 Register Rsrc1 = $src1$$Register;
9114 Register Rsrc2 = $src2$$Register;
9115 Label done;
9116
9117 if (Rsrc1 == Rsrc2) {
9118 if (Rdst != Rsrc1) {
9119 __ z_lgfr(Rdst, Rsrc1);
9120 }
9121 } else if (Rdst == Rsrc1) {
9122 __ z_cr(Rsrc1, Rsrc2);
9123 __ z_brh(done);
9124 __ z_lgfr(Rdst, Rsrc2);
9125 } else if (Rdst == Rsrc2) {
9126 __ z_cr(Rsrc2, Rsrc1);
9127 __ z_brh(done);
9128 __ z_lgfr(Rdst, Rsrc1);
9129 } else {
9130 __ z_lgfr(Rdst, Rsrc1);
9131 __ z_cr(Rsrc1, Rsrc2);
9132 __ z_brh(done);
9133 __ z_lgfr(Rdst, Rsrc2);
9134 }
9135
9136 __ bind(done);
9137 %}
9138
9139 ins_pipe(pipe_class_dummy);
9140 %}
9141
9142 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9143 match(Set dst (MaxI src1 src2));
9144 effect(KILL cr);
9145 predicate(VM_Version::has_LoadStoreConditional());
9146 ins_cost(3 * DEFAULT_COST);
9147 // TODO: s390 port size(VARIABLE_SIZE);
9148 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
9149 ins_encode %{
9150 Register Rdst = $dst$$Register;
9151 Register Rsrc1 = $src1$$Register;
9152 int Isrc2 = $src2$$constant;
9153
9154 if (Rdst == Rsrc1) {
9155 __ load_const_optimized(Z_R0_scratch, Isrc2);
9156 __ z_cfi(Rsrc1, Isrc2);
9157 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9158 } else {
9159 __ load_const_optimized(Rdst, Isrc2);
9160 __ z_cfi(Rsrc1, Isrc2);
9161 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9162 }
9163 %}
9164 ins_pipe(pipe_class_dummy);
9165 %}
9166
9167 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9168 match(Set dst (MaxI src1 src2));
9169 effect(KILL cr);
9170 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9171 // TODO: s390 port size(VARIABLE_SIZE);
9172 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
9173 ins_encode %{
9174 Label done;
9175 if ($dst$$Register != $src1$$Register) {
9176 __ z_lgfr($dst$$Register, $src1$$Register);
9177 }
9178 __ z_cfi($src1$$Register, $src2$$constant);
9179 __ z_brh(done);
9180 __ z_lgfi($dst$$Register, $src2$$constant);
9181 __ bind(done);
9182 %}
9183 ins_pipe(pipe_class_dummy);
9184 %}
9185
9186 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9187 match(Set dst (MaxI src1 src2));
9188 effect(KILL cr);
9189 predicate(VM_Version::has_LoadStoreConditional());
9190 ins_cost(3 * DEFAULT_COST);
9191 // TODO: s390 port size(VARIABLE_SIZE);
9192 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
9193 ins_encode %{
9194 Register Rdst = $dst$$Register;
9195 Register Rsrc1 = $src1$$Register;
9196 int Isrc2 = $src2$$constant;
9197 if (Rdst == Rsrc1) {
9198 __ load_const_optimized(Z_R0_scratch, Isrc2);
9199 __ z_chi(Rsrc1, Isrc2);
9200 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9201 } else {
9202 __ load_const_optimized(Rdst, Isrc2);
9203 __ z_chi(Rsrc1, Isrc2);
9204 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9205 }
9206 %}
9207 ins_pipe(pipe_class_dummy);
9208 %}
9209
9210 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9211 match(Set dst (MaxI src1 src2));
9212 effect(KILL cr);
9213 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9214 // TODO: s390 port size(VARIABLE_SIZE);
9215 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
9216 ins_encode %{
9217 Label done;
9218 if ($dst$$Register != $src1$$Register) {
9219 __ z_lgfr($dst$$Register, $src1$$Register);
9220 }
9221 __ z_chi($src1$$Register, $src2$$constant);
9222 __ z_brh(done);
9223 __ z_lghi($dst$$Register, $src2$$constant);
9224 __ bind(done);
9225 %}
9226 ins_pipe(pipe_class_dummy);
9227 %}
9228
9229 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
9230 match(Set dst (MaxI src1 src2));
9231 effect(KILL cr);
9232 predicate(VM_Version::has_CompareBranch());
9233 ins_cost(DEFAULT_COST + BRANCH_COST);
9234 // TODO: s390 port size(VARIABLE_SIZE);
9235 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
9236 ins_encode %{
9237 Label done;
9238 if ($dst$$Register != $src1$$Register) {
9239 __ z_lgfr($dst$$Register, $src1$$Register);
9240 }
9241 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
9242 __ z_lghi($dst$$Register, $src2$$constant);
9243 __ bind(done);
9244 %}
9245 ins_pipe(pipe_class_dummy);
9246 %}
9247
9248 //----------Abs---------------------------------------------------------------
9249
9250 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
9251 match(Set dst (AbsI src));
9252 effect(KILL cr);
9253 ins_cost(DEFAULT_COST_LOW);
9254 // TODO: s390 port size(FIXED_SIZE);
9255 format %{ "LPR $dst, $src" %}
9256 opcode(LPR_ZOPC);
9257 ins_encode(z_rrform(dst, src));
9258 ins_pipe(pipe_class_dummy);
9259 %}
9260
9261 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
9262 match(Set dst (AbsL src));
9263 effect(KILL cr);
9264 ins_cost(DEFAULT_COST_LOW);
9265 // TODO: s390 port size(FIXED_SIZE);
9266 format %{ "LPGR $dst, $src" %}
9267 opcode(LPGR_ZOPC);
9268 ins_encode(z_rreform(dst, src));
9269 ins_pipe(pipe_class_dummy);
9270 %}
9271
9272 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9273 match(Set dst (SubI zero (AbsI src)));
9274 effect(KILL cr);
9275 ins_cost(DEFAULT_COST_LOW);
9276 // TODO: s390 port size(FIXED_SIZE);
9277 format %{ "LNR $dst, $src" %}
9278 opcode(LNR_ZOPC);
9279 ins_encode(z_rrform(dst, src));
9280 ins_pipe(pipe_class_dummy);
9281 %}
9282
9283 //----------Float Compares----------------------------------------------------
9284
9285 // Compare floating, generate condition code.
9286 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9287 match(Set cr (CmpF src1 src2));
9288 ins_cost(ALU_REG_COST);
9289 size(4);
9290 format %{ "FCMPcc $src1,$src2\t # float" %}
9291 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9292 ins_pipe(pipe_class_dummy);
9293 %}
9294
9295 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9296 match(Set cr (CmpD src1 src2));
9297 ins_cost(ALU_REG_COST);
9298 size(4);
9299 format %{ "FCMPcc $src1,$src2 \t # double" %}
9300 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9301 ins_pipe(pipe_class_dummy);
9302 %}
9303
9304 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9305 match(Set cr (CmpF src1 (LoadF src2)));
9306 ins_cost(ALU_MEMORY_COST);
9307 size(6);
9308 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9309 opcode(CEB_ZOPC);
9310 ins_encode(z_form_rt_memFP(src1, src2));
9311 ins_pipe(pipe_class_dummy);
9312 %}
9313
9314 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9315 match(Set cr (CmpD src1 (LoadD src2)));
9316 ins_cost(ALU_MEMORY_COST);
9317 size(6);
9318 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9319 opcode(CDB_ZOPC);
9320 ins_encode(z_form_rt_memFP(src1, src2));
9321 ins_pipe(pipe_class_dummy);
9322 %}
9323
9324 // Compare floating, generate condition code
9325 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9326 match(Set cr (CmpF src1 src2));
9327 ins_cost(DEFAULT_COST);
9328 size(4);
9329 format %{ "LTEBR $src1,$src1\t # float" %}
9330 opcode(LTEBR_ZOPC);
9331 ins_encode(z_rreform(src1, src1));
9332 ins_pipe(pipe_class_dummy);
9333 %}
9334
9335 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9336 match(Set cr (CmpD src1 src2));
9337 ins_cost(DEFAULT_COST);
9338 size(4);
9339 format %{ "LTDBR $src1,$src1 \t # double" %}
9340 opcode(LTDBR_ZOPC);
9341 ins_encode(z_rreform(src1, src1));
9342 ins_pipe(pipe_class_dummy);
9343 %}
9344
9345 // Compare floating, generate -1,0,1
9346 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9347 match(Set dst (CmpF3 src1 src2));
9348 effect(KILL cr);
9349 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9350 size(24);
9351 format %{ "CmpF3 $dst,$src1,$src2" %}
9352 ins_encode %{
9353 // compare registers
9354 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9355 // Convert condition code into -1,0,1, where
9356 // -1 means unordered or less
9357 // 0 means equal
9358 // 1 means greater.
9359 if (VM_Version::has_LoadStoreConditional()) {
9360 Register one = Z_R0_scratch;
9361 Register minus_one = Z_R1_scratch;
9362 __ z_lghi(minus_one, -1);
9363 __ z_lghi(one, 1);
9364 __ z_lghi( $dst$$Register, 0);
9365 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9366 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9367 } else {
9368 Label done;
9369 __ clear_reg($dst$$Register, true, false);
9370 __ z_bre(done);
9371 __ z_lhi($dst$$Register, 1);
9372 __ z_brh(done);
9373 __ z_lhi($dst$$Register, -1);
9374 __ bind(done);
9375 }
9376 %}
9377 ins_pipe(pipe_class_dummy);
9378 %}
9379
9380 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9381 match(Set dst (CmpD3 src1 src2));
9382 effect(KILL cr);
9383 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9384 size(24);
9385 format %{ "CmpD3 $dst,$src1,$src2" %}
9386 ins_encode %{
9387 // compare registers
9388 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9389 // Convert condition code into -1,0,1, where
9390 // -1 means unordered or less
9391 // 0 means equal
9392 // 1 means greater.
9393 if (VM_Version::has_LoadStoreConditional()) {
9394 Register one = Z_R0_scratch;
9395 Register minus_one = Z_R1_scratch;
9396 __ z_lghi(minus_one, -1);
9397 __ z_lghi(one, 1);
9398 __ z_lghi( $dst$$Register, 0);
9399 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9400 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9401 } else {
9402 Label done;
9403 // indicate unused result
9404 (void) __ clear_reg($dst$$Register, true, false);
9405 __ z_bre(done);
9406 __ z_lhi($dst$$Register, 1);
9407 __ z_brh(done);
9408 __ z_lhi($dst$$Register, -1);
9409 __ bind(done);
9410 }
9411 %}
9412 ins_pipe(pipe_class_dummy);
9413 %}
9414
9415 //----------Branches---------------------------------------------------------
9416 // Jump
9417
9418 // Direct Branch.
9419 instruct branch(label labl) %{
9420 match(Goto);
9421 effect(USE labl);
9422 ins_cost(BRANCH_COST);
9423 size(4);
9424 format %{ "BRU $labl" %}
9425 ins_encode(z_enc_bru(labl));
9426 ins_pipe(pipe_class_dummy);
9427 // If set to 1 this indicates that the current instruction is a
9428 // short variant of a long branch. This avoids using this
9429 // instruction in first-pass matching. It will then only be used in
9430 // the `Shorten_branches' pass.
9431 ins_short_branch(1);
9432 %}
9433
9434 // Direct Branch.
9435 instruct branchFar(label labl) %{
9436 match(Goto);
9437 effect(USE labl);
9438 ins_cost(BRANCH_COST);
9439 size(6);
9440 format %{ "BRUL $labl" %}
9441 ins_encode(z_enc_brul(labl));
9442 ins_pipe(pipe_class_dummy);
9443 // This is not a short variant of a branch, but the long variant.
9444 ins_short_branch(0);
9445 %}
9446
9447 // Conditional Near Branch
9448 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9449 // Same match rule as `branchConFar'.
9450 match(If cmp cr);
9451 effect(USE lbl);
9452 ins_cost(BRANCH_COST);
9453 size(4);
9454 format %{ "branch_con_short,$cmp $lbl" %}
9455 ins_encode(z_enc_branch_con_short(cmp, lbl));
9456 ins_pipe(pipe_class_dummy);
9457 // If set to 1 this indicates that the current instruction is a
9458 // short variant of a long branch. This avoids using this
9459 // instruction in first-pass matching. It will then only be used in
9460 // the `Shorten_branches' pass.
9461 ins_short_branch(1);
9462 %}
9463
9464 // This is for cases when the z/Architecture conditional branch instruction
9465 // does not reach far enough. So we emit a far branch here, which is
9466 // more expensive.
9467 //
9468 // Conditional Far Branch
9469 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9470 // Same match rule as `branchCon'.
9471 match(If cmp cr);
9472 effect(USE cr, USE lbl);
9473 // Make more expensive to prefer compare_and_branch over separate instructions.
9474 ins_cost(2 * BRANCH_COST);
9475 size(6);
9476 format %{ "branch_con_far,$cmp $lbl" %}
9477 ins_encode(z_enc_branch_con_far(cmp, lbl));
9478 ins_pipe(pipe_class_dummy);
9479 // This is not a short variant of a branch, but the long variant..
9480 ins_short_branch(0);
9481 %}
9482
9483 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9484 match(CountedLoopEnd cmp cr);
9485 effect(USE labl);
9486 ins_cost(BRANCH_COST);
9487 size(4);
9488 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9489 ins_encode(z_enc_branch_con_short(cmp, labl));
9490 ins_pipe(pipe_class_dummy);
9491 // If set to 1 this indicates that the current instruction is a
9492 // short variant of a long branch. This avoids using this
9493 // instruction in first-pass matching. It will then only be used in
9494 // the `Shorten_branches' pass.
9495 ins_short_branch(1);
9496 %}
9497
9498 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9499 match(CountedLoopEnd cmp cr);
9500 effect(USE labl);
9501 ins_cost(BRANCH_COST);
9502 size(6);
9503 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9504 ins_encode(z_enc_branch_con_far(cmp, labl));
9505 ins_pipe(pipe_class_dummy);
9506 // This is not a short variant of a branch, but the long variant.
9507 ins_short_branch(0);
9508 %}
9509
9510 //----------Compare and Branch (short distance)------------------------------
9511
9512 // INT REG operands for loop counter processing.
9513 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9514 match(CountedLoopEnd boolnode (CmpI src1 src2));
9515 effect(USE labl, KILL cr);
9516 predicate(VM_Version::has_CompareBranch());
9517 ins_cost(BRANCH_COST);
9518 // TODO: s390 port size(FIXED_SIZE);
9519 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9520 opcode(CRJ_ZOPC);
9521 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9522 ins_pipe(pipe_class_dummy);
9523 ins_short_branch(1);
9524 %}
9525
9526 // INT REG operands.
9527 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9528 match(If boolnode (CmpI src1 src2));
9529 effect(USE labl, KILL cr);
9530 predicate(VM_Version::has_CompareBranch());
9531 ins_cost(BRANCH_COST);
9532 // TODO: s390 port size(FIXED_SIZE);
9533 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9534 opcode(CRJ_ZOPC);
9535 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9536 ins_pipe(pipe_class_dummy);
9537 ins_short_branch(1);
9538 %}
9539
9540 // Unsigned INT REG operands
9541 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9542 match(If boolnode (CmpU src1 src2));
9543 effect(USE labl, KILL cr);
9544 predicate(VM_Version::has_CompareBranch());
9545 ins_cost(BRANCH_COST);
9546 // TODO: s390 port size(FIXED_SIZE);
9547 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9548 opcode(CLRJ_ZOPC);
9549 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9550 ins_pipe(pipe_class_dummy);
9551 ins_short_branch(1);
9552 %}
9553
9554 // LONG REG operands
9555 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9556 match(If boolnode (CmpL src1 src2));
9557 effect(USE labl, KILL cr);
9558 predicate(VM_Version::has_CompareBranch());
9559 ins_cost(BRANCH_COST);
9560 // TODO: s390 port size(FIXED_SIZE);
9561 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9562 opcode(CGRJ_ZOPC);
9563 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9564 ins_pipe(pipe_class_dummy);
9565 ins_short_branch(1);
9566 %}
9567
9568 // PTR REG operands
9569
9570 // Separate rules for regular and narrow oops. ADLC can't recognize
9571 // rules with polymorphic operands to be sisters -> shorten_branches
9572 // will not shorten.
9573
9574 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9575 match(If boolnode (CmpP src1 src2));
9576 effect(USE labl, KILL cr);
9577 predicate(VM_Version::has_CompareBranch());
9578 ins_cost(BRANCH_COST);
9579 // TODO: s390 port size(FIXED_SIZE);
9580 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9581 opcode(CLGRJ_ZOPC);
9582 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9583 ins_pipe(pipe_class_dummy);
9584 ins_short_branch(1);
9585 %}
9586
9587 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9588 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9589 effect(USE labl, KILL cr);
9590 predicate(VM_Version::has_CompareBranch());
9591 ins_cost(BRANCH_COST);
9592 // TODO: s390 port size(FIXED_SIZE);
9593 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9594 opcode(CLGRJ_ZOPC);
9595 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9596 ins_pipe(pipe_class_dummy);
9597 ins_short_branch(1);
9598 %}
9599
9600 // INT REG/IMM operands for loop counter processing
9601 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9602 match(CountedLoopEnd boolnode (CmpI src1 src2));
9603 effect(USE labl, KILL cr);
9604 predicate(VM_Version::has_CompareBranch());
9605 ins_cost(BRANCH_COST);
9606 // TODO: s390 port size(FIXED_SIZE);
9607 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9608 opcode(CIJ_ZOPC);
9609 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9610 ins_pipe(pipe_class_dummy);
9611 ins_short_branch(1);
9612 %}
9613
9614 // INT REG/IMM operands
9615 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9616 match(If boolnode (CmpI src1 src2));
9617 effect(USE labl, KILL cr);
9618 predicate(VM_Version::has_CompareBranch());
9619 ins_cost(BRANCH_COST);
9620 // TODO: s390 port size(FIXED_SIZE);
9621 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9622 opcode(CIJ_ZOPC);
9623 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9624 ins_pipe(pipe_class_dummy);
9625 ins_short_branch(1);
9626 %}
9627
9628 // INT REG/IMM operands
9629 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9630 match(If boolnode (CmpU src1 src2));
9631 effect(USE labl, KILL cr);
9632 predicate(VM_Version::has_CompareBranch());
9633 ins_cost(BRANCH_COST);
9634 // TODO: s390 port size(FIXED_SIZE);
9635 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9636 opcode(CLIJ_ZOPC);
9637 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9638 ins_pipe(pipe_class_dummy);
9639 ins_short_branch(1);
9640 %}
9641
9642 // LONG REG/IMM operands
9643 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9644 match(If boolnode (CmpL src1 src2));
9645 effect(USE labl, KILL cr);
9646 predicate(VM_Version::has_CompareBranch());
9647 ins_cost(BRANCH_COST);
9648 // TODO: s390 port size(FIXED_SIZE);
9649 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9650 opcode(CGIJ_ZOPC);
9651 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9652 ins_pipe(pipe_class_dummy);
9653 ins_short_branch(1);
9654 %}
9655
9656 // PTR REG-imm operands
9657
9658 // Separate rules for regular and narrow oops. ADLC can't recognize
9659 // rules with polymorphic operands to be sisters -> shorten_branches
9660 // will not shorten.
9661
9662 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9663 match(If boolnode (CmpP src1 src2));
9664 effect(USE labl, KILL cr);
9665 predicate(VM_Version::has_CompareBranch());
9666 ins_cost(BRANCH_COST);
9667 // TODO: s390 port size(FIXED_SIZE);
9668 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9669 opcode(CLGIJ_ZOPC);
9670 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9671 ins_pipe(pipe_class_dummy);
9672 ins_short_branch(1);
9673 %}
9674
9675 // Compare against zero only, do not mix N and P oops (encode/decode required).
9676 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9677 match(If boolnode (CmpP (DecodeN src1) src2));
9678 effect(USE labl, KILL cr);
9679 predicate(VM_Version::has_CompareBranch());
9680 ins_cost(BRANCH_COST);
9681 // TODO: s390 port size(FIXED_SIZE);
9682 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9683 opcode(CLGIJ_ZOPC);
9684 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9685 ins_pipe(pipe_class_dummy);
9686 ins_short_branch(1);
9687 %}
9688
9689 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9690 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9691 effect(USE labl, KILL cr);
9692 predicate(VM_Version::has_CompareBranch());
9693 ins_cost(BRANCH_COST);
9694 // TODO: s390 port size(FIXED_SIZE);
9695 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9696 opcode(CLGIJ_ZOPC);
9697 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9698 ins_pipe(pipe_class_dummy);
9699 ins_short_branch(1);
9700 %}
9701
9702
9703 //----------Compare and Branch (far distance)------------------------------
9704
9705 // INT REG operands for loop counter processing
9706 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9707 match(CountedLoopEnd boolnode (CmpI src1 src2));
9708 effect(USE labl, KILL cr);
9709 predicate(VM_Version::has_CompareBranch());
9710 ins_cost(BRANCH_COST+DEFAULT_COST);
9711 // TODO: s390 port size(FIXED_SIZE);
9712 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9713 opcode(CR_ZOPC, BRCL_ZOPC);
9714 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9715 ins_pipe(pipe_class_dummy);
9716 ins_short_branch(0);
9717 %}
9718
9719 // INT REG operands
9720 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9721 match(If boolnode (CmpI src1 src2));
9722 effect(USE labl, KILL cr);
9723 predicate(VM_Version::has_CompareBranch());
9724 ins_cost(BRANCH_COST+DEFAULT_COST);
9725 // TODO: s390 port size(FIXED_SIZE);
9726 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9727 opcode(CR_ZOPC, BRCL_ZOPC);
9728 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9729 ins_pipe(pipe_class_dummy);
9730 ins_short_branch(0);
9731 %}
9732
9733 // INT REG operands
9734 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9735 match(If boolnode (CmpU src1 src2));
9736 effect(USE labl, KILL cr);
9737 predicate(VM_Version::has_CompareBranch());
9738 ins_cost(BRANCH_COST+DEFAULT_COST);
9739 // TODO: s390 port size(FIXED_SIZE);
9740 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9741 opcode(CLR_ZOPC, BRCL_ZOPC);
9742 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9743 ins_pipe(pipe_class_dummy);
9744 ins_short_branch(0);
9745 %}
9746
9747 // LONG REG operands
9748 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9749 match(If boolnode (CmpL src1 src2));
9750 effect(USE labl, KILL cr);
9751 predicate(VM_Version::has_CompareBranch());
9752 ins_cost(BRANCH_COST+DEFAULT_COST);
9753 // TODO: s390 port size(FIXED_SIZE);
9754 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9755 opcode(CGR_ZOPC, BRCL_ZOPC);
9756 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9757 ins_pipe(pipe_class_dummy);
9758 ins_short_branch(0);
9759 %}
9760
9761 // PTR REG operands
9762
9763 // Separate rules for regular and narrow oops. ADLC can't recognize
9764 // rules with polymorphic operands to be sisters -> shorten_branches
9765 // will not shorten.
9766
9767 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9768 match(If boolnode (CmpP src1 src2));
9769 effect(USE labl, KILL cr);
9770 predicate(VM_Version::has_CompareBranch());
9771 ins_cost(BRANCH_COST+DEFAULT_COST);
9772 // TODO: s390 port size(FIXED_SIZE);
9773 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9774 opcode(CLGR_ZOPC, BRCL_ZOPC);
9775 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9776 ins_pipe(pipe_class_dummy);
9777 ins_short_branch(0);
9778 %}
9779
9780 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9781 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9782 effect(USE labl, KILL cr);
9783 predicate(VM_Version::has_CompareBranch());
9784 ins_cost(BRANCH_COST+DEFAULT_COST);
9785 // TODO: s390 port size(FIXED_SIZE);
9786 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9787 opcode(CLGR_ZOPC, BRCL_ZOPC);
9788 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9789 ins_pipe(pipe_class_dummy);
9790 ins_short_branch(0);
9791 %}
9792
9793 // INT REG/IMM operands for loop counter processing
9794 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9795 match(CountedLoopEnd boolnode (CmpI src1 src2));
9796 effect(USE labl, KILL cr);
9797 predicate(VM_Version::has_CompareBranch());
9798 ins_cost(BRANCH_COST+DEFAULT_COST);
9799 // TODO: s390 port size(FIXED_SIZE);
9800 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9801 opcode(CHI_ZOPC, BRCL_ZOPC);
9802 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9803 ins_pipe(pipe_class_dummy);
9804 ins_short_branch(0);
9805 %}
9806
9807 // INT REG/IMM operands
9808 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9809 match(If boolnode (CmpI src1 src2));
9810 effect(USE labl, KILL cr);
9811 predicate(VM_Version::has_CompareBranch());
9812 ins_cost(BRANCH_COST+DEFAULT_COST);
9813 // TODO: s390 port size(FIXED_SIZE);
9814 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9815 opcode(CHI_ZOPC, BRCL_ZOPC);
9816 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9817 ins_pipe(pipe_class_dummy);
9818 ins_short_branch(0);
9819 %}
9820
9821 // INT REG/IMM operands
9822 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9823 match(If boolnode (CmpU src1 src2));
9824 effect(USE labl, KILL cr);
9825 predicate(VM_Version::has_CompareBranch());
9826 ins_cost(BRANCH_COST+DEFAULT_COST);
9827 // TODO: s390 port size(FIXED_SIZE);
9828 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9829 opcode(CLFI_ZOPC, BRCL_ZOPC);
9830 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9831 ins_pipe(pipe_class_dummy);
9832 ins_short_branch(0);
9833 %}
9834
9835 // LONG REG/IMM operands
9836 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9837 match(If boolnode (CmpL src1 src2));
9838 effect(USE labl, KILL cr);
9839 predicate(VM_Version::has_CompareBranch());
9840 ins_cost(BRANCH_COST+DEFAULT_COST);
9841 // TODO: s390 port size(FIXED_SIZE);
9842 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9843 opcode(CGHI_ZOPC, BRCL_ZOPC);
9844 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9845 ins_pipe(pipe_class_dummy);
9846 ins_short_branch(0);
9847 %}
9848
9849 // PTR REG-imm operands
9850
9851 // Separate rules for regular and narrow oops. ADLC can't recognize
9852 // rules with polymorphic operands to be sisters -> shorten_branches
9853 // will not shorten.
9854
9855 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9856 match(If boolnode (CmpP src1 src2));
9857 effect(USE labl, KILL cr);
9858 predicate(VM_Version::has_CompareBranch());
9859 ins_cost(BRANCH_COST+DEFAULT_COST);
9860 // TODO: s390 port size(FIXED_SIZE);
9861 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9862 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9863 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9864 ins_pipe(pipe_class_dummy);
9865 ins_short_branch(0);
9866 %}
9867
9868 // Compare against zero only, do not mix N and P oops (encode/decode required).
9869 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9870 match(If boolnode (CmpP (DecodeN src1) src2));
9871 effect(USE labl, KILL cr);
9872 predicate(VM_Version::has_CompareBranch());
9873 ins_cost(BRANCH_COST+DEFAULT_COST);
9874 // TODO: s390 port size(FIXED_SIZE);
9875 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9876 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9877 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9878 ins_pipe(pipe_class_dummy);
9879 ins_short_branch(0);
9880 %}
9881
9882 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9883 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9884 effect(USE labl, KILL cr);
9885 predicate(VM_Version::has_CompareBranch());
9886 ins_cost(BRANCH_COST+DEFAULT_COST);
9887 // TODO: s390 port size(FIXED_SIZE);
9888 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9889 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9890 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9891 ins_pipe(pipe_class_dummy);
9892 ins_short_branch(0);
9893 %}
9894
9895 // ============================================================================
9896 // Long Compare
9897
9898 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9899 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9900 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9901 // are collapsed internally in the ADLC's dfa-gen code. The match for
9902 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9903 // foo match ends up with the wrong leaf. One fix is to not match both
9904 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9905 // both forms beat the trinary form of long-compare and both are very useful
9906 // on platforms which have few registers.
9907
9908 // Manifest a CmpL3 result in an integer register. Very painful.
9909 // This is the test to avoid.
9910 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9911 match(Set dst (CmpL3 src1 src2));
9912 effect(KILL cr);
9913 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9914 size(24);
9915 format %{ "CmpL3 $dst,$src1,$src2" %}
9916 ins_encode %{
9917 Label done;
9918 // compare registers
9919 __ z_cgr($src1$$Register, $src2$$Register);
9920 // Convert condition code into -1,0,1, where
9921 // -1 means less
9922 // 0 means equal
9923 // 1 means greater.
9924 if (VM_Version::has_LoadStoreConditional()) {
9925 Register one = Z_R0_scratch;
9926 Register minus_one = Z_R1_scratch;
9927 __ z_lghi(minus_one, -1);
9928 __ z_lghi(one, 1);
9929 __ z_lghi( $dst$$Register, 0);
9930 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9931 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9932 } else {
9933 __ clear_reg($dst$$Register, true, false);
9934 __ z_bre(done);
9935 __ z_lhi($dst$$Register, 1);
9936 __ z_brh(done);
9937 __ z_lhi($dst$$Register, -1);
9938 }
9939 __ bind(done);
9940 %}
9941 ins_pipe(pipe_class_dummy);
9942 %}
9943
9944 // ============================================================================
9945 // Safepoint Instruction
9946
9947 instruct safePoint() %{
9948 match(SafePoint);
9949 predicate(false);
9950 // TODO: s390 port size(FIXED_SIZE);
9951 format %{ "UNIMPLEMENTED Safepoint_ " %}
9952 ins_encode(enc_unimplemented());
9953 ins_pipe(pipe_class_dummy);
9954 %}
9955
9956 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9957 match(SafePoint poll);
9958 effect(USE poll, KILL cr); // R0 is killed, too.
9959 // TODO: s390 port size(FIXED_SIZE);
9960 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9961 ins_encode %{
9962 // Mark the code position where the load from the safepoint
9963 // polling page was emitted as relocInfo::poll_type.
9964 __ relocate(relocInfo::poll_type);
9965 __ load_from_polling_page($poll$$Register);
9966 %}
9967 ins_pipe(pipe_class_dummy);
9968 %}
9969
9970 // ============================================================================
9971
9972 // Call Instructions
9973
9974 // Call Java Static Instruction
9975 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9976 match(CallStaticJava);
9977 effect(USE meth);
9978 ins_cost(CALL_COST);
9979 // TODO: s390 port size(VARIABLE_SIZE);
9980 format %{ "CALL,static dynTOC $meth; ==> " %}
9981 ins_encode( z_enc_java_static_call(meth) );
9982 ins_pipe(pipe_class_dummy);
9983 ins_alignment(2);
9984 %}
9985
9986 // Call Java Dynamic Instruction
9987 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9988 match(CallDynamicJava);
9989 effect(USE meth);
9990 ins_cost(CALL_COST);
9991 // TODO: s390 port size(VARIABLE_SIZE);
9992 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9993 ins_encode(z_enc_java_dynamic_call(meth));
9994 ins_pipe(pipe_class_dummy);
9995 ins_alignment(2);
9996 %}
9997
9998 // Call Runtime Instruction
9999 instruct CallRuntimeDirect(method meth) %{
10000 match(CallRuntime);
10001 effect(USE meth);
10002 ins_cost(CALL_COST);
10003 // TODO: s390 port size(VARIABLE_SIZE);
10004 ins_num_consts(1);
10005 ins_alignment(2);
10006 format %{ "CALL,runtime" %}
10007 ins_encode( z_enc_java_to_runtime_call(meth) );
10008 ins_pipe(pipe_class_dummy);
10009 %}
10010
10011 // Call runtime without safepoint - same as CallRuntime
10012 instruct CallLeafDirect(method meth) %{
10013 match(CallLeaf);
10014 effect(USE meth);
10015 ins_cost(CALL_COST);
10016 // TODO: s390 port size(VARIABLE_SIZE);
10017 ins_num_consts(1);
10018 ins_alignment(2);
10019 format %{ "CALL,runtime leaf $meth" %}
10020 ins_encode( z_enc_java_to_runtime_call(meth) );
10021 ins_pipe(pipe_class_dummy);
10022 %}
10023
10024 // Call runtime without safepoint - same as CallLeaf
10025 instruct CallLeafNoFPDirect(method meth) %{
10026 match(CallLeafNoFP);
10027 effect(USE meth);
10028 ins_cost(CALL_COST);
10029 // TODO: s390 port size(VARIABLE_SIZE);
10030 ins_num_consts(1);
10031 format %{ "CALL,runtime leaf nofp $meth" %}
10032 ins_encode( z_enc_java_to_runtime_call(meth) );
10033 ins_pipe(pipe_class_dummy);
10034 ins_alignment(2);
10035 %}
10036
10037 // Tail Call; Jump from runtime stub to Java code.
10038 // Also known as an 'interprocedural jump'.
10039 // Target of jump will eventually return to caller.
10040 // TailJump below removes the return address.
10041 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{
10042 match(TailCall jump_target method_ptr);
10043 ins_cost(CALL_COST);
10044 size(2);
10045 format %{ "Jmp $jump_target\t # $method_ptr holds method" %}
10046 ins_encode %{ __ z_br($jump_target$$Register); %}
10047 ins_pipe(pipe_class_dummy);
10048 %}
10049
10050 // Return Instruction
10051 instruct Ret() %{
10052 match(Return);
10053 size(2);
10054 format %{ "BR(Z_R14) // branch to link register" %}
10055 ins_encode %{ __ z_br(Z_R14); %}
10056 ins_pipe(pipe_class_dummy);
10057 %}
10058
10059 // Tail Jump; remove the return address; jump to target.
10060 // TailCall above leaves the return address around.
10061 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10062 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10063 // "restore" before this instruction (in Epilogue), we need to materialize it
10064 // in %i0.
10065 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
10066 match(TailJump jump_target ex_oop);
10067 ins_cost(CALL_COST);
10068 size(8);
10069 format %{ "TailJump $jump_target" %}
10070 ins_encode %{
10071 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
10072 __ z_br($jump_target$$Register);
10073 %}
10074 ins_pipe(pipe_class_dummy);
10075 %}
10076
10077 // Forward exception.
10078 instruct ForwardExceptionjmp() %{
10079 match(ForwardException);
10080 ins_cost(CALL_COST);
10081 format %{ "Jmp forward_exception_stub" %}
10082 ins_encode %{
10083 __ set_inst_mark();
10084 __ load_const_optimized(Z_R1_scratch, (address)StubRoutines::forward_exception_entry());
10085 __ z_br(Z_R1_scratch);
10086 __ clear_inst_mark();
10087 %}
10088 ins_pipe(pipe_class_dummy);
10089 %}
10090
10091 // Create exception oop: created by stack-crawling runtime code.
10092 // Created exception is now available to this handler, and is setup
10093 // just prior to jumping to this handler. No code emitted.
10094 instruct CreateException(rarg1RegP ex_oop) %{
10095 match(Set ex_oop (CreateEx));
10096 ins_cost(0);
10097 size(0);
10098 format %{ "# exception oop; no code emitted" %}
10099 ins_encode(/*empty*/);
10100 ins_pipe(pipe_class_dummy);
10101 %}
10102
10103 // Rethrow exception: The exception oop will come in the first
10104 // argument position. Then JUMP (not call) to the rethrow stub code.
10105 instruct RethrowException() %{
10106 match(Rethrow);
10107 ins_cost(CALL_COST);
10108 // TODO: s390 port size(VARIABLE_SIZE);
10109 format %{ "Jmp rethrow_stub" %}
10110 ins_encode %{
10111 __ set_inst_mark();
10112 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
10113 __ z_br(Z_R1_scratch);
10114 __ clear_inst_mark();
10115 %}
10116 ins_pipe(pipe_class_dummy);
10117 %}
10118
10119 // Die now.
10120 instruct ShouldNotReachHere() %{
10121 match(Halt);
10122 ins_cost(CALL_COST);
10123 format %{ "ILLTRAP; ShouldNotReachHere" %}
10124 ins_encode %{
10125 if (is_reachable()) {
10126 const char* str = __ code_string(_halt_reason);
10127 __ stop(str);
10128 }
10129 %}
10130 ins_pipe(pipe_class_dummy);
10131 %}
10132
10133 // ============================================================================
10134 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10135 // array for an instance of the superklass. Set a hidden internal cache on a
10136 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10137 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10138 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
10139 rarg4RegP scratch1, rarg5RegP scratch2) %{
10140 match(Set index (PartialSubtypeCheck sub super));
10141 predicate(!UseSecondarySupersTable);
10142 effect(KILL pcc, KILL scratch1, KILL scratch2);
10143 ins_cost(20 * DEFAULT_COST); // slightly larger than the next version
10144 // TODO: s390 port size(FIXED_SIZE);
10145 format %{ " CALL PartialSubtypeCheck\n" %}
10146 ins_encode %{
10147 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
10148 __ load_const_optimized(Z_ARG4, stub_address);
10149 __ z_basr(Z_R14, Z_ARG4);
10150 %}
10151 ins_pipe(pipe_class_dummy);
10152 %}
10153
10154 // Two versions of partialSubtypeCheck, both used when we need to
10155 // search for a super class in the secondary supers array. The first
10156 // is used when we don't know _a priori_ the class being searched
10157 // for. The second, far more common, is used when we do know: this is
10158 // used for instanceof, checkcast, and any case where C2 can determine
10159 // it by constant propagation.
10160 instruct partialSubtypeCheckVarSuper(rarg2RegP sub, rarg3RegP super,
10161 r11TempRegP result,
10162 rarg1RegP temp1, rarg4RegP temp2, rarg5RegP temp3, r10TempRegP temp4,
10163 flagsReg pcc) %{
10164 match(Set result (PartialSubtypeCheck sub super));
10165 predicate(UseSecondarySupersTable);
10166 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10167 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10168 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10169 ins_encode %{
10170 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register,
10171 $temp1$$Register, $temp2$$Register, $temp3$$Register, $temp4$$Register,
10172 $result$$Register);
10173 %}
10174 ins_pipe(pipe_class_dummy);
10175 %}
10176
10177
10178 instruct partialSubtypeCheckConstSuper(rarg2RegP sub, rarg1RegP super, immP super_con,
10179 r11TempRegP result, rarg5RegP temp1, rarg4RegP temp2,
10180 rarg3RegP temp3, r10TempRegP temp4, flagsReg pcc) %{
10181 match(Set result (PartialSubtypeCheck sub (Binary super super_con)));
10182 predicate(UseSecondarySupersTable);
10183 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10184 ins_cost(5 * DEFAULT_COST); // smaller than the next version
10185 format %{ "partialSubtypeCheck $result, $sub, $super, $super_con" %}
10186
10187 ins_encode %{
10188 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10189 if (InlineSecondarySupersTest) {
10190 __ lookup_secondary_supers_table_const($sub$$Register, $super$$Register,
10191 $temp1$$Register, $temp2$$Register, $temp3$$Register,
10192 $temp4$$Register, $result$$Register, super_klass_slot);
10193 } else {
10194 AddressLiteral stub_address(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot));
10195 __ load_const_optimized(Z_ARG4, stub_address);
10196 __ z_basr(Z_R14, Z_ARG4);
10197 }
10198
10199 %}
10200
10201 ins_pipe(pipe_class_dummy);
10202 %}
10203
10204 // ============================================================================
10205 // inlined locking and unlocking
10206
10207 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10208 match(Set pcc (FastLock oop box));
10209 effect(TEMP tmp1, TEMP tmp2);
10210 ins_cost(100);
10211 // TODO: s390 port size(VARIABLE_SIZE);
10212 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10213 ins_encode %{
10214 __ fast_lock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10215 // If locking was successful, cc should indicate 'EQ'.
10216 // The compiler generates a branch to the runtime call to
10217 // _complete_monitor_locking_Java for the case where cc is 'NE'.
10218 %}
10219 ins_pipe(pipe_class_dummy);
10220 %}
10221
10222 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10223 match(Set pcc (FastUnlock oop box));
10224 effect(TEMP tmp1, TEMP tmp2);
10225 ins_cost(100);
10226 // TODO: s390 port size(FIXED_SIZE);
10227 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10228 ins_encode %{
10229 __ fast_unlock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10230 // If unlocking was successful, cc should indicate 'EQ'.
10231 // The compiler generates a branch to the runtime call to
10232 // _complete_monitor_unlocking_Java for the case where cc is 'NE'.
10233 %}
10234 ins_pipe(pipe_class_dummy);
10235 %}
10236
10237 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
10238 match(Set dummy (ClearArray cnt base));
10239 effect(KILL cr);
10240 ins_cost(100);
10241 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
10242 format %{ "ClearArrayConst $cnt,$base" %}
10243 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
10244 ins_pipe(pipe_class_dummy);
10245 %}
10246
10247 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10248 match(Set dummy (ClearArray cnt base));
10249 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10250 ins_cost(200);
10251 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
10252 format %{ "ClearArrayConstBig $cnt,$base" %}
10253 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
10254 ins_pipe(pipe_class_dummy);
10255 %}
10256
10257 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10258 match(Set dummy (ClearArray cnt base));
10259 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10260 ins_cost(300);
10261 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
10262 format %{ "ClearArrayVar $cnt,$base" %}
10263 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
10264 ins_pipe(pipe_class_dummy);
10265 %}
10266
10267 // ============================================================================
10268 // CompactStrings
10269
10270 // String equals
10271 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10272 match(Set result (StrEquals (Binary str1 str2) cnt));
10273 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10274 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10275 ins_cost(300);
10276 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10277 ins_encode %{
10278 __ array_equals(false, $str1$$Register, $str2$$Register,
10279 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
10280 $result$$Register, true /* byte */);
10281 %}
10282 ins_pipe(pipe_class_dummy);
10283 %}
10284
10285 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
10286 match(Set result (StrEquals (Binary str1 str2) cnt));
10287 effect(KILL cr); // R0 is killed, too.
10288 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10289 ins_cost(100);
10290 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10291 ins_encode %{
10292 const int cnt_imm = $cnt$$constant;
10293 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
10294 __ z_lhi($result$$Register, 1);
10295 if (cnt_imm) {
10296 if (VM_Version::has_LoadStoreConditional()) {
10297 __ z_lhi(Z_R0_scratch, 0);
10298 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10299 } else {
10300 Label Lskip;
10301 __ z_bre(Lskip);
10302 __ clear_reg($result$$Register);
10303 __ bind(Lskip);
10304 }
10305 }
10306 %}
10307 ins_pipe(pipe_class_dummy);
10308 %}
10309
10310 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
10311 match(Set result (StrEquals (Binary str1 str2) cnt));
10312 effect(KILL cr); // R0 is killed, too.
10313 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
10314 ins_cost(100);
10315 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10316 ins_encode %{
10317 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10318 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10319 __ z_lhi($result$$Register, 1);
10320 if (cnt_imm) {
10321 if (VM_Version::has_LoadStoreConditional()) {
10322 __ z_lhi(Z_R0_scratch, 0);
10323 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10324 } else {
10325 Label Lskip;
10326 __ z_bre(Lskip);
10327 __ clear_reg($result$$Register);
10328 __ bind(Lskip);
10329 }
10330 }
10331 %}
10332 ins_pipe(pipe_class_dummy);
10333 %}
10334
10335 // Array equals
10336 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10337 match(Set result (AryEq ary1 ary2));
10338 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10339 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10340 ins_cost(300);
10341 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10342 ins_encode %{
10343 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10344 noreg, $oddReg$$Register, $evenReg$$Register,
10345 $result$$Register, true /* byte */);
10346 %}
10347 ins_pipe(pipe_class_dummy);
10348 %}
10349
10350 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10351 match(Set result (AryEq ary1 ary2));
10352 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10353 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10354 ins_cost(300);
10355 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10356 ins_encode %{
10357 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10358 noreg, $oddReg$$Register, $evenReg$$Register,
10359 $result$$Register, false /* byte */);
10360 %}
10361 ins_pipe(pipe_class_dummy);
10362 %}
10363
10364 // String CompareTo
10365 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10366 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10367 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10368 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10369 ins_cost(300);
10370 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10371 ins_encode %{
10372 __ string_compare($str1$$Register, $str2$$Register,
10373 $cnt1$$Register, $cnt2$$Register,
10374 $oddReg$$Register, $evenReg$$Register,
10375 $result$$Register, StrIntrinsicNode::LL);
10376 %}
10377 ins_pipe(pipe_class_dummy);
10378 %}
10379
10380 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10381 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10382 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10383 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10384 ins_cost(300);
10385 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10386 ins_encode %{
10387 __ string_compare($str1$$Register, $str2$$Register,
10388 $cnt1$$Register, $cnt2$$Register,
10389 $oddReg$$Register, $evenReg$$Register,
10390 $result$$Register, StrIntrinsicNode::UU);
10391 %}
10392 ins_pipe(pipe_class_dummy);
10393 %}
10394
10395 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10396 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10397 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10398 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10399 ins_cost(300);
10400 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10401 ins_encode %{
10402 __ string_compare($str1$$Register, $str2$$Register,
10403 $cnt1$$Register, $cnt2$$Register,
10404 $oddReg$$Register, $evenReg$$Register,
10405 $result$$Register, StrIntrinsicNode::LU);
10406 %}
10407 ins_pipe(pipe_class_dummy);
10408 %}
10409
10410 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10411 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10412 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10413 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10414 ins_cost(300);
10415 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10416 ins_encode %{
10417 __ string_compare($str2$$Register, $str1$$Register,
10418 $cnt2$$Register, $cnt1$$Register,
10419 $oddReg$$Register, $evenReg$$Register,
10420 $result$$Register, StrIntrinsicNode::UL);
10421 %}
10422 ins_pipe(pipe_class_dummy);
10423 %}
10424
10425 // String IndexOfChar
10426 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10427 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10428 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10429 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
10430 ins_cost(200);
10431 format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10432 ins_encode %{
10433 __ string_indexof_char($result$$Register,
10434 $haystack$$Register, $haycnt$$Register,
10435 $ch$$Register, 0 /* unused, ch is in register */,
10436 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10437 %}
10438 ins_pipe(pipe_class_dummy);
10439 %}
10440
10441 instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10442 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10443 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10444 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
10445 ins_cost(200);
10446 format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10447 ins_encode %{
10448 __ string_indexof_char($result$$Register,
10449 $haystack$$Register, $haycnt$$Register,
10450 $ch$$Register, 0 /* unused, ch is in register */,
10451 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10452 %}
10453 ins_pipe(pipe_class_dummy);
10454 %}
10455
10456 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10457 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10458 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10459 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10460 ins_cost(200);
10461 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10462 ins_encode %{
10463 immPOper *needleOper = (immPOper *)$needle;
10464 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10465 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10466 jchar chr;
10467 #ifdef VM_LITTLE_ENDIAN
10468 Unimplemented();
10469 #else
10470 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10471 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10472 #endif
10473 __ string_indexof_char($result$$Register,
10474 $haystack$$Register, $haycnt$$Register,
10475 noreg, chr,
10476 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10477 %}
10478 ins_pipe(pipe_class_dummy);
10479 %}
10480
10481 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10482 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10483 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10484 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10485 ins_cost(200);
10486 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10487 ins_encode %{
10488 immPOper *needleOper = (immPOper *)$needle;
10489 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10490 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10491 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10492 __ string_indexof_char($result$$Register,
10493 $haystack$$Register, $haycnt$$Register,
10494 noreg, chr,
10495 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10496 %}
10497 ins_pipe(pipe_class_dummy);
10498 %}
10499
10500 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10501 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10502 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10503 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10504 ins_cost(200);
10505 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10506 ins_encode %{
10507 immPOper *needleOper = (immPOper *)$needle;
10508 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10509 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10510 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10511 __ string_indexof_char($result$$Register,
10512 $haystack$$Register, $haycnt$$Register,
10513 noreg, chr,
10514 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10515 %}
10516 ins_pipe(pipe_class_dummy);
10517 %}
10518
10519 // String IndexOf
10520 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10521 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10522 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10523 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10524 ins_cost(250);
10525 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10526 ins_encode %{
10527 __ string_indexof($result$$Register,
10528 $haystack$$Register, $haycnt$$Register,
10529 $needle$$Register, noreg, $needlecntImm$$constant,
10530 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10531 %}
10532 ins_pipe(pipe_class_dummy);
10533 %}
10534
10535 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10536 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10537 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10538 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10539 ins_cost(250);
10540 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10541 ins_encode %{
10542 __ string_indexof($result$$Register,
10543 $haystack$$Register, $haycnt$$Register,
10544 $needle$$Register, noreg, $needlecntImm$$constant,
10545 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10546 %}
10547 ins_pipe(pipe_class_dummy);
10548 %}
10549
10550 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10551 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10552 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10553 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10554 ins_cost(250);
10555 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10556 ins_encode %{
10557 __ string_indexof($result$$Register,
10558 $haystack$$Register, $haycnt$$Register,
10559 $needle$$Register, noreg, $needlecntImm$$constant,
10560 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10561 %}
10562 ins_pipe(pipe_class_dummy);
10563 %}
10564
10565 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10566 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10567 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10568 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10569 ins_cost(300);
10570 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10571 ins_encode %{
10572 __ string_indexof($result$$Register,
10573 $haystack$$Register, $haycnt$$Register,
10574 $needle$$Register, $needlecnt$$Register, 0,
10575 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10576 %}
10577 ins_pipe(pipe_class_dummy);
10578 %}
10579
10580 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10581 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10582 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10583 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10584 ins_cost(300);
10585 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10586 ins_encode %{
10587 __ string_indexof($result$$Register,
10588 $haystack$$Register, $haycnt$$Register,
10589 $needle$$Register, $needlecnt$$Register, 0,
10590 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10591 %}
10592 ins_pipe(pipe_class_dummy);
10593 %}
10594
10595 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10596 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10597 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10598 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10599 ins_cost(300);
10600 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10601 ins_encode %{
10602 __ string_indexof($result$$Register,
10603 $haystack$$Register, $haycnt$$Register,
10604 $needle$$Register, $needlecnt$$Register, 0,
10605 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10606 %}
10607 ins_pipe(pipe_class_dummy);
10608 %}
10609
10610 // char[] to byte[] compression
10611 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18,
10612 v19TempReg v19, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10613 match(Set result (StrCompressedCopy src (Binary dst len)));
10614 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19, TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10615 ins_cost(300);
10616 format %{ "String Compress $src->$dst($len) -> $result" %}
10617 ins_encode %{
10618 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10619 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10620 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10621 $v23$$VectorRegister);
10622 %}
10623 ins_pipe(pipe_class_dummy);
10624 %}
10625
10626 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10627 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10628 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10629 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10630 // predicate(VM_Version::has_ETF2Enhancements());
10631 // ins_cost(300);
10632 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10633 // ins_encode %{
10634 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10635 // %}
10636 // ins_pipe(pipe_class_dummy);
10637 //%}
10638
10639 // byte[] to char[] inflation
10640 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10641 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10642 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10643 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10644 ins_cost(300);
10645 format %{ "String Inflate $src->$dst($len)" %}
10646 ins_encode %{
10647 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, $v20$$VectorRegister,
10648 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10649 $v25$$VectorRegister);
10650 %}
10651 ins_pipe(pipe_class_dummy);
10652 %}
10653
10654 // byte[] to char[] inflation
10655 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10656 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10657 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10658 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10659 ins_cost(300);
10660 format %{ "String Inflate (constLen) $src->$dst($len)" %}
10661 ins_encode %{
10662 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant , $v20$$VectorRegister,
10663 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10664 $v25$$VectorRegister);
10665 %}
10666 ins_pipe(pipe_class_dummy);
10667 %}
10668
10669 // StringCoding.java intrinsics
10670 instruct count_positives(iRegP ary1, iRegI len, iRegI result, iRegI tmp, flagsReg cr) %{
10671 match(Set result (CountPositives ary1 len));
10672 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10673 ins_cost(300);
10674 format %{ "count positives byte[] $ary1($len) -> $result" %}
10675 ins_encode %{
10676 __ count_positives($result$$Register, $ary1$$Register, $len$$Register, $tmp$$Register);
10677 %}
10678 ins_pipe(pipe_class_dummy);
10679 %}
10680
10681 // encode char[] to byte[] in ISO_8859_1
10682 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10683 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10684 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
10685 match(Set result (EncodeISOArray src (Binary dst len)));
10686 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10687 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10688 ins_cost(300);
10689 format %{ "Encode iso array $src->$dst($len) -> $result" %}
10690 ins_encode %{
10691 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10692 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10693 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10694 $v23$$VectorRegister);
10695 %}
10696 ins_pipe(pipe_class_dummy);
10697 %}
10698
10699 // encode char[] to byte[] in ASCII
10700 instruct encode_ascii_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10701 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10702 predicate(((EncodeISOArrayNode*)n)->is_ascii());
10703 match(Set result (EncodeISOArray src (Binary dst len)));
10704 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10705 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10706 ins_cost(300);
10707 format %{ "Encode ascii array $src->$dst($len) -> $result" %}
10708 ins_encode %{
10709 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10710 $tmp$$Register, true, true, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10711 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10712 $v23$$VectorRegister);
10713 %}
10714 ins_pipe(pipe_class_dummy);
10715 %}
10716
10717
10718 //----------PEEPHOLE RULES-----------------------------------------------------
10719 // These must follow all instruction definitions as they use the names
10720 // defined in the instructions definitions.
10721 //
10722 // peepmatch (root_instr_name [preceeding_instruction]*);
10723 //
10724 // peepconstraint %{
10725 // (instruction_number.operand_name relational_op instruction_number.operand_name
10726 // [, ...]);
10727 // // instruction numbers are zero-based using left to right order in peepmatch
10728 //
10729 // peepreplace (instr_name([instruction_number.operand_name]*));
10730 // // provide an instruction_number.operand_name for each operand that appears
10731 // // in the replacement instruction's match rule
10732 //
10733 // ---------VM FLAGS---------------------------------------------------------
10734 //
10735 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10736 //
10737 // Each peephole rule is given an identifying number starting with zero and
10738 // increasing by one in the order seen by the parser. An individual peephole
10739 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10740 // on the command-line.
10741 //
10742 // ---------CURRENT LIMITATIONS----------------------------------------------
10743 //
10744 // Only match adjacent instructions in same basic block
10745 // Only equality constraints
10746 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10747 // Only one replacement instruction
10748 //
10749 // ---------EXAMPLE----------------------------------------------------------
10750 //
10751 // // pertinent parts of existing instructions in architecture description
10752 // instruct movI(eRegI dst, eRegI src) %{
10753 // match(Set dst (CopyI src));
10754 // %}
10755 //
10756 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10757 // match(Set dst (AddI dst src));
10758 // effect(KILL cr);
10759 // %}
10760 //
10761 // // Change (inc mov) to lea
10762 // peephole %{
10763 // // increment preceded by register-register move
10764 // peepmatch (incI_eReg movI);
10765 // // require that the destination register of the increment
10766 // // match the destination register of the move
10767 // peepconstraint (0.dst == 1.dst);
10768 // // construct a replacement instruction that sets
10769 // // the destination to (move's source register + one)
10770 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10771 // %}
10772 //
10773 // Implementation no longer uses movX instructions since
10774 // machine-independent system no longer uses CopyX nodes.
10775 //
10776 // peephole %{
10777 // peepmatch (incI_eReg movI);
10778 // peepconstraint (0.dst == 1.dst);
10779 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10780 // %}
10781 //
10782 // peephole %{
10783 // peepmatch (decI_eReg movI);
10784 // peepconstraint (0.dst == 1.dst);
10785 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10786 // %}
10787 //
10788 // peephole %{
10789 // peepmatch (addI_eReg_imm movI);
10790 // peepconstraint (0.dst == 1.dst);
10791 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10792 // %}
10793 //
10794 // peephole %{
10795 // peepmatch (addP_eReg_imm movP);
10796 // peepconstraint (0.dst == 1.dst);
10797 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10798 // %}
10799
10800
10801 // This peephole rule does not work, probably because ADLC can't handle two effects:
10802 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10803 // condense a load from memory and subsequent test for zero
10804 // into a single, more efficient ICM instruction.
10805 // peephole %{
10806 // peepmatch (compI_iReg_imm0 loadI);
10807 // peepconstraint (1.dst == 0.op1);
10808 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10809 // %}
10810
10811 // // Change load of spilled value to only a spill
10812 // instruct storeI(memory mem, eRegI src) %{
10813 // match(Set mem (StoreI mem src));
10814 // %}
10815 //
10816 // instruct loadI(eRegI dst, memory mem) %{
10817 // match(Set dst (LoadI mem));
10818 // %}
10819 //
10820 peephole %{
10821 peepmatch (loadI storeI);
10822 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10823 peepreplace (storeI(1.mem 1.mem 1.src));
10824 %}
10825
10826 peephole %{
10827 peepmatch (loadL storeL);
10828 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10829 peepreplace (storeL(1.mem 1.mem 1.src));
10830 %}
10831
10832 peephole %{
10833 peepmatch (loadP storeP);
10834 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10835 peepreplace (storeP(1.dst 1.dst 1.src));
10836 %}
10837
10838 //----------SUPERWORD RULES---------------------------------------------------
10839
10840 // Expand rules for special cases
10841
10842 instruct expand_storeF(stackSlotF mem, regF src) %{
10843 // No match rule, false predicate, for expand only.
10844 effect(DEF mem, USE src);
10845 predicate(false);
10846 ins_cost(MEMORY_REF_COST);
10847 // TODO: s390 port size(FIXED_SIZE);
10848 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10849 opcode(STE_ZOPC, STE_ZOPC);
10850 ins_encode(z_form_rt_mem(src, mem));
10851 ins_pipe(pipe_class_dummy);
10852 %}
10853
10854 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10855 // No match rule, false predicate, for expand only.
10856 effect(DEF dst, USE mem);
10857 predicate(false);
10858 ins_cost(MEMORY_REF_COST);
10859 // TODO: s390 port size(FIXED_SIZE);
10860 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10861 opcode(LLGF_ZOPC, LLGF_ZOPC);
10862 ins_encode(z_form_rt_mem(dst, mem));
10863 ins_pipe(pipe_class_dummy);
10864 %}
10865
10866 // Replicate scalar int to packed int values (8 Bytes)
10867 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10868 // Dummy match rule, false predicate, for expand only.
10869 match(Set dst (ConvI2L src));
10870 predicate(false);
10871 ins_cost(DEFAULT_COST);
10872 // TODO: s390 port size(FIXED_SIZE);
10873 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10874 ins_encode %{
10875 if ($dst$$Register == $src$$Register) {
10876 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10877 __ z_ogr($dst$$Register, Z_R0_scratch);
10878 } else {
10879 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10880 __ z_ogr( $dst$$Register, $src$$Register);
10881 }
10882 %}
10883 ins_pipe(pipe_class_dummy);
10884 %}
10885
10886 // Replication
10887
10888 // Exploit rotate_then_insert, if available
10889 // Replicate scalar byte to packed byte values (8 Bytes).
10890 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10891 match(Set dst (Replicate src));
10892 effect(KILL cr);
10893 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10894 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10895 ins_encode %{
10896 if ($dst$$Register != $src$$Register) {
10897 __ z_lgr($dst$$Register, $src$$Register);
10898 }
10899 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10900 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10901 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10902 %}
10903 ins_pipe(pipe_class_dummy);
10904 %}
10905
10906 // Replicate scalar byte to packed byte values (8 Bytes).
10907 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10908 match(Set dst (Replicate src));
10909 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10910 ins_should_rematerialize(true);
10911 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10912 ins_encode %{
10913 int64_t Isrc8 = $src$$constant & 0x000000ff;
10914 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10915 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10916 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10917
10918 __ z_llilf($dst$$Register, Isrc32);
10919 __ z_iihf($dst$$Register, Isrc32);
10920 %}
10921 ins_pipe(pipe_class_dummy);
10922 %}
10923
10924 // Replicate scalar byte to packed byte values (8 Bytes).
10925 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10926 match(Set dst (Replicate src));
10927 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10928 ins_should_rematerialize(true);
10929 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10930 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10931 ins_pipe(pipe_class_dummy);
10932 %}
10933
10934 // Replicate scalar byte to packed byte values (8 Bytes).
10935 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10936 match(Set dst (Replicate src));
10937 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10938 ins_should_rematerialize(true);
10939 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10940 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10941 ins_pipe(pipe_class_dummy);
10942 %}
10943
10944 // Exploit rotate_then_insert, if available
10945 // Replicate scalar short to packed short values (8 Bytes).
10946 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10947 match(Set dst (Replicate src));
10948 effect(KILL cr);
10949 predicate((n->as_Vector()->length() == 4) && Matcher::vector_element_basic_type(n) == T_SHORT);
10950 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10951 ins_encode %{
10952 if ($dst$$Register != $src$$Register) {
10953 __ z_lgr($dst$$Register, $src$$Register);
10954 }
10955 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10956 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10957 %}
10958 ins_pipe(pipe_class_dummy);
10959 %}
10960
10961 // Replicate scalar short to packed short values (8 Bytes).
10962 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10963 match(Set dst (Replicate src));
10964 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10965 ins_should_rematerialize(true);
10966 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10967 ins_encode %{
10968 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10969 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10970 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10971 ") should be handled by other match rules.", $src$$constant);
10972
10973 __ z_llilf($dst$$Register, Isrc32);
10974 __ z_iihf($dst$$Register, Isrc32);
10975 %}
10976 ins_pipe(pipe_class_dummy);
10977 %}
10978
10979 // Replicate scalar short to packed short values (8 Bytes).
10980 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10981 match(Set dst (Replicate src));
10982 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10983 ins_should_rematerialize(true);
10984 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10985 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10986 ins_pipe(pipe_class_dummy);
10987 %}
10988
10989 // Replicate scalar short to packed short values (8 Bytes).
10990 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10991 match(Set dst (Replicate src));
10992 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10993 ins_should_rematerialize(true);
10994 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10995 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10996 ins_pipe(pipe_class_dummy);
10997 %}
10998
10999 instruct repl8S_reg_Ex(vecX dst, iRegI src) %{
11000 match(Set dst (Replicate src));
11001 predicate(n->as_Vector()->length() == 8 &&
11002 Matcher::vector_element_basic_type(n) == T_SHORT);
11003
11004 size(12);
11005 ins_encode %{
11006 __ z_vlvgh($dst$$VectorRegister, $src$$Register, 0);
11007 __ z_vreph($dst$$VectorRegister, $dst$$VectorRegister, 0);
11008 %}
11009 ins_pipe(pipe_class_dummy);
11010 %}
11011
11012 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
11013 match(Set dst (Replicate src));
11014 predicate(n->as_Vector()->length() == 8 &&
11015 Matcher::vector_element_basic_type(n) == T_SHORT);
11016
11017 format %{ "VONE $dst, $src \t// replicate8S" %}
11018 size(6);
11019 ins_encode %{
11020 __ z_vone($dst$$VectorRegister);
11021 %}
11022 ins_pipe(pipe_class_dummy);
11023 %}
11024
11025 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
11026 match(Set dst (Replicate zero));
11027 predicate(n->as_Vector()->length() == 8 &&
11028 Matcher::vector_element_basic_type(n) == T_SHORT);
11029
11030 format %{ "VZERO $dst, $zero \t// replicate8S" %}
11031 size(6);
11032 ins_encode %{
11033 __ z_vzero($dst$$VectorRegister);
11034 %}
11035 ins_pipe(pipe_class_dummy);
11036 %}
11037
11038 // Exploit rotate_then_insert, if available.
11039 // Replicate scalar int to packed int values (8 Bytes).
11040 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
11041 match(Set dst (Replicate src));
11042 effect(KILL cr);
11043 predicate((n->as_Vector()->length() == 2) && Matcher::vector_element_basic_type(n) == T_INT);
11044 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
11045 ins_encode %{
11046 if ($dst$$Register != $src$$Register) {
11047 __ z_lgr($dst$$Register, $src$$Register);
11048 }
11049 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
11050 %}
11051 ins_pipe(pipe_class_dummy);
11052 %}
11053
11054 // Replicate scalar int to packed int values (8 Bytes).
11055 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
11056 match(Set dst (Replicate src));
11057 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11058 ins_should_rematerialize(true);
11059 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
11060 ins_encode %{
11061 int64_t Isrc32 = $src$$constant;
11062 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
11063
11064 __ z_llilf($dst$$Register, Isrc32);
11065 __ z_iihf($dst$$Register, Isrc32);
11066 %}
11067 ins_pipe(pipe_class_dummy);
11068 %}
11069
11070 // Replicate scalar int to packed int values (8 Bytes).
11071 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
11072 match(Set dst (Replicate src));
11073 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11074 ins_should_rematerialize(true);
11075 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
11076 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11077 ins_pipe(pipe_class_dummy);
11078 %}
11079
11080 // Replicate scalar int to packed int values (8 Bytes).
11081 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
11082 match(Set dst (Replicate src));
11083 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11084 ins_should_rematerialize(true);
11085 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
11086 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
11087 ins_pipe(pipe_class_dummy);
11088 %}
11089
11090 instruct repl4I_reg_Ex(vecX dst, iRegI src) %{
11091 match(Set dst (Replicate src));
11092 predicate(n->as_Vector()->length() == 4 &&
11093 Matcher::vector_element_basic_type(n) == T_INT);
11094
11095 size(12);
11096 ins_encode %{
11097 __ z_vlvgf($dst$$VectorRegister, $src$$Register, 0);
11098 __ z_vrepf($dst$$VectorRegister, $dst$$VectorRegister, 0);
11099 %}
11100 ins_pipe(pipe_class_dummy);
11101 %}
11102
11103 instruct repl4I_immI0(vecX dst, immI_0 zero) %{
11104 match(Set dst (Replicate zero));
11105 predicate(n->as_Vector()->length() == 4 &&
11106 Matcher::vector_element_basic_type(n) == T_INT);
11107
11108 format %{ "VZERO $dst, $zero \t// replicate4I" %}
11109 size(6);
11110 ins_encode %{
11111 __ z_vzero($dst$$VectorRegister);
11112 %}
11113 ins_pipe(pipe_class_dummy);
11114 %}
11115
11116 instruct repl4I_immIminus1(vecX dst, immI_minus1 src) %{
11117 match(Set dst (Replicate src));
11118 predicate(n->as_Vector()->length() == 4 &&
11119 Matcher::vector_element_basic_type(n) == T_INT);
11120
11121 format %{ "VONE $dst, $dst, $dst \t// replicate4I" %}
11122 size(6);
11123 ins_encode %{
11124 __ z_vone($dst$$VectorRegister);
11125 %}
11126 ins_pipe(pipe_class_dummy);
11127 %}
11128
11129 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
11130 match(Set dst (Replicate src));
11131 effect(KILL cr);
11132 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11133 Matcher::vector_element_basic_type(n) == T_FLOAT);
11134 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
11135 expand %{
11136 stackSlotF tmp;
11137 iRegL tmp2;
11138 expand_storeF(tmp, src);
11139 expand_LoadLogical_I2L(tmp2, tmp);
11140 expand_Repl2I_reg(dst, tmp2);
11141 %}
11142 %}
11143
11144 // Replicate scalar float to packed float values in GREG (8 Bytes).
11145 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
11146 match(Set dst (Replicate src));
11147 effect(KILL cr);
11148 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11149 Matcher::vector_element_basic_type(n) == T_FLOAT);
11150 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
11151 ins_encode %{
11152 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
11153 __ z_lgdr($dst$$Register, $src$$FloatRegister);
11154
11155 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
11156 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
11157 __ z_ogr($dst$$Register, Z_R0_scratch);
11158 %}
11159 ins_pipe(pipe_class_dummy);
11160 %}
11161
11162 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
11163 instruct Repl2F_imm(iRegL dst, immF src) %{
11164 match(Set dst (Replicate src));
11165 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11166 ins_should_rematerialize(true);
11167 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
11168 ins_encode %{
11169 union {
11170 int Isrc32;
11171 float Fsrc32;
11172 };
11173 Fsrc32 = $src$$constant;
11174 __ z_llilf($dst$$Register, Isrc32);
11175 __ z_iihf($dst$$Register, Isrc32);
11176 %}
11177 ins_pipe(pipe_class_dummy);
11178 %}
11179
11180 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
11181 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
11182 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
11183 match(Set dst (Replicate src));
11184 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11185 ins_should_rematerialize(true);
11186 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
11187 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11188 ins_pipe(pipe_class_dummy);
11189 %}
11190
11191 instruct repl4F_reg_Ex(vecX dst, regF src) %{
11192 match(Set dst (Replicate src));
11193 predicate(n->as_Vector()->length() == 4 &&
11194 Matcher::vector_element_basic_type(n) == T_FLOAT);
11195
11196 format %{ "VREP $dst, $src \t// replicate4F" %}
11197 size(6);
11198
11199 ins_encode %{
11200 __ z_vrepf($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11201 %}
11202 ins_pipe(pipe_class_dummy);
11203 %}
11204
11205 instruct repl4F_immF0(vecX dst, immFp0 zero) %{
11206 match(Set dst (Replicate zero));
11207 predicate(n->as_Vector()->length() == 4 &&
11208 Matcher::vector_element_basic_type(n) == T_FLOAT);
11209
11210 format %{ "VZERO $dst, $zero \t// replicate4F" %}
11211 size(6);
11212 ins_encode %{
11213 __ z_vzero($dst$$VectorRegister);
11214 %}
11215 ins_pipe(pipe_class_dummy);
11216 %}
11217
11218 instruct repl2D_reg_Ex(vecX dst, regD src) %{
11219 match(Set dst (Replicate src));
11220 predicate(n->as_Vector()->length() == 2 &&
11221 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11222
11223 format %{ "VREP $dst, $src \t// replicate2D" %}
11224 size(6);
11225
11226 ins_encode %{
11227 __ z_vrepg($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11228 %}
11229 ins_pipe(pipe_class_dummy);
11230 %}
11231
11232 instruct repl2D_immD0(vecX dst, immDp0 zero) %{
11233 match(Set dst (Replicate zero));
11234 predicate(n->as_Vector()->length() == 2 &&
11235 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11236
11237 format %{ "VZERO $dst, $zero \t// replicate2D" %}
11238 size(6);
11239 ins_encode %{
11240 __ z_vzero($dst$$VectorRegister);
11241 %}
11242 ins_pipe(pipe_class_dummy);
11243 %}
11244
11245 instruct repl16B_reg_Ex(vecX dst, iRegI src) %{
11246 match(Set dst (Replicate src));
11247 predicate(n->as_Vector()->length() == 16 &&
11248 Matcher::vector_element_basic_type(n) == T_BYTE);
11249
11250 size(12);
11251 ins_encode %{
11252 __ z_vlvgb($dst$$VectorRegister, $src$$Register, 0);
11253 __ z_vrepb($dst$$VectorRegister, $dst$$VectorRegister, 0);
11254 %}
11255 ins_pipe(pipe_class_dummy);
11256 %}
11257
11258 instruct repl16B_immIminus1(vecX dst, immI_minus1 src) %{
11259 match(Set dst (Replicate src));
11260 predicate(n->as_Vector()->length() == 16 &&
11261 Matcher::vector_element_basic_type(n) == T_BYTE);
11262
11263 format %{ "VONE $dst, $src \t// replicate16B" %}
11264 size(6);
11265 ins_encode %{
11266 __ z_vone($dst$$VectorRegister);
11267 %}
11268 ins_pipe(pipe_class_dummy);
11269 %}
11270
11271 instruct repl16B_immI0(vecX dst, immI_0 zero) %{
11272 match(Set dst (Replicate zero));
11273 predicate(n->as_Vector()->length() == 16 &&
11274 Matcher::vector_element_basic_type(n) == T_BYTE);
11275
11276 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11277 size(6);
11278 ins_encode %{
11279 __ z_vzero($dst$$VectorRegister);
11280 %}
11281 ins_pipe(pipe_class_dummy);
11282 %}
11283
11284 instruct repl2L_reg_Ex(vecX dst, iRegL src) %{
11285 match(Set dst (Replicate src));
11286 predicate(n->as_Vector()->length() == 2 &&
11287 Matcher::vector_element_basic_type(n) == T_LONG);
11288
11289 size(12);
11290 ins_encode %{
11291 __ z_vlvgg($dst$$VectorRegister, $src$$Register, 0);
11292 __ z_vrepg($dst$$VectorRegister, $dst$$VectorRegister, 0);
11293 %}
11294 ins_pipe(pipe_class_dummy);
11295 %}
11296
11297 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
11298 match(Set dst (Replicate src));
11299 predicate(n->as_Vector()->length() == 2 &&
11300 Matcher::vector_element_basic_type(n) == T_LONG);
11301
11302 format %{ "VONE $dst, $src \t// replicate2L" %}
11303 size(6);
11304 ins_encode %{
11305 __ z_vone($dst$$VectorRegister);
11306 %}
11307 ins_pipe(pipe_class_dummy);
11308 %}
11309
11310 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
11311 match(Set dst (Replicate zero));
11312 predicate(n->as_Vector()->length() == 2 &&
11313 Matcher::vector_element_basic_type(n) == T_LONG);
11314
11315 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11316 size(6);
11317 ins_encode %{
11318 __ z_vzero($dst$$VectorRegister);
11319 %}
11320 ins_pipe(pipe_class_dummy);
11321 %}
11322
11323
11324 // Load/Store vector
11325
11326 // Store Aligned Packed Byte register to memory (8 Bytes).
11327 instruct storeA8B(memory mem, iRegL src) %{
11328 match(Set mem (StoreVector mem src));
11329 predicate(n->as_StoreVector()->memory_size() == 8);
11330 ins_cost(MEMORY_REF_COST);
11331 // TODO: s390 port size(VARIABLE_SIZE);
11332 format %{ "STG $src,$mem\t # ST(packed8B)" %}
11333 opcode(STG_ZOPC, STG_ZOPC);
11334 ins_encode(z_form_rt_mem_opt(src, mem));
11335 ins_pipe(pipe_class_dummy);
11336 %}
11337
11338 // Store Packed Byte long register to memory
11339 instruct storeV16(memoryRX mem, vecX src) %{
11340 predicate(n->as_StoreVector()->memory_size() == 16);
11341 match(Set mem (StoreVector mem src));
11342 ins_cost(MEMORY_REF_COST);
11343
11344 format %{ "VST $mem, $src \t// store 16-byte Vector" %}
11345 size(6);
11346 ins_encode %{
11347 __ z_vst($src$$VectorRegister,
11348 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11349 %}
11350 ins_pipe(pipe_class_dummy);
11351 %}
11352
11353 instruct loadV8(iRegL dst, memory mem) %{
11354 match(Set dst (LoadVector mem));
11355 predicate(n->as_LoadVector()->memory_size() == 8);
11356 ins_cost(MEMORY_REF_COST);
11357 // TODO: s390 port size(VARIABLE_SIZE);
11358 format %{ "LG $dst,$mem\t # L(packed8B)" %}
11359 opcode(LG_ZOPC, LG_ZOPC);
11360 ins_encode(z_form_rt_mem_opt(dst, mem));
11361 ins_pipe(pipe_class_dummy);
11362 %}
11363
11364 // Load Aligned Packed Byte
11365 instruct loadV16(vecX dst, memoryRX mem) %{
11366 predicate(n->as_LoadVector()->memory_size() == 16);
11367 match(Set dst (LoadVector mem));
11368 ins_cost(MEMORY_REF_COST);
11369
11370 format %{ "VL $dst, $mem \t// load 16-byte Vector" %}
11371 size(6);
11372 ins_encode %{
11373 __ z_vl($dst$$VectorRegister,
11374 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11375 %}
11376 ins_pipe(pipe_class_dummy);
11377 %}
11378
11379 // Reinterpret: only one vector size used
11380 instruct reinterpret(iRegL dst) %{
11381 match(Set dst (VectorReinterpret dst));
11382 ins_cost(0);
11383 format %{ "reinterpret $dst" %}
11384 ins_encode( /*empty*/ );
11385 ins_pipe(pipe_class_dummy);
11386 %}
11387
11388 instruct reinterpretX(vecX dst) %{
11389 match(Set dst (VectorReinterpret dst));
11390 ins_cost(0);
11391 format %{ "reinterpret $dst" %}
11392 ins_encode( /*empty*/ );
11393 ins_pipe(pipe_class_dummy);
11394 %}
11395
11396 //----------Vector Arithmetic Instructions--------------------------------------
11397
11398 // Vector Addition Instructions
11399
11400 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
11401 match(Set dst (AddVB src1 src2));
11402 predicate(n->as_Vector()->length() == 16);
11403 format %{ "VAB $dst,$src1,$src2\t// add packed16B" %}
11404 size(6);
11405 ins_encode %{
11406 __ z_vab($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11407 %}
11408 ins_pipe(pipe_class_dummy);
11409 %}
11410
11411 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
11412 match(Set dst (AddVS src1 src2));
11413 predicate(n->as_Vector()->length() == 8);
11414 format %{ "VAH $dst,$src1,$src2\t// add packed8S" %}
11415 size(6);
11416 ins_encode %{
11417 __ z_vah($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11418 %}
11419 ins_pipe(pipe_class_dummy);
11420 %}
11421
11422 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
11423 match(Set dst (AddVI src1 src2));
11424 predicate(n->as_Vector()->length() == 4);
11425 format %{ "VAF $dst,$src1,$src2\t// add packed4I" %}
11426 size(6);
11427 ins_encode %{
11428 __ z_vaf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11429 %}
11430 ins_pipe(pipe_class_dummy);
11431 %}
11432
11433 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
11434 match(Set dst (AddVL src1 src2));
11435 predicate(n->as_Vector()->length() == 2);
11436 format %{ "VAG $dst,$src1,$src2\t// add packed2L" %}
11437 size(6);
11438 ins_encode %{
11439 __ z_vag($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11440 %}
11441 ins_pipe(pipe_class_dummy);
11442 %}
11443
11444 instruct vmul16B_reg(vecX dst, vecX src1, vecX src2) %{
11445 match(Set dst (MulVB src1 src2));
11446 predicate(n->as_Vector()->length() == 16);
11447 format %{ "VMLB $dst,$src1,$src2\t// mul packed16B" %}
11448 size(6);
11449 ins_encode %{
11450 __ z_vmlb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11451 %}
11452 ins_pipe(pipe_class_dummy);
11453 %}
11454
11455 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2) %{
11456 match(Set dst (MulVS src1 src2));
11457 predicate(n->as_Vector()->length() == 8);
11458 format %{ "VMLHW $dst,$src1,$src2\t// mul packed8S" %}
11459 size(6);
11460 ins_encode %{
11461 __ z_vmlhw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11462 %}
11463 ins_pipe(pipe_class_dummy);
11464 %}
11465
11466 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
11467 match(Set dst (MulVI src1 src2));
11468 predicate(n->as_Vector()->length() == 4);
11469 format %{ "VMLF $dst,$src1,$src2\t// mul packed4I" %}
11470 size(6);
11471 ins_encode %{
11472 __ z_vmlf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11473 %}
11474 ins_pipe(pipe_class_dummy);
11475 %}
11476
11477 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
11478 match(Set dst (SubVB src1 src2));
11479 predicate(n->as_Vector()->length() == 16);
11480 format %{ "VSB $dst,$src1,$src2\t// sub packed16B" %}
11481 size(6);
11482 ins_encode %{
11483 __ z_vsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11484 %}
11485 ins_pipe(pipe_class_dummy);
11486 %}
11487
11488 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
11489 match(Set dst (SubVS src1 src2));
11490 predicate(n->as_Vector()->length() == 8);
11491 format %{ "VSH $dst,$src1,$src2\t// sub packed8S" %}
11492 size(6);
11493 ins_encode %{
11494 __ z_vsh($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11495 %}
11496 ins_pipe(pipe_class_dummy);
11497 %}
11498
11499 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
11500 match(Set dst (SubVI src1 src2));
11501 predicate(n->as_Vector()->length() == 4);
11502 format %{ "VSF $dst,$src1,$src2\t// sub packed4I" %}
11503 size(6);
11504 ins_encode %{
11505 __ z_vsf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11506 %}
11507 ins_pipe(pipe_class_dummy);
11508 %}
11509
11510 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
11511 match(Set dst (SubVL src1 src2));
11512 predicate(n->as_Vector()->length() == 2);
11513 format %{ "VSG $dst,$src1,$src2\t// sub packed2L" %}
11514 size(6);
11515 ins_encode %{
11516 __ z_vsg($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11517 %}
11518 ins_pipe(pipe_class_dummy);
11519 %}
11520
11521 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
11522 match(Set dst (AddVF src1 src2));
11523 predicate(n->as_Vector()->length() == 4);
11524 format %{ "VFASB $dst,$src1,$src2\t// add packed4F" %}
11525 size(6);
11526 ins_encode %{
11527 __ z_vfasb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11528 %}
11529 ins_pipe(pipe_class_dummy);
11530 %}
11531
11532 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
11533 match(Set dst (AddVD src1 src2));
11534 predicate(n->as_Vector()->length() == 2);
11535 format %{ "VFADB $dst,$src1,$src2\t// add packed2D" %}
11536 size(6);
11537 ins_encode %{
11538 __ z_vfadb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11539 %}
11540 ins_pipe(pipe_class_dummy);
11541 %}
11542
11543 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
11544 match(Set dst (SubVF src1 src2));
11545 predicate(n->as_Vector()->length() == 4);
11546 format %{ "VFSSB $dst,$src1,$src2\t// sub packed4F" %}
11547 size(6);
11548 ins_encode %{
11549 __ z_vfssb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11550 %}
11551 ins_pipe(pipe_class_dummy);
11552 %}
11553
11554 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
11555 match(Set dst (SubVD src1 src2));
11556 predicate(n->as_Vector()->length() == 2);
11557 format %{ "VFSDB $dst,$src1,$src2\t// sub packed2D" %}
11558 size(6);
11559 ins_encode %{
11560 __ z_vfsdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11561 %}
11562 ins_pipe(pipe_class_dummy);
11563 %}
11564
11565 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
11566 match(Set dst (MulVF src1 src2));
11567 predicate(n->as_Vector()->length() == 4);
11568 format %{ "VFMSB $dst,$src1,$src2\t// mul packed4F" %}
11569 size(6);
11570 ins_encode %{
11571 __ z_vfmsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11572 %}
11573 ins_pipe(pipe_class_dummy);
11574 %}
11575
11576 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
11577 match(Set dst (MulVD src1 src2));
11578 predicate(n->as_Vector()->length() == 2);
11579 format %{ "VFMDB $dst,$src1,$src2\t// mul packed2D" %}
11580 size(6);
11581 ins_encode %{
11582 __ z_vfmdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11583 %}
11584 ins_pipe(pipe_class_dummy);
11585 %}
11586
11587 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
11588 match(Set dst (DivVF src1 src2));
11589 predicate(n->as_Vector()->length() == 4);
11590 format %{ "VFDSB $dst,$src1,$src2\t// div packed4F" %}
11591 size(6);
11592 ins_encode %{
11593 __ z_vfdsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11594 %}
11595 ins_pipe(pipe_class_dummy);
11596 %}
11597
11598 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
11599 match(Set dst (DivVD src1 src2));
11600 predicate(n->as_Vector()->length() == 2);
11601 format %{ "VFDDB $dst,$src1,$src2\t// div packed2D" %}
11602 size(6);
11603 ins_encode %{
11604 __ z_vfddb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11605 %}
11606 ins_pipe(pipe_class_dummy);
11607 %}
11608
11609 // Vector Square Root Instructions
11610
11611 instruct vsqrt4F_reg(vecX dst, vecX src) %{
11612 match(Set dst (SqrtVF src));
11613 predicate(n->as_Vector()->length() == 4);
11614 format %{ "VFSQSB $dst,$src\t// sqrt packed4F" %}
11615 size(6);
11616 ins_encode %{
11617 __ z_vfsqsb($dst$$VectorRegister, $src$$VectorRegister);
11618 %}
11619 ins_pipe(pipe_class_dummy);
11620 %}
11621
11622 instruct vsqrt2D_reg(vecX dst, vecX src) %{
11623 match(Set dst (SqrtVD src));
11624 predicate(n->as_Vector()->length() == 2);
11625 format %{ "VFSQDB $dst,$src\t// sqrt packed2D" %}
11626 size(6);
11627 ins_encode %{
11628 __ z_vfsqdb($dst$$VectorRegister, $src$$VectorRegister);
11629 %}
11630 ins_pipe(pipe_class_dummy);
11631 %}
11632
11633 // Vector Population Count Instructions
11634
11635 instruct vpopcnt_reg(vecX dst, vecX src) %{
11636 match(Set dst (PopCountVI src));
11637 format %{ "VPOPCT $dst,$src\t// pop count packed" %}
11638 size(6);
11639 ins_encode %{
11640 BasicType bt = Matcher::vector_element_basic_type(this);
11641 switch (bt) {
11642 case T_BYTE:
11643 __ z_vpopctb($dst$$VectorRegister, $src$$VectorRegister);
11644 break;
11645 case T_SHORT:
11646 __ z_vpopcth($dst$$VectorRegister, $src$$VectorRegister);
11647 break;
11648 case T_INT:
11649 __ z_vpopctf($dst$$VectorRegister, $src$$VectorRegister);
11650 break;
11651 case T_LONG:
11652 __ z_vpopctg($dst$$VectorRegister, $src$$VectorRegister);
11653 break;
11654 default:
11655 ShouldNotReachHere();
11656 }
11657 %}
11658 ins_pipe(pipe_class_dummy);
11659 %}
11660
11661 // Vector Round Instructions
11662 instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
11663 match(Set dst (RoundDoubleModeV src rmode));
11664 predicate(n->as_Vector()->length() == 2);
11665 format %{ "RoundDoubleModeV $src,$rmode" %}
11666 size(6);
11667 ins_encode %{
11668 switch ($rmode$$constant) {
11669 case RoundDoubleModeNode::rmode_rint:
11670 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 0);
11671 break;
11672 case RoundDoubleModeNode::rmode_floor:
11673 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 7);
11674 break;
11675 case RoundDoubleModeNode::rmode_ceil:
11676 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 6);
11677 break;
11678 default:
11679 ShouldNotReachHere();
11680 }
11681 %}
11682 ins_pipe(pipe_class_dummy);
11683 %}
11684
11685 //----------POPULATION COUNT RULES--------------------------------------------
11686
11687 // Byte reverse
11688
11689 instruct bytes_reverse_short(iRegI dst, iRegI src) %{
11690 match(Set dst (ReverseBytesS src));
11691 predicate(UseByteReverseInstruction);
11692 ins_cost(2 * DEFAULT_COST);
11693 size(8);
11694
11695 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11696 "SRA $dst, 0x0010\t # right shift by 16, sign extended" %}
11697
11698 ins_encode %{
11699 __ z_lrvr($dst$$Register, $src$$Register);
11700 __ z_sra($dst$$Register, 0x0010);
11701 %}
11702 ins_pipe(pipe_class_dummy);
11703 %}
11704
11705 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
11706 match(Set dst (ReverseBytesUS src));
11707 predicate(UseByteReverseInstruction);
11708 ins_cost(2 * DEFAULT_COST);
11709 size(8);
11710
11711 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11712 "SRL $dst, 0x0010\t # right shift by 16, zero extended" %}
11713
11714 ins_encode %{
11715 __ z_lrvr($dst$$Register, $src$$Register);
11716 __ z_srl($dst$$Register, 0x0010);
11717 %}
11718 ins_pipe(pipe_class_dummy);
11719 %}
11720
11721 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
11722 match(Set dst (ReverseBytesI src));
11723 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11724 ins_cost(DEFAULT_COST);
11725 size(4);
11726 format %{ "LRVR $dst,$src\t # byte reverse int" %}
11727 opcode(LRVR_ZOPC);
11728 ins_encode(z_rreform(dst, src));
11729 ins_pipe(pipe_class_dummy);
11730 %}
11731
11732 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
11733 match(Set dst (ReverseBytesL src));
11734 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11735 ins_cost(DEFAULT_COST);
11736 // TODO: s390 port size(FIXED_SIZE);
11737 format %{ "LRVGR $dst,$src\t # byte reverse long" %}
11738 opcode(LRVGR_ZOPC);
11739 ins_encode(z_rreform(dst, src));
11740 ins_pipe(pipe_class_dummy);
11741 %}
11742
11743 // Leading zeroes
11744
11745 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
11746 // returns the bit position of the leftmost 1 in the 64bit source register.
11747 // As the bits are numbered from left to right (0..63), the returned
11748 // position index is equivalent to the number of leading zeroes.
11749 // If no 1-bit is found (i.e. the register contains zero), the instruction
11750 // returns position 64. That's exactly what we need.
11751
11752 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11753 match(Set dst (CountLeadingZerosI src));
11754 effect(KILL tmp, KILL cr);
11755 ins_cost(3 * DEFAULT_COST);
11756 size(14);
11757 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
11758 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
11759 "FLOGR $dst,$dst"
11760 %}
11761 ins_encode %{
11762 // Performance experiments indicate that "FLOGR" is using some kind of
11763 // iteration to find the leftmost "1" bit.
11764 //
11765 // The prior implementation zero-extended the 32-bit argument to 64 bit,
11766 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
11767 // We could gain measurable speedup in micro benchmark:
11768 //
11769 // leading trailing
11770 // z10: int 2.04 1.68
11771 // long 1.00 1.02
11772 // z196: int 0.99 1.23
11773 // long 1.00 1.11
11774 //
11775 // By shifting the argument into the high-word instead of zero-extending it.
11776 // The add'l branch on condition (taken for a zero argument, very infrequent,
11777 // good prediction) is well compensated for by the savings.
11778 //
11779 // We leave the previous implementation in for some time in the future when
11780 // the "FLOGR" instruction may become less iterative.
11781
11782 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
11783 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
11784 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
11785 __ z_flogr($dst$$Register, $dst$$Register);
11786 %}
11787 ins_pipe(pipe_class_dummy);
11788 %}
11789
11790 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
11791 match(Set dst (CountLeadingZerosL src));
11792 effect(KILL tmp, KILL cr);
11793 ins_cost(DEFAULT_COST);
11794 size(4);
11795 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
11796 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
11797 ins_pipe(pipe_class_dummy);
11798 %}
11799
11800 // trailing zeroes
11801
11802 // We transform the trailing zeroes problem to a leading zeroes problem
11803 // such that can use the FLOGR instruction to our advantage.
11804
11805 // With
11806 // tmp1 = src - 1
11807 // we flip all trailing zeroes to ones and the rightmost one to zero.
11808 // All other bits remain unchanged.
11809 // With the complement
11810 // tmp2 = ~src
11811 // we get all ones in the trailing zeroes positions. Thus,
11812 // tmp3 = tmp1 & tmp2
11813 // yields ones in the trailing zeroes positions and zeroes elsewhere.
11814 // Now we can apply FLOGR and get 64-(trailing zeroes).
11815 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11816 match(Set dst (CountTrailingZerosI src));
11817 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11818 ins_cost(8 * DEFAULT_COST);
11819 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11820 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
11821 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t"
11822 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11823 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t"
11824 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t"
11825 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t"
11826 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11827 "LCR $dst,$dst \t # res = -tmp4"
11828 %}
11829 ins_encode %{
11830 Register Rdst = $dst$$Register;
11831 Register Rsrc = $src$$Register;
11832 // Rtmp only needed for for zero-argument shortcut. With kill effect in
11833 // match rule Rsrc = roddReg would be possible, saving one register.
11834 Register Rtmp = $tmp$$Register;
11835
11836 assert_different_registers(Rdst, Rsrc, Rtmp);
11837
11838 // Algorithm:
11839 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
11840 // All other bits in the result are zero.
11841 // - Find the "leftmost one" bit position in the single-bit result from previous step.
11842 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
11843
11844 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
11845 Label done;
11846 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
11847 __ z_lcgfr(Rtmp, Rsrc);
11848 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
11849
11850 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
11851 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
11852 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
11853 // into upper half of reg. Not relevant with sllg below.
11854 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
11855 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
11856 // Depends on CC set by ahi above.
11857 // Taken very infrequently, good prediction, no BHT entry.
11858 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
11859 // after SLLG Rdst == 0(64bit)).
11860 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11861 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
11862 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11863 __ bind(done);
11864 %}
11865 ins_pipe(pipe_class_dummy);
11866 %}
11867
11868 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
11869 match(Set dst (CountTrailingZerosL src));
11870 effect(TEMP_DEF dst, KILL tmp, KILL cr);
11871 ins_cost(8 * DEFAULT_COST);
11872 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11873 format %{ "LCGR $dst,$src \t # preserve src\n\t"
11874 "NGR $dst,$src \t #\n\t"
11875 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11876 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t"
11877 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11878 "LCR $dst,$dst \t #"
11879 %}
11880 ins_encode %{
11881 Register Rdst = $dst$$Register;
11882 Register Rsrc = $src$$Register;
11883 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
11884
11885 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
11886 __ z_lcgr(Rdst, Rsrc);
11887 __ z_ngr(Rdst, Rsrc);
11888 __ add2reg(Rdst, -1);
11889 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11890 __ add2reg(Rdst, -64);
11891 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11892 %}
11893 ins_pipe(pipe_class_dummy);
11894 %}
11895
11896
11897 // bit count
11898
11899 instruct popCountI_Ext3(iRegI dst, iRegI src, flagsReg cr) %{
11900 match(Set dst (PopCountI src));
11901 effect(TEMP_DEF dst, KILL cr);
11902 predicate(UsePopCountInstruction &&
11903 VM_Version::has_PopCount() &&
11904 VM_Version::has_MiscInstrExt3());
11905 ins_cost(DEFAULT_COST);
11906 size(8); // popcnt + llgfr
11907 format %{ "POPCNT $dst,$src\t # pop count int" %}
11908 ins_encode %{
11909 Register Rdst = $dst$$Register;
11910 Register Rsrc = $src$$Register;
11911
11912 __ pop_count_int_with_ext3(Rdst, Rsrc);
11913
11914 %}
11915 ins_pipe(pipe_class_dummy);
11916 %}
11917
11918 instruct popCountL_Ext3(iRegI dst, iRegL src, flagsReg cr) %{
11919 match(Set dst (PopCountL src));
11920 effect(TEMP_DEF dst, KILL cr);
11921 predicate(UsePopCountInstruction &&
11922 VM_Version::has_PopCount() &&
11923 VM_Version::has_MiscInstrExt3());
11924 ins_cost(DEFAULT_COST);
11925 size(4); // popcnt
11926 format %{ "POPCNT $dst,$src\t # pop count long" %}
11927 ins_encode %{
11928 Register Rdst = $dst$$Register;
11929 Register Rsrc = $src$$Register;
11930
11931 __ pop_count_long_with_ext3(Rdst, Rsrc);
11932 %}
11933 ins_pipe(pipe_class_dummy);
11934 %}
11935
11936 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
11937 match(Set dst (PopCountI src));
11938 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11939 predicate(UsePopCountInstruction &&
11940 VM_Version::has_PopCount() &&
11941 (!VM_Version::has_MiscInstrExt3()));
11942 ins_cost(DEFAULT_COST);
11943 size(24);
11944 format %{ "POPCNT $dst,$src\t # pop count int" %}
11945 ins_encode %{
11946 Register Rdst = $dst$$Register;
11947 Register Rsrc = $src$$Register;
11948 Register Rtmp = $tmp$$Register;
11949
11950 __ pop_count_int_without_ext3(Rdst, Rsrc, Rtmp);
11951
11952 %}
11953 ins_pipe(pipe_class_dummy);
11954 %}
11955
11956 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
11957 match(Set dst (PopCountL src));
11958 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11959 predicate(UsePopCountInstruction &&
11960 VM_Version::has_PopCount() &&
11961 (!VM_Version::has_MiscInstrExt3()));
11962 ins_cost(DEFAULT_COST);
11963 size(34);
11964 format %{ "POPCNT $dst,$src\t # pop count long" %}
11965 ins_encode %{
11966 Register Rdst = $dst$$Register;
11967 Register Rsrc = $src$$Register;
11968 Register Rtmp = $tmp$$Register;
11969
11970 __ pop_count_long_without_ext3(Rdst, Rsrc, Rtmp);
11971 %}
11972 ins_pipe(pipe_class_dummy);
11973 %}
11974
11975 //----------SMARTSPILL RULES---------------------------------------------------
11976 // These must follow all instruction definitions as they use the names
11977 // defined in the instructions definitions.
11978
11979 // ============================================================================
11980 // TYPE PROFILING RULES