1 //
2 // Copyright (c) 2017, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2017, 2024 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alignment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to continue at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // ----------------------------
101 // Integer/Long Registers
102 // ----------------------------
103
104 // z/Architecture has 16 64-bit integer registers.
105
106 // types: v = volatile, nv = non-volatile, s = system
107 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
108 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
109 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
110 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
111 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
112 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
113 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
114 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
115 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
116 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
117 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
118 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
119 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
120 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
121 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
122 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
123 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
124 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
125 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
126 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
127 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
128 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
129 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
130 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
131 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
132 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
133 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
134 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
135 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
136 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
137 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
138 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
139
140 // ----------------------------
141 // Float/Double Registers
142 // ----------------------------
143
144 // The rules of ADL require that double registers be defined in pairs.
145 // Each pair must be two 32-bit values, but not necessarily a pair of
146 // single float registers. In each pair, ADLC-assigned register numbers
147 // must be adjacent, with the lower number even. Finally, when the
148 // CPU stores such a register pair to memory, the word associated with
149 // the lower ADLC-assigned number must be stored to the lower address.
150
151 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
152 // or double precision floating-point value.
153
154 // types: v = volatile, nv = non-volatile, s = system
155 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
156 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
157 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
158 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
159 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
160 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
161 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
162 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
163 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
164 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
165 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
166 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
167 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
168 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
169 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
170 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
171 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
172 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
173 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
174 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
175 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
176 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
177 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
178 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
179 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
180 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
181 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
182 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
183 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
184 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
185 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
186 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
187
188 // ----------------------------
189 // Vector Registers
190 // ----------------------------
191 // 1st 16 VRs are aliases for the FPRs which are already defined above.
192 reg_def Z_VR0 ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
193 reg_def Z_VR0_H ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
194 reg_def Z_VR0_J ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
195 reg_def Z_VR0_K ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
196
197 reg_def Z_VR1 ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
198 reg_def Z_VR1_H ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
199 reg_def Z_VR1_J ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
200 reg_def Z_VR1_K ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
201
202 reg_def Z_VR2 ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
203 reg_def Z_VR2_H ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
204 reg_def Z_VR2_J ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
205 reg_def Z_VR2_K ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
206
207 reg_def Z_VR3 ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
208 reg_def Z_VR3_H ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
209 reg_def Z_VR3_J ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
210 reg_def Z_VR3_K ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
211
212 reg_def Z_VR4 ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
213 reg_def Z_VR4_H ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
214 reg_def Z_VR4_J ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
215 reg_def Z_VR4_K ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
216
217 reg_def Z_VR5 ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
218 reg_def Z_VR5_H ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
219 reg_def Z_VR5_J ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
220 reg_def Z_VR5_K ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
221
222 reg_def Z_VR6 ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
223 reg_def Z_VR6_H ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
224 reg_def Z_VR6_J ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
225 reg_def Z_VR6_K ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
226
227 reg_def Z_VR7 ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
228 reg_def Z_VR7_H ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
229 reg_def Z_VR7_J ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
230 reg_def Z_VR7_K ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
231
232 reg_def Z_VR8 ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
233 reg_def Z_VR8_H ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
234 reg_def Z_VR8_J ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
235 reg_def Z_VR8_K ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
236
237 reg_def Z_VR9 ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
238 reg_def Z_VR9_H ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
239 reg_def Z_VR9_J ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
240 reg_def Z_VR9_K ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
241
242 reg_def Z_VR10 ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
243 reg_def Z_VR10_H ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
244 reg_def Z_VR10_J ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
245 reg_def Z_VR10_K ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
246
247 reg_def Z_VR11 ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
248 reg_def Z_VR11_H ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
249 reg_def Z_VR11_J ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
250 reg_def Z_VR11_K ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
251
252 reg_def Z_VR12 ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
253 reg_def Z_VR12_H ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
254 reg_def Z_VR12_J ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
255 reg_def Z_VR12_K ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
256
257 reg_def Z_VR13 ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
258 reg_def Z_VR13_H ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
259 reg_def Z_VR13_J ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
260 reg_def Z_VR13_K ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
261
262 reg_def Z_VR14 ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
263 reg_def Z_VR14_H ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
264 reg_def Z_VR14_J ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
265 reg_def Z_VR14_K ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
266
267 reg_def Z_VR15 ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
268 reg_def Z_VR15_H ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
269 reg_def Z_VR15_J ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
270 reg_def Z_VR15_K ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
271
272 reg_def Z_VR16 ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg() );
273 reg_def Z_VR16_H ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next() );
274 reg_def Z_VR16_J ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(2) );
275 reg_def Z_VR16_K ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(3) );
276
277 reg_def Z_VR17 ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg() );
278 reg_def Z_VR17_H ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next() );
279 reg_def Z_VR17_J ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(2) );
280 reg_def Z_VR17_K ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(3) );
281
282 reg_def Z_VR18 ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg() );
283 reg_def Z_VR18_H ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next() );
284 reg_def Z_VR18_J ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(2) );
285 reg_def Z_VR18_K ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(3) );
286
287 reg_def Z_VR19 ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg() );
288 reg_def Z_VR19_H ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next() );
289 reg_def Z_VR19_J ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(2) );
290 reg_def Z_VR19_K ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(3) );
291
292 reg_def Z_VR20 ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg() );
293 reg_def Z_VR20_H ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next() );
294 reg_def Z_VR20_J ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(2) );
295 reg_def Z_VR20_K ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(3) );
296
297 reg_def Z_VR21 ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg() );
298 reg_def Z_VR21_H ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next() );
299 reg_def Z_VR21_J ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(2) );
300 reg_def Z_VR21_K ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(3) );
301
302 reg_def Z_VR22 ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg() );
303 reg_def Z_VR22_H ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next() );
304 reg_def Z_VR22_J ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(2) );
305 reg_def Z_VR22_K ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(3) );
306
307 reg_def Z_VR23 ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg() );
308 reg_def Z_VR23_H ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next() );
309 reg_def Z_VR23_J ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(2) );
310 reg_def Z_VR23_K ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(3) );
311
312 reg_def Z_VR24 ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg() );
313 reg_def Z_VR24_H ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next() );
314 reg_def Z_VR24_J ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(2) );
315 reg_def Z_VR24_K ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(3) );
316
317 reg_def Z_VR25 ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg() );
318 reg_def Z_VR25_H ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next() );
319 reg_def Z_VR25_J ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(2) );
320 reg_def Z_VR25_K ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(3) );
321
322 reg_def Z_VR26 ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg() );
323 reg_def Z_VR26_H ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next() );
324 reg_def Z_VR26_J ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(2) );
325 reg_def Z_VR26_K ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(3) );
326
327 reg_def Z_VR27 ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg() );
328 reg_def Z_VR27_H ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next() );
329 reg_def Z_VR27_J ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(2) );
330 reg_def Z_VR27_K ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(3) );
331
332 reg_def Z_VR28 ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg() );
333 reg_def Z_VR28_H ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next() );
334 reg_def Z_VR28_J ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(2) );
335 reg_def Z_VR28_K ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(3) );
336
337 reg_def Z_VR29 ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg() );
338 reg_def Z_VR29_H ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next() );
339 reg_def Z_VR29_J ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(2) );
340 reg_def Z_VR29_K ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(3) );
341
342 reg_def Z_VR30 ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg() );
343 reg_def Z_VR30_H ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next() );
344 reg_def Z_VR30_J ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(2) );
345 reg_def Z_VR30_K ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(3) );
346
347 reg_def Z_VR31 ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg() );
348 reg_def Z_VR31_H ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next() );
349 reg_def Z_VR31_J ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(2) );
350 reg_def Z_VR31_K ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(3) );
351 // Special Registers
352
353 // Condition Codes Flag Registers
354
355 // z/Architecture has the PSW (program status word) that contains
356 // (among other information) the condition code. We treat this
357 // part of the PSW as a condition register CR. It consists of 4
358 // bits. Floating point instructions influence the same condition register CR.
359
360 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
361
362 // Specify priority of register selection within phases of register
363 // allocation. Highest priority is first. A useful heuristic is to
364 // give registers a low priority when they are required by machine
365 // instructions, and choose no-save registers before save-on-call, and
366 // save-on-call before save-on-entry. Registers which participate in
367 // fix calling sequences should come last. Registers which are used
368 // as pairs must fall on an even boundary.
369
370 // It's worth about 1% on SPEC geomean to get this right.
371
372 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
373 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
374 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
375 // the same as Z_R3->encoding()! Furthermore, we cannot make any
376 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
377 // Additionally, the function
378 // static enum RC rc_class(OptoReg::Name reg)
379 // maps a given <register>_num value to its chunk type (except for flags)
380 // and its current implementation relies on chunk0 and chunk1 having a
381 // size of 64 each.
382
383 alloc_class chunk0(
384 // chunk0 contains *all* 32 integer registers halves.
385
386 // potential SOE regs
387 Z_R13,Z_R13_H,
388 Z_R12,Z_R12_H,
389 Z_R11,Z_R11_H,
390 Z_R10,Z_R10_H,
391
392 Z_R9,Z_R9_H,
393 Z_R8,Z_R8_H,
394 Z_R7,Z_R7_H,
395
396 Z_R1,Z_R1_H,
397 Z_R0,Z_R0_H,
398
399 // argument registers
400 Z_R6,Z_R6_H,
401 Z_R5,Z_R5_H,
402 Z_R4,Z_R4_H,
403 Z_R3,Z_R3_H,
404 Z_R2,Z_R2_H,
405
406 // special registers
407 Z_R14,Z_R14_H,
408 Z_R15,Z_R15_H
409 );
410
411 alloc_class chunk1(
412 // Chunk1 contains *all* 64 floating-point registers halves.
413
414 Z_F15,Z_F15_H,
415 Z_F14,Z_F14_H,
416 Z_F13,Z_F13_H,
417 Z_F12,Z_F12_H,
418 Z_F11,Z_F11_H,
419 Z_F10,Z_F10_H,
420 Z_F9,Z_F9_H,
421 Z_F8,Z_F8_H,
422 // scratch register
423 Z_F7,Z_F7_H,
424 Z_F5,Z_F5_H,
425 Z_F3,Z_F3_H,
426 Z_F1,Z_F1_H,
427 // argument registers
428 Z_F6,Z_F6_H,
429 Z_F4,Z_F4_H,
430 Z_F2,Z_F2_H,
431 Z_F0,Z_F0_H
432 );
433
434 alloc_class chunk2(
435 Z_VR0, Z_VR0_H, Z_VR0_J, Z_VR0_K,
436 Z_VR1, Z_VR1_H, Z_VR1_J, Z_VR1_K,
437 Z_VR2, Z_VR2_H, Z_VR2_J, Z_VR2_K,
438 Z_VR3, Z_VR3_H, Z_VR3_J, Z_VR3_K,
439 Z_VR4, Z_VR4_H, Z_VR4_J, Z_VR4_K,
440 Z_VR5, Z_VR5_H, Z_VR5_J, Z_VR5_K,
441 Z_VR6, Z_VR6_H, Z_VR6_J, Z_VR6_K,
442 Z_VR7, Z_VR7_H, Z_VR7_J, Z_VR7_K,
443 Z_VR8, Z_VR8_H, Z_VR8_J, Z_VR8_K,
444 Z_VR9, Z_VR9_H, Z_VR9_J, Z_VR9_K,
445 Z_VR10, Z_VR10_H, Z_VR10_J, Z_VR10_K,
446 Z_VR11, Z_VR11_H, Z_VR11_J, Z_VR11_K,
447 Z_VR12, Z_VR12_H, Z_VR12_J, Z_VR12_K,
448 Z_VR13, Z_VR13_H, Z_VR13_J, Z_VR13_K,
449 Z_VR14, Z_VR14_H, Z_VR14_J, Z_VR14_K,
450 Z_VR15, Z_VR15_H, Z_VR15_J, Z_VR15_K,
451 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
452 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
453 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
454 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
455 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
456 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
457 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
458 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
459 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
460 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
461 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
462 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
463 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
464 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
465 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
466 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
467 );
468
469 alloc_class chunk3(
470 Z_CR
471 );
472
473
474 //-------Architecture Description Register Classes-----------------------
475
476 // Several register classes are automatically defined based upon
477 // information in this architecture description.
478
479 // 1) reg_class inline_cache_reg (as defined in frame section)
480 // 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
481
482 // Integer Register Classes
483 reg_class z_int_reg(
484 /*Z_R0*/ // R0
485 /*Z_R1*/
486 Z_R2,
487 Z_R3,
488 Z_R4,
489 Z_R5,
490 Z_R6,
491 Z_R7,
492 /*Z_R8,*/ // Z_thread
493 Z_R9,
494 Z_R10,
495 Z_R11,
496 Z_R12,
497 Z_R13
498 /*Z_R14*/ // return_pc
499 /*Z_R15*/ // SP
500 );
501
502 reg_class z_no_odd_int_reg(
503 /*Z_R0*/ // R0
504 /*Z_R1*/
505 Z_R2,
506 Z_R3,
507 Z_R4,
508 /*Z_R5,*/ // odd part of fix register pair
509 Z_R6,
510 Z_R7,
511 /*Z_R8,*/ // Z_thread
512 Z_R9,
513 Z_R10,
514 Z_R11,
515 Z_R12,
516 Z_R13
517 /*Z_R14*/ // return_pc
518 /*Z_R15*/ // SP
519 );
520
521 reg_class z_no_arg_int_reg(
522 /*Z_R0*/ // R0
523 /*Z_R1*/ // scratch
524 /*Z_R2*/
525 /*Z_R3*/
526 /*Z_R4*/
527 /*Z_R5*/
528 /*Z_R6*/
529 Z_R7,
530 /*Z_R8*/ // Z_thread
531 Z_R9,
532 Z_R10,
533 Z_R11,
534 Z_R12,
535 Z_R13
536 /*Z_R14*/ // return_pc
537 /*Z_R15*/ // SP
538 );
539
540 reg_class z_rarg1_int_reg(Z_R2);
541 reg_class z_rarg2_int_reg(Z_R3);
542 reg_class z_rarg3_int_reg(Z_R4);
543 reg_class z_rarg4_int_reg(Z_R5);
544 reg_class z_rarg5_int_reg(Z_R6);
545
546 // Pointer Register Classes
547
548 // 64-bit build means 64-bit pointers means hi/lo pairs.
549
550 reg_class z_rarg5_ptrN_reg(Z_R6);
551
552 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
553 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
554 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
555 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
556 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
557 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
558 reg_class z_r10_ptr_reg(Z_R10_H, Z_R10);
559 reg_class z_r11_ptr_reg(Z_R11_H, Z_R11);
560
561 reg_class z_ptr_reg(
562 /*Z_R0_H,Z_R0*/ // R0
563 /*Z_R1_H,Z_R1*/
564 Z_R2_H,Z_R2,
565 Z_R3_H,Z_R3,
566 Z_R4_H,Z_R4,
567 Z_R5_H,Z_R5,
568 Z_R6_H,Z_R6,
569 Z_R7_H,Z_R7,
570 /*Z_R8_H,Z_R8,*/ // Z_thread
571 Z_R9_H,Z_R9,
572 Z_R10_H,Z_R10,
573 Z_R11_H,Z_R11,
574 Z_R12_H,Z_R12,
575 Z_R13_H,Z_R13
576 /*Z_R14_H,Z_R14*/ // return_pc
577 /*Z_R15_H,Z_R15*/ // SP
578 );
579
580 reg_class z_lock_ptr_reg(
581 /*Z_R0_H,Z_R0*/ // R0
582 /*Z_R1_H,Z_R1*/
583 Z_R2_H,Z_R2,
584 Z_R3_H,Z_R3,
585 Z_R4_H,Z_R4,
586 /*Z_R5_H,Z_R5,*/
587 /*Z_R6_H,Z_R6,*/
588 Z_R7_H,Z_R7,
589 /*Z_R8_H,Z_R8,*/ // Z_thread
590 Z_R9_H,Z_R9,
591 Z_R10_H,Z_R10,
592 Z_R11_H,Z_R11,
593 Z_R12_H,Z_R12,
594 Z_R13_H,Z_R13
595 /*Z_R14_H,Z_R14*/ // return_pc
596 /*Z_R15_H,Z_R15*/ // SP
597 );
598
599 reg_class z_no_arg_ptr_reg(
600 /*Z_R0_H,Z_R0*/ // R0
601 /*Z_R1_H,Z_R1*/ // scratch
602 /*Z_R2_H,Z_R2*/
603 /*Z_R3_H,Z_R3*/
604 /*Z_R4_H,Z_R4*/
605 /*Z_R5_H,Z_R5*/
606 /*Z_R6_H,Z_R6*/
607 Z_R7_H, Z_R7,
608 /*Z_R8_H,Z_R8*/ // Z_thread
609 Z_R9_H,Z_R9,
610 Z_R10_H,Z_R10,
611 Z_R11_H,Z_R11,
612 Z_R12_H,Z_R12,
613 Z_R13_H,Z_R13
614 /*Z_R14_H,Z_R14*/ // return_pc
615 /*Z_R15_H,Z_R15*/ // SP
616 );
617
618 // Special class for storeP instructions, which can store SP or RPC to
619 // TLS. (Note: Do not generalize this to "any_reg". If you add
620 // another register, such as FP, to this mask, the allocator may try
621 // to put a temp in it.)
622 // Register class for memory access base registers,
623 // This class is a superset of z_ptr_reg including Z_thread.
624 reg_class z_memory_ptr_reg(
625 /*Z_R0_H,Z_R0*/ // R0
626 /*Z_R1_H,Z_R1*/
627 Z_R2_H,Z_R2,
628 Z_R3_H,Z_R3,
629 Z_R4_H,Z_R4,
630 Z_R5_H,Z_R5,
631 Z_R6_H,Z_R6,
632 Z_R7_H,Z_R7,
633 Z_R8_H,Z_R8, // Z_thread
634 Z_R9_H,Z_R9,
635 Z_R10_H,Z_R10,
636 Z_R11_H,Z_R11,
637 Z_R12_H,Z_R12,
638 Z_R13_H,Z_R13
639 /*Z_R14_H,Z_R14*/ // return_pc
640 /*Z_R15_H,Z_R15*/ // SP
641 );
642
643 // Other special pointer regs.
644 reg_class z_r1_regP(Z_R1_H,Z_R1);
645 reg_class z_r9_regP(Z_R9_H,Z_R9);
646
647
648 // Long Register Classes
649
650 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
651 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
652 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
653 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
654 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
655
656 // Longs in 1 register. Aligned adjacent hi/lo pairs.
657 reg_class z_long_reg(
658 /*Z_R0_H,Z_R0*/ // R0
659 /*Z_R1_H,Z_R1*/
660 Z_R2_H,Z_R2,
661 Z_R3_H,Z_R3,
662 Z_R4_H,Z_R4,
663 Z_R5_H,Z_R5,
664 Z_R6_H,Z_R6,
665 Z_R7_H,Z_R7,
666 /*Z_R8_H,Z_R8,*/ // Z_thread
667 Z_R9_H,Z_R9,
668 Z_R10_H,Z_R10,
669 Z_R11_H,Z_R11,
670 Z_R12_H,Z_R12,
671 Z_R13_H,Z_R13
672 /*Z_R14_H,Z_R14,*/ // return_pc
673 /*Z_R15_H,Z_R15*/ // SP
674 );
675
676 // z_long_reg without even registers
677 reg_class z_long_odd_reg(
678 /*Z_R0_H,Z_R0*/ // R0
679 /*Z_R1_H,Z_R1*/
680 Z_R3_H,Z_R3,
681 Z_R5_H,Z_R5,
682 Z_R7_H,Z_R7,
683 Z_R9_H,Z_R9,
684 Z_R11_H,Z_R11,
685 Z_R13_H,Z_R13
686 /*Z_R14_H,Z_R14,*/ // return_pc
687 /*Z_R15_H,Z_R15*/ // SP
688 );
689
690 // Special Class for Condition Code Flags Register
691
692 reg_class z_condition_reg(
693 Z_CR
694 );
695
696 // Scratch register for late profiling. Callee saved.
697 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
698
699
700 // Float Register Classes
701
702 reg_class z_flt_reg(
703 Z_F0,
704 /*Z_F1,*/ // scratch
705 Z_F2,
706 Z_F3,
707 Z_F4,
708 Z_F5,
709 Z_F6,
710 Z_F7,
711 Z_F8,
712 Z_F9,
713 Z_F10,
714 Z_F11,
715 Z_F12,
716 Z_F13,
717 Z_F14,
718 Z_F15
719 );
720 reg_class z_rscratch1_flt_reg(Z_F1);
721
722 // Double precision float registers have virtual `high halves' that
723 // are needed by the allocator.
724 reg_class z_dbl_reg(
725 Z_F0,Z_F0_H,
726 /*Z_F1,Z_F1_H,*/ // scratch
727 Z_F2,Z_F2_H,
728 Z_F3,Z_F3_H,
729 Z_F4,Z_F4_H,
730 Z_F5,Z_F5_H,
731 Z_F6,Z_F6_H,
732 Z_F7,Z_F7_H,
733 Z_F8,Z_F8_H,
734 Z_F9,Z_F9_H,
735 Z_F10,Z_F10_H,
736 Z_F11,Z_F11_H,
737 Z_F12,Z_F12_H,
738 Z_F13,Z_F13_H,
739 Z_F14,Z_F14_H,
740 Z_F15,Z_F15_H
741 );
742 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
743
744 reg_class z_v_reg(
745 // Attention: Only these ones are saved & restored at safepoint by RegisterSaver.
746 //1st 16 VRs overlaps with 1st 16 FPRs.
747 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
748 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
749 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
750 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
751 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
752 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
753 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
754 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
755 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
756 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
757 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
758 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
759 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
760 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
761 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
762 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
763 );
764
765 // class for vector register v16
766 reg_class z_vreg_16(
767 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K
768 );
769
770 // class for vector register v17
771 reg_class z_vreg_17(
772 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K
773 );
774
775 // class for vector register v18
776 reg_class z_vreg_18(
777 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K
778 );
779
780 // class for vector register v19
781 reg_class z_vreg_19(
782 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K
783 );
784
785 // class for vector register v20
786 reg_class z_vreg_20(
787 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K
788 );
789
790 // class for vector register v21
791 reg_class z_vreg_21(
792 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K
793 );
794
795 // class for vector register v22
796 reg_class z_vreg_22(
797 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K
798 );
799
800 // class for vector register v23
801 reg_class z_vreg_23(
802 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K
803 );
804
805 // class for vector register v24
806 reg_class z_vreg_24(
807 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K
808 );
809
810 // class for vector register v25
811 reg_class z_vreg_25(
812 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K
813 );
814
815 %}
816
817 //----------DEFINITION BLOCK---------------------------------------------------
818 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
819 // Current support includes integer values in the range [0, 0x7FFFFFFF].
820 // Format:
821 // int_def <name> (<int_value>, <expression>);
822 // Generated Code in ad_<arch>.hpp
823 // #define <name> (<expression>)
824 // // value == <int_value>
825 // Generated code in ad_<arch>.cpp adlc_verification()
826 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
827 //
828 definitions %{
829 // The default cost (of an ALU instruction).
830 int_def DEFAULT_COST ( 100, 100);
831 int_def DEFAULT_COST_LOW ( 80, 80);
832 int_def DEFAULT_COST_HIGH ( 120, 120);
833 int_def HUGE_COST (1000000, 1000000);
834
835 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
836 int_def ALU_REG_COST ( 100, DEFAULT_COST);
837 int_def ALU_MEMORY_COST ( 150, 150);
838
839 // Memory refs are twice as expensive as run-of-the-mill.
840 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
841 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
842 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
843
844 // Branches are even more expensive.
845 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
846 int_def CALL_COST ( 300, DEFAULT_COST * 3);
847 %}
848
849 source %{
850
851 #ifdef PRODUCT
852 #define BLOCK_COMMENT(str)
853 #define BIND(label) __ bind(label)
854 #else
855 #define BLOCK_COMMENT(str) __ block_comment(str)
856 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
857 #endif
858
859 #define __ masm->
860
861 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
862 #define Z_DISP3_SIZE 6
863
864 // Tertiary op of a LoadP or StoreP encoding.
865 #define REGP_OP true
866
867 // Given a register encoding, produce an Integer Register object.
868 static Register reg_to_register_object(int register_encoding);
869
870 // ****************************************************************************
871
872 // REQUIRED FUNCTIONALITY
873
874 // !!!!! Special hack to get all type of calls to specify the byte offset
875 // from the start of the call to the point where the return address
876 // will point.
877
878 void PhaseOutput::pd_perform_mach_node_analysis() {
879 }
880
881 int MachNode::pd_alignment_required() const {
882 return 1;
883 }
884
885 int MachNode::compute_padding(int current_offset) const {
886 return 0;
887 }
888
889 int MachCallStaticJavaNode::ret_addr_offset() {
890 if (_method) {
891 return 8;
892 } else {
893 return MacroAssembler::call_far_patchable_ret_addr_offset();
894 }
895 }
896
897 int MachCallDynamicJavaNode::ret_addr_offset() {
898 // Consider size of receiver type profiling (C2 tiers).
899 int profile_receiver_type_size = 0;
900
901 int vtable_index = this->_vtable_index;
902 if (vtable_index == -4) {
903 return 14 + profile_receiver_type_size;
904 } else {
905 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
906 return 36 + profile_receiver_type_size;
907 }
908 }
909
910 int MachCallRuntimeNode::ret_addr_offset() {
911 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
912 }
913
914 // Compute padding required for nodes which need alignment
915 //
916 // The addresses of the call instructions needs to be 4-byte aligned to
917 // ensure that they don't span a cache line so that they are atomically patchable.
918 // The actual calls get emitted at different offsets within the node emitters.
919 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
920
921 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
922 return (0 - current_offset) & 2;
923 }
924
925 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
926 return (6 - current_offset) & 2;
927 }
928
929 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
930 return (12 - current_offset) & 2;
931 }
932
933 int CallLeafDirectNode::compute_padding(int current_offset) const {
934 return (12 - current_offset) & 2;
935 }
936
937 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
938 return (12 - current_offset) & 2;
939 }
940
941 void emit_nop(C2_MacroAssembler *masm) {
942 __ z_nop();
943 }
944
945 // Emit an interrupt that is caught by the debugger (for debugging compiler).
946 void emit_break(C2_MacroAssembler *masm) {
947 __ z_illtrap();
948 }
949
950 #if !defined(PRODUCT)
951 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
952 os->print("TA");
953 }
954 #endif
955
956 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
957 emit_break(masm);
958 }
959
960 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
961 return MachNode::size(ra_);
962 }
963
964 static inline void z_emit16(C2_MacroAssembler *masm, long value) {
965 __ emit_instruction((unsigned long)value, 2);
966 }
967
968 static inline void z_emit32(C2_MacroAssembler *masm, long value) {
969 __ emit_instruction((unsigned long)value, 4);
970 }
971
972 static inline void z_emit48(C2_MacroAssembler *masm, long value) {
973 __ emit_instruction((unsigned long)value, 6);
974 }
975
976 static inline unsigned int z_emit_inst(C2_MacroAssembler *masm, long value) {
977 if (value < 0) {
978 // There obviously has been an unintended sign extension (int->long). Revert it.
979 value = (long)((unsigned long)((unsigned int)value));
980 }
981
982 int len = __ emit_instruction((unsigned long)value, 0);
983 return len;
984 }
985
986 // Check effective address (at runtime) for required alignment.
987 static inline void z_assert_aligned(C2_MacroAssembler *masm, int disp, Register index, Register base, int alignment) {
988 __ z_lay(Z_R0, disp, index, base);
989 __ z_nill(Z_R0, alignment-1);
990 __ z_brc(Assembler::bcondEqual, +3);
991 __ z_illtrap();
992 }
993
994 int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, relocInfo::relocType rtype,
995 PhaseRegAlloc* ra_, bool is_native_call = false) {
996 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
997 address old_mark = __ inst_mark();
998 unsigned int start_off = __ offset();
999
1000 if (is_native_call) {
1001 ShouldNotReachHere();
1002 }
1003
1004 if (rtype == relocInfo::runtime_call_w_cp_type) {
1005 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
1006 address call_addr = __ call_c_opt((address)entry_point);
1007 if (call_addr == nullptr) {
1008 Compile::current()->env()->record_out_of_memory_failure();
1009 return -1;
1010 }
1011 } else {
1012 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
1013 rtype == relocInfo::static_call_type, "unexpected rtype");
1014 __ relocate(rtype);
1015 // BRASL must be prepended with a nop to identify it in the instruction stream.
1016 __ z_nop();
1017 __ z_brasl(Z_R14, (address)entry_point);
1018 }
1019
1020 unsigned int ret_off = __ offset();
1021
1022 return (ret_off - start_off);
1023 }
1024
1025 static int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, RelocationHolder const& rspec) {
1026 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
1027 address old_mark = __ inst_mark();
1028 unsigned int start_off = __ offset();
1029
1030 relocInfo::relocType rtype = rspec.type();
1031 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
1032 "unexpected rtype");
1033
1034 __ relocate(rspec);
1035 __ z_nop();
1036 __ z_brasl(Z_R14, (address)entry_point);
1037
1038 unsigned int ret_off = __ offset();
1039
1040 return (ret_off - start_off);
1041 }
1042
1043 //=============================================================================
1044
1045 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
1046 int ConstantTable::calculate_table_base_offset() const {
1047 return 0; // absolute addressing, no offset
1048 }
1049
1050 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1051 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1052 ShouldNotReachHere();
1053 }
1054
1055 // Even with PC-relative TOC addressing, we still need this node.
1056 // Float loads/stores do not support PC-relative addresses.
1057 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1058 Register Rtoc = as_Register(ra_->get_encode(this));
1059 __ load_toc(Rtoc);
1060 }
1061
1062 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1063 // PCrelative TOC access.
1064 return 6; // sizeof(LARL)
1065 }
1066
1067 #if !defined(PRODUCT)
1068 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1069 Register r = as_Register(ra_->get_encode(this));
1070 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
1071 }
1072 #endif
1073
1074 //=============================================================================
1075
1076 #include "gc/shared/barrierSetAssembler.hpp"
1077
1078 #if !defined(PRODUCT)
1079 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1080 Compile* C = ra_->C;
1081 st->print_cr("--- MachPrologNode ---");
1082 st->print("\t");
1083 for (int i = 0; i < OptoPrologueNops; i++) {
1084 st->print_cr("NOP"); st->print("\t");
1085 }
1086
1087 long framesize = C->output()->frame_size_in_bytes();
1088 int bangsize = C->output()->bang_size_in_bytes();
1089
1090 // Calls to C2R adapters often do not accept exceptional returns.
1091 // We require that their callers must bang for them. But be
1092 // careful, because some VM calls (such as call site linkage) can
1093 // use several kilobytes of stack. But the stack safety zone should
1094 // account for that. See bugs 4446381, 4468289, 4497237.
1095 if (C->output()->need_stack_bang(bangsize)) {
1096 st->print_cr("# stack bang"); st->print("\t");
1097 }
1098 st->print_cr("push_frame %d", (int)-framesize);
1099 st->print("\t");
1100
1101 if (C->stub_function() == nullptr) {
1102 st->print("nmethod entry barrier\n\t");
1103 }
1104 }
1105 #endif
1106
1107 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1108 Compile* C = ra_->C;
1109
1110 size_t framesize = C->output()->frame_size_in_bytes();
1111 size_t bangsize = C->output()->bang_size_in_bytes();
1112
1113 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
1114
1115 if (C->clinit_barrier_on_entry()) {
1116 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1117
1118 Label L_skip_barrier;
1119 Register klass = Z_R1_scratch;
1120
1121 // Notify OOP recorder (don't need the relocation)
1122 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
1123 __ load_const_optimized(klass, md.value());
1124 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
1125
1126 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
1127 __ z_br(klass);
1128
1129 __ bind(L_skip_barrier);
1130 }
1131
1132 // Calls to C2R adapters often do not accept exceptional returns.
1133 // We require that their callers must bang for them. But be
1134 // careful, because some VM calls (such as call site linkage) can
1135 // use several kilobytes of stack. But the stack safety zone should
1136 // account for that. See bugs 4446381, 4468289, 4497237.
1137 if (C->output()->need_stack_bang(bangsize)) {
1138 __ generate_stack_overflow_check(bangsize);
1139 }
1140
1141 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
1142 __ save_return_pc();
1143
1144 // The z/Architecture abi is already accounted for in `framesize' via the
1145 // 'out_preserve_stack_slots' declaration.
1146 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
1147
1148 if (C->has_mach_constant_base_node()) {
1149 // NOTE: We set the table base offset here because users might be
1150 // emitted before MachConstantBaseNode.
1151 ConstantTable& constant_table = C->output()->constant_table();
1152 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1153 }
1154
1155 if (C->stub_function() == nullptr) {
1156 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1157 bs->nmethod_entry_barrier(masm);
1158 }
1159
1160 C->output()->set_frame_complete(__ offset());
1161 }
1162 int MachPrologNode::reloc() const {
1163 // Return number of relocatable values contained in this instruction.
1164 return 1; // One reloc entry for load_const(toc).
1165 }
1166
1167 //=============================================================================
1168
1169 #if !defined(PRODUCT)
1170 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1171 os->print_cr("epilog");
1172 os->print("\t");
1173 if (do_polling() && ra_->C->is_method_compilation()) {
1174 os->print_cr("load_from_polling_page Z_R1_scratch");
1175 os->print("\t");
1176 }
1177 }
1178 #endif
1179
1180 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1181 Compile* C = ra_->C;
1182
1183 // If this does safepoint polling, then do it here.
1184 bool need_polling = do_polling() && C->is_method_compilation();
1185
1186 // Pop frame, restore return_pc, and all stuff needed by interpreter.
1187 int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
1188 __ pop_frame_restore_retPC(frame_size_in_bytes);
1189
1190 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1191 __ reserved_stack_check(Z_R14);
1192 }
1193
1194 // Touch the polling page.
1195 if (need_polling) {
1196 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1197 // We need to mark the code position where the load from the safepoint
1198 // polling page was emitted as relocInfo::poll_return_type here.
1199 __ relocate(relocInfo::poll_return_type);
1200 __ load_from_polling_page(Z_R1_scratch);
1201 }
1202 }
1203
1204 int MachEpilogNode::reloc() const {
1205 // Return number of relocatable values contained in this instruction.
1206 return 1; // One for load_from_polling_page.
1207 }
1208
1209 const Pipeline * MachEpilogNode::pipeline() const {
1210 return MachNode::pipeline_class();
1211 }
1212
1213 //=============================================================================
1214
1215 // Figure out which register class each belongs in: rc_int, rc_float, rc_vector, rc_stack.
1216 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1217
1218 static enum RC rc_class(OptoReg::Name reg) {
1219 // Return the register class for the given register. The given register
1220 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1221 // enumeration in adGlobals_s390.hpp.
1222
1223 if (reg == OptoReg::Bad) {
1224 return rc_bad;
1225 }
1226
1227 // We have 32 integer register halves, starting at index 0.
1228 if (reg < 32) {
1229 return rc_int;
1230 }
1231
1232 // We have 32 floating-point register halves, starting at index 32.
1233 if (reg < 32+32) {
1234 return rc_float;
1235 }
1236
1237 // we have 128 vector register halves at index 64
1238 if (reg < 32+32+128) {
1239 return rc_vector;
1240 }
1241
1242 // Between float regs & stack are the flags regs.
1243 assert(OptoReg::is_stack(reg) || reg < 32+32+128, "blow up if spilling flags");
1244 return rc_stack;
1245 }
1246
1247 // Returns size as obtained from z_emit_instr.
1248 static unsigned int z_ld_st_helper(C2_MacroAssembler *masm, const char *op_str, unsigned long opcode,
1249 int reg, int offset, bool do_print, outputStream *os) {
1250
1251 if (masm) {
1252 if (opcode > (1L<<32)) {
1253 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1254 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1255 } else {
1256 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1257 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1258 }
1259 }
1260
1261 #if !defined(PRODUCT)
1262 if (do_print) {
1263 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1264 }
1265 #endif
1266 return (opcode > (1L << 32)) ? 6 : 4;
1267 }
1268
1269 static unsigned int z_mvc_helper(C2_MacroAssembler *masm, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1270 if (masm) {
1271 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1272 }
1273
1274 #if !defined(PRODUCT)
1275 else if (do_print) {
1276 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1277 }
1278 #endif
1279
1280 return 6;
1281 }
1282
1283 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1284 // Get registers to move.
1285 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1286 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1287 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1288 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1289
1290 enum RC src_hi_rc = rc_class(src_hi);
1291 enum RC src_lo_rc = rc_class(src_lo);
1292 enum RC dst_hi_rc = rc_class(dst_hi);
1293 enum RC dst_lo_rc = rc_class(dst_lo);
1294
1295 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1296 bool is64 = (src_hi_rc != rc_bad);
1297 assert(!is64 ||
1298 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1299 "expected aligned-adjacent pairs");
1300
1301 // Generate spill code!
1302 int size = 0;
1303 if (src_lo == dst_lo && src_hi == dst_hi) {
1304 return 0; // Self copy, no move.
1305 }
1306
1307 int src_offset = ra_->reg2offset(src_lo);
1308 int dst_offset = ra_->reg2offset(dst_lo);
1309 bool print = !do_size;
1310 bool src12 = Immediate::is_uimm12(src_offset);
1311 bool dst12 = Immediate::is_uimm12(dst_offset);
1312
1313 const char *mnemo = nullptr;
1314 unsigned long opc = 0;
1315
1316 if (bottom_type()->isa_vect() != nullptr && ideal_reg() == Op_VecX) {
1317 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1318 if (masm != nullptr) {
1319 __ z_mvc(Address(Z_SP, 0, dst_offset), Address(Z_SP, 0, src_offset), 16);
1320 }
1321 size += 6;
1322 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1323 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1324 if (masm != nullptr) {
1325 __ z_vst(Rsrc, Address(Z_SP, 0, dst_offset));
1326 }
1327 size += 6;
1328 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1329 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1330 if (masm != nullptr) {
1331 __ z_vl(Rdst, Address(Z_SP, 0, src_offset));
1332 }
1333 size += 6;
1334 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1335 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1336 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1337 if (masm != nullptr) {
1338 __ z_vlr(Rdst, Rsrc);
1339 }
1340 size += 6;
1341 } else {
1342 ShouldNotReachHere();
1343 }
1344 return size;
1345 }
1346
1347 // Memory->Memory Spill. Use Z_R0 to hold the value.
1348 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1349
1350 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1351 "expected same type of move for high parts");
1352
1353 if (src12 && dst12) {
1354 return z_mvc_helper(masm, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1355 }
1356
1357 int r0 = Z_R0_num;
1358 if (is64) {
1359 return z_ld_st_helper(masm, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1360 z_ld_st_helper(masm, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1361 }
1362
1363 return z_ld_st_helper(masm, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1364 z_ld_st_helper(masm, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1365 }
1366
1367 // Check for float->int copy. Requires a trip through memory.
1368 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1369 Unimplemented(); // Unsafe, do not remove!
1370 }
1371
1372 // Check for integer reg-reg copy.
1373 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1374 if (masm) {
1375 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1376 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1377 __ z_lgr(Rdst, Rsrc);
1378 return 4;
1379 }
1380 #if !defined(PRODUCT)
1381 // else
1382 if (print) {
1383 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1384 }
1385 #endif
1386 return 4;
1387 }
1388
1389 // Check for integer store.
1390 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1391 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1392 "expected same type of move for high parts");
1393
1394 if (is64) {
1395 return z_ld_st_helper(masm, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1396 }
1397
1398 // else
1399 mnemo = dst12 ? "ST " : "STY ";
1400 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1401
1402 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1403 }
1404
1405 // Check for integer load
1406 // Always load cOops zero-extended. That doesn't hurt int loads.
1407 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1408
1409 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1410 "expected same type of move for high parts");
1411
1412 mnemo = is64 ? "LG " : "LLGF";
1413 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1414
1415 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1416 }
1417
1418 // Check for float reg-reg copy.
1419 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1420 if (masm) {
1421 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1422 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1423 __ z_ldr(Rdst, Rsrc);
1424 return 2;
1425 }
1426 #if !defined(PRODUCT)
1427 // else
1428 if (print) {
1429 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1430 }
1431 #endif
1432 return 2;
1433 }
1434
1435 // Check for float store.
1436 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1437 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1438 "expected same type of move for high parts");
1439
1440 if (is64) {
1441 mnemo = dst12 ? "STD " : "STDY ";
1442 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1443 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1444 }
1445 // else
1446
1447 mnemo = dst12 ? "STE " : "STEY ";
1448 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1449 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1450 }
1451
1452 // Check for float load.
1453 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1454 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1455 "expected same type of move for high parts");
1456
1457 if (is64) {
1458 mnemo = src12 ? "LD " : "LDY ";
1459 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1460 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1461 }
1462 // else
1463
1464 mnemo = src12 ? "LE " : "LEY ";
1465 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1466 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1467 }
1468
1469 // --------------------------------------------------------------------
1470 // Check for hi bits still needing moving. Only happens for misaligned
1471 // arguments to native calls.
1472 if (src_hi == dst_hi) {
1473 return 0; // Self copy, no move.
1474 }
1475
1476 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1477 Unimplemented(); // Unsafe, do not remove!
1478
1479 return 0; // never reached, but make the compiler shut up!
1480 }
1481
1482 #if !defined(PRODUCT)
1483 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1484 if (ra_ && ra_->node_regs_max_index() > 0) {
1485 implementation(nullptr, ra_, false, os);
1486 } else {
1487 if (req() == 2 && in(1)) {
1488 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1489 } else {
1490 const char *c = "(";
1491 os->print("N%d = ", _idx);
1492 for (uint i = 1; i < req(); ++i) {
1493 os->print("%sN%d", c, in(i)->_idx);
1494 c = ", ";
1495 }
1496 os->print(")");
1497 }
1498 }
1499 }
1500 #endif
1501
1502 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1503 implementation(masm, ra_, false, nullptr);
1504 }
1505
1506 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1507 return implementation(nullptr, ra_, true, nullptr);
1508 }
1509
1510 //=============================================================================
1511
1512 #if !defined(PRODUCT)
1513 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1514 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1515 }
1516 #endif
1517
1518 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc * ra_) const {
1519 int rem_space = 0;
1520 if (!(ra_->C->output()->in_scratch_emit_size())) {
1521 rem_space = __ code()->insts()->remaining();
1522 if (rem_space <= _count*2 + 8) {
1523 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1524 }
1525 }
1526
1527 for (int i = 0; i < _count; i++) {
1528 __ z_nop();
1529 }
1530
1531 if (!(ra_->C->output()->in_scratch_emit_size())) {
1532 if (rem_space <= _count*2 + 8) {
1533 int rem_space2 = __ code()->insts()->remaining();
1534 tty->print_cr(", after = %d", rem_space2);
1535 }
1536 }
1537 }
1538
1539 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1540 return 2 * _count;
1541 }
1542
1543 #if !defined(PRODUCT)
1544 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1545 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1546 if (ra_ && ra_->node_regs_max_index() > 0) {
1547 int reg = ra_->get_reg_first(this);
1548 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1549 } else {
1550 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1551 }
1552 }
1553 #endif
1554
1555 // Take care of the size function, if you make changes here!
1556 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1557 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1558 int reg = ra_->get_encode(this);
1559 __ z_lay(as_Register(reg), offset, Z_SP);
1560 }
1561
1562 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1563 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1564 return 6;
1565 }
1566
1567 %} // end source section
1568
1569 //----------SOURCE BLOCK-------------------------------------------------------
1570 // This is a block of C++ code which provides values, functions, and
1571 // definitions necessary in the rest of the architecture description
1572
1573 source_hpp %{
1574
1575 // Header information of the source block.
1576 // Method declarations/definitions which are used outside
1577 // the ad-scope can conveniently be defined here.
1578 //
1579 // To keep related declarations/definitions/uses close together,
1580 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1581 #include "opto/convertnode.hpp"
1582 #include "oops/klass.inline.hpp"
1583
1584 //--------------------------------------------------------------
1585 // Used for optimization in Compile::Shorten_branches
1586 //--------------------------------------------------------------
1587
1588 class CallStubImpl {
1589 public:
1590
1591 // call trampolines
1592 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1593 static uint size_call_trampoline() {
1594 return 0; // no call trampolines on this platform
1595 }
1596
1597 // call trampolines
1598 // Number of relocations needed by a call trampoline stub.
1599 static uint reloc_call_trampoline() {
1600 return 0; // No call trampolines on this platform.
1601 }
1602 };
1603
1604 %} // end source_hpp section
1605
1606 source %{
1607
1608 #ifndef PRODUCT
1609 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1610 {
1611 Unimplemented();
1612 }
1613 #endif
1614
1615 void MachVEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc* ra_) const
1616 {
1617 Unimplemented();
1618 }
1619
1620 #if !defined(PRODUCT)
1621 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1622 os->print_cr("---- MachUEPNode ----");
1623 os->print_cr("\tTA");
1624 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1625 os->print_cr("\tBR(Z_R1)");
1626 os->print_cr("\tTA # pad with illtraps");
1627 os->print_cr("\t...");
1628 os->print_cr("\tTA");
1629 os->print_cr("\tLTGR Z_R2, Z_R2");
1630 os->print_cr("\tBRU ic_miss");
1631 }
1632 #endif
1633
1634 void MachUEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1635 // This is Unverified Entry Point
1636 __ ic_check(CodeEntryAlignment);
1637 }
1638
1639 //=============================================================================
1640
1641 %} // interrupt source section
1642
1643 source_hpp %{ // Header information of the source block.
1644
1645 class HandlerImpl {
1646 public:
1647
1648 static int emit_deopt_handler(C2_MacroAssembler* masm);
1649
1650 static uint size_deopt_handler() {
1651 return NativeCall::max_instruction_size() + MacroAssembler::jump_pcrelative_size();
1652 }
1653 };
1654
1655 class Node::PD {
1656 public:
1657 enum NodeFlags {
1658 _last_flag = Node::_last_flag
1659 };
1660 };
1661
1662 %} // end source_hpp section
1663
1664 source %{
1665
1666 // Emit deopt handler code.
1667 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm) {
1668 address base = __ start_a_stub(size_deopt_handler());
1669
1670 if (base == nullptr) {
1671 ciEnv::current()->record_failure("CodeCache is full");
1672 return 0; // CodeBuffer::expand failed
1673 }
1674
1675 int offset = __ offset();
1676
1677 Label start;
1678 __ bind(start);
1679
1680 // Size_deopt_handler() must be exact on zarch, so for simplicity
1681 // we do not use load_const_opt here.
1682 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1683 __ call(Z_R1);
1684
1685 int entry_offset = __ offset();
1686
1687 __ z_bru(start);
1688
1689 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1690 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1691 "out of bounds read in post-call NOP check");
1692
1693 __ end_a_stub();
1694 return entry_offset;
1695 }
1696
1697 //=============================================================================
1698
1699
1700 // Given a register encoding, produce an Integer Register object.
1701 static Register reg_to_register_object(int register_encoding) {
1702 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1703 return as_Register(register_encoding);
1704 }
1705
1706 bool Matcher::match_rule_supported(int opcode) {
1707 if (!has_match_rule(opcode)) {
1708 return false; // no match rule present
1709 }
1710
1711 switch (opcode) {
1712 case Op_ReverseBytesI:
1713 case Op_ReverseBytesL:
1714 case Op_ReverseBytesS:
1715 case Op_ReverseBytesUS:
1716 return UseByteReverseInstruction;
1717 case Op_PopCountI:
1718 case Op_PopCountL:
1719 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1720 return (UsePopCountInstruction && VM_Version::has_PopCount());
1721 case Op_AddVB:
1722 case Op_AddVS:
1723 case Op_AddVI:
1724 case Op_AddVL:
1725 case Op_AddVD:
1726 case Op_SubVB:
1727 case Op_SubVS:
1728 case Op_SubVI:
1729 case Op_SubVL:
1730 case Op_SubVD:
1731 case Op_MulVB:
1732 case Op_MulVS:
1733 case Op_MulVI:
1734 case Op_MulVD:
1735 case Op_DivVD:
1736 case Op_SqrtVD:
1737 case Op_RoundDoubleModeV:
1738 return SuperwordUseVX;
1739 case Op_AddVF:
1740 case Op_SubVF:
1741 case Op_MulVF:
1742 case Op_DivVF:
1743 case Op_SqrtVF:
1744 //PopCountVI supported by z14 onwards.
1745 case Op_PopCountVI:
1746 return (SuperwordUseVX && UseSFPV);
1747 case Op_FmaF:
1748 case Op_FmaD:
1749 return UseFMA;
1750 }
1751
1752 return true; // Per default match rules are supported.
1753 }
1754
1755 bool Matcher::match_rule_supported_auto_vectorization(int opcode, int vlen, BasicType bt) {
1756 return match_rule_supported_vector(opcode, vlen, bt);
1757 }
1758
1759 bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1760 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1761 return false;
1762 }
1763 return true; // Per default match rules are supported.
1764 }
1765
1766 bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
1767 return false;
1768 }
1769
1770 bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
1771 return false;
1772 }
1773
1774 bool Matcher::vector_rearrange_requires_load_shuffle(BasicType elem_bt, int vlen) {
1775 return false;
1776 }
1777
1778 bool Matcher::mask_op_prefers_predicate(int opcode, const TypeVect* vt) {
1779 return false;
1780 }
1781
1782 const RegMask* Matcher::predicate_reg_mask(void) {
1783 return nullptr;
1784 }
1785
1786 // Vector calling convention not yet implemented.
1787 bool Matcher::supports_vector_calling_convention(void) {
1788 return false;
1789 }
1790
1791 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1792 Unimplemented();
1793 return OptoRegPair(0, 0);
1794 }
1795
1796 //----------SUPERWORD HELPERS----------------------------------------
1797
1798 // Vector width in bytes.
1799 int Matcher::vector_width_in_bytes(BasicType bt) {
1800 if (SuperwordUseVX) {
1801 assert(MaxVectorSize == 16, "");
1802 return 16;
1803 } else {
1804 assert(MaxVectorSize == 8, "");
1805 return 8;
1806 }
1807 }
1808
1809 // Vector ideal reg.
1810 uint Matcher::vector_ideal_reg(int size) {
1811 if (SuperwordUseVX) {
1812 assert(MaxVectorSize == 16 && size == 16, "");
1813 return Op_VecX;
1814 } else {
1815 assert(MaxVectorSize == 8 && size == 8, "");
1816 return Op_RegL;
1817 }
1818 }
1819
1820 // Limits on vector size (number of elements) loaded into vector.
1821 int Matcher::max_vector_size(const BasicType bt) {
1822 assert(is_java_primitive(bt), "only primitive type vectors");
1823 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1824 }
1825
1826 int Matcher::min_vector_size(const BasicType bt) {
1827 return max_vector_size(bt); // Same as max.
1828 }
1829
1830 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
1831 return Matcher::max_vector_size(bt);
1832 }
1833
1834 int Matcher::scalable_vector_reg_size(const BasicType bt) {
1835 return -1;
1836 }
1837
1838 // RETURNS: whether this branch offset is short enough that a short
1839 // branch can be used.
1840 //
1841 // If the platform does not provide any short branch variants, then
1842 // this method should return `false' for offset 0.
1843 //
1844 // `Compile::Fill_buffer' will decide on basis of this information
1845 // whether to do the pass `Compile::Shorten_branches' at all.
1846 //
1847 // And `Compile::Shorten_branches' will decide on basis of this
1848 // information whether to replace particular branch sites by short
1849 // ones.
1850 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1851 // On zarch short branches use a 16 bit signed immediate that
1852 // is the pc-relative offset in halfword (= 2 bytes) units.
1853 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1854 }
1855
1856 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1857 ShouldNotReachHere(); // generic vector operands not supported
1858 return nullptr;
1859 }
1860
1861 bool Matcher::is_reg2reg_move(MachNode* m) {
1862 ShouldNotReachHere(); // generic vector operands not supported
1863 return false;
1864 }
1865
1866 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
1867 return false;
1868 }
1869
1870 bool Matcher::is_generic_vector(MachOper* opnd) {
1871 ShouldNotReachHere(); // generic vector operands not supported
1872 return false;
1873 }
1874
1875 // Constants for c2c and c calling conventions.
1876
1877 const MachRegisterNumbers z_iarg_reg[5] = {
1878 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1879 };
1880
1881 const MachRegisterNumbers z_farg_reg[4] = {
1882 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1883 };
1884
1885 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1886
1887 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1888
1889 #ifdef ASSERT
1890 // Return whether or not this register is ever used as an argument.
1891 bool Matcher::can_be_java_arg(int reg) {
1892 // We return true for all registers contained in z_iarg_reg[] and
1893 // z_farg_reg[] and their virtual halves.
1894 // We must include the virtual halves in order to get STDs and LDs
1895 // instead of STWs and LWs in the trampoline stubs.
1896
1897 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1898 reg == Z_R3_num || reg == Z_R3_H_num ||
1899 reg == Z_R4_num || reg == Z_R4_H_num ||
1900 reg == Z_R5_num || reg == Z_R5_H_num ||
1901 reg == Z_R6_num || reg == Z_R6_H_num) {
1902 return true;
1903 }
1904
1905 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1906 reg == Z_F2_num || reg == Z_F2_H_num ||
1907 reg == Z_F4_num || reg == Z_F4_H_num ||
1908 reg == Z_F6_num || reg == Z_F6_H_num) {
1909 return true;
1910 }
1911
1912 return false;
1913 }
1914 #endif
1915
1916 uint Matcher::int_pressure_limit()
1917 {
1918 // Medium size register set, 6 special purpose regs, 3 SOE regs.
1919 // 10 prevents spill-split-recycle sanity check in JVM2008.xml.transform.
1920 return (INTPRESSURE == -1) ? 10 : INTPRESSURE;
1921 }
1922
1923 uint Matcher::float_pressure_limit()
1924 {
1925 return (FLOATPRESSURE == -1) ? 15 : FLOATPRESSURE;
1926 }
1927
1928 // Register for DIVI projection of divmodI
1929 const RegMask& Matcher::divI_proj_mask() {
1930 return _Z_RARG4_INT_REG_mask;
1931 }
1932
1933 // Register for MODI projection of divmodI
1934 const RegMask& Matcher::modI_proj_mask() {
1935 return _Z_RARG3_INT_REG_mask;
1936 }
1937
1938 // Register for DIVL projection of divmodL
1939 const RegMask& Matcher::divL_proj_mask() {
1940 return _Z_RARG4_LONG_REG_mask;
1941 }
1942
1943 // Register for MODL projection of divmodL
1944 const RegMask& Matcher::modL_proj_mask() {
1945 return _Z_RARG3_LONG_REG_mask;
1946 }
1947
1948 // Should the matcher clone input 'm' of node 'n'?
1949 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
1950 if (is_encode_and_store_pattern(n, m)) {
1951 mstack.push(m, Visit);
1952 return true;
1953 }
1954 return false;
1955 }
1956
1957 // Should the Matcher clone shifts on addressing modes, expecting them
1958 // to be subsumed into complex addressing expressions or compute them
1959 // into registers?
1960 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1961 return clone_base_plus_offset_address(m, mstack, address_visited);
1962 }
1963
1964 %} // source
1965
1966 //----------ENCODING BLOCK-----------------------------------------------------
1967 // This block specifies the encoding classes used by the compiler to output
1968 // byte streams. Encoding classes are parameterized macros used by
1969 // Machine Instruction Nodes in order to generate the bit encoding of the
1970 // instruction. Operands specify their base encoding interface with the
1971 // interface keyword. There are currently supported four interfaces,
1972 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1973 // operand to generate a function which returns its register number when
1974 // queried. CONST_INTER causes an operand to generate a function which
1975 // returns the value of the constant when queried. MEMORY_INTER causes an
1976 // operand to generate four functions which return the Base Register, the
1977 // Index Register, the Scale Value, and the Offset Value of the operand when
1978 // queried. COND_INTER causes an operand to generate six functions which
1979 // return the encoding code (ie - encoding bits for the instruction)
1980 // associated with each basic boolean condition for a conditional instruction.
1981 //
1982 // Instructions specify two basic values for encoding. Again, a function
1983 // is available to check if the constant displacement is an oop. They use the
1984 // ins_encode keyword to specify their encoding classes (which must be
1985 // a sequence of enc_class names, and their parameters, specified in
1986 // the encoding block), and they use the
1987 // opcode keyword to specify, in order, their primary, secondary, and
1988 // tertiary opcode. Only the opcode sections which a particular instruction
1989 // needs for encoding need to be specified.
1990 encode %{
1991 enc_class enc_unimplemented %{
1992 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1993 %}
1994
1995 enc_class enc_untested %{
1996 #ifdef ASSERT
1997 __ untested("Untested mach node encoding in AD file.");
1998 #endif
1999 %}
2000
2001 enc_class z_rrform(iRegI dst, iRegI src) %{
2002 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
2003 assert( ($primary >> 16) == 0, "Instruction format error");
2004 z_emit16(masm, $primary |
2005 Assembler::reg($dst$$reg,8,16) |
2006 Assembler::reg($src$$reg,12,16));
2007 %}
2008
2009 enc_class z_rreform(iRegI dst1, iRegI src2) %{
2010 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2011 z_emit32(masm, $primary |
2012 Assembler::reg($dst1$$reg,24,32) |
2013 Assembler::reg($src2$$reg,28,32));
2014 %}
2015
2016 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
2017 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2018 z_emit32(masm, $primary |
2019 Assembler::reg($dst1$$reg,24,32) |
2020 Assembler::reg($src2$$reg,28,32) |
2021 Assembler::reg($src3$$reg,16,32));
2022 %}
2023
2024 enc_class z_riform_signed(iRegI dst, immI16 src) %{
2025 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2026 z_emit32(masm, $primary |
2027 Assembler::reg($dst$$reg,8,32) |
2028 Assembler::simm16($src$$constant,16,32));
2029 %}
2030
2031 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
2032 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2033 z_emit32(masm, $primary |
2034 Assembler::reg($dst$$reg,8,32) |
2035 Assembler::uimm16($src$$constant,16,32));
2036 %}
2037
2038 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
2039 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2040 z_emit48(masm, $primary |
2041 Assembler::reg($dst1$$reg,8,48) |
2042 Assembler::reg($src3$$reg,12,48) |
2043 Assembler::simm16($src2$$constant,16,48));
2044 %}
2045
2046 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
2047 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2048 z_emit48(masm, $primary |
2049 Assembler::reg($dst$$reg,8,48) |
2050 Assembler::simm32($src$$constant,16,48));
2051 %}
2052
2053 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
2054 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2055 z_emit48(masm, $primary |
2056 Assembler::reg($dst$$reg,8,48) |
2057 Assembler::uimm32($src$$constant,16,48));
2058 %}
2059
2060 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
2061 z_emit48(masm, $primary |
2062 Assembler::reg($dst$$reg,8,48) |
2063 Assembler::reg($src1$$reg,12,48) |
2064 Assembler::simm20($src2$$constant));
2065 %}
2066
2067 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
2068 z_emit48(masm, $primary |
2069 Assembler::reg($dst$$reg,8,48) |
2070 Assembler::reg($src$$reg,12,48) |
2071 Assembler::reg($shft$$reg,16,48) |
2072 Assembler::simm20(0));
2073 %}
2074
2075 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2076 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2077 z_emit32(masm, $primary |
2078 Assembler::reg($dst$$reg,8,32) |
2079 Assembler::reg($src1$$reg,12,32) |
2080 Assembler::reg($src2$$reg,16,32) |
2081 Assembler::uimm12($con$$constant,20,32));
2082 %}
2083
2084 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
2085 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2086 z_emit32(masm, $primary |
2087 Assembler::reg($dst$$reg,8,32) |
2088 Assembler::reg($src$$reg,16,32) |
2089 Assembler::uimm12($con$$constant,20,32));
2090 %}
2091
2092 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2093 z_emit48(masm, $primary |
2094 Assembler::reg($dst$$reg,8,48) |
2095 Assembler::reg($src1$$reg,12,48) |
2096 Assembler::reg($src2$$reg,16,48) |
2097 Assembler::simm20($con$$constant));
2098 %}
2099
2100 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
2101 z_emit48(masm, $primary |
2102 Assembler::reg($dst$$reg,8,48) |
2103 Assembler::reg($src$$reg,16,48) |
2104 Assembler::simm20($con$$constant));
2105 %}
2106
2107 // Direct memory arithmetic.
2108 enc_class z_siyform(memoryRSY mem, immI8 src) %{
2109 int disp = $mem$$disp;
2110 Register base = reg_to_register_object($mem$$base);
2111 int con = $src$$constant;
2112
2113 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
2114 z_emit_inst(masm, $primary |
2115 Assembler::regz(base,16,48) |
2116 Assembler::simm20(disp) |
2117 Assembler::simm8(con,8,48));
2118 %}
2119
2120 enc_class z_silform(memoryRS mem, immI16 src) %{
2121 z_emit_inst(masm, $primary |
2122 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
2123 Assembler::uimm12($mem$$disp,20,48) |
2124 Assembler::simm16($src$$constant,32,48));
2125 %}
2126
2127 // Encoder for FP ALU reg/mem instructions (support only short displacements).
2128 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
2129 Register Ridx = $mem$$index$$Register;
2130 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2131 if ($primary > (1L << 32)) {
2132 z_emit_inst(masm, $primary |
2133 Assembler::reg($dst$$reg, 8, 48) |
2134 Assembler::uimm12($mem$$disp, 20, 48) |
2135 Assembler::reg(Ridx, 12, 48) |
2136 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2137 } else {
2138 z_emit_inst(masm, $primary |
2139 Assembler::reg($dst$$reg, 8, 32) |
2140 Assembler::uimm12($mem$$disp, 20, 32) |
2141 Assembler::reg(Ridx, 12, 32) |
2142 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2143 }
2144 %}
2145
2146 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
2147 Register Ridx = $mem$$index$$Register;
2148 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2149 if ($primary > (1L<<32)) {
2150 z_emit_inst(masm, $primary |
2151 Assembler::reg($dst$$reg, 8, 48) |
2152 Assembler::simm20($mem$$disp) |
2153 Assembler::reg(Ridx, 12, 48) |
2154 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2155 } else {
2156 z_emit_inst(masm, $primary |
2157 Assembler::reg($dst$$reg, 8, 32) |
2158 Assembler::uimm12($mem$$disp, 20, 32) |
2159 Assembler::reg(Ridx, 12, 32) |
2160 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2161 }
2162 %}
2163
2164 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
2165 int isize = $secondary > 1L << 32 ? 48 : 32;
2166 Register Ridx = $mem$$index$$Register;
2167 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2168
2169 if (Displacement::is_shortDisp((long)$mem$$disp)) {
2170 z_emit_inst(masm, $secondary |
2171 Assembler::reg($dst$$reg, 8, isize) |
2172 Assembler::uimm12($mem$$disp, 20, isize) |
2173 Assembler::reg(Ridx, 12, isize) |
2174 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2175 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
2176 z_emit_inst(masm, $primary |
2177 Assembler::reg($dst$$reg, 8, 48) |
2178 Assembler::simm20($mem$$disp) |
2179 Assembler::reg(Ridx, 12, 48) |
2180 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2181 } else {
2182 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2183 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2184 z_emit_inst(masm, $secondary |
2185 Assembler::reg($dst$$reg, 8, isize) |
2186 Assembler::uimm12(0, 20, isize) |
2187 Assembler::reg(Z_R1_scratch, 12, isize) |
2188 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2189 }
2190 %}
2191
2192 enc_class z_enc_brul(Label lbl) %{
2193 Label* p = $lbl$$label;
2194
2195 // 'p' is `nullptr' when this encoding class is used only to
2196 // determine the size of the encoded instruction.
2197 // Use a bound dummy label in that case.
2198 Label d;
2199 __ bind(d);
2200 Label& l = (nullptr == p) ? d : *(p);
2201 __ z_brul(l);
2202 %}
2203
2204 enc_class z_enc_bru(Label lbl) %{
2205 Label* p = $lbl$$label;
2206
2207 // 'p' is `nullptr' when this encoding class is used only to
2208 // determine the size of the encoded instruction.
2209 // Use a bound dummy label in that case.
2210 Label d;
2211 __ bind(d);
2212 Label& l = (nullptr == p) ? d : *(p);
2213 __ z_bru(l);
2214 %}
2215
2216 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2217 Label* p = $lbl$$label;
2218
2219 // 'p' is `nullptr' when this encoding class is used only to
2220 // determine the size of the encoded instruction.
2221 // Use a bound dummy label in that case.
2222 Label d;
2223 __ bind(d);
2224 Label& l = (nullptr == p) ? d : *(p);
2225 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2226 %}
2227
2228 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2229 Label* p = $lbl$$label;
2230
2231 // 'p' is `nullptr' when this encoding class is used only to
2232 // determine the size of the encoded instruction.
2233 // Use a bound dummy label in that case.
2234 Label d;
2235 __ bind(d);
2236 Label& l = (nullptr == p) ? d : *(p);
2237 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2238 %}
2239
2240 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2241 Label* p = $lbl$$label;
2242
2243 // 'p' is `nullptr' when this encoding class is used only to
2244 // determine the size of the encoded instruction.
2245 // Use a bound dummy label in that case.
2246 Label d;
2247 __ bind(d);
2248 Label& l = (nullptr == p) ? d : *(p);
2249 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2250 unsigned long instr = $primary;
2251 if (instr == CRJ_ZOPC) {
2252 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2253 } else if (instr == CLRJ_ZOPC) {
2254 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2255 } else if (instr == CGRJ_ZOPC) {
2256 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2257 } else {
2258 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2259 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2260 }
2261 %}
2262
2263 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2264 Label* p = $lbl$$label;
2265
2266 // 'p' is `nullptr' when this encoding class is used only to
2267 // determine the size of the encoded instruction.
2268 // Use a bound dummy label in that case.
2269 Label d;
2270 __ bind(d);
2271 Label& l = (nullptr == p) ? d : *(p);
2272
2273 unsigned long instr = $primary;
2274 if (instr == CR_ZOPC) {
2275 __ z_cr($src1$$Register, $src2$$Register);
2276 } else if (instr == CLR_ZOPC) {
2277 __ z_clr($src1$$Register, $src2$$Register);
2278 } else if (instr == CGR_ZOPC) {
2279 __ z_cgr($src1$$Register, $src2$$Register);
2280 } else {
2281 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2282 __ z_clgr($src1$$Register, $src2$$Register);
2283 }
2284
2285 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2286 %}
2287
2288 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2289 Label* p = $lbl$$label;
2290
2291 // 'p' is `nullptr' when this encoding class is used only to
2292 // determine the size of the encoded instruction.
2293 // Use a bound dummy label in that case.
2294 Label d;
2295 __ bind(d);
2296 Label& l = (nullptr == p) ? d : *(p);
2297
2298 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2299 unsigned long instr = $primary;
2300 if (instr == CIJ_ZOPC) {
2301 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2302 } else if (instr == CLIJ_ZOPC) {
2303 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2304 } else if (instr == CGIJ_ZOPC) {
2305 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2306 } else {
2307 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2308 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2309 }
2310 %}
2311
2312 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2313 Label* p = $lbl$$label;
2314
2315 // 'p' is `nullptr' when this encoding class is used only to
2316 // determine the size of the encoded instruction.
2317 // Use a bound dummy label in that case.
2318 Label d;
2319 __ bind(d);
2320 Label& l = (nullptr == p) ? d : *(p);
2321
2322 unsigned long instr = $primary;
2323 if (instr == CHI_ZOPC) {
2324 __ z_chi($src1$$Register, $src2$$constant);
2325 } else if (instr == CLFI_ZOPC) {
2326 __ z_clfi($src1$$Register, $src2$$constant);
2327 } else if (instr == CGHI_ZOPC) {
2328 __ z_cghi($src1$$Register, $src2$$constant);
2329 } else {
2330 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2331 __ z_clgfi($src1$$Register, $src2$$constant);
2332 }
2333
2334 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2335 %}
2336
2337 // Call from Java to runtime.
2338 enc_class z_enc_java_to_runtime_call(method meth) %{
2339 // Save return pc before call to the place where we need it, since
2340 // callee doesn't.
2341 unsigned int start_off = __ offset();
2342 // Compute size of "larl + stg + call_c_opt".
2343 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2344 __ get_PC(Z_R14, size_of_code);
2345 __ save_return_pc();
2346 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2347
2348 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2349 address call_addr = __ call_c_opt((address)$meth$$method);
2350 if (call_addr == nullptr) {
2351 Compile::current()->env()->record_out_of_memory_failure();
2352 return;
2353 }
2354
2355 #ifdef ASSERT
2356 // Plausibility check for size_of_code assumptions.
2357 unsigned int actual_ret_off = __ offset();
2358 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2359 #endif
2360 %}
2361
2362 enc_class z_enc_java_static_call(method meth) %{
2363 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2364 // whom we intended to call.
2365 int ret_offset = 0;
2366
2367 if (!_method) {
2368 ret_offset = emit_call_reloc(masm, $meth$$method,
2369 relocInfo::runtime_call_w_cp_type, ra_);
2370 } else {
2371 int method_index = resolved_method_index(masm);
2372 if (_optimized_virtual) {
2373 ret_offset = emit_call_reloc(masm, $meth$$method,
2374 opt_virtual_call_Relocation::spec(method_index));
2375 } else {
2376 ret_offset = emit_call_reloc(masm, $meth$$method,
2377 static_call_Relocation::spec(method_index));
2378 }
2379 }
2380 assert(__ inst_mark() != nullptr, "emit_call_reloc must set_inst_mark()");
2381
2382 if (_method) { // Emit stub for static call.
2383 address stub = CompiledDirectCall::emit_to_interp_stub(masm);
2384 if (stub == nullptr) {
2385 __ clear_inst_mark();
2386 ciEnv::current()->record_failure("CodeCache is full");
2387 return;
2388 }
2389 }
2390
2391 __ clear_inst_mark();
2392 %}
2393
2394 // Java dynamic call
2395 enc_class z_enc_java_dynamic_call(method meth) %{
2396 unsigned int start_off = __ offset();
2397
2398 int vtable_index = this->_vtable_index;
2399 if (vtable_index == -4) {
2400 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2401 address virtual_call_oop_addr = nullptr;
2402
2403 AddressLiteral empty_ic((address) Universe::non_oop_word());
2404 virtual_call_oop_addr = __ pc();
2405 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2406 if (!success) {
2407 Compile::current()->env()->record_out_of_memory_failure();
2408 return;
2409 }
2410
2411 // Call to fixup routine. Fixup routine uses ScopeDesc info
2412 // to determine who we intended to call.
2413 int method_index = resolved_method_index(masm);
2414 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2415 unsigned int ret_off = __ offset();
2416 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2417 ret_off += emit_call_reloc(masm, $meth$$method, relocInfo::none, ra_);
2418 __ clear_inst_mark();
2419 assert(_method, "lazy_constant may be wrong when _method==null");
2420 } else {
2421 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2422 // Go through the vtable. Get receiver klass. Receiver already
2423 // checked for non-null. If we'll go thru a C2I adapter, the
2424 // interpreter expects method in Z_method.
2425 // Use Z_method to temporarily hold the klass oop.
2426 // Z_R1_scratch is destroyed.
2427 __ load_klass(Z_method, Z_R2);
2428
2429 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2430 int v_off = entry_offset + in_bytes(vtableEntry::method_offset());
2431
2432 if (Displacement::is_validDisp(v_off) ) {
2433 // Can use load instruction with large offset.
2434 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2435 } else {
2436 // Worse case, must load offset into register.
2437 __ load_const(Z_R1_scratch, v_off);
2438 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2439 }
2440 // NOTE: for vtable dispatches, the vtable entry will never be
2441 // null. However it may very well end up in handle_wrong_method
2442 // if the method is abstract for the particular class.
2443 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2444 // Call target. Either compiled code or C2I adapter.
2445 __ z_basr(Z_R14, Z_R1_scratch);
2446 unsigned int ret_off = __ offset();
2447 }
2448 %}
2449
2450 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2451 Register Rdst = reg_to_register_object($dst$$reg);
2452 Register Rsrc = reg_to_register_object($src$$reg);
2453
2454 // Don't emit code if operands are identical (same register).
2455 if (Rsrc != Rdst) {
2456 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2457
2458 if (VM_Version::has_LoadStoreConditional()) {
2459 __ z_locgr(Rdst, Rsrc, cc);
2460 } else {
2461 // Branch if not (cmp cr).
2462 Label done;
2463 __ z_brc(Assembler::inverse_condition(cc), done);
2464 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2465 __ bind(done);
2466 }
2467 }
2468 %}
2469
2470 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2471 Register Rdst = reg_to_register_object($dst$$reg);
2472 int Csrc = $src$$constant;
2473 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2474 Label done;
2475 // Branch if not (cmp cr).
2476 __ z_brc(Assembler::inverse_condition(cc), done);
2477 if (Csrc == 0) {
2478 // Don't set CC.
2479 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2480 } else {
2481 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2482 }
2483 __ bind(done);
2484 %}
2485
2486 enc_class z_enc_cctobool(iRegI res) %{
2487 Register Rres = reg_to_register_object($res$$reg);
2488
2489 if (VM_Version::has_LoadStoreConditional()) {
2490 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2491 __ load_const_optimized(Rres, 1L); // true (succeed)
2492 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2493 } else {
2494 Label done;
2495 __ load_const_optimized(Rres, 0L); // false (failed)
2496 __ z_brne(done); // Assume true to be the common case.
2497 __ load_const_optimized(Rres, 1L); // true (succeed)
2498 __ bind(done);
2499 }
2500 %}
2501
2502 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2503 Register Rcomp = reg_to_register_object($compare_value$$reg);
2504 Register Rnew = reg_to_register_object($exchange_value$$reg);
2505 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2506
2507 __ z_cs(Rcomp, Rnew, 0, Raddr);
2508 %}
2509
2510 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2511 Register Rcomp = reg_to_register_object($compare_value$$reg);
2512 Register Rnew = reg_to_register_object($exchange_value$$reg);
2513 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2514
2515 __ z_csg(Rcomp, Rnew, 0, Raddr);
2516 %}
2517
2518 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2519 Register Rdst = reg_to_register_object($dst$$reg);
2520 Register Rtmp = reg_to_register_object($tmp$$reg);
2521 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2522 Label retry;
2523
2524 // Iterate until swap succeeds.
2525 __ z_llgf(Rtmp, $mem$$Address); // current contents
2526 __ bind(retry);
2527 // Calculate incremented value.
2528 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2529 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2530 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2531 %}
2532
2533 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2534 Register Rdst = reg_to_register_object($dst$$reg);
2535 Register Rtmp = reg_to_register_object($tmp$$reg);
2536 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2537 Label retry;
2538
2539 // Iterate until swap succeeds.
2540 __ z_lg(Rtmp, $mem$$Address); // current contents
2541 __ bind(retry);
2542 // Calculate incremented value.
2543 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2544 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2545 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2546 %}
2547
2548 %} // encode
2549
2550 source %{
2551
2552 // Check whether outs are all Stores. If so, we can omit clearing the upper
2553 // 32 bits after encoding.
2554 static bool all_outs_are_Stores(const Node *n) {
2555 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2556 Node *out = n->fast_out(k);
2557 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2558 // Most other outs are SpillCopy, but there are various other.
2559 // jvm98 has arond 9% Encodes where we return false.
2560 return false;
2561 }
2562 }
2563 return true;
2564 }
2565
2566 %} // source
2567
2568
2569 //----------FRAME--------------------------------------------------------------
2570 // Definition of frame structure and management information.
2571
2572 frame %{
2573 // These two registers define part of the calling convention between
2574 // compiled code and the interpreter.
2575
2576 // Inline Cache Register
2577 inline_cache_reg(Z_R9); // Z_inline_cache
2578
2579 // Argument pointer for I2C adapters
2580 //
2581 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2582 // interpreter_arg_ptr_reg(Z_R6);
2583
2584 // Optional: name the operand used by cisc-spilling to access
2585 // [stack_pointer + offset].
2586 cisc_spilling_operand_name(indOffset12);
2587
2588 // Number of stack slots consumed by a Monitor enter.
2589 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2590
2591 // Compiled code's Frame Pointer
2592 //
2593 // z/Architecture stack pointer
2594 frame_pointer(Z_R15); // Z_SP
2595
2596 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2597 stack_alignment(frame::alignment_in_bytes);
2598
2599 // A `slot' is assumed 4 bytes here!
2600 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2601
2602 // Number of outgoing stack slots killed above the
2603 // out_preserve_stack_slots for calls to C. Supports the var-args
2604 // backing area for register parms.
2605 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2606
2607 // The after-PROLOG location of the return address. Location of
2608 // return address specifies a type (REG or STACK) and a number
2609 // representing the register number (i.e. - use a register name) or
2610 // stack slot.
2611 return_addr(REG Z_R14);
2612
2613 // Location of native (C/C++) and interpreter return values. This
2614 // is specified to be the same as Java. In the 32-bit VM, long
2615 // values are actually returned from native calls in O0:O1 and
2616 // returned to the interpreter in I0:I1. The copying to and from
2617 // the register pairs is done by the appropriate call and epilog
2618 // opcodes. This simplifies the register allocator.
2619 //
2620 // Use register pair for c return value.
2621 c_return_value %{
2622 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2623 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2624 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2625 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2626 %}
2627
2628 // Use register pair for return value.
2629 // Location of compiled Java return values. Same as C
2630 return_value %{
2631 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2632 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2633 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2634 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2635 %}
2636 %}
2637
2638
2639 //----------ATTRIBUTES---------------------------------------------------------
2640
2641 //----------Operand Attributes-------------------------------------------------
2642 op_attrib op_cost(1); // Required cost attribute
2643
2644 //----------Instruction Attributes---------------------------------------------
2645
2646 // Cost attribute. required.
2647 ins_attrib ins_cost(DEFAULT_COST);
2648
2649 // Is this instruction a non-matching short branch variant of some
2650 // long branch? Not required.
2651 ins_attrib ins_short_branch(0);
2652
2653 // Indicates this is a trap based check node and final control-flow fixup
2654 // must generate a proper fall through.
2655 ins_attrib ins_is_TrapBasedCheckNode(true);
2656
2657 // Attribute of instruction to tell how many constants the instruction will generate.
2658 // (optional attribute). Default: 0.
2659 ins_attrib ins_num_consts(0);
2660
2661 // Required alignment attribute (must be a power of 2)
2662 // specifies the alignment that some part of the instruction (not
2663 // necessarily the start) requires. If > 1, a compute_padding()
2664 // function must be provided for the instruction.
2665 //
2666 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2667 // instructions which depend on the proper alignment, because the
2668 // desired alignment isn't guaranteed for the call to "emit()" during
2669 // the size computation.
2670 ins_attrib ins_alignment(1);
2671
2672 // Enforce/prohibit rematerializations.
2673 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2674 // then rematerialization of that instruction is prohibited and the
2675 // instruction's value will be spilled if necessary.
2676 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2677 // then rematerialization is enforced and the instruction's value will
2678 // never get spilled. a copy of the instruction will be inserted if
2679 // necessary.
2680 // Note: this may result in rematerializations in front of every use.
2681 // (optional attribute)
2682 ins_attrib ins_cannot_rematerialize(false);
2683 ins_attrib ins_should_rematerialize(false);
2684
2685 //----------OPERANDS-----------------------------------------------------------
2686 // Operand definitions must precede instruction definitions for correct
2687 // parsing in the ADLC because operands constitute user defined types
2688 // which are used in instruction definitions.
2689
2690 //----------Simple Operands----------------------------------------------------
2691 // Immediate Operands
2692 // Please note:
2693 // Formats are generated automatically for constants and base registers.
2694 operand vecX() %{
2695 constraint(ALLOC_IN_RC(z_v_reg));
2696 match(VecX);
2697 match(v16TempReg);
2698 match(v17TempReg);
2699 match(v18TempReg);
2700 match(v19TempReg);
2701 match(v20TempReg);
2702 match(v21TempReg);
2703 match(v22TempReg);
2704 match(v23TempReg);
2705 match(v24TempReg);
2706 match(v25TempReg);
2707 format %{ %}
2708 interface(REG_INTER);
2709 %}
2710
2711 operand v16TempReg() %{
2712 constraint(ALLOC_IN_RC(z_vreg_16));
2713 match(VecX);
2714 format %{ %}
2715 interface(REG_INTER);
2716 %}
2717
2718 operand v17TempReg() %{
2719 constraint(ALLOC_IN_RC(z_vreg_17));
2720 match(VecX);
2721 format %{ %}
2722 interface(REG_INTER);
2723 %}
2724
2725 operand v18TempReg() %{
2726 constraint(ALLOC_IN_RC(z_vreg_18));
2727 match(VecX);
2728 format %{ %}
2729 interface(REG_INTER);
2730 %}
2731
2732 operand v19TempReg() %{
2733 constraint(ALLOC_IN_RC(z_vreg_19));
2734 match(VecX);
2735 format %{ %}
2736 interface(REG_INTER);
2737 %}
2738
2739 operand v20TempReg() %{
2740 constraint(ALLOC_IN_RC(z_vreg_20));
2741 match(VecX);
2742 format %{ %}
2743 interface(REG_INTER);
2744 %}
2745
2746 operand v21TempReg() %{
2747 constraint(ALLOC_IN_RC(z_vreg_21));
2748 match(VecX);
2749 format %{ %}
2750 interface(REG_INTER);
2751 %}
2752
2753 operand v22TempReg() %{
2754 constraint(ALLOC_IN_RC(z_vreg_22));
2755 match(VecX);
2756 format %{ %}
2757 interface(REG_INTER);
2758 %}
2759
2760 operand v23TempReg() %{
2761 constraint(ALLOC_IN_RC(z_vreg_23));
2762 match(VecX);
2763 format %{ %}
2764 interface(REG_INTER);
2765 %}
2766
2767 operand v24TempReg() %{
2768 constraint(ALLOC_IN_RC(z_vreg_24));
2769 match(VecX);
2770 format %{ %}
2771 interface(REG_INTER);
2772 %}
2773
2774 operand v25TempReg() %{
2775 constraint(ALLOC_IN_RC(z_vreg_25));
2776 match(VecX);
2777 format %{ %}
2778 interface(REG_INTER);
2779 %}
2780
2781 //----------------------------------------------
2782 // SIGNED (shorter than INT) immediate operands
2783 //----------------------------------------------
2784
2785 // Byte Immediate: constant 'int -1'
2786 operand immB_minus1() %{
2787 // sign-ext constant zero-ext constant
2788 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2789 match(ConI);
2790 op_cost(1);
2791 format %{ %}
2792 interface(CONST_INTER);
2793 %}
2794
2795 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2796 operand immB_n0m1() %{
2797 // sign-ext constant zero-ext constant
2798 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2799 match(ConI);
2800 op_cost(1);
2801 format %{ %}
2802 interface(CONST_INTER);
2803 %}
2804
2805 // Short Immediate: constant 'int -1'
2806 operand immS_minus1() %{
2807 // sign-ext constant zero-ext constant
2808 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2809 match(ConI);
2810 op_cost(1);
2811 format %{ %}
2812 interface(CONST_INTER);
2813 %}
2814
2815 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2816 operand immS_n0m1() %{
2817 // sign-ext constant zero-ext constant
2818 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2819 match(ConI);
2820 op_cost(1);
2821 format %{ %}
2822 interface(CONST_INTER);
2823 %}
2824
2825 //-----------------------------------------
2826 // SIGNED INT immediate operands
2827 //-----------------------------------------
2828
2829 // Integer Immediate: 32-bit
2830 operand immI() %{
2831 match(ConI);
2832 op_cost(1);
2833 format %{ %}
2834 interface(CONST_INTER);
2835 %}
2836
2837 // Int Immediate: 20-bit
2838 operand immI20() %{
2839 predicate(Immediate::is_simm20(n->get_int()));
2840 match(ConI);
2841 op_cost(1);
2842 format %{ %}
2843 interface(CONST_INTER);
2844 %}
2845
2846 // Integer Immediate: 16-bit
2847 operand immI16() %{
2848 predicate(Immediate::is_simm16(n->get_int()));
2849 match(ConI);
2850 op_cost(1);
2851 format %{ %}
2852 interface(CONST_INTER);
2853 %}
2854
2855 // Integer Immediate: 8-bit
2856 operand immI8() %{
2857 predicate(Immediate::is_simm8(n->get_int()));
2858 match(ConI);
2859 op_cost(1);
2860 format %{ %}
2861 interface(CONST_INTER);
2862 %}
2863
2864 // Integer Immediate: constant 'int 0'
2865 operand immI_0() %{
2866 predicate(n->get_int() == 0);
2867 match(ConI);
2868 op_cost(1);
2869 format %{ %}
2870 interface(CONST_INTER);
2871 %}
2872
2873 // Integer Immediate: constant 'int -1'
2874 operand immI_minus1() %{
2875 predicate(n->get_int() == -1);
2876 match(ConI);
2877 op_cost(1);
2878 format %{ %}
2879 interface(CONST_INTER);
2880 %}
2881
2882 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2883 operand immI_n0m1() %{
2884 predicate(n->get_int() != 0 && n->get_int() != -1);
2885 match(ConI);
2886 op_cost(1);
2887 format %{ %}
2888 interface(CONST_INTER);
2889 %}
2890
2891 //-------------------------------------------
2892 // UNSIGNED INT immediate operands
2893 //-------------------------------------------
2894
2895 // Unsigned Integer Immediate: 32-bit
2896 operand uimmI() %{
2897 match(ConI);
2898 op_cost(1);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // Unsigned Integer Immediate: 16-bit
2904 operand uimmI16() %{
2905 predicate(Immediate::is_uimm16(n->get_int()));
2906 match(ConI);
2907 op_cost(1);
2908 format %{ %}
2909 interface(CONST_INTER);
2910 %}
2911
2912 // Unsigned Integer Immediate: 12-bit
2913 operand uimmI12() %{
2914 predicate(Immediate::is_uimm12(n->get_int()));
2915 match(ConI);
2916 op_cost(1);
2917 format %{ %}
2918 interface(CONST_INTER);
2919 %}
2920
2921 // Unsigned Integer Immediate: 12-bit
2922 operand uimmI8() %{
2923 predicate(Immediate::is_uimm8(n->get_int()));
2924 match(ConI);
2925 op_cost(1);
2926 format %{ %}
2927 interface(CONST_INTER);
2928 %}
2929
2930 // Length for SS instructions, given in DWs,
2931 // possible range [1..512], i.e. [8..4096] Bytes
2932 // used range [1..256], i.e. [8..2048] Bytes
2933 // operand type int
2934 // Unsigned Integer Immediate: 9-bit
2935 operand SSlenDW() %{
2936 predicate(Immediate::is_uimm8((julong)n->get_long()-1));
2937 match(ConL);
2938 op_cost(1);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 //------------------------------------------
2944 // (UN)SIGNED INT specific values
2945 //------------------------------------------
2946
2947 // Integer Immediate: the value 1
2948 operand immI_1() %{
2949 predicate(n->get_int() == 1);
2950 match(ConI);
2951 op_cost(1);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 // Integer Immediate: the value 16.
2957 operand immI_16() %{
2958 predicate(n->get_int() == 16);
2959 match(ConI);
2960 op_cost(1);
2961 format %{ %}
2962 interface(CONST_INTER);
2963 %}
2964
2965 // Integer Immediate: the value 24.
2966 operand immI_24() %{
2967 predicate(n->get_int() == 24);
2968 match(ConI);
2969 op_cost(1);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 // Integer Immediate: the values 32-63
2975 operand immI_32_63() %{
2976 predicate(n->get_int() >= 32 && n->get_int() <= 63);
2977 match(ConI);
2978 op_cost(1);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 // Unsigned Integer Immediate: LL-part, extended by 1s.
2984 operand uimmI_LL1() %{
2985 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2986 match(ConI);
2987 op_cost(1);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Unsigned Integer Immediate: LH-part, extended by 1s.
2993 operand uimmI_LH1() %{
2994 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2995 match(ConI);
2996 op_cost(1);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 //------------------------------------------
3002 // SIGNED LONG immediate operands
3003 //------------------------------------------
3004
3005 operand immL() %{
3006 match(ConL);
3007 op_cost(1);
3008 format %{ %}
3009 interface(CONST_INTER);
3010 %}
3011
3012 // Long Immediate: 32-bit
3013 operand immL32() %{
3014 predicate(Immediate::is_simm32(n->get_long()));
3015 match(ConL);
3016 op_cost(1);
3017 format %{ %}
3018 interface(CONST_INTER);
3019 %}
3020
3021 // Long Immediate: 20-bit
3022 operand immL20() %{
3023 predicate(Immediate::is_simm20(n->get_long()));
3024 match(ConL);
3025 op_cost(1);
3026 format %{ %}
3027 interface(CONST_INTER);
3028 %}
3029
3030 // Long Immediate: 16-bit
3031 operand immL16() %{
3032 predicate(Immediate::is_simm16(n->get_long()));
3033 match(ConL);
3034 op_cost(1);
3035 format %{ %}
3036 interface(CONST_INTER);
3037 %}
3038
3039 // Long Immediate: 8-bit
3040 operand immL8() %{
3041 predicate(Immediate::is_simm8(n->get_long()));
3042 match(ConL);
3043 op_cost(1);
3044 format %{ %}
3045 interface(CONST_INTER);
3046 %}
3047
3048 //--------------------------------------------
3049 // UNSIGNED LONG immediate operands
3050 //--------------------------------------------
3051
3052 operand uimmL32() %{
3053 predicate(Immediate::is_uimm32(n->get_long()));
3054 match(ConL);
3055 op_cost(1);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060 // Unsigned Long Immediate: 16-bit
3061 operand uimmL16() %{
3062 predicate(Immediate::is_uimm16(n->get_long()));
3063 match(ConL);
3064 op_cost(1);
3065 format %{ %}
3066 interface(CONST_INTER);
3067 %}
3068
3069 // Unsigned Long Immediate: 12-bit
3070 operand uimmL12() %{
3071 predicate(Immediate::is_uimm12(n->get_long()));
3072 match(ConL);
3073 op_cost(1);
3074 format %{ %}
3075 interface(CONST_INTER);
3076 %}
3077
3078 //-------------------------------------------
3079 // (UN)SIGNED LONG specific values
3080 //-------------------------------------------
3081
3082 // Long Immediate: the value FFFFFFFF
3083 operand immL_FFFFFFFF() %{
3084 predicate(n->get_long() == 0xFFFFFFFFL);
3085 match(ConL);
3086 op_cost(1);
3087 format %{ %}
3088 interface(CONST_INTER);
3089 %}
3090
3091 operand immL_0() %{
3092 predicate(n->get_long() == 0L);
3093 match(ConL);
3094 op_cost(1);
3095 format %{ %}
3096 interface(CONST_INTER);
3097 %}
3098
3099 // Unsigned Long Immediate: LL-part, extended by 1s.
3100 operand uimmL_LL1() %{
3101 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
3102 match(ConL);
3103 op_cost(1);
3104 format %{ %}
3105 interface(CONST_INTER);
3106 %}
3107
3108 // Unsigned Long Immediate: LH-part, extended by 1s.
3109 operand uimmL_LH1() %{
3110 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
3111 match(ConL);
3112 op_cost(1);
3113 format %{ %}
3114 interface(CONST_INTER);
3115 %}
3116
3117 // Unsigned Long Immediate: HL-part, extended by 1s.
3118 operand uimmL_HL1() %{
3119 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
3120 match(ConL);
3121 op_cost(1);
3122 format %{ %}
3123 interface(CONST_INTER);
3124 %}
3125
3126 // Unsigned Long Immediate: HH-part, extended by 1s.
3127 operand uimmL_HH1() %{
3128 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
3129 match(ConL);
3130 op_cost(1);
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Long Immediate: low 32-bit mask
3136 operand immL_32bits() %{
3137 predicate(n->get_long() == 0xFFFFFFFFL);
3138 match(ConL);
3139 op_cost(1);
3140 format %{ %}
3141 interface(CONST_INTER);
3142 %}
3143
3144 //--------------------------------------
3145 // POINTER immediate operands
3146 //--------------------------------------
3147
3148 // Pointer Immediate: 64-bit
3149 operand immP() %{
3150 match(ConP);
3151 op_cost(1);
3152 format %{ %}
3153 interface(CONST_INTER);
3154 %}
3155
3156 // Pointer Immediate: 16-bit
3157 operand immP16() %{
3158 predicate(Immediate::is_uimm16(n->get_ptr()));
3159 match(ConP);
3160 op_cost(1);
3161 format %{ %}
3162 interface(CONST_INTER);
3163 %}
3164
3165 // Pointer Immediate: 8-bit
3166 operand immP8() %{
3167 predicate(Immediate::is_uimm8(n->get_ptr()));
3168 match(ConP);
3169 op_cost(1);
3170 format %{ %}
3171 interface(CONST_INTER);
3172 %}
3173
3174 //-----------------------------------
3175 // POINTER specific values
3176 //-----------------------------------
3177
3178 // Pointer Immediate: nullptr
3179 operand immP0() %{
3180 predicate(n->get_ptr() == 0);
3181 match(ConP);
3182 op_cost(1);
3183 format %{ %}
3184 interface(CONST_INTER);
3185 %}
3186
3187 //---------------------------------------------
3188 // NARROW POINTER immediate operands
3189 //---------------------------------------------
3190
3191 // Narrow Pointer Immediate
3192 operand immN() %{
3193 match(ConN);
3194 op_cost(1);
3195 format %{ %}
3196 interface(CONST_INTER);
3197 %}
3198
3199 operand immNKlass() %{
3200 match(ConNKlass);
3201 op_cost(1);
3202 format %{ %}
3203 interface(CONST_INTER);
3204 %}
3205
3206 // Narrow Pointer Immediate
3207 operand immN8() %{
3208 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3209 match(ConN);
3210 op_cost(1);
3211 format %{ %}
3212 interface(CONST_INTER);
3213 %}
3214
3215 // Narrow Null Pointer Immediate
3216 operand immN0() %{
3217 predicate(n->get_narrowcon() == 0);
3218 match(ConN);
3219 op_cost(1);
3220 format %{ %}
3221 interface(CONST_INTER);
3222 %}
3223
3224 // FLOAT and DOUBLE immediate operands
3225
3226 // Double Immediate
3227 operand immD() %{
3228 match(ConD);
3229 op_cost(1);
3230 format %{ %}
3231 interface(CONST_INTER);
3232 %}
3233
3234 // Double Immediate: +-0
3235 operand immDpm0() %{
3236 predicate(n->getd() == 0);
3237 match(ConD);
3238 op_cost(1);
3239 format %{ %}
3240 interface(CONST_INTER);
3241 %}
3242
3243 // Double Immediate: +0
3244 operand immDp0() %{
3245 predicate(jlong_cast(n->getd()) == 0);
3246 match(ConD);
3247 op_cost(1);
3248 format %{ %}
3249 interface(CONST_INTER);
3250 %}
3251
3252 // Float Immediate
3253 operand immF() %{
3254 match(ConF);
3255 op_cost(1);
3256 format %{ %}
3257 interface(CONST_INTER);
3258 %}
3259
3260 // Float Immediate: +-0
3261 operand immFpm0() %{
3262 predicate(n->getf() == 0);
3263 match(ConF);
3264 op_cost(1);
3265 format %{ %}
3266 interface(CONST_INTER);
3267 %}
3268
3269 // Float Immediate: +0
3270 operand immFp0() %{
3271 predicate(jint_cast(n->getf()) == 0);
3272 match(ConF);
3273 op_cost(1);
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3277
3278 // End of Immediate Operands
3279
3280 // Integer Register Operands
3281 // Integer Register
3282 operand iRegI() %{
3283 constraint(ALLOC_IN_RC(z_int_reg));
3284 match(RegI);
3285 match(noArg_iRegI);
3286 match(rarg1RegI);
3287 match(rarg2RegI);
3288 match(rarg3RegI);
3289 match(rarg4RegI);
3290 match(rarg5RegI);
3291 match(noOdd_iRegI);
3292 match(revenRegI);
3293 match(roddRegI);
3294 format %{ %}
3295 interface(REG_INTER);
3296 %}
3297
3298 operand noArg_iRegI() %{
3299 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3300 match(RegI);
3301 format %{ %}
3302 interface(REG_INTER);
3303 %}
3304
3305 // revenRegI and roddRegI constitute and even-odd-pair.
3306 operand revenRegI() %{
3307 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3308 match(iRegI);
3309 format %{ %}
3310 interface(REG_INTER);
3311 %}
3312
3313 // revenRegI and roddRegI constitute and even-odd-pair.
3314 operand roddRegI() %{
3315 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3316 match(iRegI);
3317 format %{ %}
3318 interface(REG_INTER);
3319 %}
3320
3321 operand rarg1RegI() %{
3322 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3323 match(iRegI);
3324 format %{ %}
3325 interface(REG_INTER);
3326 %}
3327
3328 operand rarg2RegI() %{
3329 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3330 match(iRegI);
3331 format %{ %}
3332 interface(REG_INTER);
3333 %}
3334
3335 operand rarg3RegI() %{
3336 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3337 match(iRegI);
3338 format %{ %}
3339 interface(REG_INTER);
3340 %}
3341
3342 operand rarg4RegI() %{
3343 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3344 match(iRegI);
3345 format %{ %}
3346 interface(REG_INTER);
3347 %}
3348
3349 operand rarg5RegI() %{
3350 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3351 match(iRegI);
3352 format %{ %}
3353 interface(REG_INTER);
3354 %}
3355
3356 operand noOdd_iRegI() %{
3357 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3358 match(RegI);
3359 match(revenRegI);
3360 format %{ %}
3361 interface(REG_INTER);
3362 %}
3363
3364 // Pointer Register
3365 operand iRegP() %{
3366 constraint(ALLOC_IN_RC(z_ptr_reg));
3367 match(RegP);
3368 match(noArg_iRegP);
3369 match(rarg1RegP);
3370 match(rarg2RegP);
3371 match(rarg3RegP);
3372 match(rarg4RegP);
3373 match(rarg5RegP);
3374 match(revenRegP);
3375 match(roddRegP);
3376 match(r10TempRegP);
3377 match(r11TempRegP);
3378 format %{ %}
3379 interface(REG_INTER);
3380 %}
3381
3382 // thread operand
3383 operand threadRegP() %{
3384 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3385 match(RegP);
3386 format %{ "Z_THREAD" %}
3387 interface(REG_INTER);
3388 %}
3389
3390 operand r10TempRegP() %{
3391 constraint(ALLOC_IN_RC(z_r10_ptr_reg));
3392 match(iRegP);
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 operand r11TempRegP() %{
3398 constraint(ALLOC_IN_RC(z_r11_ptr_reg));
3399 match(iRegP);
3400 format %{ %}
3401 interface(REG_INTER);
3402 %}
3403
3404 operand noArg_iRegP() %{
3405 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3406 match(iRegP);
3407 format %{ %}
3408 interface(REG_INTER);
3409 %}
3410
3411 operand rarg1RegP() %{
3412 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3413 match(iRegP);
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 operand rarg2RegP() %{
3419 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3420 match(iRegP);
3421 format %{ %}
3422 interface(REG_INTER);
3423 %}
3424
3425 operand rarg3RegP() %{
3426 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3427 match(iRegP);
3428 format %{ %}
3429 interface(REG_INTER);
3430 %}
3431
3432 operand rarg4RegP() %{
3433 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3434 match(iRegP);
3435 format %{ %}
3436 interface(REG_INTER);
3437 %}
3438
3439 operand rarg5RegP() %{
3440 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3441 match(iRegP);
3442 format %{ %}
3443 interface(REG_INTER);
3444 %}
3445
3446 operand memoryRegP() %{
3447 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3448 match(RegP);
3449 match(iRegP);
3450 match(threadRegP);
3451 format %{ %}
3452 interface(REG_INTER);
3453 %}
3454
3455 // revenRegP and roddRegP constitute and even-odd-pair.
3456 operand revenRegP() %{
3457 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3458 match(iRegP);
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // revenRegP and roddRegP constitute and even-odd-pair.
3464 operand roddRegP() %{
3465 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3466 match(iRegP);
3467 format %{ %}
3468 interface(REG_INTER);
3469 %}
3470
3471 operand iRegN() %{
3472 constraint(ALLOC_IN_RC(z_int_reg));
3473 match(RegN);
3474 match(noArg_iRegN);
3475 match(rarg1RegN);
3476 match(rarg2RegN);
3477 match(rarg3RegN);
3478 match(rarg4RegN);
3479 match(rarg5RegN);
3480 format %{ %}
3481 interface(REG_INTER);
3482 %}
3483
3484 operand noArg_iRegN() %{
3485 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3486 match(iRegN);
3487 format %{ %}
3488 interface(REG_INTER);
3489 %}
3490
3491 operand rarg1RegN() %{
3492 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3493 match(iRegN);
3494 format %{ %}
3495 interface(REG_INTER);
3496 %}
3497
3498 operand rarg2RegN() %{
3499 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3500 match(iRegN);
3501 format %{ %}
3502 interface(REG_INTER);
3503 %}
3504
3505 operand rarg3RegN() %{
3506 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3507 match(iRegN);
3508 format %{ %}
3509 interface(REG_INTER);
3510 %}
3511
3512 operand rarg4RegN() %{
3513 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3514 match(iRegN);
3515 format %{ %}
3516 interface(REG_INTER);
3517 %}
3518
3519 operand rarg5RegN() %{
3520 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3521 match(iRegN);
3522 format %{ %}
3523 interface(REG_INTER);
3524 %}
3525
3526 // Long Register
3527 operand iRegL() %{
3528 constraint(ALLOC_IN_RC(z_long_reg));
3529 match(RegL);
3530 match(revenRegL);
3531 match(roddRegL);
3532 match(allRoddRegL);
3533 match(rarg1RegL);
3534 match(rarg5RegL);
3535 format %{ %}
3536 interface(REG_INTER);
3537 %}
3538
3539 // revenRegL and roddRegL constitute and even-odd-pair.
3540 operand revenRegL() %{
3541 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3542 match(iRegL);
3543 format %{ %}
3544 interface(REG_INTER);
3545 %}
3546
3547 // revenRegL and roddRegL constitute and even-odd-pair.
3548 operand roddRegL() %{
3549 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3550 match(iRegL);
3551 format %{ %}
3552 interface(REG_INTER);
3553 %}
3554
3555 // available odd registers for iRegL
3556 operand allRoddRegL() %{
3557 constraint(ALLOC_IN_RC(z_long_odd_reg));
3558 match(iRegL);
3559 format %{ %}
3560 interface(REG_INTER);
3561 %}
3562
3563 operand rarg1RegL() %{
3564 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3565 match(iRegL);
3566 format %{ %}
3567 interface(REG_INTER);
3568 %}
3569
3570 operand rarg5RegL() %{
3571 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3572 match(iRegL);
3573 format %{ %}
3574 interface(REG_INTER);
3575 %}
3576
3577 // Condition Code Flag Registers
3578 operand flagsReg() %{
3579 constraint(ALLOC_IN_RC(z_condition_reg));
3580 match(RegFlags);
3581 format %{ "CR" %}
3582 interface(REG_INTER);
3583 %}
3584
3585 operand regD() %{
3586 constraint(ALLOC_IN_RC(z_dbl_reg));
3587 match(RegD);
3588 format %{ %}
3589 interface(REG_INTER);
3590 %}
3591
3592 operand regF() %{
3593 constraint(ALLOC_IN_RC(z_flt_reg));
3594 match(RegF);
3595 format %{ %}
3596 interface(REG_INTER);
3597 %}
3598
3599 // Special Registers
3600
3601 // Method Register
3602 operand inline_cache_regP(iRegP reg) %{
3603 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3604 match(reg);
3605 format %{ %}
3606 interface(REG_INTER);
3607 %}
3608
3609 //----------Complex Operands---------------------------------------------------
3610
3611 // Indirect Memory Reference
3612 operand indirect(memoryRegP base) %{
3613 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3614 match(base);
3615 op_cost(1);
3616 format %{ "#0[,$base]" %}
3617 interface(MEMORY_INTER) %{
3618 base($base);
3619 index(0xffffFFFF); // noreg
3620 scale(0x0);
3621 disp(0x0);
3622 %}
3623 %}
3624
3625 // Indirect with Offset (long)
3626 operand indOffset20(memoryRegP base, immL20 offset) %{
3627 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3628 match(AddP base offset);
3629 op_cost(1);
3630 format %{ "$offset[,$base]" %}
3631 interface(MEMORY_INTER) %{
3632 base($base);
3633 index(0xffffFFFF); // noreg
3634 scale(0x0);
3635 disp($offset);
3636 %}
3637 %}
3638
3639 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3640 predicate(Matcher::narrow_oop_use_complex_address());
3641 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3642 match(AddP (DecodeN base) offset);
3643 op_cost(1);
3644 format %{ "$offset[,$base]" %}
3645 interface(MEMORY_INTER) %{
3646 base($base);
3647 index(0xffffFFFF); // noreg
3648 scale(0x0);
3649 disp($offset);
3650 %}
3651 %}
3652
3653 // Indirect with Offset (short)
3654 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3655 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3656 match(AddP base offset);
3657 op_cost(1);
3658 format %{ "$offset[[,$base]]" %}
3659 interface(MEMORY_INTER) %{
3660 base($base);
3661 index(0xffffFFFF); // noreg
3662 scale(0x0);
3663 disp($offset);
3664 %}
3665 %}
3666
3667 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3668 predicate(Matcher::narrow_oop_use_complex_address());
3669 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3670 match(AddP (DecodeN base) offset);
3671 op_cost(1);
3672 format %{ "$offset[[,$base]]" %}
3673 interface(MEMORY_INTER) %{
3674 base($base);
3675 index(0xffffFFFF); // noreg
3676 scale(0x0);
3677 disp($offset);
3678 %}
3679 %}
3680
3681 // Indirect with Register Index
3682 operand indIndex(memoryRegP base, iRegL index) %{
3683 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3684 match(AddP base index);
3685 op_cost(1);
3686 format %{ "#0[($index,$base)]" %}
3687 interface(MEMORY_INTER) %{
3688 base($base);
3689 index($index);
3690 scale(0x0);
3691 disp(0x0);
3692 %}
3693 %}
3694
3695 // Indirect with Offset (long) and index
3696 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3697 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3698 match(AddP (AddP base index) offset);
3699 op_cost(1);
3700 format %{ "$offset[($index,$base)]" %}
3701 interface(MEMORY_INTER) %{
3702 base($base);
3703 index($index);
3704 scale(0x0);
3705 disp($offset);
3706 %}
3707 %}
3708
3709 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3710 predicate(Matcher::narrow_oop_use_complex_address());
3711 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3712 match(AddP (AddP (DecodeN base) index) offset);
3713 op_cost(1);
3714 format %{ "$offset[($index,$base)]" %}
3715 interface(MEMORY_INTER) %{
3716 base($base);
3717 index($index);
3718 scale(0x0);
3719 disp($offset);
3720 %}
3721 %}
3722
3723 // Indirect with Offset (short) and index
3724 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3725 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3726 match(AddP (AddP base index) offset);
3727 op_cost(1);
3728 format %{ "$offset[[($index,$base)]]" %}
3729 interface(MEMORY_INTER) %{
3730 base($base);
3731 index($index);
3732 scale(0x0);
3733 disp($offset);
3734 %}
3735 %}
3736
3737 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3738 predicate(Matcher::narrow_oop_use_complex_address());
3739 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3740 match(AddP (AddP (DecodeN base) index) offset);
3741 op_cost(1);
3742 format %{ "$offset[[($index,$base)]]" %}
3743 interface(MEMORY_INTER) %{
3744 base($base);
3745 index($index);
3746 scale(0x0);
3747 disp($offset);
3748 %}
3749 %}
3750
3751 //----------Special Memory Operands--------------------------------------------
3752
3753 // Stack Slot Operand
3754 // This operand is used for loading and storing temporary values on
3755 // the stack where a match requires a value to flow through memory.
3756 operand stackSlotI(sRegI reg) %{
3757 constraint(ALLOC_IN_RC(stack_slots));
3758 op_cost(1);
3759 format %{ "[$reg(stackSlotI)]" %}
3760 interface(MEMORY_INTER) %{
3761 base(0xf); // Z_SP
3762 index(0xffffFFFF); // noreg
3763 scale(0x0);
3764 disp($reg); // stack offset
3765 %}
3766 %}
3767
3768 operand stackSlotP(sRegP reg) %{
3769 constraint(ALLOC_IN_RC(stack_slots));
3770 op_cost(1);
3771 format %{ "[$reg(stackSlotP)]" %}
3772 interface(MEMORY_INTER) %{
3773 base(0xf); // Z_SP
3774 index(0xffffFFFF); // noreg
3775 scale(0x0);
3776 disp($reg); // Stack Offset
3777 %}
3778 %}
3779
3780 operand stackSlotF(sRegF reg) %{
3781 constraint(ALLOC_IN_RC(stack_slots));
3782 op_cost(1);
3783 format %{ "[$reg(stackSlotF)]" %}
3784 interface(MEMORY_INTER) %{
3785 base(0xf); // Z_SP
3786 index(0xffffFFFF); // noreg
3787 scale(0x0);
3788 disp($reg); // Stack Offset
3789 %}
3790 %}
3791
3792 operand stackSlotD(sRegD reg) %{
3793 constraint(ALLOC_IN_RC(stack_slots));
3794 op_cost(1);
3795 //match(RegD);
3796 format %{ "[$reg(stackSlotD)]" %}
3797 interface(MEMORY_INTER) %{
3798 base(0xf); // Z_SP
3799 index(0xffffFFFF); // noreg
3800 scale(0x0);
3801 disp($reg); // Stack Offset
3802 %}
3803 %}
3804
3805 operand stackSlotL(sRegL reg) %{
3806 constraint(ALLOC_IN_RC(stack_slots));
3807 op_cost(1); //match(RegL);
3808 format %{ "[$reg(stackSlotL)]" %}
3809 interface(MEMORY_INTER) %{
3810 base(0xf); // Z_SP
3811 index(0xffffFFFF); // noreg
3812 scale(0x0);
3813 disp($reg); // Stack Offset
3814 %}
3815 %}
3816
3817 // Operands for expressing Control Flow
3818 // NOTE: Label is a predefined operand which should not be redefined in
3819 // the AD file. It is generically handled within the ADLC.
3820
3821 //----------Conditional Branch Operands----------------------------------------
3822 // Comparison Op - This is the operation of the comparison, and is limited to
3823 // the following set of codes:
3824 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3825 //
3826 // Other attributes of the comparison, such as unsignedness, are specified
3827 // by the comparison instruction that sets a condition code flags register.
3828 // That result is represented by a flags operand whose subtype is appropriate
3829 // to the unsignedness (etc.) of the comparison.
3830 //
3831 // Later, the instruction which matches both the Comparison Op (a Bool) and
3832 // the flags (produced by the Cmp) specifies the coding of the comparison op
3833 // by matching a specific subtype of Bool operand below.
3834
3835 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3836 // have mask bit #3 set.
3837 operand cmpOpT() %{
3838 match(Bool);
3839 format %{ "" %}
3840 interface(COND_INTER) %{
3841 equal(0x8); // Assembler::bcondEqual
3842 not_equal(0x6); // Assembler::bcondNotEqual
3843 less(0x4); // Assembler::bcondLow
3844 greater_equal(0xa); // Assembler::bcondNotLow
3845 less_equal(0xc); // Assembler::bcondNotHigh
3846 greater(0x2); // Assembler::bcondHigh
3847 overflow(0x1); // Assembler::bcondOverflow
3848 no_overflow(0xe); // Assembler::bcondNotOverflow
3849 %}
3850 %}
3851
3852 // When used for floating point comparisons: unordered is treated as less.
3853 operand cmpOpF() %{
3854 match(Bool);
3855 format %{ "" %}
3856 interface(COND_INTER) %{
3857 equal(0x8);
3858 not_equal(0x7); // Includes 'unordered'.
3859 less(0x5); // Includes 'unordered'.
3860 greater_equal(0xa);
3861 less_equal(0xd); // Includes 'unordered'.
3862 greater(0x2);
3863 overflow(0x0); // Not meaningful on z/Architecture.
3864 no_overflow(0x0); // leave unchanged (zero) therefore
3865 %}
3866 %}
3867
3868 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3869 operand cmpOp() %{
3870 match(Bool);
3871 format %{ "" %}
3872 interface(COND_INTER) %{
3873 equal(0x8);
3874 not_equal(0x7); // Includes 'unordered'.
3875 less(0x5); // Includes 'unordered'.
3876 greater_equal(0xa);
3877 less_equal(0xd); // Includes 'unordered'.
3878 greater(0x2);
3879 overflow(0x1); // Assembler::bcondOverflow
3880 no_overflow(0xe); // Assembler::bcondNotOverflow
3881 %}
3882 %}
3883
3884 //----------OPERAND CLASSES----------------------------------------------------
3885 // Operand Classes are groups of operands that are used to simplify
3886 // instruction definitions by not requiring the AD writer to specify
3887 // separate instructions for every form of operand when the
3888 // instruction accepts multiple operand types with the same basic
3889 // encoding and format. The classic case of this is memory operands.
3890 // Indirect is not included since its use is limited to Compare & Swap
3891
3892 // Most general memory operand, allows base, index, and long displacement.
3893 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3894 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3895
3896 // General memory operand, allows base, index, and short displacement.
3897 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3898
3899 // Memory operand, allows only base and long displacement.
3900 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3901
3902 // Memory operand, allows only base and short displacement.
3903 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3904
3905 // Operand classes to match encode and decode.
3906 opclass iRegN_P2N(iRegN);
3907 opclass iRegP_N2P(iRegP);
3908
3909
3910 //----------PIPELINE-----------------------------------------------------------
3911 pipeline %{
3912
3913 //----------ATTRIBUTES---------------------------------------------------------
3914 attributes %{
3915 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3916 variable_size_instructions;
3917 instruction_unit_size = 2;
3918
3919 // Meaningless on z/Architecture.
3920 max_instructions_per_bundle = 1;
3921
3922 // The z/Architecture processor fetches 64 bytes...
3923 instruction_fetch_unit_size = 64;
3924
3925 // ...in one line.
3926 instruction_fetch_units = 1
3927 %}
3928
3929 //----------RESOURCES----------------------------------------------------------
3930 // Resources are the functional units available to the machine.
3931 resources(
3932 Z_BR, // branch unit
3933 Z_CR, // condition unit
3934 Z_FX1, // integer arithmetic unit 1
3935 Z_FX2, // integer arithmetic unit 2
3936 Z_LDST1, // load/store unit 1
3937 Z_LDST2, // load/store unit 2
3938 Z_FP1, // float arithmetic unit 1
3939 Z_FP2, // float arithmetic unit 2
3940 Z_LDST = Z_LDST1 | Z_LDST2,
3941 Z_FX = Z_FX1 | Z_FX2,
3942 Z_FP = Z_FP1 | Z_FP2
3943 );
3944
3945 //----------PIPELINE DESCRIPTION-----------------------------------------------
3946 // Pipeline Description specifies the stages in the machine's pipeline.
3947 pipe_desc(
3948 // TODO: adapt
3949 Z_IF, // instruction fetch
3950 Z_IC,
3951 Z_D0, // decode
3952 Z_D1, // decode
3953 Z_D2, // decode
3954 Z_D3, // decode
3955 Z_Xfer1,
3956 Z_GD, // group definition
3957 Z_MP, // map
3958 Z_ISS, // issue
3959 Z_RF, // resource fetch
3960 Z_EX1, // execute (all units)
3961 Z_EX2, // execute (FP, LDST)
3962 Z_EX3, // execute (FP, LDST)
3963 Z_EX4, // execute (FP)
3964 Z_EX5, // execute (FP)
3965 Z_EX6, // execute (FP)
3966 Z_WB, // write back
3967 Z_Xfer2,
3968 Z_CP
3969 );
3970
3971 //----------PIPELINE CLASSES---------------------------------------------------
3972 // Pipeline Classes describe the stages in which input and output are
3973 // referenced by the hardware pipeline.
3974
3975 // Providing the `ins_pipe' declarations in the instruction
3976 // specifications seems to be of little use. So we use
3977 // `pipe_class_dummy' for all our instructions at present.
3978 pipe_class pipe_class_dummy() %{
3979 single_instruction;
3980 fixed_latency(4);
3981 %}
3982
3983 // SIGTRAP based implicit range checks in compiled code.
3984 // Currently, no pipe classes are used on z/Architecture.
3985 pipe_class pipe_class_trap() %{
3986 single_instruction;
3987 %}
3988
3989 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3990 single_instruction;
3991 dst : Z_EX1(write);
3992 src1 : Z_RF(read);
3993 src2 : Z_RF(read);
3994 Z_FX : Z_RF;
3995 %}
3996
3997 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
3998 single_instruction;
3999 mem : Z_RF(read);
4000 dst : Z_WB(write);
4001 Z_LDST : Z_RF;
4002 %}
4003
4004 define %{
4005 MachNop = pipe_class_dummy;
4006 %}
4007
4008 %}
4009
4010 //----------INSTRUCTIONS-------------------------------------------------------
4011
4012 //---------- Chain stack slots between similar types --------
4013
4014 // Load integer from stack slot.
4015 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
4016 match(Set dst src);
4017 ins_cost(MEMORY_REF_COST);
4018 // TODO: s390 port size(FIXED_SIZE);
4019 format %{ "L $dst,$src\t # stk reload int" %}
4020 opcode(L_ZOPC);
4021 ins_encode(z_form_rt_mem(dst, src));
4022 ins_pipe(pipe_class_dummy);
4023 %}
4024
4025 // Store integer to stack slot.
4026 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
4027 match(Set dst src);
4028 ins_cost(MEMORY_REF_COST);
4029 // TODO: s390 port size(FIXED_SIZE);
4030 format %{ "ST $src,$dst\t # stk spill int" %}
4031 opcode(ST_ZOPC);
4032 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4033 ins_pipe(pipe_class_dummy);
4034 %}
4035
4036 // Load long from stack slot.
4037 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
4038 match(Set dst src);
4039 ins_cost(MEMORY_REF_COST);
4040 // TODO: s390 port size(FIXED_SIZE);
4041 format %{ "LG $dst,$src\t # stk reload long" %}
4042 opcode(LG_ZOPC);
4043 ins_encode(z_form_rt_mem(dst, src));
4044 ins_pipe(pipe_class_dummy);
4045 %}
4046
4047 // Store long to stack slot.
4048 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
4049 match(Set dst src);
4050 ins_cost(MEMORY_REF_COST);
4051 size(6);
4052 format %{ "STG $src,$dst\t # stk spill long" %}
4053 opcode(STG_ZOPC);
4054 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4055 ins_pipe(pipe_class_dummy);
4056 %}
4057
4058 // Load pointer from stack slot, 64-bit encoding.
4059 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
4060 match(Set dst src);
4061 ins_cost(MEMORY_REF_COST);
4062 // TODO: s390 port size(FIXED_SIZE);
4063 format %{ "LG $dst,$src\t # stk reload ptr" %}
4064 opcode(LG_ZOPC);
4065 ins_encode(z_form_rt_mem(dst, src));
4066 ins_pipe(pipe_class_dummy);
4067 %}
4068
4069 // Store pointer to stack slot.
4070 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
4071 match(Set dst src);
4072 ins_cost(MEMORY_REF_COST);
4073 // TODO: s390 port size(FIXED_SIZE);
4074 format %{ "STG $src,$dst\t # stk spill ptr" %}
4075 opcode(STG_ZOPC);
4076 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4077 ins_pipe(pipe_class_dummy);
4078 %}
4079
4080 // Float types
4081
4082 // Load float value from stack slot.
4083 instruct stkF_to_regF(regF dst, stackSlotF src) %{
4084 match(Set dst src);
4085 ins_cost(MEMORY_REF_COST);
4086 size(4);
4087 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
4088 opcode(LE_ZOPC);
4089 ins_encode(z_form_rt_mem(dst, src));
4090 ins_pipe(pipe_class_dummy);
4091 %}
4092
4093 // Store float value to stack slot.
4094 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4095 match(Set dst src);
4096 ins_cost(MEMORY_REF_COST);
4097 size(4);
4098 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4099 opcode(STE_ZOPC);
4100 ins_encode(z_form_rt_mem(src, dst));
4101 ins_pipe(pipe_class_dummy);
4102 %}
4103
4104 // Load double value from stack slot.
4105 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4106 match(Set dst src);
4107 ins_cost(MEMORY_REF_COST);
4108 // TODO: s390 port size(FIXED_SIZE);
4109 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4110 opcode(LD_ZOPC);
4111 ins_encode(z_form_rt_mem(dst, src));
4112 ins_pipe(pipe_class_dummy);
4113 %}
4114
4115 // Store double value to stack slot.
4116 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4117 match(Set dst src);
4118 ins_cost(MEMORY_REF_COST);
4119 size(4);
4120 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4121 opcode(STD_ZOPC);
4122 ins_encode(z_form_rt_mem(src, dst));
4123 ins_pipe(pipe_class_dummy);
4124 %}
4125
4126 //----------Load/Store/Move Instructions---------------------------------------
4127
4128 //----------Load Instructions--------------------------------------------------
4129
4130 //------------------
4131 // MEMORY
4132 //------------------
4133
4134 // BYTE
4135 // Load Byte (8bit signed)
4136 instruct loadB(iRegI dst, memory mem) %{
4137 match(Set dst (LoadB mem));
4138 ins_cost(MEMORY_REF_COST);
4139 size(Z_DISP3_SIZE);
4140 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4141 opcode(LB_ZOPC, LB_ZOPC);
4142 ins_encode(z_form_rt_mem_opt(dst, mem));
4143 ins_pipe(pipe_class_dummy);
4144 %}
4145
4146 // Load Byte (8bit signed)
4147 instruct loadB2L(iRegL dst, memory mem) %{
4148 match(Set dst (ConvI2L (LoadB mem)));
4149 ins_cost(MEMORY_REF_COST);
4150 size(Z_DISP3_SIZE);
4151 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4152 opcode(LGB_ZOPC, LGB_ZOPC);
4153 ins_encode(z_form_rt_mem_opt(dst, mem));
4154 ins_pipe(pipe_class_dummy);
4155 %}
4156
4157 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4158 instruct loadUB(iRegI dst, memory mem) %{
4159 match(Set dst (LoadUB mem));
4160 ins_cost(MEMORY_REF_COST);
4161 size(Z_DISP3_SIZE);
4162 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4163 opcode(LLGC_ZOPC, LLGC_ZOPC);
4164 ins_encode(z_form_rt_mem_opt(dst, mem));
4165 ins_pipe(pipe_class_dummy);
4166 %}
4167
4168 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4169 instruct loadUB2L(iRegL dst, memory mem) %{
4170 match(Set dst (ConvI2L (LoadUB mem)));
4171 ins_cost(MEMORY_REF_COST);
4172 size(Z_DISP3_SIZE);
4173 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4174 opcode(LLGC_ZOPC, LLGC_ZOPC);
4175 ins_encode(z_form_rt_mem_opt(dst, mem));
4176 ins_pipe(pipe_class_dummy);
4177 %}
4178
4179 // CHAR/SHORT
4180
4181 // Load Short (16bit signed)
4182 instruct loadS(iRegI dst, memory mem) %{
4183 match(Set dst (LoadS mem));
4184 ins_cost(MEMORY_REF_COST);
4185 size(Z_DISP_SIZE);
4186 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4187 opcode(LHY_ZOPC, LH_ZOPC);
4188 ins_encode(z_form_rt_mem_opt(dst, mem));
4189 ins_pipe(pipe_class_dummy);
4190 %}
4191
4192 // Load Short (16bit signed)
4193 instruct loadS2L(iRegL dst, memory mem) %{
4194 match(Set dst (ConvI2L (LoadS mem)));
4195 ins_cost(MEMORY_REF_COST);
4196 size(Z_DISP3_SIZE);
4197 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4198 opcode(LGH_ZOPC, LGH_ZOPC);
4199 ins_encode(z_form_rt_mem_opt(dst, mem));
4200 ins_pipe(pipe_class_dummy);
4201 %}
4202
4203 // Load Char (16bit Unsigned)
4204 instruct loadUS(iRegI dst, memory mem) %{
4205 match(Set dst (LoadUS mem));
4206 ins_cost(MEMORY_REF_COST);
4207 size(Z_DISP3_SIZE);
4208 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4209 opcode(LLGH_ZOPC, LLGH_ZOPC);
4210 ins_encode(z_form_rt_mem_opt(dst, mem));
4211 ins_pipe(pipe_class_dummy);
4212 %}
4213
4214 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4215 instruct loadUS2L(iRegL dst, memory mem) %{
4216 match(Set dst (ConvI2L (LoadUS mem)));
4217 ins_cost(MEMORY_REF_COST);
4218 size(Z_DISP3_SIZE);
4219 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4220 opcode(LLGH_ZOPC, LLGH_ZOPC);
4221 ins_encode(z_form_rt_mem_opt(dst, mem));
4222 ins_pipe(pipe_class_dummy);
4223 %}
4224
4225 // INT
4226
4227 // Load Integer
4228 instruct loadI(iRegI dst, memory mem) %{
4229 match(Set dst (LoadI mem));
4230 ins_cost(MEMORY_REF_COST);
4231 size(Z_DISP_SIZE);
4232 format %{ "L(Y) $dst,$mem\t #" %}
4233 opcode(LY_ZOPC, L_ZOPC);
4234 ins_encode(z_form_rt_mem_opt(dst, mem));
4235 ins_pipe(pipe_class_dummy);
4236 %}
4237
4238 // Load and convert to long.
4239 instruct loadI2L(iRegL dst, memory mem) %{
4240 match(Set dst (ConvI2L (LoadI mem)));
4241 ins_cost(MEMORY_REF_COST);
4242 size(Z_DISP3_SIZE);
4243 format %{ "LGF $dst,$mem\t #" %}
4244 opcode(LGF_ZOPC, LGF_ZOPC);
4245 ins_encode(z_form_rt_mem_opt(dst, mem));
4246 ins_pipe(pipe_class_dummy);
4247 %}
4248
4249 // Load Unsigned Integer into a Long Register
4250 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4251 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4252 ins_cost(MEMORY_REF_COST);
4253 size(Z_DISP3_SIZE);
4254 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4255 opcode(LLGF_ZOPC, LLGF_ZOPC);
4256 ins_encode(z_form_rt_mem_opt(dst, mem));
4257 ins_pipe(pipe_class_dummy);
4258 %}
4259
4260 // range = array length (=jint)
4261 // Load Range
4262 instruct loadRange(iRegI dst, memory mem) %{
4263 match(Set dst (LoadRange mem));
4264 ins_cost(MEMORY_REF_COST);
4265 size(Z_DISP_SIZE);
4266 format %{ "L(Y) $dst,$mem\t # range" %}
4267 opcode(LY_ZOPC, L_ZOPC);
4268 ins_encode(z_form_rt_mem_opt(dst, mem));
4269 ins_pipe(pipe_class_dummy);
4270 %}
4271
4272 // LONG
4273
4274 // Load Long - aligned
4275 instruct loadL(iRegL dst, memory mem) %{
4276 match(Set dst (LoadL mem));
4277 ins_cost(MEMORY_REF_COST);
4278 size(Z_DISP3_SIZE);
4279 format %{ "LG $dst,$mem\t # long" %}
4280 opcode(LG_ZOPC, LG_ZOPC);
4281 ins_encode(z_form_rt_mem_opt(dst, mem));
4282 ins_pipe(pipe_class_dummy);
4283 %}
4284
4285 // Load Long - UNaligned
4286 instruct loadL_unaligned(iRegL dst, memory mem) %{
4287 match(Set dst (LoadL_unaligned mem));
4288 ins_cost(MEMORY_REF_COST);
4289 size(Z_DISP3_SIZE);
4290 format %{ "LG $dst,$mem\t # unaligned long" %}
4291 opcode(LG_ZOPC, LG_ZOPC);
4292 ins_encode(z_form_rt_mem_opt(dst, mem));
4293 ins_pipe(pipe_class_dummy);
4294 %}
4295
4296
4297 // PTR
4298
4299 // Load Pointer
4300 instruct loadP(iRegP dst, memory mem) %{
4301 match(Set dst (LoadP mem));
4302 predicate(n->as_Load()->barrier_data() == 0);
4303 ins_cost(MEMORY_REF_COST);
4304 size(Z_DISP3_SIZE);
4305 format %{ "LG $dst,$mem\t # ptr" %}
4306 opcode(LG_ZOPC, LG_ZOPC);
4307 ins_encode(z_form_rt_mem_opt(dst, mem));
4308 ins_pipe(pipe_class_dummy);
4309 %}
4310
4311 // LoadP + CastP2L
4312 instruct castP2X_loadP(iRegL dst, memory mem) %{
4313 match(Set dst (CastP2X (LoadP mem)));
4314 predicate(n->as_Load()->barrier_data() == 0);
4315 ins_cost(MEMORY_REF_COST);
4316 size(Z_DISP3_SIZE);
4317 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4318 opcode(LG_ZOPC, LG_ZOPC);
4319 ins_encode(z_form_rt_mem_opt(dst, mem));
4320 ins_pipe(pipe_class_dummy);
4321 %}
4322
4323 // Load Klass Pointer
4324 instruct loadKlass(iRegP dst, memory mem) %{
4325 match(Set dst (LoadKlass mem));
4326 ins_cost(MEMORY_REF_COST);
4327 size(Z_DISP3_SIZE);
4328 format %{ "LG $dst,$mem\t # klass ptr" %}
4329 opcode(LG_ZOPC, LG_ZOPC);
4330 ins_encode(z_form_rt_mem_opt(dst, mem));
4331 ins_pipe(pipe_class_dummy);
4332 %}
4333
4334 instruct loadTOC(iRegL dst) %{
4335 effect(DEF dst);
4336 ins_cost(DEFAULT_COST);
4337 // TODO: s390 port size(FIXED_SIZE);
4338 // TODO: check why this attribute causes many unnecessary rematerializations.
4339 //
4340 // The graphs I saw just had high register pressure. Further the
4341 // register TOC is loaded to is overwritten by the constant short
4342 // after. Here something as round robin register allocation might
4343 // help. But rematerializing seems not to hurt, jack even seems to
4344 // improve slightly.
4345 //
4346 // Without this flag we get spill-split recycle sanity check
4347 // failures in
4348 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4349 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4350 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4351 // stack. Later tlsLoadP is rematerialized, leaving the register
4352 // allocator with TOC on the stack and a badly placed reload.
4353 ins_should_rematerialize(true);
4354 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4355 ins_encode %{ __ load_toc($dst$$Register); %}
4356 ins_pipe(pipe_class_dummy);
4357 %}
4358
4359 // FLOAT
4360
4361 // Load Float
4362 instruct loadF(regF dst, memory mem) %{
4363 match(Set dst (LoadF mem));
4364 ins_cost(MEMORY_REF_COST);
4365 size(Z_DISP_SIZE);
4366 format %{ "LE(Y) $dst,$mem" %}
4367 opcode(LEY_ZOPC, LE_ZOPC);
4368 ins_encode(z_form_rt_mem_opt(dst, mem));
4369 ins_pipe(pipe_class_dummy);
4370 %}
4371
4372 // DOUBLE
4373
4374 // Load Double
4375 instruct loadD(regD dst, memory mem) %{
4376 match(Set dst (LoadD mem));
4377 ins_cost(MEMORY_REF_COST);
4378 size(Z_DISP_SIZE);
4379 format %{ "LD(Y) $dst,$mem" %}
4380 opcode(LDY_ZOPC, LD_ZOPC);
4381 ins_encode(z_form_rt_mem_opt(dst, mem));
4382 ins_pipe(pipe_class_dummy);
4383 %}
4384
4385 // Load Double - UNaligned
4386 instruct loadD_unaligned(regD dst, memory mem) %{
4387 match(Set dst (LoadD_unaligned mem));
4388 ins_cost(MEMORY_REF_COST);
4389 size(Z_DISP_SIZE);
4390 format %{ "LD(Y) $dst,$mem" %}
4391 opcode(LDY_ZOPC, LD_ZOPC);
4392 ins_encode(z_form_rt_mem_opt(dst, mem));
4393 ins_pipe(pipe_class_dummy);
4394 %}
4395
4396
4397 //----------------------
4398 // IMMEDIATES
4399 //----------------------
4400
4401 instruct loadConI(iRegI dst, immI src) %{
4402 match(Set dst src);
4403 ins_cost(DEFAULT_COST);
4404 size(6);
4405 format %{ "LGFI $dst,$src\t # (int)" %}
4406 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4407 ins_pipe(pipe_class_dummy);
4408 %}
4409
4410 instruct loadConI16(iRegI dst, immI16 src) %{
4411 match(Set dst src);
4412 ins_cost(DEFAULT_COST_LOW);
4413 size(4);
4414 format %{ "LGHI $dst,$src\t # (int)" %}
4415 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4416 ins_pipe(pipe_class_dummy);
4417 %}
4418
4419 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4420 match(Set dst src);
4421 effect(KILL cr);
4422 ins_cost(DEFAULT_COST_LOW);
4423 size(4);
4424 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4425 opcode(XGR_ZOPC);
4426 ins_encode(z_rreform(dst, dst));
4427 ins_pipe(pipe_class_dummy);
4428 %}
4429
4430 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4431 match(Set dst src);
4432 // TODO: s390 port size(FIXED_SIZE);
4433 format %{ "LLILL $dst,$src" %}
4434 opcode(LLILL_ZOPC);
4435 ins_encode(z_riform_unsigned(dst, src) );
4436 ins_pipe(pipe_class_dummy);
4437 %}
4438
4439 // Load long constant from TOC with pcrelative address.
4440 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4441 match(Set dst src);
4442 ins_cost(MEMORY_REF_COST_LO);
4443 size(6);
4444 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4445 ins_encode %{
4446 address long_address = __ long_constant($src$$constant);
4447 if (long_address == nullptr) {
4448 Compile::current()->env()->record_out_of_memory_failure();
4449 return;
4450 }
4451 __ load_long_pcrelative($dst$$Register, long_address);
4452 %}
4453 ins_pipe(pipe_class_dummy);
4454 %}
4455
4456 instruct loadConL32(iRegL dst, immL32 src) %{
4457 match(Set dst src);
4458 ins_cost(DEFAULT_COST);
4459 size(6);
4460 format %{ "LGFI $dst,$src\t # (long)" %}
4461 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4462 ins_pipe(pipe_class_dummy);
4463 %}
4464
4465 instruct loadConL16(iRegL dst, immL16 src) %{
4466 match(Set dst src);
4467 ins_cost(DEFAULT_COST_LOW);
4468 size(4);
4469 format %{ "LGHI $dst,$src\t # (long)" %}
4470 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4471 ins_pipe(pipe_class_dummy);
4472 %}
4473
4474 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4475 match(Set dst src);
4476 effect(KILL cr);
4477 ins_cost(DEFAULT_COST_LOW);
4478 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4479 opcode(XGR_ZOPC);
4480 ins_encode(z_rreform(dst, dst));
4481 ins_pipe(pipe_class_dummy);
4482 %}
4483
4484 // Load ptr constant from TOC with pc relative address.
4485 // Special handling for oop constants required.
4486 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4487 match(Set dst src);
4488 ins_cost(MEMORY_REF_COST_LO);
4489 size(6);
4490 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4491 ins_encode %{
4492 relocInfo::relocType constant_reloc = $src->constant_reloc();
4493 if (constant_reloc == relocInfo::oop_type) {
4494 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4495 bool success = __ load_oop_from_toc($dst$$Register, a);
4496 if (!success) {
4497 Compile::current()->env()->record_out_of_memory_failure();
4498 return;
4499 }
4500 } else if (constant_reloc == relocInfo::metadata_type) {
4501 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4502 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4503 if (const_toc_addr == nullptr) {
4504 Compile::current()->env()->record_out_of_memory_failure();
4505 return;
4506 }
4507 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4508 } else { // Non-oop pointers, e.g. card mark base, heap top.
4509 address long_address = __ long_constant((jlong)$src$$constant);
4510 if (long_address == nullptr) {
4511 Compile::current()->env()->record_out_of_memory_failure();
4512 return;
4513 }
4514 __ load_long_pcrelative($dst$$Register, long_address);
4515 }
4516 %}
4517 ins_pipe(pipe_class_dummy);
4518 %}
4519
4520 // We don't use immP16 to avoid problems with oops.
4521 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4522 match(Set dst src);
4523 effect(KILL cr);
4524 size(4);
4525 format %{ "XGR $dst,$dst\t # null pointer" %}
4526 opcode(XGR_ZOPC);
4527 ins_encode(z_rreform(dst, dst));
4528 ins_pipe(pipe_class_dummy);
4529 %}
4530
4531 //----------Load Float Constant Instructions-------------------------------------------------
4532
4533 // We may not specify this instruction via an `expand' rule. If we do,
4534 // code selection will forget that this instruction needs a floating
4535 // point constant inserted into the code buffer. So `Shorten_branches'
4536 // will fail.
4537 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4538 match(Set dst src);
4539 effect(KILL cr);
4540 ins_cost(MEMORY_REF_COST);
4541 size(6);
4542 // If this instruction rematerializes, it prolongs the live range
4543 // of the toc node, causing illegal graphs.
4544 ins_cannot_rematerialize(true);
4545 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4546 ins_encode %{
4547 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4548 %}
4549 ins_pipe(pipe_class_dummy);
4550 %}
4551
4552 // E may not specify this instruction via an `expand' rule. If we do,
4553 // code selection will forget that this instruction needs a floating
4554 // point constant inserted into the code buffer. So `Shorten_branches'
4555 // will fail.
4556 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4557 match(Set dst src);
4558 effect(KILL cr);
4559 ins_cost(MEMORY_REF_COST);
4560 size(6);
4561 // If this instruction rematerializes, it prolongs the live range
4562 // of the toc node, causing illegal graphs.
4563 ins_cannot_rematerialize(true);
4564 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4565 ins_encode %{
4566 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4567 %}
4568 ins_pipe(pipe_class_dummy);
4569 %}
4570
4571 // Special case: Load Const 0.0F
4572
4573 // There's a special instr to clear a FP register.
4574 instruct loadConF0(regF dst, immFp0 src) %{
4575 match(Set dst src);
4576 ins_cost(DEFAULT_COST_LOW);
4577 size(4);
4578 format %{ "LZER $dst,$src\t # clear to zero" %}
4579 opcode(LZER_ZOPC);
4580 ins_encode(z_rreform(dst, Z_F0));
4581 ins_pipe(pipe_class_dummy);
4582 %}
4583
4584 // There's a special instr to clear a FP register.
4585 instruct loadConD0(regD dst, immDp0 src) %{
4586 match(Set dst src);
4587 ins_cost(DEFAULT_COST_LOW);
4588 size(4);
4589 format %{ "LZDR $dst,$src\t # clear to zero" %}
4590 opcode(LZDR_ZOPC);
4591 ins_encode(z_rreform(dst, Z_F0));
4592 ins_pipe(pipe_class_dummy);
4593 %}
4594
4595
4596 //----------Store Instructions-------------------------------------------------
4597
4598 // BYTE
4599
4600 // Store Byte
4601 instruct storeB(memory mem, iRegI src) %{
4602 match(Set mem (StoreB mem src));
4603 ins_cost(MEMORY_REF_COST);
4604 size(Z_DISP_SIZE);
4605 format %{ "STC(Y) $src,$mem\t # byte" %}
4606 opcode(STCY_ZOPC, STC_ZOPC);
4607 ins_encode(z_form_rt_mem_opt(src, mem));
4608 ins_pipe(pipe_class_dummy);
4609 %}
4610
4611 // CHAR/SHORT
4612
4613 // Store Char/Short
4614 instruct storeC(memory mem, iRegI src) %{
4615 match(Set mem (StoreC mem src));
4616 ins_cost(MEMORY_REF_COST);
4617 size(Z_DISP_SIZE);
4618 format %{ "STH(Y) $src,$mem\t # short" %}
4619 opcode(STHY_ZOPC, STH_ZOPC);
4620 ins_encode(z_form_rt_mem_opt(src, mem));
4621 ins_pipe(pipe_class_dummy);
4622 %}
4623
4624 // INT
4625
4626 // Store Integer
4627 instruct storeI(memory mem, iRegI src) %{
4628 match(Set mem (StoreI mem src));
4629 ins_cost(MEMORY_REF_COST);
4630 size(Z_DISP_SIZE);
4631 format %{ "ST(Y) $src,$mem\t # int" %}
4632 opcode(STY_ZOPC, ST_ZOPC);
4633 ins_encode(z_form_rt_mem_opt(src, mem));
4634 ins_pipe(pipe_class_dummy);
4635 %}
4636
4637 // LONG
4638
4639 // Store Long
4640 instruct storeL(memory mem, iRegL src) %{
4641 match(Set mem (StoreL mem src));
4642 ins_cost(MEMORY_REF_COST);
4643 size(Z_DISP3_SIZE);
4644 format %{ "STG $src,$mem\t # long" %}
4645 opcode(STG_ZOPC, STG_ZOPC);
4646 ins_encode(z_form_rt_mem_opt(src, mem));
4647 ins_pipe(pipe_class_dummy);
4648 %}
4649
4650 // PTR
4651
4652 // Store Pointer
4653 instruct storeP(memory dst, memoryRegP src) %{
4654 match(Set dst (StoreP dst src));
4655 predicate(n->as_Store()->barrier_data() == 0);
4656 ins_cost(MEMORY_REF_COST);
4657 size(Z_DISP3_SIZE);
4658 format %{ "STG $src,$dst\t # ptr" %}
4659 opcode(STG_ZOPC, STG_ZOPC);
4660 ins_encode(z_form_rt_mem_opt(src, dst));
4661 ins_pipe(pipe_class_dummy);
4662 %}
4663
4664 // FLOAT
4665
4666 // Store Float
4667 instruct storeF(memory mem, regF src) %{
4668 match(Set mem (StoreF mem src));
4669 ins_cost(MEMORY_REF_COST);
4670 size(Z_DISP_SIZE);
4671 format %{ "STE(Y) $src,$mem\t # float" %}
4672 opcode(STEY_ZOPC, STE_ZOPC);
4673 ins_encode(z_form_rt_mem_opt(src, mem));
4674 ins_pipe(pipe_class_dummy);
4675 %}
4676
4677 // DOUBLE
4678
4679 // Store Double
4680 instruct storeD(memory mem, regD src) %{
4681 match(Set mem (StoreD mem src));
4682 ins_cost(MEMORY_REF_COST);
4683 size(Z_DISP_SIZE);
4684 format %{ "STD(Y) $src,$mem\t # double" %}
4685 opcode(STDY_ZOPC, STD_ZOPC);
4686 ins_encode(z_form_rt_mem_opt(src, mem));
4687 ins_pipe(pipe_class_dummy);
4688 %}
4689
4690 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4691
4692 // Should support match rule for PrefetchAllocation.
4693 // Still needed after 8068977 for PrefetchAllocate.
4694 instruct prefetchAlloc(memory mem) %{
4695 match(PrefetchAllocation mem);
4696 predicate(VM_Version::has_Prefetch());
4697 ins_cost(DEFAULT_COST);
4698 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4699 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4700 ins_pipe(pipe_class_dummy);
4701 %}
4702
4703 //----------Memory init instructions------------------------------------------
4704
4705 // Move Immediate to 1-byte memory.
4706 instruct memInitB(memoryRSY mem, immI8 src) %{
4707 match(Set mem (StoreB mem src));
4708 ins_cost(MEMORY_REF_COST);
4709 // TODO: s390 port size(VARIABLE_SIZE);
4710 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4711 ins_encode %{
4712 if (Immediate::is_uimm12((long)$mem$$disp)) {
4713 __ z_mvi($mem$$Address, $src$$constant);
4714 } else {
4715 __ z_mviy($mem$$Address, $src$$constant);
4716 }
4717 %}
4718 ins_pipe(pipe_class_dummy);
4719 %}
4720
4721 // Move Immediate to 2-byte memory.
4722 instruct memInitC(memoryRS mem, immI16 src) %{
4723 match(Set mem (StoreC mem src));
4724 ins_cost(MEMORY_REF_COST);
4725 size(6);
4726 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4727 opcode(MVHHI_ZOPC);
4728 ins_encode(z_silform(mem, src));
4729 ins_pipe(pipe_class_dummy);
4730 %}
4731
4732 // Move Immediate to 4-byte memory.
4733 instruct memInitI(memoryRS mem, immI16 src) %{
4734 match(Set mem (StoreI mem src));
4735 ins_cost(MEMORY_REF_COST);
4736 size(6);
4737 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4738 opcode(MVHI_ZOPC);
4739 ins_encode(z_silform(mem, src));
4740 ins_pipe(pipe_class_dummy);
4741 %}
4742
4743
4744 // Move Immediate to 8-byte memory.
4745 instruct memInitL(memoryRS mem, immL16 src) %{
4746 match(Set mem (StoreL mem src));
4747 ins_cost(MEMORY_REF_COST);
4748 size(6);
4749 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4750 opcode(MVGHI_ZOPC);
4751 ins_encode(z_silform(mem, src));
4752 ins_pipe(pipe_class_dummy);
4753 %}
4754
4755 // Move Immediate to 8-byte memory.
4756 instruct memInitP(memoryRS mem, immP16 src) %{
4757 match(Set mem (StoreP mem src));
4758 predicate(n->as_Store()->barrier_data() == 0);
4759 ins_cost(MEMORY_REF_COST);
4760 size(6);
4761 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4762 opcode(MVGHI_ZOPC);
4763 ins_encode(z_silform(mem, src));
4764 ins_pipe(pipe_class_dummy);
4765 %}
4766
4767
4768 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4769
4770 // See cOop encoding classes for elaborate comment.
4771
4772 // Moved here because it is needed in expand rules for encode.
4773 // Long negation.
4774 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4775 match(Set dst (SubL zero src));
4776 effect(KILL cr);
4777 size(4);
4778 format %{ "NEG $dst, $src\t # long" %}
4779 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4780 ins_pipe(pipe_class_dummy);
4781 %}
4782
4783 // Load Compressed Pointer
4784
4785 // Load narrow oop
4786 instruct loadN(iRegN dst, memory mem) %{
4787 match(Set dst (LoadN mem));
4788 predicate(n->as_Load()->barrier_data() == 0);
4789 ins_cost(MEMORY_REF_COST);
4790 size(Z_DISP3_SIZE);
4791 format %{ "LoadN $dst,$mem\t # (cOop)" %}
4792 opcode(LLGF_ZOPC, LLGF_ZOPC);
4793 ins_encode(z_form_rt_mem_opt(dst, mem));
4794 ins_pipe(pipe_class_dummy);
4795 %}
4796
4797 // Load narrow Klass Pointer
4798 instruct loadNKlass(iRegN dst, memory mem) %{
4799 predicate(!UseCompactObjectHeaders);
4800 match(Set dst (LoadNKlass mem));
4801 ins_cost(MEMORY_REF_COST);
4802 size(Z_DISP3_SIZE);
4803 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
4804 opcode(LLGF_ZOPC, LLGF_ZOPC);
4805 ins_encode(z_form_rt_mem_opt(dst, mem));
4806 ins_pipe(pipe_class_dummy);
4807 %}
4808
4809 instruct loadNKlassCompactHeaders(iRegN dst, memory mem, flagsReg cr) %{
4810 match(Set dst (LoadNKlass mem));
4811 predicate(UseCompactObjectHeaders);
4812 effect(KILL cr);
4813 ins_cost(MEMORY_REF_COST);
4814 format %{ "load_narrow_klass_compact $dst,$mem \t# compressed class ptr" %}
4815 // TODO: size()
4816 ins_encode %{
4817 __ block_comment("load_narrow_klass_compact_c2 {");
4818 __ load_narrow_klass_compact_c2($dst$$Register, $mem$$Address);
4819 __ block_comment("} load_narrow_klass_compact");
4820 %}
4821 ins_pipe(pipe_class_dummy);
4822 %}
4823
4824 // Load constant Compressed Pointer
4825
4826 instruct loadConN(iRegN dst, immN src) %{
4827 match(Set dst src);
4828 ins_cost(DEFAULT_COST);
4829 size(6);
4830 format %{ "loadConN $dst,$src\t # (cOop)" %}
4831 ins_encode %{
4832 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4833 __ relocate(cOop.rspec(), 1);
4834 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4835 %}
4836 ins_pipe(pipe_class_dummy);
4837 %}
4838
4839 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4840 match(Set dst src);
4841 effect(KILL cr);
4842 ins_cost(DEFAULT_COST_LOW);
4843 size(4);
4844 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4845 opcode(XGR_ZOPC);
4846 ins_encode(z_rreform(dst, dst));
4847 ins_pipe(pipe_class_dummy);
4848 %}
4849
4850 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4851 match(Set dst src);
4852 ins_cost(DEFAULT_COST);
4853 size(6);
4854 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4855 ins_encode %{
4856 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4857 __ relocate(NKlass.rspec(), 1);
4858 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4859 %}
4860 ins_pipe(pipe_class_dummy);
4861 %}
4862
4863 // Load and Decode Compressed Pointer
4864 // optimized variants for Unscaled cOops
4865
4866 instruct decodeLoadN(iRegP dst, memory mem) %{
4867 match(Set dst (DecodeN (LoadN mem)));
4868 predicate(false && (CompressedOops::base()==nullptr) && (CompressedOops::shift()==0));
4869 ins_cost(MEMORY_REF_COST);
4870 size(Z_DISP3_SIZE);
4871 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
4872 opcode(LLGF_ZOPC, LLGF_ZOPC);
4873 ins_encode(z_form_rt_mem_opt(dst, mem));
4874 ins_pipe(pipe_class_dummy);
4875 %}
4876
4877 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4878 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4879 predicate(false && (CompressedKlassPointers::base()==nullptr)&&(CompressedKlassPointers::shift()==0));
4880 ins_cost(MEMORY_REF_COST);
4881 size(Z_DISP3_SIZE);
4882 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
4883 opcode(LLGF_ZOPC, LLGF_ZOPC);
4884 ins_encode(z_form_rt_mem_opt(dst, mem));
4885 ins_pipe(pipe_class_dummy);
4886 %}
4887
4888 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4889 match(Set dst (DecodeNKlass src));
4890 ins_cost(3 * DEFAULT_COST);
4891 size(12);
4892 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4893 ins_encode %{
4894 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4895 __ relocate(NKlass.rspec(), 1);
4896 __ load_const($dst$$Register, (Klass*)NKlass.value());
4897 %}
4898 ins_pipe(pipe_class_dummy);
4899 %}
4900
4901 // Decode Compressed Pointer
4902
4903 // General decoder
4904 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4905 match(Set dst (DecodeN src));
4906 effect(KILL cr);
4907 predicate(CompressedOops::base() == nullptr || !ExpandLoadingBaseDecode);
4908 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4909 // TODO: s390 port size(VARIABLE_SIZE);
4910 format %{ "decodeN $dst,$src\t # (decode cOop)" %}
4911 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4912 ins_pipe(pipe_class_dummy);
4913 %}
4914
4915 // General Klass decoder
4916 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4917 match(Set dst (DecodeNKlass src));
4918 effect(KILL cr);
4919 ins_cost(3 * DEFAULT_COST);
4920 format %{ "decode_klass $dst,$src" %}
4921 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4922 ins_pipe(pipe_class_dummy);
4923 %}
4924
4925 // General decoder
4926 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4927 match(Set dst (DecodeN src));
4928 effect(KILL cr);
4929 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4930 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4931 (CompressedOops::base()== nullptr || !ExpandLoadingBaseDecode_NN));
4932 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4933 // TODO: s390 port size(VARIABLE_SIZE);
4934 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
4935 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4936 ins_pipe(pipe_class_dummy);
4937 %}
4938
4939 instruct loadBase(iRegL dst, immL baseImm) %{
4940 effect(DEF dst, USE baseImm);
4941 predicate(false);
4942 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4943 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4944 ins_pipe(pipe_class_dummy);
4945 %}
4946
4947 // Decoder for heapbased mode peeling off loading the base.
4948 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4949 match(Set dst (DecodeN src base));
4950 // Note: Effect TEMP dst was used with the intention to get
4951 // different regs for dst and base, but this has caused ADLC to
4952 // generate wrong code. Oop_decoder generates additional lgr when
4953 // dst==base.
4954 effect(KILL cr);
4955 predicate(false);
4956 // TODO: s390 port size(VARIABLE_SIZE);
4957 format %{ "decodeN $dst = ($src == 0) ? nullptr : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4958 ins_encode %{
4959 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4960 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4961 %}
4962 ins_pipe(pipe_class_dummy);
4963 %}
4964
4965 // Decoder for heapbased mode peeling off loading the base.
4966 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4967 match(Set dst (DecodeN src base));
4968 effect(KILL cr);
4969 predicate(false);
4970 // TODO: s390 port size(VARIABLE_SIZE);
4971 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4972 ins_encode %{
4973 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4974 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4975 %}
4976 ins_pipe(pipe_class_dummy);
4977 %}
4978
4979 // Decoder for heapbased mode peeling off loading the base.
4980 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4981 match(Set dst (DecodeN src));
4982 predicate(CompressedOops::base() != nullptr && ExpandLoadingBaseDecode);
4983 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4984 // TODO: s390 port size(VARIABLE_SIZE);
4985 expand %{
4986 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
4987 iRegL base;
4988 loadBase(base, baseImm);
4989 decodeN_base(dst, src, base, cr);
4990 %}
4991 %}
4992
4993 // Decoder for heapbased mode peeling off loading the base.
4994 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4995 match(Set dst (DecodeN src));
4996 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4997 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4998 CompressedOops::base() != nullptr && ExpandLoadingBaseDecode_NN);
4999 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5000 // TODO: s390 port size(VARIABLE_SIZE);
5001 expand %{
5002 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5003 iRegL base;
5004 loadBase(base, baseImm);
5005 decodeN_NN_base(dst, src, base, cr);
5006 %}
5007 %}
5008
5009 // Encode Compressed Pointer
5010
5011 // General encoder
5012 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
5013 match(Set dst (EncodeP src));
5014 effect(KILL cr);
5015 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5016 (CompressedOops::base() == nullptr ||
5017 CompressedOops::base_disjoint() ||
5018 !ExpandLoadingBaseEncode));
5019 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5020 // TODO: s390 port size(VARIABLE_SIZE);
5021 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5022 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5023 ins_pipe(pipe_class_dummy);
5024 %}
5025
5026 // General class encoder
5027 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
5028 match(Set dst (EncodePKlass src));
5029 effect(KILL cr);
5030 format %{ "encode_klass $dst,$src" %}
5031 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
5032 ins_pipe(pipe_class_dummy);
5033 %}
5034
5035 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
5036 match(Set dst (EncodeP src));
5037 effect(KILL cr);
5038 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5039 (CompressedOops::base() == nullptr ||
5040 CompressedOops::base_disjoint() ||
5041 !ExpandLoadingBaseEncode_NN));
5042 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5043 // TODO: s390 port size(VARIABLE_SIZE);
5044 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5045 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5046 ins_pipe(pipe_class_dummy);
5047 %}
5048
5049 // Encoder for heapbased mode peeling off loading the base.
5050 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
5051 match(Set dst (EncodeP src (Binary base dst)));
5052 effect(TEMP_DEF dst);
5053 predicate(false);
5054 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5055 // TODO: s390 port size(VARIABLE_SIZE);
5056 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
5057 ins_encode %{
5058 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
5059 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
5060 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
5061 %}
5062 ins_pipe(pipe_class_dummy);
5063 %}
5064
5065 // Encoder for heapbased mode peeling off loading the base.
5066 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
5067 match(Set dst (EncodeP src base));
5068 effect(USE pow2_offset);
5069 predicate(false);
5070 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5071 // TODO: s390 port size(VARIABLE_SIZE);
5072 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
5073 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
5074 ins_pipe(pipe_class_dummy);
5075 %}
5076
5077 // Encoder for heapbased mode peeling off loading the base.
5078 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5079 match(Set dst (EncodeP src));
5080 effect(KILL cr);
5081 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5082 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
5083 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5084 // TODO: s390 port size(VARIABLE_SIZE);
5085 expand %{
5086 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
5087 immL_0 zero %{ (0) %}
5088 flagsReg ccr;
5089 iRegL base;
5090 iRegL negBase;
5091 loadBase(base, baseImm);
5092 negL_reg_reg(negBase, zero, base, ccr);
5093 encodeP_base(dst, src, negBase);
5094 %}
5095 %}
5096
5097 // Encoder for heapbased mode peeling off loading the base.
5098 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5099 match(Set dst (EncodeP src));
5100 effect(KILL cr);
5101 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5102 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
5103 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5104 // TODO: s390 port size(VARIABLE_SIZE);
5105 expand %{
5106 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5107 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
5108 immL_0 zero %{ 0 %}
5109 flagsReg ccr;
5110 iRegL base;
5111 iRegL negBase;
5112 loadBase(base, baseImm);
5113 negL_reg_reg(negBase, zero, base, ccr);
5114 encodeP_NN_base(dst, src, negBase, pow2_offset);
5115 %}
5116 %}
5117
5118 // Store Compressed Pointer
5119
5120 // Store Compressed Pointer
5121 instruct storeN(memory mem, iRegN_P2N src) %{
5122 match(Set mem (StoreN mem src));
5123 predicate(n->as_Store()->barrier_data() == 0);
5124 ins_cost(MEMORY_REF_COST);
5125 size(Z_DISP_SIZE);
5126 format %{ "ST $src,$mem\t # (cOop)" %}
5127 opcode(STY_ZOPC, ST_ZOPC);
5128 ins_encode(z_form_rt_mem_opt(src, mem));
5129 ins_pipe(pipe_class_dummy);
5130 %}
5131
5132 // Store Compressed Klass pointer
5133 instruct storeNKlass(memory mem, iRegN src) %{
5134 match(Set mem (StoreNKlass mem src));
5135 ins_cost(MEMORY_REF_COST);
5136 size(Z_DISP_SIZE);
5137 format %{ "ST $src,$mem\t # (cKlass)" %}
5138 opcode(STY_ZOPC, ST_ZOPC);
5139 ins_encode(z_form_rt_mem_opt(src, mem));
5140 ins_pipe(pipe_class_dummy);
5141 %}
5142
5143 // Compare Compressed Pointers
5144
5145 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5146 match(Set cr (CmpN src1 src2));
5147 ins_cost(DEFAULT_COST);
5148 size(2);
5149 format %{ "CLR $src1,$src2\t # (cOop)" %}
5150 opcode(CLR_ZOPC);
5151 ins_encode(z_rrform(src1, src2));
5152 ins_pipe(pipe_class_dummy);
5153 %}
5154
5155 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5156 match(Set cr (CmpN src1 src2));
5157 ins_cost(DEFAULT_COST);
5158 size(6);
5159 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
5160 ins_encode %{
5161 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5162 __ relocate(cOop.rspec(), 1);
5163 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5164 %}
5165 ins_pipe(pipe_class_dummy);
5166 %}
5167
5168 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5169 match(Set cr (CmpN src1 src2));
5170 ins_cost(DEFAULT_COST);
5171 size(6);
5172 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
5173 ins_encode %{
5174 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5175 __ relocate(NKlass.rspec(), 1);
5176 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5177 %}
5178 ins_pipe(pipe_class_dummy);
5179 %}
5180
5181 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5182 match(Set cr (CmpN src1 src2));
5183 ins_cost(DEFAULT_COST);
5184 size(2);
5185 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
5186 opcode(LTR_ZOPC);
5187 ins_encode(z_rrform(src1, src1));
5188 ins_pipe(pipe_class_dummy);
5189 %}
5190
5191
5192 //----------MemBar Instructions-----------------------------------------------
5193
5194 // Memory barrier flavors
5195
5196 instruct membar_acquire() %{
5197 match(MemBarAcquire);
5198 match(LoadFence);
5199 ins_cost(4*MEMORY_REF_COST);
5200 size(0);
5201 format %{ "MEMBAR-acquire" %}
5202 ins_encode %{ __ z_acquire(); %}
5203 ins_pipe(pipe_class_dummy);
5204 %}
5205
5206 instruct membar_acquire_lock() %{
5207 match(MemBarAcquireLock);
5208 ins_cost(0);
5209 size(0);
5210 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5211 ins_encode(/*empty*/);
5212 ins_pipe(pipe_class_dummy);
5213 %}
5214
5215 instruct membar_release() %{
5216 match(MemBarRelease);
5217 match(StoreFence);
5218 ins_cost(4 * MEMORY_REF_COST);
5219 size(0);
5220 format %{ "MEMBAR-release" %}
5221 ins_encode %{ __ z_release(); %}
5222 ins_pipe(pipe_class_dummy);
5223 %}
5224
5225 instruct membar_release_lock() %{
5226 match(MemBarReleaseLock);
5227 ins_cost(0);
5228 size(0);
5229 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5230 ins_encode(/*empty*/);
5231 ins_pipe(pipe_class_dummy);
5232 %}
5233
5234 instruct membar_storeload() %{
5235 match(MemBarStoreLoad);
5236 ins_cost(4 * MEMORY_REF_COST);
5237 size(2);
5238 format %{ "MEMBAR-storeload" %}
5239 ins_encode %{ __ z_fence(); %}
5240 ins_pipe(pipe_class_dummy);
5241 %}
5242
5243 instruct membar_volatile() %{
5244 match(MemBarVolatile);
5245 ins_cost(4 * MEMORY_REF_COST);
5246 size(2);
5247 format %{ "MEMBAR-volatile" %}
5248 ins_encode %{ __ z_fence(); %}
5249 ins_pipe(pipe_class_dummy);
5250 %}
5251
5252 instruct unnecessary_membar_volatile() %{
5253 match(MemBarVolatile);
5254 predicate(Matcher::post_store_load_barrier(n));
5255 ins_cost(0);
5256 size(0);
5257 format %{ "# MEMBAR-volatile (empty)" %}
5258 ins_encode(/*empty*/);
5259 ins_pipe(pipe_class_dummy);
5260 %}
5261
5262 instruct membar_full() %{
5263 match(MemBarFull);
5264 ins_cost(4 * MEMORY_REF_COST);
5265 size(2);
5266 format %{ "MEMBAR-full" %}
5267 ins_encode %{ __ z_fence(); %}
5268 ins_pipe(pipe_class_dummy);
5269 %}
5270
5271 instruct membar_CPUOrder() %{
5272 match(MemBarCPUOrder);
5273 ins_cost(0);
5274 // TODO: s390 port size(FIXED_SIZE);
5275 format %{ "MEMBAR-CPUOrder (empty)" %}
5276 ins_encode(/*empty*/);
5277 ins_pipe(pipe_class_dummy);
5278 %}
5279
5280 instruct membar_storestore() %{
5281 match(MemBarStoreStore);
5282 match(StoreStoreFence);
5283 ins_cost(0);
5284 size(0);
5285 format %{ "MEMBAR-storestore (empty)" %}
5286 ins_encode();
5287 ins_pipe(pipe_class_dummy);
5288 %}
5289
5290
5291 //----------Register Move Instructions-----------------------------------------
5292
5293 // Cast Long to Pointer for unsafe natives.
5294 instruct castX2P(iRegP dst, iRegL src) %{
5295 match(Set dst (CastX2P src));
5296 // TODO: s390 port size(VARIABLE_SIZE);
5297 format %{ "LGR $dst,$src\t # CastX2P" %}
5298 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5299 ins_pipe(pipe_class_dummy);
5300 %}
5301
5302 // Cast Pointer to Long for unsafe natives.
5303 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5304 match(Set dst (CastP2X src));
5305 // TODO: s390 port size(VARIABLE_SIZE);
5306 format %{ "LGR $dst,$src\t # CastP2X" %}
5307 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5308 ins_pipe(pipe_class_dummy);
5309 %}
5310
5311 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5312 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5313 match(Set stkSlot src); // chain rule
5314 ins_cost(MEMORY_REF_COST);
5315 // TODO: s390 port size(FIXED_SIZE);
5316 format %{ " STD $src,$stkSlot\t # stk" %}
5317 opcode(STD_ZOPC);
5318 ins_encode(z_form_rt_mem(src, stkSlot));
5319 ins_pipe(pipe_class_dummy);
5320 %}
5321
5322 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5323 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5324 match(Set stkSlot src); // chain rule
5325 ins_cost(MEMORY_REF_COST);
5326 // TODO: s390 port size(FIXED_SIZE);
5327 format %{ "STE $src,$stkSlot\t # stk" %}
5328 opcode(STE_ZOPC);
5329 ins_encode(z_form_rt_mem(src, stkSlot));
5330 ins_pipe(pipe_class_dummy);
5331 %}
5332
5333 //----------Conditional Move---------------------------------------------------
5334
5335 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5336 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5337 ins_cost(DEFAULT_COST + BRANCH_COST);
5338 // TODO: s390 port size(VARIABLE_SIZE);
5339 format %{ "CMoveN,$cmp $dst,$src" %}
5340 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5341 ins_pipe(pipe_class_dummy);
5342 %}
5343
5344 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5345 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5346 ins_cost(DEFAULT_COST + BRANCH_COST);
5347 // TODO: s390 port size(VARIABLE_SIZE);
5348 format %{ "CMoveN,$cmp $dst,$src" %}
5349 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5350 ins_pipe(pipe_class_dummy);
5351 %}
5352
5353 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5354 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5355 ins_cost(DEFAULT_COST + BRANCH_COST);
5356 // TODO: s390 port size(VARIABLE_SIZE);
5357 format %{ "CMoveI,$cmp $dst,$src" %}
5358 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5359 ins_pipe(pipe_class_dummy);
5360 %}
5361
5362 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5363 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5364 ins_cost(DEFAULT_COST + BRANCH_COST);
5365 // TODO: s390 port size(VARIABLE_SIZE);
5366 format %{ "CMoveI,$cmp $dst,$src" %}
5367 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5368 ins_pipe(pipe_class_dummy);
5369 %}
5370
5371 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5372 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5373 ins_cost(DEFAULT_COST + BRANCH_COST);
5374 // TODO: s390 port size(VARIABLE_SIZE);
5375 format %{ "CMoveP,$cmp $dst,$src" %}
5376 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5377 ins_pipe(pipe_class_dummy);
5378 %}
5379
5380 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5381 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5382 ins_cost(DEFAULT_COST + BRANCH_COST);
5383 // TODO: s390 port size(VARIABLE_SIZE);
5384 format %{ "CMoveP,$cmp $dst,$src" %}
5385 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5386 ins_pipe(pipe_class_dummy);
5387 %}
5388
5389 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5390 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5391 ins_cost(DEFAULT_COST + BRANCH_COST);
5392 // TODO: s390 port size(VARIABLE_SIZE);
5393 format %{ "CMoveF,$cmp $dst,$src" %}
5394 ins_encode %{
5395 // Don't emit code if operands are identical (same register).
5396 if ($dst$$FloatRegister != $src$$FloatRegister) {
5397 Label done;
5398 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5399 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5400 __ bind(done);
5401 }
5402 %}
5403 ins_pipe(pipe_class_dummy);
5404 %}
5405
5406 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5407 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5408 ins_cost(DEFAULT_COST + BRANCH_COST);
5409 // TODO: s390 port size(VARIABLE_SIZE);
5410 format %{ "CMoveD,$cmp $dst,$src" %}
5411 ins_encode %{
5412 // Don't emit code if operands are identical (same register).
5413 if ($dst$$FloatRegister != $src$$FloatRegister) {
5414 Label done;
5415 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5416 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5417 __ bind(done);
5418 }
5419 %}
5420 ins_pipe(pipe_class_dummy);
5421 %}
5422
5423 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5424 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5425 ins_cost(DEFAULT_COST + BRANCH_COST);
5426 // TODO: s390 port size(VARIABLE_SIZE);
5427 format %{ "CMoveL,$cmp $dst,$src" %}
5428 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5429 ins_pipe(pipe_class_dummy);
5430 %}
5431
5432 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5433 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5434 ins_cost(DEFAULT_COST + BRANCH_COST);
5435 // TODO: s390 port size(VARIABLE_SIZE);
5436 format %{ "CMoveL,$cmp $dst,$src" %}
5437 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5438 ins_pipe(pipe_class_dummy);
5439 %}
5440
5441 //----------OS and Locking Instructions----------------------------------------
5442
5443 // This name is KNOWN by the ADLC and cannot be changed.
5444 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5445 // for this guy.
5446 instruct tlsLoadP(threadRegP dst) %{
5447 match(Set dst (ThreadLocal));
5448 ins_cost(0);
5449 size(0);
5450 ins_should_rematerialize(true);
5451 format %{ "# $dst=ThreadLocal" %}
5452 ins_encode(/* empty */);
5453 ins_pipe(pipe_class_dummy);
5454 %}
5455
5456 instruct checkCastPP(iRegP dst) %{
5457 match(Set dst (CheckCastPP dst));
5458 size(0);
5459 format %{ "# checkcastPP of $dst" %}
5460 ins_encode(/*empty*/);
5461 ins_pipe(pipe_class_dummy);
5462 %}
5463
5464 instruct castPP(iRegP dst) %{
5465 match(Set dst (CastPP dst));
5466 size(0);
5467 format %{ "# castPP of $dst" %}
5468 ins_encode(/*empty*/);
5469 ins_pipe(pipe_class_dummy);
5470 %}
5471
5472 instruct castII(iRegI dst) %{
5473 match(Set dst (CastII dst));
5474 size(0);
5475 format %{ "# castII of $dst" %}
5476 ins_encode(/*empty*/);
5477 ins_pipe(pipe_class_dummy);
5478 %}
5479
5480 instruct castLL(iRegL dst) %{
5481 match(Set dst (CastLL dst));
5482 size(0);
5483 format %{ "# castLL of $dst" %}
5484 ins_encode(/*empty*/);
5485 ins_pipe(pipe_class_dummy);
5486 %}
5487
5488 instruct castFF(regF dst) %{
5489 match(Set dst (CastFF dst));
5490 size(0);
5491 format %{ "# castFF of $dst" %}
5492 ins_encode(/*empty*/);
5493 ins_pipe(pipe_class_dummy);
5494 %}
5495
5496 instruct castDD(regD dst) %{
5497 match(Set dst (CastDD dst));
5498 size(0);
5499 format %{ "# castDD of $dst" %}
5500 ins_encode(/*empty*/);
5501 ins_pipe(pipe_class_dummy);
5502 %}
5503
5504 instruct castVV(iRegL dst) %{
5505 match(Set dst (CastVV dst));
5506 size(0);
5507 format %{ "# castVV of $dst" %}
5508 ins_encode(/*empty*/);
5509 ins_pipe(pipe_class_dummy);
5510 %}
5511
5512 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5513
5514 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5515 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5516 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5517 size(16);
5518 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5519 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5520 z_enc_cctobool(res));
5521 ins_pipe(pipe_class_dummy);
5522 %}
5523
5524 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5525 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5526 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5527 size(18);
5528 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5529 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5530 z_enc_cctobool(res));
5531 ins_pipe(pipe_class_dummy);
5532 %}
5533
5534 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5535 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5536 predicate(n->as_LoadStore()->barrier_data() == 0);
5537 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5538 size(18);
5539 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5540 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5541 z_enc_cctobool(res));
5542 ins_pipe(pipe_class_dummy);
5543 %}
5544
5545 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5546 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5547 predicate(n->as_LoadStore()->barrier_data() == 0);
5548 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5549 size(16);
5550 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5551 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5552 z_enc_cctobool(res));
5553 ins_pipe(pipe_class_dummy);
5554 %}
5555
5556 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5557
5558 // Exploit: direct memory arithmetic
5559 // Prereqs: - instructions available
5560 // - instructions guarantee atomicity
5561 // - immediate operand to be added
5562 // - immediate operand is small enough (8-bit signed).
5563 // - result of instruction is not used
5564 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5565 match(Set dummy (GetAndAddI mem src));
5566 effect(KILL cr);
5567 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5568 ins_cost(MEMORY_REF_COST);
5569 size(6);
5570 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5571 opcode(ASI_ZOPC);
5572 ins_encode(z_siyform(mem, src));
5573 ins_pipe(pipe_class_dummy);
5574 %}
5575
5576 // Fallback: direct memory arithmetic not available
5577 // Disadvantages: - CS-Loop required, very expensive.
5578 // - more code generated (26 to xx bytes vs. 6 bytes)
5579 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5580 match(Set dst (GetAndAddI mem src));
5581 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5582 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5583 format %{ "BEGIN ATOMIC {\n\t"
5584 " LGF $dst,[$mem]\n\t"
5585 " AHIK $tmp,$dst,$src\n\t"
5586 " CSY $dst,$tmp,$mem\n\t"
5587 " retry if failed\n\t"
5588 "} END ATOMIC"
5589 %}
5590 ins_encode %{
5591 Register Rdst = $dst$$Register;
5592 Register Rtmp = $tmp$$Register;
5593 int Isrc = $src$$constant;
5594 Label retry;
5595
5596 // Iterate until update with incremented value succeeds.
5597 __ z_lgf(Rdst, $mem$$Address); // current contents
5598 __ bind(retry);
5599 // Calculate incremented value.
5600 if (VM_Version::has_DistinctOpnds()) {
5601 __ z_ahik(Rtmp, Rdst, Isrc);
5602 } else {
5603 __ z_lr(Rtmp, Rdst);
5604 __ z_ahi(Rtmp, Isrc);
5605 }
5606 // Swap into memory location.
5607 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5608 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5609 %}
5610 ins_pipe(pipe_class_dummy);
5611 %}
5612
5613 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5614 match(Set dst (GetAndAddI mem src));
5615 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5616 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5617 format %{ "BEGIN ATOMIC {\n\t"
5618 " LGF $dst,[$mem]\n\t"
5619 " LGR $tmp,$dst\n\t"
5620 " AFI $tmp,$src\n\t"
5621 " CSY $dst,$tmp,$mem\n\t"
5622 " retry if failed\n\t"
5623 "} END ATOMIC"
5624 %}
5625 ins_encode %{
5626 Register Rdst = $dst$$Register;
5627 Register Rtmp = $tmp$$Register;
5628 int Isrc = $src$$constant;
5629 Label retry;
5630
5631 // Iterate until update with incremented value succeeds.
5632 __ z_lgf(Rdst, $mem$$Address); // current contents
5633 __ bind(retry);
5634 // Calculate incremented value.
5635 __ z_lr(Rtmp, Rdst);
5636 __ z_afi(Rtmp, Isrc);
5637 // Swap into memory location.
5638 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5639 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5640 %}
5641 ins_pipe(pipe_class_dummy);
5642 %}
5643
5644 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5645 match(Set dst (GetAndAddI mem src));
5646 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5647 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5648 format %{ "BEGIN ATOMIC {\n\t"
5649 " LGF $dst,[$mem]\n\t"
5650 " ARK $tmp,$dst,$src\n\t"
5651 " CSY $dst,$tmp,$mem\n\t"
5652 " retry if failed\n\t"
5653 "} END ATOMIC"
5654 %}
5655 ins_encode %{
5656 Register Rsrc = $src$$Register;
5657 Register Rdst = $dst$$Register;
5658 Register Rtmp = $tmp$$Register;
5659 Label retry;
5660
5661 // Iterate until update with incremented value succeeds.
5662 __ z_lgf(Rdst, $mem$$Address); // current contents
5663 __ bind(retry);
5664 // Calculate incremented value.
5665 if (VM_Version::has_DistinctOpnds()) {
5666 __ z_ark(Rtmp, Rdst, Rsrc);
5667 } else {
5668 __ z_lr(Rtmp, Rdst);
5669 __ z_ar(Rtmp, Rsrc);
5670 }
5671 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5672 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5673 %}
5674 ins_pipe(pipe_class_dummy);
5675 %}
5676
5677
5678 // Exploit: direct memory arithmetic
5679 // Prereqs: - instructions available
5680 // - instructions guarantee atomicity
5681 // - immediate operand to be added
5682 // - immediate operand is small enough (8-bit signed).
5683 // - result of instruction is not used
5684 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5685 match(Set dummy (GetAndAddL mem src));
5686 effect(KILL cr);
5687 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5688 ins_cost(MEMORY_REF_COST);
5689 size(6);
5690 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5691 opcode(AGSI_ZOPC);
5692 ins_encode(z_siyform(mem, src));
5693 ins_pipe(pipe_class_dummy);
5694 %}
5695
5696 // Fallback: direct memory arithmetic not available
5697 // Disadvantages: - CS-Loop required, very expensive.
5698 // - more code generated (26 to xx bytes vs. 6 bytes)
5699 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5700 match(Set dst (GetAndAddL mem src));
5701 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5702 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5703 format %{ "BEGIN ATOMIC {\n\t"
5704 " LG $dst,[$mem]\n\t"
5705 " AGHIK $tmp,$dst,$src\n\t"
5706 " CSG $dst,$tmp,$mem\n\t"
5707 " retry if failed\n\t"
5708 "} END ATOMIC"
5709 %}
5710 ins_encode %{
5711 Register Rdst = $dst$$Register;
5712 Register Rtmp = $tmp$$Register;
5713 int Isrc = $src$$constant;
5714 Label retry;
5715
5716 // Iterate until update with incremented value succeeds.
5717 __ z_lg(Rdst, $mem$$Address); // current contents
5718 __ bind(retry);
5719 // Calculate incremented value.
5720 if (VM_Version::has_DistinctOpnds()) {
5721 __ z_aghik(Rtmp, Rdst, Isrc);
5722 } else {
5723 __ z_lgr(Rtmp, Rdst);
5724 __ z_aghi(Rtmp, Isrc);
5725 }
5726 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5727 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5728 %}
5729 ins_pipe(pipe_class_dummy);
5730 %}
5731
5732 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5733 match(Set dst (GetAndAddL mem src));
5734 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5735 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5736 format %{ "BEGIN ATOMIC {\n\t"
5737 " LG $dst,[$mem]\n\t"
5738 " LGR $tmp,$dst\n\t"
5739 " AGFI $tmp,$src\n\t"
5740 " CSG $dst,$tmp,$mem\n\t"
5741 " retry if failed\n\t"
5742 "} END ATOMIC"
5743 %}
5744 ins_encode %{
5745 Register Rdst = $dst$$Register;
5746 Register Rtmp = $tmp$$Register;
5747 int Isrc = $src$$constant;
5748 Label retry;
5749
5750 // Iterate until update with incremented value succeeds.
5751 __ z_lg(Rdst, $mem$$Address); // current contents
5752 __ bind(retry);
5753 // Calculate incremented value.
5754 __ z_lgr(Rtmp, Rdst);
5755 __ z_agfi(Rtmp, Isrc);
5756 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5757 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5758 %}
5759 ins_pipe(pipe_class_dummy);
5760 %}
5761
5762 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5763 match(Set dst (GetAndAddL mem src));
5764 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5765 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5766 format %{ "BEGIN ATOMIC {\n\t"
5767 " LG $dst,[$mem]\n\t"
5768 " AGRK $tmp,$dst,$src\n\t"
5769 " CSG $dst,$tmp,$mem\n\t"
5770 " retry if failed\n\t"
5771 "} END ATOMIC"
5772 %}
5773 ins_encode %{
5774 Register Rsrc = $src$$Register;
5775 Register Rdst = $dst$$Register;
5776 Register Rtmp = $tmp$$Register;
5777 Label retry;
5778
5779 // Iterate until update with incremented value succeeds.
5780 __ z_lg(Rdst, $mem$$Address); // current contents
5781 __ bind(retry);
5782 // Calculate incremented value.
5783 if (VM_Version::has_DistinctOpnds()) {
5784 __ z_agrk(Rtmp, Rdst, Rsrc);
5785 } else {
5786 __ z_lgr(Rtmp, Rdst);
5787 __ z_agr(Rtmp, Rsrc);
5788 }
5789 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5790 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5791 %}
5792 ins_pipe(pipe_class_dummy);
5793 %}
5794
5795 // Increment value in memory, save old value in dst.
5796 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5797 match(Set dst (GetAndAddI mem src));
5798 predicate(VM_Version::has_LoadAndALUAtomicV1());
5799 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5800 size(6);
5801 format %{ "LAA $dst,$src,[$mem]" %}
5802 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5803 ins_pipe(pipe_class_dummy);
5804 %}
5805
5806 // Increment value in memory, save old value in dst.
5807 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5808 match(Set dst (GetAndAddL mem src));
5809 predicate(VM_Version::has_LoadAndALUAtomicV1());
5810 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5811 size(6);
5812 format %{ "LAAG $dst,$src,[$mem]" %}
5813 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5814 ins_pipe(pipe_class_dummy);
5815 %}
5816
5817
5818 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5819 match(Set dst (GetAndSetI mem dst));
5820 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5821 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5822 ins_encode(z_enc_SwapI(mem, dst, tmp));
5823 ins_pipe(pipe_class_dummy);
5824 %}
5825
5826 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5827 match(Set dst (GetAndSetL mem dst));
5828 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5829 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5830 ins_encode(z_enc_SwapL(mem, dst, tmp));
5831 ins_pipe(pipe_class_dummy);
5832 %}
5833
5834 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5835 predicate(n->as_LoadStore()->barrier_data() == 0);
5836 match(Set dst (GetAndSetN mem dst));
5837 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5838 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5839 ins_encode(z_enc_SwapI(mem, dst, tmp));
5840 ins_pipe(pipe_class_dummy);
5841 %}
5842
5843 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5844 match(Set dst (GetAndSetP mem dst));
5845 predicate(n->as_LoadStore()->barrier_data() == 0);
5846 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5847 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5848 ins_encode(z_enc_SwapL(mem, dst, tmp));
5849 ins_pipe(pipe_class_dummy);
5850 %}
5851
5852
5853 //----------Arithmetic Instructions--------------------------------------------
5854
5855 // The rules are sorted by right operand type and operand length. Please keep
5856 // it that way.
5857 // Left operand type is always reg. Left operand len is I, L, P
5858 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5859 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5860
5861 // ADD
5862
5863 // REG = REG + REG
5864
5865 // Register Addition
5866 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5867 match(Set dst (AddI dst src));
5868 effect(KILL cr);
5869 // TODO: s390 port size(FIXED_SIZE);
5870 format %{ "AR $dst,$src\t # int CISC ALU" %}
5871 opcode(AR_ZOPC);
5872 ins_encode(z_rrform(dst, src));
5873 ins_pipe(pipe_class_dummy);
5874 %}
5875
5876 // Avoid use of LA(Y) for general ALU operation.
5877 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5878 match(Set dst (AddI src1 src2));
5879 effect(KILL cr);
5880 predicate(VM_Version::has_DistinctOpnds());
5881 ins_cost(DEFAULT_COST);
5882 size(4);
5883 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5884 opcode(ARK_ZOPC);
5885 ins_encode(z_rrfform(dst, src1, src2));
5886 ins_pipe(pipe_class_dummy);
5887 %}
5888
5889 // REG = REG + IMM
5890
5891 // Avoid use of LA(Y) for general ALU operation.
5892 // Immediate Addition
5893 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5894 match(Set dst (AddI dst con));
5895 effect(KILL cr);
5896 ins_cost(DEFAULT_COST);
5897 // TODO: s390 port size(FIXED_SIZE);
5898 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5899 opcode(AHI_ZOPC);
5900 ins_encode(z_riform_signed(dst, con));
5901 ins_pipe(pipe_class_dummy);
5902 %}
5903
5904 // Avoid use of LA(Y) for general ALU operation.
5905 // Immediate Addition
5906 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5907 match(Set dst (AddI src con));
5908 effect(KILL cr);
5909 predicate( VM_Version::has_DistinctOpnds());
5910 ins_cost(DEFAULT_COST);
5911 // TODO: s390 port size(FIXED_SIZE);
5912 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5913 opcode(AHIK_ZOPC);
5914 ins_encode(z_rieform_d(dst, src, con));
5915 ins_pipe(pipe_class_dummy);
5916 %}
5917
5918 // Immediate Addition
5919 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5920 match(Set dst (AddI dst src));
5921 effect(KILL cr);
5922 ins_cost(DEFAULT_COST_HIGH);
5923 size(6);
5924 format %{ "AFI $dst,$src" %}
5925 opcode(AFI_ZOPC);
5926 ins_encode(z_rilform_signed(dst, src));
5927 ins_pipe(pipe_class_dummy);
5928 %}
5929
5930 // Immediate Addition
5931 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5932 match(Set dst (AddI src con));
5933 predicate(PreferLAoverADD);
5934 ins_cost(DEFAULT_COST_LOW);
5935 size(4);
5936 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
5937 opcode(LA_ZOPC);
5938 ins_encode(z_rxform_imm_reg(dst, con, src));
5939 ins_pipe(pipe_class_dummy);
5940 %}
5941
5942 // Immediate Addition
5943 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5944 match(Set dst (AddI src con));
5945 predicate(PreferLAoverADD);
5946 ins_cost(DEFAULT_COST);
5947 size(6);
5948 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
5949 opcode(LAY_ZOPC);
5950 ins_encode(z_rxyform_imm_reg(dst, con, src));
5951 ins_pipe(pipe_class_dummy);
5952 %}
5953
5954 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5955 match(Set dst (AddI (AddI src1 src2) con));
5956 predicate( PreferLAoverADD);
5957 ins_cost(DEFAULT_COST_LOW);
5958 size(4);
5959 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5960 opcode(LA_ZOPC);
5961 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5962 ins_pipe(pipe_class_dummy);
5963 %}
5964
5965 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5966 match(Set dst (AddI (AddI src1 src2) con));
5967 predicate(PreferLAoverADD);
5968 ins_cost(DEFAULT_COST);
5969 size(6);
5970 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5971 opcode(LAY_ZOPC);
5972 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5973 ins_pipe(pipe_class_dummy);
5974 %}
5975
5976 // REG = REG + MEM
5977
5978 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5979 match(Set dst (AddI dst (LoadI src)));
5980 effect(KILL cr);
5981 ins_cost(MEMORY_REF_COST);
5982 // TODO: s390 port size(VARIABLE_SIZE);
5983 format %{ "A(Y) $dst, $src\t # int" %}
5984 opcode(AY_ZOPC, A_ZOPC);
5985 ins_encode(z_form_rt_mem_opt(dst, src));
5986 ins_pipe(pipe_class_dummy);
5987 %}
5988
5989 // MEM = MEM + IMM
5990
5991 // Add Immediate to 4-byte memory operand and result
5992 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5993 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5994 effect(KILL cr);
5995 predicate(VM_Version::has_MemWithImmALUOps());
5996 ins_cost(MEMORY_REF_COST);
5997 size(6);
5998 format %{ "ASI $mem,$src\t # direct mem add 4" %}
5999 opcode(ASI_ZOPC);
6000 ins_encode(z_siyform(mem, src));
6001 ins_pipe(pipe_class_dummy);
6002 %}
6003
6004
6005 //
6006
6007 // REG = REG + REG
6008
6009 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
6010 match(Set dst (AddL dst (ConvI2L src)));
6011 effect(KILL cr);
6012 size(4);
6013 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
6014 opcode(AGFR_ZOPC);
6015 ins_encode(z_rreform(dst, src));
6016 ins_pipe(pipe_class_dummy);
6017 %}
6018
6019 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6020 match(Set dst (AddL dst src));
6021 effect(KILL cr);
6022 // TODO: s390 port size(FIXED_SIZE);
6023 format %{ "AGR $dst, $src\t # long CISC ALU" %}
6024 opcode(AGR_ZOPC);
6025 ins_encode(z_rreform(dst, src));
6026 ins_pipe(pipe_class_dummy);
6027 %}
6028
6029 // Avoid use of LA(Y) for general ALU operation.
6030 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6031 match(Set dst (AddL src1 src2));
6032 effect(KILL cr);
6033 predicate(VM_Version::has_DistinctOpnds());
6034 ins_cost(DEFAULT_COST);
6035 size(4);
6036 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
6037 opcode(AGRK_ZOPC);
6038 ins_encode(z_rrfform(dst, src1, src2));
6039 ins_pipe(pipe_class_dummy);
6040 %}
6041
6042 // REG = REG + IMM
6043
6044 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
6045 match(Set dst (AddL src con));
6046 predicate( PreferLAoverADD);
6047 ins_cost(DEFAULT_COST_LOW);
6048 size(4);
6049 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
6050 opcode(LA_ZOPC);
6051 ins_encode(z_rxform_imm_reg(dst, con, src));
6052 ins_pipe(pipe_class_dummy);
6053 %}
6054
6055 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
6056 match(Set dst (AddL src con));
6057 predicate(PreferLAoverADD);
6058 ins_cost(DEFAULT_COST);
6059 size(6);
6060 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
6061 opcode(LAY_ZOPC);
6062 ins_encode(z_rxyform_imm_reg(dst, con, src));
6063 ins_pipe(pipe_class_dummy);
6064 %}
6065
6066 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
6067 match(Set dst (AddL dst con));
6068 effect(KILL cr);
6069 ins_cost(DEFAULT_COST_HIGH);
6070 size(6);
6071 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
6072 opcode(AGFI_ZOPC);
6073 ins_encode(z_rilform_signed(dst, con));
6074 ins_pipe(pipe_class_dummy);
6075 %}
6076
6077 // Avoid use of LA(Y) for general ALU operation.
6078 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6079 match(Set dst (AddL dst con));
6080 effect(KILL cr);
6081 ins_cost(DEFAULT_COST);
6082 // TODO: s390 port size(FIXED_SIZE);
6083 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6084 opcode(AGHI_ZOPC);
6085 ins_encode(z_riform_signed(dst, con));
6086 ins_pipe(pipe_class_dummy);
6087 %}
6088
6089 // Avoid use of LA(Y) for general ALU operation.
6090 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6091 match(Set dst (AddL src con));
6092 effect(KILL cr);
6093 predicate( VM_Version::has_DistinctOpnds());
6094 ins_cost(DEFAULT_COST);
6095 size(6);
6096 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6097 opcode(AGHIK_ZOPC);
6098 ins_encode(z_rieform_d(dst, src, con));
6099 ins_pipe(pipe_class_dummy);
6100 %}
6101
6102 // REG = REG + MEM
6103
6104 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6105 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6106 effect(KILL cr);
6107 ins_cost(MEMORY_REF_COST);
6108 size(Z_DISP3_SIZE);
6109 format %{ "AGF $dst, $src\t # long/int" %}
6110 opcode(AGF_ZOPC, AGF_ZOPC);
6111 ins_encode(z_form_rt_mem_opt(dst, src));
6112 ins_pipe(pipe_class_dummy);
6113 %}
6114
6115 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6116 match(Set dst (AddL dst (LoadL src)));
6117 effect(KILL cr);
6118 ins_cost(MEMORY_REF_COST);
6119 size(Z_DISP3_SIZE);
6120 format %{ "AG $dst, $src\t # long" %}
6121 opcode(AG_ZOPC, AG_ZOPC);
6122 ins_encode(z_form_rt_mem_opt(dst, src));
6123 ins_pipe(pipe_class_dummy);
6124 %}
6125
6126 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6127 match(Set dst (AddL (AddL src1 src2) con));
6128 predicate( PreferLAoverADD);
6129 ins_cost(DEFAULT_COST_LOW);
6130 size(4);
6131 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6132 opcode(LA_ZOPC);
6133 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6134 ins_pipe(pipe_class_dummy);
6135 %}
6136
6137 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6138 match(Set dst (AddL (AddL src1 src2) con));
6139 predicate(PreferLAoverADD);
6140 ins_cost(DEFAULT_COST);
6141 size(6);
6142 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6143 opcode(LAY_ZOPC);
6144 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6145 ins_pipe(pipe_class_dummy);
6146 %}
6147
6148 // MEM = MEM + IMM
6149
6150 // Add Immediate to 8-byte memory operand and result.
6151 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6152 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6153 effect(KILL cr);
6154 predicate(VM_Version::has_MemWithImmALUOps());
6155 ins_cost(MEMORY_REF_COST);
6156 size(6);
6157 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6158 opcode(AGSI_ZOPC);
6159 ins_encode(z_siyform(mem, src));
6160 ins_pipe(pipe_class_dummy);
6161 %}
6162
6163
6164 // REG = REG + REG
6165
6166 // Ptr Addition
6167 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6168 match(Set dst (AddP src1 src2));
6169 predicate( PreferLAoverADD);
6170 ins_cost(DEFAULT_COST);
6171 size(4);
6172 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6173 opcode(LA_ZOPC);
6174 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6175 ins_pipe(pipe_class_dummy);
6176 %}
6177
6178 // Ptr Addition
6179 // Avoid use of LA(Y) for general ALU operation.
6180 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6181 match(Set dst (AddP dst src));
6182 effect(KILL cr);
6183 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6184 ins_cost(DEFAULT_COST);
6185 // TODO: s390 port size(FIXED_SIZE);
6186 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6187 opcode(ALGR_ZOPC);
6188 ins_encode(z_rreform(dst, src));
6189 ins_pipe(pipe_class_dummy);
6190 %}
6191
6192 // Ptr Addition
6193 // Avoid use of LA(Y) for general ALU operation.
6194 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6195 match(Set dst (AddP src1 src2));
6196 effect(KILL cr);
6197 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6198 ins_cost(DEFAULT_COST);
6199 // TODO: s390 port size(FIXED_SIZE);
6200 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6201 opcode(ALGRK_ZOPC);
6202 ins_encode(z_rrfform(dst, src1, src2));
6203 ins_pipe(pipe_class_dummy);
6204 %}
6205
6206 // REG = REG + IMM
6207
6208 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6209 match(Set dst (AddP src con));
6210 predicate( PreferLAoverADD);
6211 ins_cost(DEFAULT_COST_LOW);
6212 size(4);
6213 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6214 opcode(LA_ZOPC);
6215 ins_encode(z_rxform_imm_reg(dst, con, src));
6216 ins_pipe(pipe_class_dummy);
6217 %}
6218
6219 // Avoid use of LA(Y) for general ALU operation.
6220 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6221 match(Set dst (AddP dst src));
6222 effect(KILL cr);
6223 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6224 ins_cost(DEFAULT_COST);
6225 // TODO: s390 port size(FIXED_SIZE);
6226 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6227 opcode(AGHI_ZOPC);
6228 ins_encode(z_riform_signed(dst, src));
6229 ins_pipe(pipe_class_dummy);
6230 %}
6231
6232 // Avoid use of LA(Y) for general ALU operation.
6233 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6234 match(Set dst (AddP src con));
6235 effect(KILL cr);
6236 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6237 ins_cost(DEFAULT_COST);
6238 // TODO: s390 port size(FIXED_SIZE);
6239 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6240 opcode(ALGHSIK_ZOPC);
6241 ins_encode(z_rieform_d(dst, src, con));
6242 ins_pipe(pipe_class_dummy);
6243 %}
6244
6245 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6246 match(Set dst (AddP src con));
6247 predicate(PreferLAoverADD);
6248 ins_cost(DEFAULT_COST);
6249 size(6);
6250 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6251 opcode(LAY_ZOPC);
6252 ins_encode(z_rxyform_imm_reg(dst, con, src));
6253 ins_pipe(pipe_class_dummy);
6254 %}
6255
6256 // Pointer Immediate Addition
6257 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6258 match(Set dst (AddP dst src));
6259 effect(KILL cr);
6260 ins_cost(DEFAULT_COST_HIGH);
6261 // TODO: s390 port size(FIXED_SIZE);
6262 format %{ "AGFI $dst,$src\t # ptr" %}
6263 opcode(AGFI_ZOPC);
6264 ins_encode(z_rilform_signed(dst, src));
6265 ins_pipe(pipe_class_dummy);
6266 %}
6267
6268 // REG = REG1 + REG2 + IMM
6269
6270 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6271 match(Set dst (AddP (AddP src1 src2) con));
6272 predicate( PreferLAoverADD);
6273 ins_cost(DEFAULT_COST_LOW);
6274 size(4);
6275 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6276 opcode(LA_ZOPC);
6277 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6278 ins_pipe(pipe_class_dummy);
6279 %}
6280
6281 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6282 match(Set dst (AddP (AddP src1 src2) con));
6283 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6284 ins_cost(DEFAULT_COST_LOW);
6285 size(4);
6286 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6287 opcode(LA_ZOPC);
6288 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6289 ins_pipe(pipe_class_dummy);
6290 %}
6291
6292 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6293 match(Set dst (AddP (AddP src1 src2) con));
6294 predicate(PreferLAoverADD);
6295 ins_cost(DEFAULT_COST);
6296 // TODO: s390 port size(FIXED_SIZE);
6297 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6298 opcode(LAY_ZOPC);
6299 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6300 ins_pipe(pipe_class_dummy);
6301 %}
6302
6303 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6304 match(Set dst (AddP (AddP src1 src2) con));
6305 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6306 ins_cost(DEFAULT_COST);
6307 // TODO: s390 port size(FIXED_SIZE);
6308 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6309 opcode(LAY_ZOPC);
6310 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6311 ins_pipe(pipe_class_dummy);
6312 %}
6313
6314 // MEM = MEM + IMM
6315
6316 // Add Immediate to 8-byte memory operand and result
6317 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6318 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6319 effect(KILL cr);
6320 predicate(VM_Version::has_MemWithImmALUOps() && n->as_LoadStore()->barrier_data() == 0);
6321 ins_cost(MEMORY_REF_COST);
6322 size(6);
6323 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6324 opcode(AGSI_ZOPC);
6325 ins_encode(z_siyform(mem, src));
6326 ins_pipe(pipe_class_dummy);
6327 %}
6328
6329 // SUB
6330
6331 // Register Subtraction
6332 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6333 match(Set dst (SubI dst src));
6334 effect(KILL cr);
6335 // TODO: s390 port size(FIXED_SIZE);
6336 format %{ "SR $dst,$src\t # int CISC ALU" %}
6337 opcode(SR_ZOPC);
6338 ins_encode(z_rrform(dst, src));
6339 ins_pipe(pipe_class_dummy);
6340 %}
6341
6342 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6343 match(Set dst (SubI src1 src2));
6344 effect(KILL cr);
6345 predicate(VM_Version::has_DistinctOpnds());
6346 ins_cost(DEFAULT_COST);
6347 size(4);
6348 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6349 opcode(SRK_ZOPC);
6350 ins_encode(z_rrfform(dst, src1, src2));
6351 ins_pipe(pipe_class_dummy);
6352 %}
6353
6354 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6355 match(Set dst (SubI dst (LoadI src)));
6356 effect(KILL cr);
6357 ins_cost(MEMORY_REF_COST);
6358 // TODO: s390 port size(VARIABLE_SIZE);
6359 format %{ "S(Y) $dst, $src\t # int" %}
6360 opcode(SY_ZOPC, S_ZOPC);
6361 ins_encode(z_form_rt_mem_opt(dst, src));
6362 ins_pipe(pipe_class_dummy);
6363 %}
6364
6365 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6366 match(Set dst (SubI zero src));
6367 effect(KILL cr);
6368 size(2);
6369 format %{ "NEG $dst, $src" %}
6370 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6371 ins_pipe(pipe_class_dummy);
6372 %}
6373
6374 //
6375
6376 // Long subtraction
6377 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6378 match(Set dst (SubL dst src));
6379 effect(KILL cr);
6380 // TODO: s390 port size(FIXED_SIZE);
6381 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6382 opcode(SGR_ZOPC);
6383 ins_encode(z_rreform(dst, src));
6384 ins_pipe(pipe_class_dummy);
6385 %}
6386
6387 // Avoid use of LA(Y) for general ALU operation.
6388 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6389 match(Set dst (SubL src1 src2));
6390 effect(KILL cr);
6391 predicate(VM_Version::has_DistinctOpnds());
6392 ins_cost(DEFAULT_COST);
6393 size(4);
6394 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6395 opcode(SGRK_ZOPC);
6396 ins_encode(z_rrfform(dst, src1, src2));
6397 ins_pipe(pipe_class_dummy);
6398 %}
6399
6400 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6401 match(Set dst (SubL dst (ConvI2L src)));
6402 effect(KILL cr);
6403 size(4);
6404 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6405 opcode(SGFR_ZOPC);
6406 ins_encode(z_rreform(dst, src));
6407 ins_pipe(pipe_class_dummy);
6408 %}
6409
6410 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6411 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6412 effect(KILL cr);
6413 ins_cost(MEMORY_REF_COST);
6414 size(Z_DISP3_SIZE);
6415 format %{ "SGF $dst, $src\t # long/int" %}
6416 opcode(SGF_ZOPC, SGF_ZOPC);
6417 ins_encode(z_form_rt_mem_opt(dst, src));
6418 ins_pipe(pipe_class_dummy);
6419 %}
6420
6421 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6422 match(Set dst (SubL dst (LoadL src)));
6423 effect(KILL cr);
6424 ins_cost(MEMORY_REF_COST);
6425 size(Z_DISP3_SIZE);
6426 format %{ "SG $dst, $src\t # long" %}
6427 opcode(SG_ZOPC, SG_ZOPC);
6428 ins_encode(z_form_rt_mem_opt(dst, src));
6429 ins_pipe(pipe_class_dummy);
6430 %}
6431
6432 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6433
6434 // MUL
6435
6436 // Register Multiplication
6437 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6438 match(Set dst (MulI dst src));
6439 ins_cost(DEFAULT_COST);
6440 size(4);
6441 format %{ "MSR $dst, $src" %}
6442 opcode(MSR_ZOPC);
6443 ins_encode(z_rreform(dst, src));
6444 ins_pipe(pipe_class_dummy);
6445 %}
6446
6447 // Immediate Multiplication
6448 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6449 match(Set dst (MulI dst con));
6450 ins_cost(DEFAULT_COST);
6451 // TODO: s390 port size(FIXED_SIZE);
6452 format %{ "MHI $dst,$con" %}
6453 opcode(MHI_ZOPC);
6454 ins_encode(z_riform_signed(dst,con));
6455 ins_pipe(pipe_class_dummy);
6456 %}
6457
6458 // Immediate (32bit) Multiplication
6459 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6460 match(Set dst (MulI dst con));
6461 ins_cost(DEFAULT_COST);
6462 size(6);
6463 format %{ "MSFI $dst,$con" %}
6464 opcode(MSFI_ZOPC);
6465 ins_encode(z_rilform_signed(dst,con));
6466 ins_pipe(pipe_class_dummy);
6467 %}
6468
6469 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6470 match(Set dst (MulI dst (LoadI src)));
6471 ins_cost(MEMORY_REF_COST);
6472 // TODO: s390 port size(VARIABLE_SIZE);
6473 format %{ "MS(Y) $dst, $src\t # int" %}
6474 opcode(MSY_ZOPC, MS_ZOPC);
6475 ins_encode(z_form_rt_mem_opt(dst, src));
6476 ins_pipe(pipe_class_dummy);
6477 %}
6478
6479 //
6480
6481 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6482 match(Set dst (MulL dst (ConvI2L src)));
6483 ins_cost(DEFAULT_COST);
6484 // TODO: s390 port size(FIXED_SIZE);
6485 format %{ "MSGFR $dst $src\t # long/int" %}
6486 opcode(MSGFR_ZOPC);
6487 ins_encode(z_rreform(dst, src));
6488 ins_pipe(pipe_class_dummy);
6489 %}
6490
6491 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6492 match(Set dst (MulL dst src));
6493 ins_cost(DEFAULT_COST);
6494 size(4);
6495 format %{ "MSGR $dst $src\t # long" %}
6496 opcode(MSGR_ZOPC);
6497 ins_encode(z_rreform(dst, src));
6498 ins_pipe(pipe_class_dummy);
6499 %}
6500
6501 // Immediate Multiplication
6502 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6503 match(Set dst (MulL dst src));
6504 ins_cost(DEFAULT_COST);
6505 // TODO: s390 port size(FIXED_SIZE);
6506 format %{ "MGHI $dst,$src\t # long" %}
6507 opcode(MGHI_ZOPC);
6508 ins_encode(z_riform_signed(dst, src));
6509 ins_pipe(pipe_class_dummy);
6510 %}
6511
6512 // Immediate (32bit) Multiplication
6513 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6514 match(Set dst (MulL dst con));
6515 ins_cost(DEFAULT_COST);
6516 size(6);
6517 format %{ "MSGFI $dst,$con" %}
6518 opcode(MSGFI_ZOPC);
6519 ins_encode(z_rilform_signed(dst,con));
6520 ins_pipe(pipe_class_dummy);
6521 %}
6522
6523 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6524 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6525 ins_cost(MEMORY_REF_COST);
6526 size(Z_DISP3_SIZE);
6527 format %{ "MSGF $dst, $src\t # long" %}
6528 opcode(MSGF_ZOPC, MSGF_ZOPC);
6529 ins_encode(z_form_rt_mem_opt(dst, src));
6530 ins_pipe(pipe_class_dummy);
6531 %}
6532
6533 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6534 match(Set dst (MulL dst (LoadL src)));
6535 ins_cost(MEMORY_REF_COST);
6536 size(Z_DISP3_SIZE);
6537 format %{ "MSG $dst, $src\t # long" %}
6538 opcode(MSG_ZOPC, MSG_ZOPC);
6539 ins_encode(z_form_rt_mem_opt(dst, src));
6540 ins_pipe(pipe_class_dummy);
6541 %}
6542
6543 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6544 match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6545 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6546 ins_cost(7*DEFAULT_COST);
6547 // TODO: s390 port size(VARIABLE_SIZE);
6548 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6549 ins_encode%{
6550 Register dst = $Rdst$$Register;
6551 Register src1 = $Rsrc1$$Register;
6552 Register src2 = $Rsrc2$$Register;
6553 Register tmp1 = $Rtmp1$$Register;
6554 Register tmp2 = $Rdst$$Register;
6555 // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6556 // implementing mulhs(a,b) = mulhu(a,b) - (a & (b>>63)) - (b & (a>>63))
6557 __ z_srag(tmp2, src1, 63); // a>>63
6558 __ z_srag(tmp1, src2, 63); // b>>63
6559 __ z_ngr(tmp2, src2); // b & (a>>63)
6560 __ z_ngr(tmp1, src1); // a & (b>>63)
6561 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63)))
6562 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1),
6563 // multiplicand is taken from oddReg (src1), multiplier in src2.
6564 __ z_sgr(dst, tmp1);
6565 %}
6566 ins_pipe(pipe_class_dummy);
6567 %}
6568
6569 // DIV
6570
6571 // Integer DIVMOD with Register, both quotient and mod results
6572 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6573 match(DivModI dst1src1 src2);
6574 effect(KILL cr);
6575 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6576 size((VM_Version::has_CompareBranch() ? 24 : 26));
6577 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6578 ins_encode %{
6579 Register d1s1 = $dst1src1$$Register;
6580 Register d2 = $dst2$$Register;
6581 Register s2 = $src2$$Register;
6582
6583 assert_different_registers(d1s1, s2);
6584
6585 Label do_div, done_div;
6586 if (VM_Version::has_CompareBranch()) {
6587 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6588 } else {
6589 __ z_chi(s2, -1);
6590 __ z_brne(do_div);
6591 }
6592 __ z_lcr(d1s1, d1s1);
6593 __ clear_reg(d2, false, false);
6594 __ z_bru(done_div);
6595 __ bind(do_div);
6596 __ z_lgfr(d1s1, d1s1);
6597 __ z_dsgfr(d2, s2);
6598 __ bind(done_div);
6599 %}
6600 ins_pipe(pipe_class_dummy);
6601 %}
6602
6603
6604 // Register Division
6605 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6606 match(Set dst (DivI src1 src2));
6607 effect(KILL tmp, KILL cr);
6608 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6609 size((VM_Version::has_CompareBranch() ? 20 : 22));
6610 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6611 ins_encode %{
6612 Register a = $src1$$Register;
6613 Register b = $src2$$Register;
6614 Register t = $dst$$Register;
6615
6616 assert_different_registers(t, b);
6617
6618 Label do_div, done_div;
6619 if (VM_Version::has_CompareBranch()) {
6620 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6621 } else {
6622 __ z_chi(b, -1);
6623 __ z_brne(do_div);
6624 }
6625 __ z_lcr(t, a);
6626 __ z_bru(done_div);
6627 __ bind(do_div);
6628 __ z_lgfr(t, a);
6629 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6630 __ bind(done_div);
6631 %}
6632 ins_pipe(pipe_class_dummy);
6633 %}
6634
6635 // Immediate Division
6636 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6637 match(Set dst (DivI src1 src2));
6638 effect(KILL tmp, KILL cr); // R0 is killed, too.
6639 ins_cost(2 * DEFAULT_COST);
6640 // TODO: s390 port size(VARIABLE_SIZE);
6641 format %{ "DIV_const $dst,$src1,$src2" %}
6642 ins_encode %{
6643 // No sign extension of Rdividend needed here.
6644 if ($src2$$constant != -1) {
6645 __ z_lghi(Z_R0_scratch, $src2$$constant);
6646 __ z_lgfr($dst$$Register, $src1$$Register);
6647 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6648 } else {
6649 __ z_lcr($dst$$Register, $src1$$Register);
6650 }
6651 %}
6652 ins_pipe(pipe_class_dummy);
6653 %}
6654
6655 // Unsigned Integer Register Division
6656 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6657 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6658 instruct udivI_reg_reg(roddRegI r5_rodd_dst, iRegI src2, revenRegI r4_reven_tmp, flagsReg cr) %{
6659 match(Set r5_rodd_dst (UDivI r5_rodd_dst src2));
6660 effect(TEMP r4_reven_tmp, KILL cr);
6661 // TODO: size(4);
6662 format %{ "UDIV $r5_rodd_dst,$r5_rodd_dst,$src2" %}
6663 ins_encode %{
6664 Register b = $src2$$Register;
6665 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6666 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6667 assert_different_registers(r4_reven_tmp, r5_rodd_dst, b);
6668 assert(r4_reven_tmp->successor() == r5_rodd_dst, "even-odd pair required for the instruction");
6669
6670 __ block_comment("unsigned_div_int {");
6671 __ z_lhi(r4_reven_tmp, 0); // make upper 32bits 0
6672 __ z_dlr(r4_reven_tmp, b);
6673 __ block_comment("} unsigned_div_int");
6674 %}
6675 ins_pipe(pipe_class_dummy);
6676 %}
6677
6678 // Long DIVMOD with Register, both quotient and mod results
6679 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6680 match(DivModL dst1src1 src2);
6681 effect(KILL cr);
6682 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6683 size((VM_Version::has_CompareBranch() ? 22 : 24));
6684 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6685 ins_encode %{
6686 Register d1s1 = $dst1src1$$Register;
6687 Register d2 = $dst2$$Register;
6688 Register s2 = $src2$$Register;
6689
6690 Label do_div, done_div;
6691 if (VM_Version::has_CompareBranch()) {
6692 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6693 } else {
6694 __ z_cghi(s2, -1);
6695 __ z_brne(do_div);
6696 }
6697 __ z_lcgr(d1s1, d1s1);
6698 // indicate unused result
6699 (void) __ clear_reg(d2, true, false);
6700 __ z_bru(done_div);
6701 __ bind(do_div);
6702 __ z_dsgr(d2, s2);
6703 __ bind(done_div);
6704 %}
6705 ins_pipe(pipe_class_dummy);
6706 %}
6707
6708 // Register Long Division
6709 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6710 match(Set dst (DivL dst src));
6711 effect(KILL tmp, KILL cr);
6712 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6713 size((VM_Version::has_CompareBranch() ? 18 : 20));
6714 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6715 ins_encode %{
6716 Register b = $src$$Register;
6717 Register t = $dst$$Register;
6718
6719 Label done_div;
6720 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6721 if (VM_Version::has_CompareBranch()) {
6722 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6723 } else {
6724 __ z_cghi(b, -1);
6725 __ z_bre(done_div);
6726 }
6727 __ z_lcgr(t, t); // Restore sign.
6728 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6729 __ bind(done_div);
6730 %}
6731 ins_pipe(pipe_class_dummy);
6732 %}
6733
6734 // Register Unsigned Long Division
6735 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6736 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6737 instruct udivL_reg_reg(roddRegL r5_rodd_dst, iRegL src, revenRegL r4_reven_tmp, flagsReg cr) %{
6738 match(Set r5_rodd_dst (UDivL r5_rodd_dst src));
6739 effect(TEMP r4_reven_tmp, KILL cr);
6740 ins_cost(DEFAULT_COST);
6741 // TODO: size(4);
6742 format %{ "UDIVG $r5_rodd_dst,$r5_rodd_dst,$src" %}
6743 ins_encode %{
6744 Register b = $src$$Register;
6745 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6746 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6747 assert_different_registers(r5_rodd_dst, r4_reven_tmp, b);
6748 __ block_comment("unsigned_div_long {");
6749 __ z_lghi(r4_reven_tmp, 0); // make upper 64bits 0
6750 __ z_dlgr(r4_reven_tmp, b);
6751 __ block_comment("} unsigned_div_long");
6752 %}
6753 ins_pipe(pipe_class_dummy);
6754 %}
6755
6756 // Immediate Long Division
6757 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6758 match(Set dst (DivL src1 src2));
6759 effect(KILL tmp, KILL cr); // R0 is killed, too.
6760 ins_cost(2 * DEFAULT_COST);
6761 // TODO: s390 port size(VARIABLE_SIZE);
6762 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6763 ins_encode %{
6764 if ($src2$$constant != -1) {
6765 __ z_lghi(Z_R0_scratch, $src2$$constant);
6766 __ lgr_if_needed($dst$$Register, $src1$$Register);
6767 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6768 } else {
6769 __ z_lcgr($dst$$Register, $src1$$Register);
6770 }
6771 %}
6772 ins_pipe(pipe_class_dummy);
6773 %}
6774
6775 // REM
6776
6777 // Integer Remainder
6778 // Register Remainder
6779 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6780 match(Set dst (ModI src1 src2));
6781 effect(KILL tmp, KILL cr);
6782 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6783 // TODO: s390 port size(VARIABLE_SIZE);
6784 format %{ "MOD_checked $dst,$src1,$src2" %}
6785 ins_encode %{
6786 Register a = $src1$$Register;
6787 Register b = $src2$$Register;
6788 Register t = $dst$$Register;
6789 assert_different_registers(t->successor(), b);
6790
6791 Label do_div, done_div;
6792
6793 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6794 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6795 if (VM_Version::has_CompareBranch()) {
6796 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6797 } else {
6798 __ z_chi(b, -1);
6799 __ z_bre(done_div);
6800 }
6801 __ z_lgfr(t->successor(), a);
6802 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6803 } else {
6804 if (VM_Version::has_CompareBranch()) {
6805 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6806 } else {
6807 __ z_chi(b, -1);
6808 __ z_brne(do_div);
6809 }
6810 __ clear_reg(t, true, false);
6811 __ z_bru(done_div);
6812 __ bind(do_div);
6813 __ z_lgfr(t->successor(), a);
6814 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6815 }
6816 __ bind(done_div);
6817 %}
6818 ins_pipe(pipe_class_dummy);
6819 %}
6820
6821 // Register Unsigned Integer Remainder
6822 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6823 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6824 instruct umodI_reg_reg(revenRegI r4_reven_dst, iRegI src2, roddRegI r5_rodd_tmp, flagsReg cr) %{
6825 match(Set r4_reven_dst (UModI r4_reven_dst src2));
6826 effect(TEMP r5_rodd_tmp, KILL cr);
6827 ins_cost(DEFAULT_COST);
6828 // TODO: s390 port size(VARIABLE_SIZE);
6829 format %{ "UMOD $r4_reven_dst,$r4_reven_dst,$src2" %}
6830 ins_encode %{
6831 Register b = $src2$$Register;
6832 Register r4_reven_dst = $r4_reven_dst$$Register;
6833 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6834 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6835 assert(r4_reven_dst->successor() == r5_rodd_tmp, "must be an even-odd pair");
6836
6837 __ block_comment("unsigned_mod_integer {");
6838 __ z_lr(r5_rodd_tmp, r4_reven_dst); // load lower 32bits in odd register
6839 __ z_lhi(r4_reven_dst, 0); // make upper 32bits 0
6840 __ z_dlr(r4_reven_dst, b);
6841 __ block_comment("} unsigned_mod_integer");
6842 %}
6843 ins_pipe(pipe_class_dummy);
6844 %}
6845
6846 // Immediate Remainder
6847 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6848 match(Set dst (ModI src1 src2));
6849 effect(KILL tmp, KILL cr); // R0 is killed, too.
6850 ins_cost(3 * DEFAULT_COST);
6851 // TODO: s390 port size(VARIABLE_SIZE);
6852 format %{ "MOD_const $dst,src1,$src2" %}
6853 ins_encode %{
6854 assert_different_registers($dst$$Register, $src1$$Register);
6855 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6856 int divisor = $src2$$constant;
6857
6858 if (divisor != -1) {
6859 __ z_lghi(Z_R0_scratch, divisor);
6860 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6861 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6862 } else {
6863 __ clear_reg($dst$$Register, true, false);
6864 }
6865 %}
6866 ins_pipe(pipe_class_dummy);
6867 %}
6868
6869 // Register Long Remainder
6870 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6871 match(Set dst (ModL src1 src2));
6872 effect(KILL src1, KILL cr); // R0 is killed, too.
6873 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6874 // TODO: s390 port size(VARIABLE_SIZE);
6875 format %{ "MODG_checked $dst,$src1,$src2" %}
6876 ins_encode %{
6877 Register a = $src1$$Register;
6878 Register b = $src2$$Register;
6879 Register t = $dst$$Register;
6880 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6881
6882 Label do_div, done_div;
6883 if (t->encoding() != b->encoding()) {
6884 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6885 if (VM_Version::has_CompareBranch()) {
6886 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6887 } else {
6888 __ z_cghi(b, -1);
6889 __ z_bre(done_div);
6890 }
6891 __ z_dsgr(t, b);
6892 } else {
6893 if (VM_Version::has_CompareBranch()) {
6894 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6895 } else {
6896 __ z_cghi(b, -1);
6897 __ z_brne(do_div);
6898 }
6899 __ clear_reg(t, true, false);
6900 __ z_bru(done_div);
6901 __ bind(do_div);
6902 __ z_dsgr(t, b);
6903 }
6904 __ bind(done_div);
6905 %}
6906 ins_pipe(pipe_class_dummy);
6907 %}
6908
6909 // Register Unsigned Long Remainder
6910 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6911 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6912 instruct umodL_reg_reg(revenRegL r4_reven_dst, roddRegL r5_rodd_tmp, iRegL src2, flagsReg cr) %{
6913 match(Set r4_reven_dst (UModL r4_reven_dst src2));
6914 effect(TEMP r5_rodd_tmp, KILL cr);
6915 ins_cost(DEFAULT_COST);
6916 // TODO: s390 port size(VARIABLE_SIZE);
6917 format %{ "UMODG $r4_reven_dst,$r4_reven_dst,$src2" %}
6918 ins_encode %{
6919 Register b = $src2$$Register;
6920 Register r4_reven_dst = $r4_reven_dst$$Register;
6921 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6922 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6923 assert(r4_reven_dst->successor() == r5_rodd_tmp, "instruction requires an even-odd pair" );
6924
6925 __ block_comment("unsigned_mod_long {");
6926 __ z_lgr(r5_rodd_tmp, r4_reven_dst); // load lower 64bits in even register
6927 __ z_lghi(r4_reven_dst, 0); // make upper 64bits 0
6928 __ z_dlgr(r4_reven_dst, b);
6929 __ block_comment("} unsigned_mod_long");
6930 %}
6931 ins_pipe(pipe_class_dummy);
6932 %}
6933
6934 // Register Long Remainder
6935 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6936 match(Set dst (ModL src1 src2));
6937 effect(KILL tmp, KILL cr); // R0 is killed, too.
6938 ins_cost(3 * DEFAULT_COST);
6939 // TODO: s390 port size(VARIABLE_SIZE);
6940 format %{ "MODG_const $dst,src1,$src2\t # long" %}
6941 ins_encode %{
6942 int divisor = $src2$$constant;
6943 if (divisor != -1) {
6944 __ z_lghi(Z_R0_scratch, divisor);
6945 __ z_lgr($dst$$Register->successor(), $src1$$Register);
6946 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6947 } else {
6948 __ clear_reg($dst$$Register, true, false);
6949 }
6950 %}
6951 ins_pipe(pipe_class_dummy);
6952 %}
6953
6954 // SHIFT
6955
6956 // Shift left logical
6957
6958 // Register Shift Left variable
6959 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6960 match(Set dst (LShiftI src nbits));
6961 effect(KILL cr); // R1 is killed, too.
6962 ins_cost(3 * DEFAULT_COST);
6963 size(14);
6964 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
6965 ins_encode %{
6966 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6967 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6968 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6969 %}
6970 ins_pipe(pipe_class_dummy);
6971 %}
6972
6973 // Register Shift Left Immediate
6974 // Constant shift count is masked in ideal graph already.
6975 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6976 match(Set dst (LShiftI src nbits));
6977 size(6);
6978 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
6979 ins_encode %{
6980 int Nbit = $nbits$$constant;
6981 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6982 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6983 %}
6984 ins_pipe(pipe_class_dummy);
6985 %}
6986
6987 // Register Shift Left Immediate by 1bit
6988 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6989 match(Set dst (LShiftI src nbits));
6990 predicate(PreferLAoverADD);
6991 ins_cost(DEFAULT_COST_LOW);
6992 size(4);
6993 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6994 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6995 ins_pipe(pipe_class_dummy);
6996 %}
6997
6998 // Register Shift Left Long
6999 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
7000 match(Set dst (LShiftL src1 nbits));
7001 size(6);
7002 format %{ "SLLG $dst,$src1,[$nbits]" %}
7003 opcode(SLLG_ZOPC);
7004 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
7005 ins_pipe(pipe_class_dummy);
7006 %}
7007
7008 // Register Shift Left Long Immediate
7009 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
7010 match(Set dst (LShiftL src1 nbits));
7011 size(6);
7012 format %{ "SLLG $dst,$src1,$nbits" %}
7013 opcode(SLLG_ZOPC);
7014 ins_encode(z_rsyform_const(dst, src1, nbits));
7015 ins_pipe(pipe_class_dummy);
7016 %}
7017
7018 // Register Shift Left Long Immediate by 1bit
7019 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
7020 match(Set dst (LShiftL src1 nbits));
7021 predicate(PreferLAoverADD);
7022 ins_cost(DEFAULT_COST_LOW);
7023 size(4);
7024 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
7025 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
7026 ins_pipe(pipe_class_dummy);
7027 %}
7028
7029 // Shift right arithmetic
7030
7031 // Register Arithmetic Shift Right
7032 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7033 match(Set dst (RShiftI dst src));
7034 effect(KILL cr); // R1 is killed, too.
7035 ins_cost(3 * DEFAULT_COST);
7036 size(12);
7037 format %{ "SRA $dst,[$src] & 31" %}
7038 ins_encode %{
7039 __ z_lgr(Z_R1_scratch, $src$$Register);
7040 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7041 __ z_sra($dst$$Register, 0, Z_R1_scratch);
7042 %}
7043 ins_pipe(pipe_class_dummy);
7044 %}
7045
7046 // Register Arithmetic Shift Right Immediate
7047 // Constant shift count is masked in ideal graph already.
7048 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
7049 match(Set dst (RShiftI dst src));
7050 effect(KILL cr);
7051 size(4);
7052 format %{ "SRA $dst,$src" %}
7053 ins_encode %{
7054 int Nbit = $src$$constant;
7055 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7056 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7057 %}
7058 ins_pipe(pipe_class_dummy);
7059 %}
7060
7061 // Register Arithmetic Shift Right Long
7062 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
7063 match(Set dst (RShiftL src1 src2));
7064 effect(KILL cr);
7065 size(6);
7066 format %{ "SRAG $dst,$src1,[$src2]" %}
7067 opcode(SRAG_ZOPC);
7068 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7069 ins_pipe(pipe_class_dummy);
7070 %}
7071
7072 // Register Arithmetic Shift Right Long Immediate
7073 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
7074 match(Set dst (RShiftL src1 src2));
7075 effect(KILL cr);
7076 size(6);
7077 format %{ "SRAG $dst,$src1,$src2" %}
7078 opcode(SRAG_ZOPC);
7079 ins_encode(z_rsyform_const(dst, src1, src2));
7080 ins_pipe(pipe_class_dummy);
7081 %}
7082
7083 // Shift right logical
7084
7085 // Register Shift Right
7086 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7087 match(Set dst (URShiftI dst src));
7088 effect(KILL cr); // R1 is killed, too.
7089 ins_cost(3 * DEFAULT_COST);
7090 size(12);
7091 format %{ "SRL $dst,[$src] & 31" %}
7092 ins_encode %{
7093 __ z_lgr(Z_R1_scratch, $src$$Register);
7094 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7095 __ z_srl($dst$$Register, 0, Z_R1_scratch);
7096 %}
7097 ins_pipe(pipe_class_dummy);
7098 %}
7099
7100 // Register Shift Right Immediate
7101 // Constant shift count is masked in ideal graph already.
7102 instruct srlI_reg_imm(iRegI dst, immI src) %{
7103 match(Set dst (URShiftI dst src));
7104 size(4);
7105 format %{ "SRL $dst,$src" %}
7106 ins_encode %{
7107 int Nbit = $src$$constant;
7108 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7109 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7110 %}
7111 ins_pipe(pipe_class_dummy);
7112 %}
7113
7114 // Register Shift Right Long
7115 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7116 match(Set dst (URShiftL src1 src2));
7117 size(6);
7118 format %{ "SRLG $dst,$src1,[$src2]" %}
7119 opcode(SRLG_ZOPC);
7120 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7121 ins_pipe(pipe_class_dummy);
7122 %}
7123
7124 // Register Shift Right Long Immediate
7125 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
7126 match(Set dst (URShiftL src1 src2));
7127 size(6);
7128 format %{ "SRLG $dst,$src1,$src2" %}
7129 opcode(SRLG_ZOPC);
7130 ins_encode(z_rsyform_const(dst, src1, src2));
7131 ins_pipe(pipe_class_dummy);
7132 %}
7133
7134 // Register Shift Right Immediate with a CastP2X
7135 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
7136 match(Set dst (URShiftL (CastP2X src1) src2));
7137 size(6);
7138 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
7139 opcode(SRLG_ZOPC);
7140 ins_encode(z_rsyform_const(dst, src1, src2));
7141 ins_pipe(pipe_class_dummy);
7142 %}
7143
7144 //----------Rotate Instructions------------------------------------------------
7145
7146 // Rotate left 32bit.
7147 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
7148 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
7149 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7150 size(6);
7151 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
7152 opcode(RLL_ZOPC);
7153 ins_encode(z_rsyform_const(dst, src, lshift));
7154 ins_pipe(pipe_class_dummy);
7155 %}
7156
7157 // Rotate left 64bit.
7158 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
7159 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
7160 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7161 size(6);
7162 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
7163 opcode(RLLG_ZOPC);
7164 ins_encode(z_rsyform_const(dst, src, lshift));
7165 ins_pipe(pipe_class_dummy);
7166 %}
7167
7168 // Rotate right 32bit.
7169 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
7170 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
7171 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7172 // TODO: s390 port size(FIXED_SIZE);
7173 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
7174 opcode(RLL_ZOPC);
7175 ins_encode(z_rsyform_const(dst, src, rshift));
7176 ins_pipe(pipe_class_dummy);
7177 %}
7178
7179 // Rotate right 64bit.
7180 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7181 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7182 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7183 // TODO: s390 port size(FIXED_SIZE);
7184 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
7185 opcode(RLLG_ZOPC);
7186 ins_encode(z_rsyform_const(dst, src, rshift));
7187 ins_pipe(pipe_class_dummy);
7188 %}
7189
7190
7191 //----------Overflow Math Instructions-----------------------------------------
7192
7193 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7194 match(Set cr (OverflowAddI op1 op2));
7195 effect(DEF cr, USE op1, USE op2);
7196 // TODO: s390 port size(FIXED_SIZE);
7197 format %{ "AR $op1,$op2\t # overflow check int" %}
7198 ins_encode %{
7199 __ z_lr(Z_R0_scratch, $op1$$Register);
7200 __ z_ar(Z_R0_scratch, $op2$$Register);
7201 %}
7202 ins_pipe(pipe_class_dummy);
7203 %}
7204
7205 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7206 match(Set cr (OverflowAddI op1 op2));
7207 effect(DEF cr, USE op1, USE op2);
7208 // TODO: s390 port size(VARIABLE_SIZE);
7209 format %{ "AR $op1,$op2\t # overflow check int" %}
7210 ins_encode %{
7211 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7212 __ z_ar(Z_R0_scratch, $op1$$Register);
7213 %}
7214 ins_pipe(pipe_class_dummy);
7215 %}
7216
7217 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7218 match(Set cr (OverflowAddL op1 op2));
7219 effect(DEF cr, USE op1, USE op2);
7220 // TODO: s390 port size(FIXED_SIZE);
7221 format %{ "AGR $op1,$op2\t # overflow check long" %}
7222 ins_encode %{
7223 __ z_lgr(Z_R0_scratch, $op1$$Register);
7224 __ z_agr(Z_R0_scratch, $op2$$Register);
7225 %}
7226 ins_pipe(pipe_class_dummy);
7227 %}
7228
7229 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7230 match(Set cr (OverflowAddL op1 op2));
7231 effect(DEF cr, USE op1, USE op2);
7232 // TODO: s390 port size(VARIABLE_SIZE);
7233 format %{ "AGR $op1,$op2\t # overflow check long" %}
7234 ins_encode %{
7235 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7236 __ z_agr(Z_R0_scratch, $op1$$Register);
7237 %}
7238 ins_pipe(pipe_class_dummy);
7239 %}
7240
7241 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7242 match(Set cr (OverflowSubI op1 op2));
7243 effect(DEF cr, USE op1, USE op2);
7244 // TODO: s390 port size(FIXED_SIZE);
7245 format %{ "SR $op1,$op2\t # overflow check int" %}
7246 ins_encode %{
7247 __ z_lr(Z_R0_scratch, $op1$$Register);
7248 __ z_sr(Z_R0_scratch, $op2$$Register);
7249 %}
7250 ins_pipe(pipe_class_dummy);
7251 %}
7252
7253 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7254 match(Set cr (OverflowSubI op1 op2));
7255 effect(DEF cr, USE op1, USE op2);
7256 // TODO: s390 port size(VARIABLE_SIZE);
7257 format %{ "SR $op1,$op2\t # overflow check int" %}
7258 ins_encode %{
7259 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7260 __ z_lr(Z_R0_scratch, $op1$$Register);
7261 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7262 %}
7263 ins_pipe(pipe_class_dummy);
7264 %}
7265
7266 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7267 match(Set cr (OverflowSubL op1 op2));
7268 effect(DEF cr, USE op1, USE op2);
7269 // TODO: s390 port size(FIXED_SIZE);
7270 format %{ "SGR $op1,$op2\t # overflow check long" %}
7271 ins_encode %{
7272 __ z_lgr(Z_R0_scratch, $op1$$Register);
7273 __ z_sgr(Z_R0_scratch, $op2$$Register);
7274 %}
7275 ins_pipe(pipe_class_dummy);
7276 %}
7277
7278 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7279 match(Set cr (OverflowSubL op1 op2));
7280 effect(DEF cr, USE op1, USE op2);
7281 // TODO: s390 port size(VARIABLE_SIZE);
7282 format %{ "SGR $op1,$op2\t # overflow check long" %}
7283 ins_encode %{
7284 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7285 __ z_lgr(Z_R0_scratch, $op1$$Register);
7286 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7287 %}
7288 ins_pipe(pipe_class_dummy);
7289 %}
7290
7291 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7292 match(Set cr (OverflowSubI zero op2));
7293 effect(DEF cr, USE op2);
7294 format %{ "NEG $op2\t # overflow check int" %}
7295 ins_encode %{
7296 __ clear_reg(Z_R0_scratch, false, false);
7297 __ z_sr(Z_R0_scratch, $op2$$Register);
7298 %}
7299 ins_pipe(pipe_class_dummy);
7300 %}
7301
7302 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7303 match(Set cr (OverflowSubL zero op2));
7304 effect(DEF cr, USE op2);
7305 format %{ "NEGG $op2\t # overflow check long" %}
7306 ins_encode %{
7307 __ clear_reg(Z_R0_scratch, true, false);
7308 __ z_sgr(Z_R0_scratch, $op2$$Register);
7309 %}
7310 ins_pipe(pipe_class_dummy);
7311 %}
7312
7313 // No intrinsics for multiplication, since there is no easy way
7314 // to check for overflow.
7315
7316
7317 //----------Floating Point Arithmetic Instructions-----------------------------
7318
7319 // ADD
7320
7321 // Add float single precision
7322 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7323 match(Set dst (AddF dst src));
7324 effect(KILL cr);
7325 ins_cost(ALU_REG_COST);
7326 size(4);
7327 format %{ "AEBR $dst,$src" %}
7328 opcode(AEBR_ZOPC);
7329 ins_encode(z_rreform(dst, src));
7330 ins_pipe(pipe_class_dummy);
7331 %}
7332
7333 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7334 match(Set dst (AddF dst (LoadF src)));
7335 effect(KILL cr);
7336 ins_cost(ALU_MEMORY_COST);
7337 size(6);
7338 format %{ "AEB $dst,$src\t # floatMemory" %}
7339 opcode(AEB_ZOPC);
7340 ins_encode(z_form_rt_memFP(dst, src));
7341 ins_pipe(pipe_class_dummy);
7342 %}
7343
7344 // Add float double precision
7345 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7346 match(Set dst (AddD dst src));
7347 effect(KILL cr);
7348 ins_cost(ALU_REG_COST);
7349 size(4);
7350 format %{ "ADBR $dst,$src" %}
7351 opcode(ADBR_ZOPC);
7352 ins_encode(z_rreform(dst, src));
7353 ins_pipe(pipe_class_dummy);
7354 %}
7355
7356 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7357 match(Set dst (AddD dst (LoadD src)));
7358 effect(KILL cr);
7359 ins_cost(ALU_MEMORY_COST);
7360 size(6);
7361 format %{ "ADB $dst,$src\t # doubleMemory" %}
7362 opcode(ADB_ZOPC);
7363 ins_encode(z_form_rt_memFP(dst, src));
7364 ins_pipe(pipe_class_dummy);
7365 %}
7366
7367 // SUB
7368
7369 // Sub float single precision
7370 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7371 match(Set dst (SubF dst src));
7372 effect(KILL cr);
7373 ins_cost(ALU_REG_COST);
7374 size(4);
7375 format %{ "SEBR $dst,$src" %}
7376 opcode(SEBR_ZOPC);
7377 ins_encode(z_rreform(dst, src));
7378 ins_pipe(pipe_class_dummy);
7379 %}
7380
7381 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7382 match(Set dst (SubF dst (LoadF src)));
7383 effect(KILL cr);
7384 ins_cost(ALU_MEMORY_COST);
7385 size(6);
7386 format %{ "SEB $dst,$src\t # floatMemory" %}
7387 opcode(SEB_ZOPC);
7388 ins_encode(z_form_rt_memFP(dst, src));
7389 ins_pipe(pipe_class_dummy);
7390 %}
7391
7392 // Sub float double precision
7393 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7394 match(Set dst (SubD dst src));
7395 effect(KILL cr);
7396 ins_cost(ALU_REG_COST);
7397 size(4);
7398 format %{ "SDBR $dst,$src" %}
7399 opcode(SDBR_ZOPC);
7400 ins_encode(z_rreform(dst, src));
7401 ins_pipe(pipe_class_dummy);
7402 %}
7403
7404 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7405 match(Set dst (SubD dst (LoadD src)));
7406 effect(KILL cr);
7407 ins_cost(ALU_MEMORY_COST);
7408 size(6);
7409 format %{ "SDB $dst,$src\t # doubleMemory" %}
7410 opcode(SDB_ZOPC);
7411 ins_encode(z_form_rt_memFP(dst, src));
7412 ins_pipe(pipe_class_dummy);
7413 %}
7414
7415 // MUL
7416
7417 // Mul float single precision
7418 instruct mulF_reg_reg(regF dst, regF src) %{
7419 match(Set dst (MulF dst src));
7420 // CC unchanged by MUL.
7421 ins_cost(ALU_REG_COST);
7422 size(4);
7423 format %{ "MEEBR $dst,$src" %}
7424 opcode(MEEBR_ZOPC);
7425 ins_encode(z_rreform(dst, src));
7426 ins_pipe(pipe_class_dummy);
7427 %}
7428
7429 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7430 match(Set dst (MulF dst (LoadF src)));
7431 // CC unchanged by MUL.
7432 ins_cost(ALU_MEMORY_COST);
7433 size(6);
7434 format %{ "MEEB $dst,$src\t # floatMemory" %}
7435 opcode(MEEB_ZOPC);
7436 ins_encode(z_form_rt_memFP(dst, src));
7437 ins_pipe(pipe_class_dummy);
7438 %}
7439
7440 // Mul float double precision
7441 instruct mulD_reg_reg(regD dst, regD src) %{
7442 match(Set dst (MulD dst src));
7443 // CC unchanged by MUL.
7444 ins_cost(ALU_REG_COST);
7445 size(4);
7446 format %{ "MDBR $dst,$src" %}
7447 opcode(MDBR_ZOPC);
7448 ins_encode(z_rreform(dst, src));
7449 ins_pipe(pipe_class_dummy);
7450 %}
7451
7452 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7453 match(Set dst (MulD dst (LoadD src)));
7454 // CC unchanged by MUL.
7455 ins_cost(ALU_MEMORY_COST);
7456 size(6);
7457 format %{ "MDB $dst,$src\t # doubleMemory" %}
7458 opcode(MDB_ZOPC);
7459 ins_encode(z_form_rt_memFP(dst, src));
7460 ins_pipe(pipe_class_dummy);
7461 %}
7462
7463 // Multiply-Accumulate
7464 // src1 * src2 + dst
7465 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7466 match(Set dst (FmaF dst (Binary src1 src2)));
7467 // CC unchanged by MUL-ADD.
7468 ins_cost(ALU_REG_COST);
7469 size(4);
7470 format %{ "MAEBR $dst, $src1, $src2" %}
7471 ins_encode %{
7472 assert(UseFMA, "Needs FMA instructions support.");
7473 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7474 %}
7475 ins_pipe(pipe_class_dummy);
7476 %}
7477
7478 // src1 * src2 + dst
7479 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7480 match(Set dst (FmaD dst (Binary src1 src2)));
7481 // CC unchanged by MUL-ADD.
7482 ins_cost(ALU_REG_COST);
7483 size(4);
7484 format %{ "MADBR $dst, $src1, $src2" %}
7485 ins_encode %{
7486 assert(UseFMA, "Needs FMA instructions support.");
7487 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7488 %}
7489 ins_pipe(pipe_class_dummy);
7490 %}
7491
7492 // src1 * src2 - dst
7493 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7494 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7495 // CC unchanged by MUL-SUB.
7496 ins_cost(ALU_REG_COST);
7497 size(4);
7498 format %{ "MSEBR $dst, $src1, $src2" %}
7499 ins_encode %{
7500 assert(UseFMA, "Needs FMA instructions support.");
7501 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7502 %}
7503 ins_pipe(pipe_class_dummy);
7504 %}
7505
7506 // src1 * src2 - dst
7507 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7508 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7509 // CC unchanged by MUL-SUB.
7510 ins_cost(ALU_REG_COST);
7511 size(4);
7512 format %{ "MSDBR $dst, $src1, $src2" %}
7513 ins_encode %{
7514 assert(UseFMA, "Needs FMA instructions support.");
7515 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7516 %}
7517 ins_pipe(pipe_class_dummy);
7518 %}
7519
7520 // src1 * src2 + dst
7521 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7522 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7523 // CC unchanged by MUL-ADD.
7524 ins_cost(ALU_MEMORY_COST);
7525 size(6);
7526 format %{ "MAEB $dst, $src1, $src2" %}
7527 ins_encode %{
7528 assert(UseFMA, "Needs FMA instructions support.");
7529 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7530 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7531 %}
7532 ins_pipe(pipe_class_dummy);
7533 %}
7534
7535 // src1 * src2 + dst
7536 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7537 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7538 // CC unchanged by MUL-ADD.
7539 ins_cost(ALU_MEMORY_COST);
7540 size(6);
7541 format %{ "MADB $dst, $src1, $src2" %}
7542 ins_encode %{
7543 assert(UseFMA, "Needs FMA instructions support.");
7544 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7545 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7546 %}
7547 ins_pipe(pipe_class_dummy);
7548 %}
7549
7550 // src1 * src2 - dst
7551 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7552 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7553 // CC unchanged by MUL-SUB.
7554 ins_cost(ALU_MEMORY_COST);
7555 size(6);
7556 format %{ "MSEB $dst, $src1, $src2" %}
7557 ins_encode %{
7558 assert(UseFMA, "Needs FMA instructions support.");
7559 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7560 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7561 %}
7562 ins_pipe(pipe_class_dummy);
7563 %}
7564
7565 // src1 * src2 - dst
7566 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7567 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7568 // CC unchanged by MUL-SUB.
7569 ins_cost(ALU_MEMORY_COST);
7570 size(6);
7571 format %{ "MSDB $dst, $src1, $src2" %}
7572 ins_encode %{
7573 assert(UseFMA, "Needs FMA instructions support.");
7574 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7575 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7576 %}
7577 ins_pipe(pipe_class_dummy);
7578 %}
7579
7580 // src1 * src2 + dst
7581 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7582 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7583 // CC unchanged by MUL-ADD.
7584 ins_cost(ALU_MEMORY_COST);
7585 size(6);
7586 format %{ "MAEB $dst, $src1, $src2" %}
7587 ins_encode %{
7588 assert(UseFMA, "Needs FMA instructions support.");
7589 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7590 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7591 %}
7592 ins_pipe(pipe_class_dummy);
7593 %}
7594
7595 // src1 * src2 + dst
7596 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7597 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7598 // CC unchanged by MUL-ADD.
7599 ins_cost(ALU_MEMORY_COST);
7600 size(6);
7601 format %{ "MADB $dst, $src1, $src2" %}
7602 ins_encode %{
7603 assert(UseFMA, "Needs FMA instructions support.");
7604 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7605 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7606 %}
7607 ins_pipe(pipe_class_dummy);
7608 %}
7609
7610 // src1 * src2 - dst
7611 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7612 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7613 // CC unchanged by MUL-SUB.
7614 ins_cost(ALU_MEMORY_COST);
7615 size(6);
7616 format %{ "MSEB $dst, $src1, $src2" %}
7617 ins_encode %{
7618 assert(UseFMA, "Needs FMA instructions support.");
7619 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7620 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7621 %}
7622 ins_pipe(pipe_class_dummy);
7623 %}
7624
7625 // src1 * src2 - dst
7626 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7627 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7628 // CC unchanged by MUL-SUB.
7629 ins_cost(ALU_MEMORY_COST);
7630 size(6);
7631 format %{ "MSDB $dst, $src1, $src2" %}
7632 ins_encode %{
7633 assert(UseFMA, "Needs FMA instructions support.");
7634 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7635 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7636 %}
7637 ins_pipe(pipe_class_dummy);
7638 %}
7639
7640 // DIV
7641
7642 // Div float single precision
7643 instruct divF_reg_reg(regF dst, regF src) %{
7644 match(Set dst (DivF dst src));
7645 // CC unchanged by DIV.
7646 ins_cost(ALU_REG_COST);
7647 size(4);
7648 format %{ "DEBR $dst,$src" %}
7649 opcode(DEBR_ZOPC);
7650 ins_encode(z_rreform(dst, src));
7651 ins_pipe(pipe_class_dummy);
7652 %}
7653
7654 instruct divF_reg_mem(regF dst, memoryRX src)%{
7655 match(Set dst (DivF dst (LoadF src)));
7656 // CC unchanged by DIV.
7657 ins_cost(ALU_MEMORY_COST);
7658 size(6);
7659 format %{ "DEB $dst,$src\t # floatMemory" %}
7660 opcode(DEB_ZOPC);
7661 ins_encode(z_form_rt_memFP(dst, src));
7662 ins_pipe(pipe_class_dummy);
7663 %}
7664
7665 // Div float double precision
7666 instruct divD_reg_reg(regD dst, regD src) %{
7667 match(Set dst (DivD dst src));
7668 // CC unchanged by DIV.
7669 ins_cost(ALU_REG_COST);
7670 size(4);
7671 format %{ "DDBR $dst,$src" %}
7672 opcode(DDBR_ZOPC);
7673 ins_encode(z_rreform(dst, src));
7674 ins_pipe(pipe_class_dummy);
7675 %}
7676
7677 instruct divD_reg_mem(regD dst, memoryRX src)%{
7678 match(Set dst (DivD dst (LoadD src)));
7679 // CC unchanged by DIV.
7680 ins_cost(ALU_MEMORY_COST);
7681 size(6);
7682 format %{ "DDB $dst,$src\t # doubleMemory" %}
7683 opcode(DDB_ZOPC);
7684 ins_encode(z_form_rt_memFP(dst, src));
7685 ins_pipe(pipe_class_dummy);
7686 %}
7687
7688 // ABS
7689
7690 // Absolute float single precision
7691 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7692 match(Set dst (AbsF src));
7693 effect(KILL cr);
7694 size(4);
7695 format %{ "LPEBR $dst,$src\t float" %}
7696 opcode(LPEBR_ZOPC);
7697 ins_encode(z_rreform(dst, src));
7698 ins_pipe(pipe_class_dummy);
7699 %}
7700
7701 // Absolute float double precision
7702 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7703 match(Set dst (AbsD src));
7704 effect(KILL cr);
7705 size(4);
7706 format %{ "LPDBR $dst,$src\t double" %}
7707 opcode(LPDBR_ZOPC);
7708 ins_encode(z_rreform(dst, src));
7709 ins_pipe(pipe_class_dummy);
7710 %}
7711
7712 // NEG(ABS)
7713
7714 // Negative absolute float single precision
7715 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7716 match(Set dst (NegF (AbsF src)));
7717 effect(KILL cr);
7718 size(4);
7719 format %{ "LNEBR $dst,$src\t float" %}
7720 opcode(LNEBR_ZOPC);
7721 ins_encode(z_rreform(dst, src));
7722 ins_pipe(pipe_class_dummy);
7723 %}
7724
7725 // Negative absolute float double precision
7726 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7727 match(Set dst (NegD (AbsD src)));
7728 effect(KILL cr);
7729 size(4);
7730 format %{ "LNDBR $dst,$src\t double" %}
7731 opcode(LNDBR_ZOPC);
7732 ins_encode(z_rreform(dst, src));
7733 ins_pipe(pipe_class_dummy);
7734 %}
7735
7736 // NEG
7737
7738 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7739 match(Set dst (NegF src));
7740 effect(KILL cr);
7741 size(4);
7742 format %{ "NegF $dst,$src\t float" %}
7743 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7744 ins_pipe(pipe_class_dummy);
7745 %}
7746
7747 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7748 match(Set dst (NegD src));
7749 effect(KILL cr);
7750 size(4);
7751 format %{ "NegD $dst,$src\t double" %}
7752 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7753 ins_pipe(pipe_class_dummy);
7754 %}
7755
7756 // SQRT
7757
7758 // Sqrt float precision
7759 instruct sqrtF_reg(regF dst, regF src) %{
7760 match(Set dst (SqrtF src));
7761 // CC remains unchanged.
7762 ins_cost(ALU_REG_COST);
7763 size(4);
7764 format %{ "SQEBR $dst,$src" %}
7765 opcode(SQEBR_ZOPC);
7766 ins_encode(z_rreform(dst, src));
7767 ins_pipe(pipe_class_dummy);
7768 %}
7769
7770 // Sqrt double precision
7771 instruct sqrtD_reg(regD dst, regD src) %{
7772 match(Set dst (SqrtD src));
7773 // CC remains unchanged.
7774 ins_cost(ALU_REG_COST);
7775 size(4);
7776 format %{ "SQDBR $dst,$src" %}
7777 opcode(SQDBR_ZOPC);
7778 ins_encode(z_rreform(dst, src));
7779 ins_pipe(pipe_class_dummy);
7780 %}
7781
7782 instruct sqrtF_mem(regF dst, memoryRX src) %{
7783 match(Set dst (SqrtF src));
7784 // CC remains unchanged.
7785 ins_cost(ALU_MEMORY_COST);
7786 size(6);
7787 format %{ "SQEB $dst,$src\t # floatMemory" %}
7788 opcode(SQEB_ZOPC);
7789 ins_encode(z_form_rt_memFP(dst, src));
7790 ins_pipe(pipe_class_dummy);
7791 %}
7792
7793 instruct sqrtD_mem(regD dst, memoryRX src) %{
7794 match(Set dst (SqrtD src));
7795 // CC remains unchanged.
7796 ins_cost(ALU_MEMORY_COST);
7797 // TODO: s390 port size(FIXED_SIZE);
7798 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7799 opcode(SQDB_ZOPC);
7800 ins_encode(z_form_rt_memFP(dst, src));
7801 ins_pipe(pipe_class_dummy);
7802 %}
7803
7804 //----------Logical Instructions-----------------------------------------------
7805
7806 // Register And
7807 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7808 match(Set dst (AndI dst src));
7809 effect(KILL cr);
7810 ins_cost(DEFAULT_COST_LOW);
7811 size(2);
7812 format %{ "NR $dst,$src\t # int" %}
7813 opcode(NR_ZOPC);
7814 ins_encode(z_rrform(dst, src));
7815 ins_pipe(pipe_class_dummy);
7816 %}
7817
7818 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7819 match(Set dst (AndI dst (LoadI src)));
7820 effect(KILL cr);
7821 ins_cost(MEMORY_REF_COST);
7822 // TODO: s390 port size(VARIABLE_SIZE);
7823 format %{ "N(Y) $dst, $src\t # int" %}
7824 opcode(NY_ZOPC, N_ZOPC);
7825 ins_encode(z_form_rt_mem_opt(dst, src));
7826 ins_pipe(pipe_class_dummy);
7827 %}
7828
7829 // Immediate And
7830 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7831 match(Set dst (AndI dst src));
7832 effect(KILL cr);
7833 ins_cost(DEFAULT_COST_HIGH);
7834 size(6);
7835 format %{ "NILF $dst,$src" %}
7836 opcode(NILF_ZOPC);
7837 ins_encode(z_rilform_unsigned(dst, src));
7838 ins_pipe(pipe_class_dummy);
7839 %}
7840
7841 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7842 match(Set dst (AndI dst src));
7843 effect(KILL cr);
7844 ins_cost(DEFAULT_COST);
7845 size(4);
7846 format %{ "NILH $dst,$src" %}
7847 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7848 ins_pipe(pipe_class_dummy);
7849 %}
7850
7851 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7852 match(Set dst (AndI dst src));
7853 effect(KILL cr);
7854 ins_cost(DEFAULT_COST);
7855 size(4);
7856 format %{ "NILL $dst,$src" %}
7857 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7858 ins_pipe(pipe_class_dummy);
7859 %}
7860
7861 // Register And Long
7862 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7863 match(Set dst (AndL dst src));
7864 effect(KILL cr);
7865 ins_cost(DEFAULT_COST);
7866 size(4);
7867 format %{ "NGR $dst,$src\t # long" %}
7868 opcode(NGR_ZOPC);
7869 ins_encode(z_rreform(dst, src));
7870 ins_pipe(pipe_class_dummy);
7871 %}
7872
7873 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7874 match(Set dst (AndL dst (LoadL src)));
7875 effect(KILL cr);
7876 ins_cost(MEMORY_REF_COST);
7877 size(Z_DISP3_SIZE);
7878 format %{ "NG $dst, $src\t # long" %}
7879 opcode(NG_ZOPC, NG_ZOPC);
7880 ins_encode(z_form_rt_mem_opt(dst, src));
7881 ins_pipe(pipe_class_dummy);
7882 %}
7883
7884 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7885 match(Set dst (AndL dst src));
7886 effect(KILL cr);
7887 ins_cost(DEFAULT_COST);
7888 size(4);
7889 format %{ "NILL $dst,$src\t # long" %}
7890 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7891 ins_pipe(pipe_class_dummy);
7892 %}
7893
7894 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7895 match(Set dst (AndL dst src));
7896 effect(KILL cr);
7897 ins_cost(DEFAULT_COST);
7898 size(4);
7899 format %{ "NILH $dst,$src\t # long" %}
7900 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7901 ins_pipe(pipe_class_dummy);
7902 %}
7903
7904 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7905 match(Set dst (AndL dst src));
7906 effect(KILL cr);
7907 ins_cost(DEFAULT_COST);
7908 size(4);
7909 format %{ "NIHL $dst,$src\t # long" %}
7910 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7911 ins_pipe(pipe_class_dummy);
7912 %}
7913
7914 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7915 match(Set dst (AndL dst src));
7916 effect(KILL cr);
7917 ins_cost(DEFAULT_COST);
7918 size(4);
7919 format %{ "NIHH $dst,$src\t # long" %}
7920 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7921 ins_pipe(pipe_class_dummy);
7922 %}
7923
7924 // OR
7925
7926 // Or Instructions
7927 // Register Or
7928 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7929 match(Set dst (OrI dst src));
7930 effect(KILL cr);
7931 size(2);
7932 format %{ "OR $dst,$src" %}
7933 opcode(OR_ZOPC);
7934 ins_encode(z_rrform(dst, src));
7935 ins_pipe(pipe_class_dummy);
7936 %}
7937
7938 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7939 match(Set dst (OrI dst (LoadI src)));
7940 effect(KILL cr);
7941 ins_cost(MEMORY_REF_COST);
7942 // TODO: s390 port size(VARIABLE_SIZE);
7943 format %{ "O(Y) $dst, $src\t # int" %}
7944 opcode(OY_ZOPC, O_ZOPC);
7945 ins_encode(z_form_rt_mem_opt(dst, src));
7946 ins_pipe(pipe_class_dummy);
7947 %}
7948
7949 // Immediate Or
7950 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7951 match(Set dst (OrI dst con));
7952 effect(KILL cr);
7953 size(4);
7954 format %{ "OILL $dst,$con" %}
7955 opcode(OILL_ZOPC);
7956 ins_encode(z_riform_unsigned(dst,con));
7957 ins_pipe(pipe_class_dummy);
7958 %}
7959
7960 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7961 match(Set dst (OrI dst con));
7962 effect(KILL cr);
7963 ins_cost(DEFAULT_COST_HIGH);
7964 size(6);
7965 format %{ "OILF $dst,$con" %}
7966 opcode(OILF_ZOPC);
7967 ins_encode(z_rilform_unsigned(dst,con));
7968 ins_pipe(pipe_class_dummy);
7969 %}
7970
7971 // Register Or Long
7972 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7973 match(Set dst (OrL dst src));
7974 effect(KILL cr);
7975 ins_cost(DEFAULT_COST);
7976 size(4);
7977 format %{ "OGR $dst,$src\t # long" %}
7978 opcode(OGR_ZOPC);
7979 ins_encode(z_rreform(dst, src));
7980 ins_pipe(pipe_class_dummy);
7981 %}
7982
7983 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7984 match(Set dst (OrL dst (LoadL src)));
7985 effect(KILL cr);
7986 ins_cost(MEMORY_REF_COST);
7987 size(Z_DISP3_SIZE);
7988 format %{ "OG $dst, $src\t # long" %}
7989 opcode(OG_ZOPC, OG_ZOPC);
7990 ins_encode(z_form_rt_mem_opt(dst, src));
7991 ins_pipe(pipe_class_dummy);
7992 %}
7993
7994 // Immediate Or long
7995 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
7996 match(Set dst (OrL dst con));
7997 effect(KILL cr);
7998 ins_cost(DEFAULT_COST);
7999 size(4);
8000 format %{ "OILL $dst,$con\t # long" %}
8001 opcode(OILL_ZOPC);
8002 ins_encode(z_riform_unsigned(dst,con));
8003 ins_pipe(pipe_class_dummy);
8004 %}
8005
8006 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
8007 match(Set dst (OrI dst con));
8008 effect(KILL cr);
8009 ins_cost(DEFAULT_COST_HIGH);
8010 // TODO: s390 port size(FIXED_SIZE);
8011 format %{ "OILF $dst,$con\t # long" %}
8012 opcode(OILF_ZOPC);
8013 ins_encode(z_rilform_unsigned(dst,con));
8014 ins_pipe(pipe_class_dummy);
8015 %}
8016
8017 // XOR
8018
8019 // Register Xor
8020 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8021 match(Set dst (XorI dst src));
8022 effect(KILL cr);
8023 size(2);
8024 format %{ "XR $dst,$src" %}
8025 opcode(XR_ZOPC);
8026 ins_encode(z_rrform(dst, src));
8027 ins_pipe(pipe_class_dummy);
8028 %}
8029
8030 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
8031 match(Set dst (XorI dst (LoadI src)));
8032 effect(KILL cr);
8033 ins_cost(MEMORY_REF_COST);
8034 // TODO: s390 port size(VARIABLE_SIZE);
8035 format %{ "X(Y) $dst, $src\t # int" %}
8036 opcode(XY_ZOPC, X_ZOPC);
8037 ins_encode(z_form_rt_mem_opt(dst, src));
8038 ins_pipe(pipe_class_dummy);
8039 %}
8040
8041 // Immediate Xor
8042 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
8043 match(Set dst (XorI dst src));
8044 effect(KILL cr);
8045 ins_cost(DEFAULT_COST_HIGH);
8046 size(6);
8047 format %{ "XILF $dst,$src" %}
8048 opcode(XILF_ZOPC);
8049 ins_encode(z_rilform_unsigned(dst, src));
8050 ins_pipe(pipe_class_dummy);
8051 %}
8052
8053 // Register Xor Long
8054 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
8055 match(Set dst (XorL dst src));
8056 effect(KILL cr);
8057 ins_cost(DEFAULT_COST);
8058 size(4);
8059 format %{ "XGR $dst,$src\t # long" %}
8060 opcode(XGR_ZOPC);
8061 ins_encode(z_rreform(dst, src));
8062 ins_pipe(pipe_class_dummy);
8063 %}
8064
8065 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
8066 match(Set dst (XorL dst (LoadL src)));
8067 effect(KILL cr);
8068 ins_cost(MEMORY_REF_COST);
8069 size(Z_DISP3_SIZE);
8070 format %{ "XG $dst, $src\t # long" %}
8071 opcode(XG_ZOPC, XG_ZOPC);
8072 ins_encode(z_form_rt_mem_opt(dst, src));
8073 ins_pipe(pipe_class_dummy);
8074 %}
8075
8076 // Immediate Xor Long
8077 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
8078 match(Set dst (XorL dst con));
8079 effect(KILL cr);
8080 ins_cost(DEFAULT_COST_HIGH);
8081 size(6);
8082 format %{ "XILF $dst,$con\t # long" %}
8083 opcode(XILF_ZOPC);
8084 ins_encode(z_rilform_unsigned(dst,con));
8085 ins_pipe(pipe_class_dummy);
8086 %}
8087
8088 //----------Convert to Boolean-------------------------------------------------
8089
8090 // Convert integer to boolean.
8091 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
8092 match(Set dst (Conv2B src));
8093 effect(KILL cr);
8094 ins_cost(3 * DEFAULT_COST);
8095 size(6);
8096 format %{ "convI2B $dst,$src" %}
8097 ins_encode %{
8098 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
8099 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
8100 %}
8101 ins_pipe(pipe_class_dummy);
8102 %}
8103
8104 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
8105 match(Set dst (Conv2B src));
8106 effect(KILL cr);
8107 ins_cost(3 * DEFAULT_COST);
8108 size(10);
8109 format %{ "convP2B $dst,$src" %}
8110 ins_encode %{
8111 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
8112 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
8113 %}
8114 ins_pipe(pipe_class_dummy);
8115 %}
8116
8117 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8118 match(Set dst (CmpLTMask dst src));
8119 effect(KILL cr);
8120 ins_cost(2 * DEFAULT_COST);
8121 size(18);
8122 format %{ "Set $dst CmpLTMask $dst,$src" %}
8123 ins_encode %{
8124 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
8125 __ z_lgfr(Z_R0_scratch, $src$$Register);
8126 __ z_lgfr($dst$$Register, $dst$$Register);
8127 __ z_sgr($dst$$Register, Z_R0_scratch);
8128 __ z_srag($dst$$Register, $dst$$Register, 63);
8129 %}
8130 ins_pipe(pipe_class_dummy);
8131 %}
8132
8133 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
8134 match(Set dst (CmpLTMask dst zero));
8135 effect(KILL cr);
8136 ins_cost(DEFAULT_COST);
8137 size(4);
8138 format %{ "Set $dst CmpLTMask $dst,$zero" %}
8139 ins_encode %{ __ z_sra($dst$$Register, 31); %}
8140 ins_pipe(pipe_class_dummy);
8141 %}
8142
8143
8144 //----------Arithmetic Conversion Instructions---------------------------------
8145 // The conversions operations are all Alpha sorted. Please keep it that way!
8146
8147 instruct convD2F_reg(regF dst, regD src) %{
8148 match(Set dst (ConvD2F src));
8149 // CC remains unchanged.
8150 size(4);
8151 format %{ "LEDBR $dst,$src" %}
8152 opcode(LEDBR_ZOPC);
8153 ins_encode(z_rreform(dst, src));
8154 ins_pipe(pipe_class_dummy);
8155 %}
8156
8157 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
8158 match(Set dst (ConvF2I src));
8159 effect(KILL cr);
8160 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8161 size(16);
8162 format %{ "convF2I $dst,$src" %}
8163 ins_encode %{
8164 Label done;
8165 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8166 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8167 __ z_brno(done); // Result is zero if unordered argument.
8168 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8169 __ bind(done);
8170 %}
8171 ins_pipe(pipe_class_dummy);
8172 %}
8173
8174 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
8175 match(Set dst (ConvD2I src));
8176 effect(KILL cr);
8177 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8178 size(16);
8179 format %{ "convD2I $dst,$src" %}
8180 ins_encode %{
8181 Label done;
8182 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8183 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8184 __ z_brno(done); // Result is zero if unordered argument.
8185 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8186 __ bind(done);
8187 %}
8188 ins_pipe(pipe_class_dummy);
8189 %}
8190
8191 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8192 match(Set dst (ConvF2L src));
8193 effect(KILL cr);
8194 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8195 size(16);
8196 format %{ "convF2L $dst,$src" %}
8197 ins_encode %{
8198 Label done;
8199 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8200 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8201 __ z_brno(done); // Result is zero if unordered argument.
8202 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8203 __ bind(done);
8204 %}
8205 ins_pipe(pipe_class_dummy);
8206 %}
8207
8208 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8209 match(Set dst (ConvD2L src));
8210 effect(KILL cr);
8211 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8212 size(16);
8213 format %{ "convD2L $dst,$src" %}
8214 ins_encode %{
8215 Label done;
8216 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8217 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8218 __ z_brno(done); // Result is zero if unordered argument.
8219 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8220 __ bind(done);
8221 %}
8222 ins_pipe(pipe_class_dummy);
8223 %}
8224
8225 instruct convF2D_reg(regD dst, regF src) %{
8226 match(Set dst (ConvF2D src));
8227 // CC remains unchanged.
8228 size(4);
8229 format %{ "LDEBR $dst,$src" %}
8230 opcode(LDEBR_ZOPC);
8231 ins_encode(z_rreform(dst, src));
8232 ins_pipe(pipe_class_dummy);
8233 %}
8234
8235 instruct convF2D_mem(regD dst, memoryRX src) %{
8236 match(Set dst (ConvF2D src));
8237 // CC remains unchanged.
8238 size(6);
8239 format %{ "LDEB $dst,$src" %}
8240 opcode(LDEB_ZOPC);
8241 ins_encode(z_form_rt_memFP(dst, src));
8242 ins_pipe(pipe_class_dummy);
8243 %}
8244
8245 instruct convI2D_reg(regD dst, iRegI src) %{
8246 match(Set dst (ConvI2D src));
8247 // CC remains unchanged.
8248 ins_cost(DEFAULT_COST);
8249 size(4);
8250 format %{ "CDFBR $dst,$src" %}
8251 opcode(CDFBR_ZOPC);
8252 ins_encode(z_rreform(dst, src));
8253 ins_pipe(pipe_class_dummy);
8254 %}
8255
8256 // Optimization that saves up to two memory operations for each conversion.
8257 instruct convI2F_ireg(regF dst, iRegI src) %{
8258 match(Set dst (ConvI2F src));
8259 // CC remains unchanged.
8260 ins_cost(DEFAULT_COST);
8261 size(4);
8262 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8263 opcode(CEFBR_ZOPC);
8264 ins_encode(z_rreform(dst, src));
8265 ins_pipe(pipe_class_dummy);
8266 %}
8267
8268 instruct convI2L_reg(iRegL dst, iRegI src) %{
8269 match(Set dst (ConvI2L src));
8270 size(4);
8271 format %{ "LGFR $dst,$src\t # int->long" %}
8272 opcode(LGFR_ZOPC);
8273 ins_encode(z_rreform(dst, src));
8274 ins_pipe(pipe_class_dummy);
8275 %}
8276
8277 // Zero-extend convert int to long.
8278 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8279 match(Set dst (AndL (ConvI2L src) mask));
8280 size(4);
8281 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8282 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8283 ins_pipe(pipe_class_dummy);
8284 %}
8285
8286 // Zero-extend convert int to long.
8287 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8288 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8289 // Uses load_const_optmized, so size can vary.
8290 // TODO: s390 port size(VARIABLE_SIZE);
8291 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8292 opcode(LLGF_ZOPC, LLGF_ZOPC);
8293 ins_encode(z_form_rt_mem_opt(dst, src));
8294 ins_pipe(pipe_class_dummy);
8295 %}
8296
8297 // Zero-extend long
8298 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8299 match(Set dst (AndL src mask));
8300 size(4);
8301 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8302 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8303 ins_pipe(pipe_class_dummy);
8304 %}
8305
8306 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8307 match(Set dst (RShiftI (LShiftI src amount) amount));
8308 size(4);
8309 format %{ "LHR $dst,$src\t short->int" %}
8310 opcode(LHR_ZOPC);
8311 ins_encode(z_rreform(dst, src));
8312 ins_pipe(pipe_class_dummy);
8313 %}
8314
8315 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8316 match(Set dst (RShiftI (LShiftI src amount) amount));
8317 size(4);
8318 format %{ "LBR $dst,$src\t byte->int" %}
8319 opcode(LBR_ZOPC);
8320 ins_encode(z_rreform(dst, src));
8321 ins_pipe(pipe_class_dummy);
8322 %}
8323
8324 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8325 match(Set dst (MoveF2I src));
8326 ins_cost(MEMORY_REF_COST);
8327 size(4);
8328 format %{ "L $dst,$src\t # MoveF2I" %}
8329 opcode(L_ZOPC);
8330 ins_encode(z_form_rt_mem(dst, src));
8331 ins_pipe(pipe_class_dummy);
8332 %}
8333
8334 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8335 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8336 match(Set dst (MoveI2F src));
8337 ins_cost(MEMORY_REF_COST);
8338 // TODO: s390 port size(FIXED_SIZE);
8339 format %{ "LE $dst,$src\t # MoveI2F" %}
8340 opcode(LE_ZOPC);
8341 ins_encode(z_form_rt_mem(dst, src));
8342 ins_pipe(pipe_class_dummy);
8343 %}
8344
8345 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8346 match(Set dst (MoveD2L src));
8347 ins_cost(MEMORY_REF_COST);
8348 size(6);
8349 format %{ "LG $src,$dst\t # MoveD2L" %}
8350 opcode(LG_ZOPC);
8351 ins_encode(z_form_rt_mem(dst, src));
8352 ins_pipe(pipe_class_dummy);
8353 %}
8354
8355 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8356 match(Set dst (MoveL2D src));
8357 ins_cost(MEMORY_REF_COST);
8358 size(4);
8359 format %{ "LD $dst,$src\t # MoveL2D" %}
8360 opcode(LD_ZOPC);
8361 ins_encode(z_form_rt_mem(dst, src));
8362 ins_pipe(pipe_class_dummy);
8363 %}
8364
8365 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8366 match(Set dst (MoveI2F src));
8367 ins_cost(MEMORY_REF_COST);
8368 size(4);
8369 format %{ "ST $src,$dst\t # MoveI2F" %}
8370 opcode(ST_ZOPC);
8371 ins_encode(z_form_rt_mem(src, dst));
8372 ins_pipe(pipe_class_dummy);
8373 %}
8374
8375 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8376 match(Set dst (MoveD2L src));
8377 effect(DEF dst, USE src);
8378 ins_cost(MEMORY_REF_COST);
8379 size(4);
8380 format %{ "STD $src,$dst\t # MoveD2L" %}
8381 opcode(STD_ZOPC);
8382 ins_encode(z_form_rt_mem(src,dst));
8383 ins_pipe(pipe_class_dummy);
8384 %}
8385
8386 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8387 match(Set dst (MoveL2D src));
8388 ins_cost(MEMORY_REF_COST);
8389 size(6);
8390 format %{ "STG $src,$dst\t # MoveL2D" %}
8391 opcode(STG_ZOPC);
8392 ins_encode(z_form_rt_mem(src,dst));
8393 ins_pipe(pipe_class_dummy);
8394 %}
8395
8396 instruct convL2F_reg(regF dst, iRegL src) %{
8397 match(Set dst (ConvL2F src));
8398 // CC remains unchanged.
8399 ins_cost(DEFAULT_COST);
8400 size(4);
8401 format %{ "CEGBR $dst,$src" %}
8402 opcode(CEGBR_ZOPC);
8403 ins_encode(z_rreform(dst, src));
8404 ins_pipe(pipe_class_dummy);
8405 %}
8406
8407 instruct convL2D_reg(regD dst, iRegL src) %{
8408 match(Set dst (ConvL2D src));
8409 // CC remains unchanged.
8410 ins_cost(DEFAULT_COST);
8411 size(4);
8412 format %{ "CDGBR $dst,$src" %}
8413 opcode(CDGBR_ZOPC);
8414 ins_encode(z_rreform(dst, src));
8415 ins_pipe(pipe_class_dummy);
8416 %}
8417
8418 instruct convL2I_reg(iRegI dst, iRegL src) %{
8419 match(Set dst (ConvL2I src));
8420 // TODO: s390 port size(VARIABLE_SIZE);
8421 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8422 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8423 ins_pipe(pipe_class_dummy);
8424 %}
8425
8426 // Register Shift Right Immediate
8427 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8428 match(Set dst (ConvL2I (RShiftL src cnt)));
8429 effect(KILL cr);
8430 size(6);
8431 format %{ "SRAG $dst,$src,$cnt" %}
8432 opcode(SRAG_ZOPC);
8433 ins_encode(z_rsyform_const(dst, src, cnt));
8434 ins_pipe(pipe_class_dummy);
8435 %}
8436
8437 //----------TRAP based zero checks and range checks----------------------------
8438
8439 // SIGTRAP based implicit range checks in compiled code.
8440 // A range check in the ideal world has one of the following shapes:
8441 // - (If le (CmpU length index)), (IfTrue throw exception)
8442 // - (If lt (CmpU index length)), (IfFalse throw exception)
8443 //
8444 // Match range check 'If le (CmpU length index)'
8445 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8446 match(If cmp (CmpU length index));
8447 effect(USE labl);
8448 predicate(TrapBasedRangeChecks &&
8449 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8450 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8451 Matcher::branches_to_uncommon_trap(_leaf));
8452 ins_cost(1);
8453 // TODO: s390 port size(FIXED_SIZE);
8454
8455 ins_is_TrapBasedCheckNode(true);
8456
8457 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8458 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8459 ins_pipe(pipe_class_trap);
8460 %}
8461
8462 // Match range check 'If lt (CmpU index length)'
8463 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8464 match(If cmp (CmpU index length));
8465 effect(USE labl, KILL cr);
8466 predicate(TrapBasedRangeChecks &&
8467 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8468 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8469 Matcher::branches_to_uncommon_trap(_leaf));
8470 ins_cost(1);
8471 // TODO: s390 port size(FIXED_SIZE);
8472
8473 ins_is_TrapBasedCheckNode(true);
8474
8475 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8476 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8477 ins_pipe(pipe_class_trap);
8478 %}
8479
8480 // Match range check 'If lt (CmpU index length)'
8481 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8482 match(If cmp (CmpU index length));
8483 effect(USE labl);
8484 predicate(TrapBasedRangeChecks &&
8485 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8486 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8487 Matcher::branches_to_uncommon_trap(_leaf));
8488 ins_cost(1);
8489 // TODO: s390 port size(FIXED_SIZE);
8490
8491 ins_is_TrapBasedCheckNode(true);
8492
8493 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8494 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8495 ins_pipe(pipe_class_trap);
8496 %}
8497
8498 // Implicit zero checks (more implicit null checks).
8499 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8500 match(If cmp (CmpP value zero));
8501 effect(USE labl);
8502 predicate(TrapBasedNullChecks &&
8503 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8504 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8505 Matcher::branches_to_uncommon_trap(_leaf));
8506 size(6);
8507
8508 ins_is_TrapBasedCheckNode(true);
8509
8510 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8511 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8512 ins_pipe(pipe_class_trap);
8513 %}
8514
8515 // Implicit zero checks (more implicit null checks).
8516 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8517 match(If cmp (CmpN value zero));
8518 effect(USE labl);
8519 predicate(TrapBasedNullChecks &&
8520 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8521 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8522 Matcher::branches_to_uncommon_trap(_leaf));
8523 size(6);
8524
8525 ins_is_TrapBasedCheckNode(true);
8526
8527 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8528 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8529 ins_pipe(pipe_class_trap);
8530 %}
8531
8532 //----------Compare instructions-----------------------------------------------
8533
8534 // INT signed
8535
8536 // Compare Integers
8537 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8538 match(Set cr (CmpI op1 op2));
8539 size(2);
8540 format %{ "CR $op1,$op2" %}
8541 opcode(CR_ZOPC);
8542 ins_encode(z_rrform(op1, op2));
8543 ins_pipe(pipe_class_dummy);
8544 %}
8545
8546 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8547 match(Set cr (CmpI op1 op2));
8548 size(6);
8549 format %{ "CFI $op1,$op2" %}
8550 opcode(CFI_ZOPC);
8551 ins_encode(z_rilform_signed(op1, op2));
8552 ins_pipe(pipe_class_dummy);
8553 %}
8554
8555 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8556 match(Set cr (CmpI op1 op2));
8557 size(4);
8558 format %{ "CHI $op1,$op2" %}
8559 opcode(CHI_ZOPC);
8560 ins_encode(z_riform_signed(op1, op2));
8561 ins_pipe(pipe_class_dummy);
8562 %}
8563
8564 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8565 match(Set cr (CmpI op1 zero));
8566 ins_cost(DEFAULT_COST_LOW);
8567 size(2);
8568 format %{ "LTR $op1,$op1" %}
8569 opcode(LTR_ZOPC);
8570 ins_encode(z_rrform(op1, op1));
8571 ins_pipe(pipe_class_dummy);
8572 %}
8573
8574 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8575 match(Set cr (CmpI op1 (LoadI op2)));
8576 ins_cost(MEMORY_REF_COST);
8577 // TODO: s390 port size(VARIABLE_SIZE);
8578 format %{ "C(Y) $op1, $op2\t # int" %}
8579 opcode(CY_ZOPC, C_ZOPC);
8580 ins_encode(z_form_rt_mem_opt(op1, op2));
8581 ins_pipe(pipe_class_dummy);
8582 %}
8583
8584 // INT unsigned
8585
8586 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8587 match(Set cr (CmpU op1 op2));
8588 size(2);
8589 format %{ "CLR $op1,$op2\t # unsigned" %}
8590 opcode(CLR_ZOPC);
8591 ins_encode(z_rrform(op1, op2));
8592 ins_pipe(pipe_class_dummy);
8593 %}
8594
8595 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8596 match(Set cr (CmpU op1 op2));
8597 size(6);
8598 format %{ "CLFI $op1,$op2\t # unsigned" %}
8599 opcode(CLFI_ZOPC);
8600 ins_encode(z_rilform_unsigned(op1, op2));
8601 ins_pipe(pipe_class_dummy);
8602 %}
8603
8604 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8605 match(Set cr (CmpU op1 (LoadI op2)));
8606 ins_cost(MEMORY_REF_COST);
8607 // TODO: s390 port size(VARIABLE_SIZE);
8608 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8609 opcode(CLY_ZOPC, CL_ZOPC);
8610 ins_encode(z_form_rt_mem_opt(op1, op2));
8611 ins_pipe(pipe_class_dummy);
8612 %}
8613
8614 // LONG signed
8615
8616 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8617 match(Set cr (CmpL op1 op2));
8618 size(4);
8619 format %{ "CGR $op1,$op2\t # long" %}
8620 opcode(CGR_ZOPC);
8621 ins_encode(z_rreform(op1, op2));
8622 ins_pipe(pipe_class_dummy);
8623 %}
8624
8625 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8626 match(Set cr (CmpL op1 (ConvI2L op2)));
8627 size(4);
8628 format %{ "CGFR $op1,$op2\t # long/int" %}
8629 opcode(CGFR_ZOPC);
8630 ins_encode(z_rreform(op1, op2));
8631 ins_pipe(pipe_class_dummy);
8632 %}
8633
8634 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8635 match(Set cr (CmpL op1 con));
8636 size(6);
8637 format %{ "CGFI $op1,$con" %}
8638 opcode(CGFI_ZOPC);
8639 ins_encode(z_rilform_signed(op1, con));
8640 ins_pipe(pipe_class_dummy);
8641 %}
8642
8643 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8644 match(Set cr (CmpL op1 con));
8645 size(4);
8646 format %{ "CGHI $op1,$con" %}
8647 opcode(CGHI_ZOPC);
8648 ins_encode(z_riform_signed(op1, con));
8649 ins_pipe(pipe_class_dummy);
8650 %}
8651
8652 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8653 match(Set cr (CmpL op1 con));
8654 ins_cost(DEFAULT_COST_LOW);
8655 size(4);
8656 format %{ "LTGR $op1,$op1" %}
8657 opcode(LTGR_ZOPC);
8658 ins_encode(z_rreform(op1, op1));
8659 ins_pipe(pipe_class_dummy);
8660 %}
8661
8662 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8663 match(Set cr (CmpL (ConvI2L op1) con));
8664 ins_cost(DEFAULT_COST_LOW);
8665 size(4);
8666 format %{ "LTGFR $op1,$op1" %}
8667 opcode(LTGFR_ZOPC);
8668 ins_encode(z_rreform(op1, op1));
8669 ins_pipe(pipe_class_dummy);
8670 %}
8671
8672 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8673 match(Set cr (CmpL dst (LoadL src)));
8674 ins_cost(MEMORY_REF_COST);
8675 size(Z_DISP3_SIZE);
8676 format %{ "CG $dst, $src\t # long" %}
8677 opcode(CG_ZOPC, CG_ZOPC);
8678 ins_encode(z_form_rt_mem_opt(dst, src));
8679 ins_pipe(pipe_class_dummy);
8680 %}
8681
8682 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8683 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8684 ins_cost(MEMORY_REF_COST);
8685 size(Z_DISP3_SIZE);
8686 format %{ "CGF $dst, $src\t # long/int" %}
8687 opcode(CGF_ZOPC, CGF_ZOPC);
8688 ins_encode(z_form_rt_mem_opt(dst, src));
8689 ins_pipe(pipe_class_dummy);
8690 %}
8691
8692 // LONG unsigned
8693 // Added CmpUL for LoopPredicate.
8694 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8695 match(Set cr (CmpUL op1 op2));
8696 size(4);
8697 format %{ "CLGR $op1,$op2\t # long" %}
8698 opcode(CLGR_ZOPC);
8699 ins_encode(z_rreform(op1, op2));
8700 ins_pipe(pipe_class_dummy);
8701 %}
8702
8703 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8704 match(Set cr (CmpUL op1 con));
8705 size(6);
8706 format %{ "CLGFI $op1,$con" %}
8707 opcode(CLGFI_ZOPC);
8708 ins_encode(z_rilform_unsigned(op1, con));
8709 ins_pipe(pipe_class_dummy);
8710 %}
8711
8712 // PTR unsigned
8713
8714 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8715 match(Set cr (CmpP op1 op2));
8716 size(4);
8717 format %{ "CLGR $op1,$op2\t # ptr" %}
8718 opcode(CLGR_ZOPC);
8719 ins_encode(z_rreform(op1, op2));
8720 ins_pipe(pipe_class_dummy);
8721 %}
8722
8723 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8724 match(Set cr (CmpP op1 op2));
8725 ins_cost(DEFAULT_COST_LOW);
8726 size(4);
8727 format %{ "LTGR $op1, $op1\t # ptr" %}
8728 opcode(LTGR_ZOPC);
8729 ins_encode(z_rreform(op1, op1));
8730 ins_pipe(pipe_class_dummy);
8731 %}
8732
8733 // Don't use LTGFR which performs sign extend.
8734 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8735 match(Set cr (CmpP (DecodeN op1) op2));
8736 predicate(CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
8737 ins_cost(DEFAULT_COST_LOW);
8738 size(2);
8739 format %{ "LTR $op1, $op1\t # ptr" %}
8740 opcode(LTR_ZOPC);
8741 ins_encode(z_rrform(op1, op1));
8742 ins_pipe(pipe_class_dummy);
8743 %}
8744
8745 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8746 match(Set cr (CmpP dst (LoadP src)));
8747 ins_cost(MEMORY_REF_COST);
8748 size(Z_DISP3_SIZE);
8749 format %{ "CLG $dst, $src\t # ptr" %}
8750 opcode(CLG_ZOPC, CLG_ZOPC);
8751 ins_encode(z_form_rt_mem_opt(dst, src));
8752 ins_pipe(pipe_class_dummy);
8753 %}
8754
8755 //----------Max and Min--------------------------------------------------------
8756
8757 // Max Register with Register
8758 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8759 match(Set dst (MinI src1 src2));
8760 effect(KILL cr);
8761 predicate(VM_Version::has_LoadStoreConditional());
8762 ins_cost(3 * DEFAULT_COST);
8763 // TODO: s390 port size(VARIABLE_SIZE);
8764 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8765 ins_encode %{
8766 Register Rdst = $dst$$Register;
8767 Register Rsrc1 = $src1$$Register;
8768 Register Rsrc2 = $src2$$Register;
8769
8770 if (Rsrc1 == Rsrc2) {
8771 if (Rdst != Rsrc1) {
8772 __ z_lgfr(Rdst, Rsrc1);
8773 }
8774 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8775 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8776 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8777 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8778 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8779 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8780 } else {
8781 // Rdst is disjoint from operands, move in either case.
8782 __ z_cr(Rsrc1, Rsrc2);
8783 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8784 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8785 }
8786 %}
8787 ins_pipe(pipe_class_dummy);
8788 %}
8789
8790 // Min Register with Register.
8791 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8792 match(Set dst (MinI src1 src2));
8793 effect(KILL cr);
8794 predicate(VM_Version::has_CompareBranch());
8795 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8796 // TODO: s390 port size(VARIABLE_SIZE);
8797 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8798 ins_encode %{
8799 Register Rdst = $dst$$Register;
8800 Register Rsrc1 = $src1$$Register;
8801 Register Rsrc2 = $src2$$Register;
8802 Label done;
8803
8804 if (Rsrc1 == Rsrc2) {
8805 if (Rdst != Rsrc1) {
8806 __ z_lgfr(Rdst, Rsrc1);
8807 }
8808 } else if (Rdst == Rsrc1) {
8809 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8810 __ z_lgfr(Rdst, Rsrc2);
8811 } else if (Rdst == Rsrc2) {
8812 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8813 __ z_lgfr(Rdst, Rsrc1);
8814 } else {
8815 __ z_lgfr(Rdst, Rsrc1);
8816 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8817 __ z_lgfr(Rdst, Rsrc2);
8818 }
8819 __ bind(done);
8820 %}
8821 ins_pipe(pipe_class_dummy);
8822 %}
8823
8824 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8825 match(Set dst (MinI src1 src2));
8826 effect(KILL cr);
8827 predicate(!VM_Version::has_CompareBranch());
8828 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8829 // TODO: s390 port size(VARIABLE_SIZE);
8830 format %{ "MinI $dst $src1,$src2\t MinI" %}
8831 ins_encode %{
8832 Register Rdst = $dst$$Register;
8833 Register Rsrc1 = $src1$$Register;
8834 Register Rsrc2 = $src2$$Register;
8835 Label done;
8836
8837 if (Rsrc1 == Rsrc2) {
8838 if (Rdst != Rsrc1) {
8839 __ z_lgfr(Rdst, Rsrc1);
8840 }
8841 } else if (Rdst == Rsrc1) {
8842 __ z_cr(Rsrc1, Rsrc2);
8843 __ z_brl(done);
8844 __ z_lgfr(Rdst, Rsrc2);
8845 } else if (Rdst == Rsrc2) {
8846 __ z_cr(Rsrc2, Rsrc1);
8847 __ z_brl(done);
8848 __ z_lgfr(Rdst, Rsrc1);
8849 } else {
8850 __ z_lgfr(Rdst, Rsrc1);
8851 __ z_cr(Rsrc1, Rsrc2);
8852 __ z_brl(done);
8853 __ z_lgfr(Rdst, Rsrc2);
8854 }
8855 __ bind(done);
8856 %}
8857 ins_pipe(pipe_class_dummy);
8858 %}
8859
8860 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8861 match(Set dst (MinI src1 src2));
8862 effect(KILL cr);
8863 predicate(VM_Version::has_LoadStoreConditional());
8864 ins_cost(3 * DEFAULT_COST);
8865 // TODO: s390 port size(VARIABLE_SIZE);
8866 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8867 ins_encode %{
8868 Register Rdst = $dst$$Register;
8869 Register Rsrc1 = $src1$$Register;
8870 int Isrc2 = $src2$$constant;
8871
8872 if (Rdst == Rsrc1) {
8873 __ load_const_optimized(Z_R0_scratch, Isrc2);
8874 __ z_cfi(Rsrc1, Isrc2);
8875 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8876 } else {
8877 __ load_const_optimized(Rdst, Isrc2);
8878 __ z_cfi(Rsrc1, Isrc2);
8879 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8880 }
8881 %}
8882 ins_pipe(pipe_class_dummy);
8883 %}
8884
8885 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8886 match(Set dst (MinI src1 src2));
8887 effect(KILL cr);
8888 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8889 // TODO: s390 port size(VARIABLE_SIZE);
8890 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8891 ins_encode %{
8892 Label done;
8893 if ($dst$$Register != $src1$$Register) {
8894 __ z_lgfr($dst$$Register, $src1$$Register);
8895 }
8896 __ z_cfi($src1$$Register, $src2$$constant);
8897 __ z_brl(done);
8898 __ z_lgfi($dst$$Register, $src2$$constant);
8899 __ bind(done);
8900 %}
8901 ins_pipe(pipe_class_dummy);
8902 %}
8903
8904 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8905 match(Set dst (MinI src1 src2));
8906 effect(KILL cr);
8907 predicate(VM_Version::has_LoadStoreConditional());
8908 ins_cost(3 * DEFAULT_COST);
8909 // TODO: s390 port size(VARIABLE_SIZE);
8910 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8911 ins_encode %{
8912 Register Rdst = $dst$$Register;
8913 Register Rsrc1 = $src1$$Register;
8914 int Isrc2 = $src2$$constant;
8915
8916 if (Rdst == Rsrc1) {
8917 __ load_const_optimized(Z_R0_scratch, Isrc2);
8918 __ z_chi(Rsrc1, Isrc2);
8919 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8920 } else {
8921 __ load_const_optimized(Rdst, Isrc2);
8922 __ z_chi(Rsrc1, Isrc2);
8923 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8924 }
8925 %}
8926 ins_pipe(pipe_class_dummy);
8927 %}
8928
8929 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8930 match(Set dst (MinI src1 src2));
8931 effect(KILL cr);
8932 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8933 // TODO: s390 port size(VARIABLE_SIZE);
8934 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8935 ins_encode %{
8936 Label done;
8937 if ($dst$$Register != $src1$$Register) {
8938 __ z_lgfr($dst$$Register, $src1$$Register);
8939 }
8940 __ z_chi($src1$$Register, $src2$$constant);
8941 __ z_brl(done);
8942 __ z_lghi($dst$$Register, $src2$$constant);
8943 __ bind(done);
8944 %}
8945 ins_pipe(pipe_class_dummy);
8946 %}
8947
8948 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8949 match(Set dst (MinI src1 src2));
8950 effect(KILL cr);
8951 predicate(VM_Version::has_CompareBranch());
8952 ins_cost(DEFAULT_COST + BRANCH_COST);
8953 // TODO: s390 port size(VARIABLE_SIZE);
8954 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8955 ins_encode %{
8956 Label done;
8957 if ($dst$$Register != $src1$$Register) {
8958 __ z_lgfr($dst$$Register, $src1$$Register);
8959 }
8960 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8961 __ z_lghi($dst$$Register, $src2$$constant);
8962 __ bind(done);
8963 %}
8964 ins_pipe(pipe_class_dummy);
8965 %}
8966
8967 // Max Register with Register
8968 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8969 match(Set dst (MaxI src1 src2));
8970 effect(KILL cr);
8971 predicate(VM_Version::has_LoadStoreConditional());
8972 ins_cost(3 * DEFAULT_COST);
8973 // TODO: s390 port size(VARIABLE_SIZE);
8974 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8975 ins_encode %{
8976 Register Rdst = $dst$$Register;
8977 Register Rsrc1 = $src1$$Register;
8978 Register Rsrc2 = $src2$$Register;
8979
8980 if (Rsrc1 == Rsrc2) {
8981 if (Rdst != Rsrc1) {
8982 __ z_lgfr(Rdst, Rsrc1);
8983 }
8984 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8985 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
8986 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8987 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8988 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
8989 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8990 } else { // Rdst is disjoint from operands, move in either case.
8991 __ z_cr(Rsrc1, Rsrc2);
8992 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8993 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8994 }
8995 %}
8996 ins_pipe(pipe_class_dummy);
8997 %}
8998
8999 // Max Register with Register
9000 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9001 match(Set dst (MaxI src1 src2));
9002 effect(KILL cr);
9003 predicate(VM_Version::has_CompareBranch());
9004 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9005 // TODO: s390 port size(VARIABLE_SIZE);
9006 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
9007 ins_encode %{
9008 Register Rdst = $dst$$Register;
9009 Register Rsrc1 = $src1$$Register;
9010 Register Rsrc2 = $src2$$Register;
9011 Label done;
9012
9013 if (Rsrc1 == Rsrc2) {
9014 if (Rdst != Rsrc1) {
9015 __ z_lgfr(Rdst, Rsrc1);
9016 }
9017 } else if (Rdst == Rsrc1) {
9018 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9019 __ z_lgfr(Rdst, Rsrc2);
9020 } else if (Rdst == Rsrc2) {
9021 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
9022 __ z_lgfr(Rdst, Rsrc1);
9023 } else {
9024 __ z_lgfr(Rdst, Rsrc1);
9025 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9026 __ z_lgfr(Rdst, Rsrc2);
9027 }
9028 __ bind(done);
9029 %}
9030 ins_pipe(pipe_class_dummy);
9031 %}
9032
9033 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9034 match(Set dst (MaxI src1 src2));
9035 effect(KILL cr);
9036 predicate(!VM_Version::has_CompareBranch());
9037 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
9038 // TODO: s390 port size(VARIABLE_SIZE);
9039 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
9040 ins_encode %{
9041 Register Rdst = $dst$$Register;
9042 Register Rsrc1 = $src1$$Register;
9043 Register Rsrc2 = $src2$$Register;
9044 Label done;
9045
9046 if (Rsrc1 == Rsrc2) {
9047 if (Rdst != Rsrc1) {
9048 __ z_lgfr(Rdst, Rsrc1);
9049 }
9050 } else if (Rdst == Rsrc1) {
9051 __ z_cr(Rsrc1, Rsrc2);
9052 __ z_brh(done);
9053 __ z_lgfr(Rdst, Rsrc2);
9054 } else if (Rdst == Rsrc2) {
9055 __ z_cr(Rsrc2, Rsrc1);
9056 __ z_brh(done);
9057 __ z_lgfr(Rdst, Rsrc1);
9058 } else {
9059 __ z_lgfr(Rdst, Rsrc1);
9060 __ z_cr(Rsrc1, Rsrc2);
9061 __ z_brh(done);
9062 __ z_lgfr(Rdst, Rsrc2);
9063 }
9064
9065 __ bind(done);
9066 %}
9067
9068 ins_pipe(pipe_class_dummy);
9069 %}
9070
9071 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9072 match(Set dst (MaxI src1 src2));
9073 effect(KILL cr);
9074 predicate(VM_Version::has_LoadStoreConditional());
9075 ins_cost(3 * DEFAULT_COST);
9076 // TODO: s390 port size(VARIABLE_SIZE);
9077 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
9078 ins_encode %{
9079 Register Rdst = $dst$$Register;
9080 Register Rsrc1 = $src1$$Register;
9081 int Isrc2 = $src2$$constant;
9082
9083 if (Rdst == Rsrc1) {
9084 __ load_const_optimized(Z_R0_scratch, Isrc2);
9085 __ z_cfi(Rsrc1, Isrc2);
9086 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9087 } else {
9088 __ load_const_optimized(Rdst, Isrc2);
9089 __ z_cfi(Rsrc1, Isrc2);
9090 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9091 }
9092 %}
9093 ins_pipe(pipe_class_dummy);
9094 %}
9095
9096 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9097 match(Set dst (MaxI src1 src2));
9098 effect(KILL cr);
9099 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9100 // TODO: s390 port size(VARIABLE_SIZE);
9101 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
9102 ins_encode %{
9103 Label done;
9104 if ($dst$$Register != $src1$$Register) {
9105 __ z_lgfr($dst$$Register, $src1$$Register);
9106 }
9107 __ z_cfi($src1$$Register, $src2$$constant);
9108 __ z_brh(done);
9109 __ z_lgfi($dst$$Register, $src2$$constant);
9110 __ bind(done);
9111 %}
9112 ins_pipe(pipe_class_dummy);
9113 %}
9114
9115 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9116 match(Set dst (MaxI src1 src2));
9117 effect(KILL cr);
9118 predicate(VM_Version::has_LoadStoreConditional());
9119 ins_cost(3 * DEFAULT_COST);
9120 // TODO: s390 port size(VARIABLE_SIZE);
9121 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
9122 ins_encode %{
9123 Register Rdst = $dst$$Register;
9124 Register Rsrc1 = $src1$$Register;
9125 int Isrc2 = $src2$$constant;
9126 if (Rdst == Rsrc1) {
9127 __ load_const_optimized(Z_R0_scratch, Isrc2);
9128 __ z_chi(Rsrc1, Isrc2);
9129 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9130 } else {
9131 __ load_const_optimized(Rdst, Isrc2);
9132 __ z_chi(Rsrc1, Isrc2);
9133 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9134 }
9135 %}
9136 ins_pipe(pipe_class_dummy);
9137 %}
9138
9139 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9140 match(Set dst (MaxI src1 src2));
9141 effect(KILL cr);
9142 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9143 // TODO: s390 port size(VARIABLE_SIZE);
9144 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
9145 ins_encode %{
9146 Label done;
9147 if ($dst$$Register != $src1$$Register) {
9148 __ z_lgfr($dst$$Register, $src1$$Register);
9149 }
9150 __ z_chi($src1$$Register, $src2$$constant);
9151 __ z_brh(done);
9152 __ z_lghi($dst$$Register, $src2$$constant);
9153 __ bind(done);
9154 %}
9155 ins_pipe(pipe_class_dummy);
9156 %}
9157
9158 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
9159 match(Set dst (MaxI src1 src2));
9160 effect(KILL cr);
9161 predicate(VM_Version::has_CompareBranch());
9162 ins_cost(DEFAULT_COST + BRANCH_COST);
9163 // TODO: s390 port size(VARIABLE_SIZE);
9164 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
9165 ins_encode %{
9166 Label done;
9167 if ($dst$$Register != $src1$$Register) {
9168 __ z_lgfr($dst$$Register, $src1$$Register);
9169 }
9170 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
9171 __ z_lghi($dst$$Register, $src2$$constant);
9172 __ bind(done);
9173 %}
9174 ins_pipe(pipe_class_dummy);
9175 %}
9176
9177 //----------Abs---------------------------------------------------------------
9178
9179 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
9180 match(Set dst (AbsI src));
9181 effect(KILL cr);
9182 ins_cost(DEFAULT_COST_LOW);
9183 // TODO: s390 port size(FIXED_SIZE);
9184 format %{ "LPR $dst, $src" %}
9185 opcode(LPR_ZOPC);
9186 ins_encode(z_rrform(dst, src));
9187 ins_pipe(pipe_class_dummy);
9188 %}
9189
9190 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
9191 match(Set dst (AbsL src));
9192 effect(KILL cr);
9193 ins_cost(DEFAULT_COST_LOW);
9194 // TODO: s390 port size(FIXED_SIZE);
9195 format %{ "LPGR $dst, $src" %}
9196 opcode(LPGR_ZOPC);
9197 ins_encode(z_rreform(dst, src));
9198 ins_pipe(pipe_class_dummy);
9199 %}
9200
9201 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9202 match(Set dst (SubI zero (AbsI src)));
9203 effect(KILL cr);
9204 ins_cost(DEFAULT_COST_LOW);
9205 // TODO: s390 port size(FIXED_SIZE);
9206 format %{ "LNR $dst, $src" %}
9207 opcode(LNR_ZOPC);
9208 ins_encode(z_rrform(dst, src));
9209 ins_pipe(pipe_class_dummy);
9210 %}
9211
9212 //----------Float Compares----------------------------------------------------
9213
9214 // Compare floating, generate condition code.
9215 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9216 match(Set cr (CmpF src1 src2));
9217 ins_cost(ALU_REG_COST);
9218 size(4);
9219 format %{ "FCMPcc $src1,$src2\t # float" %}
9220 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9221 ins_pipe(pipe_class_dummy);
9222 %}
9223
9224 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9225 match(Set cr (CmpD src1 src2));
9226 ins_cost(ALU_REG_COST);
9227 size(4);
9228 format %{ "FCMPcc $src1,$src2 \t # double" %}
9229 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9230 ins_pipe(pipe_class_dummy);
9231 %}
9232
9233 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9234 match(Set cr (CmpF src1 (LoadF src2)));
9235 ins_cost(ALU_MEMORY_COST);
9236 size(6);
9237 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9238 opcode(CEB_ZOPC);
9239 ins_encode(z_form_rt_memFP(src1, src2));
9240 ins_pipe(pipe_class_dummy);
9241 %}
9242
9243 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9244 match(Set cr (CmpD src1 (LoadD src2)));
9245 ins_cost(ALU_MEMORY_COST);
9246 size(6);
9247 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9248 opcode(CDB_ZOPC);
9249 ins_encode(z_form_rt_memFP(src1, src2));
9250 ins_pipe(pipe_class_dummy);
9251 %}
9252
9253 // Compare floating, generate condition code
9254 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9255 match(Set cr (CmpF src1 src2));
9256 ins_cost(DEFAULT_COST);
9257 size(4);
9258 format %{ "LTEBR $src1,$src1\t # float" %}
9259 opcode(LTEBR_ZOPC);
9260 ins_encode(z_rreform(src1, src1));
9261 ins_pipe(pipe_class_dummy);
9262 %}
9263
9264 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9265 match(Set cr (CmpD src1 src2));
9266 ins_cost(DEFAULT_COST);
9267 size(4);
9268 format %{ "LTDBR $src1,$src1 \t # double" %}
9269 opcode(LTDBR_ZOPC);
9270 ins_encode(z_rreform(src1, src1));
9271 ins_pipe(pipe_class_dummy);
9272 %}
9273
9274 // Compare floating, generate -1,0,1
9275 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9276 match(Set dst (CmpF3 src1 src2));
9277 effect(KILL cr);
9278 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9279 size(24);
9280 format %{ "CmpF3 $dst,$src1,$src2" %}
9281 ins_encode %{
9282 // compare registers
9283 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9284 // Convert condition code into -1,0,1, where
9285 // -1 means unordered or less
9286 // 0 means equal
9287 // 1 means greater.
9288 if (VM_Version::has_LoadStoreConditional()) {
9289 Register one = Z_R0_scratch;
9290 Register minus_one = Z_R1_scratch;
9291 __ z_lghi(minus_one, -1);
9292 __ z_lghi(one, 1);
9293 __ z_lghi( $dst$$Register, 0);
9294 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9295 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9296 } else {
9297 Label done;
9298 __ clear_reg($dst$$Register, true, false);
9299 __ z_bre(done);
9300 __ z_lhi($dst$$Register, 1);
9301 __ z_brh(done);
9302 __ z_lhi($dst$$Register, -1);
9303 __ bind(done);
9304 }
9305 %}
9306 ins_pipe(pipe_class_dummy);
9307 %}
9308
9309 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9310 match(Set dst (CmpD3 src1 src2));
9311 effect(KILL cr);
9312 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9313 size(24);
9314 format %{ "CmpD3 $dst,$src1,$src2" %}
9315 ins_encode %{
9316 // compare registers
9317 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9318 // Convert condition code into -1,0,1, where
9319 // -1 means unordered or less
9320 // 0 means equal
9321 // 1 means greater.
9322 if (VM_Version::has_LoadStoreConditional()) {
9323 Register one = Z_R0_scratch;
9324 Register minus_one = Z_R1_scratch;
9325 __ z_lghi(minus_one, -1);
9326 __ z_lghi(one, 1);
9327 __ z_lghi( $dst$$Register, 0);
9328 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9329 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9330 } else {
9331 Label done;
9332 // indicate unused result
9333 (void) __ clear_reg($dst$$Register, true, false);
9334 __ z_bre(done);
9335 __ z_lhi($dst$$Register, 1);
9336 __ z_brh(done);
9337 __ z_lhi($dst$$Register, -1);
9338 __ bind(done);
9339 }
9340 %}
9341 ins_pipe(pipe_class_dummy);
9342 %}
9343
9344 //----------Branches---------------------------------------------------------
9345 // Jump
9346
9347 // Direct Branch.
9348 instruct branch(label labl) %{
9349 match(Goto);
9350 effect(USE labl);
9351 ins_cost(BRANCH_COST);
9352 size(4);
9353 format %{ "BRU $labl" %}
9354 ins_encode(z_enc_bru(labl));
9355 ins_pipe(pipe_class_dummy);
9356 // If set to 1 this indicates that the current instruction is a
9357 // short variant of a long branch. This avoids using this
9358 // instruction in first-pass matching. It will then only be used in
9359 // the `Shorten_branches' pass.
9360 ins_short_branch(1);
9361 %}
9362
9363 // Direct Branch.
9364 instruct branchFar(label labl) %{
9365 match(Goto);
9366 effect(USE labl);
9367 ins_cost(BRANCH_COST);
9368 size(6);
9369 format %{ "BRUL $labl" %}
9370 ins_encode(z_enc_brul(labl));
9371 ins_pipe(pipe_class_dummy);
9372 // This is not a short variant of a branch, but the long variant.
9373 ins_short_branch(0);
9374 %}
9375
9376 // Conditional Near Branch
9377 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9378 // Same match rule as `branchConFar'.
9379 match(If cmp cr);
9380 effect(USE lbl);
9381 ins_cost(BRANCH_COST);
9382 size(4);
9383 format %{ "branch_con_short,$cmp $lbl" %}
9384 ins_encode(z_enc_branch_con_short(cmp, lbl));
9385 ins_pipe(pipe_class_dummy);
9386 // If set to 1 this indicates that the current instruction is a
9387 // short variant of a long branch. This avoids using this
9388 // instruction in first-pass matching. It will then only be used in
9389 // the `Shorten_branches' pass.
9390 ins_short_branch(1);
9391 %}
9392
9393 // This is for cases when the z/Architecture conditional branch instruction
9394 // does not reach far enough. So we emit a far branch here, which is
9395 // more expensive.
9396 //
9397 // Conditional Far Branch
9398 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9399 // Same match rule as `branchCon'.
9400 match(If cmp cr);
9401 effect(USE cr, USE lbl);
9402 // Make more expensive to prefer compare_and_branch over separate instructions.
9403 ins_cost(2 * BRANCH_COST);
9404 size(6);
9405 format %{ "branch_con_far,$cmp $lbl" %}
9406 ins_encode(z_enc_branch_con_far(cmp, lbl));
9407 ins_pipe(pipe_class_dummy);
9408 // This is not a short variant of a branch, but the long variant..
9409 ins_short_branch(0);
9410 %}
9411
9412 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9413 match(CountedLoopEnd cmp cr);
9414 effect(USE labl);
9415 ins_cost(BRANCH_COST);
9416 size(4);
9417 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9418 ins_encode(z_enc_branch_con_short(cmp, labl));
9419 ins_pipe(pipe_class_dummy);
9420 // If set to 1 this indicates that the current instruction is a
9421 // short variant of a long branch. This avoids using this
9422 // instruction in first-pass matching. It will then only be used in
9423 // the `Shorten_branches' pass.
9424 ins_short_branch(1);
9425 %}
9426
9427 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9428 match(CountedLoopEnd cmp cr);
9429 effect(USE labl);
9430 ins_cost(BRANCH_COST);
9431 size(6);
9432 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9433 ins_encode(z_enc_branch_con_far(cmp, labl));
9434 ins_pipe(pipe_class_dummy);
9435 // This is not a short variant of a branch, but the long variant.
9436 ins_short_branch(0);
9437 %}
9438
9439 //----------Compare and Branch (short distance)------------------------------
9440
9441 // INT REG operands for loop counter processing.
9442 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9443 match(CountedLoopEnd boolnode (CmpI src1 src2));
9444 effect(USE labl, KILL cr);
9445 predicate(VM_Version::has_CompareBranch());
9446 ins_cost(BRANCH_COST);
9447 // TODO: s390 port size(FIXED_SIZE);
9448 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9449 opcode(CRJ_ZOPC);
9450 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9451 ins_pipe(pipe_class_dummy);
9452 ins_short_branch(1);
9453 %}
9454
9455 // INT REG operands.
9456 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9457 match(If boolnode (CmpI src1 src2));
9458 effect(USE labl, KILL cr);
9459 predicate(VM_Version::has_CompareBranch());
9460 ins_cost(BRANCH_COST);
9461 // TODO: s390 port size(FIXED_SIZE);
9462 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9463 opcode(CRJ_ZOPC);
9464 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9465 ins_pipe(pipe_class_dummy);
9466 ins_short_branch(1);
9467 %}
9468
9469 // Unsigned INT REG operands
9470 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9471 match(If boolnode (CmpU src1 src2));
9472 effect(USE labl, KILL cr);
9473 predicate(VM_Version::has_CompareBranch());
9474 ins_cost(BRANCH_COST);
9475 // TODO: s390 port size(FIXED_SIZE);
9476 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9477 opcode(CLRJ_ZOPC);
9478 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9479 ins_pipe(pipe_class_dummy);
9480 ins_short_branch(1);
9481 %}
9482
9483 // LONG REG operands
9484 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9485 match(If boolnode (CmpL src1 src2));
9486 effect(USE labl, KILL cr);
9487 predicate(VM_Version::has_CompareBranch());
9488 ins_cost(BRANCH_COST);
9489 // TODO: s390 port size(FIXED_SIZE);
9490 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9491 opcode(CGRJ_ZOPC);
9492 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9493 ins_pipe(pipe_class_dummy);
9494 ins_short_branch(1);
9495 %}
9496
9497 // PTR REG operands
9498
9499 // Separate rules for regular and narrow oops. ADLC can't recognize
9500 // rules with polymorphic operands to be sisters -> shorten_branches
9501 // will not shorten.
9502
9503 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9504 match(If boolnode (CmpP src1 src2));
9505 effect(USE labl, KILL cr);
9506 predicate(VM_Version::has_CompareBranch());
9507 ins_cost(BRANCH_COST);
9508 // TODO: s390 port size(FIXED_SIZE);
9509 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9510 opcode(CLGRJ_ZOPC);
9511 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9512 ins_pipe(pipe_class_dummy);
9513 ins_short_branch(1);
9514 %}
9515
9516 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9517 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9518 effect(USE labl, KILL cr);
9519 predicate(VM_Version::has_CompareBranch());
9520 ins_cost(BRANCH_COST);
9521 // TODO: s390 port size(FIXED_SIZE);
9522 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9523 opcode(CLGRJ_ZOPC);
9524 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9525 ins_pipe(pipe_class_dummy);
9526 ins_short_branch(1);
9527 %}
9528
9529 // INT REG/IMM operands for loop counter processing
9530 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9531 match(CountedLoopEnd boolnode (CmpI src1 src2));
9532 effect(USE labl, KILL cr);
9533 predicate(VM_Version::has_CompareBranch());
9534 ins_cost(BRANCH_COST);
9535 // TODO: s390 port size(FIXED_SIZE);
9536 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9537 opcode(CIJ_ZOPC);
9538 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9539 ins_pipe(pipe_class_dummy);
9540 ins_short_branch(1);
9541 %}
9542
9543 // INT REG/IMM operands
9544 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9545 match(If boolnode (CmpI src1 src2));
9546 effect(USE labl, KILL cr);
9547 predicate(VM_Version::has_CompareBranch());
9548 ins_cost(BRANCH_COST);
9549 // TODO: s390 port size(FIXED_SIZE);
9550 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9551 opcode(CIJ_ZOPC);
9552 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9553 ins_pipe(pipe_class_dummy);
9554 ins_short_branch(1);
9555 %}
9556
9557 // INT REG/IMM operands
9558 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9559 match(If boolnode (CmpU src1 src2));
9560 effect(USE labl, KILL cr);
9561 predicate(VM_Version::has_CompareBranch());
9562 ins_cost(BRANCH_COST);
9563 // TODO: s390 port size(FIXED_SIZE);
9564 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9565 opcode(CLIJ_ZOPC);
9566 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9567 ins_pipe(pipe_class_dummy);
9568 ins_short_branch(1);
9569 %}
9570
9571 // LONG REG/IMM operands
9572 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9573 match(If boolnode (CmpL src1 src2));
9574 effect(USE labl, KILL cr);
9575 predicate(VM_Version::has_CompareBranch());
9576 ins_cost(BRANCH_COST);
9577 // TODO: s390 port size(FIXED_SIZE);
9578 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9579 opcode(CGIJ_ZOPC);
9580 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9581 ins_pipe(pipe_class_dummy);
9582 ins_short_branch(1);
9583 %}
9584
9585 // PTR REG-imm operands
9586
9587 // Separate rules for regular and narrow oops. ADLC can't recognize
9588 // rules with polymorphic operands to be sisters -> shorten_branches
9589 // will not shorten.
9590
9591 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9592 match(If boolnode (CmpP src1 src2));
9593 effect(USE labl, KILL cr);
9594 predicate(VM_Version::has_CompareBranch());
9595 ins_cost(BRANCH_COST);
9596 // TODO: s390 port size(FIXED_SIZE);
9597 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9598 opcode(CLGIJ_ZOPC);
9599 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9600 ins_pipe(pipe_class_dummy);
9601 ins_short_branch(1);
9602 %}
9603
9604 // Compare against zero only, do not mix N and P oops (encode/decode required).
9605 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9606 match(If boolnode (CmpP (DecodeN src1) src2));
9607 effect(USE labl, KILL cr);
9608 predicate(VM_Version::has_CompareBranch());
9609 ins_cost(BRANCH_COST);
9610 // TODO: s390 port size(FIXED_SIZE);
9611 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9612 opcode(CLGIJ_ZOPC);
9613 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9614 ins_pipe(pipe_class_dummy);
9615 ins_short_branch(1);
9616 %}
9617
9618 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9619 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9620 effect(USE labl, KILL cr);
9621 predicate(VM_Version::has_CompareBranch());
9622 ins_cost(BRANCH_COST);
9623 // TODO: s390 port size(FIXED_SIZE);
9624 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9625 opcode(CLGIJ_ZOPC);
9626 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9627 ins_pipe(pipe_class_dummy);
9628 ins_short_branch(1);
9629 %}
9630
9631
9632 //----------Compare and Branch (far distance)------------------------------
9633
9634 // INT REG operands for loop counter processing
9635 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9636 match(CountedLoopEnd boolnode (CmpI src1 src2));
9637 effect(USE labl, KILL cr);
9638 predicate(VM_Version::has_CompareBranch());
9639 ins_cost(BRANCH_COST+DEFAULT_COST);
9640 // TODO: s390 port size(FIXED_SIZE);
9641 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9642 opcode(CR_ZOPC, BRCL_ZOPC);
9643 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9644 ins_pipe(pipe_class_dummy);
9645 ins_short_branch(0);
9646 %}
9647
9648 // INT REG operands
9649 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9650 match(If boolnode (CmpI src1 src2));
9651 effect(USE labl, KILL cr);
9652 predicate(VM_Version::has_CompareBranch());
9653 ins_cost(BRANCH_COST+DEFAULT_COST);
9654 // TODO: s390 port size(FIXED_SIZE);
9655 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9656 opcode(CR_ZOPC, BRCL_ZOPC);
9657 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9658 ins_pipe(pipe_class_dummy);
9659 ins_short_branch(0);
9660 %}
9661
9662 // INT REG operands
9663 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9664 match(If boolnode (CmpU src1 src2));
9665 effect(USE labl, KILL cr);
9666 predicate(VM_Version::has_CompareBranch());
9667 ins_cost(BRANCH_COST+DEFAULT_COST);
9668 // TODO: s390 port size(FIXED_SIZE);
9669 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9670 opcode(CLR_ZOPC, BRCL_ZOPC);
9671 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9672 ins_pipe(pipe_class_dummy);
9673 ins_short_branch(0);
9674 %}
9675
9676 // LONG REG operands
9677 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9678 match(If boolnode (CmpL src1 src2));
9679 effect(USE labl, KILL cr);
9680 predicate(VM_Version::has_CompareBranch());
9681 ins_cost(BRANCH_COST+DEFAULT_COST);
9682 // TODO: s390 port size(FIXED_SIZE);
9683 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9684 opcode(CGR_ZOPC, BRCL_ZOPC);
9685 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9686 ins_pipe(pipe_class_dummy);
9687 ins_short_branch(0);
9688 %}
9689
9690 // PTR REG operands
9691
9692 // Separate rules for regular and narrow oops. ADLC can't recognize
9693 // rules with polymorphic operands to be sisters -> shorten_branches
9694 // will not shorten.
9695
9696 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9697 match(If boolnode (CmpP src1 src2));
9698 effect(USE labl, KILL cr);
9699 predicate(VM_Version::has_CompareBranch());
9700 ins_cost(BRANCH_COST+DEFAULT_COST);
9701 // TODO: s390 port size(FIXED_SIZE);
9702 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9703 opcode(CLGR_ZOPC, BRCL_ZOPC);
9704 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9705 ins_pipe(pipe_class_dummy);
9706 ins_short_branch(0);
9707 %}
9708
9709 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9710 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9711 effect(USE labl, KILL cr);
9712 predicate(VM_Version::has_CompareBranch());
9713 ins_cost(BRANCH_COST+DEFAULT_COST);
9714 // TODO: s390 port size(FIXED_SIZE);
9715 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9716 opcode(CLGR_ZOPC, BRCL_ZOPC);
9717 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9718 ins_pipe(pipe_class_dummy);
9719 ins_short_branch(0);
9720 %}
9721
9722 // INT REG/IMM operands for loop counter processing
9723 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9724 match(CountedLoopEnd boolnode (CmpI src1 src2));
9725 effect(USE labl, KILL cr);
9726 predicate(VM_Version::has_CompareBranch());
9727 ins_cost(BRANCH_COST+DEFAULT_COST);
9728 // TODO: s390 port size(FIXED_SIZE);
9729 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9730 opcode(CHI_ZOPC, BRCL_ZOPC);
9731 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9732 ins_pipe(pipe_class_dummy);
9733 ins_short_branch(0);
9734 %}
9735
9736 // INT REG/IMM operands
9737 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9738 match(If boolnode (CmpI src1 src2));
9739 effect(USE labl, KILL cr);
9740 predicate(VM_Version::has_CompareBranch());
9741 ins_cost(BRANCH_COST+DEFAULT_COST);
9742 // TODO: s390 port size(FIXED_SIZE);
9743 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9744 opcode(CHI_ZOPC, BRCL_ZOPC);
9745 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9746 ins_pipe(pipe_class_dummy);
9747 ins_short_branch(0);
9748 %}
9749
9750 // INT REG/IMM operands
9751 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9752 match(If boolnode (CmpU src1 src2));
9753 effect(USE labl, KILL cr);
9754 predicate(VM_Version::has_CompareBranch());
9755 ins_cost(BRANCH_COST+DEFAULT_COST);
9756 // TODO: s390 port size(FIXED_SIZE);
9757 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9758 opcode(CLFI_ZOPC, BRCL_ZOPC);
9759 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9760 ins_pipe(pipe_class_dummy);
9761 ins_short_branch(0);
9762 %}
9763
9764 // LONG REG/IMM operands
9765 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9766 match(If boolnode (CmpL src1 src2));
9767 effect(USE labl, KILL cr);
9768 predicate(VM_Version::has_CompareBranch());
9769 ins_cost(BRANCH_COST+DEFAULT_COST);
9770 // TODO: s390 port size(FIXED_SIZE);
9771 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9772 opcode(CGHI_ZOPC, BRCL_ZOPC);
9773 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9774 ins_pipe(pipe_class_dummy);
9775 ins_short_branch(0);
9776 %}
9777
9778 // PTR REG-imm operands
9779
9780 // Separate rules for regular and narrow oops. ADLC can't recognize
9781 // rules with polymorphic operands to be sisters -> shorten_branches
9782 // will not shorten.
9783
9784 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9785 match(If boolnode (CmpP src1 src2));
9786 effect(USE labl, KILL cr);
9787 predicate(VM_Version::has_CompareBranch());
9788 ins_cost(BRANCH_COST+DEFAULT_COST);
9789 // TODO: s390 port size(FIXED_SIZE);
9790 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9791 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9792 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9793 ins_pipe(pipe_class_dummy);
9794 ins_short_branch(0);
9795 %}
9796
9797 // Compare against zero only, do not mix N and P oops (encode/decode required).
9798 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9799 match(If boolnode (CmpP (DecodeN src1) src2));
9800 effect(USE labl, KILL cr);
9801 predicate(VM_Version::has_CompareBranch());
9802 ins_cost(BRANCH_COST+DEFAULT_COST);
9803 // TODO: s390 port size(FIXED_SIZE);
9804 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9805 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9806 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9807 ins_pipe(pipe_class_dummy);
9808 ins_short_branch(0);
9809 %}
9810
9811 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9812 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9813 effect(USE labl, KILL cr);
9814 predicate(VM_Version::has_CompareBranch());
9815 ins_cost(BRANCH_COST+DEFAULT_COST);
9816 // TODO: s390 port size(FIXED_SIZE);
9817 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9818 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9819 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9820 ins_pipe(pipe_class_dummy);
9821 ins_short_branch(0);
9822 %}
9823
9824 // ============================================================================
9825 // Long Compare
9826
9827 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9828 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9829 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9830 // are collapsed internally in the ADLC's dfa-gen code. The match for
9831 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9832 // foo match ends up with the wrong leaf. One fix is to not match both
9833 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9834 // both forms beat the trinary form of long-compare and both are very useful
9835 // on platforms which have few registers.
9836
9837 // Manifest a CmpL3 result in an integer register. Very painful.
9838 // This is the test to avoid.
9839 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9840 match(Set dst (CmpL3 src1 src2));
9841 effect(KILL cr);
9842 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9843 size(24);
9844 format %{ "CmpL3 $dst,$src1,$src2" %}
9845 ins_encode %{
9846 Label done;
9847 // compare registers
9848 __ z_cgr($src1$$Register, $src2$$Register);
9849 // Convert condition code into -1,0,1, where
9850 // -1 means less
9851 // 0 means equal
9852 // 1 means greater.
9853 if (VM_Version::has_LoadStoreConditional()) {
9854 Register one = Z_R0_scratch;
9855 Register minus_one = Z_R1_scratch;
9856 __ z_lghi(minus_one, -1);
9857 __ z_lghi(one, 1);
9858 __ z_lghi( $dst$$Register, 0);
9859 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9860 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9861 } else {
9862 __ clear_reg($dst$$Register, true, false);
9863 __ z_bre(done);
9864 __ z_lhi($dst$$Register, 1);
9865 __ z_brh(done);
9866 __ z_lhi($dst$$Register, -1);
9867 }
9868 __ bind(done);
9869 %}
9870 ins_pipe(pipe_class_dummy);
9871 %}
9872
9873 // ============================================================================
9874 // Safepoint Instruction
9875
9876 instruct safePoint() %{
9877 match(SafePoint);
9878 predicate(false);
9879 // TODO: s390 port size(FIXED_SIZE);
9880 format %{ "UNIMPLEMENTED Safepoint_ " %}
9881 ins_encode(enc_unimplemented());
9882 ins_pipe(pipe_class_dummy);
9883 %}
9884
9885 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9886 match(SafePoint poll);
9887 effect(USE poll, KILL cr); // R0 is killed, too.
9888 // TODO: s390 port size(FIXED_SIZE);
9889 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9890 ins_encode %{
9891 // Mark the code position where the load from the safepoint
9892 // polling page was emitted as relocInfo::poll_type.
9893 __ relocate(relocInfo::poll_type);
9894 __ load_from_polling_page($poll$$Register);
9895 %}
9896 ins_pipe(pipe_class_dummy);
9897 %}
9898
9899 // ============================================================================
9900
9901 // Call Instructions
9902
9903 // Call Java Static Instruction
9904 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9905 match(CallStaticJava);
9906 effect(USE meth);
9907 ins_cost(CALL_COST);
9908 // TODO: s390 port size(VARIABLE_SIZE);
9909 format %{ "CALL,static dynTOC $meth; ==> " %}
9910 ins_encode( z_enc_java_static_call(meth) );
9911 ins_pipe(pipe_class_dummy);
9912 ins_alignment(2);
9913 %}
9914
9915 // Call Java Dynamic Instruction
9916 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9917 match(CallDynamicJava);
9918 effect(USE meth);
9919 ins_cost(CALL_COST);
9920 // TODO: s390 port size(VARIABLE_SIZE);
9921 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9922 ins_encode(z_enc_java_dynamic_call(meth));
9923 ins_pipe(pipe_class_dummy);
9924 ins_alignment(2);
9925 %}
9926
9927 // Call Runtime Instruction
9928 instruct CallRuntimeDirect(method meth) %{
9929 match(CallRuntime);
9930 effect(USE meth);
9931 ins_cost(CALL_COST);
9932 // TODO: s390 port size(VARIABLE_SIZE);
9933 ins_num_consts(1);
9934 ins_alignment(2);
9935 format %{ "CALL,runtime" %}
9936 ins_encode( z_enc_java_to_runtime_call(meth) );
9937 ins_pipe(pipe_class_dummy);
9938 %}
9939
9940 // Call runtime without safepoint - same as CallRuntime
9941 instruct CallLeafDirect(method meth) %{
9942 match(CallLeaf);
9943 effect(USE meth);
9944 ins_cost(CALL_COST);
9945 // TODO: s390 port size(VARIABLE_SIZE);
9946 ins_num_consts(1);
9947 ins_alignment(2);
9948 format %{ "CALL,runtime leaf $meth" %}
9949 ins_encode( z_enc_java_to_runtime_call(meth) );
9950 ins_pipe(pipe_class_dummy);
9951 %}
9952
9953 // Call runtime without safepoint - same as CallLeaf
9954 instruct CallLeafNoFPDirect(method meth) %{
9955 match(CallLeafNoFP);
9956 effect(USE meth);
9957 ins_cost(CALL_COST);
9958 // TODO: s390 port size(VARIABLE_SIZE);
9959 ins_num_consts(1);
9960 format %{ "CALL,runtime leaf nofp $meth" %}
9961 ins_encode( z_enc_java_to_runtime_call(meth) );
9962 ins_pipe(pipe_class_dummy);
9963 ins_alignment(2);
9964 %}
9965
9966 // Tail Call; Jump from runtime stub to Java code.
9967 // Also known as an 'interprocedural jump'.
9968 // Target of jump will eventually return to caller.
9969 // TailJump below removes the return address.
9970 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{
9971 match(TailCall jump_target method_ptr);
9972 ins_cost(CALL_COST);
9973 size(2);
9974 format %{ "Jmp $jump_target\t # $method_ptr holds method" %}
9975 ins_encode %{ __ z_br($jump_target$$Register); %}
9976 ins_pipe(pipe_class_dummy);
9977 %}
9978
9979 // Return Instruction
9980 instruct Ret() %{
9981 match(Return);
9982 size(2);
9983 format %{ "BR(Z_R14) // branch to link register" %}
9984 ins_encode %{ __ z_br(Z_R14); %}
9985 ins_pipe(pipe_class_dummy);
9986 %}
9987
9988 // Tail Jump; remove the return address; jump to target.
9989 // TailCall above leaves the return address around.
9990 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9991 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9992 // "restore" before this instruction (in Epilogue), we need to materialize it
9993 // in %i0.
9994 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9995 match(TailJump jump_target ex_oop);
9996 ins_cost(CALL_COST);
9997 size(8);
9998 format %{ "TailJump $jump_target" %}
9999 ins_encode %{
10000 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
10001 __ z_br($jump_target$$Register);
10002 %}
10003 ins_pipe(pipe_class_dummy);
10004 %}
10005
10006 // Forward exception.
10007 instruct ForwardExceptionjmp() %{
10008 match(ForwardException);
10009 ins_cost(CALL_COST);
10010 format %{ "Jmp forward_exception_stub" %}
10011 ins_encode %{
10012 __ set_inst_mark();
10013 __ load_const_optimized(Z_R1_scratch, (address)StubRoutines::forward_exception_entry());
10014 __ z_br(Z_R1_scratch);
10015 __ clear_inst_mark();
10016 %}
10017 ins_pipe(pipe_class_dummy);
10018 %}
10019
10020 // Create exception oop: created by stack-crawling runtime code.
10021 // Created exception is now available to this handler, and is setup
10022 // just prior to jumping to this handler. No code emitted.
10023 instruct CreateException(rarg1RegP ex_oop) %{
10024 match(Set ex_oop (CreateEx));
10025 ins_cost(0);
10026 size(0);
10027 format %{ "# exception oop; no code emitted" %}
10028 ins_encode(/*empty*/);
10029 ins_pipe(pipe_class_dummy);
10030 %}
10031
10032 // Rethrow exception: The exception oop will come in the first
10033 // argument position. Then JUMP (not call) to the rethrow stub code.
10034 instruct RethrowException() %{
10035 match(Rethrow);
10036 ins_cost(CALL_COST);
10037 // TODO: s390 port size(VARIABLE_SIZE);
10038 format %{ "Jmp rethrow_stub" %}
10039 ins_encode %{
10040 __ set_inst_mark();
10041 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
10042 __ z_br(Z_R1_scratch);
10043 __ clear_inst_mark();
10044 %}
10045 ins_pipe(pipe_class_dummy);
10046 %}
10047
10048 // Die now.
10049 instruct ShouldNotReachHere() %{
10050 match(Halt);
10051 ins_cost(CALL_COST);
10052 format %{ "ILLTRAP; ShouldNotReachHere" %}
10053 ins_encode %{
10054 if (is_reachable()) {
10055 const char* str = __ code_string(_halt_reason);
10056 __ stop(str);
10057 }
10058 %}
10059 ins_pipe(pipe_class_dummy);
10060 %}
10061
10062 // ============================================================================
10063 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10064 // array for an instance of the superklass. Set a hidden internal cache on a
10065 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10066 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10067 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
10068 rarg4RegP scratch1, rarg5RegP scratch2) %{
10069 match(Set index (PartialSubtypeCheck sub super));
10070 predicate(!UseSecondarySupersTable);
10071 effect(KILL pcc, KILL scratch1, KILL scratch2);
10072 ins_cost(20 * DEFAULT_COST); // slightly larger than the next version
10073 // TODO: s390 port size(FIXED_SIZE);
10074 format %{ " CALL PartialSubtypeCheck\n" %}
10075 ins_encode %{
10076 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
10077 __ load_const_optimized(Z_ARG4, stub_address);
10078 __ z_basr(Z_R14, Z_ARG4);
10079 %}
10080 ins_pipe(pipe_class_dummy);
10081 %}
10082
10083 // Two versions of partialSubtypeCheck, both used when we need to
10084 // search for a super class in the secondary supers array. The first
10085 // is used when we don't know _a priori_ the class being searched
10086 // for. The second, far more common, is used when we do know: this is
10087 // used for instanceof, checkcast, and any case where C2 can determine
10088 // it by constant propagation.
10089 instruct partialSubtypeCheckVarSuper(rarg2RegP sub, rarg3RegP super,
10090 r11TempRegP result,
10091 rarg1RegP temp1, rarg4RegP temp2, rarg5RegP temp3, r10TempRegP temp4,
10092 flagsReg pcc) %{
10093 match(Set result (PartialSubtypeCheck sub super));
10094 predicate(UseSecondarySupersTable);
10095 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10096 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10097 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10098 ins_encode %{
10099 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register,
10100 $temp1$$Register, $temp2$$Register, $temp3$$Register, $temp4$$Register,
10101 $result$$Register);
10102 %}
10103 ins_pipe(pipe_class_dummy);
10104 %}
10105
10106
10107 instruct partialSubtypeCheckConstSuper(rarg2RegP sub, rarg1RegP super, immP super_con,
10108 r11TempRegP result, rarg5RegP temp1, rarg4RegP temp2,
10109 rarg3RegP temp3, r10TempRegP temp4, flagsReg pcc) %{
10110 match(Set result (PartialSubtypeCheck sub (Binary super super_con)));
10111 predicate(UseSecondarySupersTable);
10112 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10113 ins_cost(5 * DEFAULT_COST); // smaller than the next version
10114 format %{ "partialSubtypeCheck $result, $sub, $super, $super_con" %}
10115
10116 ins_encode %{
10117 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10118 if (InlineSecondarySupersTest) {
10119 __ lookup_secondary_supers_table_const($sub$$Register, $super$$Register,
10120 $temp1$$Register, $temp2$$Register, $temp3$$Register,
10121 $temp4$$Register, $result$$Register, super_klass_slot);
10122 } else {
10123 AddressLiteral stub_address(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot));
10124 __ load_const_optimized(Z_ARG4, stub_address);
10125 __ z_basr(Z_R14, Z_ARG4);
10126 }
10127
10128 %}
10129
10130 ins_pipe(pipe_class_dummy);
10131 %}
10132
10133 // ============================================================================
10134 // inlined locking and unlocking
10135
10136 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10137 match(Set pcc (FastLock oop box));
10138 effect(TEMP tmp1, TEMP tmp2);
10139 ins_cost(100);
10140 // TODO: s390 port size(VARIABLE_SIZE);
10141 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10142 ins_encode %{
10143 __ fast_lock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10144 // If locking was successful, cc should indicate 'EQ'.
10145 // The compiler generates a branch to the runtime call to
10146 // _complete_monitor_locking_Java for the case where cc is 'NE'.
10147 %}
10148 ins_pipe(pipe_class_dummy);
10149 %}
10150
10151 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10152 match(Set pcc (FastUnlock oop box));
10153 effect(TEMP tmp1, TEMP tmp2);
10154 ins_cost(100);
10155 // TODO: s390 port size(FIXED_SIZE);
10156 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10157 ins_encode %{
10158 __ fast_unlock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10159 // If unlocking was successful, cc should indicate 'EQ'.
10160 // The compiler generates a branch to the runtime call to
10161 // _complete_monitor_unlocking_Java for the case where cc is 'NE'.
10162 %}
10163 ins_pipe(pipe_class_dummy);
10164 %}
10165
10166 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
10167 match(Set dummy (ClearArray cnt base));
10168 effect(KILL cr);
10169 ins_cost(100);
10170 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
10171 format %{ "ClearArrayConst $cnt,$base" %}
10172 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
10173 ins_pipe(pipe_class_dummy);
10174 %}
10175
10176 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10177 match(Set dummy (ClearArray cnt base));
10178 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10179 ins_cost(200);
10180 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
10181 format %{ "ClearArrayConstBig $cnt,$base" %}
10182 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
10183 ins_pipe(pipe_class_dummy);
10184 %}
10185
10186 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10187 match(Set dummy (ClearArray cnt base));
10188 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10189 ins_cost(300);
10190 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
10191 format %{ "ClearArrayVar $cnt,$base" %}
10192 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
10193 ins_pipe(pipe_class_dummy);
10194 %}
10195
10196 // ============================================================================
10197 // CompactStrings
10198
10199 // String equals
10200 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10201 match(Set result (StrEquals (Binary str1 str2) cnt));
10202 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10203 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10204 ins_cost(300);
10205 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10206 ins_encode %{
10207 __ array_equals(false, $str1$$Register, $str2$$Register,
10208 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
10209 $result$$Register, true /* byte */);
10210 %}
10211 ins_pipe(pipe_class_dummy);
10212 %}
10213
10214 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
10215 match(Set result (StrEquals (Binary str1 str2) cnt));
10216 effect(KILL cr); // R0 is killed, too.
10217 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10218 ins_cost(100);
10219 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10220 ins_encode %{
10221 const int cnt_imm = $cnt$$constant;
10222 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
10223 __ z_lhi($result$$Register, 1);
10224 if (cnt_imm) {
10225 if (VM_Version::has_LoadStoreConditional()) {
10226 __ z_lhi(Z_R0_scratch, 0);
10227 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10228 } else {
10229 Label Lskip;
10230 __ z_bre(Lskip);
10231 __ clear_reg($result$$Register);
10232 __ bind(Lskip);
10233 }
10234 }
10235 %}
10236 ins_pipe(pipe_class_dummy);
10237 %}
10238
10239 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
10240 match(Set result (StrEquals (Binary str1 str2) cnt));
10241 effect(KILL cr); // R0 is killed, too.
10242 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
10243 ins_cost(100);
10244 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10245 ins_encode %{
10246 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10247 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10248 __ z_lhi($result$$Register, 1);
10249 if (cnt_imm) {
10250 if (VM_Version::has_LoadStoreConditional()) {
10251 __ z_lhi(Z_R0_scratch, 0);
10252 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10253 } else {
10254 Label Lskip;
10255 __ z_bre(Lskip);
10256 __ clear_reg($result$$Register);
10257 __ bind(Lskip);
10258 }
10259 }
10260 %}
10261 ins_pipe(pipe_class_dummy);
10262 %}
10263
10264 // Array equals
10265 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10266 match(Set result (AryEq ary1 ary2));
10267 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10268 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10269 ins_cost(300);
10270 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10271 ins_encode %{
10272 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10273 noreg, $oddReg$$Register, $evenReg$$Register,
10274 $result$$Register, true /* byte */);
10275 %}
10276 ins_pipe(pipe_class_dummy);
10277 %}
10278
10279 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10280 match(Set result (AryEq ary1 ary2));
10281 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10282 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10283 ins_cost(300);
10284 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10285 ins_encode %{
10286 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10287 noreg, $oddReg$$Register, $evenReg$$Register,
10288 $result$$Register, false /* byte */);
10289 %}
10290 ins_pipe(pipe_class_dummy);
10291 %}
10292
10293 // String CompareTo
10294 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10295 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10296 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10297 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10298 ins_cost(300);
10299 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10300 ins_encode %{
10301 __ string_compare($str1$$Register, $str2$$Register,
10302 $cnt1$$Register, $cnt2$$Register,
10303 $oddReg$$Register, $evenReg$$Register,
10304 $result$$Register, StrIntrinsicNode::LL);
10305 %}
10306 ins_pipe(pipe_class_dummy);
10307 %}
10308
10309 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10310 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10311 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10312 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10313 ins_cost(300);
10314 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10315 ins_encode %{
10316 __ string_compare($str1$$Register, $str2$$Register,
10317 $cnt1$$Register, $cnt2$$Register,
10318 $oddReg$$Register, $evenReg$$Register,
10319 $result$$Register, StrIntrinsicNode::UU);
10320 %}
10321 ins_pipe(pipe_class_dummy);
10322 %}
10323
10324 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10325 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10326 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10327 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10328 ins_cost(300);
10329 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10330 ins_encode %{
10331 __ string_compare($str1$$Register, $str2$$Register,
10332 $cnt1$$Register, $cnt2$$Register,
10333 $oddReg$$Register, $evenReg$$Register,
10334 $result$$Register, StrIntrinsicNode::LU);
10335 %}
10336 ins_pipe(pipe_class_dummy);
10337 %}
10338
10339 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10340 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10341 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10342 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10343 ins_cost(300);
10344 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10345 ins_encode %{
10346 __ string_compare($str2$$Register, $str1$$Register,
10347 $cnt2$$Register, $cnt1$$Register,
10348 $oddReg$$Register, $evenReg$$Register,
10349 $result$$Register, StrIntrinsicNode::UL);
10350 %}
10351 ins_pipe(pipe_class_dummy);
10352 %}
10353
10354 // String IndexOfChar
10355 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10356 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10357 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10358 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
10359 ins_cost(200);
10360 format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10361 ins_encode %{
10362 __ string_indexof_char($result$$Register,
10363 $haystack$$Register, $haycnt$$Register,
10364 $ch$$Register, 0 /* unused, ch is in register */,
10365 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10366 %}
10367 ins_pipe(pipe_class_dummy);
10368 %}
10369
10370 instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10371 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10372 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10373 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
10374 ins_cost(200);
10375 format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10376 ins_encode %{
10377 __ string_indexof_char($result$$Register,
10378 $haystack$$Register, $haycnt$$Register,
10379 $ch$$Register, 0 /* unused, ch is in register */,
10380 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10381 %}
10382 ins_pipe(pipe_class_dummy);
10383 %}
10384
10385 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10386 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10387 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10388 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10389 ins_cost(200);
10390 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10391 ins_encode %{
10392 immPOper *needleOper = (immPOper *)$needle;
10393 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10394 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10395 jchar chr;
10396 #ifdef VM_LITTLE_ENDIAN
10397 Unimplemented();
10398 #else
10399 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10400 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10401 #endif
10402 __ string_indexof_char($result$$Register,
10403 $haystack$$Register, $haycnt$$Register,
10404 noreg, chr,
10405 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10406 %}
10407 ins_pipe(pipe_class_dummy);
10408 %}
10409
10410 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10411 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10412 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10413 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10414 ins_cost(200);
10415 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10416 ins_encode %{
10417 immPOper *needleOper = (immPOper *)$needle;
10418 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10419 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10420 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10421 __ string_indexof_char($result$$Register,
10422 $haystack$$Register, $haycnt$$Register,
10423 noreg, chr,
10424 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10425 %}
10426 ins_pipe(pipe_class_dummy);
10427 %}
10428
10429 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10430 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10431 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10432 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10433 ins_cost(200);
10434 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10435 ins_encode %{
10436 immPOper *needleOper = (immPOper *)$needle;
10437 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10438 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10439 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10440 __ string_indexof_char($result$$Register,
10441 $haystack$$Register, $haycnt$$Register,
10442 noreg, chr,
10443 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10444 %}
10445 ins_pipe(pipe_class_dummy);
10446 %}
10447
10448 // String IndexOf
10449 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10450 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10451 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10452 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10453 ins_cost(250);
10454 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10455 ins_encode %{
10456 __ string_indexof($result$$Register,
10457 $haystack$$Register, $haycnt$$Register,
10458 $needle$$Register, noreg, $needlecntImm$$constant,
10459 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10460 %}
10461 ins_pipe(pipe_class_dummy);
10462 %}
10463
10464 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10465 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10466 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10467 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10468 ins_cost(250);
10469 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10470 ins_encode %{
10471 __ string_indexof($result$$Register,
10472 $haystack$$Register, $haycnt$$Register,
10473 $needle$$Register, noreg, $needlecntImm$$constant,
10474 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10475 %}
10476 ins_pipe(pipe_class_dummy);
10477 %}
10478
10479 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10480 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10481 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10482 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10483 ins_cost(250);
10484 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10485 ins_encode %{
10486 __ string_indexof($result$$Register,
10487 $haystack$$Register, $haycnt$$Register,
10488 $needle$$Register, noreg, $needlecntImm$$constant,
10489 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10490 %}
10491 ins_pipe(pipe_class_dummy);
10492 %}
10493
10494 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10495 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10496 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10497 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10498 ins_cost(300);
10499 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10500 ins_encode %{
10501 __ string_indexof($result$$Register,
10502 $haystack$$Register, $haycnt$$Register,
10503 $needle$$Register, $needlecnt$$Register, 0,
10504 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10505 %}
10506 ins_pipe(pipe_class_dummy);
10507 %}
10508
10509 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10510 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10511 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10512 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10513 ins_cost(300);
10514 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10515 ins_encode %{
10516 __ string_indexof($result$$Register,
10517 $haystack$$Register, $haycnt$$Register,
10518 $needle$$Register, $needlecnt$$Register, 0,
10519 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10520 %}
10521 ins_pipe(pipe_class_dummy);
10522 %}
10523
10524 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10525 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10526 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10527 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10528 ins_cost(300);
10529 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10530 ins_encode %{
10531 __ string_indexof($result$$Register,
10532 $haystack$$Register, $haycnt$$Register,
10533 $needle$$Register, $needlecnt$$Register, 0,
10534 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10535 %}
10536 ins_pipe(pipe_class_dummy);
10537 %}
10538
10539 // char[] to byte[] compression
10540 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18,
10541 v19TempReg v19, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10542 match(Set result (StrCompressedCopy src (Binary dst len)));
10543 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19, TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10544 ins_cost(300);
10545 format %{ "String Compress $src->$dst($len) -> $result" %}
10546 ins_encode %{
10547 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10548 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10549 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10550 $v23$$VectorRegister);
10551 %}
10552 ins_pipe(pipe_class_dummy);
10553 %}
10554
10555 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10556 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10557 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10558 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10559 // predicate(VM_Version::has_ETF2Enhancements());
10560 // ins_cost(300);
10561 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10562 // ins_encode %{
10563 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10564 // %}
10565 // ins_pipe(pipe_class_dummy);
10566 //%}
10567
10568 // byte[] to char[] inflation
10569 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10570 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10571 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10572 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10573 ins_cost(300);
10574 format %{ "String Inflate $src->$dst($len)" %}
10575 ins_encode %{
10576 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, $v20$$VectorRegister,
10577 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10578 $v25$$VectorRegister);
10579 %}
10580 ins_pipe(pipe_class_dummy);
10581 %}
10582
10583 // byte[] to char[] inflation
10584 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10585 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10586 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10587 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10588 ins_cost(300);
10589 format %{ "String Inflate (constLen) $src->$dst($len)" %}
10590 ins_encode %{
10591 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant , $v20$$VectorRegister,
10592 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10593 $v25$$VectorRegister);
10594 %}
10595 ins_pipe(pipe_class_dummy);
10596 %}
10597
10598 // StringCoding.java intrinsics
10599 instruct count_positives(iRegP ary1, iRegI len, iRegI result, iRegI tmp, flagsReg cr) %{
10600 match(Set result (CountPositives ary1 len));
10601 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10602 ins_cost(300);
10603 format %{ "count positives byte[] $ary1($len) -> $result" %}
10604 ins_encode %{
10605 __ count_positives($result$$Register, $ary1$$Register, $len$$Register, $tmp$$Register);
10606 %}
10607 ins_pipe(pipe_class_dummy);
10608 %}
10609
10610 // encode char[] to byte[] in ISO_8859_1
10611 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10612 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10613 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
10614 match(Set result (EncodeISOArray src (Binary dst len)));
10615 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10616 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10617 ins_cost(300);
10618 format %{ "Encode iso array $src->$dst($len) -> $result" %}
10619 ins_encode %{
10620 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10621 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10622 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10623 $v23$$VectorRegister);
10624 %}
10625 ins_pipe(pipe_class_dummy);
10626 %}
10627
10628 // encode char[] to byte[] in ASCII
10629 instruct encode_ascii_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10630 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10631 predicate(((EncodeISOArrayNode*)n)->is_ascii());
10632 match(Set result (EncodeISOArray src (Binary dst len)));
10633 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10634 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10635 ins_cost(300);
10636 format %{ "Encode ascii array $src->$dst($len) -> $result" %}
10637 ins_encode %{
10638 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10639 $tmp$$Register, true, true, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10640 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10641 $v23$$VectorRegister);
10642 %}
10643 ins_pipe(pipe_class_dummy);
10644 %}
10645
10646
10647 //----------PEEPHOLE RULES-----------------------------------------------------
10648 // These must follow all instruction definitions as they use the names
10649 // defined in the instructions definitions.
10650 //
10651 // peepmatch (root_instr_name [preceeding_instruction]*);
10652 //
10653 // peepconstraint %{
10654 // (instruction_number.operand_name relational_op instruction_number.operand_name
10655 // [, ...]);
10656 // // instruction numbers are zero-based using left to right order in peepmatch
10657 //
10658 // peepreplace (instr_name([instruction_number.operand_name]*));
10659 // // provide an instruction_number.operand_name for each operand that appears
10660 // // in the replacement instruction's match rule
10661 //
10662 // ---------VM FLAGS---------------------------------------------------------
10663 //
10664 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10665 //
10666 // Each peephole rule is given an identifying number starting with zero and
10667 // increasing by one in the order seen by the parser. An individual peephole
10668 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10669 // on the command-line.
10670 //
10671 // ---------CURRENT LIMITATIONS----------------------------------------------
10672 //
10673 // Only match adjacent instructions in same basic block
10674 // Only equality constraints
10675 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10676 // Only one replacement instruction
10677 //
10678 // ---------EXAMPLE----------------------------------------------------------
10679 //
10680 // // pertinent parts of existing instructions in architecture description
10681 // instruct movI(eRegI dst, eRegI src) %{
10682 // match(Set dst (CopyI src));
10683 // %}
10684 //
10685 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10686 // match(Set dst (AddI dst src));
10687 // effect(KILL cr);
10688 // %}
10689 //
10690 // // Change (inc mov) to lea
10691 // peephole %{
10692 // // increment preceded by register-register move
10693 // peepmatch (incI_eReg movI);
10694 // // require that the destination register of the increment
10695 // // match the destination register of the move
10696 // peepconstraint (0.dst == 1.dst);
10697 // // construct a replacement instruction that sets
10698 // // the destination to (move's source register + one)
10699 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10700 // %}
10701 //
10702 // Implementation no longer uses movX instructions since
10703 // machine-independent system no longer uses CopyX nodes.
10704 //
10705 // peephole %{
10706 // peepmatch (incI_eReg movI);
10707 // peepconstraint (0.dst == 1.dst);
10708 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10709 // %}
10710 //
10711 // peephole %{
10712 // peepmatch (decI_eReg movI);
10713 // peepconstraint (0.dst == 1.dst);
10714 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10715 // %}
10716 //
10717 // peephole %{
10718 // peepmatch (addI_eReg_imm movI);
10719 // peepconstraint (0.dst == 1.dst);
10720 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10721 // %}
10722 //
10723 // peephole %{
10724 // peepmatch (addP_eReg_imm movP);
10725 // peepconstraint (0.dst == 1.dst);
10726 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10727 // %}
10728
10729
10730 // This peephole rule does not work, probably because ADLC can't handle two effects:
10731 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10732 // condense a load from memory and subsequent test for zero
10733 // into a single, more efficient ICM instruction.
10734 // peephole %{
10735 // peepmatch (compI_iReg_imm0 loadI);
10736 // peepconstraint (1.dst == 0.op1);
10737 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10738 // %}
10739
10740 // // Change load of spilled value to only a spill
10741 // instruct storeI(memory mem, eRegI src) %{
10742 // match(Set mem (StoreI mem src));
10743 // %}
10744 //
10745 // instruct loadI(eRegI dst, memory mem) %{
10746 // match(Set dst (LoadI mem));
10747 // %}
10748 //
10749 peephole %{
10750 peepmatch (loadI storeI);
10751 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10752 peepreplace (storeI(1.mem 1.mem 1.src));
10753 %}
10754
10755 peephole %{
10756 peepmatch (loadL storeL);
10757 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10758 peepreplace (storeL(1.mem 1.mem 1.src));
10759 %}
10760
10761 peephole %{
10762 peepmatch (loadP storeP);
10763 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10764 peepreplace (storeP(1.dst 1.dst 1.src));
10765 %}
10766
10767 //----------SUPERWORD RULES---------------------------------------------------
10768
10769 // Expand rules for special cases
10770
10771 instruct expand_storeF(stackSlotF mem, regF src) %{
10772 // No match rule, false predicate, for expand only.
10773 effect(DEF mem, USE src);
10774 predicate(false);
10775 ins_cost(MEMORY_REF_COST);
10776 // TODO: s390 port size(FIXED_SIZE);
10777 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10778 opcode(STE_ZOPC, STE_ZOPC);
10779 ins_encode(z_form_rt_mem(src, mem));
10780 ins_pipe(pipe_class_dummy);
10781 %}
10782
10783 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10784 // No match rule, false predicate, for expand only.
10785 effect(DEF dst, USE mem);
10786 predicate(false);
10787 ins_cost(MEMORY_REF_COST);
10788 // TODO: s390 port size(FIXED_SIZE);
10789 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10790 opcode(LLGF_ZOPC, LLGF_ZOPC);
10791 ins_encode(z_form_rt_mem(dst, mem));
10792 ins_pipe(pipe_class_dummy);
10793 %}
10794
10795 // Replicate scalar int to packed int values (8 Bytes)
10796 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10797 // Dummy match rule, false predicate, for expand only.
10798 match(Set dst (ConvI2L src));
10799 predicate(false);
10800 ins_cost(DEFAULT_COST);
10801 // TODO: s390 port size(FIXED_SIZE);
10802 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10803 ins_encode %{
10804 if ($dst$$Register == $src$$Register) {
10805 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10806 __ z_ogr($dst$$Register, Z_R0_scratch);
10807 } else {
10808 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10809 __ z_ogr( $dst$$Register, $src$$Register);
10810 }
10811 %}
10812 ins_pipe(pipe_class_dummy);
10813 %}
10814
10815 // Replication
10816
10817 // Exploit rotate_then_insert, if available
10818 // Replicate scalar byte to packed byte values (8 Bytes).
10819 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10820 match(Set dst (Replicate src));
10821 effect(KILL cr);
10822 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10823 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10824 ins_encode %{
10825 if ($dst$$Register != $src$$Register) {
10826 __ z_lgr($dst$$Register, $src$$Register);
10827 }
10828 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10829 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10830 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10831 %}
10832 ins_pipe(pipe_class_dummy);
10833 %}
10834
10835 // Replicate scalar byte to packed byte values (8 Bytes).
10836 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10837 match(Set dst (Replicate src));
10838 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10839 ins_should_rematerialize(true);
10840 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10841 ins_encode %{
10842 int64_t Isrc8 = $src$$constant & 0x000000ff;
10843 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10844 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10845 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10846
10847 __ z_llilf($dst$$Register, Isrc32);
10848 __ z_iihf($dst$$Register, Isrc32);
10849 %}
10850 ins_pipe(pipe_class_dummy);
10851 %}
10852
10853 // Replicate scalar byte to packed byte values (8 Bytes).
10854 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10855 match(Set dst (Replicate src));
10856 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10857 ins_should_rematerialize(true);
10858 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10859 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10860 ins_pipe(pipe_class_dummy);
10861 %}
10862
10863 // Replicate scalar byte to packed byte values (8 Bytes).
10864 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10865 match(Set dst (Replicate src));
10866 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10867 ins_should_rematerialize(true);
10868 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10869 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10870 ins_pipe(pipe_class_dummy);
10871 %}
10872
10873 // Exploit rotate_then_insert, if available
10874 // Replicate scalar short to packed short values (8 Bytes).
10875 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10876 match(Set dst (Replicate src));
10877 effect(KILL cr);
10878 predicate((n->as_Vector()->length() == 4) && Matcher::vector_element_basic_type(n) == T_SHORT);
10879 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10880 ins_encode %{
10881 if ($dst$$Register != $src$$Register) {
10882 __ z_lgr($dst$$Register, $src$$Register);
10883 }
10884 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10885 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10886 %}
10887 ins_pipe(pipe_class_dummy);
10888 %}
10889
10890 // Replicate scalar short to packed short values (8 Bytes).
10891 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10892 match(Set dst (Replicate src));
10893 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10894 ins_should_rematerialize(true);
10895 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10896 ins_encode %{
10897 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10898 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10899 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10900 ") should be handled by other match rules.", $src$$constant);
10901
10902 __ z_llilf($dst$$Register, Isrc32);
10903 __ z_iihf($dst$$Register, Isrc32);
10904 %}
10905 ins_pipe(pipe_class_dummy);
10906 %}
10907
10908 // Replicate scalar short to packed short values (8 Bytes).
10909 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10910 match(Set dst (Replicate src));
10911 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10912 ins_should_rematerialize(true);
10913 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10914 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10915 ins_pipe(pipe_class_dummy);
10916 %}
10917
10918 // Replicate scalar short to packed short values (8 Bytes).
10919 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10920 match(Set dst (Replicate src));
10921 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10922 ins_should_rematerialize(true);
10923 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10924 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10925 ins_pipe(pipe_class_dummy);
10926 %}
10927
10928 instruct repl8S_reg_Ex(vecX dst, iRegI src) %{
10929 match(Set dst (Replicate src));
10930 predicate(n->as_Vector()->length() == 8 &&
10931 Matcher::vector_element_basic_type(n) == T_SHORT);
10932
10933 size(12);
10934 ins_encode %{
10935 __ z_vlvgh($dst$$VectorRegister, $src$$Register, 0);
10936 __ z_vreph($dst$$VectorRegister, $dst$$VectorRegister, 0);
10937 %}
10938 ins_pipe(pipe_class_dummy);
10939 %}
10940
10941 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
10942 match(Set dst (Replicate src));
10943 predicate(n->as_Vector()->length() == 8 &&
10944 Matcher::vector_element_basic_type(n) == T_SHORT);
10945
10946 format %{ "VONE $dst, $src \t// replicate8S" %}
10947 size(6);
10948 ins_encode %{
10949 __ z_vone($dst$$VectorRegister);
10950 %}
10951 ins_pipe(pipe_class_dummy);
10952 %}
10953
10954 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
10955 match(Set dst (Replicate zero));
10956 predicate(n->as_Vector()->length() == 8 &&
10957 Matcher::vector_element_basic_type(n) == T_SHORT);
10958
10959 format %{ "VZERO $dst, $zero \t// replicate8S" %}
10960 size(6);
10961 ins_encode %{
10962 __ z_vzero($dst$$VectorRegister);
10963 %}
10964 ins_pipe(pipe_class_dummy);
10965 %}
10966
10967 // Exploit rotate_then_insert, if available.
10968 // Replicate scalar int to packed int values (8 Bytes).
10969 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10970 match(Set dst (Replicate src));
10971 effect(KILL cr);
10972 predicate((n->as_Vector()->length() == 2) && Matcher::vector_element_basic_type(n) == T_INT);
10973 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10974 ins_encode %{
10975 if ($dst$$Register != $src$$Register) {
10976 __ z_lgr($dst$$Register, $src$$Register);
10977 }
10978 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10979 %}
10980 ins_pipe(pipe_class_dummy);
10981 %}
10982
10983 // Replicate scalar int to packed int values (8 Bytes).
10984 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10985 match(Set dst (Replicate src));
10986 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
10987 ins_should_rematerialize(true);
10988 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10989 ins_encode %{
10990 int64_t Isrc32 = $src$$constant;
10991 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10992
10993 __ z_llilf($dst$$Register, Isrc32);
10994 __ z_iihf($dst$$Register, Isrc32);
10995 %}
10996 ins_pipe(pipe_class_dummy);
10997 %}
10998
10999 // Replicate scalar int to packed int values (8 Bytes).
11000 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
11001 match(Set dst (Replicate src));
11002 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11003 ins_should_rematerialize(true);
11004 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
11005 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11006 ins_pipe(pipe_class_dummy);
11007 %}
11008
11009 // Replicate scalar int to packed int values (8 Bytes).
11010 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
11011 match(Set dst (Replicate src));
11012 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11013 ins_should_rematerialize(true);
11014 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
11015 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
11016 ins_pipe(pipe_class_dummy);
11017 %}
11018
11019 instruct repl4I_reg_Ex(vecX dst, iRegI src) %{
11020 match(Set dst (Replicate src));
11021 predicate(n->as_Vector()->length() == 4 &&
11022 Matcher::vector_element_basic_type(n) == T_INT);
11023
11024 size(12);
11025 ins_encode %{
11026 __ z_vlvgf($dst$$VectorRegister, $src$$Register, 0);
11027 __ z_vrepf($dst$$VectorRegister, $dst$$VectorRegister, 0);
11028 %}
11029 ins_pipe(pipe_class_dummy);
11030 %}
11031
11032 instruct repl4I_immI0(vecX dst, immI_0 zero) %{
11033 match(Set dst (Replicate zero));
11034 predicate(n->as_Vector()->length() == 4 &&
11035 Matcher::vector_element_basic_type(n) == T_INT);
11036
11037 format %{ "VZERO $dst, $zero \t// replicate4I" %}
11038 size(6);
11039 ins_encode %{
11040 __ z_vzero($dst$$VectorRegister);
11041 %}
11042 ins_pipe(pipe_class_dummy);
11043 %}
11044
11045 instruct repl4I_immIminus1(vecX dst, immI_minus1 src) %{
11046 match(Set dst (Replicate src));
11047 predicate(n->as_Vector()->length() == 4 &&
11048 Matcher::vector_element_basic_type(n) == T_INT);
11049
11050 format %{ "VONE $dst, $dst, $dst \t// replicate4I" %}
11051 size(6);
11052 ins_encode %{
11053 __ z_vone($dst$$VectorRegister);
11054 %}
11055 ins_pipe(pipe_class_dummy);
11056 %}
11057
11058 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
11059 match(Set dst (Replicate src));
11060 effect(KILL cr);
11061 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11062 Matcher::vector_element_basic_type(n) == T_FLOAT);
11063 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
11064 expand %{
11065 stackSlotF tmp;
11066 iRegL tmp2;
11067 expand_storeF(tmp, src);
11068 expand_LoadLogical_I2L(tmp2, tmp);
11069 expand_Repl2I_reg(dst, tmp2);
11070 %}
11071 %}
11072
11073 // Replicate scalar float to packed float values in GREG (8 Bytes).
11074 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
11075 match(Set dst (Replicate src));
11076 effect(KILL cr);
11077 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11078 Matcher::vector_element_basic_type(n) == T_FLOAT);
11079 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
11080 ins_encode %{
11081 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
11082 __ z_lgdr($dst$$Register, $src$$FloatRegister);
11083
11084 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
11085 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
11086 __ z_ogr($dst$$Register, Z_R0_scratch);
11087 %}
11088 ins_pipe(pipe_class_dummy);
11089 %}
11090
11091 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
11092 instruct Repl2F_imm(iRegL dst, immF src) %{
11093 match(Set dst (Replicate src));
11094 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11095 ins_should_rematerialize(true);
11096 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
11097 ins_encode %{
11098 union {
11099 int Isrc32;
11100 float Fsrc32;
11101 };
11102 Fsrc32 = $src$$constant;
11103 __ z_llilf($dst$$Register, Isrc32);
11104 __ z_iihf($dst$$Register, Isrc32);
11105 %}
11106 ins_pipe(pipe_class_dummy);
11107 %}
11108
11109 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
11110 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
11111 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
11112 match(Set dst (Replicate src));
11113 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11114 ins_should_rematerialize(true);
11115 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
11116 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11117 ins_pipe(pipe_class_dummy);
11118 %}
11119
11120 instruct repl4F_reg_Ex(vecX dst, regF src) %{
11121 match(Set dst (Replicate src));
11122 predicate(n->as_Vector()->length() == 4 &&
11123 Matcher::vector_element_basic_type(n) == T_FLOAT);
11124
11125 format %{ "VREP $dst, $src \t// replicate4F" %}
11126 size(6);
11127
11128 ins_encode %{
11129 __ z_vrepf($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11130 %}
11131 ins_pipe(pipe_class_dummy);
11132 %}
11133
11134 instruct repl4F_immF0(vecX dst, immFp0 zero) %{
11135 match(Set dst (Replicate zero));
11136 predicate(n->as_Vector()->length() == 4 &&
11137 Matcher::vector_element_basic_type(n) == T_FLOAT);
11138
11139 format %{ "VZERO $dst, $zero \t// replicate4F" %}
11140 size(6);
11141 ins_encode %{
11142 __ z_vzero($dst$$VectorRegister);
11143 %}
11144 ins_pipe(pipe_class_dummy);
11145 %}
11146
11147 instruct repl2D_reg_Ex(vecX dst, regD src) %{
11148 match(Set dst (Replicate src));
11149 predicate(n->as_Vector()->length() == 2 &&
11150 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11151
11152 format %{ "VREP $dst, $src \t// replicate2D" %}
11153 size(6);
11154
11155 ins_encode %{
11156 __ z_vrepg($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11157 %}
11158 ins_pipe(pipe_class_dummy);
11159 %}
11160
11161 instruct repl2D_immD0(vecX dst, immDp0 zero) %{
11162 match(Set dst (Replicate zero));
11163 predicate(n->as_Vector()->length() == 2 &&
11164 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11165
11166 format %{ "VZERO $dst, $zero \t// replicate2D" %}
11167 size(6);
11168 ins_encode %{
11169 __ z_vzero($dst$$VectorRegister);
11170 %}
11171 ins_pipe(pipe_class_dummy);
11172 %}
11173
11174 instruct repl16B_reg_Ex(vecX dst, iRegI src) %{
11175 match(Set dst (Replicate src));
11176 predicate(n->as_Vector()->length() == 16 &&
11177 Matcher::vector_element_basic_type(n) == T_BYTE);
11178
11179 size(12);
11180 ins_encode %{
11181 __ z_vlvgb($dst$$VectorRegister, $src$$Register, 0);
11182 __ z_vrepb($dst$$VectorRegister, $dst$$VectorRegister, 0);
11183 %}
11184 ins_pipe(pipe_class_dummy);
11185 %}
11186
11187 instruct repl16B_immIminus1(vecX dst, immI_minus1 src) %{
11188 match(Set dst (Replicate src));
11189 predicate(n->as_Vector()->length() == 16 &&
11190 Matcher::vector_element_basic_type(n) == T_BYTE);
11191
11192 format %{ "VONE $dst, $src \t// replicate16B" %}
11193 size(6);
11194 ins_encode %{
11195 __ z_vone($dst$$VectorRegister);
11196 %}
11197 ins_pipe(pipe_class_dummy);
11198 %}
11199
11200 instruct repl16B_immI0(vecX dst, immI_0 zero) %{
11201 match(Set dst (Replicate zero));
11202 predicate(n->as_Vector()->length() == 16 &&
11203 Matcher::vector_element_basic_type(n) == T_BYTE);
11204
11205 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11206 size(6);
11207 ins_encode %{
11208 __ z_vzero($dst$$VectorRegister);
11209 %}
11210 ins_pipe(pipe_class_dummy);
11211 %}
11212
11213 instruct repl2L_reg_Ex(vecX dst, iRegL src) %{
11214 match(Set dst (Replicate src));
11215 predicate(n->as_Vector()->length() == 2 &&
11216 Matcher::vector_element_basic_type(n) == T_LONG);
11217
11218 size(12);
11219 ins_encode %{
11220 __ z_vlvgg($dst$$VectorRegister, $src$$Register, 0);
11221 __ z_vrepg($dst$$VectorRegister, $dst$$VectorRegister, 0);
11222 %}
11223 ins_pipe(pipe_class_dummy);
11224 %}
11225
11226 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
11227 match(Set dst (Replicate src));
11228 predicate(n->as_Vector()->length() == 2 &&
11229 Matcher::vector_element_basic_type(n) == T_LONG);
11230
11231 format %{ "VONE $dst, $src \t// replicate2L" %}
11232 size(6);
11233 ins_encode %{
11234 __ z_vone($dst$$VectorRegister);
11235 %}
11236 ins_pipe(pipe_class_dummy);
11237 %}
11238
11239 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
11240 match(Set dst (Replicate zero));
11241 predicate(n->as_Vector()->length() == 2 &&
11242 Matcher::vector_element_basic_type(n) == T_LONG);
11243
11244 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11245 size(6);
11246 ins_encode %{
11247 __ z_vzero($dst$$VectorRegister);
11248 %}
11249 ins_pipe(pipe_class_dummy);
11250 %}
11251
11252
11253 // Load/Store vector
11254
11255 // Store Aligned Packed Byte register to memory (8 Bytes).
11256 instruct storeA8B(memory mem, iRegL src) %{
11257 match(Set mem (StoreVector mem src));
11258 predicate(n->as_StoreVector()->memory_size() == 8);
11259 ins_cost(MEMORY_REF_COST);
11260 // TODO: s390 port size(VARIABLE_SIZE);
11261 format %{ "STG $src,$mem\t # ST(packed8B)" %}
11262 opcode(STG_ZOPC, STG_ZOPC);
11263 ins_encode(z_form_rt_mem_opt(src, mem));
11264 ins_pipe(pipe_class_dummy);
11265 %}
11266
11267 // Store Packed Byte long register to memory
11268 instruct storeV16(memoryRX mem, vecX src) %{
11269 predicate(n->as_StoreVector()->memory_size() == 16);
11270 match(Set mem (StoreVector mem src));
11271 ins_cost(MEMORY_REF_COST);
11272
11273 format %{ "VST $mem, $src \t// store 16-byte Vector" %}
11274 size(6);
11275 ins_encode %{
11276 __ z_vst($src$$VectorRegister,
11277 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11278 %}
11279 ins_pipe(pipe_class_dummy);
11280 %}
11281
11282 instruct loadV8(iRegL dst, memory mem) %{
11283 match(Set dst (LoadVector mem));
11284 predicate(n->as_LoadVector()->memory_size() == 8);
11285 ins_cost(MEMORY_REF_COST);
11286 // TODO: s390 port size(VARIABLE_SIZE);
11287 format %{ "LG $dst,$mem\t # L(packed8B)" %}
11288 opcode(LG_ZOPC, LG_ZOPC);
11289 ins_encode(z_form_rt_mem_opt(dst, mem));
11290 ins_pipe(pipe_class_dummy);
11291 %}
11292
11293 // Load Aligned Packed Byte
11294 instruct loadV16(vecX dst, memoryRX mem) %{
11295 predicate(n->as_LoadVector()->memory_size() == 16);
11296 match(Set dst (LoadVector mem));
11297 ins_cost(MEMORY_REF_COST);
11298
11299 format %{ "VL $dst, $mem \t// load 16-byte Vector" %}
11300 size(6);
11301 ins_encode %{
11302 __ z_vl($dst$$VectorRegister,
11303 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11304 %}
11305 ins_pipe(pipe_class_dummy);
11306 %}
11307
11308 // Reinterpret: only one vector size used
11309 instruct reinterpret(iRegL dst) %{
11310 match(Set dst (VectorReinterpret dst));
11311 ins_cost(0);
11312 format %{ "reinterpret $dst" %}
11313 ins_encode( /*empty*/ );
11314 ins_pipe(pipe_class_dummy);
11315 %}
11316
11317 instruct reinterpretX(vecX dst) %{
11318 match(Set dst (VectorReinterpret dst));
11319 ins_cost(0);
11320 format %{ "reinterpret $dst" %}
11321 ins_encode( /*empty*/ );
11322 ins_pipe(pipe_class_dummy);
11323 %}
11324
11325 //----------Vector Arithmetic Instructions--------------------------------------
11326
11327 // Vector Addition Instructions
11328
11329 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
11330 match(Set dst (AddVB src1 src2));
11331 predicate(n->as_Vector()->length() == 16);
11332 format %{ "VAB $dst,$src1,$src2\t// add packed16B" %}
11333 size(6);
11334 ins_encode %{
11335 __ z_vab($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11336 %}
11337 ins_pipe(pipe_class_dummy);
11338 %}
11339
11340 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
11341 match(Set dst (AddVS src1 src2));
11342 predicate(n->as_Vector()->length() == 8);
11343 format %{ "VAH $dst,$src1,$src2\t// add packed8S" %}
11344 size(6);
11345 ins_encode %{
11346 __ z_vah($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11347 %}
11348 ins_pipe(pipe_class_dummy);
11349 %}
11350
11351 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
11352 match(Set dst (AddVI src1 src2));
11353 predicate(n->as_Vector()->length() == 4);
11354 format %{ "VAF $dst,$src1,$src2\t// add packed4I" %}
11355 size(6);
11356 ins_encode %{
11357 __ z_vaf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11358 %}
11359 ins_pipe(pipe_class_dummy);
11360 %}
11361
11362 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
11363 match(Set dst (AddVL src1 src2));
11364 predicate(n->as_Vector()->length() == 2);
11365 format %{ "VAG $dst,$src1,$src2\t// add packed2L" %}
11366 size(6);
11367 ins_encode %{
11368 __ z_vag($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11369 %}
11370 ins_pipe(pipe_class_dummy);
11371 %}
11372
11373 instruct vmul16B_reg(vecX dst, vecX src1, vecX src2) %{
11374 match(Set dst (MulVB src1 src2));
11375 predicate(n->as_Vector()->length() == 16);
11376 format %{ "VMLB $dst,$src1,$src2\t// mul packed16B" %}
11377 size(6);
11378 ins_encode %{
11379 __ z_vmlb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11380 %}
11381 ins_pipe(pipe_class_dummy);
11382 %}
11383
11384 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2) %{
11385 match(Set dst (MulVS src1 src2));
11386 predicate(n->as_Vector()->length() == 8);
11387 format %{ "VMLHW $dst,$src1,$src2\t// mul packed8S" %}
11388 size(6);
11389 ins_encode %{
11390 __ z_vmlhw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11391 %}
11392 ins_pipe(pipe_class_dummy);
11393 %}
11394
11395 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
11396 match(Set dst (MulVI src1 src2));
11397 predicate(n->as_Vector()->length() == 4);
11398 format %{ "VMLF $dst,$src1,$src2\t// mul packed4I" %}
11399 size(6);
11400 ins_encode %{
11401 __ z_vmlf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11402 %}
11403 ins_pipe(pipe_class_dummy);
11404 %}
11405
11406 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
11407 match(Set dst (SubVB src1 src2));
11408 predicate(n->as_Vector()->length() == 16);
11409 format %{ "VSB $dst,$src1,$src2\t// sub packed16B" %}
11410 size(6);
11411 ins_encode %{
11412 __ z_vsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11413 %}
11414 ins_pipe(pipe_class_dummy);
11415 %}
11416
11417 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
11418 match(Set dst (SubVS src1 src2));
11419 predicate(n->as_Vector()->length() == 8);
11420 format %{ "VSH $dst,$src1,$src2\t// sub packed8S" %}
11421 size(6);
11422 ins_encode %{
11423 __ z_vsh($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11424 %}
11425 ins_pipe(pipe_class_dummy);
11426 %}
11427
11428 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
11429 match(Set dst (SubVI src1 src2));
11430 predicate(n->as_Vector()->length() == 4);
11431 format %{ "VSF $dst,$src1,$src2\t// sub packed4I" %}
11432 size(6);
11433 ins_encode %{
11434 __ z_vsf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11435 %}
11436 ins_pipe(pipe_class_dummy);
11437 %}
11438
11439 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
11440 match(Set dst (SubVL src1 src2));
11441 predicate(n->as_Vector()->length() == 2);
11442 format %{ "VSG $dst,$src1,$src2\t// sub packed2L" %}
11443 size(6);
11444 ins_encode %{
11445 __ z_vsg($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11446 %}
11447 ins_pipe(pipe_class_dummy);
11448 %}
11449
11450 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
11451 match(Set dst (AddVF src1 src2));
11452 predicate(n->as_Vector()->length() == 4);
11453 format %{ "VFASB $dst,$src1,$src2\t// add packed4F" %}
11454 size(6);
11455 ins_encode %{
11456 __ z_vfasb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11457 %}
11458 ins_pipe(pipe_class_dummy);
11459 %}
11460
11461 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
11462 match(Set dst (AddVD src1 src2));
11463 predicate(n->as_Vector()->length() == 2);
11464 format %{ "VFADB $dst,$src1,$src2\t// add packed2D" %}
11465 size(6);
11466 ins_encode %{
11467 __ z_vfadb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11468 %}
11469 ins_pipe(pipe_class_dummy);
11470 %}
11471
11472 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
11473 match(Set dst (SubVF src1 src2));
11474 predicate(n->as_Vector()->length() == 4);
11475 format %{ "VFSSB $dst,$src1,$src2\t// sub packed4F" %}
11476 size(6);
11477 ins_encode %{
11478 __ z_vfssb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11479 %}
11480 ins_pipe(pipe_class_dummy);
11481 %}
11482
11483 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
11484 match(Set dst (SubVD src1 src2));
11485 predicate(n->as_Vector()->length() == 2);
11486 format %{ "VFSDB $dst,$src1,$src2\t// sub packed2D" %}
11487 size(6);
11488 ins_encode %{
11489 __ z_vfsdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11490 %}
11491 ins_pipe(pipe_class_dummy);
11492 %}
11493
11494 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
11495 match(Set dst (MulVF src1 src2));
11496 predicate(n->as_Vector()->length() == 4);
11497 format %{ "VFMSB $dst,$src1,$src2\t// mul packed4F" %}
11498 size(6);
11499 ins_encode %{
11500 __ z_vfmsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11501 %}
11502 ins_pipe(pipe_class_dummy);
11503 %}
11504
11505 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
11506 match(Set dst (MulVD src1 src2));
11507 predicate(n->as_Vector()->length() == 2);
11508 format %{ "VFMDB $dst,$src1,$src2\t// mul packed2D" %}
11509 size(6);
11510 ins_encode %{
11511 __ z_vfmdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11512 %}
11513 ins_pipe(pipe_class_dummy);
11514 %}
11515
11516 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
11517 match(Set dst (DivVF src1 src2));
11518 predicate(n->as_Vector()->length() == 4);
11519 format %{ "VFDSB $dst,$src1,$src2\t// div packed4F" %}
11520 size(6);
11521 ins_encode %{
11522 __ z_vfdsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11523 %}
11524 ins_pipe(pipe_class_dummy);
11525 %}
11526
11527 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
11528 match(Set dst (DivVD src1 src2));
11529 predicate(n->as_Vector()->length() == 2);
11530 format %{ "VFDDB $dst,$src1,$src2\t// div packed2D" %}
11531 size(6);
11532 ins_encode %{
11533 __ z_vfddb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11534 %}
11535 ins_pipe(pipe_class_dummy);
11536 %}
11537
11538 // Vector Square Root Instructions
11539
11540 instruct vsqrt4F_reg(vecX dst, vecX src) %{
11541 match(Set dst (SqrtVF src));
11542 predicate(n->as_Vector()->length() == 4);
11543 format %{ "VFSQSB $dst,$src\t// sqrt packed4F" %}
11544 size(6);
11545 ins_encode %{
11546 __ z_vfsqsb($dst$$VectorRegister, $src$$VectorRegister);
11547 %}
11548 ins_pipe(pipe_class_dummy);
11549 %}
11550
11551 instruct vsqrt2D_reg(vecX dst, vecX src) %{
11552 match(Set dst (SqrtVD src));
11553 predicate(n->as_Vector()->length() == 2);
11554 format %{ "VFSQDB $dst,$src\t// sqrt packed2D" %}
11555 size(6);
11556 ins_encode %{
11557 __ z_vfsqdb($dst$$VectorRegister, $src$$VectorRegister);
11558 %}
11559 ins_pipe(pipe_class_dummy);
11560 %}
11561
11562 // Vector Population Count Instructions
11563
11564 instruct vpopcnt_reg(vecX dst, vecX src) %{
11565 match(Set dst (PopCountVI src));
11566 format %{ "VPOPCT $dst,$src\t// pop count packed" %}
11567 size(6);
11568 ins_encode %{
11569 BasicType bt = Matcher::vector_element_basic_type(this);
11570 switch (bt) {
11571 case T_BYTE:
11572 __ z_vpopctb($dst$$VectorRegister, $src$$VectorRegister);
11573 break;
11574 case T_SHORT:
11575 __ z_vpopcth($dst$$VectorRegister, $src$$VectorRegister);
11576 break;
11577 case T_INT:
11578 __ z_vpopctf($dst$$VectorRegister, $src$$VectorRegister);
11579 break;
11580 case T_LONG:
11581 __ z_vpopctg($dst$$VectorRegister, $src$$VectorRegister);
11582 break;
11583 default:
11584 ShouldNotReachHere();
11585 }
11586 %}
11587 ins_pipe(pipe_class_dummy);
11588 %}
11589
11590 // Vector Round Instructions
11591 instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
11592 match(Set dst (RoundDoubleModeV src rmode));
11593 predicate(n->as_Vector()->length() == 2);
11594 format %{ "RoundDoubleModeV $src,$rmode" %}
11595 size(6);
11596 ins_encode %{
11597 switch ($rmode$$constant) {
11598 case RoundDoubleModeNode::rmode_rint:
11599 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 0);
11600 break;
11601 case RoundDoubleModeNode::rmode_floor:
11602 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 7);
11603 break;
11604 case RoundDoubleModeNode::rmode_ceil:
11605 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 6);
11606 break;
11607 default:
11608 ShouldNotReachHere();
11609 }
11610 %}
11611 ins_pipe(pipe_class_dummy);
11612 %}
11613
11614 //----------POPULATION COUNT RULES--------------------------------------------
11615
11616 // Byte reverse
11617
11618 instruct bytes_reverse_short(iRegI dst, iRegI src) %{
11619 match(Set dst (ReverseBytesS src));
11620 predicate(UseByteReverseInstruction);
11621 ins_cost(2 * DEFAULT_COST);
11622 size(8);
11623
11624 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11625 "SRA $dst, 0x0010\t # right shift by 16, sign extended" %}
11626
11627 ins_encode %{
11628 __ z_lrvr($dst$$Register, $src$$Register);
11629 __ z_sra($dst$$Register, 0x0010);
11630 %}
11631 ins_pipe(pipe_class_dummy);
11632 %}
11633
11634 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
11635 match(Set dst (ReverseBytesUS src));
11636 predicate(UseByteReverseInstruction);
11637 ins_cost(2 * DEFAULT_COST);
11638 size(8);
11639
11640 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11641 "SRL $dst, 0x0010\t # right shift by 16, zero extended" %}
11642
11643 ins_encode %{
11644 __ z_lrvr($dst$$Register, $src$$Register);
11645 __ z_srl($dst$$Register, 0x0010);
11646 %}
11647 ins_pipe(pipe_class_dummy);
11648 %}
11649
11650 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
11651 match(Set dst (ReverseBytesI src));
11652 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11653 ins_cost(DEFAULT_COST);
11654 size(4);
11655 format %{ "LRVR $dst,$src\t # byte reverse int" %}
11656 opcode(LRVR_ZOPC);
11657 ins_encode(z_rreform(dst, src));
11658 ins_pipe(pipe_class_dummy);
11659 %}
11660
11661 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
11662 match(Set dst (ReverseBytesL src));
11663 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11664 ins_cost(DEFAULT_COST);
11665 // TODO: s390 port size(FIXED_SIZE);
11666 format %{ "LRVGR $dst,$src\t # byte reverse long" %}
11667 opcode(LRVGR_ZOPC);
11668 ins_encode(z_rreform(dst, src));
11669 ins_pipe(pipe_class_dummy);
11670 %}
11671
11672 // Leading zeroes
11673
11674 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
11675 // returns the bit position of the leftmost 1 in the 64bit source register.
11676 // As the bits are numbered from left to right (0..63), the returned
11677 // position index is equivalent to the number of leading zeroes.
11678 // If no 1-bit is found (i.e. the register contains zero), the instruction
11679 // returns position 64. That's exactly what we need.
11680
11681 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11682 match(Set dst (CountLeadingZerosI src));
11683 effect(KILL tmp, KILL cr);
11684 ins_cost(3 * DEFAULT_COST);
11685 size(14);
11686 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
11687 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
11688 "FLOGR $dst,$dst"
11689 %}
11690 ins_encode %{
11691 // Performance experiments indicate that "FLOGR" is using some kind of
11692 // iteration to find the leftmost "1" bit.
11693 //
11694 // The prior implementation zero-extended the 32-bit argument to 64 bit,
11695 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
11696 // We could gain measurable speedup in micro benchmark:
11697 //
11698 // leading trailing
11699 // z10: int 2.04 1.68
11700 // long 1.00 1.02
11701 // z196: int 0.99 1.23
11702 // long 1.00 1.11
11703 //
11704 // By shifting the argument into the high-word instead of zero-extending it.
11705 // The add'l branch on condition (taken for a zero argument, very infrequent,
11706 // good prediction) is well compensated for by the savings.
11707 //
11708 // We leave the previous implementation in for some time in the future when
11709 // the "FLOGR" instruction may become less iterative.
11710
11711 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
11712 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
11713 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
11714 __ z_flogr($dst$$Register, $dst$$Register);
11715 %}
11716 ins_pipe(pipe_class_dummy);
11717 %}
11718
11719 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
11720 match(Set dst (CountLeadingZerosL src));
11721 effect(KILL tmp, KILL cr);
11722 ins_cost(DEFAULT_COST);
11723 size(4);
11724 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
11725 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
11726 ins_pipe(pipe_class_dummy);
11727 %}
11728
11729 // trailing zeroes
11730
11731 // We transform the trailing zeroes problem to a leading zeroes problem
11732 // such that can use the FLOGR instruction to our advantage.
11733
11734 // With
11735 // tmp1 = src - 1
11736 // we flip all trailing zeroes to ones and the rightmost one to zero.
11737 // All other bits remain unchanged.
11738 // With the complement
11739 // tmp2 = ~src
11740 // we get all ones in the trailing zeroes positions. Thus,
11741 // tmp3 = tmp1 & tmp2
11742 // yields ones in the trailing zeroes positions and zeroes elsewhere.
11743 // Now we can apply FLOGR and get 64-(trailing zeroes).
11744 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11745 match(Set dst (CountTrailingZerosI src));
11746 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11747 ins_cost(8 * DEFAULT_COST);
11748 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11749 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
11750 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t"
11751 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11752 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t"
11753 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t"
11754 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t"
11755 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11756 "LCR $dst,$dst \t # res = -tmp4"
11757 %}
11758 ins_encode %{
11759 Register Rdst = $dst$$Register;
11760 Register Rsrc = $src$$Register;
11761 // Rtmp only needed for for zero-argument shortcut. With kill effect in
11762 // match rule Rsrc = roddReg would be possible, saving one register.
11763 Register Rtmp = $tmp$$Register;
11764
11765 assert_different_registers(Rdst, Rsrc, Rtmp);
11766
11767 // Algorithm:
11768 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
11769 // All other bits in the result are zero.
11770 // - Find the "leftmost one" bit position in the single-bit result from previous step.
11771 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
11772
11773 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
11774 Label done;
11775 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
11776 __ z_lcgfr(Rtmp, Rsrc);
11777 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
11778
11779 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
11780 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
11781 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
11782 // into upper half of reg. Not relevant with sllg below.
11783 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
11784 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
11785 // Depends on CC set by ahi above.
11786 // Taken very infrequently, good prediction, no BHT entry.
11787 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
11788 // after SLLG Rdst == 0(64bit)).
11789 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11790 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
11791 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11792 __ bind(done);
11793 %}
11794 ins_pipe(pipe_class_dummy);
11795 %}
11796
11797 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
11798 match(Set dst (CountTrailingZerosL src));
11799 effect(TEMP_DEF dst, KILL tmp, KILL cr);
11800 ins_cost(8 * DEFAULT_COST);
11801 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11802 format %{ "LCGR $dst,$src \t # preserve src\n\t"
11803 "NGR $dst,$src \t #\n\t"
11804 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11805 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t"
11806 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11807 "LCR $dst,$dst \t #"
11808 %}
11809 ins_encode %{
11810 Register Rdst = $dst$$Register;
11811 Register Rsrc = $src$$Register;
11812 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
11813
11814 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
11815 __ z_lcgr(Rdst, Rsrc);
11816 __ z_ngr(Rdst, Rsrc);
11817 __ add2reg(Rdst, -1);
11818 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11819 __ add2reg(Rdst, -64);
11820 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11821 %}
11822 ins_pipe(pipe_class_dummy);
11823 %}
11824
11825
11826 // bit count
11827
11828 instruct popCountI_Ext3(iRegI dst, iRegI src, flagsReg cr) %{
11829 match(Set dst (PopCountI src));
11830 effect(TEMP_DEF dst, KILL cr);
11831 predicate(UsePopCountInstruction &&
11832 VM_Version::has_PopCount() &&
11833 VM_Version::has_MiscInstrExt3());
11834 ins_cost(DEFAULT_COST);
11835 size(8); // popcnt + llgfr
11836 format %{ "POPCNT $dst,$src\t # pop count int" %}
11837 ins_encode %{
11838 Register Rdst = $dst$$Register;
11839 Register Rsrc = $src$$Register;
11840
11841 __ pop_count_int_with_ext3(Rdst, Rsrc);
11842
11843 %}
11844 ins_pipe(pipe_class_dummy);
11845 %}
11846
11847 instruct popCountL_Ext3(iRegI dst, iRegL src, flagsReg cr) %{
11848 match(Set dst (PopCountL src));
11849 effect(TEMP_DEF dst, KILL cr);
11850 predicate(UsePopCountInstruction &&
11851 VM_Version::has_PopCount() &&
11852 VM_Version::has_MiscInstrExt3());
11853 ins_cost(DEFAULT_COST);
11854 size(4); // popcnt
11855 format %{ "POPCNT $dst,$src\t # pop count long" %}
11856 ins_encode %{
11857 Register Rdst = $dst$$Register;
11858 Register Rsrc = $src$$Register;
11859
11860 __ pop_count_long_with_ext3(Rdst, Rsrc);
11861 %}
11862 ins_pipe(pipe_class_dummy);
11863 %}
11864
11865 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
11866 match(Set dst (PopCountI src));
11867 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11868 predicate(UsePopCountInstruction &&
11869 VM_Version::has_PopCount() &&
11870 (!VM_Version::has_MiscInstrExt3()));
11871 ins_cost(DEFAULT_COST);
11872 size(24);
11873 format %{ "POPCNT $dst,$src\t # pop count int" %}
11874 ins_encode %{
11875 Register Rdst = $dst$$Register;
11876 Register Rsrc = $src$$Register;
11877 Register Rtmp = $tmp$$Register;
11878
11879 __ pop_count_int_without_ext3(Rdst, Rsrc, Rtmp);
11880
11881 %}
11882 ins_pipe(pipe_class_dummy);
11883 %}
11884
11885 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
11886 match(Set dst (PopCountL src));
11887 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11888 predicate(UsePopCountInstruction &&
11889 VM_Version::has_PopCount() &&
11890 (!VM_Version::has_MiscInstrExt3()));
11891 ins_cost(DEFAULT_COST);
11892 size(34);
11893 format %{ "POPCNT $dst,$src\t # pop count long" %}
11894 ins_encode %{
11895 Register Rdst = $dst$$Register;
11896 Register Rsrc = $src$$Register;
11897 Register Rtmp = $tmp$$Register;
11898
11899 __ pop_count_long_without_ext3(Rdst, Rsrc, Rtmp);
11900 %}
11901 ins_pipe(pipe_class_dummy);
11902 %}
11903
11904 //----------SMARTSPILL RULES---------------------------------------------------
11905 // These must follow all instruction definitions as they use the names
11906 // defined in the instructions definitions.
11907
11908 // ============================================================================
11909 // TYPE PROFILING RULES