1 //
2 // Copyright (c) 2017, 2026, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2017, 2024 SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alignment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to continue at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // ----------------------------
101 // Integer/Long Registers
102 // ----------------------------
103
104 // z/Architecture has 16 64-bit integer registers.
105
106 // types: v = volatile, nv = non-volatile, s = system
107 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
108 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
109 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
110 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
111 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
112 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
113 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
114 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
115 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
116 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
117 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
118 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
119 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
120 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
121 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
122 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
123 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
124 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
125 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
126 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
127 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
128 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
129 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
130 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
131 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
132 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
133 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
134 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
135 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
136 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
137 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
138 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
139
140 // ----------------------------
141 // Float/Double Registers
142 // ----------------------------
143
144 // The rules of ADL require that double registers be defined in pairs.
145 // Each pair must be two 32-bit values, but not necessarily a pair of
146 // single float registers. In each pair, ADLC-assigned register numbers
147 // must be adjacent, with the lower number even. Finally, when the
148 // CPU stores such a register pair to memory, the word associated with
149 // the lower ADLC-assigned number must be stored to the lower address.
150
151 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
152 // or double precision floating-point value.
153
154 // types: v = volatile, nv = non-volatile, s = system
155 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
156 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
157 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
158 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
159 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
160 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
161 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
162 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
163 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
164 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
165 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
166 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
167 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
168 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
169 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
170 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
171 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
172 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
173 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
174 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
175 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
176 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
177 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
178 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
179 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
180 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
181 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
182 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
183 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
184 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
185 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
186 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
187
188 // ----------------------------
189 // Vector Registers
190 // ----------------------------
191 // 1st 16 VRs are aliases for the FPRs which are already defined above.
192 reg_def Z_VR0 ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
193 reg_def Z_VR0_H ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
194 reg_def Z_VR0_J ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
195 reg_def Z_VR0_K ( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
196
197 reg_def Z_VR1 ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
198 reg_def Z_VR1_H ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
199 reg_def Z_VR1_J ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
200 reg_def Z_VR1_K ( SOC, SOC, Op_RegF, 1, VMRegImpl::Bad());
201
202 reg_def Z_VR2 ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
203 reg_def Z_VR2_H ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
204 reg_def Z_VR2_J ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
205 reg_def Z_VR2_K ( SOC, SOC, Op_RegF, 2, VMRegImpl::Bad());
206
207 reg_def Z_VR3 ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
208 reg_def Z_VR3_H ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
209 reg_def Z_VR3_J ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
210 reg_def Z_VR3_K ( SOC, SOC, Op_RegF, 3, VMRegImpl::Bad());
211
212 reg_def Z_VR4 ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
213 reg_def Z_VR4_H ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
214 reg_def Z_VR4_J ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
215 reg_def Z_VR4_K ( SOC, SOC, Op_RegF, 4, VMRegImpl::Bad());
216
217 reg_def Z_VR5 ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
218 reg_def Z_VR5_H ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
219 reg_def Z_VR5_J ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
220 reg_def Z_VR5_K ( SOC, SOC, Op_RegF, 5, VMRegImpl::Bad());
221
222 reg_def Z_VR6 ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
223 reg_def Z_VR6_H ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
224 reg_def Z_VR6_J ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
225 reg_def Z_VR6_K ( SOC, SOC, Op_RegF, 6, VMRegImpl::Bad());
226
227 reg_def Z_VR7 ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
228 reg_def Z_VR7_H ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
229 reg_def Z_VR7_J ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
230 reg_def Z_VR7_K ( SOC, SOC, Op_RegF, 7, VMRegImpl::Bad());
231
232 reg_def Z_VR8 ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
233 reg_def Z_VR8_H ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
234 reg_def Z_VR8_J ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
235 reg_def Z_VR8_K ( SOC, SOC, Op_RegF, 8, VMRegImpl::Bad());
236
237 reg_def Z_VR9 ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
238 reg_def Z_VR9_H ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
239 reg_def Z_VR9_J ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
240 reg_def Z_VR9_K ( SOC, SOC, Op_RegF, 9, VMRegImpl::Bad());
241
242 reg_def Z_VR10 ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
243 reg_def Z_VR10_H ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
244 reg_def Z_VR10_J ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
245 reg_def Z_VR10_K ( SOC, SOC, Op_RegF, 10, VMRegImpl::Bad());
246
247 reg_def Z_VR11 ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
248 reg_def Z_VR11_H ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
249 reg_def Z_VR11_J ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
250 reg_def Z_VR11_K ( SOC, SOC, Op_RegF, 11, VMRegImpl::Bad());
251
252 reg_def Z_VR12 ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
253 reg_def Z_VR12_H ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
254 reg_def Z_VR12_J ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
255 reg_def Z_VR12_K ( SOC, SOC, Op_RegF, 12, VMRegImpl::Bad());
256
257 reg_def Z_VR13 ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
258 reg_def Z_VR13_H ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
259 reg_def Z_VR13_J ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
260 reg_def Z_VR13_K ( SOC, SOC, Op_RegF, 13, VMRegImpl::Bad());
261
262 reg_def Z_VR14 ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
263 reg_def Z_VR14_H ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
264 reg_def Z_VR14_J ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
265 reg_def Z_VR14_K ( SOC, SOC, Op_RegF, 14, VMRegImpl::Bad());
266
267 reg_def Z_VR15 ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
268 reg_def Z_VR15_H ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
269 reg_def Z_VR15_J ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
270 reg_def Z_VR15_K ( SOC, SOC, Op_RegF, 15, VMRegImpl::Bad());
271
272 reg_def Z_VR16 ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg() );
273 reg_def Z_VR16_H ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next() );
274 reg_def Z_VR16_J ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(2) );
275 reg_def Z_VR16_K ( SOC, SOC, Op_RegF, 16, Z_V16->as_VMReg()->next(3) );
276
277 reg_def Z_VR17 ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg() );
278 reg_def Z_VR17_H ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next() );
279 reg_def Z_VR17_J ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(2) );
280 reg_def Z_VR17_K ( SOC, SOC, Op_RegF, 17, Z_V17->as_VMReg()->next(3) );
281
282 reg_def Z_VR18 ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg() );
283 reg_def Z_VR18_H ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next() );
284 reg_def Z_VR18_J ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(2) );
285 reg_def Z_VR18_K ( SOC, SOC, Op_RegF, 18, Z_V18->as_VMReg()->next(3) );
286
287 reg_def Z_VR19 ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg() );
288 reg_def Z_VR19_H ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next() );
289 reg_def Z_VR19_J ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(2) );
290 reg_def Z_VR19_K ( SOC, SOC, Op_RegF, 19, Z_V19->as_VMReg()->next(3) );
291
292 reg_def Z_VR20 ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg() );
293 reg_def Z_VR20_H ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next() );
294 reg_def Z_VR20_J ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(2) );
295 reg_def Z_VR20_K ( SOC, SOC, Op_RegF, 20, Z_V20->as_VMReg()->next(3) );
296
297 reg_def Z_VR21 ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg() );
298 reg_def Z_VR21_H ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next() );
299 reg_def Z_VR21_J ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(2) );
300 reg_def Z_VR21_K ( SOC, SOC, Op_RegF, 21, Z_V21->as_VMReg()->next(3) );
301
302 reg_def Z_VR22 ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg() );
303 reg_def Z_VR22_H ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next() );
304 reg_def Z_VR22_J ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(2) );
305 reg_def Z_VR22_K ( SOC, SOC, Op_RegF, 22, Z_V22->as_VMReg()->next(3) );
306
307 reg_def Z_VR23 ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg() );
308 reg_def Z_VR23_H ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next() );
309 reg_def Z_VR23_J ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(2) );
310 reg_def Z_VR23_K ( SOC, SOC, Op_RegF, 23, Z_V23->as_VMReg()->next(3) );
311
312 reg_def Z_VR24 ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg() );
313 reg_def Z_VR24_H ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next() );
314 reg_def Z_VR24_J ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(2) );
315 reg_def Z_VR24_K ( SOC, SOC, Op_RegF, 24, Z_V24->as_VMReg()->next(3) );
316
317 reg_def Z_VR25 ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg() );
318 reg_def Z_VR25_H ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next() );
319 reg_def Z_VR25_J ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(2) );
320 reg_def Z_VR25_K ( SOC, SOC, Op_RegF, 25, Z_V25->as_VMReg()->next(3) );
321
322 reg_def Z_VR26 ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg() );
323 reg_def Z_VR26_H ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next() );
324 reg_def Z_VR26_J ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(2) );
325 reg_def Z_VR26_K ( SOC, SOC, Op_RegF, 26, Z_V26->as_VMReg()->next(3) );
326
327 reg_def Z_VR27 ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg() );
328 reg_def Z_VR27_H ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next() );
329 reg_def Z_VR27_J ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(2) );
330 reg_def Z_VR27_K ( SOC, SOC, Op_RegF, 27, Z_V27->as_VMReg()->next(3) );
331
332 reg_def Z_VR28 ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg() );
333 reg_def Z_VR28_H ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next() );
334 reg_def Z_VR28_J ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(2) );
335 reg_def Z_VR28_K ( SOC, SOC, Op_RegF, 28, Z_V28->as_VMReg()->next(3) );
336
337 reg_def Z_VR29 ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg() );
338 reg_def Z_VR29_H ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next() );
339 reg_def Z_VR29_J ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(2) );
340 reg_def Z_VR29_K ( SOC, SOC, Op_RegF, 29, Z_V29->as_VMReg()->next(3) );
341
342 reg_def Z_VR30 ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg() );
343 reg_def Z_VR30_H ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next() );
344 reg_def Z_VR30_J ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(2) );
345 reg_def Z_VR30_K ( SOC, SOC, Op_RegF, 30, Z_V30->as_VMReg()->next(3) );
346
347 reg_def Z_VR31 ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg() );
348 reg_def Z_VR31_H ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next() );
349 reg_def Z_VR31_J ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(2) );
350 reg_def Z_VR31_K ( SOC, SOC, Op_RegF, 31, Z_V31->as_VMReg()->next(3) );
351 // Special Registers
352
353 // Condition Codes Flag Registers
354
355 // z/Architecture has the PSW (program status word) that contains
356 // (among other information) the condition code. We treat this
357 // part of the PSW as a condition register CR. It consists of 4
358 // bits. Floating point instructions influence the same condition register CR.
359
360 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
361
362 // Specify priority of register selection within phases of register
363 // allocation. Highest priority is first. A useful heuristic is to
364 // give registers a low priority when they are required by machine
365 // instructions, and choose no-save registers before save-on-call, and
366 // save-on-call before save-on-entry. Registers which participate in
367 // fix calling sequences should come last. Registers which are used
368 // as pairs must fall on an even boundary.
369
370 // It's worth about 1% on SPEC geomean to get this right.
371
372 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
373 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
374 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
375 // the same as Z_R3->encoding()! Furthermore, we cannot make any
376 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
377 // Additionally, the function
378 // static enum RC rc_class(OptoReg::Name reg)
379 // maps a given <register>_num value to its chunk type (except for flags)
380 // and its current implementation relies on chunk0 and chunk1 having a
381 // size of 64 each.
382
383 alloc_class chunk0(
384 // chunk0 contains *all* 32 integer registers halves.
385
386 // potential SOE regs
387 Z_R13,Z_R13_H,
388 Z_R12,Z_R12_H,
389 Z_R11,Z_R11_H,
390 Z_R10,Z_R10_H,
391
392 Z_R9,Z_R9_H,
393 Z_R8,Z_R8_H,
394 Z_R7,Z_R7_H,
395
396 Z_R1,Z_R1_H,
397 Z_R0,Z_R0_H,
398
399 // argument registers
400 Z_R6,Z_R6_H,
401 Z_R5,Z_R5_H,
402 Z_R4,Z_R4_H,
403 Z_R3,Z_R3_H,
404 Z_R2,Z_R2_H,
405
406 // special registers
407 Z_R14,Z_R14_H,
408 Z_R15,Z_R15_H
409 );
410
411 alloc_class chunk1(
412 // Chunk1 contains *all* 64 floating-point registers halves.
413
414 Z_F15,Z_F15_H,
415 Z_F14,Z_F14_H,
416 Z_F13,Z_F13_H,
417 Z_F12,Z_F12_H,
418 Z_F11,Z_F11_H,
419 Z_F10,Z_F10_H,
420 Z_F9,Z_F9_H,
421 Z_F8,Z_F8_H,
422 // scratch register
423 Z_F7,Z_F7_H,
424 Z_F5,Z_F5_H,
425 Z_F3,Z_F3_H,
426 Z_F1,Z_F1_H,
427 // argument registers
428 Z_F6,Z_F6_H,
429 Z_F4,Z_F4_H,
430 Z_F2,Z_F2_H,
431 Z_F0,Z_F0_H
432 );
433
434 alloc_class chunk2(
435 Z_VR0, Z_VR0_H, Z_VR0_J, Z_VR0_K,
436 Z_VR1, Z_VR1_H, Z_VR1_J, Z_VR1_K,
437 Z_VR2, Z_VR2_H, Z_VR2_J, Z_VR2_K,
438 Z_VR3, Z_VR3_H, Z_VR3_J, Z_VR3_K,
439 Z_VR4, Z_VR4_H, Z_VR4_J, Z_VR4_K,
440 Z_VR5, Z_VR5_H, Z_VR5_J, Z_VR5_K,
441 Z_VR6, Z_VR6_H, Z_VR6_J, Z_VR6_K,
442 Z_VR7, Z_VR7_H, Z_VR7_J, Z_VR7_K,
443 Z_VR8, Z_VR8_H, Z_VR8_J, Z_VR8_K,
444 Z_VR9, Z_VR9_H, Z_VR9_J, Z_VR9_K,
445 Z_VR10, Z_VR10_H, Z_VR10_J, Z_VR10_K,
446 Z_VR11, Z_VR11_H, Z_VR11_J, Z_VR11_K,
447 Z_VR12, Z_VR12_H, Z_VR12_J, Z_VR12_K,
448 Z_VR13, Z_VR13_H, Z_VR13_J, Z_VR13_K,
449 Z_VR14, Z_VR14_H, Z_VR14_J, Z_VR14_K,
450 Z_VR15, Z_VR15_H, Z_VR15_J, Z_VR15_K,
451 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
452 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
453 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
454 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
455 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
456 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
457 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
458 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
459 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
460 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
461 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
462 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
463 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
464 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
465 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
466 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
467 );
468
469 alloc_class chunk3(
470 Z_CR
471 );
472
473
474 //-------Architecture Description Register Classes-----------------------
475
476 // Several register classes are automatically defined based upon
477 // information in this architecture description.
478
479 // 1) reg_class inline_cache_reg (as defined in frame section)
480 // 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
481
482 // Integer Register Classes
483 reg_class z_int_reg(
484 /*Z_R0*/ // R0
485 /*Z_R1*/
486 Z_R2,
487 Z_R3,
488 Z_R4,
489 Z_R5,
490 Z_R6,
491 Z_R7,
492 /*Z_R8,*/ // Z_thread
493 Z_R9,
494 Z_R10,
495 Z_R11,
496 Z_R12,
497 Z_R13
498 /*Z_R14*/ // return_pc
499 /*Z_R15*/ // SP
500 );
501
502 reg_class z_no_odd_int_reg(
503 /*Z_R0*/ // R0
504 /*Z_R1*/
505 Z_R2,
506 Z_R3,
507 Z_R4,
508 /*Z_R5,*/ // odd part of fix register pair
509 Z_R6,
510 Z_R7,
511 /*Z_R8,*/ // Z_thread
512 Z_R9,
513 Z_R10,
514 Z_R11,
515 Z_R12,
516 Z_R13
517 /*Z_R14*/ // return_pc
518 /*Z_R15*/ // SP
519 );
520
521 reg_class z_no_arg_int_reg(
522 /*Z_R0*/ // R0
523 /*Z_R1*/ // scratch
524 /*Z_R2*/
525 /*Z_R3*/
526 /*Z_R4*/
527 /*Z_R5*/
528 /*Z_R6*/
529 Z_R7,
530 /*Z_R8*/ // Z_thread
531 Z_R9,
532 Z_R10,
533 Z_R11,
534 Z_R12,
535 Z_R13
536 /*Z_R14*/ // return_pc
537 /*Z_R15*/ // SP
538 );
539
540 reg_class z_rarg1_int_reg(Z_R2);
541 reg_class z_rarg2_int_reg(Z_R3);
542 reg_class z_rarg3_int_reg(Z_R4);
543 reg_class z_rarg4_int_reg(Z_R5);
544 reg_class z_rarg5_int_reg(Z_R6);
545
546 // Pointer Register Classes
547
548 // 64-bit build means 64-bit pointers means hi/lo pairs.
549
550 reg_class z_rarg5_ptrN_reg(Z_R6);
551
552 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
553 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
554 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
555 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
556 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
557 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
558 reg_class z_r10_ptr_reg(Z_R10_H, Z_R10);
559 reg_class z_r11_ptr_reg(Z_R11_H, Z_R11);
560
561 reg_class z_ptr_reg(
562 /*Z_R0_H,Z_R0*/ // R0
563 /*Z_R1_H,Z_R1*/
564 Z_R2_H,Z_R2,
565 Z_R3_H,Z_R3,
566 Z_R4_H,Z_R4,
567 Z_R5_H,Z_R5,
568 Z_R6_H,Z_R6,
569 Z_R7_H,Z_R7,
570 /*Z_R8_H,Z_R8,*/ // Z_thread
571 Z_R9_H,Z_R9,
572 Z_R10_H,Z_R10,
573 Z_R11_H,Z_R11,
574 Z_R12_H,Z_R12,
575 Z_R13_H,Z_R13
576 /*Z_R14_H,Z_R14*/ // return_pc
577 /*Z_R15_H,Z_R15*/ // SP
578 );
579
580 reg_class z_lock_ptr_reg(
581 /*Z_R0_H,Z_R0*/ // R0
582 /*Z_R1_H,Z_R1*/
583 Z_R2_H,Z_R2,
584 Z_R3_H,Z_R3,
585 Z_R4_H,Z_R4,
586 /*Z_R5_H,Z_R5,*/
587 /*Z_R6_H,Z_R6,*/
588 Z_R7_H,Z_R7,
589 /*Z_R8_H,Z_R8,*/ // Z_thread
590 Z_R9_H,Z_R9,
591 Z_R10_H,Z_R10,
592 Z_R11_H,Z_R11,
593 Z_R12_H,Z_R12,
594 Z_R13_H,Z_R13
595 /*Z_R14_H,Z_R14*/ // return_pc
596 /*Z_R15_H,Z_R15*/ // SP
597 );
598
599 reg_class z_no_arg_ptr_reg(
600 /*Z_R0_H,Z_R0*/ // R0
601 /*Z_R1_H,Z_R1*/ // scratch
602 /*Z_R2_H,Z_R2*/
603 /*Z_R3_H,Z_R3*/
604 /*Z_R4_H,Z_R4*/
605 /*Z_R5_H,Z_R5*/
606 /*Z_R6_H,Z_R6*/
607 Z_R7_H, Z_R7,
608 /*Z_R8_H,Z_R8*/ // Z_thread
609 Z_R9_H,Z_R9,
610 Z_R10_H,Z_R10,
611 Z_R11_H,Z_R11,
612 Z_R12_H,Z_R12,
613 Z_R13_H,Z_R13
614 /*Z_R14_H,Z_R14*/ // return_pc
615 /*Z_R15_H,Z_R15*/ // SP
616 );
617
618 // Special class for storeP instructions, which can store SP or RPC to
619 // TLS. (Note: Do not generalize this to "any_reg". If you add
620 // another register, such as FP, to this mask, the allocator may try
621 // to put a temp in it.)
622 // Register class for memory access base registers,
623 // This class is a superset of z_ptr_reg including Z_thread.
624 reg_class z_memory_ptr_reg(
625 /*Z_R0_H,Z_R0*/ // R0
626 /*Z_R1_H,Z_R1*/
627 Z_R2_H,Z_R2,
628 Z_R3_H,Z_R3,
629 Z_R4_H,Z_R4,
630 Z_R5_H,Z_R5,
631 Z_R6_H,Z_R6,
632 Z_R7_H,Z_R7,
633 Z_R8_H,Z_R8, // Z_thread
634 Z_R9_H,Z_R9,
635 Z_R10_H,Z_R10,
636 Z_R11_H,Z_R11,
637 Z_R12_H,Z_R12,
638 Z_R13_H,Z_R13
639 /*Z_R14_H,Z_R14*/ // return_pc
640 /*Z_R15_H,Z_R15*/ // SP
641 );
642
643 // Other special pointer regs.
644 reg_class z_r1_regP(Z_R1_H,Z_R1);
645 reg_class z_r9_regP(Z_R9_H,Z_R9);
646
647
648 // Long Register Classes
649
650 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
651 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
652 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
653 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
654 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
655
656 // Longs in 1 register. Aligned adjacent hi/lo pairs.
657 reg_class z_long_reg(
658 /*Z_R0_H,Z_R0*/ // R0
659 /*Z_R1_H,Z_R1*/
660 Z_R2_H,Z_R2,
661 Z_R3_H,Z_R3,
662 Z_R4_H,Z_R4,
663 Z_R5_H,Z_R5,
664 Z_R6_H,Z_R6,
665 Z_R7_H,Z_R7,
666 /*Z_R8_H,Z_R8,*/ // Z_thread
667 Z_R9_H,Z_R9,
668 Z_R10_H,Z_R10,
669 Z_R11_H,Z_R11,
670 Z_R12_H,Z_R12,
671 Z_R13_H,Z_R13
672 /*Z_R14_H,Z_R14,*/ // return_pc
673 /*Z_R15_H,Z_R15*/ // SP
674 );
675
676 // z_long_reg without even registers
677 reg_class z_long_odd_reg(
678 /*Z_R0_H,Z_R0*/ // R0
679 /*Z_R1_H,Z_R1*/
680 Z_R3_H,Z_R3,
681 Z_R5_H,Z_R5,
682 Z_R7_H,Z_R7,
683 Z_R9_H,Z_R9,
684 Z_R11_H,Z_R11,
685 Z_R13_H,Z_R13
686 /*Z_R14_H,Z_R14,*/ // return_pc
687 /*Z_R15_H,Z_R15*/ // SP
688 );
689
690 // Special Class for Condition Code Flags Register
691
692 reg_class z_condition_reg(
693 Z_CR
694 );
695
696 // Scratch register for late profiling. Callee saved.
697 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
698
699
700 // Float Register Classes
701
702 reg_class z_flt_reg(
703 Z_F0,
704 /*Z_F1,*/ // scratch
705 Z_F2,
706 Z_F3,
707 Z_F4,
708 Z_F5,
709 Z_F6,
710 Z_F7,
711 Z_F8,
712 Z_F9,
713 Z_F10,
714 Z_F11,
715 Z_F12,
716 Z_F13,
717 Z_F14,
718 Z_F15
719 );
720 reg_class z_rscratch1_flt_reg(Z_F1);
721
722 // Double precision float registers have virtual `high halves' that
723 // are needed by the allocator.
724 reg_class z_dbl_reg(
725 Z_F0,Z_F0_H,
726 /*Z_F1,Z_F1_H,*/ // scratch
727 Z_F2,Z_F2_H,
728 Z_F3,Z_F3_H,
729 Z_F4,Z_F4_H,
730 Z_F5,Z_F5_H,
731 Z_F6,Z_F6_H,
732 Z_F7,Z_F7_H,
733 Z_F8,Z_F8_H,
734 Z_F9,Z_F9_H,
735 Z_F10,Z_F10_H,
736 Z_F11,Z_F11_H,
737 Z_F12,Z_F12_H,
738 Z_F13,Z_F13_H,
739 Z_F14,Z_F14_H,
740 Z_F15,Z_F15_H
741 );
742 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
743
744 reg_class z_v_reg(
745 // Attention: Only these ones are saved & restored at safepoint by RegisterSaver.
746 //1st 16 VRs overlaps with 1st 16 FPRs.
747 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K,
748 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K,
749 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K,
750 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K,
751 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K,
752 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K,
753 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K,
754 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K,
755 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K,
756 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K,
757 Z_VR26, Z_VR26_H, Z_VR26_J, Z_VR26_K,
758 Z_VR27, Z_VR27_H, Z_VR27_J, Z_VR27_K,
759 Z_VR28, Z_VR28_H, Z_VR28_J, Z_VR28_K,
760 Z_VR29, Z_VR29_H, Z_VR29_J, Z_VR29_K,
761 Z_VR30, Z_VR30_H, Z_VR30_J, Z_VR30_K,
762 Z_VR31, Z_VR31_H, Z_VR31_J, Z_VR31_K
763 );
764
765 // class for vector register v16
766 reg_class z_vreg_16(
767 Z_VR16, Z_VR16_H, Z_VR16_J, Z_VR16_K
768 );
769
770 // class for vector register v17
771 reg_class z_vreg_17(
772 Z_VR17, Z_VR17_H, Z_VR17_J, Z_VR17_K
773 );
774
775 // class for vector register v18
776 reg_class z_vreg_18(
777 Z_VR18, Z_VR18_H, Z_VR18_J, Z_VR18_K
778 );
779
780 // class for vector register v19
781 reg_class z_vreg_19(
782 Z_VR19, Z_VR19_H, Z_VR19_J, Z_VR19_K
783 );
784
785 // class for vector register v20
786 reg_class z_vreg_20(
787 Z_VR20, Z_VR20_H, Z_VR20_J, Z_VR20_K
788 );
789
790 // class for vector register v21
791 reg_class z_vreg_21(
792 Z_VR21, Z_VR21_H, Z_VR21_J, Z_VR21_K
793 );
794
795 // class for vector register v22
796 reg_class z_vreg_22(
797 Z_VR22, Z_VR22_H, Z_VR22_J, Z_VR22_K
798 );
799
800 // class for vector register v23
801 reg_class z_vreg_23(
802 Z_VR23, Z_VR23_H, Z_VR23_J, Z_VR23_K
803 );
804
805 // class for vector register v24
806 reg_class z_vreg_24(
807 Z_VR24, Z_VR24_H, Z_VR24_J, Z_VR24_K
808 );
809
810 // class for vector register v25
811 reg_class z_vreg_25(
812 Z_VR25, Z_VR25_H, Z_VR25_J, Z_VR25_K
813 );
814
815 %}
816
817 //----------DEFINITION BLOCK---------------------------------------------------
818 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
819 // Current support includes integer values in the range [0, 0x7FFFFFFF].
820 // Format:
821 // int_def <name> (<int_value>, <expression>);
822 // Generated Code in ad_<arch>.hpp
823 // #define <name> (<expression>)
824 // // value == <int_value>
825 // Generated code in ad_<arch>.cpp adlc_verification()
826 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
827 //
828 definitions %{
829 // The default cost (of an ALU instruction).
830 int_def DEFAULT_COST ( 100, 100);
831 int_def DEFAULT_COST_LOW ( 80, 80);
832 int_def DEFAULT_COST_HIGH ( 120, 120);
833 int_def HUGE_COST (1000000, 1000000);
834
835 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
836 int_def ALU_REG_COST ( 100, DEFAULT_COST);
837 int_def ALU_MEMORY_COST ( 150, 150);
838
839 // Memory refs are twice as expensive as run-of-the-mill.
840 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
841 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
842 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
843
844 // Branches are even more expensive.
845 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
846 int_def CALL_COST ( 300, DEFAULT_COST * 3);
847 %}
848
849 source %{
850
851 #ifdef PRODUCT
852 #define BLOCK_COMMENT(str)
853 #define BIND(label) __ bind(label)
854 #else
855 #define BLOCK_COMMENT(str) __ block_comment(str)
856 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
857 #endif
858
859 #define __ masm->
860
861 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
862 #define Z_DISP3_SIZE 6
863
864 // Tertiary op of a LoadP or StoreP encoding.
865 #define REGP_OP true
866
867 // Given a register encoding, produce an Integer Register object.
868 static Register reg_to_register_object(int register_encoding);
869
870 // ****************************************************************************
871
872 // REQUIRED FUNCTIONALITY
873
874 // !!!!! Special hack to get all type of calls to specify the byte offset
875 // from the start of the call to the point where the return address
876 // will point.
877
878 void PhaseOutput::pd_perform_mach_node_analysis() {
879 }
880
881 int MachNode::pd_alignment_required() const {
882 return 1;
883 }
884
885 int MachNode::compute_padding(int current_offset) const {
886 return 0;
887 }
888
889 int MachCallStaticJavaNode::ret_addr_offset() const {
890 if (_method) {
891 return MacroAssembler::call_far_pcrelative_size();
892 } else {
893 return MacroAssembler::call_far_patchable_ret_addr_offset();
894 }
895 }
896
897 int MachCallDynamicJavaNode::ret_addr_offset() const {
898 // Consider size of receiver type profiling (C2 tiers).
899
900 int vtable_index = this->_vtable_index;
901 if (vtable_index == -4) {
902 return MacroAssembler::load_const_from_toc_size()
903 + MacroAssembler::call_far_pcrelative_size();
904 } else {
905 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
906 // This should return the size of instructions in vtable dispatch
907 // branch of z_enc_java_dynamic_call
908 int offset = 0;
909
910 // __ load_klass(Z_method, Z_R2);
911 if (UseCompactObjectHeaders) {
912 // load_narrow_klass_compact (z_lg z_srlg)
913 offset += 6 // z_lg
914 + 6; // z_srlg;
915 } else {
916 offset += 6; // z_llgf
917 }
918 offset += MacroAssembler::instr_size_for_decode_klass_not_null();
919
920 // check if displacement is valid, as it will generate different
921 // instructions:
922 int entry_offset = in_bytes(Klass::vtable_start_offset()) +
923 vtable_index * vtableEntry::size_in_bytes();
924 int v_off = entry_offset + in_bytes(vtableEntry::method_offset());
925 if (!Displacement::is_validDisp(v_off)) {
926 offset += MacroAssembler::load_const_size(); // emits iihf + iilf
927 }
928 // both generate z_lg
929 offset += 6; // z_lg (z_method, v_off | Address(Z_method, Z_R1_scratch))
930 // common footer
931 offset += 6; // z_lg(Z_R1_scratch, Method::from_compiled_offset())
932 offset += 2; // z_basr
933
934 return offset;
935 }
936 }
937
938 int MachCallRuntimeNode::ret_addr_offset() const {
939 return 6 // get_PC() (LARL)
940 + 6 // save_return_pc() (STG)
941 + MacroAssembler::call_far_patchable_ret_addr_offset();
942 }
943
944 // Compute padding required for nodes which need alignment
945 //
946 // The addresses of the call instructions needs to be 4-byte aligned to
947 // ensure that they don't span a cache line so that they are atomically patchable.
948 // The actual calls get emitted at different offsets within the node emitters.
949 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
950
951 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
952 return (0 - current_offset) & 2;
953 }
954
955 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
956 return (6 - current_offset) & 2;
957 }
958
959 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
960 return (12 - current_offset) & 2;
961 }
962
963 int CallLeafDirectNode::compute_padding(int current_offset) const {
964 return (12 - current_offset) & 2;
965 }
966
967 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
968 return (12 - current_offset) & 2;
969 }
970
971 void emit_nop(C2_MacroAssembler *masm) {
972 __ z_nop();
973 }
974
975 // Emit an interrupt that is caught by the debugger (for debugging compiler).
976 void emit_break(C2_MacroAssembler *masm) {
977 __ z_illtrap();
978 }
979
980 #if !defined(PRODUCT)
981 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
982 os->print("TA");
983 }
984 #endif
985
986 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
987 emit_break(masm);
988 }
989
990 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
991 return MachNode::size(ra_);
992 }
993
994 static inline void z_emit16(C2_MacroAssembler *masm, long value) {
995 __ emit_instruction((unsigned long)value, 2);
996 }
997
998 static inline void z_emit32(C2_MacroAssembler *masm, long value) {
999 __ emit_instruction((unsigned long)value, 4);
1000 }
1001
1002 static inline void z_emit48(C2_MacroAssembler *masm, long value) {
1003 __ emit_instruction((unsigned long)value, 6);
1004 }
1005
1006 static inline unsigned int z_emit_inst(C2_MacroAssembler *masm, long value) {
1007 if (value < 0) {
1008 // There obviously has been an unintended sign extension (int->long). Revert it.
1009 value = (long)((unsigned long)((unsigned int)value));
1010 }
1011
1012 int len = __ emit_instruction((unsigned long)value, 0);
1013 return len;
1014 }
1015
1016 // Check effective address (at runtime) for required alignment.
1017 static inline void z_assert_aligned(C2_MacroAssembler *masm, int disp, Register index, Register base, int alignment) {
1018 __ z_lay(Z_R0, disp, index, base);
1019 __ z_nill(Z_R0, alignment-1);
1020 __ z_brc(Assembler::bcondEqual, +3);
1021 __ z_illtrap();
1022 }
1023
1024 int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, relocInfo::relocType rtype,
1025 PhaseRegAlloc* ra_, bool is_native_call = false) {
1026 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
1027 unsigned int start_off = __ offset();
1028
1029 if (is_native_call) {
1030 ShouldNotReachHere();
1031 }
1032
1033 if (rtype == relocInfo::runtime_call_w_cp_type) {
1034 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
1035 address call_addr = __ call_c_opt((address)entry_point);
1036 if (call_addr == nullptr) {
1037 Compile::current()->env()->record_out_of_memory_failure();
1038 return -1;
1039 }
1040 } else {
1041 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
1042 rtype == relocInfo::static_call_type, "unexpected rtype");
1043 __ relocate(rtype);
1044 // BRASL must be prepended with a nop to identify it in the instruction stream.
1045 __ z_nop();
1046 __ z_brasl(Z_R14, (address)entry_point);
1047 }
1048
1049 unsigned int ret_off = __ offset();
1050
1051 return (ret_off - start_off);
1052 }
1053
1054 static int emit_call_reloc(C2_MacroAssembler *masm, intptr_t entry_point, RelocationHolder const& rspec) {
1055 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
1056 unsigned int start_off = __ offset();
1057
1058 relocInfo::relocType rtype = rspec.type();
1059 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
1060 "unexpected rtype");
1061
1062 __ relocate(rspec);
1063 __ z_nop();
1064 __ z_brasl(Z_R14, (address)entry_point);
1065
1066 unsigned int ret_off = __ offset();
1067
1068 return (ret_off - start_off);
1069 }
1070
1071 //=============================================================================
1072
1073 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
1074 int ConstantTable::calculate_table_base_offset() const {
1075 return 0; // absolute addressing, no offset
1076 }
1077
1078 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1079 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1080 ShouldNotReachHere();
1081 }
1082
1083 // Even with PC-relative TOC addressing, we still need this node.
1084 // Float loads/stores do not support PC-relative addresses.
1085 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1086 Register Rtoc = as_Register(ra_->get_encode(this));
1087 __ load_toc(Rtoc);
1088 }
1089
1090 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1091 // PCrelative TOC access.
1092 return 6; // sizeof(LARL)
1093 }
1094
1095 #if !defined(PRODUCT)
1096 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1097 Register r = as_Register(ra_->get_encode(this));
1098 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
1099 }
1100 #endif
1101
1102 //=============================================================================
1103
1104 #include "gc/shared/barrierSetAssembler.hpp"
1105
1106 #if !defined(PRODUCT)
1107 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1108 Compile* C = ra_->C;
1109 st->print_cr("--- MachPrologNode ---");
1110 st->print("\t");
1111 for (int i = 0; i < OptoPrologueNops; i++) {
1112 st->print_cr("NOP"); st->print("\t");
1113 }
1114
1115 long framesize = C->output()->frame_size_in_bytes();
1116 int bangsize = C->output()->bang_size_in_bytes();
1117
1118 // Calls to C2R adapters often do not accept exceptional returns.
1119 // We require that their callers must bang for them. But be
1120 // careful, because some VM calls (such as call site linkage) can
1121 // use several kilobytes of stack. But the stack safety zone should
1122 // account for that. See bugs 4446381, 4468289, 4497237.
1123 if (C->output()->need_stack_bang(bangsize)) {
1124 st->print_cr("# stack bang"); st->print("\t");
1125 }
1126 st->print_cr("push_frame %d", (int)-framesize);
1127 st->print("\t");
1128
1129 if (C->stub_function() == nullptr) {
1130 st->print("nmethod entry barrier\n\t");
1131 }
1132 }
1133 #endif
1134
1135 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1136 Compile* C = ra_->C;
1137
1138 size_t framesize = C->output()->frame_size_in_bytes();
1139 size_t bangsize = C->output()->bang_size_in_bytes();
1140
1141 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
1142
1143 if (C->clinit_barrier_on_entry()) {
1144 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1145
1146 Label L_skip_barrier;
1147 Register klass = Z_R1_scratch;
1148
1149 // Notify OOP recorder (don't need the relocation)
1150 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
1151 __ load_const_optimized(klass, md.value());
1152 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
1153
1154 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
1155 __ z_br(klass);
1156
1157 __ bind(L_skip_barrier);
1158 }
1159
1160 // Calls to C2R adapters often do not accept exceptional returns.
1161 // We require that their callers must bang for them. But be
1162 // careful, because some VM calls (such as call site linkage) can
1163 // use several kilobytes of stack. But the stack safety zone should
1164 // account for that. See bugs 4446381, 4468289, 4497237.
1165 if (C->output()->need_stack_bang(bangsize)) {
1166 __ generate_stack_overflow_check(bangsize);
1167 }
1168
1169 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
1170 __ save_return_pc();
1171
1172 // The z/Architecture abi is already accounted for in `framesize' via the
1173 // 'out_preserve_stack_slots' declaration.
1174 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
1175
1176 if (C->has_mach_constant_base_node()) {
1177 // NOTE: We set the table base offset here because users might be
1178 // emitted before MachConstantBaseNode.
1179 ConstantTable& constant_table = C->output()->constant_table();
1180 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1181 }
1182
1183 if (C->stub_function() == nullptr) {
1184 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1185 bs->nmethod_entry_barrier(masm);
1186 }
1187
1188 C->output()->set_frame_complete(__ offset());
1189 }
1190 int MachPrologNode::reloc() const {
1191 // Return number of relocatable values contained in this instruction.
1192 return 1; // One reloc entry for load_const(toc).
1193 }
1194
1195 //=============================================================================
1196
1197 #if !defined(PRODUCT)
1198 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1199 os->print_cr("epilog");
1200 os->print("\t");
1201 if (do_polling() && ra_->C->is_method_compilation()) {
1202 os->print_cr("load_from_polling_page Z_R1_scratch");
1203 os->print("\t");
1204 }
1205 }
1206 #endif
1207
1208 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1209 Compile* C = ra_->C;
1210
1211 // If this does safepoint polling, then do it here.
1212 bool need_polling = do_polling() && C->is_method_compilation();
1213
1214 // Pop frame, restore return_pc, and all stuff needed by interpreter.
1215 int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
1216 __ pop_frame_restore_retPC(frame_size_in_bytes);
1217
1218 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1219 __ reserved_stack_check(Z_R14);
1220 }
1221
1222 // Touch the polling page.
1223 if (need_polling) {
1224 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
1225 // We need to mark the code position where the load from the safepoint
1226 // polling page was emitted as relocInfo::poll_return_type here.
1227 __ relocate(relocInfo::poll_return_type);
1228 __ load_from_polling_page(Z_R1_scratch);
1229 }
1230 }
1231
1232 int MachEpilogNode::reloc() const {
1233 // Return number of relocatable values contained in this instruction.
1234 return 1; // One for load_from_polling_page.
1235 }
1236
1237 const Pipeline * MachEpilogNode::pipeline() const {
1238 return MachNode::pipeline_class();
1239 }
1240
1241 //=============================================================================
1242
1243 // Figure out which register class each belongs in: rc_int, rc_float, rc_vector, rc_stack.
1244 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1245
1246 static enum RC rc_class(OptoReg::Name reg) {
1247 // Return the register class for the given register. The given register
1248 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1249 // enumeration in adGlobals_s390.hpp.
1250
1251 if (reg == OptoReg::Bad) {
1252 return rc_bad;
1253 }
1254
1255 // We have 32 integer register halves, starting at index 0.
1256 if (reg < 32) {
1257 return rc_int;
1258 }
1259
1260 // We have 32 floating-point register halves, starting at index 32.
1261 if (reg < 32+32) {
1262 return rc_float;
1263 }
1264
1265 // we have 128 vector register halves at index 64
1266 if (reg < 32+32+128) {
1267 return rc_vector;
1268 }
1269
1270 // Between float regs & stack are the flags regs.
1271 assert(OptoReg::is_stack(reg) || reg < 32+32+128, "blow up if spilling flags");
1272 return rc_stack;
1273 }
1274
1275 // Returns size as obtained from z_emit_instr.
1276 static unsigned int z_ld_st_helper(C2_MacroAssembler *masm, const char *op_str, unsigned long opcode,
1277 int reg, int offset, bool do_print, outputStream *os) {
1278
1279 if (masm) {
1280 if (opcode > (1L<<32)) {
1281 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1282 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1283 } else {
1284 return z_emit_inst(masm, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1285 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1286 }
1287 }
1288
1289 #if !defined(PRODUCT)
1290 if (do_print) {
1291 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1292 }
1293 #endif
1294 return (opcode > (1L << 32)) ? 6 : 4;
1295 }
1296
1297 static unsigned int z_mvc_helper(C2_MacroAssembler *masm, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1298 if (masm) {
1299 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1300 }
1301
1302 #if !defined(PRODUCT)
1303 else if (do_print) {
1304 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1305 }
1306 #endif
1307
1308 return 6;
1309 }
1310
1311 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1312 // Get registers to move.
1313 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1314 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1315 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1316 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1317
1318 enum RC src_hi_rc = rc_class(src_hi);
1319 enum RC src_lo_rc = rc_class(src_lo);
1320 enum RC dst_hi_rc = rc_class(dst_hi);
1321 enum RC dst_lo_rc = rc_class(dst_lo);
1322
1323 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1324 bool is64 = (src_hi_rc != rc_bad);
1325 assert(!is64 ||
1326 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1327 "expected aligned-adjacent pairs");
1328
1329 // Generate spill code!
1330 int size = 0;
1331 if (src_lo == dst_lo && src_hi == dst_hi) {
1332 return 0; // Self copy, no move.
1333 }
1334
1335 int src_offset = ra_->reg2offset(src_lo);
1336 int dst_offset = ra_->reg2offset(dst_lo);
1337 bool print = !do_size;
1338 bool src12 = Immediate::is_uimm12(src_offset);
1339 bool dst12 = Immediate::is_uimm12(dst_offset);
1340
1341 const char *mnemo = nullptr;
1342 unsigned long opc = 0;
1343
1344 if (bottom_type()->isa_vect() != nullptr && ideal_reg() == Op_VecX) {
1345 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1346 if (masm != nullptr) {
1347 __ z_mvc(Address(Z_SP, 0, dst_offset), Address(Z_SP, 0, src_offset), 16);
1348 }
1349 size += 6;
1350 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1351 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1352 if (masm != nullptr) {
1353 __ z_vst(Rsrc, Address(Z_SP, 0, dst_offset));
1354 }
1355 size += 6;
1356 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1357 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1358 if (masm != nullptr) {
1359 __ z_vl(Rdst, Address(Z_SP, 0, src_offset));
1360 }
1361 size += 6;
1362 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1363 VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
1364 VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
1365 if (masm != nullptr) {
1366 __ z_vlr(Rdst, Rsrc);
1367 }
1368 size += 6;
1369 } else {
1370 ShouldNotReachHere();
1371 }
1372 return size;
1373 }
1374
1375 // Memory->Memory Spill. Use Z_R0 to hold the value.
1376 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1377
1378 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1379 "expected same type of move for high parts");
1380
1381 if (src12 && dst12) {
1382 return z_mvc_helper(masm, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1383 }
1384
1385 int r0 = Z_R0_num;
1386 if (is64) {
1387 return z_ld_st_helper(masm, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1388 z_ld_st_helper(masm, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1389 }
1390
1391 return z_ld_st_helper(masm, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1392 z_ld_st_helper(masm, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1393 }
1394
1395 // Check for float->int copy. Requires a trip through memory.
1396 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1397 Unimplemented(); // Unsafe, do not remove!
1398 }
1399
1400 // Check for integer reg-reg copy.
1401 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1402 if (masm) {
1403 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1404 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1405 __ z_lgr(Rdst, Rsrc);
1406 return 4;
1407 }
1408 #if !defined(PRODUCT)
1409 // else
1410 if (print) {
1411 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1412 }
1413 #endif
1414 return 4;
1415 }
1416
1417 // Check for integer store.
1418 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1419 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1420 "expected same type of move for high parts");
1421
1422 if (is64) {
1423 return z_ld_st_helper(masm, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1424 }
1425
1426 // else
1427 mnemo = dst12 ? "ST " : "STY ";
1428 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1429
1430 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1431 }
1432
1433 // Check for integer load
1434 // Always load cOops zero-extended. That doesn't hurt int loads.
1435 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1436
1437 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1438 "expected same type of move for high parts");
1439
1440 mnemo = is64 ? "LG " : "LLGF";
1441 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1442
1443 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1444 }
1445
1446 // Check for float reg-reg copy.
1447 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1448 if (masm) {
1449 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1450 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1451 __ z_ldr(Rdst, Rsrc);
1452 return 2;
1453 }
1454 #if !defined(PRODUCT)
1455 // else
1456 if (print) {
1457 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1458 }
1459 #endif
1460 return 2;
1461 }
1462
1463 // Check for float store.
1464 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1465 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1466 "expected same type of move for high parts");
1467
1468 if (is64) {
1469 mnemo = dst12 ? "STD " : "STDY ";
1470 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1471 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1472 }
1473 // else
1474
1475 mnemo = dst12 ? "STE " : "STEY ";
1476 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1477 return z_ld_st_helper(masm, mnemo, opc, src_lo, dst_offset, print, os);
1478 }
1479
1480 // Check for float load.
1481 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1482 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1483 "expected same type of move for high parts");
1484
1485 if (is64) {
1486 mnemo = src12 ? "LD " : "LDY ";
1487 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1488 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1489 }
1490 // else
1491
1492 mnemo = src12 ? "LE " : "LEY ";
1493 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1494 return z_ld_st_helper(masm, mnemo, opc, dst_lo, src_offset, print, os);
1495 }
1496
1497 // --------------------------------------------------------------------
1498 // Check for hi bits still needing moving. Only happens for misaligned
1499 // arguments to native calls.
1500 if (src_hi == dst_hi) {
1501 return 0; // Self copy, no move.
1502 }
1503
1504 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1505 Unimplemented(); // Unsafe, do not remove!
1506
1507 return 0; // never reached, but make the compiler shut up!
1508 }
1509
1510 #if !defined(PRODUCT)
1511 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1512 if (ra_ && ra_->node_regs_max_index() > 0) {
1513 implementation(nullptr, ra_, false, os);
1514 } else {
1515 if (req() == 2 && in(1)) {
1516 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1517 } else {
1518 const char *c = "(";
1519 os->print("N%d = ", _idx);
1520 for (uint i = 1; i < req(); ++i) {
1521 os->print("%sN%d", c, in(i)->_idx);
1522 c = ", ";
1523 }
1524 os->print(")");
1525 }
1526 }
1527 }
1528 #endif
1529
1530 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1531 implementation(masm, ra_, false, nullptr);
1532 }
1533
1534 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1535 return implementation(nullptr, ra_, true, nullptr);
1536 }
1537
1538 //=============================================================================
1539
1540 #if !defined(PRODUCT)
1541 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1542 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1543 }
1544 #endif
1545
1546 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc * ra_) const {
1547 int rem_space = 0;
1548 if (!(ra_->C->output()->in_scratch_emit_size())) {
1549 rem_space = __ code()->insts()->remaining();
1550 if (rem_space <= _count*2 + 8) {
1551 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1552 }
1553 }
1554
1555 for (int i = 0; i < _count; i++) {
1556 __ z_nop();
1557 }
1558
1559 if (!(ra_->C->output()->in_scratch_emit_size())) {
1560 if (rem_space <= _count*2 + 8) {
1561 int rem_space2 = __ code()->insts()->remaining();
1562 tty->print_cr(", after = %d", rem_space2);
1563 }
1564 }
1565 }
1566
1567 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1568 return 2 * _count;
1569 }
1570
1571 #if !defined(PRODUCT)
1572 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1573 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1574 if (ra_ && ra_->node_regs_max_index() > 0) {
1575 int reg = ra_->get_reg_first(this);
1576 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1577 } else {
1578 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1579 }
1580 }
1581 #endif
1582
1583 // Take care of the size function, if you make changes here!
1584 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1585 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1586 int reg = ra_->get_encode(this);
1587 __ z_lay(as_Register(reg), offset, Z_SP);
1588 }
1589
1590 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1591 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1592 return 6;
1593 }
1594
1595 %} // end source section
1596
1597 //----------SOURCE BLOCK-------------------------------------------------------
1598 // This is a block of C++ code which provides values, functions, and
1599 // definitions necessary in the rest of the architecture description
1600
1601 source_hpp %{
1602
1603 // Header information of the source block.
1604 // Method declarations/definitions which are used outside
1605 // the ad-scope can conveniently be defined here.
1606 //
1607 // To keep related declarations/definitions/uses close together,
1608 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1609 #include "opto/convertnode.hpp"
1610 #include "oops/klass.inline.hpp"
1611
1612 //--------------------------------------------------------------
1613 // Used for optimization in Compile::Shorten_branches
1614 //--------------------------------------------------------------
1615
1616 class CallStubImpl {
1617 public:
1618
1619 // call trampolines
1620 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1621 static uint size_call_trampoline() {
1622 return 0; // no call trampolines on this platform
1623 }
1624
1625 // call trampolines
1626 // Number of relocations needed by a call trampoline stub.
1627 static uint reloc_call_trampoline() {
1628 return 0; // No call trampolines on this platform.
1629 }
1630 };
1631
1632 %} // end source_hpp section
1633
1634 source %{
1635
1636 #ifndef PRODUCT
1637 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1638 {
1639 Unimplemented();
1640 }
1641 #endif
1642
1643 void MachVEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc* ra_) const
1644 {
1645 Unimplemented();
1646 }
1647
1648 #if !defined(PRODUCT)
1649 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1650 os->print_cr("---- MachUEPNode ----");
1651 os->print_cr("\tTA");
1652 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1653 os->print_cr("\tBR(Z_R1)");
1654 os->print_cr("\tTA # pad with illtraps");
1655 os->print_cr("\t...");
1656 os->print_cr("\tTA");
1657 os->print_cr("\tLTGR Z_R2, Z_R2");
1658 os->print_cr("\tBRU ic_miss");
1659 }
1660 #endif
1661
1662 void MachUEPNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1663 // This is Unverified Entry Point
1664 __ ic_check(CodeEntryAlignment);
1665 }
1666
1667 //=============================================================================
1668
1669 %} // interrupt source section
1670
1671 source_hpp %{ // Header information of the source block.
1672
1673 class HandlerImpl {
1674 public:
1675
1676 static int emit_deopt_handler(C2_MacroAssembler* masm);
1677
1678 static uint size_deopt_handler() {
1679 return NativeCall::max_instruction_size() + MacroAssembler::jump_pcrelative_size();
1680 }
1681 };
1682
1683 class Node::PD {
1684 public:
1685 enum NodeFlags {
1686 _last_flag = Node::_last_flag
1687 };
1688 };
1689
1690 %} // end source_hpp section
1691
1692 source %{
1693
1694 // Emit deopt handler code.
1695 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm) {
1696 address base = __ start_a_stub(size_deopt_handler());
1697
1698 if (base == nullptr) {
1699 ciEnv::current()->record_failure("CodeCache is full");
1700 return 0; // CodeBuffer::expand failed
1701 }
1702
1703 int offset = __ offset();
1704
1705 Label start;
1706 __ bind(start);
1707
1708 // Size_deopt_handler() must be exact on zarch, so for simplicity
1709 // we do not use load_const_opt here.
1710 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1711 __ call(Z_R1);
1712
1713 int entry_offset = __ offset();
1714
1715 __ z_bru(start);
1716
1717 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1718 assert(__ offset() - entry_offset >= NativePostCallNop::first_check_size,
1719 "out of bounds read in post-call NOP check");
1720
1721 __ end_a_stub();
1722 return entry_offset;
1723 }
1724
1725 //=============================================================================
1726
1727
1728 // Given a register encoding, produce an Integer Register object.
1729 static Register reg_to_register_object(int register_encoding) {
1730 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1731 return as_Register(register_encoding);
1732 }
1733
1734 bool Matcher::match_rule_supported(int opcode) {
1735 if (!has_match_rule(opcode)) {
1736 return false; // no match rule present
1737 }
1738
1739 switch (opcode) {
1740 case Op_ReverseBytesI:
1741 case Op_ReverseBytesL:
1742 case Op_ReverseBytesS:
1743 case Op_ReverseBytesUS:
1744 return UseByteReverseInstruction;
1745 case Op_PopCountI:
1746 case Op_PopCountL:
1747 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1748 return (UsePopCountInstruction && VM_Version::has_PopCount());
1749 case Op_AddVB:
1750 case Op_AddVS:
1751 case Op_AddVI:
1752 case Op_AddVL:
1753 case Op_AddVD:
1754 case Op_SubVB:
1755 case Op_SubVS:
1756 case Op_SubVI:
1757 case Op_SubVL:
1758 case Op_SubVD:
1759 case Op_MulVB:
1760 case Op_MulVS:
1761 case Op_MulVI:
1762 case Op_MulVD:
1763 case Op_DivVD:
1764 case Op_SqrtVD:
1765 case Op_RoundDoubleModeV:
1766 return SuperwordUseVX;
1767 case Op_AddVF:
1768 case Op_SubVF:
1769 case Op_MulVF:
1770 case Op_DivVF:
1771 case Op_SqrtVF:
1772 //PopCountVI supported by z14 onwards.
1773 case Op_PopCountVI:
1774 return (SuperwordUseVX && UseSFPV);
1775 case Op_FmaF:
1776 case Op_FmaD:
1777 return UseFMA;
1778 }
1779
1780 return true; // Per default match rules are supported.
1781 }
1782
1783 bool Matcher::match_rule_supported_auto_vectorization(int opcode, int vlen, BasicType bt) {
1784 return match_rule_supported_vector(opcode, vlen, bt);
1785 }
1786
1787 bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1788 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1789 return false;
1790 }
1791 return true; // Per default match rules are supported.
1792 }
1793
1794 bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
1795 return false;
1796 }
1797
1798 bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
1799 return false;
1800 }
1801
1802 bool Matcher::vector_rearrange_requires_load_shuffle(BasicType elem_bt, int vlen) {
1803 return false;
1804 }
1805
1806 bool Matcher::mask_op_prefers_predicate(int opcode, const TypeVect* vt) {
1807 return false;
1808 }
1809
1810 const RegMask* Matcher::predicate_reg_mask(void) {
1811 return nullptr;
1812 }
1813
1814 // Vector calling convention not yet implemented.
1815 bool Matcher::supports_vector_calling_convention(void) {
1816 return false;
1817 }
1818
1819 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1820 Unimplemented();
1821 return OptoRegPair(0, 0);
1822 }
1823
1824 //----------SUPERWORD HELPERS----------------------------------------
1825
1826 // Vector width in bytes.
1827 int Matcher::vector_width_in_bytes(BasicType bt) {
1828 if (SuperwordUseVX) {
1829 assert(MaxVectorSize == 16, "");
1830 return 16;
1831 } else {
1832 assert(MaxVectorSize == 8, "");
1833 return 8;
1834 }
1835 }
1836
1837 // Vector ideal reg.
1838 uint Matcher::vector_ideal_reg(int size) {
1839 if (SuperwordUseVX) {
1840 assert(MaxVectorSize == 16 && size == 16, "");
1841 return Op_VecX;
1842 } else {
1843 assert(MaxVectorSize == 8 && size == 8, "");
1844 return Op_RegL;
1845 }
1846 }
1847
1848 // Limits on vector size (number of elements) loaded into vector.
1849 int Matcher::max_vector_size(const BasicType bt) {
1850 assert(is_java_primitive(bt), "only primitive type vectors");
1851 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1852 }
1853
1854 int Matcher::min_vector_size(const BasicType bt) {
1855 return max_vector_size(bt); // Same as max.
1856 }
1857
1858 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
1859 return Matcher::max_vector_size(bt);
1860 }
1861
1862 int Matcher::scalable_vector_reg_size(const BasicType bt) {
1863 return -1;
1864 }
1865
1866 // RETURNS: whether this branch offset is short enough that a short
1867 // branch can be used.
1868 //
1869 // If the platform does not provide any short branch variants, then
1870 // this method should return `false' for offset 0.
1871 //
1872 // `Compile::Fill_buffer' will decide on basis of this information
1873 // whether to do the pass `Compile::Shorten_branches' at all.
1874 //
1875 // And `Compile::Shorten_branches' will decide on basis of this
1876 // information whether to replace particular branch sites by short
1877 // ones.
1878 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1879 // On zarch short branches use a 16 bit signed immediate that
1880 // is the pc-relative offset in halfword (= 2 bytes) units.
1881 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1882 }
1883
1884 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1885 ShouldNotReachHere(); // generic vector operands not supported
1886 return nullptr;
1887 }
1888
1889 bool Matcher::is_reg2reg_move(MachNode* m) {
1890 ShouldNotReachHere(); // generic vector operands not supported
1891 return false;
1892 }
1893
1894 bool Matcher::is_register_biasing_candidate(const MachNode* mdef, int oper_index) {
1895 return false;
1896 }
1897
1898 bool Matcher::is_generic_vector(MachOper* opnd) {
1899 ShouldNotReachHere(); // generic vector operands not supported
1900 return false;
1901 }
1902
1903 // Constants for c2c and c calling conventions.
1904
1905 const MachRegisterNumbers z_iarg_reg[5] = {
1906 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1907 };
1908
1909 const MachRegisterNumbers z_farg_reg[4] = {
1910 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1911 };
1912
1913 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1914
1915 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1916
1917 #ifdef ASSERT
1918 // Return whether or not this register is ever used as an argument.
1919 bool Matcher::can_be_java_arg(int reg) {
1920 // We return true for all registers contained in z_iarg_reg[] and
1921 // z_farg_reg[] and their virtual halves.
1922 // We must include the virtual halves in order to get STDs and LDs
1923 // instead of STWs and LWs in the trampoline stubs.
1924
1925 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1926 reg == Z_R3_num || reg == Z_R3_H_num ||
1927 reg == Z_R4_num || reg == Z_R4_H_num ||
1928 reg == Z_R5_num || reg == Z_R5_H_num ||
1929 reg == Z_R6_num || reg == Z_R6_H_num) {
1930 return true;
1931 }
1932
1933 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1934 reg == Z_F2_num || reg == Z_F2_H_num ||
1935 reg == Z_F4_num || reg == Z_F4_H_num ||
1936 reg == Z_F6_num || reg == Z_F6_H_num) {
1937 return true;
1938 }
1939
1940 return false;
1941 }
1942 #endif
1943
1944 uint Matcher::int_pressure_limit()
1945 {
1946 // Medium size register set, 6 special purpose regs, 3 SOE regs.
1947 // 10 prevents spill-split-recycle sanity check in JVM2008.xml.transform.
1948 return (INTPRESSURE == -1) ? 10 : INTPRESSURE;
1949 }
1950
1951 uint Matcher::float_pressure_limit()
1952 {
1953 return (FLOATPRESSURE == -1) ? 15 : FLOATPRESSURE;
1954 }
1955
1956 // Register for the first projection of an int pair
1957 const RegMask& Matcher::firstI_proj_mask() {
1958 return _Z_RARG4_INT_REG_mask;
1959 }
1960
1961 // Register for the second projection of an int pair
1962 const RegMask& Matcher::secondI_proj_mask() {
1963 return _Z_RARG3_INT_REG_mask;
1964 }
1965
1966 // Register for the first projection of a long pair
1967 const RegMask& Matcher::firstL_proj_mask() {
1968 return _Z_RARG4_LONG_REG_mask;
1969 }
1970
1971 // Register for the second projection of a long pair
1972 const RegMask& Matcher::secondL_proj_mask() {
1973 return _Z_RARG3_LONG_REG_mask;
1974 }
1975
1976 // Should the matcher clone input 'm' of node 'n'?
1977 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
1978 if (is_encode_and_store_pattern(n, m)) {
1979 mstack.push(m, Visit);
1980 return true;
1981 }
1982 return false;
1983 }
1984
1985 // Should the Matcher clone shifts on addressing modes, expecting them
1986 // to be subsumed into complex addressing expressions or compute them
1987 // into registers?
1988 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1989 return clone_base_plus_offset_address(m, mstack, address_visited);
1990 }
1991
1992 %} // source
1993
1994 //----------ENCODING BLOCK-----------------------------------------------------
1995 // This block specifies the encoding classes used by the compiler to output
1996 // byte streams. Encoding classes are parameterized macros used by
1997 // Machine Instruction Nodes in order to generate the bit encoding of the
1998 // instruction. Operands specify their base encoding interface with the
1999 // interface keyword. There are currently supported four interfaces,
2000 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2001 // operand to generate a function which returns its register number when
2002 // queried. CONST_INTER causes an operand to generate a function which
2003 // returns the value of the constant when queried. MEMORY_INTER causes an
2004 // operand to generate four functions which return the Base Register, the
2005 // Index Register, the Scale Value, and the Offset Value of the operand when
2006 // queried. COND_INTER causes an operand to generate six functions which
2007 // return the encoding code (ie - encoding bits for the instruction)
2008 // associated with each basic boolean condition for a conditional instruction.
2009 //
2010 // Instructions specify two basic values for encoding. Again, a function
2011 // is available to check if the constant displacement is an oop. They use the
2012 // ins_encode keyword to specify their encoding classes (which must be
2013 // a sequence of enc_class names, and their parameters, specified in
2014 // the encoding block), and they use the
2015 // opcode keyword to specify, in order, their primary, secondary, and
2016 // tertiary opcode. Only the opcode sections which a particular instruction
2017 // needs for encoding need to be specified.
2018 encode %{
2019 enc_class enc_unimplemented %{
2020 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2021 %}
2022
2023 enc_class enc_untested %{
2024 #ifdef ASSERT
2025 __ untested("Untested mach node encoding in AD file.");
2026 #endif
2027 %}
2028
2029 enc_class z_rrform(iRegI dst, iRegI src) %{
2030 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
2031 assert( ($primary >> 16) == 0, "Instruction format error");
2032 z_emit16(masm, $primary |
2033 Assembler::reg($dst$$reg,8,16) |
2034 Assembler::reg($src$$reg,12,16));
2035 %}
2036
2037 enc_class z_rreform(iRegI dst1, iRegI src2) %{
2038 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2039 z_emit32(masm, $primary |
2040 Assembler::reg($dst1$$reg,24,32) |
2041 Assembler::reg($src2$$reg,28,32));
2042 %}
2043
2044 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
2045 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
2046 z_emit32(masm, $primary |
2047 Assembler::reg($dst1$$reg,24,32) |
2048 Assembler::reg($src2$$reg,28,32) |
2049 Assembler::reg($src3$$reg,16,32));
2050 %}
2051
2052 enc_class z_riform_signed(iRegI dst, immI16 src) %{
2053 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2054 z_emit32(masm, $primary |
2055 Assembler::reg($dst$$reg,8,32) |
2056 Assembler::simm16($src$$constant,16,32));
2057 %}
2058
2059 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
2060 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
2061 z_emit32(masm, $primary |
2062 Assembler::reg($dst$$reg,8,32) |
2063 Assembler::uimm16($src$$constant,16,32));
2064 %}
2065
2066 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
2067 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2068 z_emit48(masm, $primary |
2069 Assembler::reg($dst1$$reg,8,48) |
2070 Assembler::reg($src3$$reg,12,48) |
2071 Assembler::simm16($src2$$constant,16,48));
2072 %}
2073
2074 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
2075 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2076 z_emit48(masm, $primary |
2077 Assembler::reg($dst$$reg,8,48) |
2078 Assembler::simm32($src$$constant,16,48));
2079 %}
2080
2081 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
2082 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
2083 z_emit48(masm, $primary |
2084 Assembler::reg($dst$$reg,8,48) |
2085 Assembler::uimm32($src$$constant,16,48));
2086 %}
2087
2088 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
2089 z_emit48(masm, $primary |
2090 Assembler::reg($dst$$reg,8,48) |
2091 Assembler::reg($src1$$reg,12,48) |
2092 Assembler::simm20($src2$$constant));
2093 %}
2094
2095 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
2096 z_emit48(masm, $primary |
2097 Assembler::reg($dst$$reg,8,48) |
2098 Assembler::reg($src$$reg,12,48) |
2099 Assembler::reg($shft$$reg,16,48) |
2100 Assembler::simm20(0));
2101 %}
2102
2103 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2104 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2105 z_emit32(masm, $primary |
2106 Assembler::reg($dst$$reg,8,32) |
2107 Assembler::reg($src1$$reg,12,32) |
2108 Assembler::reg($src2$$reg,16,32) |
2109 Assembler::uimm12($con$$constant,20,32));
2110 %}
2111
2112 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
2113 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
2114 z_emit32(masm, $primary |
2115 Assembler::reg($dst$$reg,8,32) |
2116 Assembler::reg($src$$reg,16,32) |
2117 Assembler::uimm12($con$$constant,20,32));
2118 %}
2119
2120 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
2121 z_emit48(masm, $primary |
2122 Assembler::reg($dst$$reg,8,48) |
2123 Assembler::reg($src1$$reg,12,48) |
2124 Assembler::reg($src2$$reg,16,48) |
2125 Assembler::simm20($con$$constant));
2126 %}
2127
2128 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
2129 z_emit48(masm, $primary |
2130 Assembler::reg($dst$$reg,8,48) |
2131 Assembler::reg($src$$reg,16,48) |
2132 Assembler::simm20($con$$constant));
2133 %}
2134
2135 // Direct memory arithmetic.
2136 enc_class z_siyform(memoryRSY mem, immI8 src) %{
2137 int disp = $mem$$disp;
2138 Register base = reg_to_register_object($mem$$base);
2139 int con = $src$$constant;
2140
2141 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
2142 z_emit_inst(masm, $primary |
2143 Assembler::regz(base,16,48) |
2144 Assembler::simm20(disp) |
2145 Assembler::simm8(con,8,48));
2146 %}
2147
2148 enc_class z_silform(memoryRS mem, immI16 src) %{
2149 z_emit_inst(masm, $primary |
2150 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
2151 Assembler::uimm12($mem$$disp,20,48) |
2152 Assembler::simm16($src$$constant,32,48));
2153 %}
2154
2155 // Encoder for FP ALU reg/mem instructions (support only short displacements).
2156 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
2157 Register Ridx = $mem$$index$$Register;
2158 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2159 if ($primary > (1L << 32)) {
2160 z_emit_inst(masm, $primary |
2161 Assembler::reg($dst$$reg, 8, 48) |
2162 Assembler::uimm12($mem$$disp, 20, 48) |
2163 Assembler::reg(Ridx, 12, 48) |
2164 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2165 } else {
2166 z_emit_inst(masm, $primary |
2167 Assembler::reg($dst$$reg, 8, 32) |
2168 Assembler::uimm12($mem$$disp, 20, 32) |
2169 Assembler::reg(Ridx, 12, 32) |
2170 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2171 }
2172 %}
2173
2174 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
2175 Register Ridx = $mem$$index$$Register;
2176 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2177 if ($primary > (1L<<32)) {
2178 z_emit_inst(masm, $primary |
2179 Assembler::reg($dst$$reg, 8, 48) |
2180 Assembler::simm20($mem$$disp) |
2181 Assembler::reg(Ridx, 12, 48) |
2182 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2183 } else {
2184 z_emit_inst(masm, $primary |
2185 Assembler::reg($dst$$reg, 8, 32) |
2186 Assembler::uimm12($mem$$disp, 20, 32) |
2187 Assembler::reg(Ridx, 12, 32) |
2188 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
2189 }
2190 %}
2191
2192 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
2193 int isize = $secondary > 1L << 32 ? 48 : 32;
2194 Register Ridx = $mem$$index$$Register;
2195 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2196
2197 if (Displacement::is_shortDisp((long)$mem$$disp)) {
2198 z_emit_inst(masm, $secondary |
2199 Assembler::reg($dst$$reg, 8, isize) |
2200 Assembler::uimm12($mem$$disp, 20, isize) |
2201 Assembler::reg(Ridx, 12, isize) |
2202 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2203 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
2204 z_emit_inst(masm, $primary |
2205 Assembler::reg($dst$$reg, 8, 48) |
2206 Assembler::simm20($mem$$disp) |
2207 Assembler::reg(Ridx, 12, 48) |
2208 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2209 } else {
2210 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2211 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2212 z_emit_inst(masm, $secondary |
2213 Assembler::reg($dst$$reg, 8, isize) |
2214 Assembler::uimm12(0, 20, isize) |
2215 Assembler::reg(Z_R1_scratch, 12, isize) |
2216 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2217 }
2218 %}
2219
2220 enc_class z_enc_brul(Label lbl) %{
2221 Label* p = $lbl$$label;
2222
2223 // 'p' is `nullptr' when this encoding class is used only to
2224 // determine the size of the encoded instruction.
2225 // Use a bound dummy label in that case.
2226 Label d;
2227 __ bind(d);
2228 Label& l = (nullptr == p) ? d : *(p);
2229 __ z_brul(l);
2230 %}
2231
2232 enc_class z_enc_bru(Label lbl) %{
2233 Label* p = $lbl$$label;
2234
2235 // 'p' is `nullptr' when this encoding class is used only to
2236 // determine the size of the encoded instruction.
2237 // Use a bound dummy label in that case.
2238 Label d;
2239 __ bind(d);
2240 Label& l = (nullptr == p) ? d : *(p);
2241 __ z_bru(l);
2242 %}
2243
2244 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2245 Label* p = $lbl$$label;
2246
2247 // 'p' is `nullptr' when this encoding class is used only to
2248 // determine the size of the encoded instruction.
2249 // Use a bound dummy label in that case.
2250 Label d;
2251 __ bind(d);
2252 Label& l = (nullptr == p) ? d : *(p);
2253 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2254 %}
2255
2256 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2257 Label* p = $lbl$$label;
2258
2259 // 'p' is `nullptr' when this encoding class is used only to
2260 // determine the size of the encoded instruction.
2261 // Use a bound dummy label in that case.
2262 Label d;
2263 __ bind(d);
2264 Label& l = (nullptr == p) ? d : *(p);
2265 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2266 %}
2267
2268 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2269 Label* p = $lbl$$label;
2270
2271 // 'p' is `nullptr' when this encoding class is used only to
2272 // determine the size of the encoded instruction.
2273 // Use a bound dummy label in that case.
2274 Label d;
2275 __ bind(d);
2276 Label& l = (nullptr == p) ? d : *(p);
2277 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2278 unsigned long instr = $primary;
2279 if (instr == CRJ_ZOPC) {
2280 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2281 } else if (instr == CLRJ_ZOPC) {
2282 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2283 } else if (instr == CGRJ_ZOPC) {
2284 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2285 } else {
2286 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2287 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2288 }
2289 %}
2290
2291 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2292 Label* p = $lbl$$label;
2293
2294 // 'p' is `nullptr' when this encoding class is used only to
2295 // determine the size of the encoded instruction.
2296 // Use a bound dummy label in that case.
2297 Label d;
2298 __ bind(d);
2299 Label& l = (nullptr == p) ? d : *(p);
2300
2301 unsigned long instr = $primary;
2302 if (instr == CR_ZOPC) {
2303 __ z_cr($src1$$Register, $src2$$Register);
2304 } else if (instr == CLR_ZOPC) {
2305 __ z_clr($src1$$Register, $src2$$Register);
2306 } else if (instr == CGR_ZOPC) {
2307 __ z_cgr($src1$$Register, $src2$$Register);
2308 } else {
2309 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2310 __ z_clgr($src1$$Register, $src2$$Register);
2311 }
2312
2313 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2314 %}
2315
2316 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2317 Label* p = $lbl$$label;
2318
2319 // 'p' is `nullptr' when this encoding class is used only to
2320 // determine the size of the encoded instruction.
2321 // Use a bound dummy label in that case.
2322 Label d;
2323 __ bind(d);
2324 Label& l = (nullptr == p) ? d : *(p);
2325
2326 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2327 unsigned long instr = $primary;
2328 if (instr == CIJ_ZOPC) {
2329 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2330 } else if (instr == CLIJ_ZOPC) {
2331 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2332 } else if (instr == CGIJ_ZOPC) {
2333 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2334 } else {
2335 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2336 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2337 }
2338 %}
2339
2340 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2341 Label* p = $lbl$$label;
2342
2343 // 'p' is `nullptr' when this encoding class is used only to
2344 // determine the size of the encoded instruction.
2345 // Use a bound dummy label in that case.
2346 Label d;
2347 __ bind(d);
2348 Label& l = (nullptr == p) ? d : *(p);
2349
2350 unsigned long instr = $primary;
2351 if (instr == CHI_ZOPC) {
2352 __ z_chi($src1$$Register, $src2$$constant);
2353 } else if (instr == CLFI_ZOPC) {
2354 __ z_clfi($src1$$Register, $src2$$constant);
2355 } else if (instr == CGHI_ZOPC) {
2356 __ z_cghi($src1$$Register, $src2$$constant);
2357 } else {
2358 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2359 __ z_clgfi($src1$$Register, $src2$$constant);
2360 }
2361
2362 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2363 %}
2364
2365 // Call from Java to runtime.
2366 enc_class z_enc_java_to_runtime_call(method meth) %{
2367 // Save return pc before call to the place where we need it, since
2368 // callee doesn't.
2369 unsigned int start_off = __ offset();
2370 // Compute size of "larl + stg + call_c_opt".
2371 __ get_PC(Z_R14, ret_addr_offset());
2372 __ save_return_pc();
2373 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2374
2375 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2376 address call_addr = __ call_c_opt((address)$meth$$method);
2377 if (call_addr == nullptr) {
2378 Compile::current()->env()->record_out_of_memory_failure();
2379 return;
2380 }
2381
2382 assert(__ offset() - start_off == (uint)ret_addr_offset(),
2383 "z_enc_java_to_runtime_call return offset mismatch: emitted %d bytes, ret_addr_offset()=%d",
2384 __ offset() - start_off, ret_addr_offset());
2385 __ post_call_nop();
2386 %}
2387
2388 enc_class z_enc_java_static_call(method meth) %{
2389 unsigned int start_off = __ offset();
2390 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2391 // whom we intended to call.
2392
2393 if (!_method) {
2394 emit_call_reloc(masm, $meth$$method,
2395 relocInfo::runtime_call_w_cp_type, ra_);
2396 } else {
2397 int method_index = resolved_method_index(masm);
2398 if (_optimized_virtual) {
2399 emit_call_reloc(masm, $meth$$method,
2400 opt_virtual_call_Relocation::spec(method_index));
2401 } else {
2402 emit_call_reloc(masm, $meth$$method,
2403 static_call_Relocation::spec(method_index));
2404 }
2405 }
2406 assert(__ inst_mark() != nullptr, "emit_call_reloc must set_inst_mark()");
2407
2408 if (_method) { // Emit stub for static call.
2409 address stub = CompiledDirectCall::emit_to_interp_stub(masm);
2410 if (stub == nullptr) {
2411 __ clear_inst_mark();
2412 ciEnv::current()->record_failure("CodeCache is full");
2413 return;
2414 }
2415 }
2416
2417 __ clear_inst_mark();
2418 assert(__ offset() - start_off == (uint)ret_addr_offset(),
2419 "z_enc_java_static_call return offset mismatch: emitted %d bytes, ret_addr_offset()=%d",
2420 __ offset() - start_off, ret_addr_offset());
2421 __ post_call_nop();
2422 %}
2423
2424 // Java dynamic call
2425 enc_class z_enc_java_dynamic_call(method meth) %{
2426 unsigned int start_off = __ offset();
2427
2428 int vtable_index = this->_vtable_index;
2429 if (vtable_index == -4) {
2430 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2431 address virtual_call_oop_addr = nullptr;
2432
2433 AddressLiteral empty_ic((address) Universe::non_oop_word());
2434 virtual_call_oop_addr = __ pc();
2435 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2436 if (!success) {
2437 Compile::current()->env()->record_out_of_memory_failure();
2438 return;
2439 }
2440
2441 // Call to fixup routine. Fixup routine uses ScopeDesc info
2442 // to determine who we intended to call.
2443 int method_index = resolved_method_index(masm);
2444 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2445 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2446 emit_call_reloc(masm, $meth$$method, relocInfo::none, ra_);
2447 __ clear_inst_mark();
2448 assert(_method, "lazy_constant may be wrong when _method==null");
2449 } else {
2450 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2451 // Go through the vtable. Get receiver klass. Receiver already
2452 // checked for non-null. If we'll go thru a C2I adapter, the
2453 // interpreter expects method in Z_method.
2454 // Use Z_method to temporarily hold the klass oop.
2455 // Z_R1_scratch is destroyed.
2456 __ load_klass(Z_method, Z_R2);
2457
2458 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2459 int v_off = entry_offset + in_bytes(vtableEntry::method_offset());
2460
2461 if (Displacement::is_validDisp(v_off) ) {
2462 // Can use load instruction with large offset.
2463 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2464 } else {
2465 // Worse case, must load offset into register.
2466 __ load_const(Z_R1_scratch, v_off);
2467 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2468 }
2469 // NOTE: for vtable dispatches, the vtable entry will never be
2470 // null. However it may very well end up in handle_wrong_method
2471 // if the method is abstract for the particular class.
2472 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2473 // Call target. Either compiled code or C2I adapter.
2474 __ z_basr(Z_R14, Z_R1_scratch);
2475 }
2476 assert(__ offset() - start_off == (uint)ret_addr_offset(),
2477 "z_enc_java_dynamic_call return offset mismatch: emitted %d bytes, ret_addr_offset()=%d",
2478 __ offset() - start_off, ret_addr_offset());
2479
2480 __ post_call_nop();
2481 %}
2482
2483 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2484 Register Rdst = reg_to_register_object($dst$$reg);
2485 Register Rsrc = reg_to_register_object($src$$reg);
2486
2487 // Don't emit code if operands are identical (same register).
2488 if (Rsrc != Rdst) {
2489 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2490
2491 if (VM_Version::has_LoadStoreConditional()) {
2492 __ z_locgr(Rdst, Rsrc, cc);
2493 } else {
2494 // Branch if not (cmp cr).
2495 Label done;
2496 __ z_brc(Assembler::inverse_condition(cc), done);
2497 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2498 __ bind(done);
2499 }
2500 }
2501 %}
2502
2503 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2504 Register Rdst = reg_to_register_object($dst$$reg);
2505 int Csrc = $src$$constant;
2506 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2507 Label done;
2508 // Branch if not (cmp cr).
2509 __ z_brc(Assembler::inverse_condition(cc), done);
2510 if (Csrc == 0) {
2511 // Don't set CC.
2512 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2513 } else {
2514 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2515 }
2516 __ bind(done);
2517 %}
2518
2519 enc_class z_enc_cctobool(iRegI res) %{
2520 Register Rres = reg_to_register_object($res$$reg);
2521
2522 if (VM_Version::has_LoadStoreConditional()) {
2523 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2524 __ load_const_optimized(Rres, 1L); // true (succeed)
2525 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2526 } else {
2527 Label done;
2528 __ load_const_optimized(Rres, 0L); // false (failed)
2529 __ z_brne(done); // Assume true to be the common case.
2530 __ load_const_optimized(Rres, 1L); // true (succeed)
2531 __ bind(done);
2532 }
2533 %}
2534
2535 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2536 Register Rcomp = reg_to_register_object($compare_value$$reg);
2537 Register Rnew = reg_to_register_object($exchange_value$$reg);
2538 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2539
2540 __ z_cs(Rcomp, Rnew, 0, Raddr);
2541 %}
2542
2543 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2544 Register Rcomp = reg_to_register_object($compare_value$$reg);
2545 Register Rnew = reg_to_register_object($exchange_value$$reg);
2546 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2547
2548 __ z_csg(Rcomp, Rnew, 0, Raddr);
2549 %}
2550
2551 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2552 Register Rdst = reg_to_register_object($dst$$reg);
2553 Register Rtmp = reg_to_register_object($tmp$$reg);
2554 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2555 Label retry;
2556
2557 // Iterate until swap succeeds.
2558 __ z_llgf(Rtmp, $mem$$Address); // current contents
2559 __ bind(retry);
2560 // Calculate incremented value.
2561 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2562 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2563 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2564 %}
2565
2566 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2567 Register Rdst = reg_to_register_object($dst$$reg);
2568 Register Rtmp = reg_to_register_object($tmp$$reg);
2569 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2570 Label retry;
2571
2572 // Iterate until swap succeeds.
2573 __ z_lg(Rtmp, $mem$$Address); // current contents
2574 __ bind(retry);
2575 // Calculate incremented value.
2576 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2577 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2578 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2579 %}
2580
2581 %} // encode
2582
2583 source %{
2584
2585 // Check whether outs are all Stores. If so, we can omit clearing the upper
2586 // 32 bits after encoding.
2587 static bool all_outs_are_Stores(const Node *n) {
2588 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2589 Node *out = n->fast_out(k);
2590 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2591 // Most other outs are SpillCopy, but there are various other.
2592 // jvm98 has arond 9% Encodes where we return false.
2593 return false;
2594 }
2595 }
2596 return true;
2597 }
2598
2599 %} // source
2600
2601
2602 //----------FRAME--------------------------------------------------------------
2603 // Definition of frame structure and management information.
2604
2605 frame %{
2606 // These two registers define part of the calling convention between
2607 // compiled code and the interpreter.
2608
2609 // Inline Cache Register
2610 inline_cache_reg(Z_R9); // Z_inline_cache
2611
2612 // Argument pointer for I2C adapters
2613 //
2614 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2615 // interpreter_arg_ptr_reg(Z_R6);
2616
2617 // Optional: name the operand used by cisc-spilling to access
2618 // [stack_pointer + offset].
2619 cisc_spilling_operand_name(indOffset12);
2620
2621 // Number of stack slots consumed by a Monitor enter.
2622 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2623
2624 // Compiled code's Frame Pointer
2625 //
2626 // z/Architecture stack pointer
2627 frame_pointer(Z_R15); // Z_SP
2628
2629 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2630 stack_alignment(frame::alignment_in_bytes);
2631
2632 // A `slot' is assumed 4 bytes here!
2633 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2634
2635 // Number of outgoing stack slots killed above the
2636 // out_preserve_stack_slots for calls to C. Supports the var-args
2637 // backing area for register parms.
2638 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2639
2640 // The after-PROLOG location of the return address. Location of
2641 // return address specifies a type (REG or STACK) and a number
2642 // representing the register number (i.e. - use a register name) or
2643 // stack slot.
2644 return_addr(REG Z_R14);
2645
2646 // Use register pair for return value.
2647 // Location of compiled Java return values. Same as C
2648 return_value %{
2649 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2650 static const int lo[Op_RegL + 1] = {
2651 0,
2652 0,
2653 Z_R2_num, // Op_RegN
2654 Z_R2_num, // Op_RegI
2655 Z_R2_num, // Op_RegP
2656 Z_F0_num, // Op_RegF
2657 Z_F0_num, // Op_RegD
2658 Z_R2_num // Op_RegL
2659 };
2660 static const int hi[Op_RegL + 1] = {
2661 0,
2662 0,
2663 OptoReg::Bad, // Op_RegN
2664 OptoReg::Bad, // Op_RegI
2665 Z_R2_H_num, // Op_RegP
2666 OptoReg::Bad, // Op_RegF
2667 Z_F0_H_num, // Op_RegD
2668 Z_R2_H_num // Op_RegL
2669 };
2670 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2671 %}
2672 %}
2673
2674
2675 //----------ATTRIBUTES---------------------------------------------------------
2676
2677 //----------Operand Attributes-------------------------------------------------
2678 op_attrib op_cost(1); // Required cost attribute
2679
2680 //----------Instruction Attributes---------------------------------------------
2681
2682 // Cost attribute. required.
2683 ins_attrib ins_cost(DEFAULT_COST);
2684
2685 // Is this instruction a non-matching short branch variant of some
2686 // long branch? Not required.
2687 ins_attrib ins_short_branch(0);
2688
2689 // Indicates this is a trap based check node and final control-flow fixup
2690 // must generate a proper fall through.
2691 ins_attrib ins_is_TrapBasedCheckNode(true);
2692
2693 // Attribute of instruction to tell how many constants the instruction will generate.
2694 // (optional attribute). Default: 0.
2695 ins_attrib ins_num_consts(0);
2696
2697 // Required alignment attribute (must be a power of 2)
2698 // specifies the alignment that some part of the instruction (not
2699 // necessarily the start) requires. If > 1, a compute_padding()
2700 // function must be provided for the instruction.
2701 //
2702 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2703 // instructions which depend on the proper alignment, because the
2704 // desired alignment isn't guaranteed for the call to "emit()" during
2705 // the size computation.
2706 ins_attrib ins_alignment(1);
2707
2708 // Enforce/prohibit rematerializations.
2709 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2710 // then rematerialization of that instruction is prohibited and the
2711 // instruction's value will be spilled if necessary.
2712 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2713 // then rematerialization is enforced and the instruction's value will
2714 // never get spilled. a copy of the instruction will be inserted if
2715 // necessary.
2716 // Note: this may result in rematerializations in front of every use.
2717 // (optional attribute)
2718 ins_attrib ins_cannot_rematerialize(false);
2719 ins_attrib ins_should_rematerialize(false);
2720
2721 //----------OPERANDS-----------------------------------------------------------
2722 // Operand definitions must precede instruction definitions for correct
2723 // parsing in the ADLC because operands constitute user defined types
2724 // which are used in instruction definitions.
2725
2726 //----------Simple Operands----------------------------------------------------
2727 // Immediate Operands
2728 // Please note:
2729 // Formats are generated automatically for constants and base registers.
2730 operand vecX() %{
2731 constraint(ALLOC_IN_RC(z_v_reg));
2732 match(VecX);
2733 match(v16TempReg);
2734 match(v17TempReg);
2735 match(v18TempReg);
2736 match(v19TempReg);
2737 match(v20TempReg);
2738 match(v21TempReg);
2739 match(v22TempReg);
2740 match(v23TempReg);
2741 match(v24TempReg);
2742 match(v25TempReg);
2743 format %{ %}
2744 interface(REG_INTER);
2745 %}
2746
2747 operand v16TempReg() %{
2748 constraint(ALLOC_IN_RC(z_vreg_16));
2749 match(VecX);
2750 format %{ %}
2751 interface(REG_INTER);
2752 %}
2753
2754 operand v17TempReg() %{
2755 constraint(ALLOC_IN_RC(z_vreg_17));
2756 match(VecX);
2757 format %{ %}
2758 interface(REG_INTER);
2759 %}
2760
2761 operand v18TempReg() %{
2762 constraint(ALLOC_IN_RC(z_vreg_18));
2763 match(VecX);
2764 format %{ %}
2765 interface(REG_INTER);
2766 %}
2767
2768 operand v19TempReg() %{
2769 constraint(ALLOC_IN_RC(z_vreg_19));
2770 match(VecX);
2771 format %{ %}
2772 interface(REG_INTER);
2773 %}
2774
2775 operand v20TempReg() %{
2776 constraint(ALLOC_IN_RC(z_vreg_20));
2777 match(VecX);
2778 format %{ %}
2779 interface(REG_INTER);
2780 %}
2781
2782 operand v21TempReg() %{
2783 constraint(ALLOC_IN_RC(z_vreg_21));
2784 match(VecX);
2785 format %{ %}
2786 interface(REG_INTER);
2787 %}
2788
2789 operand v22TempReg() %{
2790 constraint(ALLOC_IN_RC(z_vreg_22));
2791 match(VecX);
2792 format %{ %}
2793 interface(REG_INTER);
2794 %}
2795
2796 operand v23TempReg() %{
2797 constraint(ALLOC_IN_RC(z_vreg_23));
2798 match(VecX);
2799 format %{ %}
2800 interface(REG_INTER);
2801 %}
2802
2803 operand v24TempReg() %{
2804 constraint(ALLOC_IN_RC(z_vreg_24));
2805 match(VecX);
2806 format %{ %}
2807 interface(REG_INTER);
2808 %}
2809
2810 operand v25TempReg() %{
2811 constraint(ALLOC_IN_RC(z_vreg_25));
2812 match(VecX);
2813 format %{ %}
2814 interface(REG_INTER);
2815 %}
2816
2817 //----------------------------------------------
2818 // SIGNED (shorter than INT) immediate operands
2819 //----------------------------------------------
2820
2821 // Byte Immediate: constant 'int -1'
2822 operand immB_minus1() %{
2823 // sign-ext constant zero-ext constant
2824 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2825 match(ConI);
2826 op_cost(1);
2827 format %{ %}
2828 interface(CONST_INTER);
2829 %}
2830
2831 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2832 operand immB_n0m1() %{
2833 // sign-ext constant zero-ext constant
2834 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2835 match(ConI);
2836 op_cost(1);
2837 format %{ %}
2838 interface(CONST_INTER);
2839 %}
2840
2841 // Short Immediate: constant 'int -1'
2842 operand immS_minus1() %{
2843 // sign-ext constant zero-ext constant
2844 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2845 match(ConI);
2846 op_cost(1);
2847 format %{ %}
2848 interface(CONST_INTER);
2849 %}
2850
2851 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2852 operand immS_n0m1() %{
2853 // sign-ext constant zero-ext constant
2854 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2855 match(ConI);
2856 op_cost(1);
2857 format %{ %}
2858 interface(CONST_INTER);
2859 %}
2860
2861 //-----------------------------------------
2862 // SIGNED INT immediate operands
2863 //-----------------------------------------
2864
2865 // Integer Immediate: 32-bit
2866 operand immI() %{
2867 match(ConI);
2868 op_cost(1);
2869 format %{ %}
2870 interface(CONST_INTER);
2871 %}
2872
2873 // Int Immediate: 20-bit
2874 operand immI20() %{
2875 predicate(Immediate::is_simm20(n->get_int()));
2876 match(ConI);
2877 op_cost(1);
2878 format %{ %}
2879 interface(CONST_INTER);
2880 %}
2881
2882 // Integer Immediate: 16-bit
2883 operand immI16() %{
2884 predicate(Immediate::is_simm16(n->get_int()));
2885 match(ConI);
2886 op_cost(1);
2887 format %{ %}
2888 interface(CONST_INTER);
2889 %}
2890
2891 // Integer Immediate: 8-bit
2892 operand immI8() %{
2893 predicate(Immediate::is_simm8(n->get_int()));
2894 match(ConI);
2895 op_cost(1);
2896 format %{ %}
2897 interface(CONST_INTER);
2898 %}
2899
2900 // Integer Immediate: constant 'int 0'
2901 operand immI_0() %{
2902 predicate(n->get_int() == 0);
2903 match(ConI);
2904 op_cost(1);
2905 format %{ %}
2906 interface(CONST_INTER);
2907 %}
2908
2909 // Integer Immediate: constant 'int -1'
2910 operand immI_minus1() %{
2911 predicate(n->get_int() == -1);
2912 match(ConI);
2913 op_cost(1);
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2919 operand immI_n0m1() %{
2920 predicate(n->get_int() != 0 && n->get_int() != -1);
2921 match(ConI);
2922 op_cost(1);
2923 format %{ %}
2924 interface(CONST_INTER);
2925 %}
2926
2927 //-------------------------------------------
2928 // UNSIGNED INT immediate operands
2929 //-------------------------------------------
2930
2931 // Unsigned Integer Immediate: 32-bit
2932 operand uimmI() %{
2933 match(ConI);
2934 op_cost(1);
2935 format %{ %}
2936 interface(CONST_INTER);
2937 %}
2938
2939 // Unsigned Integer Immediate: 16-bit
2940 operand uimmI16() %{
2941 predicate(Immediate::is_uimm16(n->get_int()));
2942 match(ConI);
2943 op_cost(1);
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 // Unsigned Integer Immediate: 12-bit
2949 operand uimmI12() %{
2950 predicate(Immediate::is_uimm12(n->get_int()));
2951 match(ConI);
2952 op_cost(1);
2953 format %{ %}
2954 interface(CONST_INTER);
2955 %}
2956
2957 // Unsigned Integer Immediate: 12-bit
2958 operand uimmI8() %{
2959 predicate(Immediate::is_uimm8(n->get_int()));
2960 match(ConI);
2961 op_cost(1);
2962 format %{ %}
2963 interface(CONST_INTER);
2964 %}
2965
2966 // Length for SS instructions, given in DWs,
2967 // possible range [1..512], i.e. [8..4096] Bytes
2968 // used range [1..256], i.e. [8..2048] Bytes
2969 // operand type int
2970 // Unsigned Integer Immediate: 9-bit
2971 operand SSlenDW() %{
2972 predicate(Immediate::is_uimm8((julong)n->get_long()-1));
2973 match(ConL);
2974 op_cost(1);
2975 format %{ %}
2976 interface(CONST_INTER);
2977 %}
2978
2979 //------------------------------------------
2980 // (UN)SIGNED INT specific values
2981 //------------------------------------------
2982
2983 // Integer Immediate: the value 1
2984 operand immI_1() %{
2985 predicate(n->get_int() == 1);
2986 match(ConI);
2987 op_cost(1);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Integer Immediate: the value 16.
2993 operand immI_16() %{
2994 predicate(n->get_int() == 16);
2995 match(ConI);
2996 op_cost(1);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 // Integer Immediate: the value 24.
3002 operand immI_24() %{
3003 predicate(n->get_int() == 24);
3004 match(ConI);
3005 op_cost(1);
3006 format %{ %}
3007 interface(CONST_INTER);
3008 %}
3009
3010 // Integer Immediate: the values 32-63
3011 operand immI_32_63() %{
3012 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3013 match(ConI);
3014 op_cost(1);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 // Unsigned Integer Immediate: LL-part, extended by 1s.
3020 operand uimmI_LL1() %{
3021 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
3022 match(ConI);
3023 op_cost(1);
3024 format %{ %}
3025 interface(CONST_INTER);
3026 %}
3027
3028 // Unsigned Integer Immediate: LH-part, extended by 1s.
3029 operand uimmI_LH1() %{
3030 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
3031 match(ConI);
3032 op_cost(1);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 //------------------------------------------
3038 // SIGNED LONG immediate operands
3039 //------------------------------------------
3040
3041 operand immL() %{
3042 match(ConL);
3043 op_cost(1);
3044 format %{ %}
3045 interface(CONST_INTER);
3046 %}
3047
3048 // Long Immediate: 32-bit
3049 operand immL32() %{
3050 predicate(Immediate::is_simm32(n->get_long()));
3051 match(ConL);
3052 op_cost(1);
3053 format %{ %}
3054 interface(CONST_INTER);
3055 %}
3056
3057 // Long Immediate: 20-bit
3058 operand immL20() %{
3059 predicate(Immediate::is_simm20(n->get_long()));
3060 match(ConL);
3061 op_cost(1);
3062 format %{ %}
3063 interface(CONST_INTER);
3064 %}
3065
3066 // Long Immediate: 16-bit
3067 operand immL16() %{
3068 predicate(Immediate::is_simm16(n->get_long()));
3069 match(ConL);
3070 op_cost(1);
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075 // Long Immediate: 8-bit
3076 operand immL8() %{
3077 predicate(Immediate::is_simm8(n->get_long()));
3078 match(ConL);
3079 op_cost(1);
3080 format %{ %}
3081 interface(CONST_INTER);
3082 %}
3083
3084 //--------------------------------------------
3085 // UNSIGNED LONG immediate operands
3086 //--------------------------------------------
3087
3088 operand uimmL32() %{
3089 predicate(Immediate::is_uimm32(n->get_long()));
3090 match(ConL);
3091 op_cost(1);
3092 format %{ %}
3093 interface(CONST_INTER);
3094 %}
3095
3096 // Unsigned Long Immediate: 16-bit
3097 operand uimmL16() %{
3098 predicate(Immediate::is_uimm16(n->get_long()));
3099 match(ConL);
3100 op_cost(1);
3101 format %{ %}
3102 interface(CONST_INTER);
3103 %}
3104
3105 // Unsigned Long Immediate: 12-bit
3106 operand uimmL12() %{
3107 predicate(Immediate::is_uimm12(n->get_long()));
3108 match(ConL);
3109 op_cost(1);
3110 format %{ %}
3111 interface(CONST_INTER);
3112 %}
3113
3114 //-------------------------------------------
3115 // (UN)SIGNED LONG specific values
3116 //-------------------------------------------
3117
3118 // Long Immediate: the value FFFFFFFF
3119 operand immL_FFFFFFFF() %{
3120 predicate(n->get_long() == 0xFFFFFFFFL);
3121 match(ConL);
3122 op_cost(1);
3123 format %{ %}
3124 interface(CONST_INTER);
3125 %}
3126
3127 operand immL_0() %{
3128 predicate(n->get_long() == 0L);
3129 match(ConL);
3130 op_cost(1);
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Unsigned Long Immediate: LL-part, extended by 1s.
3136 operand uimmL_LL1() %{
3137 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
3138 match(ConL);
3139 op_cost(1);
3140 format %{ %}
3141 interface(CONST_INTER);
3142 %}
3143
3144 // Unsigned Long Immediate: LH-part, extended by 1s.
3145 operand uimmL_LH1() %{
3146 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
3147 match(ConL);
3148 op_cost(1);
3149 format %{ %}
3150 interface(CONST_INTER);
3151 %}
3152
3153 // Unsigned Long Immediate: HL-part, extended by 1s.
3154 operand uimmL_HL1() %{
3155 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
3156 match(ConL);
3157 op_cost(1);
3158 format %{ %}
3159 interface(CONST_INTER);
3160 %}
3161
3162 // Unsigned Long Immediate: HH-part, extended by 1s.
3163 operand uimmL_HH1() %{
3164 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
3165 match(ConL);
3166 op_cost(1);
3167 format %{ %}
3168 interface(CONST_INTER);
3169 %}
3170
3171 // Long Immediate: low 32-bit mask
3172 operand immL_32bits() %{
3173 predicate(n->get_long() == 0xFFFFFFFFL);
3174 match(ConL);
3175 op_cost(1);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 //--------------------------------------
3181 // POINTER immediate operands
3182 //--------------------------------------
3183
3184 // Pointer Immediate: 64-bit
3185 operand immP() %{
3186 match(ConP);
3187 op_cost(1);
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 // Pointer Immediate: 16-bit
3193 operand immP16() %{
3194 predicate(Immediate::is_uimm16(n->get_ptr()));
3195 match(ConP);
3196 op_cost(1);
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Pointer Immediate: 8-bit
3202 operand immP8() %{
3203 predicate(Immediate::is_uimm8(n->get_ptr()));
3204 match(ConP);
3205 op_cost(1);
3206 format %{ %}
3207 interface(CONST_INTER);
3208 %}
3209
3210 //-----------------------------------
3211 // POINTER specific values
3212 //-----------------------------------
3213
3214 // Pointer Immediate: nullptr
3215 operand immP0() %{
3216 predicate(n->get_ptr() == 0);
3217 match(ConP);
3218 op_cost(1);
3219 format %{ %}
3220 interface(CONST_INTER);
3221 %}
3222
3223 //---------------------------------------------
3224 // NARROW POINTER immediate operands
3225 //---------------------------------------------
3226
3227 // Narrow Pointer Immediate
3228 operand immN() %{
3229 match(ConN);
3230 op_cost(1);
3231 format %{ %}
3232 interface(CONST_INTER);
3233 %}
3234
3235 operand immNKlass() %{
3236 match(ConNKlass);
3237 op_cost(1);
3238 format %{ %}
3239 interface(CONST_INTER);
3240 %}
3241
3242 // Narrow Pointer Immediate
3243 operand immN8() %{
3244 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3245 match(ConN);
3246 op_cost(1);
3247 format %{ %}
3248 interface(CONST_INTER);
3249 %}
3250
3251 // Narrow Null Pointer Immediate
3252 operand immN0() %{
3253 predicate(n->get_narrowcon() == 0);
3254 match(ConN);
3255 op_cost(1);
3256 format %{ %}
3257 interface(CONST_INTER);
3258 %}
3259
3260 // FLOAT and DOUBLE immediate operands
3261
3262 // Double Immediate
3263 operand immD() %{
3264 match(ConD);
3265 op_cost(1);
3266 format %{ %}
3267 interface(CONST_INTER);
3268 %}
3269
3270 // Double Immediate: +-0
3271 operand immDpm0() %{
3272 predicate(n->getd() == 0);
3273 match(ConD);
3274 op_cost(1);
3275 format %{ %}
3276 interface(CONST_INTER);
3277 %}
3278
3279 // Double Immediate: +0
3280 operand immDp0() %{
3281 predicate(jlong_cast(n->getd()) == 0);
3282 match(ConD);
3283 op_cost(1);
3284 format %{ %}
3285 interface(CONST_INTER);
3286 %}
3287
3288 // Float Immediate
3289 operand immF() %{
3290 match(ConF);
3291 op_cost(1);
3292 format %{ %}
3293 interface(CONST_INTER);
3294 %}
3295
3296 // Float Immediate: +-0
3297 operand immFpm0() %{
3298 predicate(n->getf() == 0);
3299 match(ConF);
3300 op_cost(1);
3301 format %{ %}
3302 interface(CONST_INTER);
3303 %}
3304
3305 // Float Immediate: +0
3306 operand immFp0() %{
3307 predicate(jint_cast(n->getf()) == 0);
3308 match(ConF);
3309 op_cost(1);
3310 format %{ %}
3311 interface(CONST_INTER);
3312 %}
3313
3314 // End of Immediate Operands
3315
3316 // Integer Register Operands
3317 // Integer Register
3318 operand iRegI() %{
3319 constraint(ALLOC_IN_RC(z_int_reg));
3320 match(RegI);
3321 match(noArg_iRegI);
3322 match(rarg1RegI);
3323 match(rarg2RegI);
3324 match(rarg3RegI);
3325 match(rarg4RegI);
3326 match(rarg5RegI);
3327 match(noOdd_iRegI);
3328 match(revenRegI);
3329 match(roddRegI);
3330 format %{ %}
3331 interface(REG_INTER);
3332 %}
3333
3334 operand noArg_iRegI() %{
3335 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3336 match(RegI);
3337 format %{ %}
3338 interface(REG_INTER);
3339 %}
3340
3341 // revenRegI and roddRegI constitute and even-odd-pair.
3342 operand revenRegI() %{
3343 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3344 match(iRegI);
3345 format %{ %}
3346 interface(REG_INTER);
3347 %}
3348
3349 // revenRegI and roddRegI constitute and even-odd-pair.
3350 operand roddRegI() %{
3351 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3352 match(iRegI);
3353 format %{ %}
3354 interface(REG_INTER);
3355 %}
3356
3357 operand rarg1RegI() %{
3358 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3359 match(iRegI);
3360 format %{ %}
3361 interface(REG_INTER);
3362 %}
3363
3364 operand rarg2RegI() %{
3365 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3366 match(iRegI);
3367 format %{ %}
3368 interface(REG_INTER);
3369 %}
3370
3371 operand rarg3RegI() %{
3372 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3373 match(iRegI);
3374 format %{ %}
3375 interface(REG_INTER);
3376 %}
3377
3378 operand rarg4RegI() %{
3379 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3380 match(iRegI);
3381 format %{ %}
3382 interface(REG_INTER);
3383 %}
3384
3385 operand rarg5RegI() %{
3386 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3387 match(iRegI);
3388 format %{ %}
3389 interface(REG_INTER);
3390 %}
3391
3392 operand noOdd_iRegI() %{
3393 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3394 match(RegI);
3395 match(revenRegI);
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // Pointer Register
3401 operand iRegP() %{
3402 constraint(ALLOC_IN_RC(z_ptr_reg));
3403 match(RegP);
3404 match(noArg_iRegP);
3405 match(rarg1RegP);
3406 match(rarg2RegP);
3407 match(rarg3RegP);
3408 match(rarg4RegP);
3409 match(rarg5RegP);
3410 match(revenRegP);
3411 match(roddRegP);
3412 match(r10TempRegP);
3413 match(r11TempRegP);
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 // thread operand
3419 operand threadRegP() %{
3420 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3421 match(RegP);
3422 format %{ "Z_THREAD" %}
3423 interface(REG_INTER);
3424 %}
3425
3426 operand r10TempRegP() %{
3427 constraint(ALLOC_IN_RC(z_r10_ptr_reg));
3428 match(iRegP);
3429 format %{ %}
3430 interface(REG_INTER);
3431 %}
3432
3433 operand r11TempRegP() %{
3434 constraint(ALLOC_IN_RC(z_r11_ptr_reg));
3435 match(iRegP);
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 operand noArg_iRegP() %{
3441 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3442 match(iRegP);
3443 format %{ %}
3444 interface(REG_INTER);
3445 %}
3446
3447 operand rarg1RegP() %{
3448 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3449 match(iRegP);
3450 format %{ %}
3451 interface(REG_INTER);
3452 %}
3453
3454 operand rarg2RegP() %{
3455 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3456 match(iRegP);
3457 format %{ %}
3458 interface(REG_INTER);
3459 %}
3460
3461 operand rarg3RegP() %{
3462 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3463 match(iRegP);
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 operand rarg4RegP() %{
3469 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3470 match(iRegP);
3471 format %{ %}
3472 interface(REG_INTER);
3473 %}
3474
3475 operand rarg5RegP() %{
3476 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3477 match(iRegP);
3478 format %{ %}
3479 interface(REG_INTER);
3480 %}
3481
3482 operand memoryRegP() %{
3483 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3484 match(RegP);
3485 match(iRegP);
3486 match(threadRegP);
3487 format %{ %}
3488 interface(REG_INTER);
3489 %}
3490
3491 // revenRegP and roddRegP constitute and even-odd-pair.
3492 operand revenRegP() %{
3493 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3494 match(iRegP);
3495 format %{ %}
3496 interface(REG_INTER);
3497 %}
3498
3499 // revenRegP and roddRegP constitute and even-odd-pair.
3500 operand roddRegP() %{
3501 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3502 match(iRegP);
3503 format %{ %}
3504 interface(REG_INTER);
3505 %}
3506
3507 operand iRegN() %{
3508 constraint(ALLOC_IN_RC(z_int_reg));
3509 match(RegN);
3510 match(noArg_iRegN);
3511 match(rarg1RegN);
3512 match(rarg2RegN);
3513 match(rarg3RegN);
3514 match(rarg4RegN);
3515 match(rarg5RegN);
3516 format %{ %}
3517 interface(REG_INTER);
3518 %}
3519
3520 operand noArg_iRegN() %{
3521 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3522 match(iRegN);
3523 format %{ %}
3524 interface(REG_INTER);
3525 %}
3526
3527 operand rarg1RegN() %{
3528 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3529 match(iRegN);
3530 format %{ %}
3531 interface(REG_INTER);
3532 %}
3533
3534 operand rarg2RegN() %{
3535 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3536 match(iRegN);
3537 format %{ %}
3538 interface(REG_INTER);
3539 %}
3540
3541 operand rarg3RegN() %{
3542 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3543 match(iRegN);
3544 format %{ %}
3545 interface(REG_INTER);
3546 %}
3547
3548 operand rarg4RegN() %{
3549 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3550 match(iRegN);
3551 format %{ %}
3552 interface(REG_INTER);
3553 %}
3554
3555 operand rarg5RegN() %{
3556 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3557 match(iRegN);
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 // Long Register
3563 operand iRegL() %{
3564 constraint(ALLOC_IN_RC(z_long_reg));
3565 match(RegL);
3566 match(revenRegL);
3567 match(roddRegL);
3568 match(allRoddRegL);
3569 match(rarg1RegL);
3570 match(rarg5RegL);
3571 format %{ %}
3572 interface(REG_INTER);
3573 %}
3574
3575 // revenRegL and roddRegL constitute and even-odd-pair.
3576 operand revenRegL() %{
3577 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3578 match(iRegL);
3579 format %{ %}
3580 interface(REG_INTER);
3581 %}
3582
3583 // revenRegL and roddRegL constitute and even-odd-pair.
3584 operand roddRegL() %{
3585 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3586 match(iRegL);
3587 format %{ %}
3588 interface(REG_INTER);
3589 %}
3590
3591 // available odd registers for iRegL
3592 operand allRoddRegL() %{
3593 constraint(ALLOC_IN_RC(z_long_odd_reg));
3594 match(iRegL);
3595 format %{ %}
3596 interface(REG_INTER);
3597 %}
3598
3599 operand rarg1RegL() %{
3600 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3601 match(iRegL);
3602 format %{ %}
3603 interface(REG_INTER);
3604 %}
3605
3606 operand rarg5RegL() %{
3607 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3608 match(iRegL);
3609 format %{ %}
3610 interface(REG_INTER);
3611 %}
3612
3613 // Condition Code Flag Registers
3614 operand flagsReg() %{
3615 constraint(ALLOC_IN_RC(z_condition_reg));
3616 match(RegFlags);
3617 format %{ "CR" %}
3618 interface(REG_INTER);
3619 %}
3620
3621 operand regD() %{
3622 constraint(ALLOC_IN_RC(z_dbl_reg));
3623 match(RegD);
3624 format %{ %}
3625 interface(REG_INTER);
3626 %}
3627
3628 operand regF() %{
3629 constraint(ALLOC_IN_RC(z_flt_reg));
3630 match(RegF);
3631 format %{ %}
3632 interface(REG_INTER);
3633 %}
3634
3635 // Special Registers
3636
3637 // Method Register
3638 operand inline_cache_regP(iRegP reg) %{
3639 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3640 match(reg);
3641 format %{ %}
3642 interface(REG_INTER);
3643 %}
3644
3645 //----------Complex Operands---------------------------------------------------
3646
3647 // Indirect Memory Reference
3648 operand indirect(memoryRegP base) %{
3649 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3650 match(base);
3651 op_cost(1);
3652 format %{ "#0[,$base]" %}
3653 interface(MEMORY_INTER) %{
3654 base($base);
3655 index(0xffffFFFF); // noreg
3656 scale(0x0);
3657 disp(0x0);
3658 %}
3659 %}
3660
3661 // Indirect with Offset (long)
3662 operand indOffset20(memoryRegP base, immL20 offset) %{
3663 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3664 match(AddP base offset);
3665 op_cost(1);
3666 format %{ "$offset[,$base]" %}
3667 interface(MEMORY_INTER) %{
3668 base($base);
3669 index(0xffffFFFF); // noreg
3670 scale(0x0);
3671 disp($offset);
3672 %}
3673 %}
3674
3675 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3676 predicate(Matcher::narrow_oop_use_complex_address());
3677 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3678 match(AddP (DecodeN base) offset);
3679 op_cost(1);
3680 format %{ "$offset[,$base]" %}
3681 interface(MEMORY_INTER) %{
3682 base($base);
3683 index(0xffffFFFF); // noreg
3684 scale(0x0);
3685 disp($offset);
3686 %}
3687 %}
3688
3689 // Indirect with Offset (short)
3690 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3691 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3692 match(AddP base offset);
3693 op_cost(1);
3694 format %{ "$offset[[,$base]]" %}
3695 interface(MEMORY_INTER) %{
3696 base($base);
3697 index(0xffffFFFF); // noreg
3698 scale(0x0);
3699 disp($offset);
3700 %}
3701 %}
3702
3703 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3704 predicate(Matcher::narrow_oop_use_complex_address());
3705 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3706 match(AddP (DecodeN base) offset);
3707 op_cost(1);
3708 format %{ "$offset[[,$base]]" %}
3709 interface(MEMORY_INTER) %{
3710 base($base);
3711 index(0xffffFFFF); // noreg
3712 scale(0x0);
3713 disp($offset);
3714 %}
3715 %}
3716
3717 // Indirect with Register Index
3718 operand indIndex(memoryRegP base, iRegL index) %{
3719 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3720 match(AddP base index);
3721 op_cost(1);
3722 format %{ "#0[($index,$base)]" %}
3723 interface(MEMORY_INTER) %{
3724 base($base);
3725 index($index);
3726 scale(0x0);
3727 disp(0x0);
3728 %}
3729 %}
3730
3731 // Indirect with Offset (long) and index
3732 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3733 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3734 match(AddP (AddP base index) offset);
3735 op_cost(1);
3736 format %{ "$offset[($index,$base)]" %}
3737 interface(MEMORY_INTER) %{
3738 base($base);
3739 index($index);
3740 scale(0x0);
3741 disp($offset);
3742 %}
3743 %}
3744
3745 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3746 predicate(Matcher::narrow_oop_use_complex_address());
3747 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3748 match(AddP (AddP (DecodeN base) index) offset);
3749 op_cost(1);
3750 format %{ "$offset[($index,$base)]" %}
3751 interface(MEMORY_INTER) %{
3752 base($base);
3753 index($index);
3754 scale(0x0);
3755 disp($offset);
3756 %}
3757 %}
3758
3759 // Indirect with Offset (short) and index
3760 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3761 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3762 match(AddP (AddP base index) offset);
3763 op_cost(1);
3764 format %{ "$offset[[($index,$base)]]" %}
3765 interface(MEMORY_INTER) %{
3766 base($base);
3767 index($index);
3768 scale(0x0);
3769 disp($offset);
3770 %}
3771 %}
3772
3773 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3774 predicate(Matcher::narrow_oop_use_complex_address());
3775 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3776 match(AddP (AddP (DecodeN base) index) offset);
3777 op_cost(1);
3778 format %{ "$offset[[($index,$base)]]" %}
3779 interface(MEMORY_INTER) %{
3780 base($base);
3781 index($index);
3782 scale(0x0);
3783 disp($offset);
3784 %}
3785 %}
3786
3787 //----------Special Memory Operands--------------------------------------------
3788
3789 // Stack Slot Operand
3790 // This operand is used for loading and storing temporary values on
3791 // the stack where a match requires a value to flow through memory.
3792 operand stackSlotI(sRegI reg) %{
3793 constraint(ALLOC_IN_RC(stack_slots));
3794 op_cost(1);
3795 format %{ "[$reg(stackSlotI)]" %}
3796 interface(MEMORY_INTER) %{
3797 base(0xf); // Z_SP
3798 index(0xffffFFFF); // noreg
3799 scale(0x0);
3800 disp($reg); // stack offset
3801 %}
3802 %}
3803
3804 operand stackSlotP(sRegP reg) %{
3805 constraint(ALLOC_IN_RC(stack_slots));
3806 op_cost(1);
3807 format %{ "[$reg(stackSlotP)]" %}
3808 interface(MEMORY_INTER) %{
3809 base(0xf); // Z_SP
3810 index(0xffffFFFF); // noreg
3811 scale(0x0);
3812 disp($reg); // Stack Offset
3813 %}
3814 %}
3815
3816 operand stackSlotF(sRegF reg) %{
3817 constraint(ALLOC_IN_RC(stack_slots));
3818 op_cost(1);
3819 format %{ "[$reg(stackSlotF)]" %}
3820 interface(MEMORY_INTER) %{
3821 base(0xf); // Z_SP
3822 index(0xffffFFFF); // noreg
3823 scale(0x0);
3824 disp($reg); // Stack Offset
3825 %}
3826 %}
3827
3828 operand stackSlotD(sRegD reg) %{
3829 constraint(ALLOC_IN_RC(stack_slots));
3830 op_cost(1);
3831 //match(RegD);
3832 format %{ "[$reg(stackSlotD)]" %}
3833 interface(MEMORY_INTER) %{
3834 base(0xf); // Z_SP
3835 index(0xffffFFFF); // noreg
3836 scale(0x0);
3837 disp($reg); // Stack Offset
3838 %}
3839 %}
3840
3841 operand stackSlotL(sRegL reg) %{
3842 constraint(ALLOC_IN_RC(stack_slots));
3843 op_cost(1); //match(RegL);
3844 format %{ "[$reg(stackSlotL)]" %}
3845 interface(MEMORY_INTER) %{
3846 base(0xf); // Z_SP
3847 index(0xffffFFFF); // noreg
3848 scale(0x0);
3849 disp($reg); // Stack Offset
3850 %}
3851 %}
3852
3853 // Operands for expressing Control Flow
3854 // NOTE: Label is a predefined operand which should not be redefined in
3855 // the AD file. It is generically handled within the ADLC.
3856
3857 //----------Conditional Branch Operands----------------------------------------
3858 // Comparison Op - This is the operation of the comparison, and is limited to
3859 // the following set of codes:
3860 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3861 //
3862 // Other attributes of the comparison, such as unsignedness, are specified
3863 // by the comparison instruction that sets a condition code flags register.
3864 // That result is represented by a flags operand whose subtype is appropriate
3865 // to the unsignedness (etc.) of the comparison.
3866 //
3867 // Later, the instruction which matches both the Comparison Op (a Bool) and
3868 // the flags (produced by the Cmp) specifies the coding of the comparison op
3869 // by matching a specific subtype of Bool operand below.
3870
3871 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3872 // have mask bit #3 set.
3873 operand cmpOpT() %{
3874 match(Bool);
3875 format %{ "" %}
3876 interface(COND_INTER) %{
3877 equal(0x8); // Assembler::bcondEqual
3878 not_equal(0x6); // Assembler::bcondNotEqual
3879 less(0x4); // Assembler::bcondLow
3880 greater_equal(0xa); // Assembler::bcondNotLow
3881 less_equal(0xc); // Assembler::bcondNotHigh
3882 greater(0x2); // Assembler::bcondHigh
3883 overflow(0x1); // Assembler::bcondOverflow
3884 no_overflow(0xe); // Assembler::bcondNotOverflow
3885 %}
3886 %}
3887
3888 // When used for floating point comparisons: unordered is treated as less.
3889 operand cmpOpF() %{
3890 match(Bool);
3891 format %{ "" %}
3892 interface(COND_INTER) %{
3893 equal(0x8);
3894 not_equal(0x7); // Includes 'unordered'.
3895 less(0x5); // Includes 'unordered'.
3896 greater_equal(0xa);
3897 less_equal(0xd); // Includes 'unordered'.
3898 greater(0x2);
3899 overflow(0x0); // Not meaningful on z/Architecture.
3900 no_overflow(0x0); // leave unchanged (zero) therefore
3901 %}
3902 %}
3903
3904 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3905 operand cmpOp() %{
3906 match(Bool);
3907 format %{ "" %}
3908 interface(COND_INTER) %{
3909 equal(0x8);
3910 not_equal(0x7); // Includes 'unordered'.
3911 less(0x5); // Includes 'unordered'.
3912 greater_equal(0xa);
3913 less_equal(0xd); // Includes 'unordered'.
3914 greater(0x2);
3915 overflow(0x1); // Assembler::bcondOverflow
3916 no_overflow(0xe); // Assembler::bcondNotOverflow
3917 %}
3918 %}
3919
3920 //----------OPERAND CLASSES----------------------------------------------------
3921 // Operand Classes are groups of operands that are used to simplify
3922 // instruction definitions by not requiring the AD writer to specify
3923 // separate instructions for every form of operand when the
3924 // instruction accepts multiple operand types with the same basic
3925 // encoding and format. The classic case of this is memory operands.
3926 // Indirect is not included since its use is limited to Compare & Swap
3927
3928 // Most general memory operand, allows base, index, and long displacement.
3929 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3930 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3931
3932 // General memory operand, allows base, index, and short displacement.
3933 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3934
3935 // Memory operand, allows only base and long displacement.
3936 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3937
3938 // Memory operand, allows only base and short displacement.
3939 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3940
3941 // Operand classes to match encode and decode.
3942 opclass iRegN_P2N(iRegN);
3943 opclass iRegP_N2P(iRegP);
3944
3945
3946 //----------PIPELINE-----------------------------------------------------------
3947 pipeline %{
3948
3949 //----------ATTRIBUTES---------------------------------------------------------
3950 attributes %{
3951 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3952 variable_size_instructions;
3953 instruction_unit_size = 2;
3954
3955 // Meaningless on z/Architecture.
3956 max_instructions_per_bundle = 1;
3957
3958 // The z/Architecture processor fetches 64 bytes...
3959 instruction_fetch_unit_size = 64;
3960
3961 // ...in one line.
3962 instruction_fetch_units = 1
3963 %}
3964
3965 //----------RESOURCES----------------------------------------------------------
3966 // Resources are the functional units available to the machine.
3967 resources(
3968 Z_BR, // branch unit
3969 Z_CR, // condition unit
3970 Z_FX1, // integer arithmetic unit 1
3971 Z_FX2, // integer arithmetic unit 2
3972 Z_LDST1, // load/store unit 1
3973 Z_LDST2, // load/store unit 2
3974 Z_FP1, // float arithmetic unit 1
3975 Z_FP2, // float arithmetic unit 2
3976 Z_LDST = Z_LDST1 | Z_LDST2,
3977 Z_FX = Z_FX1 | Z_FX2,
3978 Z_FP = Z_FP1 | Z_FP2
3979 );
3980
3981 //----------PIPELINE DESCRIPTION-----------------------------------------------
3982 // Pipeline Description specifies the stages in the machine's pipeline.
3983 pipe_desc(
3984 // TODO: adapt
3985 Z_IF, // instruction fetch
3986 Z_IC,
3987 Z_D0, // decode
3988 Z_D1, // decode
3989 Z_D2, // decode
3990 Z_D3, // decode
3991 Z_Xfer1,
3992 Z_GD, // group definition
3993 Z_MP, // map
3994 Z_ISS, // issue
3995 Z_RF, // resource fetch
3996 Z_EX1, // execute (all units)
3997 Z_EX2, // execute (FP, LDST)
3998 Z_EX3, // execute (FP, LDST)
3999 Z_EX4, // execute (FP)
4000 Z_EX5, // execute (FP)
4001 Z_EX6, // execute (FP)
4002 Z_WB, // write back
4003 Z_Xfer2,
4004 Z_CP
4005 );
4006
4007 //----------PIPELINE CLASSES---------------------------------------------------
4008 // Pipeline Classes describe the stages in which input and output are
4009 // referenced by the hardware pipeline.
4010
4011 // Providing the `ins_pipe' declarations in the instruction
4012 // specifications seems to be of little use. So we use
4013 // `pipe_class_dummy' for all our instructions at present.
4014 pipe_class pipe_class_dummy() %{
4015 single_instruction;
4016 fixed_latency(4);
4017 %}
4018
4019 // SIGTRAP based implicit range checks in compiled code.
4020 // Currently, no pipe classes are used on z/Architecture.
4021 pipe_class pipe_class_trap() %{
4022 single_instruction;
4023 %}
4024
4025 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4026 single_instruction;
4027 dst : Z_EX1(write);
4028 src1 : Z_RF(read);
4029 src2 : Z_RF(read);
4030 Z_FX : Z_RF;
4031 %}
4032
4033 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
4034 single_instruction;
4035 mem : Z_RF(read);
4036 dst : Z_WB(write);
4037 Z_LDST : Z_RF;
4038 %}
4039
4040 define %{
4041 MachNop = pipe_class_dummy;
4042 %}
4043
4044 %}
4045
4046 //----------INSTRUCTIONS-------------------------------------------------------
4047
4048 //---------- Chain stack slots between similar types --------
4049
4050 // Load integer from stack slot.
4051 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
4052 match(Set dst src);
4053 ins_cost(MEMORY_REF_COST);
4054 // TODO: s390 port size(FIXED_SIZE);
4055 format %{ "L $dst,$src\t # stk reload int" %}
4056 opcode(L_ZOPC);
4057 ins_encode(z_form_rt_mem(dst, src));
4058 ins_pipe(pipe_class_dummy);
4059 %}
4060
4061 // Store integer to stack slot.
4062 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
4063 match(Set dst src);
4064 ins_cost(MEMORY_REF_COST);
4065 // TODO: s390 port size(FIXED_SIZE);
4066 format %{ "ST $src,$dst\t # stk spill int" %}
4067 opcode(ST_ZOPC);
4068 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4069 ins_pipe(pipe_class_dummy);
4070 %}
4071
4072 // Load long from stack slot.
4073 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
4074 match(Set dst src);
4075 ins_cost(MEMORY_REF_COST);
4076 // TODO: s390 port size(FIXED_SIZE);
4077 format %{ "LG $dst,$src\t # stk reload long" %}
4078 opcode(LG_ZOPC);
4079 ins_encode(z_form_rt_mem(dst, src));
4080 ins_pipe(pipe_class_dummy);
4081 %}
4082
4083 // Store long to stack slot.
4084 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
4085 match(Set dst src);
4086 ins_cost(MEMORY_REF_COST);
4087 size(6);
4088 format %{ "STG $src,$dst\t # stk spill long" %}
4089 opcode(STG_ZOPC);
4090 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4091 ins_pipe(pipe_class_dummy);
4092 %}
4093
4094 // Load pointer from stack slot, 64-bit encoding.
4095 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
4096 match(Set dst src);
4097 ins_cost(MEMORY_REF_COST);
4098 // TODO: s390 port size(FIXED_SIZE);
4099 format %{ "LG $dst,$src\t # stk reload ptr" %}
4100 opcode(LG_ZOPC);
4101 ins_encode(z_form_rt_mem(dst, src));
4102 ins_pipe(pipe_class_dummy);
4103 %}
4104
4105 // Store pointer to stack slot.
4106 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
4107 match(Set dst src);
4108 ins_cost(MEMORY_REF_COST);
4109 // TODO: s390 port size(FIXED_SIZE);
4110 format %{ "STG $src,$dst\t # stk spill ptr" %}
4111 opcode(STG_ZOPC);
4112 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4113 ins_pipe(pipe_class_dummy);
4114 %}
4115
4116 // Float types
4117
4118 // Load float value from stack slot.
4119 instruct stkF_to_regF(regF dst, stackSlotF src) %{
4120 match(Set dst src);
4121 ins_cost(MEMORY_REF_COST);
4122 size(4);
4123 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
4124 opcode(LE_ZOPC);
4125 ins_encode(z_form_rt_mem(dst, src));
4126 ins_pipe(pipe_class_dummy);
4127 %}
4128
4129 // Store float value to stack slot.
4130 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4131 match(Set dst src);
4132 ins_cost(MEMORY_REF_COST);
4133 size(4);
4134 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4135 opcode(STE_ZOPC);
4136 ins_encode(z_form_rt_mem(src, dst));
4137 ins_pipe(pipe_class_dummy);
4138 %}
4139
4140 // Load double value from stack slot.
4141 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4142 match(Set dst src);
4143 ins_cost(MEMORY_REF_COST);
4144 // TODO: s390 port size(FIXED_SIZE);
4145 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4146 opcode(LD_ZOPC);
4147 ins_encode(z_form_rt_mem(dst, src));
4148 ins_pipe(pipe_class_dummy);
4149 %}
4150
4151 // Store double value to stack slot.
4152 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4153 match(Set dst src);
4154 ins_cost(MEMORY_REF_COST);
4155 size(4);
4156 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4157 opcode(STD_ZOPC);
4158 ins_encode(z_form_rt_mem(src, dst));
4159 ins_pipe(pipe_class_dummy);
4160 %}
4161
4162 //----------Load/Store/Move Instructions---------------------------------------
4163
4164 //----------Load Instructions--------------------------------------------------
4165
4166 //------------------
4167 // MEMORY
4168 //------------------
4169
4170 // BYTE
4171 // Load Byte (8bit signed)
4172 instruct loadB(iRegI dst, memory mem) %{
4173 match(Set dst (LoadB mem));
4174 ins_cost(MEMORY_REF_COST);
4175 size(Z_DISP3_SIZE);
4176 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4177 opcode(LB_ZOPC, LB_ZOPC);
4178 ins_encode(z_form_rt_mem_opt(dst, mem));
4179 ins_pipe(pipe_class_dummy);
4180 %}
4181
4182 // Load Byte (8bit signed)
4183 instruct loadB2L(iRegL dst, memory mem) %{
4184 match(Set dst (ConvI2L (LoadB mem)));
4185 ins_cost(MEMORY_REF_COST);
4186 size(Z_DISP3_SIZE);
4187 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4188 opcode(LGB_ZOPC, LGB_ZOPC);
4189 ins_encode(z_form_rt_mem_opt(dst, mem));
4190 ins_pipe(pipe_class_dummy);
4191 %}
4192
4193 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4194 instruct loadUB(iRegI dst, memory mem) %{
4195 match(Set dst (LoadUB mem));
4196 ins_cost(MEMORY_REF_COST);
4197 size(Z_DISP3_SIZE);
4198 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4199 opcode(LLGC_ZOPC, LLGC_ZOPC);
4200 ins_encode(z_form_rt_mem_opt(dst, mem));
4201 ins_pipe(pipe_class_dummy);
4202 %}
4203
4204 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4205 instruct loadUB2L(iRegL dst, memory mem) %{
4206 match(Set dst (ConvI2L (LoadUB mem)));
4207 ins_cost(MEMORY_REF_COST);
4208 size(Z_DISP3_SIZE);
4209 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4210 opcode(LLGC_ZOPC, LLGC_ZOPC);
4211 ins_encode(z_form_rt_mem_opt(dst, mem));
4212 ins_pipe(pipe_class_dummy);
4213 %}
4214
4215 // CHAR/SHORT
4216
4217 // Load Short (16bit signed)
4218 instruct loadS(iRegI dst, memory mem) %{
4219 match(Set dst (LoadS mem));
4220 ins_cost(MEMORY_REF_COST);
4221 size(Z_DISP_SIZE);
4222 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4223 opcode(LHY_ZOPC, LH_ZOPC);
4224 ins_encode(z_form_rt_mem_opt(dst, mem));
4225 ins_pipe(pipe_class_dummy);
4226 %}
4227
4228 // Load Short (16bit signed)
4229 instruct loadS2L(iRegL dst, memory mem) %{
4230 match(Set dst (ConvI2L (LoadS mem)));
4231 ins_cost(MEMORY_REF_COST);
4232 size(Z_DISP3_SIZE);
4233 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4234 opcode(LGH_ZOPC, LGH_ZOPC);
4235 ins_encode(z_form_rt_mem_opt(dst, mem));
4236 ins_pipe(pipe_class_dummy);
4237 %}
4238
4239 // Load Char (16bit Unsigned)
4240 instruct loadUS(iRegI dst, memory mem) %{
4241 match(Set dst (LoadUS mem));
4242 ins_cost(MEMORY_REF_COST);
4243 size(Z_DISP3_SIZE);
4244 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4245 opcode(LLGH_ZOPC, LLGH_ZOPC);
4246 ins_encode(z_form_rt_mem_opt(dst, mem));
4247 ins_pipe(pipe_class_dummy);
4248 %}
4249
4250 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4251 instruct loadUS2L(iRegL dst, memory mem) %{
4252 match(Set dst (ConvI2L (LoadUS mem)));
4253 ins_cost(MEMORY_REF_COST);
4254 size(Z_DISP3_SIZE);
4255 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4256 opcode(LLGH_ZOPC, LLGH_ZOPC);
4257 ins_encode(z_form_rt_mem_opt(dst, mem));
4258 ins_pipe(pipe_class_dummy);
4259 %}
4260
4261 // INT
4262
4263 // Load Integer
4264 instruct loadI(iRegI dst, memory mem) %{
4265 match(Set dst (LoadI mem));
4266 ins_cost(MEMORY_REF_COST);
4267 size(Z_DISP_SIZE);
4268 format %{ "L(Y) $dst,$mem\t #" %}
4269 opcode(LY_ZOPC, L_ZOPC);
4270 ins_encode(z_form_rt_mem_opt(dst, mem));
4271 ins_pipe(pipe_class_dummy);
4272 %}
4273
4274 // Load and convert to long.
4275 instruct loadI2L(iRegL dst, memory mem) %{
4276 match(Set dst (ConvI2L (LoadI mem)));
4277 ins_cost(MEMORY_REF_COST);
4278 size(Z_DISP3_SIZE);
4279 format %{ "LGF $dst,$mem\t #" %}
4280 opcode(LGF_ZOPC, LGF_ZOPC);
4281 ins_encode(z_form_rt_mem_opt(dst, mem));
4282 ins_pipe(pipe_class_dummy);
4283 %}
4284
4285 // Load Unsigned Integer into a Long Register
4286 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4287 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4288 ins_cost(MEMORY_REF_COST);
4289 size(Z_DISP3_SIZE);
4290 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4291 opcode(LLGF_ZOPC, LLGF_ZOPC);
4292 ins_encode(z_form_rt_mem_opt(dst, mem));
4293 ins_pipe(pipe_class_dummy);
4294 %}
4295
4296 // range = array length (=jint)
4297 // Load Range
4298 instruct loadRange(iRegI dst, memory mem) %{
4299 match(Set dst (LoadRange mem));
4300 ins_cost(MEMORY_REF_COST);
4301 size(Z_DISP_SIZE);
4302 format %{ "L(Y) $dst,$mem\t # range" %}
4303 opcode(LY_ZOPC, L_ZOPC);
4304 ins_encode(z_form_rt_mem_opt(dst, mem));
4305 ins_pipe(pipe_class_dummy);
4306 %}
4307
4308 // LONG
4309
4310 // Load Long - aligned
4311 instruct loadL(iRegL dst, memory mem) %{
4312 match(Set dst (LoadL mem));
4313 ins_cost(MEMORY_REF_COST);
4314 size(Z_DISP3_SIZE);
4315 format %{ "LG $dst,$mem\t # long" %}
4316 opcode(LG_ZOPC, LG_ZOPC);
4317 ins_encode(z_form_rt_mem_opt(dst, mem));
4318 ins_pipe(pipe_class_dummy);
4319 %}
4320
4321 // Load Long - UNaligned
4322 instruct loadL_unaligned(iRegL dst, memory mem) %{
4323 match(Set dst (LoadL_unaligned mem));
4324 ins_cost(MEMORY_REF_COST);
4325 size(Z_DISP3_SIZE);
4326 format %{ "LG $dst,$mem\t # unaligned long" %}
4327 opcode(LG_ZOPC, LG_ZOPC);
4328 ins_encode(z_form_rt_mem_opt(dst, mem));
4329 ins_pipe(pipe_class_dummy);
4330 %}
4331
4332
4333 // PTR
4334
4335 // Load Pointer
4336 instruct loadP(iRegP dst, memory mem) %{
4337 match(Set dst (LoadP mem));
4338 predicate(n->as_Load()->barrier_data() == 0);
4339 ins_cost(MEMORY_REF_COST);
4340 size(Z_DISP3_SIZE);
4341 format %{ "LG $dst,$mem\t # ptr" %}
4342 opcode(LG_ZOPC, LG_ZOPC);
4343 ins_encode(z_form_rt_mem_opt(dst, mem));
4344 ins_pipe(pipe_class_dummy);
4345 %}
4346
4347 // LoadP + CastP2L
4348 instruct castP2X_loadP(iRegL dst, memory mem) %{
4349 match(Set dst (CastP2X (LoadP mem)));
4350 predicate(n->as_Load()->barrier_data() == 0);
4351 ins_cost(MEMORY_REF_COST);
4352 size(Z_DISP3_SIZE);
4353 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4354 opcode(LG_ZOPC, LG_ZOPC);
4355 ins_encode(z_form_rt_mem_opt(dst, mem));
4356 ins_pipe(pipe_class_dummy);
4357 %}
4358
4359 // Load Klass Pointer
4360 instruct loadKlass(iRegP dst, memory mem) %{
4361 match(Set dst (LoadKlass mem));
4362 ins_cost(MEMORY_REF_COST);
4363 size(Z_DISP3_SIZE);
4364 format %{ "LG $dst,$mem\t # klass ptr" %}
4365 opcode(LG_ZOPC, LG_ZOPC);
4366 ins_encode(z_form_rt_mem_opt(dst, mem));
4367 ins_pipe(pipe_class_dummy);
4368 %}
4369
4370 instruct loadTOC(iRegL dst) %{
4371 effect(DEF dst);
4372 ins_cost(DEFAULT_COST);
4373 // TODO: s390 port size(FIXED_SIZE);
4374 // TODO: check why this attribute causes many unnecessary rematerializations.
4375 //
4376 // The graphs I saw just had high register pressure. Further the
4377 // register TOC is loaded to is overwritten by the constant short
4378 // after. Here something as round robin register allocation might
4379 // help. But rematerializing seems not to hurt, jack even seems to
4380 // improve slightly.
4381 //
4382 // Without this flag we get spill-split recycle sanity check
4383 // failures in
4384 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4385 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4386 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4387 // stack. Later tlsLoadP is rematerialized, leaving the register
4388 // allocator with TOC on the stack and a badly placed reload.
4389 ins_should_rematerialize(true);
4390 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4391 ins_encode %{ __ load_toc($dst$$Register); %}
4392 ins_pipe(pipe_class_dummy);
4393 %}
4394
4395 // FLOAT
4396
4397 // Load Float
4398 instruct loadF(regF dst, memory mem) %{
4399 match(Set dst (LoadF mem));
4400 ins_cost(MEMORY_REF_COST);
4401 size(Z_DISP_SIZE);
4402 format %{ "LE(Y) $dst,$mem" %}
4403 opcode(LEY_ZOPC, LE_ZOPC);
4404 ins_encode(z_form_rt_mem_opt(dst, mem));
4405 ins_pipe(pipe_class_dummy);
4406 %}
4407
4408 // DOUBLE
4409
4410 // Load Double
4411 instruct loadD(regD dst, memory mem) %{
4412 match(Set dst (LoadD mem));
4413 ins_cost(MEMORY_REF_COST);
4414 size(Z_DISP_SIZE);
4415 format %{ "LD(Y) $dst,$mem" %}
4416 opcode(LDY_ZOPC, LD_ZOPC);
4417 ins_encode(z_form_rt_mem_opt(dst, mem));
4418 ins_pipe(pipe_class_dummy);
4419 %}
4420
4421 // Load Double - UNaligned
4422 instruct loadD_unaligned(regD dst, memory mem) %{
4423 match(Set dst (LoadD_unaligned mem));
4424 ins_cost(MEMORY_REF_COST);
4425 size(Z_DISP_SIZE);
4426 format %{ "LD(Y) $dst,$mem" %}
4427 opcode(LDY_ZOPC, LD_ZOPC);
4428 ins_encode(z_form_rt_mem_opt(dst, mem));
4429 ins_pipe(pipe_class_dummy);
4430 %}
4431
4432
4433 //----------------------
4434 // IMMEDIATES
4435 //----------------------
4436
4437 instruct loadConI(iRegI dst, immI src) %{
4438 match(Set dst src);
4439 ins_cost(DEFAULT_COST);
4440 size(6);
4441 format %{ "LGFI $dst,$src\t # (int)" %}
4442 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4443 ins_pipe(pipe_class_dummy);
4444 %}
4445
4446 instruct loadConI16(iRegI dst, immI16 src) %{
4447 match(Set dst src);
4448 ins_cost(DEFAULT_COST_LOW);
4449 size(4);
4450 format %{ "LGHI $dst,$src\t # (int)" %}
4451 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4452 ins_pipe(pipe_class_dummy);
4453 %}
4454
4455 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4456 match(Set dst src);
4457 effect(KILL cr);
4458 ins_cost(DEFAULT_COST_LOW);
4459 size(4);
4460 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4461 opcode(XGR_ZOPC);
4462 ins_encode(z_rreform(dst, dst));
4463 ins_pipe(pipe_class_dummy);
4464 %}
4465
4466 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4467 match(Set dst src);
4468 // TODO: s390 port size(FIXED_SIZE);
4469 format %{ "LLILL $dst,$src" %}
4470 opcode(LLILL_ZOPC);
4471 ins_encode(z_riform_unsigned(dst, src) );
4472 ins_pipe(pipe_class_dummy);
4473 %}
4474
4475 // Load long constant from TOC with pcrelative address.
4476 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4477 match(Set dst src);
4478 ins_cost(MEMORY_REF_COST_LO);
4479 size(6);
4480 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4481 ins_encode %{
4482 address long_address = __ long_constant($src$$constant);
4483 if (long_address == nullptr) {
4484 Compile::current()->env()->record_out_of_memory_failure();
4485 return;
4486 }
4487 __ load_long_pcrelative($dst$$Register, long_address);
4488 %}
4489 ins_pipe(pipe_class_dummy);
4490 %}
4491
4492 instruct loadConL32(iRegL dst, immL32 src) %{
4493 match(Set dst src);
4494 ins_cost(DEFAULT_COST);
4495 size(6);
4496 format %{ "LGFI $dst,$src\t # (long)" %}
4497 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4498 ins_pipe(pipe_class_dummy);
4499 %}
4500
4501 instruct loadConL16(iRegL dst, immL16 src) %{
4502 match(Set dst src);
4503 ins_cost(DEFAULT_COST_LOW);
4504 size(4);
4505 format %{ "LGHI $dst,$src\t # (long)" %}
4506 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4507 ins_pipe(pipe_class_dummy);
4508 %}
4509
4510 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4511 match(Set dst src);
4512 effect(KILL cr);
4513 ins_cost(DEFAULT_COST_LOW);
4514 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4515 opcode(XGR_ZOPC);
4516 ins_encode(z_rreform(dst, dst));
4517 ins_pipe(pipe_class_dummy);
4518 %}
4519
4520 // Load ptr constant from TOC with pc relative address.
4521 // Special handling for oop constants required.
4522 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4523 match(Set dst src);
4524 ins_cost(MEMORY_REF_COST_LO);
4525 size(6);
4526 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4527 ins_encode %{
4528 relocInfo::relocType constant_reloc = $src->constant_reloc();
4529 if (constant_reloc == relocInfo::oop_type) {
4530 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4531 bool success = __ load_oop_from_toc($dst$$Register, a);
4532 if (!success) {
4533 Compile::current()->env()->record_out_of_memory_failure();
4534 return;
4535 }
4536 } else if (constant_reloc == relocInfo::metadata_type) {
4537 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4538 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4539 if (const_toc_addr == nullptr) {
4540 Compile::current()->env()->record_out_of_memory_failure();
4541 return;
4542 }
4543 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4544 } else { // Non-oop pointers, e.g. card mark base, heap top.
4545 address long_address = __ long_constant((jlong)$src$$constant);
4546 if (long_address == nullptr) {
4547 Compile::current()->env()->record_out_of_memory_failure();
4548 return;
4549 }
4550 __ load_long_pcrelative($dst$$Register, long_address);
4551 }
4552 %}
4553 ins_pipe(pipe_class_dummy);
4554 %}
4555
4556 // We don't use immP16 to avoid problems with oops.
4557 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4558 match(Set dst src);
4559 effect(KILL cr);
4560 size(4);
4561 format %{ "XGR $dst,$dst\t # null pointer" %}
4562 opcode(XGR_ZOPC);
4563 ins_encode(z_rreform(dst, dst));
4564 ins_pipe(pipe_class_dummy);
4565 %}
4566
4567 //----------Load Float Constant Instructions-------------------------------------------------
4568
4569 // We may not specify this instruction via an `expand' rule. If we do,
4570 // code selection will forget that this instruction needs a floating
4571 // point constant inserted into the code buffer. So `Shorten_branches'
4572 // will fail.
4573 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4574 match(Set dst src);
4575 effect(KILL cr);
4576 ins_cost(MEMORY_REF_COST);
4577 size(6);
4578 // If this instruction rematerializes, it prolongs the live range
4579 // of the toc node, causing illegal graphs.
4580 ins_cannot_rematerialize(true);
4581 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4582 ins_encode %{
4583 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4584 %}
4585 ins_pipe(pipe_class_dummy);
4586 %}
4587
4588 // E may not specify this instruction via an `expand' rule. If we do,
4589 // code selection will forget that this instruction needs a floating
4590 // point constant inserted into the code buffer. So `Shorten_branches'
4591 // will fail.
4592 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4593 match(Set dst src);
4594 effect(KILL cr);
4595 ins_cost(MEMORY_REF_COST);
4596 size(6);
4597 // If this instruction rematerializes, it prolongs the live range
4598 // of the toc node, causing illegal graphs.
4599 ins_cannot_rematerialize(true);
4600 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4601 ins_encode %{
4602 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4603 %}
4604 ins_pipe(pipe_class_dummy);
4605 %}
4606
4607 // Special case: Load Const 0.0F
4608
4609 // There's a special instr to clear a FP register.
4610 instruct loadConF0(regF dst, immFp0 src) %{
4611 match(Set dst src);
4612 ins_cost(DEFAULT_COST_LOW);
4613 size(4);
4614 format %{ "LZER $dst,$src\t # clear to zero" %}
4615 opcode(LZER_ZOPC);
4616 ins_encode(z_rreform(dst, Z_F0));
4617 ins_pipe(pipe_class_dummy);
4618 %}
4619
4620 // There's a special instr to clear a FP register.
4621 instruct loadConD0(regD dst, immDp0 src) %{
4622 match(Set dst src);
4623 ins_cost(DEFAULT_COST_LOW);
4624 size(4);
4625 format %{ "LZDR $dst,$src\t # clear to zero" %}
4626 opcode(LZDR_ZOPC);
4627 ins_encode(z_rreform(dst, Z_F0));
4628 ins_pipe(pipe_class_dummy);
4629 %}
4630
4631
4632 //----------Store Instructions-------------------------------------------------
4633
4634 // BYTE
4635
4636 // Store Byte
4637 instruct storeB(memory mem, iRegI src) %{
4638 match(Set mem (StoreB mem src));
4639 ins_cost(MEMORY_REF_COST);
4640 size(Z_DISP_SIZE);
4641 format %{ "STC(Y) $src,$mem\t # byte" %}
4642 opcode(STCY_ZOPC, STC_ZOPC);
4643 ins_encode(z_form_rt_mem_opt(src, mem));
4644 ins_pipe(pipe_class_dummy);
4645 %}
4646
4647 // CHAR/SHORT
4648
4649 // Store Char/Short
4650 instruct storeC(memory mem, iRegI src) %{
4651 match(Set mem (StoreC mem src));
4652 ins_cost(MEMORY_REF_COST);
4653 size(Z_DISP_SIZE);
4654 format %{ "STH(Y) $src,$mem\t # short" %}
4655 opcode(STHY_ZOPC, STH_ZOPC);
4656 ins_encode(z_form_rt_mem_opt(src, mem));
4657 ins_pipe(pipe_class_dummy);
4658 %}
4659
4660 // INT
4661
4662 // Store Integer
4663 instruct storeI(memory mem, iRegI src) %{
4664 match(Set mem (StoreI mem src));
4665 ins_cost(MEMORY_REF_COST);
4666 size(Z_DISP_SIZE);
4667 format %{ "ST(Y) $src,$mem\t # int" %}
4668 opcode(STY_ZOPC, ST_ZOPC);
4669 ins_encode(z_form_rt_mem_opt(src, mem));
4670 ins_pipe(pipe_class_dummy);
4671 %}
4672
4673 // LONG
4674
4675 // Store Long
4676 instruct storeL(memory mem, iRegL src) %{
4677 match(Set mem (StoreL mem src));
4678 ins_cost(MEMORY_REF_COST);
4679 size(Z_DISP3_SIZE);
4680 format %{ "STG $src,$mem\t # long" %}
4681 opcode(STG_ZOPC, STG_ZOPC);
4682 ins_encode(z_form_rt_mem_opt(src, mem));
4683 ins_pipe(pipe_class_dummy);
4684 %}
4685
4686 // PTR
4687
4688 // Store Pointer
4689 instruct storeP(memory dst, memoryRegP src) %{
4690 match(Set dst (StoreP dst src));
4691 predicate(n->as_Store()->barrier_data() == 0);
4692 ins_cost(MEMORY_REF_COST);
4693 size(Z_DISP3_SIZE);
4694 format %{ "STG $src,$dst\t # ptr" %}
4695 opcode(STG_ZOPC, STG_ZOPC);
4696 ins_encode(z_form_rt_mem_opt(src, dst));
4697 ins_pipe(pipe_class_dummy);
4698 %}
4699
4700 // FLOAT
4701
4702 // Store Float
4703 instruct storeF(memory mem, regF src) %{
4704 match(Set mem (StoreF mem src));
4705 ins_cost(MEMORY_REF_COST);
4706 size(Z_DISP_SIZE);
4707 format %{ "STE(Y) $src,$mem\t # float" %}
4708 opcode(STEY_ZOPC, STE_ZOPC);
4709 ins_encode(z_form_rt_mem_opt(src, mem));
4710 ins_pipe(pipe_class_dummy);
4711 %}
4712
4713 // DOUBLE
4714
4715 // Store Double
4716 instruct storeD(memory mem, regD src) %{
4717 match(Set mem (StoreD mem src));
4718 ins_cost(MEMORY_REF_COST);
4719 size(Z_DISP_SIZE);
4720 format %{ "STD(Y) $src,$mem\t # double" %}
4721 opcode(STDY_ZOPC, STD_ZOPC);
4722 ins_encode(z_form_rt_mem_opt(src, mem));
4723 ins_pipe(pipe_class_dummy);
4724 %}
4725
4726 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4727
4728 // Should support match rule for PrefetchAllocation.
4729 // Still needed after 8068977 for PrefetchAllocate.
4730 instruct prefetchAlloc(memory mem) %{
4731 match(PrefetchAllocation mem);
4732 predicate(VM_Version::has_Prefetch());
4733 ins_cost(DEFAULT_COST);
4734 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4735 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4736 ins_pipe(pipe_class_dummy);
4737 %}
4738
4739 //----------Memory init instructions------------------------------------------
4740
4741 // Move Immediate to 1-byte memory.
4742 instruct memInitB(memoryRSY mem, immI8 src) %{
4743 match(Set mem (StoreB mem src));
4744 ins_cost(MEMORY_REF_COST);
4745 // TODO: s390 port size(VARIABLE_SIZE);
4746 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4747 ins_encode %{
4748 if (Immediate::is_uimm12((long)$mem$$disp)) {
4749 __ z_mvi($mem$$Address, $src$$constant);
4750 } else {
4751 __ z_mviy($mem$$Address, $src$$constant);
4752 }
4753 %}
4754 ins_pipe(pipe_class_dummy);
4755 %}
4756
4757 // Move Immediate to 2-byte memory.
4758 instruct memInitC(memoryRS mem, immI16 src) %{
4759 match(Set mem (StoreC mem src));
4760 ins_cost(MEMORY_REF_COST);
4761 size(6);
4762 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4763 opcode(MVHHI_ZOPC);
4764 ins_encode(z_silform(mem, src));
4765 ins_pipe(pipe_class_dummy);
4766 %}
4767
4768 // Move Immediate to 4-byte memory.
4769 instruct memInitI(memoryRS mem, immI16 src) %{
4770 match(Set mem (StoreI mem src));
4771 ins_cost(MEMORY_REF_COST);
4772 size(6);
4773 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4774 opcode(MVHI_ZOPC);
4775 ins_encode(z_silform(mem, src));
4776 ins_pipe(pipe_class_dummy);
4777 %}
4778
4779
4780 // Move Immediate to 8-byte memory.
4781 instruct memInitL(memoryRS mem, immL16 src) %{
4782 match(Set mem (StoreL mem src));
4783 ins_cost(MEMORY_REF_COST);
4784 size(6);
4785 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4786 opcode(MVGHI_ZOPC);
4787 ins_encode(z_silform(mem, src));
4788 ins_pipe(pipe_class_dummy);
4789 %}
4790
4791 // Move Immediate to 8-byte memory.
4792 instruct memInitP(memoryRS mem, immP16 src) %{
4793 match(Set mem (StoreP mem src));
4794 predicate(n->as_Store()->barrier_data() == 0);
4795 ins_cost(MEMORY_REF_COST);
4796 size(6);
4797 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4798 opcode(MVGHI_ZOPC);
4799 ins_encode(z_silform(mem, src));
4800 ins_pipe(pipe_class_dummy);
4801 %}
4802
4803
4804 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4805
4806 // See cOop encoding classes for elaborate comment.
4807
4808 // Moved here because it is needed in expand rules for encode.
4809 // Long negation.
4810 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4811 match(Set dst (SubL zero src));
4812 effect(KILL cr);
4813 size(4);
4814 format %{ "NEG $dst, $src\t # long" %}
4815 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4816 ins_pipe(pipe_class_dummy);
4817 %}
4818
4819 // Load Compressed Pointer
4820
4821 // Load narrow oop
4822 instruct loadN(iRegN dst, memory mem) %{
4823 match(Set dst (LoadN mem));
4824 predicate(n->as_Load()->barrier_data() == 0);
4825 ins_cost(MEMORY_REF_COST);
4826 size(Z_DISP3_SIZE);
4827 format %{ "LoadN $dst,$mem\t # (cOop)" %}
4828 opcode(LLGF_ZOPC, LLGF_ZOPC);
4829 ins_encode(z_form_rt_mem_opt(dst, mem));
4830 ins_pipe(pipe_class_dummy);
4831 %}
4832
4833 // Load narrow Klass Pointer
4834 instruct loadNKlass(iRegN dst, memory mem) %{
4835 predicate(!UseCompactObjectHeaders);
4836 match(Set dst (LoadNKlass mem));
4837 ins_cost(MEMORY_REF_COST);
4838 size(Z_DISP3_SIZE);
4839 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
4840 opcode(LLGF_ZOPC, LLGF_ZOPC);
4841 ins_encode(z_form_rt_mem_opt(dst, mem));
4842 ins_pipe(pipe_class_dummy);
4843 %}
4844
4845 instruct loadNKlassCompactHeaders(iRegN dst, memory mem) %{
4846 match(Set dst (LoadNKlass mem));
4847 predicate(UseCompactObjectHeaders);
4848 ins_cost(MEMORY_REF_COST);
4849 format %{ "load_narrow_klass_compact $dst,$mem \t# compressed class ptr" %}
4850 // z_lg (6 bytes) + z_srlg (6 bytes); neither instruction modifies the CC.
4851 size(12);
4852 ins_encode %{
4853 __ load_narrow_klass_compact_c2($dst$$Register, $mem$$Address);
4854 %}
4855 ins_pipe(pipe_class_dummy);
4856 %}
4857
4858 // Load constant Compressed Pointer
4859
4860 instruct loadConN(iRegN dst, immN src) %{
4861 match(Set dst src);
4862 ins_cost(DEFAULT_COST);
4863 size(6);
4864 format %{ "loadConN $dst,$src\t # (cOop)" %}
4865 ins_encode %{
4866 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4867 __ relocate(cOop.rspec(), 1);
4868 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4869 %}
4870 ins_pipe(pipe_class_dummy);
4871 %}
4872
4873 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4874 match(Set dst src);
4875 effect(KILL cr);
4876 ins_cost(DEFAULT_COST_LOW);
4877 size(4);
4878 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4879 opcode(XGR_ZOPC);
4880 ins_encode(z_rreform(dst, dst));
4881 ins_pipe(pipe_class_dummy);
4882 %}
4883
4884 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4885 match(Set dst src);
4886 ins_cost(DEFAULT_COST);
4887 size(6);
4888 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4889 ins_encode %{
4890 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4891 __ relocate(NKlass.rspec(), 1);
4892 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4893 %}
4894 ins_pipe(pipe_class_dummy);
4895 %}
4896
4897 // Load and Decode Compressed Pointer
4898 // optimized variants for Unscaled cOops
4899
4900 instruct decodeLoadN(iRegP dst, memory mem) %{
4901 match(Set dst (DecodeN (LoadN mem)));
4902 predicate(false && (CompressedOops::base()==nullptr) && (CompressedOops::shift()==0));
4903 ins_cost(MEMORY_REF_COST);
4904 size(Z_DISP3_SIZE);
4905 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %}
4906 opcode(LLGF_ZOPC, LLGF_ZOPC);
4907 ins_encode(z_form_rt_mem_opt(dst, mem));
4908 ins_pipe(pipe_class_dummy);
4909 %}
4910
4911 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4912 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4913 predicate(false && (CompressedKlassPointers::base()==nullptr)&&(CompressedKlassPointers::shift()==0));
4914 ins_cost(MEMORY_REF_COST);
4915 size(Z_DISP3_SIZE);
4916 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %}
4917 opcode(LLGF_ZOPC, LLGF_ZOPC);
4918 ins_encode(z_form_rt_mem_opt(dst, mem));
4919 ins_pipe(pipe_class_dummy);
4920 %}
4921
4922 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4923 match(Set dst (DecodeNKlass src));
4924 ins_cost(3 * DEFAULT_COST);
4925 size(12);
4926 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4927 ins_encode %{
4928 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4929 __ relocate(NKlass.rspec(), 1);
4930 __ load_const($dst$$Register, (Klass*)NKlass.value());
4931 %}
4932 ins_pipe(pipe_class_dummy);
4933 %}
4934
4935 // Decode Compressed Pointer
4936
4937 // General decoder
4938 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4939 match(Set dst (DecodeN src));
4940 effect(KILL cr);
4941 predicate(CompressedOops::base() == nullptr || !ExpandLoadingBaseDecode);
4942 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4943 // TODO: s390 port size(VARIABLE_SIZE);
4944 format %{ "decodeN $dst,$src\t # (decode cOop)" %}
4945 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4946 ins_pipe(pipe_class_dummy);
4947 %}
4948
4949 // General Klass decoder
4950 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4951 match(Set dst (DecodeNKlass src));
4952 effect(KILL cr);
4953 ins_cost(3 * DEFAULT_COST);
4954 format %{ "decode_klass $dst,$src" %}
4955 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4956 ins_pipe(pipe_class_dummy);
4957 %}
4958
4959 // General decoder
4960 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4961 match(Set dst (DecodeN src));
4962 effect(KILL cr);
4963 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4964 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4965 (CompressedOops::base()== nullptr || !ExpandLoadingBaseDecode_NN));
4966 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4967 // TODO: s390 port size(VARIABLE_SIZE);
4968 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %}
4969 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4970 ins_pipe(pipe_class_dummy);
4971 %}
4972
4973 instruct loadBase(iRegL dst, immL baseImm) %{
4974 effect(DEF dst, USE baseImm);
4975 predicate(false);
4976 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4977 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4978 ins_pipe(pipe_class_dummy);
4979 %}
4980
4981 // Decoder for heapbased mode peeling off loading the base.
4982 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4983 match(Set dst (DecodeN src base));
4984 // Note: Effect TEMP dst was used with the intention to get
4985 // different regs for dst and base, but this has caused ADLC to
4986 // generate wrong code. Oop_decoder generates additional lgr when
4987 // dst==base.
4988 effect(KILL cr);
4989 predicate(false);
4990 // TODO: s390 port size(VARIABLE_SIZE);
4991 format %{ "decodeN $dst = ($src == 0) ? nullptr : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4992 ins_encode %{
4993 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4994 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4995 %}
4996 ins_pipe(pipe_class_dummy);
4997 %}
4998
4999 // Decoder for heapbased mode peeling off loading the base.
5000 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
5001 match(Set dst (DecodeN src base));
5002 effect(KILL cr);
5003 predicate(false);
5004 // TODO: s390 port size(VARIABLE_SIZE);
5005 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
5006 ins_encode %{
5007 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
5008 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
5009 %}
5010 ins_pipe(pipe_class_dummy);
5011 %}
5012
5013 // Decoder for heapbased mode peeling off loading the base.
5014 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
5015 match(Set dst (DecodeN src));
5016 predicate(CompressedOops::base() != nullptr && ExpandLoadingBaseDecode);
5017 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
5018 // TODO: s390 port size(VARIABLE_SIZE);
5019 expand %{
5020 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5021 iRegL base;
5022 loadBase(base, baseImm);
5023 decodeN_base(dst, src, base, cr);
5024 %}
5025 %}
5026
5027 // Decoder for heapbased mode peeling off loading the base.
5028 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
5029 match(Set dst (DecodeN src));
5030 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
5031 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
5032 CompressedOops::base() != nullptr && ExpandLoadingBaseDecode_NN);
5033 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5034 // TODO: s390 port size(VARIABLE_SIZE);
5035 expand %{
5036 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5037 iRegL base;
5038 loadBase(base, baseImm);
5039 decodeN_NN_base(dst, src, base, cr);
5040 %}
5041 %}
5042
5043 // Encode Compressed Pointer
5044
5045 // General encoder
5046 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
5047 match(Set dst (EncodeP src));
5048 effect(KILL cr);
5049 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5050 (CompressedOops::base() == nullptr ||
5051 CompressedOops::base_disjoint() ||
5052 !ExpandLoadingBaseEncode));
5053 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5054 // TODO: s390 port size(VARIABLE_SIZE);
5055 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5056 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5057 ins_pipe(pipe_class_dummy);
5058 %}
5059
5060 // General class encoder
5061 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
5062 match(Set dst (EncodePKlass src));
5063 effect(KILL cr);
5064 format %{ "encode_klass $dst,$src" %}
5065 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
5066 ins_pipe(pipe_class_dummy);
5067 %}
5068
5069 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
5070 match(Set dst (EncodeP src));
5071 effect(KILL cr);
5072 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5073 (CompressedOops::base() == nullptr ||
5074 CompressedOops::base_disjoint() ||
5075 !ExpandLoadingBaseEncode_NN));
5076 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5077 // TODO: s390 port size(VARIABLE_SIZE);
5078 format %{ "encodeP $dst,$src\t # (encode cOop)" %}
5079 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
5080 ins_pipe(pipe_class_dummy);
5081 %}
5082
5083 // Encoder for heapbased mode peeling off loading the base.
5084 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
5085 match(Set dst (EncodeP src (Binary base dst)));
5086 effect(TEMP_DEF dst);
5087 predicate(false);
5088 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5089 // TODO: s390 port size(VARIABLE_SIZE);
5090 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
5091 ins_encode %{
5092 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
5093 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
5094 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
5095 %}
5096 ins_pipe(pipe_class_dummy);
5097 %}
5098
5099 // Encoder for heapbased mode peeling off loading the base.
5100 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
5101 match(Set dst (EncodeP src base));
5102 effect(USE pow2_offset);
5103 predicate(false);
5104 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5105 // TODO: s390 port size(VARIABLE_SIZE);
5106 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
5107 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
5108 ins_pipe(pipe_class_dummy);
5109 %}
5110
5111 // Encoder for heapbased mode peeling off loading the base.
5112 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5113 match(Set dst (EncodeP src));
5114 effect(KILL cr);
5115 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5116 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
5117 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5118 // TODO: s390 port size(VARIABLE_SIZE);
5119 expand %{
5120 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
5121 immL_0 zero %{ (0) %}
5122 flagsReg ccr;
5123 iRegL base;
5124 iRegL negBase;
5125 loadBase(base, baseImm);
5126 negL_reg_reg(negBase, zero, base, ccr);
5127 encodeP_base(dst, src, negBase);
5128 %}
5129 %}
5130
5131 // Encoder for heapbased mode peeling off loading the base.
5132 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5133 match(Set dst (EncodeP src));
5134 effect(KILL cr);
5135 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5136 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
5137 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5138 // TODO: s390 port size(VARIABLE_SIZE);
5139 expand %{
5140 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5141 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
5142 immL_0 zero %{ 0 %}
5143 flagsReg ccr;
5144 iRegL base;
5145 iRegL negBase;
5146 loadBase(base, baseImm);
5147 negL_reg_reg(negBase, zero, base, ccr);
5148 encodeP_NN_base(dst, src, negBase, pow2_offset);
5149 %}
5150 %}
5151
5152 // Store Compressed Pointer
5153
5154 // Store Compressed Pointer
5155 instruct storeN(memory mem, iRegN_P2N src) %{
5156 match(Set mem (StoreN mem src));
5157 predicate(n->as_Store()->barrier_data() == 0);
5158 ins_cost(MEMORY_REF_COST);
5159 size(Z_DISP_SIZE);
5160 format %{ "ST $src,$mem\t # (cOop)" %}
5161 opcode(STY_ZOPC, ST_ZOPC);
5162 ins_encode(z_form_rt_mem_opt(src, mem));
5163 ins_pipe(pipe_class_dummy);
5164 %}
5165
5166 // Store Compressed Klass pointer
5167 instruct storeNKlass(memory mem, iRegN src) %{
5168 match(Set mem (StoreNKlass mem src));
5169 ins_cost(MEMORY_REF_COST);
5170 size(Z_DISP_SIZE);
5171 format %{ "ST $src,$mem\t # (cKlass)" %}
5172 opcode(STY_ZOPC, ST_ZOPC);
5173 ins_encode(z_form_rt_mem_opt(src, mem));
5174 ins_pipe(pipe_class_dummy);
5175 %}
5176
5177 // Compare Compressed Pointers
5178
5179 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5180 match(Set cr (CmpN src1 src2));
5181 ins_cost(DEFAULT_COST);
5182 size(2);
5183 format %{ "CLR $src1,$src2\t # (cOop)" %}
5184 opcode(CLR_ZOPC);
5185 ins_encode(z_rrform(src1, src2));
5186 ins_pipe(pipe_class_dummy);
5187 %}
5188
5189 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5190 match(Set cr (CmpN src1 src2));
5191 ins_cost(DEFAULT_COST);
5192 size(6);
5193 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %}
5194 ins_encode %{
5195 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5196 __ relocate(cOop.rspec(), 1);
5197 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5198 %}
5199 ins_pipe(pipe_class_dummy);
5200 %}
5201
5202 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5203 match(Set cr (CmpN src1 src2));
5204 ins_cost(DEFAULT_COST);
5205 size(6);
5206 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %}
5207 ins_encode %{
5208 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5209 __ relocate(NKlass.rspec(), 1);
5210 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5211 %}
5212 ins_pipe(pipe_class_dummy);
5213 %}
5214
5215 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5216 match(Set cr (CmpN src1 src2));
5217 ins_cost(DEFAULT_COST);
5218 size(2);
5219 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %}
5220 opcode(LTR_ZOPC);
5221 ins_encode(z_rrform(src1, src1));
5222 ins_pipe(pipe_class_dummy);
5223 %}
5224
5225
5226 //----------MemBar Instructions-----------------------------------------------
5227
5228 // Memory barrier flavors
5229
5230 instruct membar_acquire() %{
5231 match(MemBarAcquire);
5232 match(LoadFence);
5233 ins_cost(4*MEMORY_REF_COST);
5234 size(0);
5235 format %{ "MEMBAR-acquire" %}
5236 ins_encode %{ __ z_acquire(); %}
5237 ins_pipe(pipe_class_dummy);
5238 %}
5239
5240 instruct membar_acquire_lock() %{
5241 match(MemBarAcquireLock);
5242 ins_cost(0);
5243 size(0);
5244 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5245 ins_encode(/*empty*/);
5246 ins_pipe(pipe_class_dummy);
5247 %}
5248
5249 instruct membar_release() %{
5250 match(MemBarRelease);
5251 match(StoreFence);
5252 ins_cost(4 * MEMORY_REF_COST);
5253 size(0);
5254 format %{ "MEMBAR-release" %}
5255 ins_encode %{ __ z_release(); %}
5256 ins_pipe(pipe_class_dummy);
5257 %}
5258
5259 instruct membar_release_lock() %{
5260 match(MemBarReleaseLock);
5261 ins_cost(0);
5262 size(0);
5263 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5264 ins_encode(/*empty*/);
5265 ins_pipe(pipe_class_dummy);
5266 %}
5267
5268 instruct membar_storeload() %{
5269 match(MemBarStoreLoad);
5270 ins_cost(4 * MEMORY_REF_COST);
5271 size(2);
5272 format %{ "MEMBAR-storeload" %}
5273 ins_encode %{ __ z_fence(); %}
5274 ins_pipe(pipe_class_dummy);
5275 %}
5276
5277 instruct membar_volatile() %{
5278 match(MemBarVolatile);
5279 ins_cost(4 * MEMORY_REF_COST);
5280 size(2);
5281 format %{ "MEMBAR-volatile" %}
5282 ins_encode %{ __ z_fence(); %}
5283 ins_pipe(pipe_class_dummy);
5284 %}
5285
5286 instruct unnecessary_membar_volatile() %{
5287 match(MemBarVolatile);
5288 predicate(Matcher::post_store_load_barrier(n));
5289 ins_cost(0);
5290 size(0);
5291 format %{ "# MEMBAR-volatile (empty)" %}
5292 ins_encode(/*empty*/);
5293 ins_pipe(pipe_class_dummy);
5294 %}
5295
5296 instruct membar_full() %{
5297 match(MemBarFull);
5298 ins_cost(4 * MEMORY_REF_COST);
5299 size(2);
5300 format %{ "MEMBAR-full" %}
5301 ins_encode %{ __ z_fence(); %}
5302 ins_pipe(pipe_class_dummy);
5303 %}
5304
5305 instruct membar_CPUOrder() %{
5306 match(MemBarCPUOrder);
5307 ins_cost(0);
5308 // TODO: s390 port size(FIXED_SIZE);
5309 format %{ "MEMBAR-CPUOrder (empty)" %}
5310 ins_encode(/*empty*/);
5311 ins_pipe(pipe_class_dummy);
5312 %}
5313
5314 instruct membar_storestore() %{
5315 match(MemBarStoreStore);
5316 match(StoreStoreFence);
5317 ins_cost(0);
5318 size(0);
5319 format %{ "MEMBAR-storestore (empty)" %}
5320 ins_encode();
5321 ins_pipe(pipe_class_dummy);
5322 %}
5323
5324
5325 //----------Register Move Instructions-----------------------------------------
5326
5327 // Cast Long to Pointer for unsafe natives.
5328 instruct castX2P(iRegP dst, iRegL src) %{
5329 match(Set dst (CastX2P src));
5330 // TODO: s390 port size(VARIABLE_SIZE);
5331 format %{ "LGR $dst,$src\t # CastX2P" %}
5332 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5333 ins_pipe(pipe_class_dummy);
5334 %}
5335
5336 // Cast Pointer to Long for unsafe natives.
5337 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5338 match(Set dst (CastP2X src));
5339 // TODO: s390 port size(VARIABLE_SIZE);
5340 format %{ "LGR $dst,$src\t # CastP2X" %}
5341 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5342 ins_pipe(pipe_class_dummy);
5343 %}
5344
5345 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5346 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5347 match(Set stkSlot src); // chain rule
5348 ins_cost(MEMORY_REF_COST);
5349 // TODO: s390 port size(FIXED_SIZE);
5350 format %{ " STD $src,$stkSlot\t # stk" %}
5351 opcode(STD_ZOPC);
5352 ins_encode(z_form_rt_mem(src, stkSlot));
5353 ins_pipe(pipe_class_dummy);
5354 %}
5355
5356 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5357 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5358 match(Set stkSlot src); // chain rule
5359 ins_cost(MEMORY_REF_COST);
5360 // TODO: s390 port size(FIXED_SIZE);
5361 format %{ "STE $src,$stkSlot\t # stk" %}
5362 opcode(STE_ZOPC);
5363 ins_encode(z_form_rt_mem(src, stkSlot));
5364 ins_pipe(pipe_class_dummy);
5365 %}
5366
5367 //----------Conditional Move---------------------------------------------------
5368
5369 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5370 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5371 ins_cost(DEFAULT_COST + BRANCH_COST);
5372 // TODO: s390 port size(VARIABLE_SIZE);
5373 format %{ "CMoveN,$cmp $dst,$src" %}
5374 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5375 ins_pipe(pipe_class_dummy);
5376 %}
5377
5378 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5379 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5380 ins_cost(DEFAULT_COST + BRANCH_COST);
5381 // TODO: s390 port size(VARIABLE_SIZE);
5382 format %{ "CMoveN,$cmp $dst,$src" %}
5383 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5384 ins_pipe(pipe_class_dummy);
5385 %}
5386
5387 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5388 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5389 ins_cost(DEFAULT_COST + BRANCH_COST);
5390 // TODO: s390 port size(VARIABLE_SIZE);
5391 format %{ "CMoveI,$cmp $dst,$src" %}
5392 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5393 ins_pipe(pipe_class_dummy);
5394 %}
5395
5396 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5397 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5398 ins_cost(DEFAULT_COST + BRANCH_COST);
5399 // TODO: s390 port size(VARIABLE_SIZE);
5400 format %{ "CMoveI,$cmp $dst,$src" %}
5401 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5402 ins_pipe(pipe_class_dummy);
5403 %}
5404
5405 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5406 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5407 ins_cost(DEFAULT_COST + BRANCH_COST);
5408 // TODO: s390 port size(VARIABLE_SIZE);
5409 format %{ "CMoveP,$cmp $dst,$src" %}
5410 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5411 ins_pipe(pipe_class_dummy);
5412 %}
5413
5414 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5415 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5416 ins_cost(DEFAULT_COST + BRANCH_COST);
5417 // TODO: s390 port size(VARIABLE_SIZE);
5418 format %{ "CMoveP,$cmp $dst,$src" %}
5419 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5420 ins_pipe(pipe_class_dummy);
5421 %}
5422
5423 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5424 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5425 ins_cost(DEFAULT_COST + BRANCH_COST);
5426 // TODO: s390 port size(VARIABLE_SIZE);
5427 format %{ "CMoveF,$cmp $dst,$src" %}
5428 ins_encode %{
5429 // Don't emit code if operands are identical (same register).
5430 if ($dst$$FloatRegister != $src$$FloatRegister) {
5431 Label done;
5432 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5433 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5434 __ bind(done);
5435 }
5436 %}
5437 ins_pipe(pipe_class_dummy);
5438 %}
5439
5440 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5441 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5442 ins_cost(DEFAULT_COST + BRANCH_COST);
5443 // TODO: s390 port size(VARIABLE_SIZE);
5444 format %{ "CMoveD,$cmp $dst,$src" %}
5445 ins_encode %{
5446 // Don't emit code if operands are identical (same register).
5447 if ($dst$$FloatRegister != $src$$FloatRegister) {
5448 Label done;
5449 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5450 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5451 __ bind(done);
5452 }
5453 %}
5454 ins_pipe(pipe_class_dummy);
5455 %}
5456
5457 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5458 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5459 ins_cost(DEFAULT_COST + BRANCH_COST);
5460 // TODO: s390 port size(VARIABLE_SIZE);
5461 format %{ "CMoveL,$cmp $dst,$src" %}
5462 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5463 ins_pipe(pipe_class_dummy);
5464 %}
5465
5466 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5467 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5468 ins_cost(DEFAULT_COST + BRANCH_COST);
5469 // TODO: s390 port size(VARIABLE_SIZE);
5470 format %{ "CMoveL,$cmp $dst,$src" %}
5471 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5472 ins_pipe(pipe_class_dummy);
5473 %}
5474
5475 //----------OS and Locking Instructions----------------------------------------
5476
5477 // This name is KNOWN by the ADLC and cannot be changed.
5478 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5479 // for this guy.
5480 instruct tlsLoadP(threadRegP dst) %{
5481 match(Set dst (ThreadLocal));
5482 ins_cost(0);
5483 size(0);
5484 ins_should_rematerialize(true);
5485 format %{ "# $dst=ThreadLocal" %}
5486 ins_encode(/* empty */);
5487 ins_pipe(pipe_class_dummy);
5488 %}
5489
5490 instruct checkCastPP(iRegP dst) %{
5491 match(Set dst (CheckCastPP dst));
5492 size(0);
5493 format %{ "# checkcastPP of $dst" %}
5494 ins_encode(/*empty*/);
5495 ins_pipe(pipe_class_dummy);
5496 %}
5497
5498 instruct castPP(iRegP dst) %{
5499 match(Set dst (CastPP dst));
5500 size(0);
5501 format %{ "# castPP of $dst" %}
5502 ins_encode(/*empty*/);
5503 ins_pipe(pipe_class_dummy);
5504 %}
5505
5506 instruct castII(iRegI dst) %{
5507 match(Set dst (CastII dst));
5508 size(0);
5509 format %{ "# castII of $dst" %}
5510 ins_encode(/*empty*/);
5511 ins_pipe(pipe_class_dummy);
5512 %}
5513
5514 instruct castLL(iRegL dst) %{
5515 match(Set dst (CastLL dst));
5516 size(0);
5517 format %{ "# castLL of $dst" %}
5518 ins_encode(/*empty*/);
5519 ins_pipe(pipe_class_dummy);
5520 %}
5521
5522 instruct castFF(regF dst) %{
5523 match(Set dst (CastFF dst));
5524 size(0);
5525 format %{ "# castFF of $dst" %}
5526 ins_encode(/*empty*/);
5527 ins_pipe(pipe_class_dummy);
5528 %}
5529
5530 instruct castDD(regD dst) %{
5531 match(Set dst (CastDD dst));
5532 size(0);
5533 format %{ "# castDD of $dst" %}
5534 ins_encode(/*empty*/);
5535 ins_pipe(pipe_class_dummy);
5536 %}
5537
5538 instruct castVV(iRegL dst) %{
5539 match(Set dst (CastVV dst));
5540 size(0);
5541 format %{ "# castVV of $dst" %}
5542 ins_encode(/*empty*/);
5543 ins_pipe(pipe_class_dummy);
5544 %}
5545
5546 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5547
5548 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5549 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5550 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5551 size(16);
5552 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5553 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5554 z_enc_cctobool(res));
5555 ins_pipe(pipe_class_dummy);
5556 %}
5557
5558 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5559 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5560 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5561 size(18);
5562 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5563 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5564 z_enc_cctobool(res));
5565 ins_pipe(pipe_class_dummy);
5566 %}
5567
5568 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5569 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5570 predicate(n->as_LoadStore()->barrier_data() == 0);
5571 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5572 size(18);
5573 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5574 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5575 z_enc_cctobool(res));
5576 ins_pipe(pipe_class_dummy);
5577 %}
5578
5579 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5580 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5581 predicate(n->as_LoadStore()->barrier_data() == 0);
5582 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5583 size(16);
5584 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5585 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5586 z_enc_cctobool(res));
5587 ins_pipe(pipe_class_dummy);
5588 %}
5589
5590 instruct compareAndExchangeN(iRegN res, iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, flagsReg cr) %{
5591 match(Set res (CompareAndExchangeN mem_ptr (Binary oldval newval)));
5592 predicate(n->as_LoadStore()->barrier_data() == 0);
5593 effect(TEMP_DEF res, USE mem_ptr, USE_KILL oldval, KILL cr);
5594 format %{ "$res = CompareAndExchangeN $oldval,$newval,$mem_ptr" %}
5595 ins_encode %{
5596 Register Rcomp = reg_to_register_object($oldval$$reg);
5597 Register Rnew = reg_to_register_object($newval$$reg);
5598 Register Raddr = reg_to_register_object($mem_ptr$$reg);
5599 Register Rres = reg_to_register_object($res$$reg);
5600 __ z_lr(Rres, Rcomp);
5601 __ z_cs(Rres, Rnew, 0, Raddr);
5602 %}
5603 ins_pipe(pipe_class_dummy);
5604 %}
5605
5606 instruct compareAndExchangeP(iRegP res, iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5607 match(Set res (CompareAndExchangeP mem_ptr (Binary oldval newval)));
5608 predicate(n->as_LoadStore()->barrier_data() == 0);
5609 effect(TEMP_DEF res, USE mem_ptr, USE_KILL oldval, KILL cr);
5610 format %{ "$res = CompareAndExchangeP $oldval,$newval,$mem_ptr" %}
5611 ins_encode %{
5612 Register Rcomp = reg_to_register_object($oldval$$reg);
5613 Register Rnew = reg_to_register_object($newval$$reg);
5614 Register Raddr = reg_to_register_object($mem_ptr$$reg);
5615 Register Rres = reg_to_register_object($res$$reg);
5616 __ z_lgr(Rres, Rcomp);
5617 __ z_csg(Rres, Rnew, 0, Raddr);
5618 %}
5619 ins_pipe(pipe_class_dummy);
5620 %}
5621
5622 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5623
5624 // Exploit: direct memory arithmetic
5625 // Prereqs: - instructions available
5626 // - instructions guarantee atomicity
5627 // - immediate operand to be added
5628 // - immediate operand is small enough (8-bit signed).
5629 // - result of instruction is not used
5630 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5631 match(Set dummy (GetAndAddI mem src));
5632 effect(KILL cr);
5633 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5634 ins_cost(MEMORY_REF_COST);
5635 size(6);
5636 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5637 opcode(ASI_ZOPC);
5638 ins_encode(z_siyform(mem, src));
5639 ins_pipe(pipe_class_dummy);
5640 %}
5641
5642 // Fallback: direct memory arithmetic not available
5643 // Disadvantages: - CS-Loop required, very expensive.
5644 // - more code generated (26 to xx bytes vs. 6 bytes)
5645 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5646 match(Set dst (GetAndAddI mem src));
5647 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5648 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5649 format %{ "BEGIN ATOMIC {\n\t"
5650 " LGF $dst,[$mem]\n\t"
5651 " AHIK $tmp,$dst,$src\n\t"
5652 " CSY $dst,$tmp,$mem\n\t"
5653 " retry if failed\n\t"
5654 "} END ATOMIC"
5655 %}
5656 ins_encode %{
5657 Register Rdst = $dst$$Register;
5658 Register Rtmp = $tmp$$Register;
5659 int Isrc = $src$$constant;
5660 Label retry;
5661
5662 // Iterate until update with incremented value succeeds.
5663 __ z_lgf(Rdst, $mem$$Address); // current contents
5664 __ bind(retry);
5665 // Calculate incremented value.
5666 if (VM_Version::has_DistinctOpnds()) {
5667 __ z_ahik(Rtmp, Rdst, Isrc);
5668 } else {
5669 __ z_lr(Rtmp, Rdst);
5670 __ z_ahi(Rtmp, Isrc);
5671 }
5672 // Swap into memory location.
5673 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5674 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5675 %}
5676 ins_pipe(pipe_class_dummy);
5677 %}
5678
5679 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5680 match(Set dst (GetAndAddI mem src));
5681 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5682 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5683 format %{ "BEGIN ATOMIC {\n\t"
5684 " LGF $dst,[$mem]\n\t"
5685 " LGR $tmp,$dst\n\t"
5686 " AFI $tmp,$src\n\t"
5687 " CSY $dst,$tmp,$mem\n\t"
5688 " retry if failed\n\t"
5689 "} END ATOMIC"
5690 %}
5691 ins_encode %{
5692 Register Rdst = $dst$$Register;
5693 Register Rtmp = $tmp$$Register;
5694 int Isrc = $src$$constant;
5695 Label retry;
5696
5697 // Iterate until update with incremented value succeeds.
5698 __ z_lgf(Rdst, $mem$$Address); // current contents
5699 __ bind(retry);
5700 // Calculate incremented value.
5701 __ z_lr(Rtmp, Rdst);
5702 __ z_afi(Rtmp, Isrc);
5703 // Swap into memory location.
5704 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5705 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5706 %}
5707 ins_pipe(pipe_class_dummy);
5708 %}
5709
5710 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5711 match(Set dst (GetAndAddI mem src));
5712 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5713 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5714 format %{ "BEGIN ATOMIC {\n\t"
5715 " LGF $dst,[$mem]\n\t"
5716 " ARK $tmp,$dst,$src\n\t"
5717 " CSY $dst,$tmp,$mem\n\t"
5718 " retry if failed\n\t"
5719 "} END ATOMIC"
5720 %}
5721 ins_encode %{
5722 Register Rsrc = $src$$Register;
5723 Register Rdst = $dst$$Register;
5724 Register Rtmp = $tmp$$Register;
5725 Label retry;
5726
5727 // Iterate until update with incremented value succeeds.
5728 __ z_lgf(Rdst, $mem$$Address); // current contents
5729 __ bind(retry);
5730 // Calculate incremented value.
5731 if (VM_Version::has_DistinctOpnds()) {
5732 __ z_ark(Rtmp, Rdst, Rsrc);
5733 } else {
5734 __ z_lr(Rtmp, Rdst);
5735 __ z_ar(Rtmp, Rsrc);
5736 }
5737 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5738 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5739 %}
5740 ins_pipe(pipe_class_dummy);
5741 %}
5742
5743
5744 // Exploit: direct memory arithmetic
5745 // Prereqs: - instructions available
5746 // - instructions guarantee atomicity
5747 // - immediate operand to be added
5748 // - immediate operand is small enough (8-bit signed).
5749 // - result of instruction is not used
5750 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5751 match(Set dummy (GetAndAddL mem src));
5752 effect(KILL cr);
5753 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5754 ins_cost(MEMORY_REF_COST);
5755 size(6);
5756 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5757 opcode(AGSI_ZOPC);
5758 ins_encode(z_siyform(mem, src));
5759 ins_pipe(pipe_class_dummy);
5760 %}
5761
5762 // Fallback: direct memory arithmetic not available
5763 // Disadvantages: - CS-Loop required, very expensive.
5764 // - more code generated (26 to xx bytes vs. 6 bytes)
5765 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5766 match(Set dst (GetAndAddL mem src));
5767 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5768 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5769 format %{ "BEGIN ATOMIC {\n\t"
5770 " LG $dst,[$mem]\n\t"
5771 " AGHIK $tmp,$dst,$src\n\t"
5772 " CSG $dst,$tmp,$mem\n\t"
5773 " retry if failed\n\t"
5774 "} END ATOMIC"
5775 %}
5776 ins_encode %{
5777 Register Rdst = $dst$$Register;
5778 Register Rtmp = $tmp$$Register;
5779 int Isrc = $src$$constant;
5780 Label retry;
5781
5782 // Iterate until update with incremented value succeeds.
5783 __ z_lg(Rdst, $mem$$Address); // current contents
5784 __ bind(retry);
5785 // Calculate incremented value.
5786 if (VM_Version::has_DistinctOpnds()) {
5787 __ z_aghik(Rtmp, Rdst, Isrc);
5788 } else {
5789 __ z_lgr(Rtmp, Rdst);
5790 __ z_aghi(Rtmp, Isrc);
5791 }
5792 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5793 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5794 %}
5795 ins_pipe(pipe_class_dummy);
5796 %}
5797
5798 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5799 match(Set dst (GetAndAddL mem src));
5800 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5801 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5802 format %{ "BEGIN ATOMIC {\n\t"
5803 " LG $dst,[$mem]\n\t"
5804 " LGR $tmp,$dst\n\t"
5805 " AGFI $tmp,$src\n\t"
5806 " CSG $dst,$tmp,$mem\n\t"
5807 " retry if failed\n\t"
5808 "} END ATOMIC"
5809 %}
5810 ins_encode %{
5811 Register Rdst = $dst$$Register;
5812 Register Rtmp = $tmp$$Register;
5813 int Isrc = $src$$constant;
5814 Label retry;
5815
5816 // Iterate until update with incremented value succeeds.
5817 __ z_lg(Rdst, $mem$$Address); // current contents
5818 __ bind(retry);
5819 // Calculate incremented value.
5820 __ z_lgr(Rtmp, Rdst);
5821 __ z_agfi(Rtmp, Isrc);
5822 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5823 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5824 %}
5825 ins_pipe(pipe_class_dummy);
5826 %}
5827
5828 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5829 match(Set dst (GetAndAddL mem src));
5830 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5831 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5832 format %{ "BEGIN ATOMIC {\n\t"
5833 " LG $dst,[$mem]\n\t"
5834 " AGRK $tmp,$dst,$src\n\t"
5835 " CSG $dst,$tmp,$mem\n\t"
5836 " retry if failed\n\t"
5837 "} END ATOMIC"
5838 %}
5839 ins_encode %{
5840 Register Rsrc = $src$$Register;
5841 Register Rdst = $dst$$Register;
5842 Register Rtmp = $tmp$$Register;
5843 Label retry;
5844
5845 // Iterate until update with incremented value succeeds.
5846 __ z_lg(Rdst, $mem$$Address); // current contents
5847 __ bind(retry);
5848 // Calculate incremented value.
5849 if (VM_Version::has_DistinctOpnds()) {
5850 __ z_agrk(Rtmp, Rdst, Rsrc);
5851 } else {
5852 __ z_lgr(Rtmp, Rdst);
5853 __ z_agr(Rtmp, Rsrc);
5854 }
5855 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5856 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5857 %}
5858 ins_pipe(pipe_class_dummy);
5859 %}
5860
5861 // Increment value in memory, save old value in dst.
5862 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5863 match(Set dst (GetAndAddI mem src));
5864 predicate(VM_Version::has_LoadAndALUAtomicV1());
5865 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5866 size(6);
5867 format %{ "LAA $dst,$src,[$mem]" %}
5868 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5869 ins_pipe(pipe_class_dummy);
5870 %}
5871
5872 // Increment value in memory, save old value in dst.
5873 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5874 match(Set dst (GetAndAddL mem src));
5875 predicate(VM_Version::has_LoadAndALUAtomicV1());
5876 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5877 size(6);
5878 format %{ "LAAG $dst,$src,[$mem]" %}
5879 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5880 ins_pipe(pipe_class_dummy);
5881 %}
5882
5883
5884 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5885 match(Set dst (GetAndSetI mem dst));
5886 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5887 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5888 ins_encode(z_enc_SwapI(mem, dst, tmp));
5889 ins_pipe(pipe_class_dummy);
5890 %}
5891
5892 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5893 match(Set dst (GetAndSetL mem dst));
5894 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5895 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5896 ins_encode(z_enc_SwapL(mem, dst, tmp));
5897 ins_pipe(pipe_class_dummy);
5898 %}
5899
5900 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5901 predicate(n->as_LoadStore()->barrier_data() == 0);
5902 match(Set dst (GetAndSetN mem dst));
5903 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5904 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5905 ins_encode(z_enc_SwapI(mem, dst, tmp));
5906 ins_pipe(pipe_class_dummy);
5907 %}
5908
5909 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5910 match(Set dst (GetAndSetP mem dst));
5911 predicate(n->as_LoadStore()->barrier_data() == 0);
5912 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5913 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5914 ins_encode(z_enc_SwapL(mem, dst, tmp));
5915 ins_pipe(pipe_class_dummy);
5916 %}
5917
5918
5919 //----------Arithmetic Instructions--------------------------------------------
5920
5921 // The rules are sorted by right operand type and operand length. Please keep
5922 // it that way.
5923 // Left operand type is always reg. Left operand len is I, L, P
5924 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5925 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5926
5927 // ADD
5928
5929 // REG = REG + REG
5930
5931 // Register Addition
5932 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5933 match(Set dst (AddI dst src));
5934 effect(KILL cr);
5935 // TODO: s390 port size(FIXED_SIZE);
5936 format %{ "AR $dst,$src\t # int CISC ALU" %}
5937 opcode(AR_ZOPC);
5938 ins_encode(z_rrform(dst, src));
5939 ins_pipe(pipe_class_dummy);
5940 %}
5941
5942 // Avoid use of LA(Y) for general ALU operation.
5943 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5944 match(Set dst (AddI src1 src2));
5945 effect(KILL cr);
5946 predicate(VM_Version::has_DistinctOpnds());
5947 ins_cost(DEFAULT_COST);
5948 size(4);
5949 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5950 opcode(ARK_ZOPC);
5951 ins_encode(z_rrfform(dst, src1, src2));
5952 ins_pipe(pipe_class_dummy);
5953 %}
5954
5955 // REG = REG + IMM
5956
5957 // Avoid use of LA(Y) for general ALU operation.
5958 // Immediate Addition
5959 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5960 match(Set dst (AddI dst con));
5961 effect(KILL cr);
5962 ins_cost(DEFAULT_COST);
5963 // TODO: s390 port size(FIXED_SIZE);
5964 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5965 opcode(AHI_ZOPC);
5966 ins_encode(z_riform_signed(dst, con));
5967 ins_pipe(pipe_class_dummy);
5968 %}
5969
5970 // Avoid use of LA(Y) for general ALU operation.
5971 // Immediate Addition
5972 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5973 match(Set dst (AddI src con));
5974 effect(KILL cr);
5975 predicate( VM_Version::has_DistinctOpnds());
5976 ins_cost(DEFAULT_COST);
5977 // TODO: s390 port size(FIXED_SIZE);
5978 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5979 opcode(AHIK_ZOPC);
5980 ins_encode(z_rieform_d(dst, src, con));
5981 ins_pipe(pipe_class_dummy);
5982 %}
5983
5984 // Immediate Addition
5985 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5986 match(Set dst (AddI dst src));
5987 effect(KILL cr);
5988 ins_cost(DEFAULT_COST_HIGH);
5989 size(6);
5990 format %{ "AFI $dst,$src" %}
5991 opcode(AFI_ZOPC);
5992 ins_encode(z_rilform_signed(dst, src));
5993 ins_pipe(pipe_class_dummy);
5994 %}
5995
5996 // Immediate Addition
5997 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5998 match(Set dst (AddI src con));
5999 predicate(PreferLAoverADD);
6000 ins_cost(DEFAULT_COST_LOW);
6001 size(4);
6002 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
6003 opcode(LA_ZOPC);
6004 ins_encode(z_rxform_imm_reg(dst, con, src));
6005 ins_pipe(pipe_class_dummy);
6006 %}
6007
6008 // Immediate Addition
6009 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
6010 match(Set dst (AddI src con));
6011 predicate(PreferLAoverADD);
6012 ins_cost(DEFAULT_COST);
6013 size(6);
6014 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
6015 opcode(LAY_ZOPC);
6016 ins_encode(z_rxyform_imm_reg(dst, con, src));
6017 ins_pipe(pipe_class_dummy);
6018 %}
6019
6020 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
6021 match(Set dst (AddI (AddI src1 src2) con));
6022 predicate( PreferLAoverADD);
6023 ins_cost(DEFAULT_COST_LOW);
6024 size(4);
6025 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
6026 opcode(LA_ZOPC);
6027 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6028 ins_pipe(pipe_class_dummy);
6029 %}
6030
6031 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
6032 match(Set dst (AddI (AddI src1 src2) con));
6033 predicate(PreferLAoverADD);
6034 ins_cost(DEFAULT_COST);
6035 size(6);
6036 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
6037 opcode(LAY_ZOPC);
6038 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6039 ins_pipe(pipe_class_dummy);
6040 %}
6041
6042 // REG = REG + MEM
6043
6044 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6045 match(Set dst (AddI dst (LoadI src)));
6046 effect(KILL cr);
6047 ins_cost(MEMORY_REF_COST);
6048 // TODO: s390 port size(VARIABLE_SIZE);
6049 format %{ "A(Y) $dst, $src\t # int" %}
6050 opcode(AY_ZOPC, A_ZOPC);
6051 ins_encode(z_form_rt_mem_opt(dst, src));
6052 ins_pipe(pipe_class_dummy);
6053 %}
6054
6055 // MEM = MEM + IMM
6056
6057 // Add Immediate to 4-byte memory operand and result
6058 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
6059 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
6060 effect(KILL cr);
6061 predicate(VM_Version::has_MemWithImmALUOps());
6062 ins_cost(MEMORY_REF_COST);
6063 size(6);
6064 format %{ "ASI $mem,$src\t # direct mem add 4" %}
6065 opcode(ASI_ZOPC);
6066 ins_encode(z_siyform(mem, src));
6067 ins_pipe(pipe_class_dummy);
6068 %}
6069
6070
6071 //
6072
6073 // REG = REG + REG
6074
6075 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
6076 match(Set dst (AddL dst (ConvI2L src)));
6077 effect(KILL cr);
6078 size(4);
6079 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
6080 opcode(AGFR_ZOPC);
6081 ins_encode(z_rreform(dst, src));
6082 ins_pipe(pipe_class_dummy);
6083 %}
6084
6085 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6086 match(Set dst (AddL dst src));
6087 effect(KILL cr);
6088 // TODO: s390 port size(FIXED_SIZE);
6089 format %{ "AGR $dst, $src\t # long CISC ALU" %}
6090 opcode(AGR_ZOPC);
6091 ins_encode(z_rreform(dst, src));
6092 ins_pipe(pipe_class_dummy);
6093 %}
6094
6095 // Avoid use of LA(Y) for general ALU operation.
6096 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6097 match(Set dst (AddL src1 src2));
6098 effect(KILL cr);
6099 predicate(VM_Version::has_DistinctOpnds());
6100 ins_cost(DEFAULT_COST);
6101 size(4);
6102 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
6103 opcode(AGRK_ZOPC);
6104 ins_encode(z_rrfform(dst, src1, src2));
6105 ins_pipe(pipe_class_dummy);
6106 %}
6107
6108 // REG = REG + IMM
6109
6110 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
6111 match(Set dst (AddL src con));
6112 predicate( PreferLAoverADD);
6113 ins_cost(DEFAULT_COST_LOW);
6114 size(4);
6115 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
6116 opcode(LA_ZOPC);
6117 ins_encode(z_rxform_imm_reg(dst, con, src));
6118 ins_pipe(pipe_class_dummy);
6119 %}
6120
6121 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
6122 match(Set dst (AddL src con));
6123 predicate(PreferLAoverADD);
6124 ins_cost(DEFAULT_COST);
6125 size(6);
6126 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
6127 opcode(LAY_ZOPC);
6128 ins_encode(z_rxyform_imm_reg(dst, con, src));
6129 ins_pipe(pipe_class_dummy);
6130 %}
6131
6132 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
6133 match(Set dst (AddL dst con));
6134 effect(KILL cr);
6135 ins_cost(DEFAULT_COST_HIGH);
6136 size(6);
6137 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
6138 opcode(AGFI_ZOPC);
6139 ins_encode(z_rilform_signed(dst, con));
6140 ins_pipe(pipe_class_dummy);
6141 %}
6142
6143 // Avoid use of LA(Y) for general ALU operation.
6144 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6145 match(Set dst (AddL dst con));
6146 effect(KILL cr);
6147 ins_cost(DEFAULT_COST);
6148 // TODO: s390 port size(FIXED_SIZE);
6149 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6150 opcode(AGHI_ZOPC);
6151 ins_encode(z_riform_signed(dst, con));
6152 ins_pipe(pipe_class_dummy);
6153 %}
6154
6155 // Avoid use of LA(Y) for general ALU operation.
6156 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6157 match(Set dst (AddL src con));
6158 effect(KILL cr);
6159 predicate( VM_Version::has_DistinctOpnds());
6160 ins_cost(DEFAULT_COST);
6161 size(6);
6162 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6163 opcode(AGHIK_ZOPC);
6164 ins_encode(z_rieform_d(dst, src, con));
6165 ins_pipe(pipe_class_dummy);
6166 %}
6167
6168 // REG = REG + MEM
6169
6170 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6171 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6172 effect(KILL cr);
6173 ins_cost(MEMORY_REF_COST);
6174 size(Z_DISP3_SIZE);
6175 format %{ "AGF $dst, $src\t # long/int" %}
6176 opcode(AGF_ZOPC, AGF_ZOPC);
6177 ins_encode(z_form_rt_mem_opt(dst, src));
6178 ins_pipe(pipe_class_dummy);
6179 %}
6180
6181 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6182 match(Set dst (AddL dst (LoadL src)));
6183 effect(KILL cr);
6184 ins_cost(MEMORY_REF_COST);
6185 size(Z_DISP3_SIZE);
6186 format %{ "AG $dst, $src\t # long" %}
6187 opcode(AG_ZOPC, AG_ZOPC);
6188 ins_encode(z_form_rt_mem_opt(dst, src));
6189 ins_pipe(pipe_class_dummy);
6190 %}
6191
6192 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6193 match(Set dst (AddL (AddL src1 src2) con));
6194 predicate( PreferLAoverADD);
6195 ins_cost(DEFAULT_COST_LOW);
6196 size(4);
6197 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6198 opcode(LA_ZOPC);
6199 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6200 ins_pipe(pipe_class_dummy);
6201 %}
6202
6203 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6204 match(Set dst (AddL (AddL src1 src2) con));
6205 predicate(PreferLAoverADD);
6206 ins_cost(DEFAULT_COST);
6207 size(6);
6208 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6209 opcode(LAY_ZOPC);
6210 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6211 ins_pipe(pipe_class_dummy);
6212 %}
6213
6214 // MEM = MEM + IMM
6215
6216 // Add Immediate to 8-byte memory operand and result.
6217 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6218 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6219 effect(KILL cr);
6220 predicate(VM_Version::has_MemWithImmALUOps());
6221 ins_cost(MEMORY_REF_COST);
6222 size(6);
6223 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6224 opcode(AGSI_ZOPC);
6225 ins_encode(z_siyform(mem, src));
6226 ins_pipe(pipe_class_dummy);
6227 %}
6228
6229
6230 // REG = REG + REG
6231
6232 // Ptr Addition
6233 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6234 match(Set dst (AddP src1 src2));
6235 predicate( PreferLAoverADD);
6236 ins_cost(DEFAULT_COST);
6237 size(4);
6238 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6239 opcode(LA_ZOPC);
6240 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6241 ins_pipe(pipe_class_dummy);
6242 %}
6243
6244 // Ptr Addition
6245 // Avoid use of LA(Y) for general ALU operation.
6246 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6247 match(Set dst (AddP dst src));
6248 effect(KILL cr);
6249 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6250 ins_cost(DEFAULT_COST);
6251 // TODO: s390 port size(FIXED_SIZE);
6252 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6253 opcode(ALGR_ZOPC);
6254 ins_encode(z_rreform(dst, src));
6255 ins_pipe(pipe_class_dummy);
6256 %}
6257
6258 // Ptr Addition
6259 // Avoid use of LA(Y) for general ALU operation.
6260 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6261 match(Set dst (AddP src1 src2));
6262 effect(KILL cr);
6263 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6264 ins_cost(DEFAULT_COST);
6265 // TODO: s390 port size(FIXED_SIZE);
6266 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6267 opcode(ALGRK_ZOPC);
6268 ins_encode(z_rrfform(dst, src1, src2));
6269 ins_pipe(pipe_class_dummy);
6270 %}
6271
6272 // REG = REG + IMM
6273
6274 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6275 match(Set dst (AddP src con));
6276 predicate( PreferLAoverADD);
6277 ins_cost(DEFAULT_COST_LOW);
6278 size(4);
6279 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6280 opcode(LA_ZOPC);
6281 ins_encode(z_rxform_imm_reg(dst, con, src));
6282 ins_pipe(pipe_class_dummy);
6283 %}
6284
6285 // Avoid use of LA(Y) for general ALU operation.
6286 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6287 match(Set dst (AddP dst src));
6288 effect(KILL cr);
6289 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6290 ins_cost(DEFAULT_COST);
6291 // TODO: s390 port size(FIXED_SIZE);
6292 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6293 opcode(AGHI_ZOPC);
6294 ins_encode(z_riform_signed(dst, src));
6295 ins_pipe(pipe_class_dummy);
6296 %}
6297
6298 // Avoid use of LA(Y) for general ALU operation.
6299 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6300 match(Set dst (AddP src con));
6301 effect(KILL cr);
6302 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6303 ins_cost(DEFAULT_COST);
6304 // TODO: s390 port size(FIXED_SIZE);
6305 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6306 opcode(ALGHSIK_ZOPC);
6307 ins_encode(z_rieform_d(dst, src, con));
6308 ins_pipe(pipe_class_dummy);
6309 %}
6310
6311 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6312 match(Set dst (AddP src con));
6313 predicate(PreferLAoverADD);
6314 ins_cost(DEFAULT_COST);
6315 size(6);
6316 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6317 opcode(LAY_ZOPC);
6318 ins_encode(z_rxyform_imm_reg(dst, con, src));
6319 ins_pipe(pipe_class_dummy);
6320 %}
6321
6322 // Pointer Immediate Addition
6323 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6324 match(Set dst (AddP dst src));
6325 effect(KILL cr);
6326 ins_cost(DEFAULT_COST_HIGH);
6327 // TODO: s390 port size(FIXED_SIZE);
6328 format %{ "AGFI $dst,$src\t # ptr" %}
6329 opcode(AGFI_ZOPC);
6330 ins_encode(z_rilform_signed(dst, src));
6331 ins_pipe(pipe_class_dummy);
6332 %}
6333
6334 // REG = REG1 + REG2 + IMM
6335
6336 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6337 match(Set dst (AddP (AddP src1 src2) con));
6338 predicate( PreferLAoverADD);
6339 ins_cost(DEFAULT_COST_LOW);
6340 size(4);
6341 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6342 opcode(LA_ZOPC);
6343 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6344 ins_pipe(pipe_class_dummy);
6345 %}
6346
6347 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6348 match(Set dst (AddP (AddP src1 src2) con));
6349 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6350 ins_cost(DEFAULT_COST_LOW);
6351 size(4);
6352 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6353 opcode(LA_ZOPC);
6354 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6355 ins_pipe(pipe_class_dummy);
6356 %}
6357
6358 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6359 match(Set dst (AddP (AddP src1 src2) con));
6360 predicate(PreferLAoverADD);
6361 ins_cost(DEFAULT_COST);
6362 // TODO: s390 port size(FIXED_SIZE);
6363 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6364 opcode(LAY_ZOPC);
6365 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6366 ins_pipe(pipe_class_dummy);
6367 %}
6368
6369 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6370 match(Set dst (AddP (AddP src1 src2) con));
6371 predicate( PreferLAoverADD && CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
6372 ins_cost(DEFAULT_COST);
6373 // TODO: s390 port size(FIXED_SIZE);
6374 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6375 opcode(LAY_ZOPC);
6376 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6377 ins_pipe(pipe_class_dummy);
6378 %}
6379
6380 // MEM = MEM + IMM
6381
6382 // Add Immediate to 8-byte memory operand and result
6383 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6384 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6385 effect(KILL cr);
6386 predicate(VM_Version::has_MemWithImmALUOps() && n->as_LoadStore()->barrier_data() == 0);
6387 ins_cost(MEMORY_REF_COST);
6388 size(6);
6389 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6390 opcode(AGSI_ZOPC);
6391 ins_encode(z_siyform(mem, src));
6392 ins_pipe(pipe_class_dummy);
6393 %}
6394
6395 // SUB
6396
6397 // Register Subtraction
6398 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6399 match(Set dst (SubI dst src));
6400 effect(KILL cr);
6401 // TODO: s390 port size(FIXED_SIZE);
6402 format %{ "SR $dst,$src\t # int CISC ALU" %}
6403 opcode(SR_ZOPC);
6404 ins_encode(z_rrform(dst, src));
6405 ins_pipe(pipe_class_dummy);
6406 %}
6407
6408 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6409 match(Set dst (SubI src1 src2));
6410 effect(KILL cr);
6411 predicate(VM_Version::has_DistinctOpnds());
6412 ins_cost(DEFAULT_COST);
6413 size(4);
6414 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6415 opcode(SRK_ZOPC);
6416 ins_encode(z_rrfform(dst, src1, src2));
6417 ins_pipe(pipe_class_dummy);
6418 %}
6419
6420 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6421 match(Set dst (SubI dst (LoadI src)));
6422 effect(KILL cr);
6423 ins_cost(MEMORY_REF_COST);
6424 // TODO: s390 port size(VARIABLE_SIZE);
6425 format %{ "S(Y) $dst, $src\t # int" %}
6426 opcode(SY_ZOPC, S_ZOPC);
6427 ins_encode(z_form_rt_mem_opt(dst, src));
6428 ins_pipe(pipe_class_dummy);
6429 %}
6430
6431 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6432 match(Set dst (SubI zero src));
6433 effect(KILL cr);
6434 size(2);
6435 format %{ "NEG $dst, $src" %}
6436 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6437 ins_pipe(pipe_class_dummy);
6438 %}
6439
6440 //
6441
6442 // Long subtraction
6443 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6444 match(Set dst (SubL dst src));
6445 effect(KILL cr);
6446 // TODO: s390 port size(FIXED_SIZE);
6447 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6448 opcode(SGR_ZOPC);
6449 ins_encode(z_rreform(dst, src));
6450 ins_pipe(pipe_class_dummy);
6451 %}
6452
6453 // Avoid use of LA(Y) for general ALU operation.
6454 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6455 match(Set dst (SubL src1 src2));
6456 effect(KILL cr);
6457 predicate(VM_Version::has_DistinctOpnds());
6458 ins_cost(DEFAULT_COST);
6459 size(4);
6460 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6461 opcode(SGRK_ZOPC);
6462 ins_encode(z_rrfform(dst, src1, src2));
6463 ins_pipe(pipe_class_dummy);
6464 %}
6465
6466 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6467 match(Set dst (SubL dst (ConvI2L src)));
6468 effect(KILL cr);
6469 size(4);
6470 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6471 opcode(SGFR_ZOPC);
6472 ins_encode(z_rreform(dst, src));
6473 ins_pipe(pipe_class_dummy);
6474 %}
6475
6476 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6477 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6478 effect(KILL cr);
6479 ins_cost(MEMORY_REF_COST);
6480 size(Z_DISP3_SIZE);
6481 format %{ "SGF $dst, $src\t # long/int" %}
6482 opcode(SGF_ZOPC, SGF_ZOPC);
6483 ins_encode(z_form_rt_mem_opt(dst, src));
6484 ins_pipe(pipe_class_dummy);
6485 %}
6486
6487 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6488 match(Set dst (SubL dst (LoadL src)));
6489 effect(KILL cr);
6490 ins_cost(MEMORY_REF_COST);
6491 size(Z_DISP3_SIZE);
6492 format %{ "SG $dst, $src\t # long" %}
6493 opcode(SG_ZOPC, SG_ZOPC);
6494 ins_encode(z_form_rt_mem_opt(dst, src));
6495 ins_pipe(pipe_class_dummy);
6496 %}
6497
6498 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6499
6500 // MUL
6501
6502 // Register Multiplication
6503 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6504 match(Set dst (MulI dst src));
6505 ins_cost(DEFAULT_COST);
6506 size(4);
6507 format %{ "MSR $dst, $src" %}
6508 opcode(MSR_ZOPC);
6509 ins_encode(z_rreform(dst, src));
6510 ins_pipe(pipe_class_dummy);
6511 %}
6512
6513 // Immediate Multiplication
6514 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6515 match(Set dst (MulI dst con));
6516 ins_cost(DEFAULT_COST);
6517 // TODO: s390 port size(FIXED_SIZE);
6518 format %{ "MHI $dst,$con" %}
6519 opcode(MHI_ZOPC);
6520 ins_encode(z_riform_signed(dst,con));
6521 ins_pipe(pipe_class_dummy);
6522 %}
6523
6524 // Immediate (32bit) Multiplication
6525 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6526 match(Set dst (MulI dst con));
6527 ins_cost(DEFAULT_COST);
6528 size(6);
6529 format %{ "MSFI $dst,$con" %}
6530 opcode(MSFI_ZOPC);
6531 ins_encode(z_rilform_signed(dst,con));
6532 ins_pipe(pipe_class_dummy);
6533 %}
6534
6535 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6536 match(Set dst (MulI dst (LoadI src)));
6537 ins_cost(MEMORY_REF_COST);
6538 // TODO: s390 port size(VARIABLE_SIZE);
6539 format %{ "MS(Y) $dst, $src\t # int" %}
6540 opcode(MSY_ZOPC, MS_ZOPC);
6541 ins_encode(z_form_rt_mem_opt(dst, src));
6542 ins_pipe(pipe_class_dummy);
6543 %}
6544
6545 //
6546
6547 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6548 match(Set dst (MulL dst (ConvI2L src)));
6549 ins_cost(DEFAULT_COST);
6550 // TODO: s390 port size(FIXED_SIZE);
6551 format %{ "MSGFR $dst $src\t # long/int" %}
6552 opcode(MSGFR_ZOPC);
6553 ins_encode(z_rreform(dst, src));
6554 ins_pipe(pipe_class_dummy);
6555 %}
6556
6557 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6558 match(Set dst (MulL dst src));
6559 ins_cost(DEFAULT_COST);
6560 size(4);
6561 format %{ "MSGR $dst $src\t # long" %}
6562 opcode(MSGR_ZOPC);
6563 ins_encode(z_rreform(dst, src));
6564 ins_pipe(pipe_class_dummy);
6565 %}
6566
6567 // Immediate Multiplication
6568 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6569 match(Set dst (MulL dst src));
6570 ins_cost(DEFAULT_COST);
6571 // TODO: s390 port size(FIXED_SIZE);
6572 format %{ "MGHI $dst,$src\t # long" %}
6573 opcode(MGHI_ZOPC);
6574 ins_encode(z_riform_signed(dst, src));
6575 ins_pipe(pipe_class_dummy);
6576 %}
6577
6578 // Immediate (32bit) Multiplication
6579 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6580 match(Set dst (MulL dst con));
6581 ins_cost(DEFAULT_COST);
6582 size(6);
6583 format %{ "MSGFI $dst,$con" %}
6584 opcode(MSGFI_ZOPC);
6585 ins_encode(z_rilform_signed(dst,con));
6586 ins_pipe(pipe_class_dummy);
6587 %}
6588
6589 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6590 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6591 ins_cost(MEMORY_REF_COST);
6592 size(Z_DISP3_SIZE);
6593 format %{ "MSGF $dst, $src\t # long" %}
6594 opcode(MSGF_ZOPC, MSGF_ZOPC);
6595 ins_encode(z_form_rt_mem_opt(dst, src));
6596 ins_pipe(pipe_class_dummy);
6597 %}
6598
6599 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6600 match(Set dst (MulL dst (LoadL src)));
6601 ins_cost(MEMORY_REF_COST);
6602 size(Z_DISP3_SIZE);
6603 format %{ "MSG $dst, $src\t # long" %}
6604 opcode(MSG_ZOPC, MSG_ZOPC);
6605 ins_encode(z_form_rt_mem_opt(dst, src));
6606 ins_pipe(pipe_class_dummy);
6607 %}
6608
6609 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6610 match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6611 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6612 ins_cost(7*DEFAULT_COST);
6613 // TODO: s390 port size(VARIABLE_SIZE);
6614 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6615 ins_encode%{
6616 Register dst = $Rdst$$Register;
6617 Register src1 = $Rsrc1$$Register;
6618 Register src2 = $Rsrc2$$Register;
6619 Register tmp1 = $Rtmp1$$Register;
6620 Register tmp2 = $Rdst$$Register;
6621 // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6622 // implementing mulhs(a,b) = mulhu(a,b) - (a & (b>>63)) - (b & (a>>63))
6623 __ z_srag(tmp2, src1, 63); // a>>63
6624 __ z_srag(tmp1, src2, 63); // b>>63
6625 __ z_ngr(tmp2, src2); // b & (a>>63)
6626 __ z_ngr(tmp1, src1); // a & (b>>63)
6627 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63)))
6628 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1),
6629 // multiplicand is taken from oddReg (src1), multiplier in src2.
6630 __ z_sgr(dst, tmp1);
6631 %}
6632 ins_pipe(pipe_class_dummy);
6633 %}
6634
6635 // DIV
6636
6637 // Integer DIVMOD with Register, both quotient and mod results
6638 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6639 match(DivModI dst1src1 src2);
6640 effect(KILL cr);
6641 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6642 size((VM_Version::has_CompareBranch() ? 24 : 26));
6643 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6644 ins_encode %{
6645 Register d1s1 = $dst1src1$$Register;
6646 Register d2 = $dst2$$Register;
6647 Register s2 = $src2$$Register;
6648
6649 assert_different_registers(d1s1, s2);
6650
6651 Label do_div, done_div;
6652 if (VM_Version::has_CompareBranch()) {
6653 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6654 } else {
6655 __ z_chi(s2, -1);
6656 __ z_brne(do_div);
6657 }
6658 __ z_lcr(d1s1, d1s1);
6659 __ clear_reg(d2, false, false);
6660 __ z_bru(done_div);
6661 __ bind(do_div);
6662 __ z_lgfr(d1s1, d1s1);
6663 __ z_dsgfr(d2, s2);
6664 __ bind(done_div);
6665 %}
6666 ins_pipe(pipe_class_dummy);
6667 %}
6668
6669
6670 // Register Division
6671 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6672 match(Set dst (DivI src1 src2));
6673 effect(KILL tmp, KILL cr);
6674 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6675 size((VM_Version::has_CompareBranch() ? 20 : 22));
6676 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6677 ins_encode %{
6678 Register a = $src1$$Register;
6679 Register b = $src2$$Register;
6680 Register t = $dst$$Register;
6681
6682 assert_different_registers(t, b);
6683
6684 Label do_div, done_div;
6685 if (VM_Version::has_CompareBranch()) {
6686 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6687 } else {
6688 __ z_chi(b, -1);
6689 __ z_brne(do_div);
6690 }
6691 __ z_lcr(t, a);
6692 __ z_bru(done_div);
6693 __ bind(do_div);
6694 __ z_lgfr(t, a);
6695 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6696 __ bind(done_div);
6697 %}
6698 ins_pipe(pipe_class_dummy);
6699 %}
6700
6701 // Immediate Division
6702 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6703 match(Set dst (DivI src1 src2));
6704 effect(KILL tmp, KILL cr); // R0 is killed, too.
6705 ins_cost(2 * DEFAULT_COST);
6706 // TODO: s390 port size(VARIABLE_SIZE);
6707 format %{ "DIV_const $dst,$src1,$src2" %}
6708 ins_encode %{
6709 // No sign extension of Rdividend needed here.
6710 if ($src2$$constant != -1) {
6711 __ z_lghi(Z_R0_scratch, $src2$$constant);
6712 __ z_lgfr($dst$$Register, $src1$$Register);
6713 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6714 } else {
6715 __ z_lcr($dst$$Register, $src1$$Register);
6716 }
6717 %}
6718 ins_pipe(pipe_class_dummy);
6719 %}
6720
6721 // Unsigned Integer Register Division
6722 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6723 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6724 instruct udivI_reg_reg(roddRegI r5_rodd_dst, iRegI src2, revenRegI r4_reven_tmp, flagsReg cr) %{
6725 match(Set r5_rodd_dst (UDivI r5_rodd_dst src2));
6726 effect(TEMP r4_reven_tmp, KILL cr);
6727 // TODO: size(4);
6728 format %{ "UDIV $r5_rodd_dst,$r5_rodd_dst,$src2" %}
6729 ins_encode %{
6730 Register b = $src2$$Register;
6731 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6732 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6733 assert_different_registers(r4_reven_tmp, r5_rodd_dst, b);
6734 assert(r4_reven_tmp->successor() == r5_rodd_dst, "even-odd pair required for the instruction");
6735
6736 __ block_comment("unsigned_div_int {");
6737 __ z_lhi(r4_reven_tmp, 0); // make upper 32bits 0
6738 __ z_dlr(r4_reven_tmp, b);
6739 __ block_comment("} unsigned_div_int");
6740 %}
6741 ins_pipe(pipe_class_dummy);
6742 %}
6743
6744 // Long DIVMOD with Register, both quotient and mod results
6745 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6746 match(DivModL dst1src1 src2);
6747 effect(KILL cr);
6748 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6749 size((VM_Version::has_CompareBranch() ? 22 : 24));
6750 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6751 ins_encode %{
6752 Register d1s1 = $dst1src1$$Register;
6753 Register d2 = $dst2$$Register;
6754 Register s2 = $src2$$Register;
6755
6756 Label do_div, done_div;
6757 if (VM_Version::has_CompareBranch()) {
6758 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6759 } else {
6760 __ z_cghi(s2, -1);
6761 __ z_brne(do_div);
6762 }
6763 __ z_lcgr(d1s1, d1s1);
6764 // indicate unused result
6765 (void) __ clear_reg(d2, true, false);
6766 __ z_bru(done_div);
6767 __ bind(do_div);
6768 __ z_dsgr(d2, s2);
6769 __ bind(done_div);
6770 %}
6771 ins_pipe(pipe_class_dummy);
6772 %}
6773
6774 // Register Long Division
6775 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6776 match(Set dst (DivL dst src));
6777 effect(KILL tmp, KILL cr);
6778 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6779 size((VM_Version::has_CompareBranch() ? 18 : 20));
6780 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6781 ins_encode %{
6782 Register b = $src$$Register;
6783 Register t = $dst$$Register;
6784
6785 Label done_div;
6786 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6787 if (VM_Version::has_CompareBranch()) {
6788 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6789 } else {
6790 __ z_cghi(b, -1);
6791 __ z_bre(done_div);
6792 }
6793 __ z_lcgr(t, t); // Restore sign.
6794 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6795 __ bind(done_div);
6796 %}
6797 ins_pipe(pipe_class_dummy);
6798 %}
6799
6800 // Register Unsigned Long Division
6801 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6802 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6803 instruct udivL_reg_reg(roddRegL r5_rodd_dst, iRegL src, revenRegL r4_reven_tmp, flagsReg cr) %{
6804 match(Set r5_rodd_dst (UDivL r5_rodd_dst src));
6805 effect(TEMP r4_reven_tmp, KILL cr);
6806 ins_cost(DEFAULT_COST);
6807 // TODO: size(4);
6808 format %{ "UDIVG $r5_rodd_dst,$r5_rodd_dst,$src" %}
6809 ins_encode %{
6810 Register b = $src$$Register;
6811 Register r5_rodd_dst = $r5_rodd_dst$$Register;
6812 Register r4_reven_tmp = $r4_reven_tmp$$Register;
6813 assert_different_registers(r5_rodd_dst, r4_reven_tmp, b);
6814 __ block_comment("unsigned_div_long {");
6815 __ z_lghi(r4_reven_tmp, 0); // make upper 64bits 0
6816 __ z_dlgr(r4_reven_tmp, b);
6817 __ block_comment("} unsigned_div_long");
6818 %}
6819 ins_pipe(pipe_class_dummy);
6820 %}
6821
6822 // Immediate Long Division
6823 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6824 match(Set dst (DivL src1 src2));
6825 effect(KILL tmp, KILL cr); // R0 is killed, too.
6826 ins_cost(2 * DEFAULT_COST);
6827 // TODO: s390 port size(VARIABLE_SIZE);
6828 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6829 ins_encode %{
6830 if ($src2$$constant != -1) {
6831 __ z_lghi(Z_R0_scratch, $src2$$constant);
6832 __ lgr_if_needed($dst$$Register, $src1$$Register);
6833 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6834 } else {
6835 __ z_lcgr($dst$$Register, $src1$$Register);
6836 }
6837 %}
6838 ins_pipe(pipe_class_dummy);
6839 %}
6840
6841 // REM
6842
6843 // Integer Remainder
6844 // Register Remainder
6845 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6846 match(Set dst (ModI src1 src2));
6847 effect(KILL tmp, KILL cr);
6848 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6849 // TODO: s390 port size(VARIABLE_SIZE);
6850 format %{ "MOD_checked $dst,$src1,$src2" %}
6851 ins_encode %{
6852 Register a = $src1$$Register;
6853 Register b = $src2$$Register;
6854 Register t = $dst$$Register;
6855 assert_different_registers(t->successor(), b);
6856
6857 Label do_div, done_div;
6858
6859 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6860 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6861 if (VM_Version::has_CompareBranch()) {
6862 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6863 } else {
6864 __ z_chi(b, -1);
6865 __ z_bre(done_div);
6866 }
6867 __ z_lgfr(t->successor(), a);
6868 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6869 } else {
6870 if (VM_Version::has_CompareBranch()) {
6871 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6872 } else {
6873 __ z_chi(b, -1);
6874 __ z_brne(do_div);
6875 }
6876 __ clear_reg(t, true, false);
6877 __ z_bru(done_div);
6878 __ bind(do_div);
6879 __ z_lgfr(t->successor(), a);
6880 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6881 }
6882 __ bind(done_div);
6883 %}
6884 ins_pipe(pipe_class_dummy);
6885 %}
6886
6887 // Register Unsigned Integer Remainder
6888 // NOTE: z_dlr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6889 // for dividend, upper 32bits will be in r4 and lower 32bits will be in r5 register.
6890 instruct umodI_reg_reg(revenRegI r4_reven_dst, iRegI src2, roddRegI r5_rodd_tmp, flagsReg cr) %{
6891 match(Set r4_reven_dst (UModI r4_reven_dst src2));
6892 effect(TEMP r5_rodd_tmp, KILL cr);
6893 ins_cost(DEFAULT_COST);
6894 // TODO: s390 port size(VARIABLE_SIZE);
6895 format %{ "UMOD $r4_reven_dst,$r4_reven_dst,$src2" %}
6896 ins_encode %{
6897 Register b = $src2$$Register;
6898 Register r4_reven_dst = $r4_reven_dst$$Register;
6899 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6900 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6901 assert(r4_reven_dst->successor() == r5_rodd_tmp, "must be an even-odd pair");
6902
6903 __ block_comment("unsigned_mod_integer {");
6904 __ z_lr(r5_rodd_tmp, r4_reven_dst); // load lower 32bits in odd register
6905 __ z_lhi(r4_reven_dst, 0); // make upper 32bits 0
6906 __ z_dlr(r4_reven_dst, b);
6907 __ block_comment("} unsigned_mod_integer");
6908 %}
6909 ins_pipe(pipe_class_dummy);
6910 %}
6911
6912 // Immediate Remainder
6913 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6914 match(Set dst (ModI src1 src2));
6915 effect(KILL tmp, KILL cr); // R0 is killed, too.
6916 ins_cost(3 * DEFAULT_COST);
6917 // TODO: s390 port size(VARIABLE_SIZE);
6918 format %{ "MOD_const $dst,src1,$src2" %}
6919 ins_encode %{
6920 assert_different_registers($dst$$Register, $src1$$Register);
6921 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6922 int divisor = $src2$$constant;
6923
6924 if (divisor != -1) {
6925 __ z_lghi(Z_R0_scratch, divisor);
6926 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6927 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6928 } else {
6929 __ clear_reg($dst$$Register, true, false);
6930 }
6931 %}
6932 ins_pipe(pipe_class_dummy);
6933 %}
6934
6935 // Register Long Remainder
6936 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6937 match(Set dst (ModL src1 src2));
6938 effect(KILL src1, KILL cr); // R0 is killed, too.
6939 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6940 // TODO: s390 port size(VARIABLE_SIZE);
6941 format %{ "MODG_checked $dst,$src1,$src2" %}
6942 ins_encode %{
6943 Register a = $src1$$Register;
6944 Register b = $src2$$Register;
6945 Register t = $dst$$Register;
6946 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6947
6948 Label do_div, done_div;
6949 if (t->encoding() != b->encoding()) {
6950 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6951 if (VM_Version::has_CompareBranch()) {
6952 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6953 } else {
6954 __ z_cghi(b, -1);
6955 __ z_bre(done_div);
6956 }
6957 __ z_dsgr(t, b);
6958 } else {
6959 if (VM_Version::has_CompareBranch()) {
6960 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6961 } else {
6962 __ z_cghi(b, -1);
6963 __ z_brne(do_div);
6964 }
6965 __ clear_reg(t, true, false);
6966 __ z_bru(done_div);
6967 __ bind(do_div);
6968 __ z_dsgr(t, b);
6969 }
6970 __ bind(done_div);
6971 %}
6972 ins_pipe(pipe_class_dummy);
6973 %}
6974
6975 // Register Unsigned Long Remainder
6976 // NOTE: z_dlgr requires even-odd pair. remainder will be in even register(r4) & quotient will be stored in odd register(r5)
6977 // for dividend, upper 64bits will be in r4 and lower 64bits will be in r5 register.
6978 instruct umodL_reg_reg(revenRegL r4_reven_dst, roddRegL r5_rodd_tmp, iRegL src2, flagsReg cr) %{
6979 match(Set r4_reven_dst (UModL r4_reven_dst src2));
6980 effect(TEMP r5_rodd_tmp, KILL cr);
6981 ins_cost(DEFAULT_COST);
6982 // TODO: s390 port size(VARIABLE_SIZE);
6983 format %{ "UMODG $r4_reven_dst,$r4_reven_dst,$src2" %}
6984 ins_encode %{
6985 Register b = $src2$$Register;
6986 Register r4_reven_dst = $r4_reven_dst$$Register;
6987 Register r5_rodd_tmp = $r5_rodd_tmp$$Register;
6988 assert_different_registers(r4_reven_dst, r5_rodd_tmp, b);
6989 assert(r4_reven_dst->successor() == r5_rodd_tmp, "instruction requires an even-odd pair" );
6990
6991 __ block_comment("unsigned_mod_long {");
6992 __ z_lgr(r5_rodd_tmp, r4_reven_dst); // load lower 64bits in even register
6993 __ z_lghi(r4_reven_dst, 0); // make upper 64bits 0
6994 __ z_dlgr(r4_reven_dst, b);
6995 __ block_comment("} unsigned_mod_long");
6996 %}
6997 ins_pipe(pipe_class_dummy);
6998 %}
6999
7000 // Register Long Remainder
7001 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
7002 match(Set dst (ModL src1 src2));
7003 effect(KILL tmp, KILL cr); // R0 is killed, too.
7004 ins_cost(3 * DEFAULT_COST);
7005 // TODO: s390 port size(VARIABLE_SIZE);
7006 format %{ "MODG_const $dst,src1,$src2\t # long" %}
7007 ins_encode %{
7008 int divisor = $src2$$constant;
7009 if (divisor != -1) {
7010 __ z_lghi(Z_R0_scratch, divisor);
7011 __ z_lgr($dst$$Register->successor(), $src1$$Register);
7012 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
7013 } else {
7014 __ clear_reg($dst$$Register, true, false);
7015 }
7016 %}
7017 ins_pipe(pipe_class_dummy);
7018 %}
7019
7020 // SHIFT
7021
7022 // Shift left logical
7023
7024 // Register Shift Left variable
7025 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
7026 match(Set dst (LShiftI src nbits));
7027 effect(KILL cr); // R1 is killed, too.
7028 ins_cost(3 * DEFAULT_COST);
7029 size(14);
7030 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
7031 ins_encode %{
7032 __ z_lgr(Z_R1_scratch, $nbits$$Register);
7033 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7034 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
7035 %}
7036 ins_pipe(pipe_class_dummy);
7037 %}
7038
7039 // Register Shift Left Immediate
7040 // Constant shift count is masked in ideal graph already.
7041 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
7042 match(Set dst (LShiftI src nbits));
7043 size(6);
7044 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
7045 ins_encode %{
7046 int Nbit = $nbits$$constant;
7047 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7048 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7049 %}
7050 ins_pipe(pipe_class_dummy);
7051 %}
7052
7053 // Register Shift Left Immediate by 1bit
7054 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
7055 match(Set dst (LShiftI src nbits));
7056 predicate(PreferLAoverADD);
7057 ins_cost(DEFAULT_COST_LOW);
7058 size(4);
7059 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
7060 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
7061 ins_pipe(pipe_class_dummy);
7062 %}
7063
7064 // Register Shift Left Long
7065 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
7066 match(Set dst (LShiftL src1 nbits));
7067 size(6);
7068 format %{ "SLLG $dst,$src1,[$nbits]" %}
7069 opcode(SLLG_ZOPC);
7070 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
7071 ins_pipe(pipe_class_dummy);
7072 %}
7073
7074 // Register Shift Left Long Immediate
7075 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
7076 match(Set dst (LShiftL src1 nbits));
7077 size(6);
7078 format %{ "SLLG $dst,$src1,$nbits" %}
7079 opcode(SLLG_ZOPC);
7080 ins_encode(z_rsyform_const(dst, src1, nbits));
7081 ins_pipe(pipe_class_dummy);
7082 %}
7083
7084 // Register Shift Left Long Immediate by 1bit
7085 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
7086 match(Set dst (LShiftL src1 nbits));
7087 predicate(PreferLAoverADD);
7088 ins_cost(DEFAULT_COST_LOW);
7089 size(4);
7090 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
7091 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
7092 ins_pipe(pipe_class_dummy);
7093 %}
7094
7095 // Shift right arithmetic
7096
7097 // Register Arithmetic Shift Right
7098 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7099 match(Set dst (RShiftI dst src));
7100 effect(KILL cr); // R1 is killed, too.
7101 ins_cost(3 * DEFAULT_COST);
7102 size(12);
7103 format %{ "SRA $dst,[$src] & 31" %}
7104 ins_encode %{
7105 __ z_lgr(Z_R1_scratch, $src$$Register);
7106 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7107 __ z_sra($dst$$Register, 0, Z_R1_scratch);
7108 %}
7109 ins_pipe(pipe_class_dummy);
7110 %}
7111
7112 // Register Arithmetic Shift Right Immediate
7113 // Constant shift count is masked in ideal graph already.
7114 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
7115 match(Set dst (RShiftI dst src));
7116 effect(KILL cr);
7117 size(4);
7118 format %{ "SRA $dst,$src" %}
7119 ins_encode %{
7120 int Nbit = $src$$constant;
7121 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7122 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7123 %}
7124 ins_pipe(pipe_class_dummy);
7125 %}
7126
7127 // Register Arithmetic Shift Right Long
7128 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
7129 match(Set dst (RShiftL src1 src2));
7130 effect(KILL cr);
7131 size(6);
7132 format %{ "SRAG $dst,$src1,[$src2]" %}
7133 opcode(SRAG_ZOPC);
7134 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7135 ins_pipe(pipe_class_dummy);
7136 %}
7137
7138 // Register Arithmetic Shift Right Long Immediate
7139 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
7140 match(Set dst (RShiftL src1 src2));
7141 effect(KILL cr);
7142 size(6);
7143 format %{ "SRAG $dst,$src1,$src2" %}
7144 opcode(SRAG_ZOPC);
7145 ins_encode(z_rsyform_const(dst, src1, src2));
7146 ins_pipe(pipe_class_dummy);
7147 %}
7148
7149 // Shift right logical
7150
7151 // Register Shift Right
7152 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7153 match(Set dst (URShiftI dst src));
7154 effect(KILL cr); // R1 is killed, too.
7155 ins_cost(3 * DEFAULT_COST);
7156 size(12);
7157 format %{ "SRL $dst,[$src] & 31" %}
7158 ins_encode %{
7159 __ z_lgr(Z_R1_scratch, $src$$Register);
7160 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
7161 __ z_srl($dst$$Register, 0, Z_R1_scratch);
7162 %}
7163 ins_pipe(pipe_class_dummy);
7164 %}
7165
7166 // Register Shift Right Immediate
7167 // Constant shift count is masked in ideal graph already.
7168 instruct srlI_reg_imm(iRegI dst, immI src) %{
7169 match(Set dst (URShiftI dst src));
7170 size(4);
7171 format %{ "SRL $dst,$src" %}
7172 ins_encode %{
7173 int Nbit = $src$$constant;
7174 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
7175 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
7176 %}
7177 ins_pipe(pipe_class_dummy);
7178 %}
7179
7180 // Register Shift Right Long
7181 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7182 match(Set dst (URShiftL src1 src2));
7183 size(6);
7184 format %{ "SRLG $dst,$src1,[$src2]" %}
7185 opcode(SRLG_ZOPC);
7186 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
7187 ins_pipe(pipe_class_dummy);
7188 %}
7189
7190 // Register Shift Right Long Immediate
7191 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
7192 match(Set dst (URShiftL src1 src2));
7193 size(6);
7194 format %{ "SRLG $dst,$src1,$src2" %}
7195 opcode(SRLG_ZOPC);
7196 ins_encode(z_rsyform_const(dst, src1, src2));
7197 ins_pipe(pipe_class_dummy);
7198 %}
7199
7200 // Register Shift Right Immediate with a CastP2X
7201 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
7202 match(Set dst (URShiftL (CastP2X src1) src2));
7203 size(6);
7204 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
7205 opcode(SRLG_ZOPC);
7206 ins_encode(z_rsyform_const(dst, src1, src2));
7207 ins_pipe(pipe_class_dummy);
7208 %}
7209
7210 //----------Rotate Instructions------------------------------------------------
7211
7212 // Rotate left 32bit.
7213 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
7214 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
7215 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7216 size(6);
7217 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
7218 opcode(RLL_ZOPC);
7219 ins_encode(z_rsyform_const(dst, src, lshift));
7220 ins_pipe(pipe_class_dummy);
7221 %}
7222
7223 // Rotate left 64bit.
7224 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
7225 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
7226 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7227 size(6);
7228 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
7229 opcode(RLLG_ZOPC);
7230 ins_encode(z_rsyform_const(dst, src, lshift));
7231 ins_pipe(pipe_class_dummy);
7232 %}
7233
7234 // Rotate right 32bit.
7235 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
7236 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
7237 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7238 // TODO: s390 port size(FIXED_SIZE);
7239 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
7240 opcode(RLL_ZOPC);
7241 ins_encode(z_rsyform_const(dst, src, rshift));
7242 ins_pipe(pipe_class_dummy);
7243 %}
7244
7245 // Rotate right 64bit.
7246 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7247 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7248 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7249 // TODO: s390 port size(FIXED_SIZE);
7250 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
7251 opcode(RLLG_ZOPC);
7252 ins_encode(z_rsyform_const(dst, src, rshift));
7253 ins_pipe(pipe_class_dummy);
7254 %}
7255
7256
7257 //----------Overflow Math Instructions-----------------------------------------
7258
7259 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7260 match(Set cr (OverflowAddI op1 op2));
7261 effect(DEF cr, USE op1, USE op2);
7262 // TODO: s390 port size(FIXED_SIZE);
7263 format %{ "AR $op1,$op2\t # overflow check int" %}
7264 ins_encode %{
7265 __ z_lr(Z_R0_scratch, $op1$$Register);
7266 __ z_ar(Z_R0_scratch, $op2$$Register);
7267 %}
7268 ins_pipe(pipe_class_dummy);
7269 %}
7270
7271 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7272 match(Set cr (OverflowAddI op1 op2));
7273 effect(DEF cr, USE op1, USE op2);
7274 // TODO: s390 port size(VARIABLE_SIZE);
7275 format %{ "AR $op1,$op2\t # overflow check int" %}
7276 ins_encode %{
7277 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7278 __ z_ar(Z_R0_scratch, $op1$$Register);
7279 %}
7280 ins_pipe(pipe_class_dummy);
7281 %}
7282
7283 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7284 match(Set cr (OverflowAddL op1 op2));
7285 effect(DEF cr, USE op1, USE op2);
7286 // TODO: s390 port size(FIXED_SIZE);
7287 format %{ "AGR $op1,$op2\t # overflow check long" %}
7288 ins_encode %{
7289 __ z_lgr(Z_R0_scratch, $op1$$Register);
7290 __ z_agr(Z_R0_scratch, $op2$$Register);
7291 %}
7292 ins_pipe(pipe_class_dummy);
7293 %}
7294
7295 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7296 match(Set cr (OverflowAddL op1 op2));
7297 effect(DEF cr, USE op1, USE op2);
7298 // TODO: s390 port size(VARIABLE_SIZE);
7299 format %{ "AGR $op1,$op2\t # overflow check long" %}
7300 ins_encode %{
7301 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7302 __ z_agr(Z_R0_scratch, $op1$$Register);
7303 %}
7304 ins_pipe(pipe_class_dummy);
7305 %}
7306
7307 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7308 match(Set cr (OverflowSubI op1 op2));
7309 effect(DEF cr, USE op1, USE op2);
7310 // TODO: s390 port size(FIXED_SIZE);
7311 format %{ "SR $op1,$op2\t # overflow check int" %}
7312 ins_encode %{
7313 __ z_lr(Z_R0_scratch, $op1$$Register);
7314 __ z_sr(Z_R0_scratch, $op2$$Register);
7315 %}
7316 ins_pipe(pipe_class_dummy);
7317 %}
7318
7319 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7320 match(Set cr (OverflowSubI op1 op2));
7321 effect(DEF cr, USE op1, USE op2);
7322 // TODO: s390 port size(VARIABLE_SIZE);
7323 format %{ "SR $op1,$op2\t # overflow check int" %}
7324 ins_encode %{
7325 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7326 __ z_lr(Z_R0_scratch, $op1$$Register);
7327 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7328 %}
7329 ins_pipe(pipe_class_dummy);
7330 %}
7331
7332 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7333 match(Set cr (OverflowSubL op1 op2));
7334 effect(DEF cr, USE op1, USE op2);
7335 // TODO: s390 port size(FIXED_SIZE);
7336 format %{ "SGR $op1,$op2\t # overflow check long" %}
7337 ins_encode %{
7338 __ z_lgr(Z_R0_scratch, $op1$$Register);
7339 __ z_sgr(Z_R0_scratch, $op2$$Register);
7340 %}
7341 ins_pipe(pipe_class_dummy);
7342 %}
7343
7344 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7345 match(Set cr (OverflowSubL op1 op2));
7346 effect(DEF cr, USE op1, USE op2);
7347 // TODO: s390 port size(VARIABLE_SIZE);
7348 format %{ "SGR $op1,$op2\t # overflow check long" %}
7349 ins_encode %{
7350 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7351 __ z_lgr(Z_R0_scratch, $op1$$Register);
7352 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7353 %}
7354 ins_pipe(pipe_class_dummy);
7355 %}
7356
7357 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7358 match(Set cr (OverflowSubI zero op2));
7359 effect(DEF cr, USE op2);
7360 format %{ "NEG $op2\t # overflow check int" %}
7361 ins_encode %{
7362 __ clear_reg(Z_R0_scratch, false, false);
7363 __ z_sr(Z_R0_scratch, $op2$$Register);
7364 %}
7365 ins_pipe(pipe_class_dummy);
7366 %}
7367
7368 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7369 match(Set cr (OverflowSubL zero op2));
7370 effect(DEF cr, USE op2);
7371 format %{ "NEGG $op2\t # overflow check long" %}
7372 ins_encode %{
7373 __ clear_reg(Z_R0_scratch, true, false);
7374 __ z_sgr(Z_R0_scratch, $op2$$Register);
7375 %}
7376 ins_pipe(pipe_class_dummy);
7377 %}
7378
7379 // No intrinsics for multiplication, since there is no easy way
7380 // to check for overflow.
7381
7382
7383 //----------Floating Point Arithmetic Instructions-----------------------------
7384
7385 // ADD
7386
7387 // Add float single precision
7388 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7389 match(Set dst (AddF dst src));
7390 effect(KILL cr);
7391 ins_cost(ALU_REG_COST);
7392 size(4);
7393 format %{ "AEBR $dst,$src" %}
7394 opcode(AEBR_ZOPC);
7395 ins_encode(z_rreform(dst, src));
7396 ins_pipe(pipe_class_dummy);
7397 %}
7398
7399 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7400 match(Set dst (AddF dst (LoadF src)));
7401 effect(KILL cr);
7402 ins_cost(ALU_MEMORY_COST);
7403 size(6);
7404 format %{ "AEB $dst,$src\t # floatMemory" %}
7405 opcode(AEB_ZOPC);
7406 ins_encode(z_form_rt_memFP(dst, src));
7407 ins_pipe(pipe_class_dummy);
7408 %}
7409
7410 // Add float double precision
7411 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7412 match(Set dst (AddD dst src));
7413 effect(KILL cr);
7414 ins_cost(ALU_REG_COST);
7415 size(4);
7416 format %{ "ADBR $dst,$src" %}
7417 opcode(ADBR_ZOPC);
7418 ins_encode(z_rreform(dst, src));
7419 ins_pipe(pipe_class_dummy);
7420 %}
7421
7422 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7423 match(Set dst (AddD dst (LoadD src)));
7424 effect(KILL cr);
7425 ins_cost(ALU_MEMORY_COST);
7426 size(6);
7427 format %{ "ADB $dst,$src\t # doubleMemory" %}
7428 opcode(ADB_ZOPC);
7429 ins_encode(z_form_rt_memFP(dst, src));
7430 ins_pipe(pipe_class_dummy);
7431 %}
7432
7433 // SUB
7434
7435 // Sub float single precision
7436 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7437 match(Set dst (SubF dst src));
7438 effect(KILL cr);
7439 ins_cost(ALU_REG_COST);
7440 size(4);
7441 format %{ "SEBR $dst,$src" %}
7442 opcode(SEBR_ZOPC);
7443 ins_encode(z_rreform(dst, src));
7444 ins_pipe(pipe_class_dummy);
7445 %}
7446
7447 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7448 match(Set dst (SubF dst (LoadF src)));
7449 effect(KILL cr);
7450 ins_cost(ALU_MEMORY_COST);
7451 size(6);
7452 format %{ "SEB $dst,$src\t # floatMemory" %}
7453 opcode(SEB_ZOPC);
7454 ins_encode(z_form_rt_memFP(dst, src));
7455 ins_pipe(pipe_class_dummy);
7456 %}
7457
7458 // Sub float double precision
7459 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7460 match(Set dst (SubD dst src));
7461 effect(KILL cr);
7462 ins_cost(ALU_REG_COST);
7463 size(4);
7464 format %{ "SDBR $dst,$src" %}
7465 opcode(SDBR_ZOPC);
7466 ins_encode(z_rreform(dst, src));
7467 ins_pipe(pipe_class_dummy);
7468 %}
7469
7470 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7471 match(Set dst (SubD dst (LoadD src)));
7472 effect(KILL cr);
7473 ins_cost(ALU_MEMORY_COST);
7474 size(6);
7475 format %{ "SDB $dst,$src\t # doubleMemory" %}
7476 opcode(SDB_ZOPC);
7477 ins_encode(z_form_rt_memFP(dst, src));
7478 ins_pipe(pipe_class_dummy);
7479 %}
7480
7481 // MUL
7482
7483 // Mul float single precision
7484 instruct mulF_reg_reg(regF dst, regF src) %{
7485 match(Set dst (MulF dst src));
7486 // CC unchanged by MUL.
7487 ins_cost(ALU_REG_COST);
7488 size(4);
7489 format %{ "MEEBR $dst,$src" %}
7490 opcode(MEEBR_ZOPC);
7491 ins_encode(z_rreform(dst, src));
7492 ins_pipe(pipe_class_dummy);
7493 %}
7494
7495 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7496 match(Set dst (MulF dst (LoadF src)));
7497 // CC unchanged by MUL.
7498 ins_cost(ALU_MEMORY_COST);
7499 size(6);
7500 format %{ "MEEB $dst,$src\t # floatMemory" %}
7501 opcode(MEEB_ZOPC);
7502 ins_encode(z_form_rt_memFP(dst, src));
7503 ins_pipe(pipe_class_dummy);
7504 %}
7505
7506 // Mul float double precision
7507 instruct mulD_reg_reg(regD dst, regD src) %{
7508 match(Set dst (MulD dst src));
7509 // CC unchanged by MUL.
7510 ins_cost(ALU_REG_COST);
7511 size(4);
7512 format %{ "MDBR $dst,$src" %}
7513 opcode(MDBR_ZOPC);
7514 ins_encode(z_rreform(dst, src));
7515 ins_pipe(pipe_class_dummy);
7516 %}
7517
7518 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7519 match(Set dst (MulD dst (LoadD src)));
7520 // CC unchanged by MUL.
7521 ins_cost(ALU_MEMORY_COST);
7522 size(6);
7523 format %{ "MDB $dst,$src\t # doubleMemory" %}
7524 opcode(MDB_ZOPC);
7525 ins_encode(z_form_rt_memFP(dst, src));
7526 ins_pipe(pipe_class_dummy);
7527 %}
7528
7529 // Multiply-Accumulate
7530 // src1 * src2 + dst
7531 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7532 match(Set dst (FmaF dst (Binary src1 src2)));
7533 // CC unchanged by MUL-ADD.
7534 ins_cost(ALU_REG_COST);
7535 size(4);
7536 format %{ "MAEBR $dst, $src1, $src2" %}
7537 ins_encode %{
7538 assert(UseFMA, "Needs FMA instructions support.");
7539 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7540 %}
7541 ins_pipe(pipe_class_dummy);
7542 %}
7543
7544 // src1 * src2 + dst
7545 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7546 match(Set dst (FmaD dst (Binary src1 src2)));
7547 // CC unchanged by MUL-ADD.
7548 ins_cost(ALU_REG_COST);
7549 size(4);
7550 format %{ "MADBR $dst, $src1, $src2" %}
7551 ins_encode %{
7552 assert(UseFMA, "Needs FMA instructions support.");
7553 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7554 %}
7555 ins_pipe(pipe_class_dummy);
7556 %}
7557
7558 // src1 * src2 - dst
7559 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7560 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7561 // CC unchanged by MUL-SUB.
7562 ins_cost(ALU_REG_COST);
7563 size(4);
7564 format %{ "MSEBR $dst, $src1, $src2" %}
7565 ins_encode %{
7566 assert(UseFMA, "Needs FMA instructions support.");
7567 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7568 %}
7569 ins_pipe(pipe_class_dummy);
7570 %}
7571
7572 // src1 * src2 - dst
7573 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7574 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7575 // CC unchanged by MUL-SUB.
7576 ins_cost(ALU_REG_COST);
7577 size(4);
7578 format %{ "MSDBR $dst, $src1, $src2" %}
7579 ins_encode %{
7580 assert(UseFMA, "Needs FMA instructions support.");
7581 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7582 %}
7583 ins_pipe(pipe_class_dummy);
7584 %}
7585
7586 // src1 * src2 + dst
7587 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7588 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7589 // CC unchanged by MUL-ADD.
7590 ins_cost(ALU_MEMORY_COST);
7591 size(6);
7592 format %{ "MAEB $dst, $src1, $src2" %}
7593 ins_encode %{
7594 assert(UseFMA, "Needs FMA instructions support.");
7595 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7596 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7597 %}
7598 ins_pipe(pipe_class_dummy);
7599 %}
7600
7601 // src1 * src2 + dst
7602 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7603 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7604 // CC unchanged by MUL-ADD.
7605 ins_cost(ALU_MEMORY_COST);
7606 size(6);
7607 format %{ "MADB $dst, $src1, $src2" %}
7608 ins_encode %{
7609 assert(UseFMA, "Needs FMA instructions support.");
7610 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7611 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7612 %}
7613 ins_pipe(pipe_class_dummy);
7614 %}
7615
7616 // src1 * src2 - dst
7617 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7618 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7619 // CC unchanged by MUL-SUB.
7620 ins_cost(ALU_MEMORY_COST);
7621 size(6);
7622 format %{ "MSEB $dst, $src1, $src2" %}
7623 ins_encode %{
7624 assert(UseFMA, "Needs FMA instructions support.");
7625 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7626 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7627 %}
7628 ins_pipe(pipe_class_dummy);
7629 %}
7630
7631 // src1 * src2 - dst
7632 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7633 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7634 // CC unchanged by MUL-SUB.
7635 ins_cost(ALU_MEMORY_COST);
7636 size(6);
7637 format %{ "MSDB $dst, $src1, $src2" %}
7638 ins_encode %{
7639 assert(UseFMA, "Needs FMA instructions support.");
7640 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7641 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7642 %}
7643 ins_pipe(pipe_class_dummy);
7644 %}
7645
7646 // src1 * src2 + dst
7647 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7648 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7649 // CC unchanged by MUL-ADD.
7650 ins_cost(ALU_MEMORY_COST);
7651 size(6);
7652 format %{ "MAEB $dst, $src1, $src2" %}
7653 ins_encode %{
7654 assert(UseFMA, "Needs FMA instructions support.");
7655 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7656 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7657 %}
7658 ins_pipe(pipe_class_dummy);
7659 %}
7660
7661 // src1 * src2 + dst
7662 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7663 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7664 // CC unchanged by MUL-ADD.
7665 ins_cost(ALU_MEMORY_COST);
7666 size(6);
7667 format %{ "MADB $dst, $src1, $src2" %}
7668 ins_encode %{
7669 assert(UseFMA, "Needs FMA instructions support.");
7670 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7671 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7672 %}
7673 ins_pipe(pipe_class_dummy);
7674 %}
7675
7676 // src1 * src2 - dst
7677 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7678 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7679 // CC unchanged by MUL-SUB.
7680 ins_cost(ALU_MEMORY_COST);
7681 size(6);
7682 format %{ "MSEB $dst, $src1, $src2" %}
7683 ins_encode %{
7684 assert(UseFMA, "Needs FMA instructions support.");
7685 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7686 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7687 %}
7688 ins_pipe(pipe_class_dummy);
7689 %}
7690
7691 // src1 * src2 - dst
7692 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7693 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7694 // CC unchanged by MUL-SUB.
7695 ins_cost(ALU_MEMORY_COST);
7696 size(6);
7697 format %{ "MSDB $dst, $src1, $src2" %}
7698 ins_encode %{
7699 assert(UseFMA, "Needs FMA instructions support.");
7700 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7701 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7702 %}
7703 ins_pipe(pipe_class_dummy);
7704 %}
7705
7706 // DIV
7707
7708 // Div float single precision
7709 instruct divF_reg_reg(regF dst, regF src) %{
7710 match(Set dst (DivF dst src));
7711 // CC unchanged by DIV.
7712 ins_cost(ALU_REG_COST);
7713 size(4);
7714 format %{ "DEBR $dst,$src" %}
7715 opcode(DEBR_ZOPC);
7716 ins_encode(z_rreform(dst, src));
7717 ins_pipe(pipe_class_dummy);
7718 %}
7719
7720 instruct divF_reg_mem(regF dst, memoryRX src)%{
7721 match(Set dst (DivF dst (LoadF src)));
7722 // CC unchanged by DIV.
7723 ins_cost(ALU_MEMORY_COST);
7724 size(6);
7725 format %{ "DEB $dst,$src\t # floatMemory" %}
7726 opcode(DEB_ZOPC);
7727 ins_encode(z_form_rt_memFP(dst, src));
7728 ins_pipe(pipe_class_dummy);
7729 %}
7730
7731 // Div float double precision
7732 instruct divD_reg_reg(regD dst, regD src) %{
7733 match(Set dst (DivD dst src));
7734 // CC unchanged by DIV.
7735 ins_cost(ALU_REG_COST);
7736 size(4);
7737 format %{ "DDBR $dst,$src" %}
7738 opcode(DDBR_ZOPC);
7739 ins_encode(z_rreform(dst, src));
7740 ins_pipe(pipe_class_dummy);
7741 %}
7742
7743 instruct divD_reg_mem(regD dst, memoryRX src)%{
7744 match(Set dst (DivD dst (LoadD src)));
7745 // CC unchanged by DIV.
7746 ins_cost(ALU_MEMORY_COST);
7747 size(6);
7748 format %{ "DDB $dst,$src\t # doubleMemory" %}
7749 opcode(DDB_ZOPC);
7750 ins_encode(z_form_rt_memFP(dst, src));
7751 ins_pipe(pipe_class_dummy);
7752 %}
7753
7754 // ABS
7755
7756 // Absolute float single precision
7757 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7758 match(Set dst (AbsF src));
7759 effect(KILL cr);
7760 size(4);
7761 format %{ "LPEBR $dst,$src\t float" %}
7762 opcode(LPEBR_ZOPC);
7763 ins_encode(z_rreform(dst, src));
7764 ins_pipe(pipe_class_dummy);
7765 %}
7766
7767 // Absolute float double precision
7768 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7769 match(Set dst (AbsD src));
7770 effect(KILL cr);
7771 size(4);
7772 format %{ "LPDBR $dst,$src\t double" %}
7773 opcode(LPDBR_ZOPC);
7774 ins_encode(z_rreform(dst, src));
7775 ins_pipe(pipe_class_dummy);
7776 %}
7777
7778 // NEG(ABS)
7779
7780 // Negative absolute float single precision
7781 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7782 match(Set dst (NegF (AbsF src)));
7783 effect(KILL cr);
7784 size(4);
7785 format %{ "LNEBR $dst,$src\t float" %}
7786 opcode(LNEBR_ZOPC);
7787 ins_encode(z_rreform(dst, src));
7788 ins_pipe(pipe_class_dummy);
7789 %}
7790
7791 // Negative absolute float double precision
7792 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7793 match(Set dst (NegD (AbsD src)));
7794 effect(KILL cr);
7795 size(4);
7796 format %{ "LNDBR $dst,$src\t double" %}
7797 opcode(LNDBR_ZOPC);
7798 ins_encode(z_rreform(dst, src));
7799 ins_pipe(pipe_class_dummy);
7800 %}
7801
7802 // NEG
7803
7804 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7805 match(Set dst (NegF src));
7806 effect(KILL cr);
7807 size(4);
7808 format %{ "NegF $dst,$src\t float" %}
7809 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7810 ins_pipe(pipe_class_dummy);
7811 %}
7812
7813 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7814 match(Set dst (NegD src));
7815 effect(KILL cr);
7816 size(4);
7817 format %{ "NegD $dst,$src\t double" %}
7818 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7819 ins_pipe(pipe_class_dummy);
7820 %}
7821
7822 // SQRT
7823
7824 // Sqrt float precision
7825 instruct sqrtF_reg(regF dst, regF src) %{
7826 match(Set dst (SqrtF src));
7827 // CC remains unchanged.
7828 ins_cost(ALU_REG_COST);
7829 size(4);
7830 format %{ "SQEBR $dst,$src" %}
7831 opcode(SQEBR_ZOPC);
7832 ins_encode(z_rreform(dst, src));
7833 ins_pipe(pipe_class_dummy);
7834 %}
7835
7836 // Sqrt double precision
7837 instruct sqrtD_reg(regD dst, regD src) %{
7838 match(Set dst (SqrtD src));
7839 // CC remains unchanged.
7840 ins_cost(ALU_REG_COST);
7841 size(4);
7842 format %{ "SQDBR $dst,$src" %}
7843 opcode(SQDBR_ZOPC);
7844 ins_encode(z_rreform(dst, src));
7845 ins_pipe(pipe_class_dummy);
7846 %}
7847
7848 instruct sqrtF_mem(regF dst, memoryRX src) %{
7849 match(Set dst (SqrtF src));
7850 // CC remains unchanged.
7851 ins_cost(ALU_MEMORY_COST);
7852 size(6);
7853 format %{ "SQEB $dst,$src\t # floatMemory" %}
7854 opcode(SQEB_ZOPC);
7855 ins_encode(z_form_rt_memFP(dst, src));
7856 ins_pipe(pipe_class_dummy);
7857 %}
7858
7859 instruct sqrtD_mem(regD dst, memoryRX src) %{
7860 match(Set dst (SqrtD src));
7861 // CC remains unchanged.
7862 ins_cost(ALU_MEMORY_COST);
7863 // TODO: s390 port size(FIXED_SIZE);
7864 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7865 opcode(SQDB_ZOPC);
7866 ins_encode(z_form_rt_memFP(dst, src));
7867 ins_pipe(pipe_class_dummy);
7868 %}
7869
7870 //----------Logical Instructions-----------------------------------------------
7871
7872 // Register And
7873 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7874 match(Set dst (AndI dst src));
7875 effect(KILL cr);
7876 ins_cost(DEFAULT_COST_LOW);
7877 size(2);
7878 format %{ "NR $dst,$src\t # int" %}
7879 opcode(NR_ZOPC);
7880 ins_encode(z_rrform(dst, src));
7881 ins_pipe(pipe_class_dummy);
7882 %}
7883
7884 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7885 match(Set dst (AndI dst (LoadI src)));
7886 effect(KILL cr);
7887 ins_cost(MEMORY_REF_COST);
7888 // TODO: s390 port size(VARIABLE_SIZE);
7889 format %{ "N(Y) $dst, $src\t # int" %}
7890 opcode(NY_ZOPC, N_ZOPC);
7891 ins_encode(z_form_rt_mem_opt(dst, src));
7892 ins_pipe(pipe_class_dummy);
7893 %}
7894
7895 // Immediate And
7896 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7897 match(Set dst (AndI dst src));
7898 effect(KILL cr);
7899 ins_cost(DEFAULT_COST_HIGH);
7900 size(6);
7901 format %{ "NILF $dst,$src" %}
7902 opcode(NILF_ZOPC);
7903 ins_encode(z_rilform_unsigned(dst, src));
7904 ins_pipe(pipe_class_dummy);
7905 %}
7906
7907 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7908 match(Set dst (AndI dst src));
7909 effect(KILL cr);
7910 ins_cost(DEFAULT_COST);
7911 size(4);
7912 format %{ "NILH $dst,$src" %}
7913 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7914 ins_pipe(pipe_class_dummy);
7915 %}
7916
7917 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7918 match(Set dst (AndI dst src));
7919 effect(KILL cr);
7920 ins_cost(DEFAULT_COST);
7921 size(4);
7922 format %{ "NILL $dst,$src" %}
7923 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7924 ins_pipe(pipe_class_dummy);
7925 %}
7926
7927 // Register And Long
7928 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7929 match(Set dst (AndL dst src));
7930 effect(KILL cr);
7931 ins_cost(DEFAULT_COST);
7932 size(4);
7933 format %{ "NGR $dst,$src\t # long" %}
7934 opcode(NGR_ZOPC);
7935 ins_encode(z_rreform(dst, src));
7936 ins_pipe(pipe_class_dummy);
7937 %}
7938
7939 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7940 match(Set dst (AndL dst (LoadL src)));
7941 effect(KILL cr);
7942 ins_cost(MEMORY_REF_COST);
7943 size(Z_DISP3_SIZE);
7944 format %{ "NG $dst, $src\t # long" %}
7945 opcode(NG_ZOPC, NG_ZOPC);
7946 ins_encode(z_form_rt_mem_opt(dst, src));
7947 ins_pipe(pipe_class_dummy);
7948 %}
7949
7950 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7951 match(Set dst (AndL dst src));
7952 effect(KILL cr);
7953 ins_cost(DEFAULT_COST);
7954 size(4);
7955 format %{ "NILL $dst,$src\t # long" %}
7956 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7957 ins_pipe(pipe_class_dummy);
7958 %}
7959
7960 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7961 match(Set dst (AndL dst src));
7962 effect(KILL cr);
7963 ins_cost(DEFAULT_COST);
7964 size(4);
7965 format %{ "NILH $dst,$src\t # long" %}
7966 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7967 ins_pipe(pipe_class_dummy);
7968 %}
7969
7970 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7971 match(Set dst (AndL dst src));
7972 effect(KILL cr);
7973 ins_cost(DEFAULT_COST);
7974 size(4);
7975 format %{ "NIHL $dst,$src\t # long" %}
7976 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7977 ins_pipe(pipe_class_dummy);
7978 %}
7979
7980 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7981 match(Set dst (AndL dst src));
7982 effect(KILL cr);
7983 ins_cost(DEFAULT_COST);
7984 size(4);
7985 format %{ "NIHH $dst,$src\t # long" %}
7986 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7987 ins_pipe(pipe_class_dummy);
7988 %}
7989
7990 // OR
7991
7992 // Or Instructions
7993 // Register Or
7994 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7995 match(Set dst (OrI dst src));
7996 effect(KILL cr);
7997 size(2);
7998 format %{ "OR $dst,$src" %}
7999 opcode(OR_ZOPC);
8000 ins_encode(z_rrform(dst, src));
8001 ins_pipe(pipe_class_dummy);
8002 %}
8003
8004 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
8005 match(Set dst (OrI dst (LoadI src)));
8006 effect(KILL cr);
8007 ins_cost(MEMORY_REF_COST);
8008 // TODO: s390 port size(VARIABLE_SIZE);
8009 format %{ "O(Y) $dst, $src\t # int" %}
8010 opcode(OY_ZOPC, O_ZOPC);
8011 ins_encode(z_form_rt_mem_opt(dst, src));
8012 ins_pipe(pipe_class_dummy);
8013 %}
8014
8015 // Immediate Or
8016 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
8017 match(Set dst (OrI dst con));
8018 effect(KILL cr);
8019 size(4);
8020 format %{ "OILL $dst,$con" %}
8021 opcode(OILL_ZOPC);
8022 ins_encode(z_riform_unsigned(dst,con));
8023 ins_pipe(pipe_class_dummy);
8024 %}
8025
8026 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
8027 match(Set dst (OrI dst con));
8028 effect(KILL cr);
8029 ins_cost(DEFAULT_COST_HIGH);
8030 size(6);
8031 format %{ "OILF $dst,$con" %}
8032 opcode(OILF_ZOPC);
8033 ins_encode(z_rilform_unsigned(dst,con));
8034 ins_pipe(pipe_class_dummy);
8035 %}
8036
8037 // Register Or Long
8038 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
8039 match(Set dst (OrL dst src));
8040 effect(KILL cr);
8041 ins_cost(DEFAULT_COST);
8042 size(4);
8043 format %{ "OGR $dst,$src\t # long" %}
8044 opcode(OGR_ZOPC);
8045 ins_encode(z_rreform(dst, src));
8046 ins_pipe(pipe_class_dummy);
8047 %}
8048
8049 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
8050 match(Set dst (OrL dst (LoadL src)));
8051 effect(KILL cr);
8052 ins_cost(MEMORY_REF_COST);
8053 size(Z_DISP3_SIZE);
8054 format %{ "OG $dst, $src\t # long" %}
8055 opcode(OG_ZOPC, OG_ZOPC);
8056 ins_encode(z_form_rt_mem_opt(dst, src));
8057 ins_pipe(pipe_class_dummy);
8058 %}
8059
8060 // Immediate Or long
8061 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
8062 match(Set dst (OrL dst con));
8063 effect(KILL cr);
8064 ins_cost(DEFAULT_COST);
8065 size(4);
8066 format %{ "OILL $dst,$con\t # long" %}
8067 opcode(OILL_ZOPC);
8068 ins_encode(z_riform_unsigned(dst,con));
8069 ins_pipe(pipe_class_dummy);
8070 %}
8071
8072 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
8073 match(Set dst (OrI dst con));
8074 effect(KILL cr);
8075 ins_cost(DEFAULT_COST_HIGH);
8076 // TODO: s390 port size(FIXED_SIZE);
8077 format %{ "OILF $dst,$con\t # long" %}
8078 opcode(OILF_ZOPC);
8079 ins_encode(z_rilform_unsigned(dst,con));
8080 ins_pipe(pipe_class_dummy);
8081 %}
8082
8083 // XOR
8084
8085 // Register Xor
8086 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8087 match(Set dst (XorI dst src));
8088 effect(KILL cr);
8089 size(2);
8090 format %{ "XR $dst,$src" %}
8091 opcode(XR_ZOPC);
8092 ins_encode(z_rrform(dst, src));
8093 ins_pipe(pipe_class_dummy);
8094 %}
8095
8096 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
8097 match(Set dst (XorI dst (LoadI src)));
8098 effect(KILL cr);
8099 ins_cost(MEMORY_REF_COST);
8100 // TODO: s390 port size(VARIABLE_SIZE);
8101 format %{ "X(Y) $dst, $src\t # int" %}
8102 opcode(XY_ZOPC, X_ZOPC);
8103 ins_encode(z_form_rt_mem_opt(dst, src));
8104 ins_pipe(pipe_class_dummy);
8105 %}
8106
8107 // Immediate Xor
8108 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
8109 match(Set dst (XorI dst src));
8110 effect(KILL cr);
8111 ins_cost(DEFAULT_COST_HIGH);
8112 size(6);
8113 format %{ "XILF $dst,$src" %}
8114 opcode(XILF_ZOPC);
8115 ins_encode(z_rilform_unsigned(dst, src));
8116 ins_pipe(pipe_class_dummy);
8117 %}
8118
8119 // Register Xor Long
8120 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
8121 match(Set dst (XorL dst src));
8122 effect(KILL cr);
8123 ins_cost(DEFAULT_COST);
8124 size(4);
8125 format %{ "XGR $dst,$src\t # long" %}
8126 opcode(XGR_ZOPC);
8127 ins_encode(z_rreform(dst, src));
8128 ins_pipe(pipe_class_dummy);
8129 %}
8130
8131 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
8132 match(Set dst (XorL dst (LoadL src)));
8133 effect(KILL cr);
8134 ins_cost(MEMORY_REF_COST);
8135 size(Z_DISP3_SIZE);
8136 format %{ "XG $dst, $src\t # long" %}
8137 opcode(XG_ZOPC, XG_ZOPC);
8138 ins_encode(z_form_rt_mem_opt(dst, src));
8139 ins_pipe(pipe_class_dummy);
8140 %}
8141
8142 // Immediate Xor Long
8143 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
8144 match(Set dst (XorL dst con));
8145 effect(KILL cr);
8146 ins_cost(DEFAULT_COST_HIGH);
8147 size(6);
8148 format %{ "XILF $dst,$con\t # long" %}
8149 opcode(XILF_ZOPC);
8150 ins_encode(z_rilform_unsigned(dst,con));
8151 ins_pipe(pipe_class_dummy);
8152 %}
8153
8154 //----------Convert to Boolean-------------------------------------------------
8155
8156 // Convert integer to boolean.
8157 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
8158 match(Set dst (Conv2B src));
8159 effect(KILL cr);
8160 ins_cost(3 * DEFAULT_COST);
8161 size(6);
8162 format %{ "convI2B $dst,$src" %}
8163 ins_encode %{
8164 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
8165 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
8166 %}
8167 ins_pipe(pipe_class_dummy);
8168 %}
8169
8170 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
8171 match(Set dst (Conv2B src));
8172 effect(KILL cr);
8173 ins_cost(3 * DEFAULT_COST);
8174 size(10);
8175 format %{ "convP2B $dst,$src" %}
8176 ins_encode %{
8177 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
8178 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
8179 %}
8180 ins_pipe(pipe_class_dummy);
8181 %}
8182
8183 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
8184 match(Set dst (CmpLTMask dst src));
8185 effect(KILL cr);
8186 ins_cost(2 * DEFAULT_COST);
8187 size(18);
8188 format %{ "Set $dst CmpLTMask $dst,$src" %}
8189 ins_encode %{
8190 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
8191 __ z_lgfr(Z_R0_scratch, $src$$Register);
8192 __ z_lgfr($dst$$Register, $dst$$Register);
8193 __ z_sgr($dst$$Register, Z_R0_scratch);
8194 __ z_srag($dst$$Register, $dst$$Register, 63);
8195 %}
8196 ins_pipe(pipe_class_dummy);
8197 %}
8198
8199 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
8200 match(Set dst (CmpLTMask dst zero));
8201 effect(KILL cr);
8202 ins_cost(DEFAULT_COST);
8203 size(4);
8204 format %{ "Set $dst CmpLTMask $dst,$zero" %}
8205 ins_encode %{ __ z_sra($dst$$Register, 31); %}
8206 ins_pipe(pipe_class_dummy);
8207 %}
8208
8209
8210 //----------Arithmetic Conversion Instructions---------------------------------
8211 // The conversions operations are all Alpha sorted. Please keep it that way!
8212
8213 instruct convD2F_reg(regF dst, regD src) %{
8214 match(Set dst (ConvD2F src));
8215 // CC remains unchanged.
8216 size(4);
8217 format %{ "LEDBR $dst,$src" %}
8218 opcode(LEDBR_ZOPC);
8219 ins_encode(z_rreform(dst, src));
8220 ins_pipe(pipe_class_dummy);
8221 %}
8222
8223 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
8224 match(Set dst (ConvF2I src));
8225 effect(KILL cr);
8226 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8227 size(16);
8228 format %{ "convF2I $dst,$src" %}
8229 ins_encode %{
8230 Label done;
8231 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8232 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8233 __ z_brno(done); // Result is zero if unordered argument.
8234 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8235 __ bind(done);
8236 %}
8237 ins_pipe(pipe_class_dummy);
8238 %}
8239
8240 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
8241 match(Set dst (ConvD2I src));
8242 effect(KILL cr);
8243 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8244 size(16);
8245 format %{ "convD2I $dst,$src" %}
8246 ins_encode %{
8247 Label done;
8248 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
8249 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8250 __ z_brno(done); // Result is zero if unordered argument.
8251 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8252 __ bind(done);
8253 %}
8254 ins_pipe(pipe_class_dummy);
8255 %}
8256
8257 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8258 match(Set dst (ConvF2L src));
8259 effect(KILL cr);
8260 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8261 size(16);
8262 format %{ "convF2L $dst,$src" %}
8263 ins_encode %{
8264 Label done;
8265 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8266 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8267 __ z_brno(done); // Result is zero if unordered argument.
8268 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8269 __ bind(done);
8270 %}
8271 ins_pipe(pipe_class_dummy);
8272 %}
8273
8274 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8275 match(Set dst (ConvD2L src));
8276 effect(KILL cr);
8277 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8278 size(16);
8279 format %{ "convD2L $dst,$src" %}
8280 ins_encode %{
8281 Label done;
8282 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8283 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8284 __ z_brno(done); // Result is zero if unordered argument.
8285 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8286 __ bind(done);
8287 %}
8288 ins_pipe(pipe_class_dummy);
8289 %}
8290
8291 instruct convF2D_reg(regD dst, regF src) %{
8292 match(Set dst (ConvF2D src));
8293 // CC remains unchanged.
8294 size(4);
8295 format %{ "LDEBR $dst,$src" %}
8296 opcode(LDEBR_ZOPC);
8297 ins_encode(z_rreform(dst, src));
8298 ins_pipe(pipe_class_dummy);
8299 %}
8300
8301 instruct convF2D_mem(regD dst, memoryRX src) %{
8302 match(Set dst (ConvF2D src));
8303 // CC remains unchanged.
8304 size(6);
8305 format %{ "LDEB $dst,$src" %}
8306 opcode(LDEB_ZOPC);
8307 ins_encode(z_form_rt_memFP(dst, src));
8308 ins_pipe(pipe_class_dummy);
8309 %}
8310
8311 instruct convI2D_reg(regD dst, iRegI src) %{
8312 match(Set dst (ConvI2D src));
8313 // CC remains unchanged.
8314 ins_cost(DEFAULT_COST);
8315 size(4);
8316 format %{ "CDFBR $dst,$src" %}
8317 opcode(CDFBR_ZOPC);
8318 ins_encode(z_rreform(dst, src));
8319 ins_pipe(pipe_class_dummy);
8320 %}
8321
8322 // Optimization that saves up to two memory operations for each conversion.
8323 instruct convI2F_ireg(regF dst, iRegI src) %{
8324 match(Set dst (ConvI2F src));
8325 // CC remains unchanged.
8326 ins_cost(DEFAULT_COST);
8327 size(4);
8328 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8329 opcode(CEFBR_ZOPC);
8330 ins_encode(z_rreform(dst, src));
8331 ins_pipe(pipe_class_dummy);
8332 %}
8333
8334 instruct convI2L_reg(iRegL dst, iRegI src) %{
8335 match(Set dst (ConvI2L src));
8336 size(4);
8337 format %{ "LGFR $dst,$src\t # int->long" %}
8338 opcode(LGFR_ZOPC);
8339 ins_encode(z_rreform(dst, src));
8340 ins_pipe(pipe_class_dummy);
8341 %}
8342
8343 // Zero-extend convert int to long.
8344 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8345 match(Set dst (AndL (ConvI2L src) mask));
8346 size(4);
8347 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8348 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8349 ins_pipe(pipe_class_dummy);
8350 %}
8351
8352 // Zero-extend convert int to long.
8353 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8354 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8355 // Uses load_const_optmized, so size can vary.
8356 // TODO: s390 port size(VARIABLE_SIZE);
8357 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8358 opcode(LLGF_ZOPC, LLGF_ZOPC);
8359 ins_encode(z_form_rt_mem_opt(dst, src));
8360 ins_pipe(pipe_class_dummy);
8361 %}
8362
8363 // Zero-extend long
8364 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8365 match(Set dst (AndL src mask));
8366 size(4);
8367 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8368 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8369 ins_pipe(pipe_class_dummy);
8370 %}
8371
8372 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8373 match(Set dst (RShiftI (LShiftI src amount) amount));
8374 size(4);
8375 format %{ "LHR $dst,$src\t short->int" %}
8376 opcode(LHR_ZOPC);
8377 ins_encode(z_rreform(dst, src));
8378 ins_pipe(pipe_class_dummy);
8379 %}
8380
8381 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8382 match(Set dst (RShiftI (LShiftI src amount) amount));
8383 size(4);
8384 format %{ "LBR $dst,$src\t byte->int" %}
8385 opcode(LBR_ZOPC);
8386 ins_encode(z_rreform(dst, src));
8387 ins_pipe(pipe_class_dummy);
8388 %}
8389
8390 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8391 match(Set dst (MoveF2I src));
8392 ins_cost(MEMORY_REF_COST);
8393 size(4);
8394 format %{ "L $dst,$src\t # MoveF2I" %}
8395 opcode(L_ZOPC);
8396 ins_encode(z_form_rt_mem(dst, src));
8397 ins_pipe(pipe_class_dummy);
8398 %}
8399
8400 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8401 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8402 match(Set dst (MoveI2F src));
8403 ins_cost(MEMORY_REF_COST);
8404 // TODO: s390 port size(FIXED_SIZE);
8405 format %{ "LE $dst,$src\t # MoveI2F" %}
8406 opcode(LE_ZOPC);
8407 ins_encode(z_form_rt_mem(dst, src));
8408 ins_pipe(pipe_class_dummy);
8409 %}
8410
8411 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8412 match(Set dst (MoveD2L src));
8413 ins_cost(MEMORY_REF_COST);
8414 size(6);
8415 format %{ "LG $src,$dst\t # MoveD2L" %}
8416 opcode(LG_ZOPC);
8417 ins_encode(z_form_rt_mem(dst, src));
8418 ins_pipe(pipe_class_dummy);
8419 %}
8420
8421 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8422 match(Set dst (MoveL2D src));
8423 ins_cost(MEMORY_REF_COST);
8424 size(4);
8425 format %{ "LD $dst,$src\t # MoveL2D" %}
8426 opcode(LD_ZOPC);
8427 ins_encode(z_form_rt_mem(dst, src));
8428 ins_pipe(pipe_class_dummy);
8429 %}
8430
8431 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8432 match(Set dst (MoveI2F src));
8433 ins_cost(MEMORY_REF_COST);
8434 size(4);
8435 format %{ "ST $src,$dst\t # MoveI2F" %}
8436 opcode(ST_ZOPC);
8437 ins_encode(z_form_rt_mem(src, dst));
8438 ins_pipe(pipe_class_dummy);
8439 %}
8440
8441 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8442 match(Set dst (MoveD2L src));
8443 effect(DEF dst, USE src);
8444 ins_cost(MEMORY_REF_COST);
8445 size(4);
8446 format %{ "STD $src,$dst\t # MoveD2L" %}
8447 opcode(STD_ZOPC);
8448 ins_encode(z_form_rt_mem(src,dst));
8449 ins_pipe(pipe_class_dummy);
8450 %}
8451
8452 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8453 match(Set dst (MoveL2D src));
8454 ins_cost(MEMORY_REF_COST);
8455 size(6);
8456 format %{ "STG $src,$dst\t # MoveL2D" %}
8457 opcode(STG_ZOPC);
8458 ins_encode(z_form_rt_mem(src,dst));
8459 ins_pipe(pipe_class_dummy);
8460 %}
8461
8462 instruct convL2F_reg(regF dst, iRegL src) %{
8463 match(Set dst (ConvL2F src));
8464 // CC remains unchanged.
8465 ins_cost(DEFAULT_COST);
8466 size(4);
8467 format %{ "CEGBR $dst,$src" %}
8468 opcode(CEGBR_ZOPC);
8469 ins_encode(z_rreform(dst, src));
8470 ins_pipe(pipe_class_dummy);
8471 %}
8472
8473 instruct convL2D_reg(regD dst, iRegL src) %{
8474 match(Set dst (ConvL2D src));
8475 // CC remains unchanged.
8476 ins_cost(DEFAULT_COST);
8477 size(4);
8478 format %{ "CDGBR $dst,$src" %}
8479 opcode(CDGBR_ZOPC);
8480 ins_encode(z_rreform(dst, src));
8481 ins_pipe(pipe_class_dummy);
8482 %}
8483
8484 instruct convL2I_reg(iRegI dst, iRegL src) %{
8485 match(Set dst (ConvL2I src));
8486 // TODO: s390 port size(VARIABLE_SIZE);
8487 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8488 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8489 ins_pipe(pipe_class_dummy);
8490 %}
8491
8492 // Register Shift Right Immediate
8493 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8494 match(Set dst (ConvL2I (RShiftL src cnt)));
8495 effect(KILL cr);
8496 size(6);
8497 format %{ "SRAG $dst,$src,$cnt" %}
8498 opcode(SRAG_ZOPC);
8499 ins_encode(z_rsyform_const(dst, src, cnt));
8500 ins_pipe(pipe_class_dummy);
8501 %}
8502
8503 //----------TRAP based zero checks and range checks----------------------------
8504
8505 // SIGTRAP based implicit range checks in compiled code.
8506 // A range check in the ideal world has one of the following shapes:
8507 // - (If le (CmpU length index)), (IfTrue throw exception)
8508 // - (If lt (CmpU index length)), (IfFalse throw exception)
8509 //
8510 // Match range check 'If le (CmpU length index)'
8511 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8512 match(If cmp (CmpU length index));
8513 effect(USE labl);
8514 predicate(TrapBasedRangeChecks &&
8515 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8516 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8517 Matcher::branches_to_uncommon_trap(_leaf));
8518 ins_cost(1);
8519 // TODO: s390 port size(FIXED_SIZE);
8520
8521 ins_is_TrapBasedCheckNode(true);
8522
8523 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8524 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8525 ins_pipe(pipe_class_trap);
8526 %}
8527
8528 // Match range check 'If lt (CmpU index length)'
8529 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8530 match(If cmp (CmpU index length));
8531 effect(USE labl, KILL cr);
8532 predicate(TrapBasedRangeChecks &&
8533 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8534 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8535 Matcher::branches_to_uncommon_trap(_leaf));
8536 ins_cost(1);
8537 // TODO: s390 port size(FIXED_SIZE);
8538
8539 ins_is_TrapBasedCheckNode(true);
8540
8541 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8542 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8543 ins_pipe(pipe_class_trap);
8544 %}
8545
8546 // Match range check 'If lt (CmpU index length)'
8547 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8548 match(If cmp (CmpU index length));
8549 effect(USE labl);
8550 predicate(TrapBasedRangeChecks &&
8551 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8552 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8553 Matcher::branches_to_uncommon_trap(_leaf));
8554 ins_cost(1);
8555 // TODO: s390 port size(FIXED_SIZE);
8556
8557 ins_is_TrapBasedCheckNode(true);
8558
8559 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8560 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8561 ins_pipe(pipe_class_trap);
8562 %}
8563
8564 // Implicit zero checks (more implicit null checks).
8565 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8566 match(If cmp (CmpP value zero));
8567 effect(USE labl);
8568 predicate(TrapBasedNullChecks &&
8569 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8570 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8571 Matcher::branches_to_uncommon_trap(_leaf));
8572 size(6);
8573
8574 ins_is_TrapBasedCheckNode(true);
8575
8576 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8577 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8578 ins_pipe(pipe_class_trap);
8579 %}
8580
8581 // Implicit zero checks (more implicit null checks).
8582 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8583 match(If cmp (CmpN value zero));
8584 effect(USE labl);
8585 predicate(TrapBasedNullChecks &&
8586 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8587 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8588 Matcher::branches_to_uncommon_trap(_leaf));
8589 size(6);
8590
8591 ins_is_TrapBasedCheckNode(true);
8592
8593 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8594 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8595 ins_pipe(pipe_class_trap);
8596 %}
8597
8598 //----------Compare instructions-----------------------------------------------
8599
8600 // INT signed
8601
8602 // Compare Integers
8603 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8604 match(Set cr (CmpI op1 op2));
8605 size(2);
8606 format %{ "CR $op1,$op2" %}
8607 opcode(CR_ZOPC);
8608 ins_encode(z_rrform(op1, op2));
8609 ins_pipe(pipe_class_dummy);
8610 %}
8611
8612 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8613 match(Set cr (CmpI op1 op2));
8614 size(6);
8615 format %{ "CFI $op1,$op2" %}
8616 opcode(CFI_ZOPC);
8617 ins_encode(z_rilform_signed(op1, op2));
8618 ins_pipe(pipe_class_dummy);
8619 %}
8620
8621 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8622 match(Set cr (CmpI op1 op2));
8623 size(4);
8624 format %{ "CHI $op1,$op2" %}
8625 opcode(CHI_ZOPC);
8626 ins_encode(z_riform_signed(op1, op2));
8627 ins_pipe(pipe_class_dummy);
8628 %}
8629
8630 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8631 match(Set cr (CmpI op1 zero));
8632 ins_cost(DEFAULT_COST_LOW);
8633 size(2);
8634 format %{ "LTR $op1,$op1" %}
8635 opcode(LTR_ZOPC);
8636 ins_encode(z_rrform(op1, op1));
8637 ins_pipe(pipe_class_dummy);
8638 %}
8639
8640 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8641 match(Set cr (CmpI op1 (LoadI op2)));
8642 ins_cost(MEMORY_REF_COST);
8643 // TODO: s390 port size(VARIABLE_SIZE);
8644 format %{ "C(Y) $op1, $op2\t # int" %}
8645 opcode(CY_ZOPC, C_ZOPC);
8646 ins_encode(z_form_rt_mem_opt(op1, op2));
8647 ins_pipe(pipe_class_dummy);
8648 %}
8649
8650 // INT unsigned
8651
8652 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8653 match(Set cr (CmpU op1 op2));
8654 size(2);
8655 format %{ "CLR $op1,$op2\t # unsigned" %}
8656 opcode(CLR_ZOPC);
8657 ins_encode(z_rrform(op1, op2));
8658 ins_pipe(pipe_class_dummy);
8659 %}
8660
8661 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8662 match(Set cr (CmpU op1 op2));
8663 size(6);
8664 format %{ "CLFI $op1,$op2\t # unsigned" %}
8665 opcode(CLFI_ZOPC);
8666 ins_encode(z_rilform_unsigned(op1, op2));
8667 ins_pipe(pipe_class_dummy);
8668 %}
8669
8670 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8671 match(Set cr (CmpU op1 (LoadI op2)));
8672 ins_cost(MEMORY_REF_COST);
8673 // TODO: s390 port size(VARIABLE_SIZE);
8674 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8675 opcode(CLY_ZOPC, CL_ZOPC);
8676 ins_encode(z_form_rt_mem_opt(op1, op2));
8677 ins_pipe(pipe_class_dummy);
8678 %}
8679
8680 // LONG signed
8681
8682 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8683 match(Set cr (CmpL op1 op2));
8684 size(4);
8685 format %{ "CGR $op1,$op2\t # long" %}
8686 opcode(CGR_ZOPC);
8687 ins_encode(z_rreform(op1, op2));
8688 ins_pipe(pipe_class_dummy);
8689 %}
8690
8691 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8692 match(Set cr (CmpL op1 (ConvI2L op2)));
8693 size(4);
8694 format %{ "CGFR $op1,$op2\t # long/int" %}
8695 opcode(CGFR_ZOPC);
8696 ins_encode(z_rreform(op1, op2));
8697 ins_pipe(pipe_class_dummy);
8698 %}
8699
8700 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8701 match(Set cr (CmpL op1 con));
8702 size(6);
8703 format %{ "CGFI $op1,$con" %}
8704 opcode(CGFI_ZOPC);
8705 ins_encode(z_rilform_signed(op1, con));
8706 ins_pipe(pipe_class_dummy);
8707 %}
8708
8709 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8710 match(Set cr (CmpL op1 con));
8711 size(4);
8712 format %{ "CGHI $op1,$con" %}
8713 opcode(CGHI_ZOPC);
8714 ins_encode(z_riform_signed(op1, con));
8715 ins_pipe(pipe_class_dummy);
8716 %}
8717
8718 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8719 match(Set cr (CmpL op1 con));
8720 ins_cost(DEFAULT_COST_LOW);
8721 size(4);
8722 format %{ "LTGR $op1,$op1" %}
8723 opcode(LTGR_ZOPC);
8724 ins_encode(z_rreform(op1, op1));
8725 ins_pipe(pipe_class_dummy);
8726 %}
8727
8728 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8729 match(Set cr (CmpL (ConvI2L op1) con));
8730 ins_cost(DEFAULT_COST_LOW);
8731 size(4);
8732 format %{ "LTGFR $op1,$op1" %}
8733 opcode(LTGFR_ZOPC);
8734 ins_encode(z_rreform(op1, op1));
8735 ins_pipe(pipe_class_dummy);
8736 %}
8737
8738 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8739 match(Set cr (CmpL dst (LoadL src)));
8740 ins_cost(MEMORY_REF_COST);
8741 size(Z_DISP3_SIZE);
8742 format %{ "CG $dst, $src\t # long" %}
8743 opcode(CG_ZOPC, CG_ZOPC);
8744 ins_encode(z_form_rt_mem_opt(dst, src));
8745 ins_pipe(pipe_class_dummy);
8746 %}
8747
8748 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8749 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8750 ins_cost(MEMORY_REF_COST);
8751 size(Z_DISP3_SIZE);
8752 format %{ "CGF $dst, $src\t # long/int" %}
8753 opcode(CGF_ZOPC, CGF_ZOPC);
8754 ins_encode(z_form_rt_mem_opt(dst, src));
8755 ins_pipe(pipe_class_dummy);
8756 %}
8757
8758 // LONG unsigned
8759 // Added CmpUL for LoopPredicate.
8760 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8761 match(Set cr (CmpUL op1 op2));
8762 size(4);
8763 format %{ "CLGR $op1,$op2\t # long" %}
8764 opcode(CLGR_ZOPC);
8765 ins_encode(z_rreform(op1, op2));
8766 ins_pipe(pipe_class_dummy);
8767 %}
8768
8769 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8770 match(Set cr (CmpUL op1 con));
8771 size(6);
8772 format %{ "CLGFI $op1,$con" %}
8773 opcode(CLGFI_ZOPC);
8774 ins_encode(z_rilform_unsigned(op1, con));
8775 ins_pipe(pipe_class_dummy);
8776 %}
8777
8778 // PTR unsigned
8779
8780 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8781 match(Set cr (CmpP op1 op2));
8782 size(4);
8783 format %{ "CLGR $op1,$op2\t # ptr" %}
8784 opcode(CLGR_ZOPC);
8785 ins_encode(z_rreform(op1, op2));
8786 ins_pipe(pipe_class_dummy);
8787 %}
8788
8789 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8790 match(Set cr (CmpP op1 op2));
8791 ins_cost(DEFAULT_COST_LOW);
8792 size(4);
8793 format %{ "LTGR $op1, $op1\t # ptr" %}
8794 opcode(LTGR_ZOPC);
8795 ins_encode(z_rreform(op1, op1));
8796 ins_pipe(pipe_class_dummy);
8797 %}
8798
8799 // Don't use LTGFR which performs sign extend.
8800 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8801 match(Set cr (CmpP (DecodeN op1) op2));
8802 predicate(CompressedOops::base() == nullptr && CompressedOops::shift() == 0);
8803 ins_cost(DEFAULT_COST_LOW);
8804 size(2);
8805 format %{ "LTR $op1, $op1\t # ptr" %}
8806 opcode(LTR_ZOPC);
8807 ins_encode(z_rrform(op1, op1));
8808 ins_pipe(pipe_class_dummy);
8809 %}
8810
8811 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8812 match(Set cr (CmpP dst (LoadP src)));
8813 predicate(n->in(2)->as_Load()->barrier_data() == 0);
8814 ins_cost(MEMORY_REF_COST);
8815 size(Z_DISP3_SIZE);
8816 format %{ "CLG $dst, $src\t # ptr" %}
8817 opcode(CLG_ZOPC, CLG_ZOPC);
8818 ins_encode(z_form_rt_mem_opt(dst, src));
8819 ins_pipe(pipe_class_dummy);
8820 %}
8821
8822 //----------Max and Min--------------------------------------------------------
8823
8824 // Max Register with Register
8825 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8826 match(Set dst (MinI src1 src2));
8827 effect(KILL cr);
8828 predicate(VM_Version::has_LoadStoreConditional());
8829 ins_cost(3 * DEFAULT_COST);
8830 // TODO: s390 port size(VARIABLE_SIZE);
8831 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8832 ins_encode %{
8833 Register Rdst = $dst$$Register;
8834 Register Rsrc1 = $src1$$Register;
8835 Register Rsrc2 = $src2$$Register;
8836
8837 if (Rsrc1 == Rsrc2) {
8838 if (Rdst != Rsrc1) {
8839 __ z_lgfr(Rdst, Rsrc1);
8840 }
8841 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8842 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8843 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8844 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8845 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8846 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8847 } else {
8848 // Rdst is disjoint from operands, move in either case.
8849 __ z_cr(Rsrc1, Rsrc2);
8850 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8851 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8852 }
8853 %}
8854 ins_pipe(pipe_class_dummy);
8855 %}
8856
8857 // Min Register with Register.
8858 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8859 match(Set dst (MinI src1 src2));
8860 effect(KILL cr);
8861 predicate(VM_Version::has_CompareBranch());
8862 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8863 // TODO: s390 port size(VARIABLE_SIZE);
8864 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8865 ins_encode %{
8866 Register Rdst = $dst$$Register;
8867 Register Rsrc1 = $src1$$Register;
8868 Register Rsrc2 = $src2$$Register;
8869 Label done;
8870
8871 if (Rsrc1 == Rsrc2) {
8872 if (Rdst != Rsrc1) {
8873 __ z_lgfr(Rdst, Rsrc1);
8874 }
8875 } else if (Rdst == Rsrc1) {
8876 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8877 __ z_lgfr(Rdst, Rsrc2);
8878 } else if (Rdst == Rsrc2) {
8879 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8880 __ z_lgfr(Rdst, Rsrc1);
8881 } else {
8882 __ z_lgfr(Rdst, Rsrc1);
8883 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8884 __ z_lgfr(Rdst, Rsrc2);
8885 }
8886 __ bind(done);
8887 %}
8888 ins_pipe(pipe_class_dummy);
8889 %}
8890
8891 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8892 match(Set dst (MinI src1 src2));
8893 effect(KILL cr);
8894 predicate(!VM_Version::has_CompareBranch());
8895 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8896 // TODO: s390 port size(VARIABLE_SIZE);
8897 format %{ "MinI $dst $src1,$src2\t MinI" %}
8898 ins_encode %{
8899 Register Rdst = $dst$$Register;
8900 Register Rsrc1 = $src1$$Register;
8901 Register Rsrc2 = $src2$$Register;
8902 Label done;
8903
8904 if (Rsrc1 == Rsrc2) {
8905 if (Rdst != Rsrc1) {
8906 __ z_lgfr(Rdst, Rsrc1);
8907 }
8908 } else if (Rdst == Rsrc1) {
8909 __ z_cr(Rsrc1, Rsrc2);
8910 __ z_brl(done);
8911 __ z_lgfr(Rdst, Rsrc2);
8912 } else if (Rdst == Rsrc2) {
8913 __ z_cr(Rsrc2, Rsrc1);
8914 __ z_brl(done);
8915 __ z_lgfr(Rdst, Rsrc1);
8916 } else {
8917 __ z_lgfr(Rdst, Rsrc1);
8918 __ z_cr(Rsrc1, Rsrc2);
8919 __ z_brl(done);
8920 __ z_lgfr(Rdst, Rsrc2);
8921 }
8922 __ bind(done);
8923 %}
8924 ins_pipe(pipe_class_dummy);
8925 %}
8926
8927 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8928 match(Set dst (MinI src1 src2));
8929 effect(KILL cr);
8930 predicate(VM_Version::has_LoadStoreConditional());
8931 ins_cost(3 * DEFAULT_COST);
8932 // TODO: s390 port size(VARIABLE_SIZE);
8933 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8934 ins_encode %{
8935 Register Rdst = $dst$$Register;
8936 Register Rsrc1 = $src1$$Register;
8937 int Isrc2 = $src2$$constant;
8938
8939 if (Rdst == Rsrc1) {
8940 __ load_const_optimized(Z_R0_scratch, Isrc2);
8941 __ z_cfi(Rsrc1, Isrc2);
8942 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8943 } else {
8944 __ load_const_optimized(Rdst, Isrc2);
8945 __ z_cfi(Rsrc1, Isrc2);
8946 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8947 }
8948 %}
8949 ins_pipe(pipe_class_dummy);
8950 %}
8951
8952 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8953 match(Set dst (MinI src1 src2));
8954 effect(KILL cr);
8955 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8956 // TODO: s390 port size(VARIABLE_SIZE);
8957 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8958 ins_encode %{
8959 Label done;
8960 if ($dst$$Register != $src1$$Register) {
8961 __ z_lgfr($dst$$Register, $src1$$Register);
8962 }
8963 __ z_cfi($src1$$Register, $src2$$constant);
8964 __ z_brl(done);
8965 __ z_lgfi($dst$$Register, $src2$$constant);
8966 __ bind(done);
8967 %}
8968 ins_pipe(pipe_class_dummy);
8969 %}
8970
8971 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8972 match(Set dst (MinI src1 src2));
8973 effect(KILL cr);
8974 predicate(VM_Version::has_LoadStoreConditional());
8975 ins_cost(3 * DEFAULT_COST);
8976 // TODO: s390 port size(VARIABLE_SIZE);
8977 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8978 ins_encode %{
8979 Register Rdst = $dst$$Register;
8980 Register Rsrc1 = $src1$$Register;
8981 int Isrc2 = $src2$$constant;
8982
8983 if (Rdst == Rsrc1) {
8984 __ load_const_optimized(Z_R0_scratch, Isrc2);
8985 __ z_chi(Rsrc1, Isrc2);
8986 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8987 } else {
8988 __ load_const_optimized(Rdst, Isrc2);
8989 __ z_chi(Rsrc1, Isrc2);
8990 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8991 }
8992 %}
8993 ins_pipe(pipe_class_dummy);
8994 %}
8995
8996 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8997 match(Set dst (MinI src1 src2));
8998 effect(KILL cr);
8999 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9000 // TODO: s390 port size(VARIABLE_SIZE);
9001 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
9002 ins_encode %{
9003 Label done;
9004 if ($dst$$Register != $src1$$Register) {
9005 __ z_lgfr($dst$$Register, $src1$$Register);
9006 }
9007 __ z_chi($src1$$Register, $src2$$constant);
9008 __ z_brl(done);
9009 __ z_lghi($dst$$Register, $src2$$constant);
9010 __ bind(done);
9011 %}
9012 ins_pipe(pipe_class_dummy);
9013 %}
9014
9015 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
9016 match(Set dst (MinI src1 src2));
9017 effect(KILL cr);
9018 predicate(VM_Version::has_CompareBranch());
9019 ins_cost(DEFAULT_COST + BRANCH_COST);
9020 // TODO: s390 port size(VARIABLE_SIZE);
9021 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
9022 ins_encode %{
9023 Label done;
9024 if ($dst$$Register != $src1$$Register) {
9025 __ z_lgfr($dst$$Register, $src1$$Register);
9026 }
9027 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
9028 __ z_lghi($dst$$Register, $src2$$constant);
9029 __ bind(done);
9030 %}
9031 ins_pipe(pipe_class_dummy);
9032 %}
9033
9034 // Max Register with Register
9035 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9036 match(Set dst (MaxI src1 src2));
9037 effect(KILL cr);
9038 predicate(VM_Version::has_LoadStoreConditional());
9039 ins_cost(3 * DEFAULT_COST);
9040 // TODO: s390 port size(VARIABLE_SIZE);
9041 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
9042 ins_encode %{
9043 Register Rdst = $dst$$Register;
9044 Register Rsrc1 = $src1$$Register;
9045 Register Rsrc2 = $src2$$Register;
9046
9047 if (Rsrc1 == Rsrc2) {
9048 if (Rdst != Rsrc1) {
9049 __ z_lgfr(Rdst, Rsrc1);
9050 }
9051 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
9052 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
9053 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
9054 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
9055 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
9056 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
9057 } else { // Rdst is disjoint from operands, move in either case.
9058 __ z_cr(Rsrc1, Rsrc2);
9059 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
9060 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9061 }
9062 %}
9063 ins_pipe(pipe_class_dummy);
9064 %}
9065
9066 // Max Register with Register
9067 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9068 match(Set dst (MaxI src1 src2));
9069 effect(KILL cr);
9070 predicate(VM_Version::has_CompareBranch());
9071 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9072 // TODO: s390 port size(VARIABLE_SIZE);
9073 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
9074 ins_encode %{
9075 Register Rdst = $dst$$Register;
9076 Register Rsrc1 = $src1$$Register;
9077 Register Rsrc2 = $src2$$Register;
9078 Label done;
9079
9080 if (Rsrc1 == Rsrc2) {
9081 if (Rdst != Rsrc1) {
9082 __ z_lgfr(Rdst, Rsrc1);
9083 }
9084 } else if (Rdst == Rsrc1) {
9085 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9086 __ z_lgfr(Rdst, Rsrc2);
9087 } else if (Rdst == Rsrc2) {
9088 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
9089 __ z_lgfr(Rdst, Rsrc1);
9090 } else {
9091 __ z_lgfr(Rdst, Rsrc1);
9092 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
9093 __ z_lgfr(Rdst, Rsrc2);
9094 }
9095 __ bind(done);
9096 %}
9097 ins_pipe(pipe_class_dummy);
9098 %}
9099
9100 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
9101 match(Set dst (MaxI src1 src2));
9102 effect(KILL cr);
9103 predicate(!VM_Version::has_CompareBranch());
9104 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
9105 // TODO: s390 port size(VARIABLE_SIZE);
9106 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
9107 ins_encode %{
9108 Register Rdst = $dst$$Register;
9109 Register Rsrc1 = $src1$$Register;
9110 Register Rsrc2 = $src2$$Register;
9111 Label done;
9112
9113 if (Rsrc1 == Rsrc2) {
9114 if (Rdst != Rsrc1) {
9115 __ z_lgfr(Rdst, Rsrc1);
9116 }
9117 } else if (Rdst == Rsrc1) {
9118 __ z_cr(Rsrc1, Rsrc2);
9119 __ z_brh(done);
9120 __ z_lgfr(Rdst, Rsrc2);
9121 } else if (Rdst == Rsrc2) {
9122 __ z_cr(Rsrc2, Rsrc1);
9123 __ z_brh(done);
9124 __ z_lgfr(Rdst, Rsrc1);
9125 } else {
9126 __ z_lgfr(Rdst, Rsrc1);
9127 __ z_cr(Rsrc1, Rsrc2);
9128 __ z_brh(done);
9129 __ z_lgfr(Rdst, Rsrc2);
9130 }
9131
9132 __ bind(done);
9133 %}
9134
9135 ins_pipe(pipe_class_dummy);
9136 %}
9137
9138 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9139 match(Set dst (MaxI src1 src2));
9140 effect(KILL cr);
9141 predicate(VM_Version::has_LoadStoreConditional());
9142 ins_cost(3 * DEFAULT_COST);
9143 // TODO: s390 port size(VARIABLE_SIZE);
9144 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
9145 ins_encode %{
9146 Register Rdst = $dst$$Register;
9147 Register Rsrc1 = $src1$$Register;
9148 int Isrc2 = $src2$$constant;
9149
9150 if (Rdst == Rsrc1) {
9151 __ load_const_optimized(Z_R0_scratch, Isrc2);
9152 __ z_cfi(Rsrc1, Isrc2);
9153 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9154 } else {
9155 __ load_const_optimized(Rdst, Isrc2);
9156 __ z_cfi(Rsrc1, Isrc2);
9157 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9158 }
9159 %}
9160 ins_pipe(pipe_class_dummy);
9161 %}
9162
9163 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
9164 match(Set dst (MaxI src1 src2));
9165 effect(KILL cr);
9166 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9167 // TODO: s390 port size(VARIABLE_SIZE);
9168 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
9169 ins_encode %{
9170 Label done;
9171 if ($dst$$Register != $src1$$Register) {
9172 __ z_lgfr($dst$$Register, $src1$$Register);
9173 }
9174 __ z_cfi($src1$$Register, $src2$$constant);
9175 __ z_brh(done);
9176 __ z_lgfi($dst$$Register, $src2$$constant);
9177 __ bind(done);
9178 %}
9179 ins_pipe(pipe_class_dummy);
9180 %}
9181
9182 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9183 match(Set dst (MaxI src1 src2));
9184 effect(KILL cr);
9185 predicate(VM_Version::has_LoadStoreConditional());
9186 ins_cost(3 * DEFAULT_COST);
9187 // TODO: s390 port size(VARIABLE_SIZE);
9188 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
9189 ins_encode %{
9190 Register Rdst = $dst$$Register;
9191 Register Rsrc1 = $src1$$Register;
9192 int Isrc2 = $src2$$constant;
9193 if (Rdst == Rsrc1) {
9194 __ load_const_optimized(Z_R0_scratch, Isrc2);
9195 __ z_chi(Rsrc1, Isrc2);
9196 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
9197 } else {
9198 __ load_const_optimized(Rdst, Isrc2);
9199 __ z_chi(Rsrc1, Isrc2);
9200 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
9201 }
9202 %}
9203 ins_pipe(pipe_class_dummy);
9204 %}
9205
9206 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
9207 match(Set dst (MaxI src1 src2));
9208 effect(KILL cr);
9209 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
9210 // TODO: s390 port size(VARIABLE_SIZE);
9211 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
9212 ins_encode %{
9213 Label done;
9214 if ($dst$$Register != $src1$$Register) {
9215 __ z_lgfr($dst$$Register, $src1$$Register);
9216 }
9217 __ z_chi($src1$$Register, $src2$$constant);
9218 __ z_brh(done);
9219 __ z_lghi($dst$$Register, $src2$$constant);
9220 __ bind(done);
9221 %}
9222 ins_pipe(pipe_class_dummy);
9223 %}
9224
9225 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
9226 match(Set dst (MaxI src1 src2));
9227 effect(KILL cr);
9228 predicate(VM_Version::has_CompareBranch());
9229 ins_cost(DEFAULT_COST + BRANCH_COST);
9230 // TODO: s390 port size(VARIABLE_SIZE);
9231 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
9232 ins_encode %{
9233 Label done;
9234 if ($dst$$Register != $src1$$Register) {
9235 __ z_lgfr($dst$$Register, $src1$$Register);
9236 }
9237 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
9238 __ z_lghi($dst$$Register, $src2$$constant);
9239 __ bind(done);
9240 %}
9241 ins_pipe(pipe_class_dummy);
9242 %}
9243
9244 //----------Abs---------------------------------------------------------------
9245
9246 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
9247 match(Set dst (AbsI src));
9248 effect(KILL cr);
9249 ins_cost(DEFAULT_COST_LOW);
9250 // TODO: s390 port size(FIXED_SIZE);
9251 format %{ "LPR $dst, $src" %}
9252 opcode(LPR_ZOPC);
9253 ins_encode(z_rrform(dst, src));
9254 ins_pipe(pipe_class_dummy);
9255 %}
9256
9257 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
9258 match(Set dst (AbsL src));
9259 effect(KILL cr);
9260 ins_cost(DEFAULT_COST_LOW);
9261 // TODO: s390 port size(FIXED_SIZE);
9262 format %{ "LPGR $dst, $src" %}
9263 opcode(LPGR_ZOPC);
9264 ins_encode(z_rreform(dst, src));
9265 ins_pipe(pipe_class_dummy);
9266 %}
9267
9268 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9269 match(Set dst (SubI zero (AbsI src)));
9270 effect(KILL cr);
9271 ins_cost(DEFAULT_COST_LOW);
9272 // TODO: s390 port size(FIXED_SIZE);
9273 format %{ "LNR $dst, $src" %}
9274 opcode(LNR_ZOPC);
9275 ins_encode(z_rrform(dst, src));
9276 ins_pipe(pipe_class_dummy);
9277 %}
9278
9279 //----------Float Compares----------------------------------------------------
9280
9281 // Compare floating, generate condition code.
9282 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9283 match(Set cr (CmpF src1 src2));
9284 ins_cost(ALU_REG_COST);
9285 size(4);
9286 format %{ "FCMPcc $src1,$src2\t # float" %}
9287 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9288 ins_pipe(pipe_class_dummy);
9289 %}
9290
9291 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9292 match(Set cr (CmpD src1 src2));
9293 ins_cost(ALU_REG_COST);
9294 size(4);
9295 format %{ "FCMPcc $src1,$src2 \t # double" %}
9296 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9297 ins_pipe(pipe_class_dummy);
9298 %}
9299
9300 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9301 match(Set cr (CmpF src1 (LoadF src2)));
9302 ins_cost(ALU_MEMORY_COST);
9303 size(6);
9304 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9305 opcode(CEB_ZOPC);
9306 ins_encode(z_form_rt_memFP(src1, src2));
9307 ins_pipe(pipe_class_dummy);
9308 %}
9309
9310 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9311 match(Set cr (CmpD src1 (LoadD src2)));
9312 ins_cost(ALU_MEMORY_COST);
9313 size(6);
9314 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9315 opcode(CDB_ZOPC);
9316 ins_encode(z_form_rt_memFP(src1, src2));
9317 ins_pipe(pipe_class_dummy);
9318 %}
9319
9320 // Compare floating, generate condition code
9321 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9322 match(Set cr (CmpF src1 src2));
9323 ins_cost(DEFAULT_COST);
9324 size(4);
9325 format %{ "LTEBR $src1,$src1\t # float" %}
9326 opcode(LTEBR_ZOPC);
9327 ins_encode(z_rreform(src1, src1));
9328 ins_pipe(pipe_class_dummy);
9329 %}
9330
9331 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9332 match(Set cr (CmpD src1 src2));
9333 ins_cost(DEFAULT_COST);
9334 size(4);
9335 format %{ "LTDBR $src1,$src1 \t # double" %}
9336 opcode(LTDBR_ZOPC);
9337 ins_encode(z_rreform(src1, src1));
9338 ins_pipe(pipe_class_dummy);
9339 %}
9340
9341 // Compare floating, generate -1,0,1
9342 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9343 match(Set dst (CmpF3 src1 src2));
9344 effect(KILL cr);
9345 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9346 size(24);
9347 format %{ "CmpF3 $dst,$src1,$src2" %}
9348 ins_encode %{
9349 // compare registers
9350 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9351 // Convert condition code into -1,0,1, where
9352 // -1 means unordered or less
9353 // 0 means equal
9354 // 1 means greater.
9355 if (VM_Version::has_LoadStoreConditional()) {
9356 Register one = Z_R0_scratch;
9357 Register minus_one = Z_R1_scratch;
9358 __ z_lghi(minus_one, -1);
9359 __ z_lghi(one, 1);
9360 __ z_lghi( $dst$$Register, 0);
9361 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9362 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9363 } else {
9364 Label done;
9365 __ clear_reg($dst$$Register, true, false);
9366 __ z_bre(done);
9367 __ z_lhi($dst$$Register, 1);
9368 __ z_brh(done);
9369 __ z_lhi($dst$$Register, -1);
9370 __ bind(done);
9371 }
9372 %}
9373 ins_pipe(pipe_class_dummy);
9374 %}
9375
9376 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9377 match(Set dst (CmpD3 src1 src2));
9378 effect(KILL cr);
9379 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9380 size(24);
9381 format %{ "CmpD3 $dst,$src1,$src2" %}
9382 ins_encode %{
9383 // compare registers
9384 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9385 // Convert condition code into -1,0,1, where
9386 // -1 means unordered or less
9387 // 0 means equal
9388 // 1 means greater.
9389 if (VM_Version::has_LoadStoreConditional()) {
9390 Register one = Z_R0_scratch;
9391 Register minus_one = Z_R1_scratch;
9392 __ z_lghi(minus_one, -1);
9393 __ z_lghi(one, 1);
9394 __ z_lghi( $dst$$Register, 0);
9395 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9396 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9397 } else {
9398 Label done;
9399 // indicate unused result
9400 (void) __ clear_reg($dst$$Register, true, false);
9401 __ z_bre(done);
9402 __ z_lhi($dst$$Register, 1);
9403 __ z_brh(done);
9404 __ z_lhi($dst$$Register, -1);
9405 __ bind(done);
9406 }
9407 %}
9408 ins_pipe(pipe_class_dummy);
9409 %}
9410
9411 //----------Branches---------------------------------------------------------
9412 // Jump
9413
9414 // Direct Branch.
9415 instruct branch(label labl) %{
9416 match(Goto);
9417 effect(USE labl);
9418 ins_cost(BRANCH_COST);
9419 size(4);
9420 format %{ "BRU $labl" %}
9421 ins_encode(z_enc_bru(labl));
9422 ins_pipe(pipe_class_dummy);
9423 // If set to 1 this indicates that the current instruction is a
9424 // short variant of a long branch. This avoids using this
9425 // instruction in first-pass matching. It will then only be used in
9426 // the `Shorten_branches' pass.
9427 ins_short_branch(1);
9428 %}
9429
9430 // Direct Branch.
9431 instruct branchFar(label labl) %{
9432 match(Goto);
9433 effect(USE labl);
9434 ins_cost(BRANCH_COST);
9435 size(6);
9436 format %{ "BRUL $labl" %}
9437 ins_encode(z_enc_brul(labl));
9438 ins_pipe(pipe_class_dummy);
9439 // This is not a short variant of a branch, but the long variant.
9440 ins_short_branch(0);
9441 %}
9442
9443 // Conditional Near Branch
9444 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9445 // Same match rule as `branchConFar'.
9446 match(If cmp cr);
9447 effect(USE lbl);
9448 ins_cost(BRANCH_COST);
9449 size(4);
9450 format %{ "branch_con_short,$cmp $lbl" %}
9451 ins_encode(z_enc_branch_con_short(cmp, lbl));
9452 ins_pipe(pipe_class_dummy);
9453 // If set to 1 this indicates that the current instruction is a
9454 // short variant of a long branch. This avoids using this
9455 // instruction in first-pass matching. It will then only be used in
9456 // the `Shorten_branches' pass.
9457 ins_short_branch(1);
9458 %}
9459
9460 // This is for cases when the z/Architecture conditional branch instruction
9461 // does not reach far enough. So we emit a far branch here, which is
9462 // more expensive.
9463 //
9464 // Conditional Far Branch
9465 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9466 // Same match rule as `branchCon'.
9467 match(If cmp cr);
9468 effect(USE cr, USE lbl);
9469 // Make more expensive to prefer compare_and_branch over separate instructions.
9470 ins_cost(2 * BRANCH_COST);
9471 size(6);
9472 format %{ "branch_con_far,$cmp $lbl" %}
9473 ins_encode(z_enc_branch_con_far(cmp, lbl));
9474 ins_pipe(pipe_class_dummy);
9475 // This is not a short variant of a branch, but the long variant..
9476 ins_short_branch(0);
9477 %}
9478
9479 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9480 match(CountedLoopEnd cmp cr);
9481 effect(USE labl);
9482 ins_cost(BRANCH_COST);
9483 size(4);
9484 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9485 ins_encode(z_enc_branch_con_short(cmp, labl));
9486 ins_pipe(pipe_class_dummy);
9487 // If set to 1 this indicates that the current instruction is a
9488 // short variant of a long branch. This avoids using this
9489 // instruction in first-pass matching. It will then only be used in
9490 // the `Shorten_branches' pass.
9491 ins_short_branch(1);
9492 %}
9493
9494 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9495 match(CountedLoopEnd cmp cr);
9496 effect(USE labl);
9497 ins_cost(BRANCH_COST);
9498 size(6);
9499 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9500 ins_encode(z_enc_branch_con_far(cmp, labl));
9501 ins_pipe(pipe_class_dummy);
9502 // This is not a short variant of a branch, but the long variant.
9503 ins_short_branch(0);
9504 %}
9505
9506 //----------Compare and Branch (short distance)------------------------------
9507
9508 // INT REG operands for loop counter processing.
9509 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9510 match(CountedLoopEnd boolnode (CmpI src1 src2));
9511 effect(USE labl, KILL cr);
9512 predicate(VM_Version::has_CompareBranch());
9513 ins_cost(BRANCH_COST);
9514 // TODO: s390 port size(FIXED_SIZE);
9515 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9516 opcode(CRJ_ZOPC);
9517 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9518 ins_pipe(pipe_class_dummy);
9519 ins_short_branch(1);
9520 %}
9521
9522 // INT REG operands.
9523 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9524 match(If boolnode (CmpI src1 src2));
9525 effect(USE labl, KILL cr);
9526 predicate(VM_Version::has_CompareBranch());
9527 ins_cost(BRANCH_COST);
9528 // TODO: s390 port size(FIXED_SIZE);
9529 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9530 opcode(CRJ_ZOPC);
9531 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9532 ins_pipe(pipe_class_dummy);
9533 ins_short_branch(1);
9534 %}
9535
9536 // Unsigned INT REG operands
9537 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9538 match(If boolnode (CmpU src1 src2));
9539 effect(USE labl, KILL cr);
9540 predicate(VM_Version::has_CompareBranch());
9541 ins_cost(BRANCH_COST);
9542 // TODO: s390 port size(FIXED_SIZE);
9543 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9544 opcode(CLRJ_ZOPC);
9545 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9546 ins_pipe(pipe_class_dummy);
9547 ins_short_branch(1);
9548 %}
9549
9550 // LONG REG operands
9551 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9552 match(If boolnode (CmpL src1 src2));
9553 effect(USE labl, KILL cr);
9554 predicate(VM_Version::has_CompareBranch());
9555 ins_cost(BRANCH_COST);
9556 // TODO: s390 port size(FIXED_SIZE);
9557 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9558 opcode(CGRJ_ZOPC);
9559 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9560 ins_pipe(pipe_class_dummy);
9561 ins_short_branch(1);
9562 %}
9563
9564 // PTR REG operands
9565
9566 // Separate rules for regular and narrow oops. ADLC can't recognize
9567 // rules with polymorphic operands to be sisters -> shorten_branches
9568 // will not shorten.
9569
9570 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9571 match(If boolnode (CmpP src1 src2));
9572 effect(USE labl, KILL cr);
9573 predicate(VM_Version::has_CompareBranch());
9574 ins_cost(BRANCH_COST);
9575 // TODO: s390 port size(FIXED_SIZE);
9576 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9577 opcode(CLGRJ_ZOPC);
9578 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9579 ins_pipe(pipe_class_dummy);
9580 ins_short_branch(1);
9581 %}
9582
9583 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9584 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9585 effect(USE labl, KILL cr);
9586 predicate(VM_Version::has_CompareBranch());
9587 ins_cost(BRANCH_COST);
9588 // TODO: s390 port size(FIXED_SIZE);
9589 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9590 opcode(CLGRJ_ZOPC);
9591 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9592 ins_pipe(pipe_class_dummy);
9593 ins_short_branch(1);
9594 %}
9595
9596 // INT REG/IMM operands for loop counter processing
9597 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9598 match(CountedLoopEnd boolnode (CmpI src1 src2));
9599 effect(USE labl, KILL cr);
9600 predicate(VM_Version::has_CompareBranch());
9601 ins_cost(BRANCH_COST);
9602 // TODO: s390 port size(FIXED_SIZE);
9603 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9604 opcode(CIJ_ZOPC);
9605 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9606 ins_pipe(pipe_class_dummy);
9607 ins_short_branch(1);
9608 %}
9609
9610 // INT REG/IMM operands
9611 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9612 match(If boolnode (CmpI src1 src2));
9613 effect(USE labl, KILL cr);
9614 predicate(VM_Version::has_CompareBranch());
9615 ins_cost(BRANCH_COST);
9616 // TODO: s390 port size(FIXED_SIZE);
9617 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9618 opcode(CIJ_ZOPC);
9619 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9620 ins_pipe(pipe_class_dummy);
9621 ins_short_branch(1);
9622 %}
9623
9624 // INT REG/IMM operands
9625 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9626 match(If boolnode (CmpU src1 src2));
9627 effect(USE labl, KILL cr);
9628 predicate(VM_Version::has_CompareBranch());
9629 ins_cost(BRANCH_COST);
9630 // TODO: s390 port size(FIXED_SIZE);
9631 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9632 opcode(CLIJ_ZOPC);
9633 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9634 ins_pipe(pipe_class_dummy);
9635 ins_short_branch(1);
9636 %}
9637
9638 // LONG REG/IMM operands
9639 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9640 match(If boolnode (CmpL src1 src2));
9641 effect(USE labl, KILL cr);
9642 predicate(VM_Version::has_CompareBranch());
9643 ins_cost(BRANCH_COST);
9644 // TODO: s390 port size(FIXED_SIZE);
9645 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9646 opcode(CGIJ_ZOPC);
9647 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9648 ins_pipe(pipe_class_dummy);
9649 ins_short_branch(1);
9650 %}
9651
9652 // PTR REG-imm operands
9653
9654 // Separate rules for regular and narrow oops. ADLC can't recognize
9655 // rules with polymorphic operands to be sisters -> shorten_branches
9656 // will not shorten.
9657
9658 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9659 match(If boolnode (CmpP src1 src2));
9660 effect(USE labl, KILL cr);
9661 predicate(VM_Version::has_CompareBranch());
9662 ins_cost(BRANCH_COST);
9663 // TODO: s390 port size(FIXED_SIZE);
9664 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9665 opcode(CLGIJ_ZOPC);
9666 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9667 ins_pipe(pipe_class_dummy);
9668 ins_short_branch(1);
9669 %}
9670
9671 // Compare against zero only, do not mix N and P oops (encode/decode required).
9672 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9673 match(If boolnode (CmpP (DecodeN src1) src2));
9674 effect(USE labl, KILL cr);
9675 predicate(VM_Version::has_CompareBranch());
9676 ins_cost(BRANCH_COST);
9677 // TODO: s390 port size(FIXED_SIZE);
9678 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9679 opcode(CLGIJ_ZOPC);
9680 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9681 ins_pipe(pipe_class_dummy);
9682 ins_short_branch(1);
9683 %}
9684
9685 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9686 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9687 effect(USE labl, KILL cr);
9688 predicate(VM_Version::has_CompareBranch());
9689 ins_cost(BRANCH_COST);
9690 // TODO: s390 port size(FIXED_SIZE);
9691 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9692 opcode(CLGIJ_ZOPC);
9693 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9694 ins_pipe(pipe_class_dummy);
9695 ins_short_branch(1);
9696 %}
9697
9698
9699 //----------Compare and Branch (far distance)------------------------------
9700
9701 // INT REG operands for loop counter processing
9702 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9703 match(CountedLoopEnd boolnode (CmpI src1 src2));
9704 effect(USE labl, KILL cr);
9705 predicate(VM_Version::has_CompareBranch());
9706 ins_cost(BRANCH_COST+DEFAULT_COST);
9707 // TODO: s390 port size(FIXED_SIZE);
9708 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9709 opcode(CR_ZOPC, BRCL_ZOPC);
9710 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9711 ins_pipe(pipe_class_dummy);
9712 ins_short_branch(0);
9713 %}
9714
9715 // INT REG operands
9716 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9717 match(If boolnode (CmpI src1 src2));
9718 effect(USE labl, KILL cr);
9719 predicate(VM_Version::has_CompareBranch());
9720 ins_cost(BRANCH_COST+DEFAULT_COST);
9721 // TODO: s390 port size(FIXED_SIZE);
9722 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9723 opcode(CR_ZOPC, BRCL_ZOPC);
9724 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9725 ins_pipe(pipe_class_dummy);
9726 ins_short_branch(0);
9727 %}
9728
9729 // INT REG operands
9730 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9731 match(If boolnode (CmpU src1 src2));
9732 effect(USE labl, KILL cr);
9733 predicate(VM_Version::has_CompareBranch());
9734 ins_cost(BRANCH_COST+DEFAULT_COST);
9735 // TODO: s390 port size(FIXED_SIZE);
9736 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9737 opcode(CLR_ZOPC, BRCL_ZOPC);
9738 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9739 ins_pipe(pipe_class_dummy);
9740 ins_short_branch(0);
9741 %}
9742
9743 // LONG REG operands
9744 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9745 match(If boolnode (CmpL src1 src2));
9746 effect(USE labl, KILL cr);
9747 predicate(VM_Version::has_CompareBranch());
9748 ins_cost(BRANCH_COST+DEFAULT_COST);
9749 // TODO: s390 port size(FIXED_SIZE);
9750 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9751 opcode(CGR_ZOPC, BRCL_ZOPC);
9752 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9753 ins_pipe(pipe_class_dummy);
9754 ins_short_branch(0);
9755 %}
9756
9757 // PTR REG operands
9758
9759 // Separate rules for regular and narrow oops. ADLC can't recognize
9760 // rules with polymorphic operands to be sisters -> shorten_branches
9761 // will not shorten.
9762
9763 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9764 match(If boolnode (CmpP src1 src2));
9765 effect(USE labl, KILL cr);
9766 predicate(VM_Version::has_CompareBranch());
9767 ins_cost(BRANCH_COST+DEFAULT_COST);
9768 // TODO: s390 port size(FIXED_SIZE);
9769 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9770 opcode(CLGR_ZOPC, BRCL_ZOPC);
9771 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9772 ins_pipe(pipe_class_dummy);
9773 ins_short_branch(0);
9774 %}
9775
9776 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9777 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9778 effect(USE labl, KILL cr);
9779 predicate(VM_Version::has_CompareBranch());
9780 ins_cost(BRANCH_COST+DEFAULT_COST);
9781 // TODO: s390 port size(FIXED_SIZE);
9782 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9783 opcode(CLGR_ZOPC, BRCL_ZOPC);
9784 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9785 ins_pipe(pipe_class_dummy);
9786 ins_short_branch(0);
9787 %}
9788
9789 // INT REG/IMM operands for loop counter processing
9790 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9791 match(CountedLoopEnd boolnode (CmpI src1 src2));
9792 effect(USE labl, KILL cr);
9793 predicate(VM_Version::has_CompareBranch());
9794 ins_cost(BRANCH_COST+DEFAULT_COST);
9795 // TODO: s390 port size(FIXED_SIZE);
9796 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9797 opcode(CHI_ZOPC, BRCL_ZOPC);
9798 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9799 ins_pipe(pipe_class_dummy);
9800 ins_short_branch(0);
9801 %}
9802
9803 // INT REG/IMM operands
9804 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9805 match(If boolnode (CmpI src1 src2));
9806 effect(USE labl, KILL cr);
9807 predicate(VM_Version::has_CompareBranch());
9808 ins_cost(BRANCH_COST+DEFAULT_COST);
9809 // TODO: s390 port size(FIXED_SIZE);
9810 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9811 opcode(CHI_ZOPC, BRCL_ZOPC);
9812 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9813 ins_pipe(pipe_class_dummy);
9814 ins_short_branch(0);
9815 %}
9816
9817 // INT REG/IMM operands
9818 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9819 match(If boolnode (CmpU src1 src2));
9820 effect(USE labl, KILL cr);
9821 predicate(VM_Version::has_CompareBranch());
9822 ins_cost(BRANCH_COST+DEFAULT_COST);
9823 // TODO: s390 port size(FIXED_SIZE);
9824 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9825 opcode(CLFI_ZOPC, BRCL_ZOPC);
9826 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9827 ins_pipe(pipe_class_dummy);
9828 ins_short_branch(0);
9829 %}
9830
9831 // LONG REG/IMM operands
9832 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9833 match(If boolnode (CmpL src1 src2));
9834 effect(USE labl, KILL cr);
9835 predicate(VM_Version::has_CompareBranch());
9836 ins_cost(BRANCH_COST+DEFAULT_COST);
9837 // TODO: s390 port size(FIXED_SIZE);
9838 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9839 opcode(CGHI_ZOPC, BRCL_ZOPC);
9840 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9841 ins_pipe(pipe_class_dummy);
9842 ins_short_branch(0);
9843 %}
9844
9845 // PTR REG-imm operands
9846
9847 // Separate rules for regular and narrow oops. ADLC can't recognize
9848 // rules with polymorphic operands to be sisters -> shorten_branches
9849 // will not shorten.
9850
9851 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9852 match(If boolnode (CmpP src1 src2));
9853 effect(USE labl, KILL cr);
9854 predicate(VM_Version::has_CompareBranch());
9855 ins_cost(BRANCH_COST+DEFAULT_COST);
9856 // TODO: s390 port size(FIXED_SIZE);
9857 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9858 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9859 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9860 ins_pipe(pipe_class_dummy);
9861 ins_short_branch(0);
9862 %}
9863
9864 // Compare against zero only, do not mix N and P oops (encode/decode required).
9865 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9866 match(If boolnode (CmpP (DecodeN src1) src2));
9867 effect(USE labl, KILL cr);
9868 predicate(VM_Version::has_CompareBranch());
9869 ins_cost(BRANCH_COST+DEFAULT_COST);
9870 // TODO: s390 port size(FIXED_SIZE);
9871 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9872 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9873 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9874 ins_pipe(pipe_class_dummy);
9875 ins_short_branch(0);
9876 %}
9877
9878 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9879 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9880 effect(USE labl, KILL cr);
9881 predicate(VM_Version::has_CompareBranch());
9882 ins_cost(BRANCH_COST+DEFAULT_COST);
9883 // TODO: s390 port size(FIXED_SIZE);
9884 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9885 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9886 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9887 ins_pipe(pipe_class_dummy);
9888 ins_short_branch(0);
9889 %}
9890
9891 // ============================================================================
9892 // Long Compare
9893
9894 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9895 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9896 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9897 // are collapsed internally in the ADLC's dfa-gen code. The match for
9898 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9899 // foo match ends up with the wrong leaf. One fix is to not match both
9900 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9901 // both forms beat the trinary form of long-compare and both are very useful
9902 // on platforms which have few registers.
9903
9904 // Manifest a CmpL3 result in an integer register. Very painful.
9905 // This is the test to avoid.
9906 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9907 match(Set dst (CmpL3 src1 src2));
9908 effect(KILL cr);
9909 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9910 size(24);
9911 format %{ "CmpL3 $dst,$src1,$src2" %}
9912 ins_encode %{
9913 Label done;
9914 // compare registers
9915 __ z_cgr($src1$$Register, $src2$$Register);
9916 // Convert condition code into -1,0,1, where
9917 // -1 means less
9918 // 0 means equal
9919 // 1 means greater.
9920 if (VM_Version::has_LoadStoreConditional()) {
9921 Register one = Z_R0_scratch;
9922 Register minus_one = Z_R1_scratch;
9923 __ z_lghi(minus_one, -1);
9924 __ z_lghi(one, 1);
9925 __ z_lghi( $dst$$Register, 0);
9926 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9927 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9928 } else {
9929 __ clear_reg($dst$$Register, true, false);
9930 __ z_bre(done);
9931 __ z_lhi($dst$$Register, 1);
9932 __ z_brh(done);
9933 __ z_lhi($dst$$Register, -1);
9934 }
9935 __ bind(done);
9936 %}
9937 ins_pipe(pipe_class_dummy);
9938 %}
9939
9940 // ============================================================================
9941 // Safepoint Instruction
9942
9943 instruct safePoint() %{
9944 match(SafePoint);
9945 predicate(false);
9946 // TODO: s390 port size(FIXED_SIZE);
9947 format %{ "UNIMPLEMENTED Safepoint_ " %}
9948 ins_encode(enc_unimplemented());
9949 ins_pipe(pipe_class_dummy);
9950 %}
9951
9952 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9953 match(SafePoint poll);
9954 effect(USE poll, KILL cr); // R0 is killed, too.
9955 // TODO: s390 port size(FIXED_SIZE);
9956 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9957 ins_encode %{
9958 // Mark the code position where the load from the safepoint
9959 // polling page was emitted as relocInfo::poll_type.
9960 __ relocate(relocInfo::poll_type);
9961 __ load_from_polling_page($poll$$Register);
9962 %}
9963 ins_pipe(pipe_class_dummy);
9964 %}
9965
9966 // ============================================================================
9967
9968 // Call Instructions
9969
9970 // Call Java Static Instruction
9971 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9972 match(CallStaticJava);
9973 effect(USE meth);
9974 ins_cost(CALL_COST);
9975 // TODO: s390 port size(VARIABLE_SIZE);
9976 format %{ "CALL,static dynTOC $meth; ==> " %}
9977 ins_encode( z_enc_java_static_call(meth) );
9978 ins_pipe(pipe_class_dummy);
9979 ins_alignment(2);
9980 %}
9981
9982 // Call Java Dynamic Instruction
9983 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9984 match(CallDynamicJava);
9985 effect(USE meth);
9986 ins_cost(CALL_COST);
9987 // TODO: s390 port size(VARIABLE_SIZE);
9988 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9989 ins_encode(z_enc_java_dynamic_call(meth));
9990 ins_pipe(pipe_class_dummy);
9991 ins_alignment(2);
9992 %}
9993
9994 // Call Runtime Instruction
9995 instruct CallRuntimeDirect(method meth) %{
9996 match(CallRuntime);
9997 effect(USE meth);
9998 ins_cost(CALL_COST);
9999 // TODO: s390 port size(VARIABLE_SIZE);
10000 ins_num_consts(1);
10001 ins_alignment(2);
10002 format %{ "CALL,runtime" %}
10003 ins_encode( z_enc_java_to_runtime_call(meth) );
10004 ins_pipe(pipe_class_dummy);
10005 %}
10006
10007 // Call runtime without safepoint - same as CallRuntime
10008 instruct CallLeafDirect(method meth) %{
10009 match(CallLeaf);
10010 effect(USE meth);
10011 ins_cost(CALL_COST);
10012 // TODO: s390 port size(VARIABLE_SIZE);
10013 ins_num_consts(1);
10014 ins_alignment(2);
10015 format %{ "CALL,runtime leaf $meth" %}
10016 ins_encode( z_enc_java_to_runtime_call(meth) );
10017 ins_pipe(pipe_class_dummy);
10018 %}
10019
10020 // Call runtime without safepoint - same as CallLeaf
10021 instruct CallLeafNoFPDirect(method meth) %{
10022 match(CallLeafNoFP);
10023 effect(USE meth);
10024 ins_cost(CALL_COST);
10025 // TODO: s390 port size(VARIABLE_SIZE);
10026 ins_num_consts(1);
10027 format %{ "CALL,runtime leaf nofp $meth" %}
10028 ins_encode( z_enc_java_to_runtime_call(meth) );
10029 ins_pipe(pipe_class_dummy);
10030 ins_alignment(2);
10031 %}
10032
10033 // Tail Call; Jump from runtime stub to Java code.
10034 // Also known as an 'interprocedural jump'.
10035 // Target of jump will eventually return to caller.
10036 // TailJump below removes the return address.
10037 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{
10038 match(TailCall jump_target method_ptr);
10039 ins_cost(CALL_COST);
10040 size(2);
10041 format %{ "Jmp $jump_target\t # $method_ptr holds method" %}
10042 ins_encode %{ __ z_br($jump_target$$Register); %}
10043 ins_pipe(pipe_class_dummy);
10044 %}
10045
10046 // Return Instruction
10047 instruct Ret() %{
10048 match(Return);
10049 size(2);
10050 format %{ "BR(Z_R14) // branch to link register" %}
10051 ins_encode %{ __ z_br(Z_R14); %}
10052 ins_pipe(pipe_class_dummy);
10053 %}
10054
10055 // Tail Jump; remove the return address; jump to target.
10056 // TailCall above leaves the return address around.
10057 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10058 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10059 // "restore" before this instruction (in Epilogue), we need to materialize it
10060 // in %i0.
10061 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
10062 match(TailJump jump_target ex_oop);
10063 ins_cost(CALL_COST);
10064 size(8);
10065 format %{ "TailJump $jump_target" %}
10066 ins_encode %{
10067 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
10068 __ z_br($jump_target$$Register);
10069 %}
10070 ins_pipe(pipe_class_dummy);
10071 %}
10072
10073 // Forward exception.
10074 instruct ForwardExceptionjmp() %{
10075 match(ForwardException);
10076 ins_cost(CALL_COST);
10077 format %{ "Jmp forward_exception_stub" %}
10078 ins_encode %{
10079 __ set_inst_mark();
10080 __ load_const_optimized(Z_R1_scratch, (address)StubRoutines::forward_exception_entry());
10081 __ z_br(Z_R1_scratch);
10082 __ clear_inst_mark();
10083 %}
10084 ins_pipe(pipe_class_dummy);
10085 %}
10086
10087 // Create exception oop: created by stack-crawling runtime code.
10088 // Created exception is now available to this handler, and is setup
10089 // just prior to jumping to this handler. No code emitted.
10090 instruct CreateException(rarg1RegP ex_oop) %{
10091 match(Set ex_oop (CreateEx));
10092 ins_cost(0);
10093 size(0);
10094 format %{ "# exception oop; no code emitted" %}
10095 ins_encode(/*empty*/);
10096 ins_pipe(pipe_class_dummy);
10097 %}
10098
10099 // Rethrow exception: The exception oop will come in the first
10100 // argument position. Then JUMP (not call) to the rethrow stub code.
10101 instruct RethrowException() %{
10102 match(Rethrow);
10103 ins_cost(CALL_COST);
10104 // TODO: s390 port size(VARIABLE_SIZE);
10105 format %{ "Jmp rethrow_stub" %}
10106 ins_encode %{
10107 __ set_inst_mark();
10108 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
10109 __ z_br(Z_R1_scratch);
10110 __ clear_inst_mark();
10111 %}
10112 ins_pipe(pipe_class_dummy);
10113 %}
10114
10115 // Die now.
10116 instruct ShouldNotReachHere() %{
10117 match(Halt);
10118 ins_cost(CALL_COST);
10119 format %{ "ILLTRAP; ShouldNotReachHere" %}
10120 ins_encode %{
10121 if (is_reachable()) {
10122 const char* str = __ code_string(_halt_reason);
10123 __ stop(str);
10124 }
10125 %}
10126 ins_pipe(pipe_class_dummy);
10127 %}
10128
10129 // ============================================================================
10130 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10131 // array for an instance of the superklass. Set a hidden internal cache on a
10132 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10133 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10134 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
10135 rarg4RegP scratch1, rarg5RegP scratch2) %{
10136 match(Set index (PartialSubtypeCheck sub super));
10137 predicate(!UseSecondarySupersTable);
10138 effect(KILL pcc, KILL scratch1, KILL scratch2);
10139 ins_cost(20 * DEFAULT_COST); // slightly larger than the next version
10140 // TODO: s390 port size(FIXED_SIZE);
10141 format %{ " CALL PartialSubtypeCheck\n" %}
10142 ins_encode %{
10143 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
10144 __ load_const_optimized(Z_ARG4, stub_address);
10145 __ z_basr(Z_R14, Z_ARG4);
10146 %}
10147 ins_pipe(pipe_class_dummy);
10148 %}
10149
10150 // Two versions of partialSubtypeCheck, both used when we need to
10151 // search for a super class in the secondary supers array. The first
10152 // is used when we don't know _a priori_ the class being searched
10153 // for. The second, far more common, is used when we do know: this is
10154 // used for instanceof, checkcast, and any case where C2 can determine
10155 // it by constant propagation.
10156 instruct partialSubtypeCheckVarSuper(rarg2RegP sub, rarg3RegP super,
10157 r11TempRegP result,
10158 rarg1RegP temp1, rarg4RegP temp2, rarg5RegP temp3, r10TempRegP temp4,
10159 flagsReg pcc) %{
10160 match(Set result (PartialSubtypeCheck sub super));
10161 predicate(UseSecondarySupersTable);
10162 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10163 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10164 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10165 ins_encode %{
10166 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register,
10167 $temp1$$Register, $temp2$$Register, $temp3$$Register, $temp4$$Register,
10168 $result$$Register);
10169 %}
10170 ins_pipe(pipe_class_dummy);
10171 %}
10172
10173
10174 instruct partialSubtypeCheckConstSuper(rarg2RegP sub, rarg1RegP super, immP super_con,
10175 r11TempRegP result, rarg5RegP temp1, rarg4RegP temp2,
10176 rarg3RegP temp3, r10TempRegP temp4, flagsReg pcc) %{
10177 match(Set result (PartialSubtypeCheck sub (Binary super super_con)));
10178 predicate(UseSecondarySupersTable);
10179 effect(KILL pcc, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
10180 ins_cost(5 * DEFAULT_COST); // smaller than the next version
10181 format %{ "partialSubtypeCheck $result, $sub, $super, $super_con" %}
10182
10183 ins_encode %{
10184 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10185 if (InlineSecondarySupersTest) {
10186 __ lookup_secondary_supers_table_const($sub$$Register, $super$$Register,
10187 $temp1$$Register, $temp2$$Register, $temp3$$Register,
10188 $temp4$$Register, $result$$Register, super_klass_slot);
10189 } else {
10190 AddressLiteral stub_address(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot));
10191 __ load_const_optimized(Z_ARG4, stub_address);
10192 __ z_basr(Z_R14, Z_ARG4);
10193 }
10194
10195 %}
10196
10197 ins_pipe(pipe_class_dummy);
10198 %}
10199
10200 // ============================================================================
10201 // inlined locking and unlocking
10202
10203 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10204 match(Set pcc (FastLock oop box));
10205 effect(TEMP tmp1, TEMP tmp2);
10206 ins_cost(100);
10207 // TODO: s390 port size(VARIABLE_SIZE);
10208 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10209 ins_encode %{
10210 __ fast_lock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10211 // If locking was successful, cc should indicate 'EQ'.
10212 // The compiler generates a branch to the runtime call to
10213 // _complete_monitor_locking_Java for the case where cc is 'NE'.
10214 %}
10215 ins_pipe(pipe_class_dummy);
10216 %}
10217
10218 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
10219 match(Set pcc (FastUnlock oop box));
10220 effect(TEMP tmp1, TEMP tmp2);
10221 ins_cost(100);
10222 // TODO: s390 port size(FIXED_SIZE);
10223 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
10224 ins_encode %{
10225 __ fast_unlock($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10226 // If unlocking was successful, cc should indicate 'EQ'.
10227 // The compiler generates a branch to the runtime call to
10228 // _complete_monitor_unlocking_Java for the case where cc is 'NE'.
10229 %}
10230 ins_pipe(pipe_class_dummy);
10231 %}
10232
10233 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
10234 match(Set dummy (ClearArray cnt base));
10235 effect(KILL cr);
10236 ins_cost(100);
10237 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
10238 format %{ "ClearArrayConst $cnt,$base" %}
10239 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
10240 ins_pipe(pipe_class_dummy);
10241 %}
10242
10243 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10244 match(Set dummy (ClearArray cnt base));
10245 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10246 ins_cost(200);
10247 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
10248 format %{ "ClearArrayConstBig $cnt,$base" %}
10249 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
10250 ins_pipe(pipe_class_dummy);
10251 %}
10252
10253 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
10254 match(Set dummy (ClearArray cnt base));
10255 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
10256 ins_cost(300);
10257 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
10258 format %{ "ClearArrayVar $cnt,$base" %}
10259 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
10260 ins_pipe(pipe_class_dummy);
10261 %}
10262
10263 // ============================================================================
10264 // CompactStrings
10265
10266 // String equals
10267 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10268 match(Set result (StrEquals (Binary str1 str2) cnt));
10269 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10270 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10271 ins_cost(300);
10272 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10273 ins_encode %{
10274 __ array_equals(false, $str1$$Register, $str2$$Register,
10275 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
10276 $result$$Register, true /* byte */);
10277 %}
10278 ins_pipe(pipe_class_dummy);
10279 %}
10280
10281 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
10282 match(Set result (StrEquals (Binary str1 str2) cnt));
10283 effect(KILL cr); // R0 is killed, too.
10284 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10285 ins_cost(100);
10286 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
10287 ins_encode %{
10288 const int cnt_imm = $cnt$$constant;
10289 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
10290 __ z_lhi($result$$Register, 1);
10291 if (cnt_imm) {
10292 if (VM_Version::has_LoadStoreConditional()) {
10293 __ z_lhi(Z_R0_scratch, 0);
10294 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10295 } else {
10296 Label Lskip;
10297 __ z_bre(Lskip);
10298 __ clear_reg($result$$Register);
10299 __ bind(Lskip);
10300 }
10301 }
10302 %}
10303 ins_pipe(pipe_class_dummy);
10304 %}
10305
10306 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
10307 match(Set result (StrEquals (Binary str1 str2) cnt));
10308 effect(KILL cr); // R0 is killed, too.
10309 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
10310 ins_cost(100);
10311 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10312 ins_encode %{
10313 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10314 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10315 __ z_lhi($result$$Register, 1);
10316 if (cnt_imm) {
10317 if (VM_Version::has_LoadStoreConditional()) {
10318 __ z_lhi(Z_R0_scratch, 0);
10319 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10320 } else {
10321 Label Lskip;
10322 __ z_bre(Lskip);
10323 __ clear_reg($result$$Register);
10324 __ bind(Lskip);
10325 }
10326 }
10327 %}
10328 ins_pipe(pipe_class_dummy);
10329 %}
10330
10331 // Array equals
10332 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10333 match(Set result (AryEq ary1 ary2));
10334 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10335 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10336 ins_cost(300);
10337 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10338 ins_encode %{
10339 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10340 noreg, $oddReg$$Register, $evenReg$$Register,
10341 $result$$Register, true /* byte */);
10342 %}
10343 ins_pipe(pipe_class_dummy);
10344 %}
10345
10346 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10347 match(Set result (AryEq ary1 ary2));
10348 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10349 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10350 ins_cost(300);
10351 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10352 ins_encode %{
10353 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10354 noreg, $oddReg$$Register, $evenReg$$Register,
10355 $result$$Register, false /* byte */);
10356 %}
10357 ins_pipe(pipe_class_dummy);
10358 %}
10359
10360 // String CompareTo
10361 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10362 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10363 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10364 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10365 ins_cost(300);
10366 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10367 ins_encode %{
10368 __ string_compare($str1$$Register, $str2$$Register,
10369 $cnt1$$Register, $cnt2$$Register,
10370 $oddReg$$Register, $evenReg$$Register,
10371 $result$$Register, StrIntrinsicNode::LL);
10372 %}
10373 ins_pipe(pipe_class_dummy);
10374 %}
10375
10376 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10377 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10378 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10379 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10380 ins_cost(300);
10381 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10382 ins_encode %{
10383 __ string_compare($str1$$Register, $str2$$Register,
10384 $cnt1$$Register, $cnt2$$Register,
10385 $oddReg$$Register, $evenReg$$Register,
10386 $result$$Register, StrIntrinsicNode::UU);
10387 %}
10388 ins_pipe(pipe_class_dummy);
10389 %}
10390
10391 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10392 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10393 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10394 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10395 ins_cost(300);
10396 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10397 ins_encode %{
10398 __ string_compare($str1$$Register, $str2$$Register,
10399 $cnt1$$Register, $cnt2$$Register,
10400 $oddReg$$Register, $evenReg$$Register,
10401 $result$$Register, StrIntrinsicNode::LU);
10402 %}
10403 ins_pipe(pipe_class_dummy);
10404 %}
10405
10406 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10407 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10408 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10409 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10410 ins_cost(300);
10411 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10412 ins_encode %{
10413 __ string_compare($str2$$Register, $str1$$Register,
10414 $cnt2$$Register, $cnt1$$Register,
10415 $oddReg$$Register, $evenReg$$Register,
10416 $result$$Register, StrIntrinsicNode::UL);
10417 %}
10418 ins_pipe(pipe_class_dummy);
10419 %}
10420
10421 // String IndexOfChar
10422 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10423 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10424 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10425 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
10426 ins_cost(200);
10427 format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10428 ins_encode %{
10429 __ string_indexof_char($result$$Register,
10430 $haystack$$Register, $haycnt$$Register,
10431 $ch$$Register, 0 /* unused, ch is in register */,
10432 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10433 %}
10434 ins_pipe(pipe_class_dummy);
10435 %}
10436
10437 instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10438 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10439 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10440 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
10441 ins_cost(200);
10442 format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10443 ins_encode %{
10444 __ string_indexof_char($result$$Register,
10445 $haystack$$Register, $haycnt$$Register,
10446 $ch$$Register, 0 /* unused, ch is in register */,
10447 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10448 %}
10449 ins_pipe(pipe_class_dummy);
10450 %}
10451
10452 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10453 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10454 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10455 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10456 ins_cost(200);
10457 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10458 ins_encode %{
10459 immPOper *needleOper = (immPOper *)$needle;
10460 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10461 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10462 jchar chr;
10463 #ifdef VM_LITTLE_ENDIAN
10464 Unimplemented();
10465 #else
10466 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10467 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10468 #endif
10469 __ string_indexof_char($result$$Register,
10470 $haystack$$Register, $haycnt$$Register,
10471 noreg, chr,
10472 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10473 %}
10474 ins_pipe(pipe_class_dummy);
10475 %}
10476
10477 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10478 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10479 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10480 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10481 ins_cost(200);
10482 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10483 ins_encode %{
10484 immPOper *needleOper = (immPOper *)$needle;
10485 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10486 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10487 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10488 __ string_indexof_char($result$$Register,
10489 $haystack$$Register, $haycnt$$Register,
10490 noreg, chr,
10491 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10492 %}
10493 ins_pipe(pipe_class_dummy);
10494 %}
10495
10496 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10497 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10498 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10499 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10500 ins_cost(200);
10501 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10502 ins_encode %{
10503 immPOper *needleOper = (immPOper *)$needle;
10504 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10505 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10506 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10507 __ string_indexof_char($result$$Register,
10508 $haystack$$Register, $haycnt$$Register,
10509 noreg, chr,
10510 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10511 %}
10512 ins_pipe(pipe_class_dummy);
10513 %}
10514
10515 // String IndexOf
10516 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10517 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10518 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10519 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10520 ins_cost(250);
10521 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10522 ins_encode %{
10523 __ string_indexof($result$$Register,
10524 $haystack$$Register, $haycnt$$Register,
10525 $needle$$Register, noreg, $needlecntImm$$constant,
10526 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10527 %}
10528 ins_pipe(pipe_class_dummy);
10529 %}
10530
10531 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10532 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10533 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10534 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10535 ins_cost(250);
10536 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10537 ins_encode %{
10538 __ string_indexof($result$$Register,
10539 $haystack$$Register, $haycnt$$Register,
10540 $needle$$Register, noreg, $needlecntImm$$constant,
10541 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10542 %}
10543 ins_pipe(pipe_class_dummy);
10544 %}
10545
10546 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10547 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10548 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10549 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10550 ins_cost(250);
10551 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10552 ins_encode %{
10553 __ string_indexof($result$$Register,
10554 $haystack$$Register, $haycnt$$Register,
10555 $needle$$Register, noreg, $needlecntImm$$constant,
10556 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10557 %}
10558 ins_pipe(pipe_class_dummy);
10559 %}
10560
10561 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10562 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10563 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10564 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10565 ins_cost(300);
10566 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10567 ins_encode %{
10568 __ string_indexof($result$$Register,
10569 $haystack$$Register, $haycnt$$Register,
10570 $needle$$Register, $needlecnt$$Register, 0,
10571 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10572 %}
10573 ins_pipe(pipe_class_dummy);
10574 %}
10575
10576 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10577 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10578 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10579 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10580 ins_cost(300);
10581 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10582 ins_encode %{
10583 __ string_indexof($result$$Register,
10584 $haystack$$Register, $haycnt$$Register,
10585 $needle$$Register, $needlecnt$$Register, 0,
10586 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10587 %}
10588 ins_pipe(pipe_class_dummy);
10589 %}
10590
10591 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10592 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10593 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10594 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10595 ins_cost(300);
10596 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10597 ins_encode %{
10598 __ string_indexof($result$$Register,
10599 $haystack$$Register, $haycnt$$Register,
10600 $needle$$Register, $needlecnt$$Register, 0,
10601 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10602 %}
10603 ins_pipe(pipe_class_dummy);
10604 %}
10605
10606 // char[] to byte[] compression
10607 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18,
10608 v19TempReg v19, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10609 match(Set result (StrCompressedCopy src (Binary dst len)));
10610 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19, TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10611 ins_cost(300);
10612 format %{ "String Compress $src->$dst($len) -> $result" %}
10613 ins_encode %{
10614 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10615 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10616 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10617 $v23$$VectorRegister);
10618 %}
10619 ins_pipe(pipe_class_dummy);
10620 %}
10621
10622 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10623 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10624 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10625 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10626 // predicate(VM_Version::has_ETF2Enhancements());
10627 // ins_cost(300);
10628 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10629 // ins_encode %{
10630 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10631 // %}
10632 // ins_pipe(pipe_class_dummy);
10633 //%}
10634
10635 // byte[] to char[] inflation
10636 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10637 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10638 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10639 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10640 ins_cost(300);
10641 format %{ "String Inflate $src->$dst($len)" %}
10642 ins_encode %{
10643 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, $v20$$VectorRegister,
10644 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10645 $v25$$VectorRegister);
10646 %}
10647 ins_pipe(pipe_class_dummy);
10648 %}
10649
10650 // byte[] to char[] inflation
10651 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, v20TempReg v20, v21TempReg v21, v22TempReg v22, v23TempReg v23,
10652 v24TempReg v24, v25TempReg v25, flagsReg cr) %{
10653 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10654 effect(TEMP tmp, TEMP v20, TEMP v21, TEMP v22, TEMP v23, TEMP v24, TEMP v25, KILL cr); // R0, R1 are killed, too.
10655 ins_cost(300);
10656 format %{ "String Inflate (constLen) $src->$dst($len)" %}
10657 ins_encode %{
10658 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant , $v20$$VectorRegister,
10659 $v21$$VectorRegister, $v22$$VectorRegister, $v23$$VectorRegister, $v24$$VectorRegister,
10660 $v25$$VectorRegister);
10661 %}
10662 ins_pipe(pipe_class_dummy);
10663 %}
10664
10665 // StringCoding.java intrinsics
10666 instruct count_positives(iRegP ary1, iRegI len, iRegI result, iRegI tmp, flagsReg cr) %{
10667 match(Set result (CountPositives ary1 len));
10668 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10669 ins_cost(300);
10670 format %{ "count positives byte[] $ary1($len) -> $result" %}
10671 ins_encode %{
10672 __ count_positives($result$$Register, $ary1$$Register, $len$$Register, $tmp$$Register);
10673 %}
10674 ins_pipe(pipe_class_dummy);
10675 %}
10676
10677 // encode char[] to byte[] in ISO_8859_1
10678 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10679 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10680 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
10681 match(Set result (EncodeISOArray src (Binary dst len)));
10682 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10683 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10684 ins_cost(300);
10685 format %{ "Encode iso array $src->$dst($len) -> $result" %}
10686 ins_encode %{
10687 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10688 $tmp$$Register, true, false, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10689 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10690 $v23$$VectorRegister);
10691 %}
10692 ins_pipe(pipe_class_dummy);
10693 %}
10694
10695 // encode char[] to byte[] in ASCII
10696 instruct encode_ascii_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, v16TempReg v16, v17TempReg v17, v18TempReg v18, v19TempReg v19, v20TempReg v20, v21TempReg v21,
10697 v22TempReg v22, v23TempReg v23, flagsReg cr) %{
10698 predicate(((EncodeISOArrayNode*)n)->is_ascii());
10699 match(Set result (EncodeISOArray src (Binary dst len)));
10700 effect(TEMP_DEF result, TEMP tmp, TEMP v16, TEMP v17, TEMP v18, TEMP v19,
10701 TEMP v20, TEMP v21, TEMP v22, TEMP v23, KILL cr); // R0, R1 are killed, too.
10702 ins_cost(300);
10703 format %{ "Encode ascii array $src->$dst($len) -> $result" %}
10704 ins_encode %{
10705 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10706 $tmp$$Register, true, true, $v16$$VectorRegister, $v17$$VectorRegister, $v18$$VectorRegister,
10707 $v19$$VectorRegister, $v20$$VectorRegister, $v21$$VectorRegister, $v22$$VectorRegister,
10708 $v23$$VectorRegister);
10709 %}
10710 ins_pipe(pipe_class_dummy);
10711 %}
10712
10713
10714 //----------PEEPHOLE RULES-----------------------------------------------------
10715 // These must follow all instruction definitions as they use the names
10716 // defined in the instructions definitions.
10717 //
10718 // peepmatch (root_instr_name [preceeding_instruction]*);
10719 //
10720 // peepconstraint %{
10721 // (instruction_number.operand_name relational_op instruction_number.operand_name
10722 // [, ...]);
10723 // // instruction numbers are zero-based using left to right order in peepmatch
10724 //
10725 // peepreplace (instr_name([instruction_number.operand_name]*));
10726 // // provide an instruction_number.operand_name for each operand that appears
10727 // // in the replacement instruction's match rule
10728 //
10729 // ---------VM FLAGS---------------------------------------------------------
10730 //
10731 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10732 //
10733 // Each peephole rule is given an identifying number starting with zero and
10734 // increasing by one in the order seen by the parser. An individual peephole
10735 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10736 // on the command-line.
10737 //
10738 // ---------CURRENT LIMITATIONS----------------------------------------------
10739 //
10740 // Only match adjacent instructions in same basic block
10741 // Only equality constraints
10742 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10743 // Only one replacement instruction
10744 //
10745 // ---------EXAMPLE----------------------------------------------------------
10746 //
10747 // // pertinent parts of existing instructions in architecture description
10748 // instruct movI(eRegI dst, eRegI src) %{
10749 // match(Set dst (CopyI src));
10750 // %}
10751 //
10752 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10753 // match(Set dst (AddI dst src));
10754 // effect(KILL cr);
10755 // %}
10756 //
10757 // // Change (inc mov) to lea
10758 // peephole %{
10759 // // increment preceded by register-register move
10760 // peepmatch (incI_eReg movI);
10761 // // require that the destination register of the increment
10762 // // match the destination register of the move
10763 // peepconstraint (0.dst == 1.dst);
10764 // // construct a replacement instruction that sets
10765 // // the destination to (move's source register + one)
10766 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10767 // %}
10768 //
10769 // Implementation no longer uses movX instructions since
10770 // machine-independent system no longer uses CopyX nodes.
10771 //
10772 // peephole %{
10773 // peepmatch (incI_eReg movI);
10774 // peepconstraint (0.dst == 1.dst);
10775 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10776 // %}
10777 //
10778 // peephole %{
10779 // peepmatch (decI_eReg movI);
10780 // peepconstraint (0.dst == 1.dst);
10781 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10782 // %}
10783 //
10784 // peephole %{
10785 // peepmatch (addI_eReg_imm movI);
10786 // peepconstraint (0.dst == 1.dst);
10787 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10788 // %}
10789 //
10790 // peephole %{
10791 // peepmatch (addP_eReg_imm movP);
10792 // peepconstraint (0.dst == 1.dst);
10793 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10794 // %}
10795
10796
10797 // This peephole rule does not work, probably because ADLC can't handle two effects:
10798 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10799 // condense a load from memory and subsequent test for zero
10800 // into a single, more efficient ICM instruction.
10801 // peephole %{
10802 // peepmatch (compI_iReg_imm0 loadI);
10803 // peepconstraint (1.dst == 0.op1);
10804 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10805 // %}
10806
10807 // // Change load of spilled value to only a spill
10808 // instruct storeI(memory mem, eRegI src) %{
10809 // match(Set mem (StoreI mem src));
10810 // %}
10811 //
10812 // instruct loadI(eRegI dst, memory mem) %{
10813 // match(Set dst (LoadI mem));
10814 // %}
10815 //
10816 peephole %{
10817 peepmatch (loadI storeI);
10818 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10819 peepreplace (storeI(1.mem 1.mem 1.src));
10820 %}
10821
10822 peephole %{
10823 peepmatch (loadL storeL);
10824 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10825 peepreplace (storeL(1.mem 1.mem 1.src));
10826 %}
10827
10828 peephole %{
10829 peepmatch (loadP storeP);
10830 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10831 peepreplace (storeP(1.dst 1.dst 1.src));
10832 %}
10833
10834 //----------SUPERWORD RULES---------------------------------------------------
10835
10836 // Expand rules for special cases
10837
10838 instruct expand_storeF(stackSlotF mem, regF src) %{
10839 // No match rule, false predicate, for expand only.
10840 effect(DEF mem, USE src);
10841 predicate(false);
10842 ins_cost(MEMORY_REF_COST);
10843 // TODO: s390 port size(FIXED_SIZE);
10844 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10845 opcode(STE_ZOPC, STE_ZOPC);
10846 ins_encode(z_form_rt_mem(src, mem));
10847 ins_pipe(pipe_class_dummy);
10848 %}
10849
10850 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10851 // No match rule, false predicate, for expand only.
10852 effect(DEF dst, USE mem);
10853 predicate(false);
10854 ins_cost(MEMORY_REF_COST);
10855 // TODO: s390 port size(FIXED_SIZE);
10856 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10857 opcode(LLGF_ZOPC, LLGF_ZOPC);
10858 ins_encode(z_form_rt_mem(dst, mem));
10859 ins_pipe(pipe_class_dummy);
10860 %}
10861
10862 // Replicate scalar int to packed int values (8 Bytes)
10863 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10864 // Dummy match rule, false predicate, for expand only.
10865 match(Set dst (ConvI2L src));
10866 predicate(false);
10867 ins_cost(DEFAULT_COST);
10868 // TODO: s390 port size(FIXED_SIZE);
10869 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10870 ins_encode %{
10871 if ($dst$$Register == $src$$Register) {
10872 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10873 __ z_ogr($dst$$Register, Z_R0_scratch);
10874 } else {
10875 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10876 __ z_ogr( $dst$$Register, $src$$Register);
10877 }
10878 %}
10879 ins_pipe(pipe_class_dummy);
10880 %}
10881
10882 // Replication
10883
10884 // Exploit rotate_then_insert, if available
10885 // Replicate scalar byte to packed byte values (8 Bytes).
10886 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10887 match(Set dst (Replicate src));
10888 effect(KILL cr);
10889 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10890 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10891 ins_encode %{
10892 if ($dst$$Register != $src$$Register) {
10893 __ z_lgr($dst$$Register, $src$$Register);
10894 }
10895 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10896 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10897 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10898 %}
10899 ins_pipe(pipe_class_dummy);
10900 %}
10901
10902 // Replicate scalar byte to packed byte values (8 Bytes).
10903 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10904 match(Set dst (Replicate src));
10905 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10906 ins_should_rematerialize(true);
10907 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10908 ins_encode %{
10909 int64_t Isrc8 = $src$$constant & 0x000000ff;
10910 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10911 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10912 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10913
10914 __ z_llilf($dst$$Register, Isrc32);
10915 __ z_iihf($dst$$Register, Isrc32);
10916 %}
10917 ins_pipe(pipe_class_dummy);
10918 %}
10919
10920 // Replicate scalar byte to packed byte values (8 Bytes).
10921 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10922 match(Set dst (Replicate src));
10923 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10924 ins_should_rematerialize(true);
10925 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10926 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10927 ins_pipe(pipe_class_dummy);
10928 %}
10929
10930 // Replicate scalar byte to packed byte values (8 Bytes).
10931 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10932 match(Set dst (Replicate src));
10933 predicate(n->as_Vector()->length() == 8 && Matcher::vector_element_basic_type(n) == T_BYTE);
10934 ins_should_rematerialize(true);
10935 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10936 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10937 ins_pipe(pipe_class_dummy);
10938 %}
10939
10940 // Exploit rotate_then_insert, if available
10941 // Replicate scalar short to packed short values (8 Bytes).
10942 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10943 match(Set dst (Replicate src));
10944 effect(KILL cr);
10945 predicate((n->as_Vector()->length() == 4) && Matcher::vector_element_basic_type(n) == T_SHORT);
10946 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10947 ins_encode %{
10948 if ($dst$$Register != $src$$Register) {
10949 __ z_lgr($dst$$Register, $src$$Register);
10950 }
10951 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10952 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10953 %}
10954 ins_pipe(pipe_class_dummy);
10955 %}
10956
10957 // Replicate scalar short to packed short values (8 Bytes).
10958 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10959 match(Set dst (Replicate src));
10960 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10961 ins_should_rematerialize(true);
10962 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10963 ins_encode %{
10964 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10965 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10966 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10967 ") should be handled by other match rules.", $src$$constant);
10968
10969 __ z_llilf($dst$$Register, Isrc32);
10970 __ z_iihf($dst$$Register, Isrc32);
10971 %}
10972 ins_pipe(pipe_class_dummy);
10973 %}
10974
10975 // Replicate scalar short to packed short values (8 Bytes).
10976 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10977 match(Set dst (Replicate src));
10978 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10979 ins_should_rematerialize(true);
10980 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10981 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10982 ins_pipe(pipe_class_dummy);
10983 %}
10984
10985 // Replicate scalar short to packed short values (8 Bytes).
10986 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10987 match(Set dst (Replicate src));
10988 predicate(n->as_Vector()->length() == 4 && Matcher::vector_element_basic_type(n) == T_SHORT);
10989 ins_should_rematerialize(true);
10990 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10991 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10992 ins_pipe(pipe_class_dummy);
10993 %}
10994
10995 instruct repl8S_reg_Ex(vecX dst, iRegI src) %{
10996 match(Set dst (Replicate src));
10997 predicate(n->as_Vector()->length() == 8 &&
10998 Matcher::vector_element_basic_type(n) == T_SHORT);
10999
11000 size(12);
11001 ins_encode %{
11002 __ z_vlvgh($dst$$VectorRegister, $src$$Register, 0);
11003 __ z_vreph($dst$$VectorRegister, $dst$$VectorRegister, 0);
11004 %}
11005 ins_pipe(pipe_class_dummy);
11006 %}
11007
11008 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
11009 match(Set dst (Replicate src));
11010 predicate(n->as_Vector()->length() == 8 &&
11011 Matcher::vector_element_basic_type(n) == T_SHORT);
11012
11013 format %{ "VONE $dst, $src \t// replicate8S" %}
11014 size(6);
11015 ins_encode %{
11016 __ z_vone($dst$$VectorRegister);
11017 %}
11018 ins_pipe(pipe_class_dummy);
11019 %}
11020
11021 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
11022 match(Set dst (Replicate zero));
11023 predicate(n->as_Vector()->length() == 8 &&
11024 Matcher::vector_element_basic_type(n) == T_SHORT);
11025
11026 format %{ "VZERO $dst, $zero \t// replicate8S" %}
11027 size(6);
11028 ins_encode %{
11029 __ z_vzero($dst$$VectorRegister);
11030 %}
11031 ins_pipe(pipe_class_dummy);
11032 %}
11033
11034 // Exploit rotate_then_insert, if available.
11035 // Replicate scalar int to packed int values (8 Bytes).
11036 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
11037 match(Set dst (Replicate src));
11038 effect(KILL cr);
11039 predicate((n->as_Vector()->length() == 2) && Matcher::vector_element_basic_type(n) == T_INT);
11040 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
11041 ins_encode %{
11042 if ($dst$$Register != $src$$Register) {
11043 __ z_lgr($dst$$Register, $src$$Register);
11044 }
11045 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
11046 %}
11047 ins_pipe(pipe_class_dummy);
11048 %}
11049
11050 // Replicate scalar int to packed int values (8 Bytes).
11051 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
11052 match(Set dst (Replicate src));
11053 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11054 ins_should_rematerialize(true);
11055 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
11056 ins_encode %{
11057 int64_t Isrc32 = $src$$constant;
11058 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
11059
11060 __ z_llilf($dst$$Register, Isrc32);
11061 __ z_iihf($dst$$Register, Isrc32);
11062 %}
11063 ins_pipe(pipe_class_dummy);
11064 %}
11065
11066 // Replicate scalar int to packed int values (8 Bytes).
11067 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
11068 match(Set dst (Replicate src));
11069 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11070 ins_should_rematerialize(true);
11071 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
11072 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11073 ins_pipe(pipe_class_dummy);
11074 %}
11075
11076 // Replicate scalar int to packed int values (8 Bytes).
11077 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
11078 match(Set dst (Replicate src));
11079 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_INT);
11080 ins_should_rematerialize(true);
11081 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
11082 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
11083 ins_pipe(pipe_class_dummy);
11084 %}
11085
11086 instruct repl4I_reg_Ex(vecX dst, iRegI src) %{
11087 match(Set dst (Replicate src));
11088 predicate(n->as_Vector()->length() == 4 &&
11089 Matcher::vector_element_basic_type(n) == T_INT);
11090
11091 size(12);
11092 ins_encode %{
11093 __ z_vlvgf($dst$$VectorRegister, $src$$Register, 0);
11094 __ z_vrepf($dst$$VectorRegister, $dst$$VectorRegister, 0);
11095 %}
11096 ins_pipe(pipe_class_dummy);
11097 %}
11098
11099 instruct repl4I_immI0(vecX dst, immI_0 zero) %{
11100 match(Set dst (Replicate zero));
11101 predicate(n->as_Vector()->length() == 4 &&
11102 Matcher::vector_element_basic_type(n) == T_INT);
11103
11104 format %{ "VZERO $dst, $zero \t// replicate4I" %}
11105 size(6);
11106 ins_encode %{
11107 __ z_vzero($dst$$VectorRegister);
11108 %}
11109 ins_pipe(pipe_class_dummy);
11110 %}
11111
11112 instruct repl4I_immIminus1(vecX dst, immI_minus1 src) %{
11113 match(Set dst (Replicate src));
11114 predicate(n->as_Vector()->length() == 4 &&
11115 Matcher::vector_element_basic_type(n) == T_INT);
11116
11117 format %{ "VONE $dst, $dst, $dst \t// replicate4I" %}
11118 size(6);
11119 ins_encode %{
11120 __ z_vone($dst$$VectorRegister);
11121 %}
11122 ins_pipe(pipe_class_dummy);
11123 %}
11124
11125 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
11126 match(Set dst (Replicate src));
11127 effect(KILL cr);
11128 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11129 Matcher::vector_element_basic_type(n) == T_FLOAT);
11130 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
11131 expand %{
11132 stackSlotF tmp;
11133 iRegL tmp2;
11134 expand_storeF(tmp, src);
11135 expand_LoadLogical_I2L(tmp2, tmp);
11136 expand_Repl2I_reg(dst, tmp2);
11137 %}
11138 %}
11139
11140 // Replicate scalar float to packed float values in GREG (8 Bytes).
11141 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
11142 match(Set dst (Replicate src));
11143 effect(KILL cr);
11144 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2 &&
11145 Matcher::vector_element_basic_type(n) == T_FLOAT);
11146 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
11147 ins_encode %{
11148 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
11149 __ z_lgdr($dst$$Register, $src$$FloatRegister);
11150
11151 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
11152 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
11153 __ z_ogr($dst$$Register, Z_R0_scratch);
11154 %}
11155 ins_pipe(pipe_class_dummy);
11156 %}
11157
11158 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
11159 instruct Repl2F_imm(iRegL dst, immF src) %{
11160 match(Set dst (Replicate src));
11161 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11162 ins_should_rematerialize(true);
11163 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
11164 ins_encode %{
11165 union {
11166 int Isrc32;
11167 float Fsrc32;
11168 };
11169 Fsrc32 = $src$$constant;
11170 __ z_llilf($dst$$Register, Isrc32);
11171 __ z_iihf($dst$$Register, Isrc32);
11172 %}
11173 ins_pipe(pipe_class_dummy);
11174 %}
11175
11176 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
11177 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
11178 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
11179 match(Set dst (Replicate src));
11180 predicate(n->as_Vector()->length() == 2 && Matcher::vector_element_basic_type(n) == T_FLOAT);
11181 ins_should_rematerialize(true);
11182 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
11183 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
11184 ins_pipe(pipe_class_dummy);
11185 %}
11186
11187 instruct repl4F_reg_Ex(vecX dst, regF src) %{
11188 match(Set dst (Replicate src));
11189 predicate(n->as_Vector()->length() == 4 &&
11190 Matcher::vector_element_basic_type(n) == T_FLOAT);
11191
11192 format %{ "VREP $dst, $src \t// replicate4F" %}
11193 size(6);
11194
11195 ins_encode %{
11196 __ z_vrepf($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11197 %}
11198 ins_pipe(pipe_class_dummy);
11199 %}
11200
11201 instruct repl4F_immF0(vecX dst, immFp0 zero) %{
11202 match(Set dst (Replicate zero));
11203 predicate(n->as_Vector()->length() == 4 &&
11204 Matcher::vector_element_basic_type(n) == T_FLOAT);
11205
11206 format %{ "VZERO $dst, $zero \t// replicate4F" %}
11207 size(6);
11208 ins_encode %{
11209 __ z_vzero($dst$$VectorRegister);
11210 %}
11211 ins_pipe(pipe_class_dummy);
11212 %}
11213
11214 instruct repl2D_reg_Ex(vecX dst, regD src) %{
11215 match(Set dst (Replicate src));
11216 predicate(n->as_Vector()->length() == 2 &&
11217 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11218
11219 format %{ "VREP $dst, $src \t// replicate2D" %}
11220 size(6);
11221
11222 ins_encode %{
11223 __ z_vrepg($dst$$VectorRegister, $src$$FloatRegister->to_vr(), 0);
11224 %}
11225 ins_pipe(pipe_class_dummy);
11226 %}
11227
11228 instruct repl2D_immD0(vecX dst, immDp0 zero) %{
11229 match(Set dst (Replicate zero));
11230 predicate(n->as_Vector()->length() == 2 &&
11231 Matcher::vector_element_basic_type(n) == T_DOUBLE);
11232
11233 format %{ "VZERO $dst, $zero \t// replicate2D" %}
11234 size(6);
11235 ins_encode %{
11236 __ z_vzero($dst$$VectorRegister);
11237 %}
11238 ins_pipe(pipe_class_dummy);
11239 %}
11240
11241 instruct repl16B_reg_Ex(vecX dst, iRegI src) %{
11242 match(Set dst (Replicate src));
11243 predicate(n->as_Vector()->length() == 16 &&
11244 Matcher::vector_element_basic_type(n) == T_BYTE);
11245
11246 size(12);
11247 ins_encode %{
11248 __ z_vlvgb($dst$$VectorRegister, $src$$Register, 0);
11249 __ z_vrepb($dst$$VectorRegister, $dst$$VectorRegister, 0);
11250 %}
11251 ins_pipe(pipe_class_dummy);
11252 %}
11253
11254 instruct repl16B_immIminus1(vecX dst, immI_minus1 src) %{
11255 match(Set dst (Replicate src));
11256 predicate(n->as_Vector()->length() == 16 &&
11257 Matcher::vector_element_basic_type(n) == T_BYTE);
11258
11259 format %{ "VONE $dst, $src \t// replicate16B" %}
11260 size(6);
11261 ins_encode %{
11262 __ z_vone($dst$$VectorRegister);
11263 %}
11264 ins_pipe(pipe_class_dummy);
11265 %}
11266
11267 instruct repl16B_immI0(vecX dst, immI_0 zero) %{
11268 match(Set dst (Replicate zero));
11269 predicate(n->as_Vector()->length() == 16 &&
11270 Matcher::vector_element_basic_type(n) == T_BYTE);
11271
11272 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11273 size(6);
11274 ins_encode %{
11275 __ z_vzero($dst$$VectorRegister);
11276 %}
11277 ins_pipe(pipe_class_dummy);
11278 %}
11279
11280 instruct repl2L_reg_Ex(vecX dst, iRegL src) %{
11281 match(Set dst (Replicate src));
11282 predicate(n->as_Vector()->length() == 2 &&
11283 Matcher::vector_element_basic_type(n) == T_LONG);
11284
11285 size(12);
11286 ins_encode %{
11287 __ z_vlvgg($dst$$VectorRegister, $src$$Register, 0);
11288 __ z_vrepg($dst$$VectorRegister, $dst$$VectorRegister, 0);
11289 %}
11290 ins_pipe(pipe_class_dummy);
11291 %}
11292
11293 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
11294 match(Set dst (Replicate src));
11295 predicate(n->as_Vector()->length() == 2 &&
11296 Matcher::vector_element_basic_type(n) == T_LONG);
11297
11298 format %{ "VONE $dst, $src \t// replicate2L" %}
11299 size(6);
11300 ins_encode %{
11301 __ z_vone($dst$$VectorRegister);
11302 %}
11303 ins_pipe(pipe_class_dummy);
11304 %}
11305
11306 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
11307 match(Set dst (Replicate zero));
11308 predicate(n->as_Vector()->length() == 2 &&
11309 Matcher::vector_element_basic_type(n) == T_LONG);
11310
11311 format %{ "VZERO $dst, $zero \t// replicate16B" %}
11312 size(6);
11313 ins_encode %{
11314 __ z_vzero($dst$$VectorRegister);
11315 %}
11316 ins_pipe(pipe_class_dummy);
11317 %}
11318
11319
11320 // Load/Store vector
11321
11322 // Store Aligned Packed Byte register to memory (8 Bytes).
11323 instruct storeA8B(memory mem, iRegL src) %{
11324 match(Set mem (StoreVector mem src));
11325 predicate(n->as_StoreVector()->memory_size() == 8);
11326 ins_cost(MEMORY_REF_COST);
11327 // TODO: s390 port size(VARIABLE_SIZE);
11328 format %{ "STG $src,$mem\t # ST(packed8B)" %}
11329 opcode(STG_ZOPC, STG_ZOPC);
11330 ins_encode(z_form_rt_mem_opt(src, mem));
11331 ins_pipe(pipe_class_dummy);
11332 %}
11333
11334 // Store Packed Byte long register to memory
11335 instruct storeV16(memoryRX mem, vecX src) %{
11336 predicate(n->as_StoreVector()->memory_size() == 16);
11337 match(Set mem (StoreVector mem src));
11338 ins_cost(MEMORY_REF_COST);
11339
11340 format %{ "VST $mem, $src \t// store 16-byte Vector" %}
11341 size(6);
11342 ins_encode %{
11343 __ z_vst($src$$VectorRegister,
11344 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11345 %}
11346 ins_pipe(pipe_class_dummy);
11347 %}
11348
11349 instruct loadV8(iRegL dst, memory mem) %{
11350 match(Set dst (LoadVector mem));
11351 predicate(n->as_LoadVector()->memory_size() == 8);
11352 ins_cost(MEMORY_REF_COST);
11353 // TODO: s390 port size(VARIABLE_SIZE);
11354 format %{ "LG $dst,$mem\t # L(packed8B)" %}
11355 opcode(LG_ZOPC, LG_ZOPC);
11356 ins_encode(z_form_rt_mem_opt(dst, mem));
11357 ins_pipe(pipe_class_dummy);
11358 %}
11359
11360 // Load Aligned Packed Byte
11361 instruct loadV16(vecX dst, memoryRX mem) %{
11362 predicate(n->as_LoadVector()->memory_size() == 16);
11363 match(Set dst (LoadVector mem));
11364 ins_cost(MEMORY_REF_COST);
11365
11366 format %{ "VL $dst, $mem \t// load 16-byte Vector" %}
11367 size(6);
11368 ins_encode %{
11369 __ z_vl($dst$$VectorRegister,
11370 Address(reg_to_register_object($mem$$base), $mem$$index$$Register, $mem$$disp));
11371 %}
11372 ins_pipe(pipe_class_dummy);
11373 %}
11374
11375 // Reinterpret: only one vector size used
11376 instruct reinterpret(iRegL dst) %{
11377 match(Set dst (VectorReinterpret dst));
11378 ins_cost(0);
11379 format %{ "reinterpret $dst" %}
11380 ins_encode( /*empty*/ );
11381 ins_pipe(pipe_class_dummy);
11382 %}
11383
11384 instruct reinterpretX(vecX dst) %{
11385 match(Set dst (VectorReinterpret dst));
11386 ins_cost(0);
11387 format %{ "reinterpret $dst" %}
11388 ins_encode( /*empty*/ );
11389 ins_pipe(pipe_class_dummy);
11390 %}
11391
11392 //----------Vector Arithmetic Instructions--------------------------------------
11393
11394 // Vector Addition Instructions
11395
11396 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
11397 match(Set dst (AddVB src1 src2));
11398 predicate(n->as_Vector()->length() == 16);
11399 format %{ "VAB $dst,$src1,$src2\t// add packed16B" %}
11400 size(6);
11401 ins_encode %{
11402 __ z_vab($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11403 %}
11404 ins_pipe(pipe_class_dummy);
11405 %}
11406
11407 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
11408 match(Set dst (AddVS src1 src2));
11409 predicate(n->as_Vector()->length() == 8);
11410 format %{ "VAH $dst,$src1,$src2\t// add packed8S" %}
11411 size(6);
11412 ins_encode %{
11413 __ z_vah($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11414 %}
11415 ins_pipe(pipe_class_dummy);
11416 %}
11417
11418 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
11419 match(Set dst (AddVI src1 src2));
11420 predicate(n->as_Vector()->length() == 4);
11421 format %{ "VAF $dst,$src1,$src2\t// add packed4I" %}
11422 size(6);
11423 ins_encode %{
11424 __ z_vaf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11425 %}
11426 ins_pipe(pipe_class_dummy);
11427 %}
11428
11429 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
11430 match(Set dst (AddVL src1 src2));
11431 predicate(n->as_Vector()->length() == 2);
11432 format %{ "VAG $dst,$src1,$src2\t// add packed2L" %}
11433 size(6);
11434 ins_encode %{
11435 __ z_vag($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11436 %}
11437 ins_pipe(pipe_class_dummy);
11438 %}
11439
11440 instruct vmul16B_reg(vecX dst, vecX src1, vecX src2) %{
11441 match(Set dst (MulVB src1 src2));
11442 predicate(n->as_Vector()->length() == 16);
11443 format %{ "VMLB $dst,$src1,$src2\t// mul packed16B" %}
11444 size(6);
11445 ins_encode %{
11446 __ z_vmlb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11447 %}
11448 ins_pipe(pipe_class_dummy);
11449 %}
11450
11451 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2) %{
11452 match(Set dst (MulVS src1 src2));
11453 predicate(n->as_Vector()->length() == 8);
11454 format %{ "VMLHW $dst,$src1,$src2\t// mul packed8S" %}
11455 size(6);
11456 ins_encode %{
11457 __ z_vmlhw($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11458 %}
11459 ins_pipe(pipe_class_dummy);
11460 %}
11461
11462 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
11463 match(Set dst (MulVI src1 src2));
11464 predicate(n->as_Vector()->length() == 4);
11465 format %{ "VMLF $dst,$src1,$src2\t// mul packed4I" %}
11466 size(6);
11467 ins_encode %{
11468 __ z_vmlf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11469 %}
11470 ins_pipe(pipe_class_dummy);
11471 %}
11472
11473 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
11474 match(Set dst (SubVB src1 src2));
11475 predicate(n->as_Vector()->length() == 16);
11476 format %{ "VSB $dst,$src1,$src2\t// sub packed16B" %}
11477 size(6);
11478 ins_encode %{
11479 __ z_vsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11480 %}
11481 ins_pipe(pipe_class_dummy);
11482 %}
11483
11484 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
11485 match(Set dst (SubVS src1 src2));
11486 predicate(n->as_Vector()->length() == 8);
11487 format %{ "VSH $dst,$src1,$src2\t// sub packed8S" %}
11488 size(6);
11489 ins_encode %{
11490 __ z_vsh($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11491 %}
11492 ins_pipe(pipe_class_dummy);
11493 %}
11494
11495 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
11496 match(Set dst (SubVI src1 src2));
11497 predicate(n->as_Vector()->length() == 4);
11498 format %{ "VSF $dst,$src1,$src2\t// sub packed4I" %}
11499 size(6);
11500 ins_encode %{
11501 __ z_vsf($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11502 %}
11503 ins_pipe(pipe_class_dummy);
11504 %}
11505
11506 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
11507 match(Set dst (SubVL src1 src2));
11508 predicate(n->as_Vector()->length() == 2);
11509 format %{ "VSG $dst,$src1,$src2\t// sub packed2L" %}
11510 size(6);
11511 ins_encode %{
11512 __ z_vsg($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11513 %}
11514 ins_pipe(pipe_class_dummy);
11515 %}
11516
11517 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
11518 match(Set dst (AddVF src1 src2));
11519 predicate(n->as_Vector()->length() == 4);
11520 format %{ "VFASB $dst,$src1,$src2\t// add packed4F" %}
11521 size(6);
11522 ins_encode %{
11523 __ z_vfasb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11524 %}
11525 ins_pipe(pipe_class_dummy);
11526 %}
11527
11528 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
11529 match(Set dst (AddVD src1 src2));
11530 predicate(n->as_Vector()->length() == 2);
11531 format %{ "VFADB $dst,$src1,$src2\t// add packed2D" %}
11532 size(6);
11533 ins_encode %{
11534 __ z_vfadb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11535 %}
11536 ins_pipe(pipe_class_dummy);
11537 %}
11538
11539 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
11540 match(Set dst (SubVF src1 src2));
11541 predicate(n->as_Vector()->length() == 4);
11542 format %{ "VFSSB $dst,$src1,$src2\t// sub packed4F" %}
11543 size(6);
11544 ins_encode %{
11545 __ z_vfssb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11546 %}
11547 ins_pipe(pipe_class_dummy);
11548 %}
11549
11550 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
11551 match(Set dst (SubVD src1 src2));
11552 predicate(n->as_Vector()->length() == 2);
11553 format %{ "VFSDB $dst,$src1,$src2\t// sub packed2D" %}
11554 size(6);
11555 ins_encode %{
11556 __ z_vfsdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11557 %}
11558 ins_pipe(pipe_class_dummy);
11559 %}
11560
11561 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
11562 match(Set dst (MulVF src1 src2));
11563 predicate(n->as_Vector()->length() == 4);
11564 format %{ "VFMSB $dst,$src1,$src2\t// mul packed4F" %}
11565 size(6);
11566 ins_encode %{
11567 __ z_vfmsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11568 %}
11569 ins_pipe(pipe_class_dummy);
11570 %}
11571
11572 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
11573 match(Set dst (MulVD src1 src2));
11574 predicate(n->as_Vector()->length() == 2);
11575 format %{ "VFMDB $dst,$src1,$src2\t// mul packed2D" %}
11576 size(6);
11577 ins_encode %{
11578 __ z_vfmdb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11579 %}
11580 ins_pipe(pipe_class_dummy);
11581 %}
11582
11583 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
11584 match(Set dst (DivVF src1 src2));
11585 predicate(n->as_Vector()->length() == 4);
11586 format %{ "VFDSB $dst,$src1,$src2\t// div packed4F" %}
11587 size(6);
11588 ins_encode %{
11589 __ z_vfdsb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11590 %}
11591 ins_pipe(pipe_class_dummy);
11592 %}
11593
11594 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
11595 match(Set dst (DivVD src1 src2));
11596 predicate(n->as_Vector()->length() == 2);
11597 format %{ "VFDDB $dst,$src1,$src2\t// div packed2D" %}
11598 size(6);
11599 ins_encode %{
11600 __ z_vfddb($dst$$VectorRegister, $src1$$VectorRegister, $src2$$VectorRegister);
11601 %}
11602 ins_pipe(pipe_class_dummy);
11603 %}
11604
11605 // Vector Square Root Instructions
11606
11607 instruct vsqrt4F_reg(vecX dst, vecX src) %{
11608 match(Set dst (SqrtVF src));
11609 predicate(n->as_Vector()->length() == 4);
11610 format %{ "VFSQSB $dst,$src\t// sqrt packed4F" %}
11611 size(6);
11612 ins_encode %{
11613 __ z_vfsqsb($dst$$VectorRegister, $src$$VectorRegister);
11614 %}
11615 ins_pipe(pipe_class_dummy);
11616 %}
11617
11618 instruct vsqrt2D_reg(vecX dst, vecX src) %{
11619 match(Set dst (SqrtVD src));
11620 predicate(n->as_Vector()->length() == 2);
11621 format %{ "VFSQDB $dst,$src\t// sqrt packed2D" %}
11622 size(6);
11623 ins_encode %{
11624 __ z_vfsqdb($dst$$VectorRegister, $src$$VectorRegister);
11625 %}
11626 ins_pipe(pipe_class_dummy);
11627 %}
11628
11629 // Vector Population Count Instructions
11630
11631 instruct vpopcnt_reg(vecX dst, vecX src) %{
11632 match(Set dst (PopCountVI src));
11633 format %{ "VPOPCT $dst,$src\t// pop count packed" %}
11634 size(6);
11635 ins_encode %{
11636 BasicType bt = Matcher::vector_element_basic_type(this);
11637 switch (bt) {
11638 case T_BYTE:
11639 __ z_vpopctb($dst$$VectorRegister, $src$$VectorRegister);
11640 break;
11641 case T_SHORT:
11642 __ z_vpopcth($dst$$VectorRegister, $src$$VectorRegister);
11643 break;
11644 case T_INT:
11645 __ z_vpopctf($dst$$VectorRegister, $src$$VectorRegister);
11646 break;
11647 case T_LONG:
11648 __ z_vpopctg($dst$$VectorRegister, $src$$VectorRegister);
11649 break;
11650 default:
11651 ShouldNotReachHere();
11652 }
11653 %}
11654 ins_pipe(pipe_class_dummy);
11655 %}
11656
11657 // Vector Round Instructions
11658 instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
11659 match(Set dst (RoundDoubleModeV src rmode));
11660 predicate(n->as_Vector()->length() == 2);
11661 format %{ "RoundDoubleModeV $src,$rmode" %}
11662 size(6);
11663 ins_encode %{
11664 switch ($rmode$$constant) {
11665 case RoundDoubleModeNode::rmode_rint:
11666 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 0);
11667 break;
11668 case RoundDoubleModeNode::rmode_floor:
11669 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 7);
11670 break;
11671 case RoundDoubleModeNode::rmode_ceil:
11672 __ z_vflrd($dst$$VectorRegister, $src$$VectorRegister, 6);
11673 break;
11674 default:
11675 ShouldNotReachHere();
11676 }
11677 %}
11678 ins_pipe(pipe_class_dummy);
11679 %}
11680
11681 //----------POPULATION COUNT RULES--------------------------------------------
11682
11683 // Byte reverse
11684
11685 instruct bytes_reverse_short(iRegI dst, iRegI src) %{
11686 match(Set dst (ReverseBytesS src));
11687 predicate(UseByteReverseInstruction);
11688 ins_cost(2 * DEFAULT_COST);
11689 size(8);
11690
11691 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11692 "SRA $dst, 0x0010\t # right shift by 16, sign extended" %}
11693
11694 ins_encode %{
11695 __ z_lrvr($dst$$Register, $src$$Register);
11696 __ z_sra($dst$$Register, 0x0010);
11697 %}
11698 ins_pipe(pipe_class_dummy);
11699 %}
11700
11701 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
11702 match(Set dst (ReverseBytesUS src));
11703 predicate(UseByteReverseInstruction);
11704 ins_cost(2 * DEFAULT_COST);
11705 size(8);
11706
11707 format %{ "LRVR $dst, $src\n\t # byte reverse int"
11708 "SRL $dst, 0x0010\t # right shift by 16, zero extended" %}
11709
11710 ins_encode %{
11711 __ z_lrvr($dst$$Register, $src$$Register);
11712 __ z_srl($dst$$Register, 0x0010);
11713 %}
11714 ins_pipe(pipe_class_dummy);
11715 %}
11716
11717 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
11718 match(Set dst (ReverseBytesI src));
11719 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11720 ins_cost(DEFAULT_COST);
11721 size(4);
11722 format %{ "LRVR $dst,$src\t # byte reverse int" %}
11723 opcode(LRVR_ZOPC);
11724 ins_encode(z_rreform(dst, src));
11725 ins_pipe(pipe_class_dummy);
11726 %}
11727
11728 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
11729 match(Set dst (ReverseBytesL src));
11730 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
11731 ins_cost(DEFAULT_COST);
11732 // TODO: s390 port size(FIXED_SIZE);
11733 format %{ "LRVGR $dst,$src\t # byte reverse long" %}
11734 opcode(LRVGR_ZOPC);
11735 ins_encode(z_rreform(dst, src));
11736 ins_pipe(pipe_class_dummy);
11737 %}
11738
11739 // Leading zeroes
11740
11741 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
11742 // returns the bit position of the leftmost 1 in the 64bit source register.
11743 // As the bits are numbered from left to right (0..63), the returned
11744 // position index is equivalent to the number of leading zeroes.
11745 // If no 1-bit is found (i.e. the register contains zero), the instruction
11746 // returns position 64. That's exactly what we need.
11747
11748 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11749 match(Set dst (CountLeadingZerosI src));
11750 effect(KILL tmp, KILL cr);
11751 ins_cost(3 * DEFAULT_COST);
11752 size(14);
11753 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
11754 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
11755 "FLOGR $dst,$dst"
11756 %}
11757 ins_encode %{
11758 // Performance experiments indicate that "FLOGR" is using some kind of
11759 // iteration to find the leftmost "1" bit.
11760 //
11761 // The prior implementation zero-extended the 32-bit argument to 64 bit,
11762 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
11763 // We could gain measurable speedup in micro benchmark:
11764 //
11765 // leading trailing
11766 // z10: int 2.04 1.68
11767 // long 1.00 1.02
11768 // z196: int 0.99 1.23
11769 // long 1.00 1.11
11770 //
11771 // By shifting the argument into the high-word instead of zero-extending it.
11772 // The add'l branch on condition (taken for a zero argument, very infrequent,
11773 // good prediction) is well compensated for by the savings.
11774 //
11775 // We leave the previous implementation in for some time in the future when
11776 // the "FLOGR" instruction may become less iterative.
11777
11778 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
11779 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
11780 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
11781 __ z_flogr($dst$$Register, $dst$$Register);
11782 %}
11783 ins_pipe(pipe_class_dummy);
11784 %}
11785
11786 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
11787 match(Set dst (CountLeadingZerosL src));
11788 effect(KILL tmp, KILL cr);
11789 ins_cost(DEFAULT_COST);
11790 size(4);
11791 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %}
11792 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
11793 ins_pipe(pipe_class_dummy);
11794 %}
11795
11796 // trailing zeroes
11797
11798 // We transform the trailing zeroes problem to a leading zeroes problem
11799 // such that can use the FLOGR instruction to our advantage.
11800
11801 // With
11802 // tmp1 = src - 1
11803 // we flip all trailing zeroes to ones and the rightmost one to zero.
11804 // All other bits remain unchanged.
11805 // With the complement
11806 // tmp2 = ~src
11807 // we get all ones in the trailing zeroes positions. Thus,
11808 // tmp3 = tmp1 & tmp2
11809 // yields ones in the trailing zeroes positions and zeroes elsewhere.
11810 // Now we can apply FLOGR and get 64-(trailing zeroes).
11811 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
11812 match(Set dst (CountTrailingZerosI src));
11813 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11814 ins_cost(8 * DEFAULT_COST);
11815 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11816 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t"
11817 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t"
11818 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11819 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t"
11820 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t"
11821 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t"
11822 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11823 "LCR $dst,$dst \t # res = -tmp4"
11824 %}
11825 ins_encode %{
11826 Register Rdst = $dst$$Register;
11827 Register Rsrc = $src$$Register;
11828 // Rtmp only needed for for zero-argument shortcut. With kill effect in
11829 // match rule Rsrc = roddReg would be possible, saving one register.
11830 Register Rtmp = $tmp$$Register;
11831
11832 assert_different_registers(Rdst, Rsrc, Rtmp);
11833
11834 // Algorithm:
11835 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
11836 // All other bits in the result are zero.
11837 // - Find the "leftmost one" bit position in the single-bit result from previous step.
11838 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
11839
11840 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
11841 Label done;
11842 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
11843 __ z_lcgfr(Rtmp, Rsrc);
11844 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
11845
11846 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
11847 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
11848 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
11849 // into upper half of reg. Not relevant with sllg below.
11850 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
11851 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
11852 // Depends on CC set by ahi above.
11853 // Taken very infrequently, good prediction, no BHT entry.
11854 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
11855 // after SLLG Rdst == 0(64bit)).
11856 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11857 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
11858 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11859 __ bind(done);
11860 %}
11861 ins_pipe(pipe_class_dummy);
11862 %}
11863
11864 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
11865 match(Set dst (CountTrailingZerosL src));
11866 effect(TEMP_DEF dst, KILL tmp, KILL cr);
11867 ins_cost(8 * DEFAULT_COST);
11868 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
11869 format %{ "LCGR $dst,$src \t # preserve src\n\t"
11870 "NGR $dst,$src \t #\n\t"
11871 "AGHI $dst,-1 \t # tmp1 = src-1\n\t"
11872 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t"
11873 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t"
11874 "LCR $dst,$dst \t #"
11875 %}
11876 ins_encode %{
11877 Register Rdst = $dst$$Register;
11878 Register Rsrc = $src$$Register;
11879 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
11880
11881 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
11882 __ z_lcgr(Rdst, Rsrc);
11883 __ z_ngr(Rdst, Rsrc);
11884 __ add2reg(Rdst, -1);
11885 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
11886 __ add2reg(Rdst, -64);
11887 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
11888 %}
11889 ins_pipe(pipe_class_dummy);
11890 %}
11891
11892
11893 // bit count
11894
11895 instruct popCountI_Ext3(iRegI dst, iRegI src, flagsReg cr) %{
11896 match(Set dst (PopCountI src));
11897 effect(TEMP_DEF dst, KILL cr);
11898 predicate(UsePopCountInstruction &&
11899 VM_Version::has_PopCount() &&
11900 VM_Version::has_MiscInstrExt3());
11901 ins_cost(DEFAULT_COST);
11902 size(8); // popcnt + llgfr
11903 format %{ "POPCNT $dst,$src\t # pop count int" %}
11904 ins_encode %{
11905 Register Rdst = $dst$$Register;
11906 Register Rsrc = $src$$Register;
11907
11908 __ pop_count_int_with_ext3(Rdst, Rsrc);
11909
11910 %}
11911 ins_pipe(pipe_class_dummy);
11912 %}
11913
11914 instruct popCountL_Ext3(iRegI dst, iRegL src, flagsReg cr) %{
11915 match(Set dst (PopCountL src));
11916 effect(TEMP_DEF dst, KILL cr);
11917 predicate(UsePopCountInstruction &&
11918 VM_Version::has_PopCount() &&
11919 VM_Version::has_MiscInstrExt3());
11920 ins_cost(DEFAULT_COST);
11921 size(4); // popcnt
11922 format %{ "POPCNT $dst,$src\t # pop count long" %}
11923 ins_encode %{
11924 Register Rdst = $dst$$Register;
11925 Register Rsrc = $src$$Register;
11926
11927 __ pop_count_long_with_ext3(Rdst, Rsrc);
11928 %}
11929 ins_pipe(pipe_class_dummy);
11930 %}
11931
11932 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
11933 match(Set dst (PopCountI src));
11934 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11935 predicate(UsePopCountInstruction &&
11936 VM_Version::has_PopCount() &&
11937 (!VM_Version::has_MiscInstrExt3()));
11938 ins_cost(DEFAULT_COST);
11939 size(24);
11940 format %{ "POPCNT $dst,$src\t # pop count int" %}
11941 ins_encode %{
11942 Register Rdst = $dst$$Register;
11943 Register Rsrc = $src$$Register;
11944 Register Rtmp = $tmp$$Register;
11945
11946 __ pop_count_int_without_ext3(Rdst, Rsrc, Rtmp);
11947
11948 %}
11949 ins_pipe(pipe_class_dummy);
11950 %}
11951
11952 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
11953 match(Set dst (PopCountL src));
11954 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11955 predicate(UsePopCountInstruction &&
11956 VM_Version::has_PopCount() &&
11957 (!VM_Version::has_MiscInstrExt3()));
11958 ins_cost(DEFAULT_COST);
11959 size(34);
11960 format %{ "POPCNT $dst,$src\t # pop count long" %}
11961 ins_encode %{
11962 Register Rdst = $dst$$Register;
11963 Register Rsrc = $src$$Register;
11964 Register Rtmp = $tmp$$Register;
11965
11966 __ pop_count_long_without_ext3(Rdst, Rsrc, Rtmp);
11967 %}
11968 ins_pipe(pipe_class_dummy);
11969 %}
11970
11971 //----------SMARTSPILL RULES---------------------------------------------------
11972 // These must follow all instruction definitions as they use the names
11973 // defined in the instructions definitions.
11974
11975 // ============================================================================
11976 // TYPE PROFILING RULES