1 /* 2 * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_CodeStubs.hpp" 29 #include "c1/c1_Compilation.hpp" 30 #include "c1/c1_LIRAssembler.hpp" 31 #include "c1/c1_MacroAssembler.hpp" 32 #include "c1/c1_Runtime1.hpp" 33 #include "c1/c1_ValueStack.hpp" 34 #include "ci/ciArrayKlass.hpp" 35 #include "ci/ciInstance.hpp" 36 #include "compiler/oopMap.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "gc/shared/gc_globals.hpp" 39 #include "nativeInst_x86.hpp" 40 #include "oops/objArrayKlass.hpp" 41 #include "runtime/frame.inline.hpp" 42 #include "runtime/safepointMechanism.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/stubRoutines.hpp" 45 #include "utilities/powerOfTwo.hpp" 46 #include "vmreg_x86.inline.hpp" 47 48 49 // These masks are used to provide 128-bit aligned bitmasks to the XMM 50 // instructions, to allow sign-masking or sign-bit flipping. They allow 51 // fast versions of NegF/NegD and AbsF/AbsD. 52 53 // Note: 'double' and 'long long' have 32-bits alignment on x86. 54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 55 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 56 // of 128-bits operands for SSE instructions. 57 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 58 // Store the value to a 128-bits operand. 59 operand[0] = lo; 60 operand[1] = hi; 61 return operand; 62 } 63 64 // Buffer for 128-bits masks used by SSE instructions. 65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 66 67 // Static initialization during VM startup. 68 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 70 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 72 73 74 NEEDS_CLEANUP // remove this definitions ? 75 const Register IC_Klass = rax; // where the IC klass is cached 76 const Register SYNC_header = rax; // synchronization header 77 const Register SHIFT_count = rcx; // where count for shift operations must be 78 79 #define __ _masm-> 80 81 82 static void select_different_registers(Register preserve, 83 Register extra, 84 Register &tmp1, 85 Register &tmp2) { 86 if (tmp1 == preserve) { 87 assert_different_registers(tmp1, tmp2, extra); 88 tmp1 = extra; 89 } else if (tmp2 == preserve) { 90 assert_different_registers(tmp1, tmp2, extra); 91 tmp2 = extra; 92 } 93 assert_different_registers(preserve, tmp1, tmp2); 94 } 95 96 97 98 static void select_different_registers(Register preserve, 99 Register extra, 100 Register &tmp1, 101 Register &tmp2, 102 Register &tmp3) { 103 if (tmp1 == preserve) { 104 assert_different_registers(tmp1, tmp2, tmp3, extra); 105 tmp1 = extra; 106 } else if (tmp2 == preserve) { 107 assert_different_registers(tmp1, tmp2, tmp3, extra); 108 tmp2 = extra; 109 } else if (tmp3 == preserve) { 110 assert_different_registers(tmp1, tmp2, tmp3, extra); 111 tmp3 = extra; 112 } 113 assert_different_registers(preserve, tmp1, tmp2, tmp3); 114 } 115 116 117 118 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 119 if (opr->is_constant()) { 120 LIR_Const* constant = opr->as_constant_ptr(); 121 switch (constant->type()) { 122 case T_INT: { 123 return true; 124 } 125 126 default: 127 return false; 128 } 129 } 130 return false; 131 } 132 133 134 LIR_Opr LIR_Assembler::receiverOpr() { 135 return FrameMap::receiver_opr; 136 } 137 138 LIR_Opr LIR_Assembler::osrBufferPointer() { 139 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 140 } 141 142 //--------------fpu register translations----------------------- 143 144 145 address LIR_Assembler::float_constant(float f) { 146 address const_addr = __ float_constant(f); 147 if (const_addr == nullptr) { 148 bailout("const section overflow"); 149 return __ code()->consts()->start(); 150 } else { 151 return const_addr; 152 } 153 } 154 155 156 address LIR_Assembler::double_constant(double d) { 157 address const_addr = __ double_constant(d); 158 if (const_addr == nullptr) { 159 bailout("const section overflow"); 160 return __ code()->consts()->start(); 161 } else { 162 return const_addr; 163 } 164 } 165 166 #ifndef _LP64 167 void LIR_Assembler::fpop() { 168 __ fpop(); 169 } 170 171 void LIR_Assembler::fxch(int i) { 172 __ fxch(i); 173 } 174 175 void LIR_Assembler::fld(int i) { 176 __ fld_s(i); 177 } 178 179 void LIR_Assembler::ffree(int i) { 180 __ ffree(i); 181 } 182 #endif // !_LP64 183 184 void LIR_Assembler::breakpoint() { 185 __ int3(); 186 } 187 188 void LIR_Assembler::push(LIR_Opr opr) { 189 if (opr->is_single_cpu()) { 190 __ push_reg(opr->as_register()); 191 } else if (opr->is_double_cpu()) { 192 NOT_LP64(__ push_reg(opr->as_register_hi())); 193 __ push_reg(opr->as_register_lo()); 194 } else if (opr->is_stack()) { 195 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 196 } else if (opr->is_constant()) { 197 LIR_Const* const_opr = opr->as_constant_ptr(); 198 if (const_opr->type() == T_OBJECT) { 199 __ push_oop(const_opr->as_jobject(), rscratch1); 200 } else if (const_opr->type() == T_INT) { 201 __ push_jint(const_opr->as_jint()); 202 } else { 203 ShouldNotReachHere(); 204 } 205 206 } else { 207 ShouldNotReachHere(); 208 } 209 } 210 211 void LIR_Assembler::pop(LIR_Opr opr) { 212 if (opr->is_single_cpu()) { 213 __ pop_reg(opr->as_register()); 214 } else { 215 ShouldNotReachHere(); 216 } 217 } 218 219 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 220 return addr->base()->is_illegal() && addr->index()->is_illegal(); 221 } 222 223 //------------------------------------------- 224 225 Address LIR_Assembler::as_Address(LIR_Address* addr) { 226 return as_Address(addr, rscratch1); 227 } 228 229 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 230 if (addr->base()->is_illegal()) { 231 assert(addr->index()->is_illegal(), "must be illegal too"); 232 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 233 if (! __ reachable(laddr)) { 234 __ movptr(tmp, laddr.addr()); 235 Address res(tmp, 0); 236 return res; 237 } else { 238 return __ as_Address(laddr); 239 } 240 } 241 242 Register base = addr->base()->as_pointer_register(); 243 244 if (addr->index()->is_illegal()) { 245 return Address( base, addr->disp()); 246 } else if (addr->index()->is_cpu_register()) { 247 Register index = addr->index()->as_pointer_register(); 248 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 249 } else if (addr->index()->is_constant()) { 250 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 251 assert(Assembler::is_simm32(addr_offset), "must be"); 252 253 return Address(base, addr_offset); 254 } else { 255 Unimplemented(); 256 return Address(); 257 } 258 } 259 260 261 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 262 Address base = as_Address(addr); 263 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 264 } 265 266 267 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 268 return as_Address(addr); 269 } 270 271 272 void LIR_Assembler::osr_entry() { 273 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 274 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 275 ValueStack* entry_state = osr_entry->state(); 276 int number_of_locks = entry_state->locks_size(); 277 278 // we jump here if osr happens with the interpreter 279 // state set up to continue at the beginning of the 280 // loop that triggered osr - in particular, we have 281 // the following registers setup: 282 // 283 // rcx: osr buffer 284 // 285 286 // build frame 287 ciMethod* m = compilation()->method(); 288 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 289 290 // OSR buffer is 291 // 292 // locals[nlocals-1..0] 293 // monitors[0..number_of_locks] 294 // 295 // locals is a direct copy of the interpreter frame so in the osr buffer 296 // so first slot in the local array is the last local from the interpreter 297 // and last slot is local[0] (receiver) from the interpreter 298 // 299 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 300 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 301 // in the interpreter frame (the method lock if a sync method) 302 303 // Initialize monitors in the compiled activation. 304 // rcx: pointer to osr buffer 305 // 306 // All other registers are dead at this point and the locals will be 307 // copied into place by code emitted in the IR. 308 309 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 310 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 311 int monitor_offset = BytesPerWord * method()->max_locals() + 312 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 313 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 314 // the OSR buffer using 2 word entries: first the lock and then 315 // the oop. 316 for (int i = 0; i < number_of_locks; i++) { 317 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 318 #ifdef ASSERT 319 // verify the interpreter's monitor has a non-null object 320 { 321 Label L; 322 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD); 323 __ jcc(Assembler::notZero, L); 324 __ stop("locked object is null"); 325 __ bind(L); 326 } 327 #endif 328 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 329 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 330 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 331 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 332 } 333 } 334 } 335 336 337 // inline cache check; done before the frame is built. 338 int LIR_Assembler::check_icache() { 339 Register receiver = FrameMap::receiver_opr->as_register(); 340 Register ic_klass = IC_Klass; 341 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 342 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 343 if (!do_post_padding) { 344 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 345 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 346 } 347 int offset = __ offset(); 348 __ inline_cache_check(receiver, IC_Klass); 349 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 350 if (do_post_padding) { 351 // force alignment after the cache check. 352 // It's been verified to be aligned if !VerifyOops 353 __ align(CodeEntryAlignment); 354 } 355 return offset; 356 } 357 358 void LIR_Assembler::clinit_barrier(ciMethod* method) { 359 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 360 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 361 362 Label L_skip_barrier; 363 Register klass = rscratch1; 364 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg ); 365 assert(thread != noreg, "x86_32 not implemented"); 366 367 __ mov_metadata(klass, method->holder()->constant_encoding()); 368 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/); 369 370 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 371 372 __ bind(L_skip_barrier); 373 } 374 375 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 376 jobject o = nullptr; 377 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 378 __ movoop(reg, o); 379 patching_epilog(patch, lir_patch_normal, reg, info); 380 } 381 382 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 383 Metadata* o = nullptr; 384 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 385 __ mov_metadata(reg, o); 386 patching_epilog(patch, lir_patch_normal, reg, info); 387 } 388 389 // This specifies the rsp decrement needed to build the frame 390 int LIR_Assembler::initial_frame_size_in_bytes() const { 391 // if rounding, must let FrameMap know! 392 393 // The frame_map records size in slots (32bit word) 394 395 // subtract two words to account for return address and link 396 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 397 } 398 399 400 int LIR_Assembler::emit_exception_handler() { 401 // generate code for exception handler 402 address handler_base = __ start_a_stub(exception_handler_size()); 403 if (handler_base == nullptr) { 404 // not enough space left for the handler 405 bailout("exception handler overflow"); 406 return -1; 407 } 408 409 int offset = code_offset(); 410 411 // the exception oop and pc are in rax, and rdx 412 // no other registers need to be preserved, so invalidate them 413 __ invalidate_registers(false, true, true, false, true, true); 414 415 // check that there is really an exception 416 __ verify_not_null_oop(rax); 417 418 // search an exception handler (rax: exception oop, rdx: throwing pc) 419 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 420 __ should_not_reach_here(); 421 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 422 __ end_a_stub(); 423 424 return offset; 425 } 426 427 428 // Emit the code to remove the frame from the stack in the exception 429 // unwind path. 430 int LIR_Assembler::emit_unwind_handler() { 431 #ifndef PRODUCT 432 if (CommentedAssembly) { 433 _masm->block_comment("Unwind handler"); 434 } 435 #endif 436 437 int offset = code_offset(); 438 439 // Fetch the exception from TLS and clear out exception related thread state 440 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 441 NOT_LP64(__ get_thread(thread)); 442 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 443 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD); 444 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD); 445 446 __ bind(_unwind_handler_entry); 447 __ verify_not_null_oop(rax); 448 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 449 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 450 } 451 452 // Perform needed unlocking 453 MonitorExitStub* stub = nullptr; 454 if (method()->is_synchronized()) { 455 monitor_address(0, FrameMap::rax_opr); 456 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 457 if (LockingMode == LM_MONITOR) { 458 __ jmp(*stub->entry()); 459 } else { 460 __ unlock_object(rdi, rsi, rax, *stub->entry()); 461 } 462 __ bind(*stub->continuation()); 463 } 464 465 if (compilation()->env()->dtrace_method_probes()) { 466 #ifdef _LP64 467 __ mov(rdi, r15_thread); 468 __ mov_metadata(rsi, method()->constant_encoding()); 469 #else 470 __ get_thread(rax); 471 __ movptr(Address(rsp, 0), rax); 472 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg); 473 #endif 474 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 475 } 476 477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 478 __ mov(rax, rbx); // Restore the exception 479 } 480 481 // remove the activation and dispatch to the unwind handler 482 __ remove_frame(initial_frame_size_in_bytes()); 483 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 484 485 // Emit the slow path assembly 486 if (stub != nullptr) { 487 stub->emit_code(this); 488 } 489 490 return offset; 491 } 492 493 494 int LIR_Assembler::emit_deopt_handler() { 495 // generate code for exception handler 496 address handler_base = __ start_a_stub(deopt_handler_size()); 497 if (handler_base == nullptr) { 498 // not enough space left for the handler 499 bailout("deopt handler overflow"); 500 return -1; 501 } 502 503 int offset = code_offset(); 504 InternalAddress here(__ pc()); 505 506 __ pushptr(here.addr(), rscratch1); 507 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 508 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 509 __ end_a_stub(); 510 511 return offset; 512 } 513 514 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 515 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 516 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 517 assert(result->fpu() == 0, "result must already be on TOS"); 518 } 519 520 // Pop the stack before the safepoint code 521 __ remove_frame(initial_frame_size_in_bytes()); 522 523 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 524 __ reserved_stack_check(); 525 } 526 527 // Note: we do not need to round double result; float result has the right precision 528 // the poll sets the condition code, but no data registers 529 530 #ifdef _LP64 531 const Register thread = r15_thread; 532 #else 533 const Register thread = rbx; 534 __ get_thread(thread); 535 #endif 536 code_stub->set_safepoint_offset(__ offset()); 537 __ relocate(relocInfo::poll_return_type); 538 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */); 539 __ ret(0); 540 } 541 542 543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 544 guarantee(info != nullptr, "Shouldn't be null"); 545 int offset = __ offset(); 546 #ifdef _LP64 547 const Register poll_addr = rscratch1; 548 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset())); 549 #else 550 assert(tmp->is_cpu_register(), "needed"); 551 const Register poll_addr = tmp->as_register(); 552 __ get_thread(poll_addr); 553 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset()))); 554 #endif 555 add_debug_info_for_branch(info); 556 __ relocate(relocInfo::poll_type); 557 address pre_pc = __ pc(); 558 __ testl(rax, Address(poll_addr, 0)); 559 address post_pc = __ pc(); 560 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 561 return offset; 562 } 563 564 565 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 566 if (from_reg != to_reg) __ mov(to_reg, from_reg); 567 } 568 569 void LIR_Assembler::swap_reg(Register a, Register b) { 570 __ xchgptr(a, b); 571 } 572 573 574 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 575 assert(src->is_constant(), "should not call otherwise"); 576 assert(dest->is_register(), "should not call otherwise"); 577 LIR_Const* c = src->as_constant_ptr(); 578 579 switch (c->type()) { 580 case T_INT: { 581 assert(patch_code == lir_patch_none, "no patching handled here"); 582 __ movl(dest->as_register(), c->as_jint()); 583 break; 584 } 585 586 case T_ADDRESS: { 587 assert(patch_code == lir_patch_none, "no patching handled here"); 588 __ movptr(dest->as_register(), c->as_jint()); 589 break; 590 } 591 592 case T_LONG: { 593 assert(patch_code == lir_patch_none, "no patching handled here"); 594 #ifdef _LP64 595 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 596 #else 597 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 598 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 599 #endif // _LP64 600 break; 601 } 602 603 case T_OBJECT: { 604 if (patch_code != lir_patch_none) { 605 jobject2reg_with_patching(dest->as_register(), info); 606 } else { 607 __ movoop(dest->as_register(), c->as_jobject()); 608 } 609 break; 610 } 611 612 case T_METADATA: { 613 if (patch_code != lir_patch_none) { 614 klass2reg_with_patching(dest->as_register(), info); 615 } else { 616 __ mov_metadata(dest->as_register(), c->as_metadata()); 617 } 618 break; 619 } 620 621 case T_FLOAT: { 622 if (dest->is_single_xmm()) { 623 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) { 624 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 625 } else { 626 __ movflt(dest->as_xmm_float_reg(), 627 InternalAddress(float_constant(c->as_jfloat()))); 628 } 629 } else { 630 #ifndef _LP64 631 assert(dest->is_single_fpu(), "must be"); 632 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 633 if (c->is_zero_float()) { 634 __ fldz(); 635 } else if (c->is_one_float()) { 636 __ fld1(); 637 } else { 638 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 639 } 640 #else 641 ShouldNotReachHere(); 642 #endif // !_LP64 643 } 644 break; 645 } 646 647 case T_DOUBLE: { 648 if (dest->is_double_xmm()) { 649 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) { 650 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 651 } else { 652 __ movdbl(dest->as_xmm_double_reg(), 653 InternalAddress(double_constant(c->as_jdouble()))); 654 } 655 } else { 656 #ifndef _LP64 657 assert(dest->is_double_fpu(), "must be"); 658 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 659 if (c->is_zero_double()) { 660 __ fldz(); 661 } else if (c->is_one_double()) { 662 __ fld1(); 663 } else { 664 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 665 } 666 #else 667 ShouldNotReachHere(); 668 #endif // !_LP64 669 } 670 break; 671 } 672 673 default: 674 ShouldNotReachHere(); 675 } 676 } 677 678 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 679 assert(src->is_constant(), "should not call otherwise"); 680 assert(dest->is_stack(), "should not call otherwise"); 681 LIR_Const* c = src->as_constant_ptr(); 682 683 switch (c->type()) { 684 case T_INT: // fall through 685 case T_FLOAT: 686 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 687 break; 688 689 case T_ADDRESS: 690 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 691 break; 692 693 case T_OBJECT: 694 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1); 695 break; 696 697 case T_LONG: // fall through 698 case T_DOUBLE: 699 #ifdef _LP64 700 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 701 lo_word_offset_in_bytes), 702 (intptr_t)c->as_jlong_bits(), 703 rscratch1); 704 #else 705 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 706 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 707 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 708 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 709 #endif // _LP64 710 break; 711 712 default: 713 ShouldNotReachHere(); 714 } 715 } 716 717 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 718 assert(src->is_constant(), "should not call otherwise"); 719 assert(dest->is_address(), "should not call otherwise"); 720 LIR_Const* c = src->as_constant_ptr(); 721 LIR_Address* addr = dest->as_address_ptr(); 722 723 int null_check_here = code_offset(); 724 switch (type) { 725 case T_INT: // fall through 726 case T_FLOAT: 727 __ movl(as_Address(addr), c->as_jint_bits()); 728 break; 729 730 case T_ADDRESS: 731 __ movptr(as_Address(addr), c->as_jint_bits()); 732 break; 733 734 case T_OBJECT: // fall through 735 case T_ARRAY: 736 if (c->as_jobject() == nullptr) { 737 if (UseCompressedOops && !wide) { 738 __ movl(as_Address(addr), NULL_WORD); 739 } else { 740 #ifdef _LP64 741 __ xorptr(rscratch1, rscratch1); 742 null_check_here = code_offset(); 743 __ movptr(as_Address(addr), rscratch1); 744 #else 745 __ movptr(as_Address(addr), NULL_WORD); 746 #endif 747 } 748 } else { 749 if (is_literal_address(addr)) { 750 ShouldNotReachHere(); 751 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1); 752 } else { 753 #ifdef _LP64 754 __ movoop(rscratch1, c->as_jobject()); 755 if (UseCompressedOops && !wide) { 756 __ encode_heap_oop(rscratch1); 757 null_check_here = code_offset(); 758 __ movl(as_Address_lo(addr), rscratch1); 759 } else { 760 null_check_here = code_offset(); 761 __ movptr(as_Address_lo(addr), rscratch1); 762 } 763 #else 764 __ movoop(as_Address(addr), c->as_jobject(), noreg); 765 #endif 766 } 767 } 768 break; 769 770 case T_LONG: // fall through 771 case T_DOUBLE: 772 #ifdef _LP64 773 if (is_literal_address(addr)) { 774 ShouldNotReachHere(); 775 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 776 } else { 777 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 778 null_check_here = code_offset(); 779 __ movptr(as_Address_lo(addr), r10); 780 } 781 #else 782 // Always reachable in 32bit so this doesn't produce useless move literal 783 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 784 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 785 #endif // _LP64 786 break; 787 788 case T_BOOLEAN: // fall through 789 case T_BYTE: 790 __ movb(as_Address(addr), c->as_jint() & 0xFF); 791 break; 792 793 case T_CHAR: // fall through 794 case T_SHORT: 795 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 796 break; 797 798 default: 799 ShouldNotReachHere(); 800 }; 801 802 if (info != nullptr) { 803 add_debug_info_for_null_check(null_check_here, info); 804 } 805 } 806 807 808 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 809 assert(src->is_register(), "should not call otherwise"); 810 assert(dest->is_register(), "should not call otherwise"); 811 812 // move between cpu-registers 813 if (dest->is_single_cpu()) { 814 #ifdef _LP64 815 if (src->type() == T_LONG) { 816 // Can do LONG -> OBJECT 817 move_regs(src->as_register_lo(), dest->as_register()); 818 return; 819 } 820 #endif 821 assert(src->is_single_cpu(), "must match"); 822 if (src->type() == T_OBJECT) { 823 __ verify_oop(src->as_register()); 824 } 825 move_regs(src->as_register(), dest->as_register()); 826 827 } else if (dest->is_double_cpu()) { 828 #ifdef _LP64 829 if (is_reference_type(src->type())) { 830 // Surprising to me but we can see move of a long to t_object 831 __ verify_oop(src->as_register()); 832 move_regs(src->as_register(), dest->as_register_lo()); 833 return; 834 } 835 #endif 836 assert(src->is_double_cpu(), "must match"); 837 Register f_lo = src->as_register_lo(); 838 Register f_hi = src->as_register_hi(); 839 Register t_lo = dest->as_register_lo(); 840 Register t_hi = dest->as_register_hi(); 841 #ifdef _LP64 842 assert(f_hi == f_lo, "must be same"); 843 assert(t_hi == t_lo, "must be same"); 844 move_regs(f_lo, t_lo); 845 #else 846 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 847 848 849 if (f_lo == t_hi && f_hi == t_lo) { 850 swap_reg(f_lo, f_hi); 851 } else if (f_hi == t_lo) { 852 assert(f_lo != t_hi, "overwriting register"); 853 move_regs(f_hi, t_hi); 854 move_regs(f_lo, t_lo); 855 } else { 856 assert(f_hi != t_lo, "overwriting register"); 857 move_regs(f_lo, t_lo); 858 move_regs(f_hi, t_hi); 859 } 860 #endif // LP64 861 862 #ifndef _LP64 863 // special moves from fpu-register to xmm-register 864 // necessary for method results 865 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 866 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 867 __ fld_s(Address(rsp, 0)); 868 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 869 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 870 __ fld_d(Address(rsp, 0)); 871 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 872 __ fstp_s(Address(rsp, 0)); 873 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 874 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 875 __ fstp_d(Address(rsp, 0)); 876 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 877 #endif // !_LP64 878 879 // move between xmm-registers 880 } else if (dest->is_single_xmm()) { 881 assert(src->is_single_xmm(), "must match"); 882 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 883 } else if (dest->is_double_xmm()) { 884 assert(src->is_double_xmm(), "must match"); 885 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 886 887 #ifndef _LP64 888 // move between fpu-registers (no instruction necessary because of fpu-stack) 889 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 890 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 891 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 892 #endif // !_LP64 893 894 } else { 895 ShouldNotReachHere(); 896 } 897 } 898 899 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 900 assert(src->is_register(), "should not call otherwise"); 901 assert(dest->is_stack(), "should not call otherwise"); 902 903 if (src->is_single_cpu()) { 904 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 905 if (is_reference_type(type)) { 906 __ verify_oop(src->as_register()); 907 __ movptr (dst, src->as_register()); 908 } else if (type == T_METADATA || type == T_ADDRESS) { 909 __ movptr (dst, src->as_register()); 910 } else { 911 __ movl (dst, src->as_register()); 912 } 913 914 } else if (src->is_double_cpu()) { 915 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 916 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 917 __ movptr (dstLO, src->as_register_lo()); 918 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 919 920 } else if (src->is_single_xmm()) { 921 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 922 __ movflt(dst_addr, src->as_xmm_float_reg()); 923 924 } else if (src->is_double_xmm()) { 925 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 926 __ movdbl(dst_addr, src->as_xmm_double_reg()); 927 928 #ifndef _LP64 929 } else if (src->is_single_fpu()) { 930 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 931 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 932 if (pop_fpu_stack) __ fstp_s (dst_addr); 933 else __ fst_s (dst_addr); 934 935 } else if (src->is_double_fpu()) { 936 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 937 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 938 if (pop_fpu_stack) __ fstp_d (dst_addr); 939 else __ fst_d (dst_addr); 940 #endif // !_LP64 941 942 } else { 943 ShouldNotReachHere(); 944 } 945 } 946 947 948 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { 949 LIR_Address* to_addr = dest->as_address_ptr(); 950 PatchingStub* patch = nullptr; 951 Register compressed_src = rscratch1; 952 953 if (is_reference_type(type)) { 954 __ verify_oop(src->as_register()); 955 #ifdef _LP64 956 if (UseCompressedOops && !wide) { 957 __ movptr(compressed_src, src->as_register()); 958 __ encode_heap_oop(compressed_src); 959 if (patch_code != lir_patch_none) { 960 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 961 } 962 } 963 #endif 964 } 965 966 if (patch_code != lir_patch_none) { 967 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 968 Address toa = as_Address(to_addr); 969 assert(toa.disp() != 0, "must have"); 970 } 971 972 int null_check_here = code_offset(); 973 switch (type) { 974 case T_FLOAT: { 975 #ifdef _LP64 976 assert(src->is_single_xmm(), "not a float"); 977 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 978 #else 979 if (src->is_single_xmm()) { 980 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 981 } else { 982 assert(src->is_single_fpu(), "must be"); 983 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 984 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 985 else __ fst_s (as_Address(to_addr)); 986 } 987 #endif // _LP64 988 break; 989 } 990 991 case T_DOUBLE: { 992 #ifdef _LP64 993 assert(src->is_double_xmm(), "not a double"); 994 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 995 #else 996 if (src->is_double_xmm()) { 997 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 998 } else { 999 assert(src->is_double_fpu(), "must be"); 1000 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1001 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1002 else __ fst_d (as_Address(to_addr)); 1003 } 1004 #endif // _LP64 1005 break; 1006 } 1007 1008 case T_ARRAY: // fall through 1009 case T_OBJECT: // fall through 1010 if (UseCompressedOops && !wide) { 1011 __ movl(as_Address(to_addr), compressed_src); 1012 } else { 1013 __ movptr(as_Address(to_addr), src->as_register()); 1014 } 1015 break; 1016 case T_METADATA: 1017 // We get here to store a method pointer to the stack to pass to 1018 // a dtrace runtime call. This can't work on 64 bit with 1019 // compressed klass ptrs: T_METADATA can be a compressed klass 1020 // ptr or a 64 bit method pointer. 1021 LP64_ONLY(ShouldNotReachHere()); 1022 __ movptr(as_Address(to_addr), src->as_register()); 1023 break; 1024 case T_ADDRESS: 1025 __ movptr(as_Address(to_addr), src->as_register()); 1026 break; 1027 case T_INT: 1028 __ movl(as_Address(to_addr), src->as_register()); 1029 break; 1030 1031 case T_LONG: { 1032 Register from_lo = src->as_register_lo(); 1033 Register from_hi = src->as_register_hi(); 1034 #ifdef _LP64 1035 __ movptr(as_Address_lo(to_addr), from_lo); 1036 #else 1037 Register base = to_addr->base()->as_register(); 1038 Register index = noreg; 1039 if (to_addr->index()->is_register()) { 1040 index = to_addr->index()->as_register(); 1041 } 1042 if (base == from_lo || index == from_lo) { 1043 assert(base != from_hi, "can't be"); 1044 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1045 __ movl(as_Address_hi(to_addr), from_hi); 1046 if (patch != nullptr) { 1047 patching_epilog(patch, lir_patch_high, base, info); 1048 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1049 patch_code = lir_patch_low; 1050 } 1051 __ movl(as_Address_lo(to_addr), from_lo); 1052 } else { 1053 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1054 __ movl(as_Address_lo(to_addr), from_lo); 1055 if (patch != nullptr) { 1056 patching_epilog(patch, lir_patch_low, base, info); 1057 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1058 patch_code = lir_patch_high; 1059 } 1060 __ movl(as_Address_hi(to_addr), from_hi); 1061 } 1062 #endif // _LP64 1063 break; 1064 } 1065 1066 case T_BYTE: // fall through 1067 case T_BOOLEAN: { 1068 Register src_reg = src->as_register(); 1069 Address dst_addr = as_Address(to_addr); 1070 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1071 __ movb(dst_addr, src_reg); 1072 break; 1073 } 1074 1075 case T_CHAR: // fall through 1076 case T_SHORT: 1077 __ movw(as_Address(to_addr), src->as_register()); 1078 break; 1079 1080 default: 1081 ShouldNotReachHere(); 1082 } 1083 if (info != nullptr) { 1084 add_debug_info_for_null_check(null_check_here, info); 1085 } 1086 1087 if (patch_code != lir_patch_none) { 1088 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1089 } 1090 } 1091 1092 1093 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1094 assert(src->is_stack(), "should not call otherwise"); 1095 assert(dest->is_register(), "should not call otherwise"); 1096 1097 if (dest->is_single_cpu()) { 1098 if (is_reference_type(type)) { 1099 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1100 __ verify_oop(dest->as_register()); 1101 } else if (type == T_METADATA || type == T_ADDRESS) { 1102 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1103 } else { 1104 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1105 } 1106 1107 } else if (dest->is_double_cpu()) { 1108 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1109 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1110 __ movptr(dest->as_register_lo(), src_addr_LO); 1111 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1112 1113 } else if (dest->is_single_xmm()) { 1114 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1115 __ movflt(dest->as_xmm_float_reg(), src_addr); 1116 1117 } else if (dest->is_double_xmm()) { 1118 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1119 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1120 1121 #ifndef _LP64 1122 } else if (dest->is_single_fpu()) { 1123 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1124 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1125 __ fld_s(src_addr); 1126 1127 } else if (dest->is_double_fpu()) { 1128 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1129 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1130 __ fld_d(src_addr); 1131 #endif // _LP64 1132 1133 } else { 1134 ShouldNotReachHere(); 1135 } 1136 } 1137 1138 1139 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1140 if (src->is_single_stack()) { 1141 if (is_reference_type(type)) { 1142 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1143 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1144 } else { 1145 #ifndef _LP64 1146 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1147 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1148 #else 1149 //no pushl on 64bits 1150 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1151 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1152 #endif 1153 } 1154 1155 } else if (src->is_double_stack()) { 1156 #ifdef _LP64 1157 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1158 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1159 #else 1160 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1161 // push and pop the part at src + wordSize, adding wordSize for the previous push 1162 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1163 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1165 #endif // _LP64 1166 1167 } else { 1168 ShouldNotReachHere(); 1169 } 1170 } 1171 1172 1173 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 1174 assert(src->is_address(), "should not call otherwise"); 1175 assert(dest->is_register(), "should not call otherwise"); 1176 1177 LIR_Address* addr = src->as_address_ptr(); 1178 Address from_addr = as_Address(addr); 1179 1180 if (addr->base()->type() == T_OBJECT) { 1181 __ verify_oop(addr->base()->as_pointer_register()); 1182 } 1183 1184 switch (type) { 1185 case T_BOOLEAN: // fall through 1186 case T_BYTE: // fall through 1187 case T_CHAR: // fall through 1188 case T_SHORT: 1189 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1190 // on pre P6 processors we may get partial register stalls 1191 // so blow away the value of to_rinfo before loading a 1192 // partial word into it. Do it here so that it precedes 1193 // the potential patch point below. 1194 __ xorptr(dest->as_register(), dest->as_register()); 1195 } 1196 break; 1197 default: 1198 break; 1199 } 1200 1201 PatchingStub* patch = nullptr; 1202 if (patch_code != lir_patch_none) { 1203 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1204 assert(from_addr.disp() != 0, "must have"); 1205 } 1206 if (info != nullptr) { 1207 add_debug_info_for_null_check_here(info); 1208 } 1209 1210 switch (type) { 1211 case T_FLOAT: { 1212 if (dest->is_single_xmm()) { 1213 __ movflt(dest->as_xmm_float_reg(), from_addr); 1214 } else { 1215 #ifndef _LP64 1216 assert(dest->is_single_fpu(), "must be"); 1217 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1218 __ fld_s(from_addr); 1219 #else 1220 ShouldNotReachHere(); 1221 #endif // !LP64 1222 } 1223 break; 1224 } 1225 1226 case T_DOUBLE: { 1227 if (dest->is_double_xmm()) { 1228 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1229 } else { 1230 #ifndef _LP64 1231 assert(dest->is_double_fpu(), "must be"); 1232 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1233 __ fld_d(from_addr); 1234 #else 1235 ShouldNotReachHere(); 1236 #endif // !LP64 1237 } 1238 break; 1239 } 1240 1241 case T_OBJECT: // fall through 1242 case T_ARRAY: // fall through 1243 if (UseCompressedOops && !wide) { 1244 __ movl(dest->as_register(), from_addr); 1245 } else { 1246 __ movptr(dest->as_register(), from_addr); 1247 } 1248 break; 1249 1250 case T_ADDRESS: 1251 __ movptr(dest->as_register(), from_addr); 1252 break; 1253 case T_INT: 1254 __ movl(dest->as_register(), from_addr); 1255 break; 1256 1257 case T_LONG: { 1258 Register to_lo = dest->as_register_lo(); 1259 Register to_hi = dest->as_register_hi(); 1260 #ifdef _LP64 1261 __ movptr(to_lo, as_Address_lo(addr)); 1262 #else 1263 Register base = addr->base()->as_register(); 1264 Register index = noreg; 1265 if (addr->index()->is_register()) { 1266 index = addr->index()->as_register(); 1267 } 1268 if ((base == to_lo && index == to_hi) || 1269 (base == to_hi && index == to_lo)) { 1270 // addresses with 2 registers are only formed as a result of 1271 // array access so this code will never have to deal with 1272 // patches or null checks. 1273 assert(info == nullptr && patch == nullptr, "must be"); 1274 __ lea(to_hi, as_Address(addr)); 1275 __ movl(to_lo, Address(to_hi, 0)); 1276 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1277 } else if (base == to_lo || index == to_lo) { 1278 assert(base != to_hi, "can't be"); 1279 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1280 __ movl(to_hi, as_Address_hi(addr)); 1281 if (patch != nullptr) { 1282 patching_epilog(patch, lir_patch_high, base, info); 1283 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1284 patch_code = lir_patch_low; 1285 } 1286 __ movl(to_lo, as_Address_lo(addr)); 1287 } else { 1288 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1289 __ movl(to_lo, as_Address_lo(addr)); 1290 if (patch != nullptr) { 1291 patching_epilog(patch, lir_patch_low, base, info); 1292 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1293 patch_code = lir_patch_high; 1294 } 1295 __ movl(to_hi, as_Address_hi(addr)); 1296 } 1297 #endif // _LP64 1298 break; 1299 } 1300 1301 case T_BOOLEAN: // fall through 1302 case T_BYTE: { 1303 Register dest_reg = dest->as_register(); 1304 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1305 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1306 __ movsbl(dest_reg, from_addr); 1307 } else { 1308 __ movb(dest_reg, from_addr); 1309 __ shll(dest_reg, 24); 1310 __ sarl(dest_reg, 24); 1311 } 1312 break; 1313 } 1314 1315 case T_CHAR: { 1316 Register dest_reg = dest->as_register(); 1317 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1318 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1319 __ movzwl(dest_reg, from_addr); 1320 } else { 1321 __ movw(dest_reg, from_addr); 1322 } 1323 break; 1324 } 1325 1326 case T_SHORT: { 1327 Register dest_reg = dest->as_register(); 1328 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1329 __ movswl(dest_reg, from_addr); 1330 } else { 1331 __ movw(dest_reg, from_addr); 1332 __ shll(dest_reg, 16); 1333 __ sarl(dest_reg, 16); 1334 } 1335 break; 1336 } 1337 1338 default: 1339 ShouldNotReachHere(); 1340 } 1341 1342 if (patch != nullptr) { 1343 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1344 } 1345 1346 if (is_reference_type(type)) { 1347 #ifdef _LP64 1348 if (UseCompressedOops && !wide) { 1349 __ decode_heap_oop(dest->as_register()); 1350 } 1351 #endif 1352 1353 if (!(UseZGC && !ZGenerational)) { 1354 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1355 __ verify_oop(dest->as_register()); 1356 } 1357 } 1358 } 1359 1360 1361 NEEDS_CLEANUP; // This could be static? 1362 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1363 int elem_size = type2aelembytes(type); 1364 switch (elem_size) { 1365 case 1: return Address::times_1; 1366 case 2: return Address::times_2; 1367 case 4: return Address::times_4; 1368 case 8: return Address::times_8; 1369 } 1370 ShouldNotReachHere(); 1371 return Address::no_scale; 1372 } 1373 1374 1375 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1376 switch (op->code()) { 1377 case lir_idiv: 1378 case lir_irem: 1379 arithmetic_idiv(op->code(), 1380 op->in_opr1(), 1381 op->in_opr2(), 1382 op->in_opr3(), 1383 op->result_opr(), 1384 op->info()); 1385 break; 1386 case lir_fmad: 1387 __ fmad(op->result_opr()->as_xmm_double_reg(), 1388 op->in_opr1()->as_xmm_double_reg(), 1389 op->in_opr2()->as_xmm_double_reg(), 1390 op->in_opr3()->as_xmm_double_reg()); 1391 break; 1392 case lir_fmaf: 1393 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1394 op->in_opr1()->as_xmm_float_reg(), 1395 op->in_opr2()->as_xmm_float_reg(), 1396 op->in_opr3()->as_xmm_float_reg()); 1397 break; 1398 default: ShouldNotReachHere(); break; 1399 } 1400 } 1401 1402 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1403 #ifdef ASSERT 1404 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label"); 1405 if (op->block() != nullptr) _branch_target_blocks.append(op->block()); 1406 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock()); 1407 #endif 1408 1409 if (op->cond() == lir_cond_always) { 1410 if (op->info() != nullptr) add_debug_info_for_branch(op->info()); 1411 __ jmp (*(op->label())); 1412 } else { 1413 Assembler::Condition acond = Assembler::zero; 1414 if (op->code() == lir_cond_float_branch) { 1415 assert(op->ublock() != nullptr, "must have unordered successor"); 1416 __ jcc(Assembler::parity, *(op->ublock()->label())); 1417 switch(op->cond()) { 1418 case lir_cond_equal: acond = Assembler::equal; break; 1419 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1420 case lir_cond_less: acond = Assembler::below; break; 1421 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1422 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1423 case lir_cond_greater: acond = Assembler::above; break; 1424 default: ShouldNotReachHere(); 1425 } 1426 } else { 1427 switch (op->cond()) { 1428 case lir_cond_equal: acond = Assembler::equal; break; 1429 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1430 case lir_cond_less: acond = Assembler::less; break; 1431 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1432 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1433 case lir_cond_greater: acond = Assembler::greater; break; 1434 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1435 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1436 default: ShouldNotReachHere(); 1437 } 1438 } 1439 __ jcc(acond,*(op->label())); 1440 } 1441 } 1442 1443 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1444 LIR_Opr src = op->in_opr(); 1445 LIR_Opr dest = op->result_opr(); 1446 1447 switch (op->bytecode()) { 1448 case Bytecodes::_i2l: 1449 #ifdef _LP64 1450 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1451 #else 1452 move_regs(src->as_register(), dest->as_register_lo()); 1453 move_regs(src->as_register(), dest->as_register_hi()); 1454 __ sarl(dest->as_register_hi(), 31); 1455 #endif // LP64 1456 break; 1457 1458 case Bytecodes::_l2i: 1459 #ifdef _LP64 1460 __ movl(dest->as_register(), src->as_register_lo()); 1461 #else 1462 move_regs(src->as_register_lo(), dest->as_register()); 1463 #endif 1464 break; 1465 1466 case Bytecodes::_i2b: 1467 move_regs(src->as_register(), dest->as_register()); 1468 __ sign_extend_byte(dest->as_register()); 1469 break; 1470 1471 case Bytecodes::_i2c: 1472 move_regs(src->as_register(), dest->as_register()); 1473 __ andl(dest->as_register(), 0xFFFF); 1474 break; 1475 1476 case Bytecodes::_i2s: 1477 move_regs(src->as_register(), dest->as_register()); 1478 __ sign_extend_short(dest->as_register()); 1479 break; 1480 1481 1482 #ifdef _LP64 1483 case Bytecodes::_f2d: 1484 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1485 break; 1486 1487 case Bytecodes::_d2f: 1488 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1489 break; 1490 1491 case Bytecodes::_i2f: 1492 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1493 break; 1494 1495 case Bytecodes::_i2d: 1496 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1497 break; 1498 1499 case Bytecodes::_l2f: 1500 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo()); 1501 break; 1502 1503 case Bytecodes::_l2d: 1504 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo()); 1505 break; 1506 1507 case Bytecodes::_f2i: 1508 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg()); 1509 break; 1510 1511 case Bytecodes::_d2i: 1512 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg()); 1513 break; 1514 1515 case Bytecodes::_f2l: 1516 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg()); 1517 break; 1518 1519 case Bytecodes::_d2l: 1520 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg()); 1521 break; 1522 #else 1523 case Bytecodes::_f2d: 1524 case Bytecodes::_d2f: 1525 if (dest->is_single_xmm()) { 1526 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1527 } else if (dest->is_double_xmm()) { 1528 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1529 } else { 1530 assert(src->fpu() == dest->fpu(), "register must be equal"); 1531 // do nothing (float result is rounded later through spilling) 1532 } 1533 break; 1534 1535 case Bytecodes::_i2f: 1536 case Bytecodes::_i2d: 1537 if (dest->is_single_xmm()) { 1538 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1539 } else if (dest->is_double_xmm()) { 1540 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1541 } else { 1542 assert(dest->fpu() == 0, "result must be on TOS"); 1543 __ movl(Address(rsp, 0), src->as_register()); 1544 __ fild_s(Address(rsp, 0)); 1545 } 1546 break; 1547 1548 case Bytecodes::_l2f: 1549 case Bytecodes::_l2d: 1550 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1551 assert(dest->fpu() == 0, "result must be on TOS"); 1552 __ movptr(Address(rsp, 0), src->as_register_lo()); 1553 __ movl(Address(rsp, BytesPerWord), src->as_register_hi()); 1554 __ fild_d(Address(rsp, 0)); 1555 // float result is rounded later through spilling 1556 break; 1557 1558 case Bytecodes::_f2i: 1559 case Bytecodes::_d2i: 1560 if (src->is_single_xmm()) { 1561 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1562 } else if (src->is_double_xmm()) { 1563 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1564 } else { 1565 assert(src->fpu() == 0, "input must be on TOS"); 1566 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc())); 1567 __ fist_s(Address(rsp, 0)); 1568 __ movl(dest->as_register(), Address(rsp, 0)); 1569 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std())); 1570 } 1571 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1572 assert(op->stub() != nullptr, "stub required"); 1573 __ cmpl(dest->as_register(), 0x80000000); 1574 __ jcc(Assembler::equal, *op->stub()->entry()); 1575 __ bind(*op->stub()->continuation()); 1576 break; 1577 1578 case Bytecodes::_f2l: 1579 case Bytecodes::_d2l: 1580 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1581 assert(src->fpu() == 0, "input must be on TOS"); 1582 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1583 1584 // instruction sequence too long to inline it here 1585 { 1586 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1587 } 1588 break; 1589 #endif // _LP64 1590 1591 default: ShouldNotReachHere(); 1592 } 1593 } 1594 1595 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1596 if (op->init_check()) { 1597 add_debug_info_for_null_check_here(op->stub()->info()); 1598 __ cmpb(Address(op->klass()->as_register(), 1599 InstanceKlass::init_state_offset()), 1600 InstanceKlass::fully_initialized); 1601 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1602 } 1603 __ allocate_object(op->obj()->as_register(), 1604 op->tmp1()->as_register(), 1605 op->tmp2()->as_register(), 1606 op->header_size(), 1607 op->object_size(), 1608 op->klass()->as_register(), 1609 *op->stub()->entry()); 1610 __ bind(*op->stub()->continuation()); 1611 } 1612 1613 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1614 Register len = op->len()->as_register(); 1615 LP64_ONLY( __ movslq(len, len); ) 1616 1617 if (UseSlowPath || 1618 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1619 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1620 __ jmp(*op->stub()->entry()); 1621 } else { 1622 Register tmp1 = op->tmp1()->as_register(); 1623 Register tmp2 = op->tmp2()->as_register(); 1624 Register tmp3 = op->tmp3()->as_register(); 1625 if (len == tmp1) { 1626 tmp1 = tmp3; 1627 } else if (len == tmp2) { 1628 tmp2 = tmp3; 1629 } else if (len == tmp3) { 1630 // everything is ok 1631 } else { 1632 __ mov(tmp3, len); 1633 } 1634 __ allocate_array(op->obj()->as_register(), 1635 len, 1636 tmp1, 1637 tmp2, 1638 arrayOopDesc::header_size(op->type()), 1639 array_element_size(op->type()), 1640 op->klass()->as_register(), 1641 *op->stub()->entry()); 1642 } 1643 __ bind(*op->stub()->continuation()); 1644 } 1645 1646 void LIR_Assembler::type_profile_helper(Register mdo, 1647 ciMethodData *md, ciProfileData *data, 1648 Register recv, Label* update_done) { 1649 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1650 Label next_test; 1651 // See if the receiver is receiver[n]. 1652 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1653 __ jccb(Assembler::notEqual, next_test); 1654 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1655 __ addptr(data_addr, DataLayout::counter_increment); 1656 __ jmp(*update_done); 1657 __ bind(next_test); 1658 } 1659 1660 // Didn't find receiver; find next empty slot and fill it in 1661 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1662 Label next_test; 1663 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1664 __ cmpptr(recv_addr, NULL_WORD); 1665 __ jccb(Assembler::notEqual, next_test); 1666 __ movptr(recv_addr, recv); 1667 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1668 __ jmp(*update_done); 1669 __ bind(next_test); 1670 } 1671 } 1672 1673 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1674 // we always need a stub for the failure case. 1675 CodeStub* stub = op->stub(); 1676 Register obj = op->object()->as_register(); 1677 Register k_RInfo = op->tmp1()->as_register(); 1678 Register klass_RInfo = op->tmp2()->as_register(); 1679 Register dst = op->result_opr()->as_register(); 1680 ciKlass* k = op->klass(); 1681 Register Rtmp1 = noreg; 1682 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 1683 1684 // check if it needs to be profiled 1685 ciMethodData* md = nullptr; 1686 ciProfileData* data = nullptr; 1687 1688 if (op->should_profile()) { 1689 ciMethod* method = op->profiled_method(); 1690 assert(method != nullptr, "Should have method"); 1691 int bci = op->profiled_bci(); 1692 md = method->method_data_or_null(); 1693 assert(md != nullptr, "Sanity"); 1694 data = md->bci_to_data(bci); 1695 assert(data != nullptr, "need data for type check"); 1696 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1697 } 1698 Label* success_target = success; 1699 Label* failure_target = failure; 1700 1701 if (obj == k_RInfo) { 1702 k_RInfo = dst; 1703 } else if (obj == klass_RInfo) { 1704 klass_RInfo = dst; 1705 } 1706 if (k->is_loaded() && !UseCompressedClassPointers) { 1707 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1708 } else { 1709 Rtmp1 = op->tmp3()->as_register(); 1710 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1711 } 1712 1713 assert_different_registers(obj, k_RInfo, klass_RInfo); 1714 1715 __ testptr(obj, obj); 1716 if (op->should_profile()) { 1717 Label not_null; 1718 Register mdo = klass_RInfo; 1719 __ mov_metadata(mdo, md->constant_encoding()); 1720 __ jccb(Assembler::notEqual, not_null); 1721 // Object is null; update MDO and exit 1722 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1723 int header_bits = BitData::null_seen_byte_constant(); 1724 __ orb(data_addr, header_bits); 1725 __ jmp(*obj_is_null); 1726 __ bind(not_null); 1727 1728 Label update_done; 1729 Register recv = k_RInfo; 1730 __ load_klass(recv, obj, tmp_load_klass); 1731 type_profile_helper(mdo, md, data, recv, &update_done); 1732 1733 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1734 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment); 1735 1736 __ bind(update_done); 1737 } else { 1738 __ jcc(Assembler::equal, *obj_is_null); 1739 } 1740 1741 if (!k->is_loaded()) { 1742 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1743 } else { 1744 #ifdef _LP64 1745 __ mov_metadata(k_RInfo, k->constant_encoding()); 1746 #endif // _LP64 1747 } 1748 __ verify_oop(obj); 1749 1750 if (op->fast_check()) { 1751 // get object class 1752 // not a safepoint as obj null check happens earlier 1753 #ifdef _LP64 1754 if (UseCompressedClassPointers) { 1755 __ load_klass(Rtmp1, obj, tmp_load_klass); 1756 __ cmpptr(k_RInfo, Rtmp1); 1757 } else { 1758 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1759 } 1760 #else 1761 if (k->is_loaded()) { 1762 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1763 } else { 1764 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1765 } 1766 #endif 1767 __ jcc(Assembler::notEqual, *failure_target); 1768 // successful cast, fall through to profile or jump 1769 } else { 1770 // get object class 1771 // not a safepoint as obj null check happens earlier 1772 __ load_klass(klass_RInfo, obj, tmp_load_klass); 1773 if (k->is_loaded()) { 1774 // See if we get an immediate positive hit 1775 #ifdef _LP64 1776 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1777 #else 1778 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1779 #endif // _LP64 1780 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1781 __ jcc(Assembler::notEqual, *failure_target); 1782 // successful cast, fall through to profile or jump 1783 } else { 1784 // See if we get an immediate positive hit 1785 __ jcc(Assembler::equal, *success_target); 1786 // check for self 1787 #ifdef _LP64 1788 __ cmpptr(klass_RInfo, k_RInfo); 1789 #else 1790 __ cmpklass(klass_RInfo, k->constant_encoding()); 1791 #endif // _LP64 1792 __ jcc(Assembler::equal, *success_target); 1793 1794 __ push(klass_RInfo); 1795 #ifdef _LP64 1796 __ push(k_RInfo); 1797 #else 1798 __ pushklass(k->constant_encoding(), noreg); 1799 #endif // _LP64 1800 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1801 __ pop(klass_RInfo); 1802 __ pop(klass_RInfo); 1803 // result is a boolean 1804 __ testl(klass_RInfo, klass_RInfo); 1805 __ jcc(Assembler::equal, *failure_target); 1806 // successful cast, fall through to profile or jump 1807 } 1808 } else { 1809 // perform the fast part of the checking logic 1810 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1811 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1812 __ push(klass_RInfo); 1813 __ push(k_RInfo); 1814 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1815 __ pop(klass_RInfo); 1816 __ pop(k_RInfo); 1817 // result is a boolean 1818 __ testl(k_RInfo, k_RInfo); 1819 __ jcc(Assembler::equal, *failure_target); 1820 // successful cast, fall through to profile or jump 1821 } 1822 } 1823 __ jmp(*success); 1824 } 1825 1826 1827 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1828 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 1829 LIR_Code code = op->code(); 1830 if (code == lir_store_check) { 1831 Register value = op->object()->as_register(); 1832 Register array = op->array()->as_register(); 1833 Register k_RInfo = op->tmp1()->as_register(); 1834 Register klass_RInfo = op->tmp2()->as_register(); 1835 Register Rtmp1 = op->tmp3()->as_register(); 1836 1837 CodeStub* stub = op->stub(); 1838 1839 // check if it needs to be profiled 1840 ciMethodData* md = nullptr; 1841 ciProfileData* data = nullptr; 1842 1843 if (op->should_profile()) { 1844 ciMethod* method = op->profiled_method(); 1845 assert(method != nullptr, "Should have method"); 1846 int bci = op->profiled_bci(); 1847 md = method->method_data_or_null(); 1848 assert(md != nullptr, "Sanity"); 1849 data = md->bci_to_data(bci); 1850 assert(data != nullptr, "need data for type check"); 1851 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1852 } 1853 Label done; 1854 Label* success_target = &done; 1855 Label* failure_target = stub->entry(); 1856 1857 __ testptr(value, value); 1858 if (op->should_profile()) { 1859 Label not_null; 1860 Register mdo = klass_RInfo; 1861 __ mov_metadata(mdo, md->constant_encoding()); 1862 __ jccb(Assembler::notEqual, not_null); 1863 // Object is null; update MDO and exit 1864 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1865 int header_bits = BitData::null_seen_byte_constant(); 1866 __ orb(data_addr, header_bits); 1867 __ jmp(done); 1868 __ bind(not_null); 1869 1870 Label update_done; 1871 Register recv = k_RInfo; 1872 __ load_klass(recv, value, tmp_load_klass); 1873 type_profile_helper(mdo, md, data, recv, &update_done); 1874 1875 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1876 __ addptr(counter_addr, DataLayout::counter_increment); 1877 __ bind(update_done); 1878 } else { 1879 __ jcc(Assembler::equal, done); 1880 } 1881 1882 add_debug_info_for_null_check_here(op->info_for_exception()); 1883 __ load_klass(k_RInfo, array, tmp_load_klass); 1884 __ load_klass(klass_RInfo, value, tmp_load_klass); 1885 1886 // get instance klass (it's already uncompressed) 1887 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1888 // perform the fast part of the checking logic 1889 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1890 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1891 __ push(klass_RInfo); 1892 __ push(k_RInfo); 1893 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1894 __ pop(klass_RInfo); 1895 __ pop(k_RInfo); 1896 // result is a boolean 1897 __ testl(k_RInfo, k_RInfo); 1898 __ jcc(Assembler::equal, *failure_target); 1899 // fall through to the success case 1900 1901 __ bind(done); 1902 } else 1903 if (code == lir_checkcast) { 1904 Register obj = op->object()->as_register(); 1905 Register dst = op->result_opr()->as_register(); 1906 Label success; 1907 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1908 __ bind(success); 1909 if (dst != obj) { 1910 __ mov(dst, obj); 1911 } 1912 } else 1913 if (code == lir_instanceof) { 1914 Register obj = op->object()->as_register(); 1915 Register dst = op->result_opr()->as_register(); 1916 Label success, failure, done; 1917 emit_typecheck_helper(op, &success, &failure, &failure); 1918 __ bind(failure); 1919 __ xorptr(dst, dst); 1920 __ jmpb(done); 1921 __ bind(success); 1922 __ movptr(dst, 1); 1923 __ bind(done); 1924 } else { 1925 ShouldNotReachHere(); 1926 } 1927 1928 } 1929 1930 1931 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1932 if (LP64_ONLY(false &&) op->code() == lir_cas_long) { 1933 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1934 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1935 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1936 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1937 Register addr = op->addr()->as_register(); 1938 __ lock(); 1939 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1940 1941 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1942 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1943 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1944 Register newval = op->new_value()->as_register(); 1945 Register cmpval = op->cmp_value()->as_register(); 1946 assert(cmpval == rax, "wrong register"); 1947 assert(newval != noreg, "new val must be register"); 1948 assert(cmpval != newval, "cmp and new values must be in different registers"); 1949 assert(cmpval != addr, "cmp and addr must be in different registers"); 1950 assert(newval != addr, "new value and addr must be in different registers"); 1951 1952 if ( op->code() == lir_cas_obj) { 1953 #ifdef _LP64 1954 if (UseCompressedOops) { 1955 __ encode_heap_oop(cmpval); 1956 __ mov(rscratch1, newval); 1957 __ encode_heap_oop(rscratch1); 1958 __ lock(); 1959 // cmpval (rax) is implicitly used by this instruction 1960 __ cmpxchgl(rscratch1, Address(addr, 0)); 1961 } else 1962 #endif 1963 { 1964 __ lock(); 1965 __ cmpxchgptr(newval, Address(addr, 0)); 1966 } 1967 } else { 1968 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1969 __ lock(); 1970 __ cmpxchgl(newval, Address(addr, 0)); 1971 } 1972 #ifdef _LP64 1973 } else if (op->code() == lir_cas_long) { 1974 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1975 Register newval = op->new_value()->as_register_lo(); 1976 Register cmpval = op->cmp_value()->as_register_lo(); 1977 assert(cmpval == rax, "wrong register"); 1978 assert(newval != noreg, "new val must be register"); 1979 assert(cmpval != newval, "cmp and new values must be in different registers"); 1980 assert(cmpval != addr, "cmp and addr must be in different registers"); 1981 assert(newval != addr, "new value and addr must be in different registers"); 1982 __ lock(); 1983 __ cmpxchgq(newval, Address(addr, 0)); 1984 #endif // _LP64 1985 } else { 1986 Unimplemented(); 1987 } 1988 } 1989 1990 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 1991 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 1992 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86"); 1993 1994 Assembler::Condition acond, ncond; 1995 switch (condition) { 1996 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1997 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1998 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1999 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 2000 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 2001 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 2002 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 2003 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 2004 default: acond = Assembler::equal; ncond = Assembler::notEqual; 2005 ShouldNotReachHere(); 2006 } 2007 2008 if (opr1->is_cpu_register()) { 2009 reg2reg(opr1, result); 2010 } else if (opr1->is_stack()) { 2011 stack2reg(opr1, result, result->type()); 2012 } else if (opr1->is_constant()) { 2013 const2reg(opr1, result, lir_patch_none, nullptr); 2014 } else { 2015 ShouldNotReachHere(); 2016 } 2017 2018 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2019 // optimized version that does not require a branch 2020 if (opr2->is_single_cpu()) { 2021 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2022 __ cmov(ncond, result->as_register(), opr2->as_register()); 2023 } else if (opr2->is_double_cpu()) { 2024 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2025 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2026 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2027 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2028 } else if (opr2->is_single_stack()) { 2029 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2030 } else if (opr2->is_double_stack()) { 2031 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2032 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2033 } else { 2034 ShouldNotReachHere(); 2035 } 2036 2037 } else { 2038 Label skip; 2039 __ jccb(acond, skip); 2040 if (opr2->is_cpu_register()) { 2041 reg2reg(opr2, result); 2042 } else if (opr2->is_stack()) { 2043 stack2reg(opr2, result, result->type()); 2044 } else if (opr2->is_constant()) { 2045 const2reg(opr2, result, lir_patch_none, nullptr); 2046 } else { 2047 ShouldNotReachHere(); 2048 } 2049 __ bind(skip); 2050 } 2051 } 2052 2053 2054 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2055 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2056 2057 if (left->is_single_cpu()) { 2058 assert(left == dest, "left and dest must be equal"); 2059 Register lreg = left->as_register(); 2060 2061 if (right->is_single_cpu()) { 2062 // cpu register - cpu register 2063 Register rreg = right->as_register(); 2064 switch (code) { 2065 case lir_add: __ addl (lreg, rreg); break; 2066 case lir_sub: __ subl (lreg, rreg); break; 2067 case lir_mul: __ imull(lreg, rreg); break; 2068 default: ShouldNotReachHere(); 2069 } 2070 2071 } else if (right->is_stack()) { 2072 // cpu register - stack 2073 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2074 switch (code) { 2075 case lir_add: __ addl(lreg, raddr); break; 2076 case lir_sub: __ subl(lreg, raddr); break; 2077 default: ShouldNotReachHere(); 2078 } 2079 2080 } else if (right->is_constant()) { 2081 // cpu register - constant 2082 jint c = right->as_constant_ptr()->as_jint(); 2083 switch (code) { 2084 case lir_add: { 2085 __ incrementl(lreg, c); 2086 break; 2087 } 2088 case lir_sub: { 2089 __ decrementl(lreg, c); 2090 break; 2091 } 2092 default: ShouldNotReachHere(); 2093 } 2094 2095 } else { 2096 ShouldNotReachHere(); 2097 } 2098 2099 } else if (left->is_double_cpu()) { 2100 assert(left == dest, "left and dest must be equal"); 2101 Register lreg_lo = left->as_register_lo(); 2102 Register lreg_hi = left->as_register_hi(); 2103 2104 if (right->is_double_cpu()) { 2105 // cpu register - cpu register 2106 Register rreg_lo = right->as_register_lo(); 2107 Register rreg_hi = right->as_register_hi(); 2108 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2109 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2110 switch (code) { 2111 case lir_add: 2112 __ addptr(lreg_lo, rreg_lo); 2113 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2114 break; 2115 case lir_sub: 2116 __ subptr(lreg_lo, rreg_lo); 2117 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2118 break; 2119 case lir_mul: 2120 #ifdef _LP64 2121 __ imulq(lreg_lo, rreg_lo); 2122 #else 2123 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2124 __ imull(lreg_hi, rreg_lo); 2125 __ imull(rreg_hi, lreg_lo); 2126 __ addl (rreg_hi, lreg_hi); 2127 __ mull (rreg_lo); 2128 __ addl (lreg_hi, rreg_hi); 2129 #endif // _LP64 2130 break; 2131 default: 2132 ShouldNotReachHere(); 2133 } 2134 2135 } else if (right->is_constant()) { 2136 // cpu register - constant 2137 #ifdef _LP64 2138 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2139 __ movptr(r10, (intptr_t) c); 2140 switch (code) { 2141 case lir_add: 2142 __ addptr(lreg_lo, r10); 2143 break; 2144 case lir_sub: 2145 __ subptr(lreg_lo, r10); 2146 break; 2147 default: 2148 ShouldNotReachHere(); 2149 } 2150 #else 2151 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2152 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2153 switch (code) { 2154 case lir_add: 2155 __ addptr(lreg_lo, c_lo); 2156 __ adcl(lreg_hi, c_hi); 2157 break; 2158 case lir_sub: 2159 __ subptr(lreg_lo, c_lo); 2160 __ sbbl(lreg_hi, c_hi); 2161 break; 2162 default: 2163 ShouldNotReachHere(); 2164 } 2165 #endif // _LP64 2166 2167 } else { 2168 ShouldNotReachHere(); 2169 } 2170 2171 } else if (left->is_single_xmm()) { 2172 assert(left == dest, "left and dest must be equal"); 2173 XMMRegister lreg = left->as_xmm_float_reg(); 2174 2175 if (right->is_single_xmm()) { 2176 XMMRegister rreg = right->as_xmm_float_reg(); 2177 switch (code) { 2178 case lir_add: __ addss(lreg, rreg); break; 2179 case lir_sub: __ subss(lreg, rreg); break; 2180 case lir_mul: __ mulss(lreg, rreg); break; 2181 case lir_div: __ divss(lreg, rreg); break; 2182 default: ShouldNotReachHere(); 2183 } 2184 } else { 2185 Address raddr; 2186 if (right->is_single_stack()) { 2187 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2188 } else if (right->is_constant()) { 2189 // hack for now 2190 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2191 } else { 2192 ShouldNotReachHere(); 2193 } 2194 switch (code) { 2195 case lir_add: __ addss(lreg, raddr); break; 2196 case lir_sub: __ subss(lreg, raddr); break; 2197 case lir_mul: __ mulss(lreg, raddr); break; 2198 case lir_div: __ divss(lreg, raddr); break; 2199 default: ShouldNotReachHere(); 2200 } 2201 } 2202 2203 } else if (left->is_double_xmm()) { 2204 assert(left == dest, "left and dest must be equal"); 2205 2206 XMMRegister lreg = left->as_xmm_double_reg(); 2207 if (right->is_double_xmm()) { 2208 XMMRegister rreg = right->as_xmm_double_reg(); 2209 switch (code) { 2210 case lir_add: __ addsd(lreg, rreg); break; 2211 case lir_sub: __ subsd(lreg, rreg); break; 2212 case lir_mul: __ mulsd(lreg, rreg); break; 2213 case lir_div: __ divsd(lreg, rreg); break; 2214 default: ShouldNotReachHere(); 2215 } 2216 } else { 2217 Address raddr; 2218 if (right->is_double_stack()) { 2219 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2220 } else if (right->is_constant()) { 2221 // hack for now 2222 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2223 } else { 2224 ShouldNotReachHere(); 2225 } 2226 switch (code) { 2227 case lir_add: __ addsd(lreg, raddr); break; 2228 case lir_sub: __ subsd(lreg, raddr); break; 2229 case lir_mul: __ mulsd(lreg, raddr); break; 2230 case lir_div: __ divsd(lreg, raddr); break; 2231 default: ShouldNotReachHere(); 2232 } 2233 } 2234 2235 #ifndef _LP64 2236 } else if (left->is_single_fpu()) { 2237 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2238 2239 if (right->is_single_fpu()) { 2240 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2241 2242 } else { 2243 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2244 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2245 2246 Address raddr; 2247 if (right->is_single_stack()) { 2248 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2249 } else if (right->is_constant()) { 2250 address const_addr = float_constant(right->as_jfloat()); 2251 assert(const_addr != nullptr, "incorrect float/double constant maintenance"); 2252 // hack for now 2253 raddr = __ as_Address(InternalAddress(const_addr)); 2254 } else { 2255 ShouldNotReachHere(); 2256 } 2257 2258 switch (code) { 2259 case lir_add: __ fadd_s(raddr); break; 2260 case lir_sub: __ fsub_s(raddr); break; 2261 case lir_mul: __ fmul_s(raddr); break; 2262 case lir_div: __ fdiv_s(raddr); break; 2263 default: ShouldNotReachHere(); 2264 } 2265 } 2266 2267 } else if (left->is_double_fpu()) { 2268 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2269 2270 if (code == lir_mul || code == lir_div) { 2271 // Double values require special handling for strictfp mul/div on x86 2272 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1())); 2273 __ fmulp(left->fpu_regnrLo() + 1); 2274 } 2275 2276 if (right->is_double_fpu()) { 2277 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2278 2279 } else { 2280 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2281 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2282 2283 Address raddr; 2284 if (right->is_double_stack()) { 2285 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2286 } else if (right->is_constant()) { 2287 // hack for now 2288 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2289 } else { 2290 ShouldNotReachHere(); 2291 } 2292 2293 switch (code) { 2294 case lir_add: __ fadd_d(raddr); break; 2295 case lir_sub: __ fsub_d(raddr); break; 2296 case lir_mul: __ fmul_d(raddr); break; 2297 case lir_div: __ fdiv_d(raddr); break; 2298 default: ShouldNotReachHere(); 2299 } 2300 } 2301 2302 if (code == lir_mul || code == lir_div) { 2303 // Double values require special handling for strictfp mul/div on x86 2304 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2())); 2305 __ fmulp(dest->fpu_regnrLo() + 1); 2306 } 2307 #endif // !_LP64 2308 2309 } else if (left->is_single_stack() || left->is_address()) { 2310 assert(left == dest, "left and dest must be equal"); 2311 2312 Address laddr; 2313 if (left->is_single_stack()) { 2314 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2315 } else if (left->is_address()) { 2316 laddr = as_Address(left->as_address_ptr()); 2317 } else { 2318 ShouldNotReachHere(); 2319 } 2320 2321 if (right->is_single_cpu()) { 2322 Register rreg = right->as_register(); 2323 switch (code) { 2324 case lir_add: __ addl(laddr, rreg); break; 2325 case lir_sub: __ subl(laddr, rreg); break; 2326 default: ShouldNotReachHere(); 2327 } 2328 } else if (right->is_constant()) { 2329 jint c = right->as_constant_ptr()->as_jint(); 2330 switch (code) { 2331 case lir_add: { 2332 __ incrementl(laddr, c); 2333 break; 2334 } 2335 case lir_sub: { 2336 __ decrementl(laddr, c); 2337 break; 2338 } 2339 default: ShouldNotReachHere(); 2340 } 2341 } else { 2342 ShouldNotReachHere(); 2343 } 2344 2345 } else { 2346 ShouldNotReachHere(); 2347 } 2348 } 2349 2350 #ifndef _LP64 2351 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2352 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2353 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2354 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2355 2356 bool left_is_tos = (left_index == 0); 2357 bool dest_is_tos = (dest_index == 0); 2358 int non_tos_index = (left_is_tos ? right_index : left_index); 2359 2360 switch (code) { 2361 case lir_add: 2362 if (pop_fpu_stack) __ faddp(non_tos_index); 2363 else if (dest_is_tos) __ fadd (non_tos_index); 2364 else __ fadda(non_tos_index); 2365 break; 2366 2367 case lir_sub: 2368 if (left_is_tos) { 2369 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2370 else if (dest_is_tos) __ fsub (non_tos_index); 2371 else __ fsubra(non_tos_index); 2372 } else { 2373 if (pop_fpu_stack) __ fsubp (non_tos_index); 2374 else if (dest_is_tos) __ fsubr (non_tos_index); 2375 else __ fsuba (non_tos_index); 2376 } 2377 break; 2378 2379 case lir_mul: 2380 if (pop_fpu_stack) __ fmulp(non_tos_index); 2381 else if (dest_is_tos) __ fmul (non_tos_index); 2382 else __ fmula(non_tos_index); 2383 break; 2384 2385 case lir_div: 2386 if (left_is_tos) { 2387 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2388 else if (dest_is_tos) __ fdiv (non_tos_index); 2389 else __ fdivra(non_tos_index); 2390 } else { 2391 if (pop_fpu_stack) __ fdivp (non_tos_index); 2392 else if (dest_is_tos) __ fdivr (non_tos_index); 2393 else __ fdiva (non_tos_index); 2394 } 2395 break; 2396 2397 case lir_rem: 2398 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2399 __ fremr(noreg); 2400 break; 2401 2402 default: 2403 ShouldNotReachHere(); 2404 } 2405 } 2406 #endif // _LP64 2407 2408 2409 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 2410 if (value->is_double_xmm()) { 2411 switch(code) { 2412 case lir_abs : 2413 { 2414 #ifdef _LP64 2415 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 2416 assert(tmp->is_valid(), "need temporary"); 2417 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2); 2418 } else 2419 #endif 2420 { 2421 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2422 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2423 } 2424 assert(!tmp->is_valid(), "do not need temporary"); 2425 __ andpd(dest->as_xmm_double_reg(), 2426 ExternalAddress((address)double_signmask_pool), 2427 rscratch1); 2428 } 2429 } 2430 break; 2431 2432 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2433 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2434 default : ShouldNotReachHere(); 2435 } 2436 2437 #ifndef _LP64 2438 } else if (value->is_double_fpu()) { 2439 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2440 switch(code) { 2441 case lir_abs : __ fabs() ; break; 2442 case lir_sqrt : __ fsqrt(); break; 2443 default : ShouldNotReachHere(); 2444 } 2445 #endif // !_LP64 2446 } else if (code == lir_f2hf) { 2447 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 2448 } else if (code == lir_hf2f) { 2449 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register()); 2450 } else { 2451 Unimplemented(); 2452 } 2453 } 2454 2455 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2456 // assert(left->destroys_register(), "check"); 2457 if (left->is_single_cpu()) { 2458 Register reg = left->as_register(); 2459 if (right->is_constant()) { 2460 int val = right->as_constant_ptr()->as_jint(); 2461 switch (code) { 2462 case lir_logic_and: __ andl (reg, val); break; 2463 case lir_logic_or: __ orl (reg, val); break; 2464 case lir_logic_xor: __ xorl (reg, val); break; 2465 default: ShouldNotReachHere(); 2466 } 2467 } else if (right->is_stack()) { 2468 // added support for stack operands 2469 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2470 switch (code) { 2471 case lir_logic_and: __ andl (reg, raddr); break; 2472 case lir_logic_or: __ orl (reg, raddr); break; 2473 case lir_logic_xor: __ xorl (reg, raddr); break; 2474 default: ShouldNotReachHere(); 2475 } 2476 } else { 2477 Register rright = right->as_register(); 2478 switch (code) { 2479 case lir_logic_and: __ andptr (reg, rright); break; 2480 case lir_logic_or : __ orptr (reg, rright); break; 2481 case lir_logic_xor: __ xorptr (reg, rright); break; 2482 default: ShouldNotReachHere(); 2483 } 2484 } 2485 move_regs(reg, dst->as_register()); 2486 } else { 2487 Register l_lo = left->as_register_lo(); 2488 Register l_hi = left->as_register_hi(); 2489 if (right->is_constant()) { 2490 #ifdef _LP64 2491 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2492 switch (code) { 2493 case lir_logic_and: 2494 __ andq(l_lo, rscratch1); 2495 break; 2496 case lir_logic_or: 2497 __ orq(l_lo, rscratch1); 2498 break; 2499 case lir_logic_xor: 2500 __ xorq(l_lo, rscratch1); 2501 break; 2502 default: ShouldNotReachHere(); 2503 } 2504 #else 2505 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2506 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2507 switch (code) { 2508 case lir_logic_and: 2509 __ andl(l_lo, r_lo); 2510 __ andl(l_hi, r_hi); 2511 break; 2512 case lir_logic_or: 2513 __ orl(l_lo, r_lo); 2514 __ orl(l_hi, r_hi); 2515 break; 2516 case lir_logic_xor: 2517 __ xorl(l_lo, r_lo); 2518 __ xorl(l_hi, r_hi); 2519 break; 2520 default: ShouldNotReachHere(); 2521 } 2522 #endif // _LP64 2523 } else { 2524 #ifdef _LP64 2525 Register r_lo; 2526 if (is_reference_type(right->type())) { 2527 r_lo = right->as_register(); 2528 } else { 2529 r_lo = right->as_register_lo(); 2530 } 2531 #else 2532 Register r_lo = right->as_register_lo(); 2533 Register r_hi = right->as_register_hi(); 2534 assert(l_lo != r_hi, "overwriting registers"); 2535 #endif 2536 switch (code) { 2537 case lir_logic_and: 2538 __ andptr(l_lo, r_lo); 2539 NOT_LP64(__ andptr(l_hi, r_hi);) 2540 break; 2541 case lir_logic_or: 2542 __ orptr(l_lo, r_lo); 2543 NOT_LP64(__ orptr(l_hi, r_hi);) 2544 break; 2545 case lir_logic_xor: 2546 __ xorptr(l_lo, r_lo); 2547 NOT_LP64(__ xorptr(l_hi, r_hi);) 2548 break; 2549 default: ShouldNotReachHere(); 2550 } 2551 } 2552 2553 Register dst_lo = dst->as_register_lo(); 2554 Register dst_hi = dst->as_register_hi(); 2555 2556 #ifdef _LP64 2557 move_regs(l_lo, dst_lo); 2558 #else 2559 if (dst_lo == l_hi) { 2560 assert(dst_hi != l_lo, "overwriting registers"); 2561 move_regs(l_hi, dst_hi); 2562 move_regs(l_lo, dst_lo); 2563 } else { 2564 assert(dst_lo != l_hi, "overwriting registers"); 2565 move_regs(l_lo, dst_lo); 2566 move_regs(l_hi, dst_hi); 2567 } 2568 #endif // _LP64 2569 } 2570 } 2571 2572 2573 // we assume that rax, and rdx can be overwritten 2574 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2575 2576 assert(left->is_single_cpu(), "left must be register"); 2577 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2578 assert(result->is_single_cpu(), "result must be register"); 2579 2580 // assert(left->destroys_register(), "check"); 2581 // assert(right->destroys_register(), "check"); 2582 2583 Register lreg = left->as_register(); 2584 Register dreg = result->as_register(); 2585 2586 if (right->is_constant()) { 2587 jint divisor = right->as_constant_ptr()->as_jint(); 2588 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2589 if (code == lir_idiv) { 2590 assert(lreg == rax, "must be rax,"); 2591 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2592 __ cdql(); // sign extend into rdx:rax 2593 if (divisor == 2) { 2594 __ subl(lreg, rdx); 2595 } else { 2596 __ andl(rdx, divisor - 1); 2597 __ addl(lreg, rdx); 2598 } 2599 __ sarl(lreg, log2i_exact(divisor)); 2600 move_regs(lreg, dreg); 2601 } else if (code == lir_irem) { 2602 Label done; 2603 __ mov(dreg, lreg); 2604 __ andl(dreg, 0x80000000 | (divisor - 1)); 2605 __ jcc(Assembler::positive, done); 2606 __ decrement(dreg); 2607 __ orl(dreg, ~(divisor - 1)); 2608 __ increment(dreg); 2609 __ bind(done); 2610 } else { 2611 ShouldNotReachHere(); 2612 } 2613 } else { 2614 Register rreg = right->as_register(); 2615 assert(lreg == rax, "left register must be rax,"); 2616 assert(rreg != rdx, "right register must not be rdx"); 2617 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2618 2619 move_regs(lreg, rax); 2620 2621 int idivl_offset = __ corrected_idivl(rreg); 2622 if (ImplicitDiv0Checks) { 2623 add_debug_info_for_div0(idivl_offset, info); 2624 } 2625 if (code == lir_irem) { 2626 move_regs(rdx, dreg); // result is in rdx 2627 } else { 2628 move_regs(rax, dreg); 2629 } 2630 } 2631 } 2632 2633 2634 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2635 if (opr1->is_single_cpu()) { 2636 Register reg1 = opr1->as_register(); 2637 if (opr2->is_single_cpu()) { 2638 // cpu register - cpu register 2639 if (is_reference_type(opr1->type())) { 2640 __ cmpoop(reg1, opr2->as_register()); 2641 } else { 2642 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 2643 __ cmpl(reg1, opr2->as_register()); 2644 } 2645 } else if (opr2->is_stack()) { 2646 // cpu register - stack 2647 if (is_reference_type(opr1->type())) { 2648 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2649 } else { 2650 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2651 } 2652 } else if (opr2->is_constant()) { 2653 // cpu register - constant 2654 LIR_Const* c = opr2->as_constant_ptr(); 2655 if (c->type() == T_INT) { 2656 jint i = c->as_jint(); 2657 if (i == 0) { 2658 __ testl(reg1, reg1); 2659 } else { 2660 __ cmpl(reg1, i); 2661 } 2662 } else if (c->type() == T_METADATA) { 2663 // All we need for now is a comparison with null for equality. 2664 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 2665 Metadata* m = c->as_metadata(); 2666 if (m == nullptr) { 2667 __ testptr(reg1, reg1); 2668 } else { 2669 ShouldNotReachHere(); 2670 } 2671 } else if (is_reference_type(c->type())) { 2672 // In 64bit oops are single register 2673 jobject o = c->as_jobject(); 2674 if (o == nullptr) { 2675 __ testptr(reg1, reg1); 2676 } else { 2677 __ cmpoop(reg1, o, rscratch1); 2678 } 2679 } else { 2680 fatal("unexpected type: %s", basictype_to_str(c->type())); 2681 } 2682 // cpu register - address 2683 } else if (opr2->is_address()) { 2684 if (op->info() != nullptr) { 2685 add_debug_info_for_null_check_here(op->info()); 2686 } 2687 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2688 } else { 2689 ShouldNotReachHere(); 2690 } 2691 2692 } else if(opr1->is_double_cpu()) { 2693 Register xlo = opr1->as_register_lo(); 2694 Register xhi = opr1->as_register_hi(); 2695 if (opr2->is_double_cpu()) { 2696 #ifdef _LP64 2697 __ cmpptr(xlo, opr2->as_register_lo()); 2698 #else 2699 // cpu register - cpu register 2700 Register ylo = opr2->as_register_lo(); 2701 Register yhi = opr2->as_register_hi(); 2702 __ subl(xlo, ylo); 2703 __ sbbl(xhi, yhi); 2704 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2705 __ orl(xhi, xlo); 2706 } 2707 #endif // _LP64 2708 } else if (opr2->is_constant()) { 2709 // cpu register - constant 0 2710 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2711 #ifdef _LP64 2712 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2713 #else 2714 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2715 __ orl(xhi, xlo); 2716 #endif // _LP64 2717 } else { 2718 ShouldNotReachHere(); 2719 } 2720 2721 } else if (opr1->is_single_xmm()) { 2722 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2723 if (opr2->is_single_xmm()) { 2724 // xmm register - xmm register 2725 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2726 } else if (opr2->is_stack()) { 2727 // xmm register - stack 2728 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2729 } else if (opr2->is_constant()) { 2730 // xmm register - constant 2731 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2732 } else if (opr2->is_address()) { 2733 // xmm register - address 2734 if (op->info() != nullptr) { 2735 add_debug_info_for_null_check_here(op->info()); 2736 } 2737 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2738 } else { 2739 ShouldNotReachHere(); 2740 } 2741 2742 } else if (opr1->is_double_xmm()) { 2743 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2744 if (opr2->is_double_xmm()) { 2745 // xmm register - xmm register 2746 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2747 } else if (opr2->is_stack()) { 2748 // xmm register - stack 2749 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2750 } else if (opr2->is_constant()) { 2751 // xmm register - constant 2752 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2753 } else if (opr2->is_address()) { 2754 // xmm register - address 2755 if (op->info() != nullptr) { 2756 add_debug_info_for_null_check_here(op->info()); 2757 } 2758 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2759 } else { 2760 ShouldNotReachHere(); 2761 } 2762 2763 #ifndef _LP64 2764 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2765 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2766 assert(opr2->is_fpu_register(), "both must be registers"); 2767 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2768 #endif // LP64 2769 2770 } else if (opr1->is_address() && opr2->is_constant()) { 2771 LIR_Const* c = opr2->as_constant_ptr(); 2772 #ifdef _LP64 2773 if (is_reference_type(c->type())) { 2774 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2775 __ movoop(rscratch1, c->as_jobject()); 2776 } 2777 #endif // LP64 2778 if (op->info() != nullptr) { 2779 add_debug_info_for_null_check_here(op->info()); 2780 } 2781 // special case: address - constant 2782 LIR_Address* addr = opr1->as_address_ptr(); 2783 if (c->type() == T_INT) { 2784 __ cmpl(as_Address(addr), c->as_jint()); 2785 } else if (is_reference_type(c->type())) { 2786 #ifdef _LP64 2787 // %%% Make this explode if addr isn't reachable until we figure out a 2788 // better strategy by giving noreg as the temp for as_Address 2789 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2790 #else 2791 __ cmpoop(as_Address(addr), c->as_jobject()); 2792 #endif // _LP64 2793 } else { 2794 ShouldNotReachHere(); 2795 } 2796 2797 } else { 2798 ShouldNotReachHere(); 2799 } 2800 } 2801 2802 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2803 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2804 if (left->is_single_xmm()) { 2805 assert(right->is_single_xmm(), "must match"); 2806 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2807 } else if (left->is_double_xmm()) { 2808 assert(right->is_double_xmm(), "must match"); 2809 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2810 2811 } else { 2812 #ifdef _LP64 2813 ShouldNotReachHere(); 2814 #else 2815 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2816 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2817 2818 assert(left->fpu() == 0, "left must be on TOS"); 2819 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2820 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2821 #endif // LP64 2822 } 2823 } else { 2824 assert(code == lir_cmp_l2i, "check"); 2825 #ifdef _LP64 2826 Label done; 2827 Register dest = dst->as_register(); 2828 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2829 __ movl(dest, -1); 2830 __ jccb(Assembler::less, done); 2831 __ setb(Assembler::notZero, dest); 2832 __ movzbl(dest, dest); 2833 __ bind(done); 2834 #else 2835 __ lcmp2int(left->as_register_hi(), 2836 left->as_register_lo(), 2837 right->as_register_hi(), 2838 right->as_register_lo()); 2839 move_regs(left->as_register_hi(), dst->as_register()); 2840 #endif // _LP64 2841 } 2842 } 2843 2844 2845 void LIR_Assembler::align_call(LIR_Code code) { 2846 // make sure that the displacement word of the call ends up word aligned 2847 int offset = __ offset(); 2848 switch (code) { 2849 case lir_static_call: 2850 case lir_optvirtual_call: 2851 case lir_dynamic_call: 2852 offset += NativeCall::displacement_offset; 2853 break; 2854 case lir_icvirtual_call: 2855 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2856 break; 2857 default: ShouldNotReachHere(); 2858 } 2859 __ align(BytesPerWord, offset); 2860 } 2861 2862 2863 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2864 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2865 "must be aligned"); 2866 __ call(AddressLiteral(op->addr(), rtype)); 2867 add_call_info(code_offset(), op->info()); 2868 __ post_call_nop(); 2869 } 2870 2871 2872 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2873 __ ic_call(op->addr()); 2874 add_call_info(code_offset(), op->info()); 2875 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2876 "must be aligned"); 2877 __ post_call_nop(); 2878 } 2879 2880 2881 void LIR_Assembler::emit_static_call_stub() { 2882 address call_pc = __ pc(); 2883 address stub = __ start_a_stub(call_stub_size()); 2884 if (stub == nullptr) { 2885 bailout("static call stub overflow"); 2886 return; 2887 } 2888 2889 int start = __ offset(); 2890 2891 // make sure that the displacement word of the call ends up word aligned 2892 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2893 __ relocate(static_stub_Relocation::spec(call_pc)); 2894 __ mov_metadata(rbx, (Metadata*)nullptr); 2895 // must be set to -1 at code generation time 2896 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned"); 2897 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2898 __ jump(RuntimeAddress(__ pc())); 2899 2900 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2901 __ end_a_stub(); 2902 } 2903 2904 2905 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2906 assert(exceptionOop->as_register() == rax, "must match"); 2907 assert(exceptionPC->as_register() == rdx, "must match"); 2908 2909 // exception object is not added to oop map by LinearScan 2910 // (LinearScan assumes that no oops are in fixed registers) 2911 info->add_register_oop(exceptionOop); 2912 Runtime1::StubID unwind_id; 2913 2914 // get current pc information 2915 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2916 int pc_for_athrow_offset = __ offset(); 2917 InternalAddress pc_for_athrow(__ pc()); 2918 __ lea(exceptionPC->as_register(), pc_for_athrow); 2919 add_call_info(pc_for_athrow_offset, info); // for exception handler 2920 2921 __ verify_not_null_oop(rax); 2922 // search an exception handler (rax: exception oop, rdx: throwing pc) 2923 if (compilation()->has_fpu_code()) { 2924 unwind_id = Runtime1::handle_exception_id; 2925 } else { 2926 unwind_id = Runtime1::handle_exception_nofpu_id; 2927 } 2928 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2929 2930 // enough room for two byte trap 2931 __ nop(); 2932 } 2933 2934 2935 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2936 assert(exceptionOop->as_register() == rax, "must match"); 2937 2938 __ jmp(_unwind_handler_entry); 2939 } 2940 2941 2942 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2943 2944 // optimized version for linear scan: 2945 // * count must be already in ECX (guaranteed by LinearScan) 2946 // * left and dest must be equal 2947 // * tmp must be unused 2948 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2949 assert(left == dest, "left and dest must be equal"); 2950 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2951 2952 if (left->is_single_cpu()) { 2953 Register value = left->as_register(); 2954 assert(value != SHIFT_count, "left cannot be ECX"); 2955 2956 switch (code) { 2957 case lir_shl: __ shll(value); break; 2958 case lir_shr: __ sarl(value); break; 2959 case lir_ushr: __ shrl(value); break; 2960 default: ShouldNotReachHere(); 2961 } 2962 } else if (left->is_double_cpu()) { 2963 Register lo = left->as_register_lo(); 2964 Register hi = left->as_register_hi(); 2965 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2966 #ifdef _LP64 2967 switch (code) { 2968 case lir_shl: __ shlptr(lo); break; 2969 case lir_shr: __ sarptr(lo); break; 2970 case lir_ushr: __ shrptr(lo); break; 2971 default: ShouldNotReachHere(); 2972 } 2973 #else 2974 2975 switch (code) { 2976 case lir_shl: __ lshl(hi, lo); break; 2977 case lir_shr: __ lshr(hi, lo, true); break; 2978 case lir_ushr: __ lshr(hi, lo, false); break; 2979 default: ShouldNotReachHere(); 2980 } 2981 #endif // LP64 2982 } else { 2983 ShouldNotReachHere(); 2984 } 2985 } 2986 2987 2988 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2989 if (dest->is_single_cpu()) { 2990 // first move left into dest so that left is not destroyed by the shift 2991 Register value = dest->as_register(); 2992 count = count & 0x1F; // Java spec 2993 2994 move_regs(left->as_register(), value); 2995 switch (code) { 2996 case lir_shl: __ shll(value, count); break; 2997 case lir_shr: __ sarl(value, count); break; 2998 case lir_ushr: __ shrl(value, count); break; 2999 default: ShouldNotReachHere(); 3000 } 3001 } else if (dest->is_double_cpu()) { 3002 #ifndef _LP64 3003 Unimplemented(); 3004 #else 3005 // first move left into dest so that left is not destroyed by the shift 3006 Register value = dest->as_register_lo(); 3007 count = count & 0x1F; // Java spec 3008 3009 move_regs(left->as_register_lo(), value); 3010 switch (code) { 3011 case lir_shl: __ shlptr(value, count); break; 3012 case lir_shr: __ sarptr(value, count); break; 3013 case lir_ushr: __ shrptr(value, count); break; 3014 default: ShouldNotReachHere(); 3015 } 3016 #endif // _LP64 3017 } else { 3018 ShouldNotReachHere(); 3019 } 3020 } 3021 3022 3023 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3024 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3025 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3026 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3027 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3028 } 3029 3030 3031 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3032 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3033 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3034 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3035 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3036 } 3037 3038 3039 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3040 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3041 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3042 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3043 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1); 3044 } 3045 3046 3047 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3048 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3049 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3050 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3051 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1); 3052 } 3053 3054 3055 // This code replaces a call to arraycopy; no exception may 3056 // be thrown in this code, they must be thrown in the System.arraycopy 3057 // activation frame; we could save some checks if this would not be the case 3058 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3059 ciArrayKlass* default_type = op->expected_type(); 3060 Register src = op->src()->as_register(); 3061 Register dst = op->dst()->as_register(); 3062 Register src_pos = op->src_pos()->as_register(); 3063 Register dst_pos = op->dst_pos()->as_register(); 3064 Register length = op->length()->as_register(); 3065 Register tmp = op->tmp()->as_register(); 3066 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3067 3068 CodeStub* stub = op->stub(); 3069 int flags = op->flags(); 3070 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL; 3071 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 3072 3073 // if we don't know anything, just go through the generic arraycopy 3074 if (default_type == nullptr) { 3075 // save outgoing arguments on stack in case call to System.arraycopy is needed 3076 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3077 // for interpreter calling conventions. Now we have to do it in new style conventions. 3078 // For the moment until C1 gets the new register allocator I just force all the 3079 // args to the right place (except the register args) and then on the back side 3080 // reload the register args properly if we go slow path. Yuck 3081 3082 // These are proper for the calling convention 3083 store_parameter(length, 2); 3084 store_parameter(dst_pos, 1); 3085 store_parameter(dst, 0); 3086 3087 // these are just temporary placements until we need to reload 3088 store_parameter(src_pos, 3); 3089 store_parameter(src, 4); 3090 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3091 3092 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3093 assert(copyfunc_addr != nullptr, "generic arraycopy stub required"); 3094 3095 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3096 #ifdef _LP64 3097 // The arguments are in java calling convention so we can trivially shift them to C 3098 // convention 3099 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3100 __ mov(c_rarg0, j_rarg0); 3101 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3102 __ mov(c_rarg1, j_rarg1); 3103 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3104 __ mov(c_rarg2, j_rarg2); 3105 assert_different_registers(c_rarg3, j_rarg4); 3106 __ mov(c_rarg3, j_rarg3); 3107 #ifdef _WIN64 3108 // Allocate abi space for args but be sure to keep stack aligned 3109 __ subptr(rsp, 6*wordSize); 3110 store_parameter(j_rarg4, 4); 3111 #ifndef PRODUCT 3112 if (PrintC1Statistics) { 3113 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3114 } 3115 #endif 3116 __ call(RuntimeAddress(copyfunc_addr)); 3117 __ addptr(rsp, 6*wordSize); 3118 #else 3119 __ mov(c_rarg4, j_rarg4); 3120 #ifndef PRODUCT 3121 if (PrintC1Statistics) { 3122 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3123 } 3124 #endif 3125 __ call(RuntimeAddress(copyfunc_addr)); 3126 #endif // _WIN64 3127 #else 3128 __ push(length); 3129 __ push(dst_pos); 3130 __ push(dst); 3131 __ push(src_pos); 3132 __ push(src); 3133 3134 #ifndef PRODUCT 3135 if (PrintC1Statistics) { 3136 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3137 } 3138 #endif 3139 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3140 3141 #endif // _LP64 3142 3143 __ testl(rax, rax); 3144 __ jcc(Assembler::equal, *stub->continuation()); 3145 3146 __ mov(tmp, rax); 3147 __ xorl(tmp, -1); 3148 3149 // Reload values from the stack so they are where the stub 3150 // expects them. 3151 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3152 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3153 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3154 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3155 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3156 3157 __ subl(length, tmp); 3158 __ addl(src_pos, tmp); 3159 __ addl(dst_pos, tmp); 3160 __ jmp(*stub->entry()); 3161 3162 __ bind(*stub->continuation()); 3163 return; 3164 } 3165 3166 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3167 3168 int elem_size = type2aelembytes(basic_type); 3169 Address::ScaleFactor scale; 3170 3171 switch (elem_size) { 3172 case 1 : 3173 scale = Address::times_1; 3174 break; 3175 case 2 : 3176 scale = Address::times_2; 3177 break; 3178 case 4 : 3179 scale = Address::times_4; 3180 break; 3181 case 8 : 3182 scale = Address::times_8; 3183 break; 3184 default: 3185 scale = Address::no_scale; 3186 ShouldNotReachHere(); 3187 } 3188 3189 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3190 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3191 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3192 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3193 3194 // length and pos's are all sign extended at this point on 64bit 3195 3196 // test for null 3197 if (flags & LIR_OpArrayCopy::src_null_check) { 3198 __ testptr(src, src); 3199 __ jcc(Assembler::zero, *stub->entry()); 3200 } 3201 if (flags & LIR_OpArrayCopy::dst_null_check) { 3202 __ testptr(dst, dst); 3203 __ jcc(Assembler::zero, *stub->entry()); 3204 } 3205 3206 // If the compiler was not able to prove that exact type of the source or the destination 3207 // of the arraycopy is an array type, check at runtime if the source or the destination is 3208 // an instance type. 3209 if (flags & LIR_OpArrayCopy::type_check) { 3210 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3211 __ load_klass(tmp, dst, tmp_load_klass); 3212 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3213 __ jcc(Assembler::greaterEqual, *stub->entry()); 3214 } 3215 3216 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3217 __ load_klass(tmp, src, tmp_load_klass); 3218 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3219 __ jcc(Assembler::greaterEqual, *stub->entry()); 3220 } 3221 } 3222 3223 // check if negative 3224 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3225 __ testl(src_pos, src_pos); 3226 __ jcc(Assembler::less, *stub->entry()); 3227 } 3228 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3229 __ testl(dst_pos, dst_pos); 3230 __ jcc(Assembler::less, *stub->entry()); 3231 } 3232 3233 if (flags & LIR_OpArrayCopy::src_range_check) { 3234 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3235 __ cmpl(tmp, src_length_addr); 3236 __ jcc(Assembler::above, *stub->entry()); 3237 } 3238 if (flags & LIR_OpArrayCopy::dst_range_check) { 3239 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3240 __ cmpl(tmp, dst_length_addr); 3241 __ jcc(Assembler::above, *stub->entry()); 3242 } 3243 3244 if (flags & LIR_OpArrayCopy::length_positive_check) { 3245 __ testl(length, length); 3246 __ jcc(Assembler::less, *stub->entry()); 3247 } 3248 3249 #ifdef _LP64 3250 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3251 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3252 #endif 3253 3254 if (flags & LIR_OpArrayCopy::type_check) { 3255 // We don't know the array types are compatible 3256 if (basic_type != T_OBJECT) { 3257 // Simple test for basic type arrays 3258 if (UseCompressedClassPointers) { 3259 __ movl(tmp, src_klass_addr); 3260 __ cmpl(tmp, dst_klass_addr); 3261 } else { 3262 __ movptr(tmp, src_klass_addr); 3263 __ cmpptr(tmp, dst_klass_addr); 3264 } 3265 __ jcc(Assembler::notEqual, *stub->entry()); 3266 } else { 3267 // For object arrays, if src is a sub class of dst then we can 3268 // safely do the copy. 3269 Label cont, slow; 3270 3271 __ push(src); 3272 __ push(dst); 3273 3274 __ load_klass(src, src, tmp_load_klass); 3275 __ load_klass(dst, dst, tmp_load_klass); 3276 3277 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr); 3278 3279 __ push(src); 3280 __ push(dst); 3281 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3282 __ pop(dst); 3283 __ pop(src); 3284 3285 __ testl(src, src); 3286 __ jcc(Assembler::notEqual, cont); 3287 3288 __ bind(slow); 3289 __ pop(dst); 3290 __ pop(src); 3291 3292 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3293 if (copyfunc_addr != nullptr) { // use stub if available 3294 // src is not a sub class of dst so we have to do a 3295 // per-element check. 3296 3297 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3298 if ((flags & mask) != mask) { 3299 // Check that at least both of them object arrays. 3300 assert(flags & mask, "one of the two should be known to be an object array"); 3301 3302 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3303 __ load_klass(tmp, src, tmp_load_klass); 3304 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3305 __ load_klass(tmp, dst, tmp_load_klass); 3306 } 3307 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3308 Address klass_lh_addr(tmp, lh_offset); 3309 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3310 __ cmpl(klass_lh_addr, objArray_lh); 3311 __ jcc(Assembler::notEqual, *stub->entry()); 3312 } 3313 3314 // Spill because stubs can use any register they like and it's 3315 // easier to restore just those that we care about. 3316 store_parameter(dst, 0); 3317 store_parameter(dst_pos, 1); 3318 store_parameter(length, 2); 3319 store_parameter(src_pos, 3); 3320 store_parameter(src, 4); 3321 3322 #ifndef _LP64 3323 __ movptr(tmp, dst_klass_addr); 3324 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3325 __ push(tmp); 3326 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3327 __ push(tmp); 3328 __ push(length); 3329 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3330 __ push(tmp); 3331 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3332 __ push(tmp); 3333 3334 __ call_VM_leaf(copyfunc_addr, 5); 3335 #else 3336 __ movl2ptr(length, length); //higher 32bits must be null 3337 3338 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3339 assert_different_registers(c_rarg0, dst, dst_pos, length); 3340 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3341 assert_different_registers(c_rarg1, dst, length); 3342 3343 __ mov(c_rarg2, length); 3344 assert_different_registers(c_rarg2, dst); 3345 3346 #ifdef _WIN64 3347 // Allocate abi space for args but be sure to keep stack aligned 3348 __ subptr(rsp, 6*wordSize); 3349 __ load_klass(c_rarg3, dst, tmp_load_klass); 3350 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3351 store_parameter(c_rarg3, 4); 3352 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3353 __ call(RuntimeAddress(copyfunc_addr)); 3354 __ addptr(rsp, 6*wordSize); 3355 #else 3356 __ load_klass(c_rarg4, dst, tmp_load_klass); 3357 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3358 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3359 __ call(RuntimeAddress(copyfunc_addr)); 3360 #endif 3361 3362 #endif 3363 3364 #ifndef PRODUCT 3365 if (PrintC1Statistics) { 3366 Label failed; 3367 __ testl(rax, rax); 3368 __ jcc(Assembler::notZero, failed); 3369 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1); 3370 __ bind(failed); 3371 } 3372 #endif 3373 3374 __ testl(rax, rax); 3375 __ jcc(Assembler::zero, *stub->continuation()); 3376 3377 #ifndef PRODUCT 3378 if (PrintC1Statistics) { 3379 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1); 3380 } 3381 #endif 3382 3383 __ mov(tmp, rax); 3384 3385 __ xorl(tmp, -1); 3386 3387 // Restore previously spilled arguments 3388 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3389 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3390 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3391 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3392 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3393 3394 3395 __ subl(length, tmp); 3396 __ addl(src_pos, tmp); 3397 __ addl(dst_pos, tmp); 3398 } 3399 3400 __ jmp(*stub->entry()); 3401 3402 __ bind(cont); 3403 __ pop(dst); 3404 __ pop(src); 3405 } 3406 } 3407 3408 #ifdef ASSERT 3409 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3410 // Sanity check the known type with the incoming class. For the 3411 // primitive case the types must match exactly with src.klass and 3412 // dst.klass each exactly matching the default type. For the 3413 // object array case, if no type check is needed then either the 3414 // dst type is exactly the expected type and the src type is a 3415 // subtype which we can't check or src is the same array as dst 3416 // but not necessarily exactly of type default_type. 3417 Label known_ok, halt; 3418 __ mov_metadata(tmp, default_type->constant_encoding()); 3419 #ifdef _LP64 3420 if (UseCompressedClassPointers) { 3421 __ encode_klass_not_null(tmp, rscratch1); 3422 } 3423 #endif 3424 3425 if (basic_type != T_OBJECT) { 3426 3427 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3428 else __ cmpptr(tmp, dst_klass_addr); 3429 __ jcc(Assembler::notEqual, halt); 3430 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3431 else __ cmpptr(tmp, src_klass_addr); 3432 __ jcc(Assembler::equal, known_ok); 3433 } else { 3434 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3435 else __ cmpptr(tmp, dst_klass_addr); 3436 __ jcc(Assembler::equal, known_ok); 3437 __ cmpptr(src, dst); 3438 __ jcc(Assembler::equal, known_ok); 3439 } 3440 __ bind(halt); 3441 __ stop("incorrect type information in arraycopy"); 3442 __ bind(known_ok); 3443 } 3444 #endif 3445 3446 #ifndef PRODUCT 3447 if (PrintC1Statistics) { 3448 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1); 3449 } 3450 #endif 3451 3452 #ifdef _LP64 3453 assert_different_registers(c_rarg0, dst, dst_pos, length); 3454 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3455 assert_different_registers(c_rarg1, length); 3456 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3457 __ mov(c_rarg2, length); 3458 3459 #else 3460 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3461 store_parameter(tmp, 0); 3462 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3463 store_parameter(tmp, 1); 3464 store_parameter(length, 2); 3465 #endif // _LP64 3466 3467 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3468 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3469 const char *name; 3470 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3471 __ call_VM_leaf(entry, 0); 3472 3473 __ bind(*stub->continuation()); 3474 } 3475 3476 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3477 assert(op->crc()->is_single_cpu(), "crc must be register"); 3478 assert(op->val()->is_single_cpu(), "byte value must be register"); 3479 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3480 Register crc = op->crc()->as_register(); 3481 Register val = op->val()->as_register(); 3482 Register res = op->result_opr()->as_register(); 3483 3484 assert_different_registers(val, crc, res); 3485 3486 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3487 __ notl(crc); // ~crc 3488 __ update_byte_crc32(crc, val, res); 3489 __ notl(crc); // ~crc 3490 __ mov(res, crc); 3491 } 3492 3493 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3494 Register obj = op->obj_opr()->as_register(); // may not be an oop 3495 Register hdr = op->hdr_opr()->as_register(); 3496 Register lock = op->lock_opr()->as_register(); 3497 if (LockingMode == LM_MONITOR) { 3498 if (op->info() != nullptr) { 3499 add_debug_info_for_null_check_here(op->info()); 3500 __ null_check(obj); 3501 } 3502 __ jmp(*op->stub()->entry()); 3503 } else if (op->code() == lir_lock) { 3504 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3505 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg; 3506 // add debug info for NullPointerException only if one is possible 3507 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry()); 3508 if (op->info() != nullptr) { 3509 add_debug_info_for_null_check(null_check_offset, op->info()); 3510 } 3511 // done 3512 } else if (op->code() == lir_unlock) { 3513 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3514 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3515 } else { 3516 Unimplemented(); 3517 } 3518 __ bind(*op->stub()->continuation()); 3519 } 3520 3521 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 3522 Register obj = op->obj()->as_pointer_register(); 3523 Register result = op->result_opr()->as_pointer_register(); 3524 3525 CodeEmitInfo* info = op->info(); 3526 if (info != nullptr) { 3527 add_debug_info_for_null_check_here(info); 3528 } 3529 3530 #ifdef _LP64 3531 if (UseCompressedClassPointers) { 3532 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes())); 3533 __ decode_klass_not_null(result, rscratch1); 3534 } else 3535 #endif 3536 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes())); 3537 } 3538 3539 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3540 ciMethod* method = op->profiled_method(); 3541 int bci = op->profiled_bci(); 3542 ciMethod* callee = op->profiled_callee(); 3543 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3544 3545 // Update counter for all call types 3546 ciMethodData* md = method->method_data_or_null(); 3547 assert(md != nullptr, "Sanity"); 3548 ciProfileData* data = md->bci_to_data(bci); 3549 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls"); 3550 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3551 Register mdo = op->mdo()->as_register(); 3552 __ mov_metadata(mdo, md->constant_encoding()); 3553 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3554 // Perform additional virtual call profiling for invokevirtual and 3555 // invokeinterface bytecodes 3556 if (op->should_profile_receiver_type()) { 3557 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3558 Register recv = op->recv()->as_register(); 3559 assert_different_registers(mdo, recv); 3560 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3561 ciKlass* known_klass = op->known_holder(); 3562 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) { 3563 // We know the type that will be seen at this call site; we can 3564 // statically update the MethodData* rather than needing to do 3565 // dynamic tests on the receiver type 3566 3567 // NOTE: we should probably put a lock around this search to 3568 // avoid collisions by concurrent compilations 3569 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3570 uint i; 3571 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3572 ciKlass* receiver = vc_data->receiver(i); 3573 if (known_klass->equals(receiver)) { 3574 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3575 __ addptr(data_addr, DataLayout::counter_increment); 3576 return; 3577 } 3578 } 3579 3580 // Receiver type not found in profile data; select an empty slot 3581 3582 // Note that this is less efficient than it should be because it 3583 // always does a write to the receiver part of the 3584 // VirtualCallData rather than just the first time 3585 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3586 ciKlass* receiver = vc_data->receiver(i); 3587 if (receiver == nullptr) { 3588 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3589 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1); 3590 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3591 __ addptr(data_addr, DataLayout::counter_increment); 3592 return; 3593 } 3594 } 3595 } else { 3596 __ load_klass(recv, recv, tmp_load_klass); 3597 Label update_done; 3598 type_profile_helper(mdo, md, data, recv, &update_done); 3599 // Receiver did not match any saved receiver and there is no empty row for it. 3600 // Increment total counter to indicate polymorphic case. 3601 __ addptr(counter_addr, DataLayout::counter_increment); 3602 3603 __ bind(update_done); 3604 } 3605 } else { 3606 // Static call 3607 __ addptr(counter_addr, DataLayout::counter_increment); 3608 } 3609 } 3610 3611 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3612 Register obj = op->obj()->as_register(); 3613 Register tmp = op->tmp()->as_pointer_register(); 3614 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3615 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3616 ciKlass* exact_klass = op->exact_klass(); 3617 intptr_t current_klass = op->current_klass(); 3618 bool not_null = op->not_null(); 3619 bool no_conflict = op->no_conflict(); 3620 3621 Label update, next, none; 3622 3623 bool do_null = !not_null; 3624 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3625 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3626 3627 assert(do_null || do_update, "why are we here?"); 3628 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3629 3630 __ verify_oop(obj); 3631 3632 #ifdef ASSERT 3633 if (obj == tmp) { 3634 #ifdef _LP64 3635 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index()); 3636 #else 3637 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index()); 3638 #endif 3639 } else { 3640 #ifdef _LP64 3641 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index()); 3642 #else 3643 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index()); 3644 #endif 3645 } 3646 #endif 3647 if (do_null) { 3648 __ testptr(obj, obj); 3649 __ jccb(Assembler::notZero, update); 3650 if (!TypeEntries::was_null_seen(current_klass)) { 3651 __ testptr(mdo_addr, TypeEntries::null_seen); 3652 #ifndef ASSERT 3653 __ jccb(Assembler::notZero, next); // already set 3654 #else 3655 __ jcc(Assembler::notZero, next); // already set 3656 #endif 3657 // atomic update to prevent overwriting Klass* with 0 3658 __ lock(); 3659 __ orptr(mdo_addr, TypeEntries::null_seen); 3660 } 3661 if (do_update) { 3662 #ifndef ASSERT 3663 __ jmpb(next); 3664 } 3665 #else 3666 __ jmp(next); 3667 } 3668 } else { 3669 __ testptr(obj, obj); 3670 __ jcc(Assembler::notZero, update); 3671 __ stop("unexpected null obj"); 3672 #endif 3673 } 3674 3675 __ bind(update); 3676 3677 if (do_update) { 3678 #ifdef ASSERT 3679 if (exact_klass != nullptr) { 3680 Label ok; 3681 __ load_klass(tmp, obj, tmp_load_klass); 3682 __ push(tmp); 3683 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3684 __ cmpptr(tmp, Address(rsp, 0)); 3685 __ jcc(Assembler::equal, ok); 3686 __ stop("exact klass and actual klass differ"); 3687 __ bind(ok); 3688 __ pop(tmp); 3689 } 3690 #endif 3691 if (!no_conflict) { 3692 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) { 3693 if (exact_klass != nullptr) { 3694 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3695 } else { 3696 __ load_klass(tmp, obj, tmp_load_klass); 3697 } 3698 #ifdef _LP64 3699 __ mov(rscratch1, tmp); // save original value before XOR 3700 #endif 3701 __ xorptr(tmp, mdo_addr); 3702 __ testptr(tmp, TypeEntries::type_klass_mask); 3703 // klass seen before, nothing to do. The unknown bit may have been 3704 // set already but no need to check. 3705 __ jccb(Assembler::zero, next); 3706 3707 __ testptr(tmp, TypeEntries::type_unknown); 3708 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3709 3710 if (TypeEntries::is_type_none(current_klass)) { 3711 __ testptr(mdo_addr, TypeEntries::type_mask); 3712 __ jccb(Assembler::zero, none); 3713 #ifdef _LP64 3714 // There is a chance that the checks above (re-reading profiling 3715 // data from memory) fail if another thread has just set the 3716 // profiling to this obj's klass 3717 __ mov(tmp, rscratch1); // get back original value before XOR 3718 __ xorptr(tmp, mdo_addr); 3719 __ testptr(tmp, TypeEntries::type_klass_mask); 3720 __ jccb(Assembler::zero, next); 3721 #endif 3722 } 3723 } else { 3724 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 3725 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3726 3727 __ testptr(mdo_addr, TypeEntries::type_unknown); 3728 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3729 } 3730 3731 // different than before. Cannot keep accurate profile. 3732 __ orptr(mdo_addr, TypeEntries::type_unknown); 3733 3734 if (TypeEntries::is_type_none(current_klass)) { 3735 __ jmpb(next); 3736 3737 __ bind(none); 3738 // first time here. Set profile type. 3739 __ movptr(mdo_addr, tmp); 3740 #ifdef ASSERT 3741 __ andptr(tmp, TypeEntries::type_klass_mask); 3742 __ verify_klass_ptr(tmp); 3743 #endif 3744 } 3745 } else { 3746 // There's a single possible klass at this profile point 3747 assert(exact_klass != nullptr, "should be"); 3748 if (TypeEntries::is_type_none(current_klass)) { 3749 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3750 __ xorptr(tmp, mdo_addr); 3751 __ testptr(tmp, TypeEntries::type_klass_mask); 3752 #ifdef ASSERT 3753 __ jcc(Assembler::zero, next); 3754 3755 { 3756 Label ok; 3757 __ push(tmp); 3758 __ testptr(mdo_addr, TypeEntries::type_mask); 3759 __ jcc(Assembler::zero, ok); 3760 // may have been set by another thread 3761 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3762 __ xorptr(tmp, mdo_addr); 3763 __ testptr(tmp, TypeEntries::type_mask); 3764 __ jcc(Assembler::zero, ok); 3765 3766 __ stop("unexpected profiling mismatch"); 3767 __ bind(ok); 3768 __ pop(tmp); 3769 } 3770 #else 3771 __ jccb(Assembler::zero, next); 3772 #endif 3773 // first time here. Set profile type. 3774 __ movptr(mdo_addr, tmp); 3775 #ifdef ASSERT 3776 __ andptr(tmp, TypeEntries::type_klass_mask); 3777 __ verify_klass_ptr(tmp); 3778 #endif 3779 } else { 3780 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 3781 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3782 3783 __ testptr(mdo_addr, TypeEntries::type_unknown); 3784 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3785 3786 __ orptr(mdo_addr, TypeEntries::type_unknown); 3787 } 3788 } 3789 } 3790 __ bind(next); 3791 } 3792 3793 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3794 Unimplemented(); 3795 } 3796 3797 3798 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3799 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3800 } 3801 3802 3803 void LIR_Assembler::align_backward_branch_target() { 3804 __ align(BytesPerWord); 3805 } 3806 3807 3808 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 3809 if (left->is_single_cpu()) { 3810 __ negl(left->as_register()); 3811 move_regs(left->as_register(), dest->as_register()); 3812 3813 } else if (left->is_double_cpu()) { 3814 Register lo = left->as_register_lo(); 3815 #ifdef _LP64 3816 Register dst = dest->as_register_lo(); 3817 __ movptr(dst, lo); 3818 __ negptr(dst); 3819 #else 3820 Register hi = left->as_register_hi(); 3821 __ lneg(hi, lo); 3822 if (dest->as_register_lo() == hi) { 3823 assert(dest->as_register_hi() != lo, "destroying register"); 3824 move_regs(hi, dest->as_register_hi()); 3825 move_regs(lo, dest->as_register_lo()); 3826 } else { 3827 move_regs(lo, dest->as_register_lo()); 3828 move_regs(hi, dest->as_register_hi()); 3829 } 3830 #endif // _LP64 3831 3832 } else if (dest->is_single_xmm()) { 3833 #ifdef _LP64 3834 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3835 assert(tmp->is_valid(), "need temporary"); 3836 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 3837 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2); 3838 } 3839 else 3840 #endif 3841 { 3842 assert(!tmp->is_valid(), "do not need temporary"); 3843 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3844 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3845 } 3846 __ xorps(dest->as_xmm_float_reg(), 3847 ExternalAddress((address)float_signflip_pool), 3848 rscratch1); 3849 } 3850 } else if (dest->is_double_xmm()) { 3851 #ifdef _LP64 3852 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3853 assert(tmp->is_valid(), "need temporary"); 3854 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg()); 3855 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2); 3856 } 3857 else 3858 #endif 3859 { 3860 assert(!tmp->is_valid(), "do not need temporary"); 3861 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3862 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3863 } 3864 __ xorpd(dest->as_xmm_double_reg(), 3865 ExternalAddress((address)double_signflip_pool), 3866 rscratch1); 3867 } 3868 #ifndef _LP64 3869 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3870 assert(left->fpu() == 0, "arg must be on TOS"); 3871 assert(dest->fpu() == 0, "dest must be TOS"); 3872 __ fchs(); 3873 #endif // !_LP64 3874 3875 } else { 3876 ShouldNotReachHere(); 3877 } 3878 } 3879 3880 3881 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 3882 assert(src->is_address(), "must be an address"); 3883 assert(dest->is_register(), "must be a register"); 3884 3885 PatchingStub* patch = nullptr; 3886 if (patch_code != lir_patch_none) { 3887 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 3888 } 3889 3890 Register reg = dest->as_pointer_register(); 3891 LIR_Address* addr = src->as_address_ptr(); 3892 __ lea(reg, as_Address(addr)); 3893 3894 if (patch != nullptr) { 3895 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 3896 } 3897 } 3898 3899 3900 3901 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3902 assert(!tmp->is_valid(), "don't need temporary"); 3903 __ call(RuntimeAddress(dest)); 3904 if (info != nullptr) { 3905 add_call_info_here(info); 3906 } 3907 __ post_call_nop(); 3908 } 3909 3910 3911 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3912 assert(type == T_LONG, "only for volatile long fields"); 3913 3914 if (info != nullptr) { 3915 add_debug_info_for_null_check_here(info); 3916 } 3917 3918 if (src->is_double_xmm()) { 3919 if (dest->is_double_cpu()) { 3920 #ifdef _LP64 3921 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3922 #else 3923 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3924 __ psrlq(src->as_xmm_double_reg(), 32); 3925 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3926 #endif // _LP64 3927 } else if (dest->is_double_stack()) { 3928 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3929 } else if (dest->is_address()) { 3930 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3931 } else { 3932 ShouldNotReachHere(); 3933 } 3934 3935 } else if (dest->is_double_xmm()) { 3936 if (src->is_double_stack()) { 3937 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3938 } else if (src->is_address()) { 3939 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3940 } else { 3941 ShouldNotReachHere(); 3942 } 3943 3944 #ifndef _LP64 3945 } else if (src->is_double_fpu()) { 3946 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3947 if (dest->is_double_stack()) { 3948 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3949 } else if (dest->is_address()) { 3950 __ fistp_d(as_Address(dest->as_address_ptr())); 3951 } else { 3952 ShouldNotReachHere(); 3953 } 3954 3955 } else if (dest->is_double_fpu()) { 3956 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3957 if (src->is_double_stack()) { 3958 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3959 } else if (src->is_address()) { 3960 __ fild_d(as_Address(src->as_address_ptr())); 3961 } else { 3962 ShouldNotReachHere(); 3963 } 3964 #endif // !_LP64 3965 3966 } else { 3967 ShouldNotReachHere(); 3968 } 3969 } 3970 3971 #ifdef ASSERT 3972 // emit run-time assertion 3973 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3974 assert(op->code() == lir_assert, "must be"); 3975 3976 if (op->in_opr1()->is_valid()) { 3977 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3978 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3979 } else { 3980 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3981 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3982 } 3983 3984 Label ok; 3985 if (op->condition() != lir_cond_always) { 3986 Assembler::Condition acond = Assembler::zero; 3987 switch (op->condition()) { 3988 case lir_cond_equal: acond = Assembler::equal; break; 3989 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3990 case lir_cond_less: acond = Assembler::less; break; 3991 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3992 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3993 case lir_cond_greater: acond = Assembler::greater; break; 3994 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3995 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3996 default: ShouldNotReachHere(); 3997 } 3998 __ jcc(acond, ok); 3999 } 4000 if (op->halt()) { 4001 const char* str = __ code_string(op->msg()); 4002 __ stop(str); 4003 } else { 4004 breakpoint(); 4005 } 4006 __ bind(ok); 4007 } 4008 #endif 4009 4010 void LIR_Assembler::membar() { 4011 // QQQ sparc TSO uses this, 4012 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4013 } 4014 4015 void LIR_Assembler::membar_acquire() { 4016 // No x86 machines currently require load fences 4017 } 4018 4019 void LIR_Assembler::membar_release() { 4020 // No x86 machines currently require store fences 4021 } 4022 4023 void LIR_Assembler::membar_loadload() { 4024 // no-op 4025 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 4026 } 4027 4028 void LIR_Assembler::membar_storestore() { 4029 // no-op 4030 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 4031 } 4032 4033 void LIR_Assembler::membar_loadstore() { 4034 // no-op 4035 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 4036 } 4037 4038 void LIR_Assembler::membar_storeload() { 4039 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4040 } 4041 4042 void LIR_Assembler::on_spin_wait() { 4043 __ pause (); 4044 } 4045 4046 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 4047 assert(result_reg->is_register(), "check"); 4048 #ifdef _LP64 4049 // __ get_thread(result_reg->as_register_lo()); 4050 __ mov(result_reg->as_register(), r15_thread); 4051 #else 4052 __ get_thread(result_reg->as_register()); 4053 #endif // _LP64 4054 } 4055 4056 4057 void LIR_Assembler::peephole(LIR_List*) { 4058 // do nothing for now 4059 } 4060 4061 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 4062 assert(data == dest, "xchg/xadd uses only 2 operands"); 4063 4064 if (data->type() == T_INT) { 4065 if (code == lir_xadd) { 4066 __ lock(); 4067 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 4068 } else { 4069 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 4070 } 4071 } else if (data->is_oop()) { 4072 assert (code == lir_xchg, "xadd for oops"); 4073 Register obj = data->as_register(); 4074 #ifdef _LP64 4075 if (UseCompressedOops) { 4076 __ encode_heap_oop(obj); 4077 __ xchgl(obj, as_Address(src->as_address_ptr())); 4078 __ decode_heap_oop(obj); 4079 } else { 4080 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4081 } 4082 #else 4083 __ xchgl(obj, as_Address(src->as_address_ptr())); 4084 #endif 4085 } else if (data->type() == T_LONG) { 4086 #ifdef _LP64 4087 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4088 if (code == lir_xadd) { 4089 __ lock(); 4090 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4091 } else { 4092 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4093 } 4094 #else 4095 ShouldNotReachHere(); 4096 #endif 4097 } else { 4098 ShouldNotReachHere(); 4099 } 4100 } 4101 4102 #undef __