1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_x86.inline.hpp"
47
48
49 // These masks are used to provide 128-bit aligned bitmasks to the XMM
50 // instructions, to allow sign-masking or sign-bit flipping. They allow
51 // fast versions of NegF/NegD and AbsF/AbsD.
52
53 // Note: 'double' and 'long long' have 32-bits alignment on x86.
54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
55 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
56 // of 128-bits operands for SSE instructions.
57 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
58 // Store the value to a 128-bits operand.
59 operand[0] = lo;
60 operand[1] = hi;
61 return operand;
62 }
63
64 // Buffer for 128-bits masks used by SSE instructions.
65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
66
67 // Static initialization during VM startup.
68 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
70 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
72
73
74 NEEDS_CLEANUP // remove this definitions ?
75 const Register SYNC_header = rax; // synchronization header
76 const Register SHIFT_count = rcx; // where count for shift operations must be
77
78 #define __ _masm->
79
80
81 static void select_different_registers(Register preserve,
82 Register extra,
83 Register &tmp1,
84 Register &tmp2) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, extra);
90 tmp2 = extra;
91 }
92 assert_different_registers(preserve, tmp1, tmp2);
93 }
94
95
96
97 static void select_different_registers(Register preserve,
98 Register extra,
99 Register &tmp1,
100 Register &tmp2,
101 Register &tmp3) {
102 if (tmp1 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp1 = extra;
105 } else if (tmp2 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp2 = extra;
108 } else if (tmp3 == preserve) {
109 assert_different_registers(tmp1, tmp2, tmp3, extra);
110 tmp3 = extra;
111 }
112 assert_different_registers(preserve, tmp1, tmp2, tmp3);
113 }
114
115
116
117 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
118 if (opr->is_constant()) {
119 LIR_Const* constant = opr->as_constant_ptr();
120 switch (constant->type()) {
121 case T_INT: {
122 return true;
123 }
124
125 default:
126 return false;
127 }
128 }
129 return false;
130 }
131
132
133 LIR_Opr LIR_Assembler::receiverOpr() {
134 return FrameMap::receiver_opr;
135 }
136
137 LIR_Opr LIR_Assembler::osrBufferPointer() {
138 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
139 }
140
141 //--------------fpu register translations-----------------------
142
143
144 address LIR_Assembler::float_constant(float f) {
145 address const_addr = __ float_constant(f);
146 if (const_addr == nullptr) {
147 bailout("const section overflow");
148 return __ code()->consts()->start();
149 } else {
150 return const_addr;
151 }
152 }
153
154
155 address LIR_Assembler::double_constant(double d) {
156 address const_addr = __ double_constant(d);
157 if (const_addr == nullptr) {
158 bailout("const section overflow");
159 return __ code()->consts()->start();
160 } else {
161 return const_addr;
162 }
163 }
164
165 #ifndef _LP64
166 void LIR_Assembler::fpop() {
167 __ fpop();
168 }
169
170 void LIR_Assembler::fxch(int i) {
171 __ fxch(i);
172 }
173
174 void LIR_Assembler::fld(int i) {
175 __ fld_s(i);
176 }
177
178 void LIR_Assembler::ffree(int i) {
179 __ ffree(i);
180 }
181 #endif // !_LP64
182
183 void LIR_Assembler::breakpoint() {
184 __ int3();
185 }
186
187 void LIR_Assembler::push(LIR_Opr opr) {
188 if (opr->is_single_cpu()) {
189 __ push_reg(opr->as_register());
190 } else if (opr->is_double_cpu()) {
191 NOT_LP64(__ push_reg(opr->as_register_hi()));
192 __ push_reg(opr->as_register_lo());
193 } else if (opr->is_stack()) {
194 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
195 } else if (opr->is_constant()) {
196 LIR_Const* const_opr = opr->as_constant_ptr();
197 if (const_opr->type() == T_OBJECT) {
198 __ push_oop(const_opr->as_jobject(), rscratch1);
199 } else if (const_opr->type() == T_INT) {
200 __ push_jint(const_opr->as_jint());
201 } else {
202 ShouldNotReachHere();
203 }
204
205 } else {
206 ShouldNotReachHere();
207 }
208 }
209
210 void LIR_Assembler::pop(LIR_Opr opr) {
211 if (opr->is_single_cpu()) {
212 __ pop_reg(opr->as_register());
213 } else {
214 ShouldNotReachHere();
215 }
216 }
217
218 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
219 return addr->base()->is_illegal() && addr->index()->is_illegal();
220 }
221
222 //-------------------------------------------
223
224 Address LIR_Assembler::as_Address(LIR_Address* addr) {
225 return as_Address(addr, rscratch1);
226 }
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
229 if (addr->base()->is_illegal()) {
230 assert(addr->index()->is_illegal(), "must be illegal too");
231 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
232 if (! __ reachable(laddr)) {
233 __ movptr(tmp, laddr.addr());
234 Address res(tmp, 0);
235 return res;
236 } else {
237 return __ as_Address(laddr);
238 }
239 }
240
241 Register base = addr->base()->as_pointer_register();
242
243 if (addr->index()->is_illegal()) {
244 return Address( base, addr->disp());
245 } else if (addr->index()->is_cpu_register()) {
246 Register index = addr->index()->as_pointer_register();
247 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
248 } else if (addr->index()->is_constant()) {
249 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
250 assert(Assembler::is_simm32(addr_offset), "must be");
251
252 return Address(base, addr_offset);
253 } else {
254 Unimplemented();
255 return Address();
256 }
257 }
258
259
260 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
261 Address base = as_Address(addr);
262 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
263 }
264
265
266 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
267 return as_Address(addr);
268 }
269
270
271 void LIR_Assembler::osr_entry() {
272 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
273 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
274 ValueStack* entry_state = osr_entry->state();
275 int number_of_locks = entry_state->locks_size();
276
277 // we jump here if osr happens with the interpreter
278 // state set up to continue at the beginning of the
279 // loop that triggered osr - in particular, we have
280 // the following registers setup:
281 //
282 // rcx: osr buffer
283 //
284
285 // build frame
286 ciMethod* m = compilation()->method();
287 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
288
289 // OSR buffer is
290 //
291 // locals[nlocals-1..0]
292 // monitors[0..number_of_locks]
293 //
294 // locals is a direct copy of the interpreter frame so in the osr buffer
295 // so first slot in the local array is the last local from the interpreter
296 // and last slot is local[0] (receiver) from the interpreter
297 //
298 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
299 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
300 // in the interpreter frame (the method lock if a sync method)
301
302 // Initialize monitors in the compiled activation.
303 // rcx: pointer to osr buffer
304 //
305 // All other registers are dead at this point and the locals will be
306 // copied into place by code emitted in the IR.
307
308 Register OSR_buf = osrBufferPointer()->as_pointer_register();
309 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
310 int monitor_offset = BytesPerWord * method()->max_locals() +
311 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
312 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
313 // the OSR buffer using 2 word entries: first the lock and then
314 // the oop.
315 for (int i = 0; i < number_of_locks; i++) {
316 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
317 #ifdef ASSERT
318 // verify the interpreter's monitor has a non-null object
319 {
320 Label L;
321 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
322 __ jcc(Assembler::notZero, L);
323 __ stop("locked object is null");
324 __ bind(L);
325 }
326 #endif
327 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
328 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
330 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
331 }
332 }
333 }
334
335
336 // inline cache check; done before the frame is built.
337 int LIR_Assembler::check_icache() {
338 return __ ic_check(CodeEntryAlignment);
339 }
340
341 void LIR_Assembler::clinit_barrier(ciMethod* method) {
342 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
343 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
344
345 Label L_skip_barrier;
346 Register klass = rscratch1;
347 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
348 assert(thread != noreg, "x86_32 not implemented");
349
350 __ mov_metadata(klass, method->holder()->constant_encoding());
351 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
352
353 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
354
355 __ bind(L_skip_barrier);
356 }
357
358 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
359 jobject o = nullptr;
360 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
361 __ movoop(reg, o);
362 patching_epilog(patch, lir_patch_normal, reg, info);
363 }
364
365 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
366 Metadata* o = nullptr;
367 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
368 __ mov_metadata(reg, o);
369 patching_epilog(patch, lir_patch_normal, reg, info);
370 }
371
372 // This specifies the rsp decrement needed to build the frame
373 int LIR_Assembler::initial_frame_size_in_bytes() const {
374 // if rounding, must let FrameMap know!
375
376 // The frame_map records size in slots (32bit word)
377
378 // subtract two words to account for return address and link
379 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
380 }
381
382
383 int LIR_Assembler::emit_exception_handler() {
384 // generate code for exception handler
385 address handler_base = __ start_a_stub(exception_handler_size());
386 if (handler_base == nullptr) {
387 // not enough space left for the handler
388 bailout("exception handler overflow");
389 return -1;
390 }
391
392 int offset = code_offset();
393
394 // the exception oop and pc are in rax, and rdx
395 // no other registers need to be preserved, so invalidate them
396 __ invalidate_registers(false, true, true, false, true, true);
397
398 // check that there is really an exception
399 __ verify_not_null_oop(rax);
400
401 // search an exception handler (rax: exception oop, rdx: throwing pc)
402 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
403 __ should_not_reach_here();
404 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
405 __ end_a_stub();
406
407 return offset;
408 }
409
410
411 // Emit the code to remove the frame from the stack in the exception
412 // unwind path.
413 int LIR_Assembler::emit_unwind_handler() {
414 #ifndef PRODUCT
415 if (CommentedAssembly) {
416 _masm->block_comment("Unwind handler");
417 }
418 #endif
419
420 int offset = code_offset();
421
422 // Fetch the exception from TLS and clear out exception related thread state
423 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
424 NOT_LP64(__ get_thread(thread));
425 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
426 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
427 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
428
429 __ bind(_unwind_handler_entry);
430 __ verify_not_null_oop(rax);
431 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
432 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
433 }
434
435 // Perform needed unlocking
436 MonitorExitStub* stub = nullptr;
437 if (method()->is_synchronized()) {
438 monitor_address(0, FrameMap::rax_opr);
439 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
440 if (LockingMode == LM_MONITOR) {
441 __ jmp(*stub->entry());
442 } else {
443 __ unlock_object(rdi, rsi, rax, *stub->entry());
444 }
445 __ bind(*stub->continuation());
446 }
447
448 if (compilation()->env()->dtrace_method_probes()) {
449 #ifdef _LP64
450 __ mov(rdi, r15_thread);
451 __ mov_metadata(rsi, method()->constant_encoding());
452 #else
453 __ get_thread(rax);
454 __ movptr(Address(rsp, 0), rax);
455 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
456 #endif
457 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
458 }
459
460 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
461 __ mov(rax, rbx); // Restore the exception
462 }
463
464 // remove the activation and dispatch to the unwind handler
465 __ remove_frame(initial_frame_size_in_bytes());
466 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
467
468 // Emit the slow path assembly
469 if (stub != nullptr) {
470 stub->emit_code(this);
471 }
472
473 return offset;
474 }
475
476
477 int LIR_Assembler::emit_deopt_handler() {
478 // generate code for exception handler
479 address handler_base = __ start_a_stub(deopt_handler_size());
480 if (handler_base == nullptr) {
481 // not enough space left for the handler
482 bailout("deopt handler overflow");
483 return -1;
484 }
485
486 int offset = code_offset();
487 InternalAddress here(__ pc());
488
489 __ pushptr(here.addr(), rscratch1);
490 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
491 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
492 __ end_a_stub();
493
494 return offset;
495 }
496
497 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
498 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
499 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
500 assert(result->fpu() == 0, "result must already be on TOS");
501 }
502
503 // Pop the stack before the safepoint code
504 __ remove_frame(initial_frame_size_in_bytes());
505
506 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
507 __ reserved_stack_check();
508 }
509
510 // Note: we do not need to round double result; float result has the right precision
511 // the poll sets the condition code, but no data registers
512
513 #ifdef _LP64
514 const Register thread = r15_thread;
515 #else
516 const Register thread = rbx;
517 __ get_thread(thread);
518 #endif
519 code_stub->set_safepoint_offset(__ offset());
520 __ relocate(relocInfo::poll_return_type);
521 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
522 __ ret(0);
523 }
524
525
526 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
527 guarantee(info != nullptr, "Shouldn't be null");
528 int offset = __ offset();
529 #ifdef _LP64
530 const Register poll_addr = rscratch1;
531 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
532 #else
533 assert(tmp->is_cpu_register(), "needed");
534 const Register poll_addr = tmp->as_register();
535 __ get_thread(poll_addr);
536 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
537 #endif
538 add_debug_info_for_branch(info);
539 __ relocate(relocInfo::poll_type);
540 address pre_pc = __ pc();
541 __ testl(rax, Address(poll_addr, 0));
542 address post_pc = __ pc();
543 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
544 return offset;
545 }
546
547
548 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
549 if (from_reg != to_reg) __ mov(to_reg, from_reg);
550 }
551
552 void LIR_Assembler::swap_reg(Register a, Register b) {
553 __ xchgptr(a, b);
554 }
555
556
557 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
558 assert(src->is_constant(), "should not call otherwise");
559 assert(dest->is_register(), "should not call otherwise");
560 LIR_Const* c = src->as_constant_ptr();
561
562 switch (c->type()) {
563 case T_INT: {
564 assert(patch_code == lir_patch_none, "no patching handled here");
565 __ movl(dest->as_register(), c->as_jint());
566 break;
567 }
568
569 case T_ADDRESS: {
570 assert(patch_code == lir_patch_none, "no patching handled here");
571 __ movptr(dest->as_register(), c->as_jint());
572 break;
573 }
574
575 case T_LONG: {
576 assert(patch_code == lir_patch_none, "no patching handled here");
577 #ifdef _LP64
578 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
579 #else
580 __ movptr(dest->as_register_lo(), c->as_jint_lo());
581 __ movptr(dest->as_register_hi(), c->as_jint_hi());
582 #endif // _LP64
583 break;
584 }
585
586 case T_OBJECT: {
587 if (patch_code != lir_patch_none) {
588 jobject2reg_with_patching(dest->as_register(), info);
589 } else {
590 __ movoop(dest->as_register(), c->as_jobject());
591 }
592 break;
593 }
594
595 case T_METADATA: {
596 if (patch_code != lir_patch_none) {
597 klass2reg_with_patching(dest->as_register(), info);
598 } else {
599 __ mov_metadata(dest->as_register(), c->as_metadata());
600 }
601 break;
602 }
603
604 case T_FLOAT: {
605 if (dest->is_single_xmm()) {
606 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
607 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
608 } else {
609 __ movflt(dest->as_xmm_float_reg(),
610 InternalAddress(float_constant(c->as_jfloat())));
611 }
612 } else {
613 #ifndef _LP64
614 assert(dest->is_single_fpu(), "must be");
615 assert(dest->fpu_regnr() == 0, "dest must be TOS");
616 if (c->is_zero_float()) {
617 __ fldz();
618 } else if (c->is_one_float()) {
619 __ fld1();
620 } else {
621 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
622 }
623 #else
624 ShouldNotReachHere();
625 #endif // !_LP64
626 }
627 break;
628 }
629
630 case T_DOUBLE: {
631 if (dest->is_double_xmm()) {
632 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
633 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
634 } else {
635 __ movdbl(dest->as_xmm_double_reg(),
636 InternalAddress(double_constant(c->as_jdouble())));
637 }
638 } else {
639 #ifndef _LP64
640 assert(dest->is_double_fpu(), "must be");
641 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
642 if (c->is_zero_double()) {
643 __ fldz();
644 } else if (c->is_one_double()) {
645 __ fld1();
646 } else {
647 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
648 }
649 #else
650 ShouldNotReachHere();
651 #endif // !_LP64
652 }
653 break;
654 }
655
656 default:
657 ShouldNotReachHere();
658 }
659 }
660
661 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
662 assert(src->is_constant(), "should not call otherwise");
663 assert(dest->is_stack(), "should not call otherwise");
664 LIR_Const* c = src->as_constant_ptr();
665
666 switch (c->type()) {
667 case T_INT: // fall through
668 case T_FLOAT:
669 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
670 break;
671
672 case T_ADDRESS:
673 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
674 break;
675
676 case T_OBJECT:
677 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
678 break;
679
680 case T_LONG: // fall through
681 case T_DOUBLE:
682 #ifdef _LP64
683 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
684 lo_word_offset_in_bytes),
685 (intptr_t)c->as_jlong_bits(),
686 rscratch1);
687 #else
688 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
689 lo_word_offset_in_bytes), c->as_jint_lo_bits());
690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
691 hi_word_offset_in_bytes), c->as_jint_hi_bits());
692 #endif // _LP64
693 break;
694
695 default:
696 ShouldNotReachHere();
697 }
698 }
699
700 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
701 assert(src->is_constant(), "should not call otherwise");
702 assert(dest->is_address(), "should not call otherwise");
703 LIR_Const* c = src->as_constant_ptr();
704 LIR_Address* addr = dest->as_address_ptr();
705
706 int null_check_here = code_offset();
707 switch (type) {
708 case T_INT: // fall through
709 case T_FLOAT:
710 __ movl(as_Address(addr), c->as_jint_bits());
711 break;
712
713 case T_ADDRESS:
714 __ movptr(as_Address(addr), c->as_jint_bits());
715 break;
716
717 case T_OBJECT: // fall through
718 case T_ARRAY:
719 if (c->as_jobject() == nullptr) {
720 if (UseCompressedOops && !wide) {
721 __ movl(as_Address(addr), NULL_WORD);
722 } else {
723 #ifdef _LP64
724 __ xorptr(rscratch1, rscratch1);
725 null_check_here = code_offset();
726 __ movptr(as_Address(addr), rscratch1);
727 #else
728 __ movptr(as_Address(addr), NULL_WORD);
729 #endif
730 }
731 } else {
732 if (is_literal_address(addr)) {
733 ShouldNotReachHere();
734 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
735 } else {
736 #ifdef _LP64
737 __ movoop(rscratch1, c->as_jobject());
738 if (UseCompressedOops && !wide) {
739 __ encode_heap_oop(rscratch1);
740 null_check_here = code_offset();
741 __ movl(as_Address_lo(addr), rscratch1);
742 } else {
743 null_check_here = code_offset();
744 __ movptr(as_Address_lo(addr), rscratch1);
745 }
746 #else
747 __ movoop(as_Address(addr), c->as_jobject(), noreg);
748 #endif
749 }
750 }
751 break;
752
753 case T_LONG: // fall through
754 case T_DOUBLE:
755 #ifdef _LP64
756 if (is_literal_address(addr)) {
757 ShouldNotReachHere();
758 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
759 } else {
760 __ movptr(r10, (intptr_t)c->as_jlong_bits());
761 null_check_here = code_offset();
762 __ movptr(as_Address_lo(addr), r10);
763 }
764 #else
765 // Always reachable in 32bit so this doesn't produce useless move literal
766 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
767 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
768 #endif // _LP64
769 break;
770
771 case T_BOOLEAN: // fall through
772 case T_BYTE:
773 __ movb(as_Address(addr), c->as_jint() & 0xFF);
774 break;
775
776 case T_CHAR: // fall through
777 case T_SHORT:
778 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
779 break;
780
781 default:
782 ShouldNotReachHere();
783 };
784
785 if (info != nullptr) {
786 add_debug_info_for_null_check(null_check_here, info);
787 }
788 }
789
790
791 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
792 assert(src->is_register(), "should not call otherwise");
793 assert(dest->is_register(), "should not call otherwise");
794
795 // move between cpu-registers
796 if (dest->is_single_cpu()) {
797 #ifdef _LP64
798 if (src->type() == T_LONG) {
799 // Can do LONG -> OBJECT
800 move_regs(src->as_register_lo(), dest->as_register());
801 return;
802 }
803 #endif
804 assert(src->is_single_cpu(), "must match");
805 if (src->type() == T_OBJECT) {
806 __ verify_oop(src->as_register());
807 }
808 move_regs(src->as_register(), dest->as_register());
809
810 } else if (dest->is_double_cpu()) {
811 #ifdef _LP64
812 if (is_reference_type(src->type())) {
813 // Surprising to me but we can see move of a long to t_object
814 __ verify_oop(src->as_register());
815 move_regs(src->as_register(), dest->as_register_lo());
816 return;
817 }
818 #endif
819 assert(src->is_double_cpu(), "must match");
820 Register f_lo = src->as_register_lo();
821 Register f_hi = src->as_register_hi();
822 Register t_lo = dest->as_register_lo();
823 Register t_hi = dest->as_register_hi();
824 #ifdef _LP64
825 assert(f_hi == f_lo, "must be same");
826 assert(t_hi == t_lo, "must be same");
827 move_regs(f_lo, t_lo);
828 #else
829 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
830
831
832 if (f_lo == t_hi && f_hi == t_lo) {
833 swap_reg(f_lo, f_hi);
834 } else if (f_hi == t_lo) {
835 assert(f_lo != t_hi, "overwriting register");
836 move_regs(f_hi, t_hi);
837 move_regs(f_lo, t_lo);
838 } else {
839 assert(f_hi != t_lo, "overwriting register");
840 move_regs(f_lo, t_lo);
841 move_regs(f_hi, t_hi);
842 }
843 #endif // LP64
844
845 #ifndef _LP64
846 // special moves from fpu-register to xmm-register
847 // necessary for method results
848 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
849 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
850 __ fld_s(Address(rsp, 0));
851 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
852 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
853 __ fld_d(Address(rsp, 0));
854 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
855 __ fstp_s(Address(rsp, 0));
856 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
857 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
858 __ fstp_d(Address(rsp, 0));
859 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
860 #endif // !_LP64
861
862 // move between xmm-registers
863 } else if (dest->is_single_xmm()) {
864 assert(src->is_single_xmm(), "must match");
865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
866 } else if (dest->is_double_xmm()) {
867 assert(src->is_double_xmm(), "must match");
868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
869
870 #ifndef _LP64
871 // move between fpu-registers (no instruction necessary because of fpu-stack)
872 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
873 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
874 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
875 #endif // !_LP64
876
877 } else {
878 ShouldNotReachHere();
879 }
880 }
881
882 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
883 assert(src->is_register(), "should not call otherwise");
884 assert(dest->is_stack(), "should not call otherwise");
885
886 if (src->is_single_cpu()) {
887 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
888 if (is_reference_type(type)) {
889 __ verify_oop(src->as_register());
890 __ movptr (dst, src->as_register());
891 } else if (type == T_METADATA || type == T_ADDRESS) {
892 __ movptr (dst, src->as_register());
893 } else {
894 __ movl (dst, src->as_register());
895 }
896
897 } else if (src->is_double_cpu()) {
898 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
899 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
900 __ movptr (dstLO, src->as_register_lo());
901 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
902
903 } else if (src->is_single_xmm()) {
904 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
905 __ movflt(dst_addr, src->as_xmm_float_reg());
906
907 } else if (src->is_double_xmm()) {
908 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
909 __ movdbl(dst_addr, src->as_xmm_double_reg());
910
911 #ifndef _LP64
912 } else if (src->is_single_fpu()) {
913 assert(src->fpu_regnr() == 0, "argument must be on TOS");
914 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
915 if (pop_fpu_stack) __ fstp_s (dst_addr);
916 else __ fst_s (dst_addr);
917
918 } else if (src->is_double_fpu()) {
919 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
920 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
921 if (pop_fpu_stack) __ fstp_d (dst_addr);
922 else __ fst_d (dst_addr);
923 #endif // !_LP64
924
925 } else {
926 ShouldNotReachHere();
927 }
928 }
929
930
931 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
932 LIR_Address* to_addr = dest->as_address_ptr();
933 PatchingStub* patch = nullptr;
934 Register compressed_src = rscratch1;
935
936 if (is_reference_type(type)) {
937 __ verify_oop(src->as_register());
938 #ifdef _LP64
939 if (UseCompressedOops && !wide) {
940 __ movptr(compressed_src, src->as_register());
941 __ encode_heap_oop(compressed_src);
942 if (patch_code != lir_patch_none) {
943 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
944 }
945 }
946 #endif
947 }
948
949 if (patch_code != lir_patch_none) {
950 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
951 Address toa = as_Address(to_addr);
952 assert(toa.disp() != 0, "must have");
953 }
954
955 int null_check_here = code_offset();
956 switch (type) {
957 case T_FLOAT: {
958 #ifdef _LP64
959 assert(src->is_single_xmm(), "not a float");
960 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
961 #else
962 if (src->is_single_xmm()) {
963 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
964 } else {
965 assert(src->is_single_fpu(), "must be");
966 assert(src->fpu_regnr() == 0, "argument must be on TOS");
967 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
968 else __ fst_s (as_Address(to_addr));
969 }
970 #endif // _LP64
971 break;
972 }
973
974 case T_DOUBLE: {
975 #ifdef _LP64
976 assert(src->is_double_xmm(), "not a double");
977 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
978 #else
979 if (src->is_double_xmm()) {
980 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
981 } else {
982 assert(src->is_double_fpu(), "must be");
983 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
984 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
985 else __ fst_d (as_Address(to_addr));
986 }
987 #endif // _LP64
988 break;
989 }
990
991 case T_ARRAY: // fall through
992 case T_OBJECT: // fall through
993 if (UseCompressedOops && !wide) {
994 __ movl(as_Address(to_addr), compressed_src);
995 } else {
996 __ movptr(as_Address(to_addr), src->as_register());
997 }
998 break;
999 case T_METADATA:
1000 // We get here to store a method pointer to the stack to pass to
1001 // a dtrace runtime call. This can't work on 64 bit with
1002 // compressed klass ptrs: T_METADATA can be a compressed klass
1003 // ptr or a 64 bit method pointer.
1004 LP64_ONLY(ShouldNotReachHere());
1005 __ movptr(as_Address(to_addr), src->as_register());
1006 break;
1007 case T_ADDRESS:
1008 __ movptr(as_Address(to_addr), src->as_register());
1009 break;
1010 case T_INT:
1011 __ movl(as_Address(to_addr), src->as_register());
1012 break;
1013
1014 case T_LONG: {
1015 Register from_lo = src->as_register_lo();
1016 Register from_hi = src->as_register_hi();
1017 #ifdef _LP64
1018 __ movptr(as_Address_lo(to_addr), from_lo);
1019 #else
1020 Register base = to_addr->base()->as_register();
1021 Register index = noreg;
1022 if (to_addr->index()->is_register()) {
1023 index = to_addr->index()->as_register();
1024 }
1025 if (base == from_lo || index == from_lo) {
1026 assert(base != from_hi, "can't be");
1027 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1028 __ movl(as_Address_hi(to_addr), from_hi);
1029 if (patch != nullptr) {
1030 patching_epilog(patch, lir_patch_high, base, info);
1031 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1032 patch_code = lir_patch_low;
1033 }
1034 __ movl(as_Address_lo(to_addr), from_lo);
1035 } else {
1036 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1037 __ movl(as_Address_lo(to_addr), from_lo);
1038 if (patch != nullptr) {
1039 patching_epilog(patch, lir_patch_low, base, info);
1040 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1041 patch_code = lir_patch_high;
1042 }
1043 __ movl(as_Address_hi(to_addr), from_hi);
1044 }
1045 #endif // _LP64
1046 break;
1047 }
1048
1049 case T_BYTE: // fall through
1050 case T_BOOLEAN: {
1051 Register src_reg = src->as_register();
1052 Address dst_addr = as_Address(to_addr);
1053 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1054 __ movb(dst_addr, src_reg);
1055 break;
1056 }
1057
1058 case T_CHAR: // fall through
1059 case T_SHORT:
1060 __ movw(as_Address(to_addr), src->as_register());
1061 break;
1062
1063 default:
1064 ShouldNotReachHere();
1065 }
1066 if (info != nullptr) {
1067 add_debug_info_for_null_check(null_check_here, info);
1068 }
1069
1070 if (patch_code != lir_patch_none) {
1071 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1072 }
1073 }
1074
1075
1076 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1077 assert(src->is_stack(), "should not call otherwise");
1078 assert(dest->is_register(), "should not call otherwise");
1079
1080 if (dest->is_single_cpu()) {
1081 if (is_reference_type(type)) {
1082 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1083 __ verify_oop(dest->as_register());
1084 } else if (type == T_METADATA || type == T_ADDRESS) {
1085 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1086 } else {
1087 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1088 }
1089
1090 } else if (dest->is_double_cpu()) {
1091 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1092 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1093 __ movptr(dest->as_register_lo(), src_addr_LO);
1094 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1095
1096 } else if (dest->is_single_xmm()) {
1097 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1098 __ movflt(dest->as_xmm_float_reg(), src_addr);
1099
1100 } else if (dest->is_double_xmm()) {
1101 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1102 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1103
1104 #ifndef _LP64
1105 } else if (dest->is_single_fpu()) {
1106 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1107 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1108 __ fld_s(src_addr);
1109
1110 } else if (dest->is_double_fpu()) {
1111 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1112 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1113 __ fld_d(src_addr);
1114 #endif // _LP64
1115
1116 } else {
1117 ShouldNotReachHere();
1118 }
1119 }
1120
1121
1122 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1123 if (src->is_single_stack()) {
1124 if (is_reference_type(type)) {
1125 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1126 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1127 } else {
1128 #ifndef _LP64
1129 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1130 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1131 #else
1132 //no pushl on 64bits
1133 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1134 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1135 #endif
1136 }
1137
1138 } else if (src->is_double_stack()) {
1139 #ifdef _LP64
1140 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1141 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1142 #else
1143 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1144 // push and pop the part at src + wordSize, adding wordSize for the previous push
1145 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1146 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1147 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1148 #endif // _LP64
1149
1150 } else {
1151 ShouldNotReachHere();
1152 }
1153 }
1154
1155
1156 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1157 assert(src->is_address(), "should not call otherwise");
1158 assert(dest->is_register(), "should not call otherwise");
1159
1160 LIR_Address* addr = src->as_address_ptr();
1161 Address from_addr = as_Address(addr);
1162
1163 if (addr->base()->type() == T_OBJECT) {
1164 __ verify_oop(addr->base()->as_pointer_register());
1165 }
1166
1167 switch (type) {
1168 case T_BOOLEAN: // fall through
1169 case T_BYTE: // fall through
1170 case T_CHAR: // fall through
1171 case T_SHORT:
1172 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1173 // on pre P6 processors we may get partial register stalls
1174 // so blow away the value of to_rinfo before loading a
1175 // partial word into it. Do it here so that it precedes
1176 // the potential patch point below.
1177 __ xorptr(dest->as_register(), dest->as_register());
1178 }
1179 break;
1180 default:
1181 break;
1182 }
1183
1184 PatchingStub* patch = nullptr;
1185 if (patch_code != lir_patch_none) {
1186 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1187 assert(from_addr.disp() != 0, "must have");
1188 }
1189 if (info != nullptr) {
1190 add_debug_info_for_null_check_here(info);
1191 }
1192
1193 switch (type) {
1194 case T_FLOAT: {
1195 if (dest->is_single_xmm()) {
1196 __ movflt(dest->as_xmm_float_reg(), from_addr);
1197 } else {
1198 #ifndef _LP64
1199 assert(dest->is_single_fpu(), "must be");
1200 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1201 __ fld_s(from_addr);
1202 #else
1203 ShouldNotReachHere();
1204 #endif // !LP64
1205 }
1206 break;
1207 }
1208
1209 case T_DOUBLE: {
1210 if (dest->is_double_xmm()) {
1211 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1212 } else {
1213 #ifndef _LP64
1214 assert(dest->is_double_fpu(), "must be");
1215 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1216 __ fld_d(from_addr);
1217 #else
1218 ShouldNotReachHere();
1219 #endif // !LP64
1220 }
1221 break;
1222 }
1223
1224 case T_OBJECT: // fall through
1225 case T_ARRAY: // fall through
1226 if (UseCompressedOops && !wide) {
1227 __ movl(dest->as_register(), from_addr);
1228 } else {
1229 __ movptr(dest->as_register(), from_addr);
1230 }
1231 break;
1232
1233 case T_ADDRESS:
1234 __ movptr(dest->as_register(), from_addr);
1235 break;
1236 case T_INT:
1237 __ movl(dest->as_register(), from_addr);
1238 break;
1239
1240 case T_LONG: {
1241 Register to_lo = dest->as_register_lo();
1242 Register to_hi = dest->as_register_hi();
1243 #ifdef _LP64
1244 __ movptr(to_lo, as_Address_lo(addr));
1245 #else
1246 Register base = addr->base()->as_register();
1247 Register index = noreg;
1248 if (addr->index()->is_register()) {
1249 index = addr->index()->as_register();
1250 }
1251 if ((base == to_lo && index == to_hi) ||
1252 (base == to_hi && index == to_lo)) {
1253 // addresses with 2 registers are only formed as a result of
1254 // array access so this code will never have to deal with
1255 // patches or null checks.
1256 assert(info == nullptr && patch == nullptr, "must be");
1257 __ lea(to_hi, as_Address(addr));
1258 __ movl(to_lo, Address(to_hi, 0));
1259 __ movl(to_hi, Address(to_hi, BytesPerWord));
1260 } else if (base == to_lo || index == to_lo) {
1261 assert(base != to_hi, "can't be");
1262 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1263 __ movl(to_hi, as_Address_hi(addr));
1264 if (patch != nullptr) {
1265 patching_epilog(patch, lir_patch_high, base, info);
1266 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1267 patch_code = lir_patch_low;
1268 }
1269 __ movl(to_lo, as_Address_lo(addr));
1270 } else {
1271 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1272 __ movl(to_lo, as_Address_lo(addr));
1273 if (patch != nullptr) {
1274 patching_epilog(patch, lir_patch_low, base, info);
1275 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1276 patch_code = lir_patch_high;
1277 }
1278 __ movl(to_hi, as_Address_hi(addr));
1279 }
1280 #endif // _LP64
1281 break;
1282 }
1283
1284 case T_BOOLEAN: // fall through
1285 case T_BYTE: {
1286 Register dest_reg = dest->as_register();
1287 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1288 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1289 __ movsbl(dest_reg, from_addr);
1290 } else {
1291 __ movb(dest_reg, from_addr);
1292 __ shll(dest_reg, 24);
1293 __ sarl(dest_reg, 24);
1294 }
1295 break;
1296 }
1297
1298 case T_CHAR: {
1299 Register dest_reg = dest->as_register();
1300 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1301 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1302 __ movzwl(dest_reg, from_addr);
1303 } else {
1304 __ movw(dest_reg, from_addr);
1305 }
1306 break;
1307 }
1308
1309 case T_SHORT: {
1310 Register dest_reg = dest->as_register();
1311 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1312 __ movswl(dest_reg, from_addr);
1313 } else {
1314 __ movw(dest_reg, from_addr);
1315 __ shll(dest_reg, 16);
1316 __ sarl(dest_reg, 16);
1317 }
1318 break;
1319 }
1320
1321 default:
1322 ShouldNotReachHere();
1323 }
1324
1325 if (patch != nullptr) {
1326 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1327 }
1328
1329 if (is_reference_type(type)) {
1330 #ifdef _LP64
1331 if (UseCompressedOops && !wide) {
1332 __ decode_heap_oop(dest->as_register());
1333 }
1334 #endif
1335
1336 if (!(UseZGC && !ZGenerational)) {
1337 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1338 __ verify_oop(dest->as_register());
1339 }
1340 }
1341 }
1342
1343
1344 NEEDS_CLEANUP; // This could be static?
1345 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1346 int elem_size = type2aelembytes(type);
1347 switch (elem_size) {
1348 case 1: return Address::times_1;
1349 case 2: return Address::times_2;
1350 case 4: return Address::times_4;
1351 case 8: return Address::times_8;
1352 }
1353 ShouldNotReachHere();
1354 return Address::no_scale;
1355 }
1356
1357
1358 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1359 switch (op->code()) {
1360 case lir_idiv:
1361 case lir_irem:
1362 arithmetic_idiv(op->code(),
1363 op->in_opr1(),
1364 op->in_opr2(),
1365 op->in_opr3(),
1366 op->result_opr(),
1367 op->info());
1368 break;
1369 case lir_fmad:
1370 __ fmad(op->result_opr()->as_xmm_double_reg(),
1371 op->in_opr1()->as_xmm_double_reg(),
1372 op->in_opr2()->as_xmm_double_reg(),
1373 op->in_opr3()->as_xmm_double_reg());
1374 break;
1375 case lir_fmaf:
1376 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1377 op->in_opr1()->as_xmm_float_reg(),
1378 op->in_opr2()->as_xmm_float_reg(),
1379 op->in_opr3()->as_xmm_float_reg());
1380 break;
1381 default: ShouldNotReachHere(); break;
1382 }
1383 }
1384
1385 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1386 #ifdef ASSERT
1387 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1388 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1389 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1390 #endif
1391
1392 if (op->cond() == lir_cond_always) {
1393 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1394 __ jmp (*(op->label()));
1395 } else {
1396 Assembler::Condition acond = Assembler::zero;
1397 if (op->code() == lir_cond_float_branch) {
1398 assert(op->ublock() != nullptr, "must have unordered successor");
1399 __ jcc(Assembler::parity, *(op->ublock()->label()));
1400 switch(op->cond()) {
1401 case lir_cond_equal: acond = Assembler::equal; break;
1402 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1403 case lir_cond_less: acond = Assembler::below; break;
1404 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1405 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1406 case lir_cond_greater: acond = Assembler::above; break;
1407 default: ShouldNotReachHere();
1408 }
1409 } else {
1410 switch (op->cond()) {
1411 case lir_cond_equal: acond = Assembler::equal; break;
1412 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1413 case lir_cond_less: acond = Assembler::less; break;
1414 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1415 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1416 case lir_cond_greater: acond = Assembler::greater; break;
1417 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1418 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1419 default: ShouldNotReachHere();
1420 }
1421 }
1422 __ jcc(acond,*(op->label()));
1423 }
1424 }
1425
1426 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1427 LIR_Opr src = op->in_opr();
1428 LIR_Opr dest = op->result_opr();
1429
1430 switch (op->bytecode()) {
1431 case Bytecodes::_i2l:
1432 #ifdef _LP64
1433 __ movl2ptr(dest->as_register_lo(), src->as_register());
1434 #else
1435 move_regs(src->as_register(), dest->as_register_lo());
1436 move_regs(src->as_register(), dest->as_register_hi());
1437 __ sarl(dest->as_register_hi(), 31);
1438 #endif // LP64
1439 break;
1440
1441 case Bytecodes::_l2i:
1442 #ifdef _LP64
1443 __ movl(dest->as_register(), src->as_register_lo());
1444 #else
1445 move_regs(src->as_register_lo(), dest->as_register());
1446 #endif
1447 break;
1448
1449 case Bytecodes::_i2b:
1450 move_regs(src->as_register(), dest->as_register());
1451 __ sign_extend_byte(dest->as_register());
1452 break;
1453
1454 case Bytecodes::_i2c:
1455 move_regs(src->as_register(), dest->as_register());
1456 __ andl(dest->as_register(), 0xFFFF);
1457 break;
1458
1459 case Bytecodes::_i2s:
1460 move_regs(src->as_register(), dest->as_register());
1461 __ sign_extend_short(dest->as_register());
1462 break;
1463
1464
1465 #ifdef _LP64
1466 case Bytecodes::_f2d:
1467 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1468 break;
1469
1470 case Bytecodes::_d2f:
1471 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1472 break;
1473
1474 case Bytecodes::_i2f:
1475 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1476 break;
1477
1478 case Bytecodes::_i2d:
1479 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1480 break;
1481
1482 case Bytecodes::_l2f:
1483 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1484 break;
1485
1486 case Bytecodes::_l2d:
1487 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1488 break;
1489
1490 case Bytecodes::_f2i:
1491 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1492 break;
1493
1494 case Bytecodes::_d2i:
1495 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1496 break;
1497
1498 case Bytecodes::_f2l:
1499 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1500 break;
1501
1502 case Bytecodes::_d2l:
1503 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1504 break;
1505 #else
1506 case Bytecodes::_f2d:
1507 case Bytecodes::_d2f:
1508 if (dest->is_single_xmm()) {
1509 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1510 } else if (dest->is_double_xmm()) {
1511 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1512 } else {
1513 assert(src->fpu() == dest->fpu(), "register must be equal");
1514 // do nothing (float result is rounded later through spilling)
1515 }
1516 break;
1517
1518 case Bytecodes::_i2f:
1519 case Bytecodes::_i2d:
1520 if (dest->is_single_xmm()) {
1521 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1522 } else if (dest->is_double_xmm()) {
1523 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1524 } else {
1525 assert(dest->fpu() == 0, "result must be on TOS");
1526 __ movl(Address(rsp, 0), src->as_register());
1527 __ fild_s(Address(rsp, 0));
1528 }
1529 break;
1530
1531 case Bytecodes::_l2f:
1532 case Bytecodes::_l2d:
1533 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1534 assert(dest->fpu() == 0, "result must be on TOS");
1535 __ movptr(Address(rsp, 0), src->as_register_lo());
1536 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1537 __ fild_d(Address(rsp, 0));
1538 // float result is rounded later through spilling
1539 break;
1540
1541 case Bytecodes::_f2i:
1542 case Bytecodes::_d2i:
1543 if (src->is_single_xmm()) {
1544 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1545 } else if (src->is_double_xmm()) {
1546 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1547 } else {
1548 assert(src->fpu() == 0, "input must be on TOS");
1549 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1550 __ fist_s(Address(rsp, 0));
1551 __ movl(dest->as_register(), Address(rsp, 0));
1552 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1553 }
1554 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1555 assert(op->stub() != nullptr, "stub required");
1556 __ cmpl(dest->as_register(), 0x80000000);
1557 __ jcc(Assembler::equal, *op->stub()->entry());
1558 __ bind(*op->stub()->continuation());
1559 break;
1560
1561 case Bytecodes::_f2l:
1562 case Bytecodes::_d2l:
1563 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1564 assert(src->fpu() == 0, "input must be on TOS");
1565 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1566
1567 // instruction sequence too long to inline it here
1568 {
1569 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1570 }
1571 break;
1572 #endif // _LP64
1573
1574 default: ShouldNotReachHere();
1575 }
1576 }
1577
1578 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1579 if (op->init_check()) {
1580 add_debug_info_for_null_check_here(op->stub()->info());
1581 // init_state needs acquire, but x86 is TSO, and so we are already good.
1582 __ cmpb(Address(op->klass()->as_register(),
1583 InstanceKlass::init_state_offset()),
1584 InstanceKlass::fully_initialized);
1585 __ jcc(Assembler::notEqual, *op->stub()->entry());
1586 }
1587 __ allocate_object(op->obj()->as_register(),
1588 op->tmp1()->as_register(),
1589 op->tmp2()->as_register(),
1590 op->header_size(),
1591 op->object_size(),
1592 op->klass()->as_register(),
1593 *op->stub()->entry());
1594 __ bind(*op->stub()->continuation());
1595 }
1596
1597 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1598 Register len = op->len()->as_register();
1599 LP64_ONLY( __ movslq(len, len); )
1600
1601 if (UseSlowPath ||
1602 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1603 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1604 __ jmp(*op->stub()->entry());
1605 } else {
1606 Register tmp1 = op->tmp1()->as_register();
1607 Register tmp2 = op->tmp2()->as_register();
1608 Register tmp3 = op->tmp3()->as_register();
1609 if (len == tmp1) {
1610 tmp1 = tmp3;
1611 } else if (len == tmp2) {
1612 tmp2 = tmp3;
1613 } else if (len == tmp3) {
1614 // everything is ok
1615 } else {
1616 __ mov(tmp3, len);
1617 }
1618 __ allocate_array(op->obj()->as_register(),
1619 len,
1620 tmp1,
1621 tmp2,
1622 arrayOopDesc::base_offset_in_bytes(op->type()),
1623 array_element_size(op->type()),
1624 op->klass()->as_register(),
1625 *op->stub()->entry(),
1626 op->zero_array());
1627 }
1628 __ bind(*op->stub()->continuation());
1629 }
1630
1631 void LIR_Assembler::type_profile_helper(Register mdo,
1632 ciMethodData *md, ciProfileData *data,
1633 Register recv, Label* update_done) {
1634 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1635 Label next_test;
1636 // See if the receiver is receiver[n].
1637 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1638 __ jccb(Assembler::notEqual, next_test);
1639 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1640 __ addptr(data_addr, DataLayout::counter_increment);
1641 __ jmp(*update_done);
1642 __ bind(next_test);
1643 }
1644
1645 // Didn't find receiver; find next empty slot and fill it in
1646 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1647 Label next_test;
1648 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1649 __ cmpptr(recv_addr, NULL_WORD);
1650 __ jccb(Assembler::notEqual, next_test);
1651 __ movptr(recv_addr, recv);
1652 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1653 __ jmp(*update_done);
1654 __ bind(next_test);
1655 }
1656 }
1657
1658 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1659 // we always need a stub for the failure case.
1660 CodeStub* stub = op->stub();
1661 Register obj = op->object()->as_register();
1662 Register k_RInfo = op->tmp1()->as_register();
1663 Register klass_RInfo = op->tmp2()->as_register();
1664 Register dst = op->result_opr()->as_register();
1665 ciKlass* k = op->klass();
1666 Register Rtmp1 = noreg;
1667 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1668
1669 // check if it needs to be profiled
1670 ciMethodData* md = nullptr;
1671 ciProfileData* data = nullptr;
1672
1673 if (op->should_profile()) {
1674 ciMethod* method = op->profiled_method();
1675 assert(method != nullptr, "Should have method");
1676 int bci = op->profiled_bci();
1677 md = method->method_data_or_null();
1678 assert(md != nullptr, "Sanity");
1679 data = md->bci_to_data(bci);
1680 assert(data != nullptr, "need data for type check");
1681 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1682 }
1683 Label* success_target = success;
1684 Label* failure_target = failure;
1685
1686 if (obj == k_RInfo) {
1687 k_RInfo = dst;
1688 } else if (obj == klass_RInfo) {
1689 klass_RInfo = dst;
1690 }
1691 if (k->is_loaded() && !UseCompressedClassPointers) {
1692 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1693 } else {
1694 Rtmp1 = op->tmp3()->as_register();
1695 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1696 }
1697
1698 assert_different_registers(obj, k_RInfo, klass_RInfo);
1699
1700 __ testptr(obj, obj);
1701 if (op->should_profile()) {
1702 Label not_null;
1703 Register mdo = klass_RInfo;
1704 __ mov_metadata(mdo, md->constant_encoding());
1705 __ jccb(Assembler::notEqual, not_null);
1706 // Object is null; update MDO and exit
1707 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1708 int header_bits = BitData::null_seen_byte_constant();
1709 __ orb(data_addr, header_bits);
1710 __ jmp(*obj_is_null);
1711 __ bind(not_null);
1712
1713 Label update_done;
1714 Register recv = k_RInfo;
1715 __ load_klass(recv, obj, tmp_load_klass);
1716 type_profile_helper(mdo, md, data, recv, &update_done);
1717
1718 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1719 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1720
1721 __ bind(update_done);
1722 } else {
1723 __ jcc(Assembler::equal, *obj_is_null);
1724 }
1725
1726 if (!k->is_loaded()) {
1727 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1728 } else {
1729 #ifdef _LP64
1730 __ mov_metadata(k_RInfo, k->constant_encoding());
1731 #endif // _LP64
1732 }
1733 __ verify_oop(obj);
1734
1735 if (op->fast_check()) {
1736 // get object class
1737 // not a safepoint as obj null check happens earlier
1738 #ifdef _LP64
1739 if (UseCompressedClassPointers) {
1740 __ load_klass(Rtmp1, obj, tmp_load_klass);
1741 __ cmpptr(k_RInfo, Rtmp1);
1742 } else {
1743 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1744 }
1745 #else
1746 if (k->is_loaded()) {
1747 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1748 } else {
1749 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1750 }
1751 #endif
1752 __ jcc(Assembler::notEqual, *failure_target);
1753 // successful cast, fall through to profile or jump
1754 } else {
1755 // get object class
1756 // not a safepoint as obj null check happens earlier
1757 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1758 if (k->is_loaded()) {
1759 // See if we get an immediate positive hit
1760 #ifdef _LP64
1761 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1762 #else
1763 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1764 #endif // _LP64
1765 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1766 __ jcc(Assembler::notEqual, *failure_target);
1767 // successful cast, fall through to profile or jump
1768 } else {
1769 // See if we get an immediate positive hit
1770 __ jcc(Assembler::equal, *success_target);
1771 // check for self
1772 #ifdef _LP64
1773 __ cmpptr(klass_RInfo, k_RInfo);
1774 #else
1775 __ cmpklass(klass_RInfo, k->constant_encoding());
1776 #endif // _LP64
1777 __ jcc(Assembler::equal, *success_target);
1778
1779 __ push(klass_RInfo);
1780 #ifdef _LP64
1781 __ push(k_RInfo);
1782 #else
1783 __ pushklass(k->constant_encoding(), noreg);
1784 #endif // _LP64
1785 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1786 __ pop(klass_RInfo);
1787 __ pop(klass_RInfo);
1788 // result is a boolean
1789 __ testl(klass_RInfo, klass_RInfo);
1790 __ jcc(Assembler::equal, *failure_target);
1791 // successful cast, fall through to profile or jump
1792 }
1793 } else {
1794 // perform the fast part of the checking logic
1795 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1796 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1797 __ push(klass_RInfo);
1798 __ push(k_RInfo);
1799 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1800 __ pop(klass_RInfo);
1801 __ pop(k_RInfo);
1802 // result is a boolean
1803 __ testl(k_RInfo, k_RInfo);
1804 __ jcc(Assembler::equal, *failure_target);
1805 // successful cast, fall through to profile or jump
1806 }
1807 }
1808 __ jmp(*success);
1809 }
1810
1811
1812 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1813 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1814 LIR_Code code = op->code();
1815 if (code == lir_store_check) {
1816 Register value = op->object()->as_register();
1817 Register array = op->array()->as_register();
1818 Register k_RInfo = op->tmp1()->as_register();
1819 Register klass_RInfo = op->tmp2()->as_register();
1820 Register Rtmp1 = op->tmp3()->as_register();
1821
1822 CodeStub* stub = op->stub();
1823
1824 // check if it needs to be profiled
1825 ciMethodData* md = nullptr;
1826 ciProfileData* data = nullptr;
1827
1828 if (op->should_profile()) {
1829 ciMethod* method = op->profiled_method();
1830 assert(method != nullptr, "Should have method");
1831 int bci = op->profiled_bci();
1832 md = method->method_data_or_null();
1833 assert(md != nullptr, "Sanity");
1834 data = md->bci_to_data(bci);
1835 assert(data != nullptr, "need data for type check");
1836 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1837 }
1838 Label done;
1839 Label* success_target = &done;
1840 Label* failure_target = stub->entry();
1841
1842 __ testptr(value, value);
1843 if (op->should_profile()) {
1844 Label not_null;
1845 Register mdo = klass_RInfo;
1846 __ mov_metadata(mdo, md->constant_encoding());
1847 __ jccb(Assembler::notEqual, not_null);
1848 // Object is null; update MDO and exit
1849 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1850 int header_bits = BitData::null_seen_byte_constant();
1851 __ orb(data_addr, header_bits);
1852 __ jmp(done);
1853 __ bind(not_null);
1854
1855 Label update_done;
1856 Register recv = k_RInfo;
1857 __ load_klass(recv, value, tmp_load_klass);
1858 type_profile_helper(mdo, md, data, recv, &update_done);
1859
1860 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1861 __ addptr(counter_addr, DataLayout::counter_increment);
1862 __ bind(update_done);
1863 } else {
1864 __ jcc(Assembler::equal, done);
1865 }
1866
1867 add_debug_info_for_null_check_here(op->info_for_exception());
1868 __ load_klass(k_RInfo, array, tmp_load_klass);
1869 __ load_klass(klass_RInfo, value, tmp_load_klass);
1870
1871 // get instance klass (it's already uncompressed)
1872 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1873 // perform the fast part of the checking logic
1874 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1875 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1876 __ push(klass_RInfo);
1877 __ push(k_RInfo);
1878 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1879 __ pop(klass_RInfo);
1880 __ pop(k_RInfo);
1881 // result is a boolean
1882 __ testl(k_RInfo, k_RInfo);
1883 __ jcc(Assembler::equal, *failure_target);
1884 // fall through to the success case
1885
1886 __ bind(done);
1887 } else
1888 if (code == lir_checkcast) {
1889 Register obj = op->object()->as_register();
1890 Register dst = op->result_opr()->as_register();
1891 Label success;
1892 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1893 __ bind(success);
1894 if (dst != obj) {
1895 __ mov(dst, obj);
1896 }
1897 } else
1898 if (code == lir_instanceof) {
1899 Register obj = op->object()->as_register();
1900 Register dst = op->result_opr()->as_register();
1901 Label success, failure, done;
1902 emit_typecheck_helper(op, &success, &failure, &failure);
1903 __ bind(failure);
1904 __ xorptr(dst, dst);
1905 __ jmpb(done);
1906 __ bind(success);
1907 __ movptr(dst, 1);
1908 __ bind(done);
1909 } else {
1910 ShouldNotReachHere();
1911 }
1912
1913 }
1914
1915
1916 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1917 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1918 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1919 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1920 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1921 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1922 Register addr = op->addr()->as_register();
1923 __ lock();
1924 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1925
1926 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1927 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1928 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1929 Register newval = op->new_value()->as_register();
1930 Register cmpval = op->cmp_value()->as_register();
1931 assert(cmpval == rax, "wrong register");
1932 assert(newval != noreg, "new val must be register");
1933 assert(cmpval != newval, "cmp and new values must be in different registers");
1934 assert(cmpval != addr, "cmp and addr must be in different registers");
1935 assert(newval != addr, "new value and addr must be in different registers");
1936
1937 if ( op->code() == lir_cas_obj) {
1938 #ifdef _LP64
1939 if (UseCompressedOops) {
1940 __ encode_heap_oop(cmpval);
1941 __ mov(rscratch1, newval);
1942 __ encode_heap_oop(rscratch1);
1943 __ lock();
1944 // cmpval (rax) is implicitly used by this instruction
1945 __ cmpxchgl(rscratch1, Address(addr, 0));
1946 } else
1947 #endif
1948 {
1949 __ lock();
1950 __ cmpxchgptr(newval, Address(addr, 0));
1951 }
1952 } else {
1953 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1954 __ lock();
1955 __ cmpxchgl(newval, Address(addr, 0));
1956 }
1957 #ifdef _LP64
1958 } else if (op->code() == lir_cas_long) {
1959 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1960 Register newval = op->new_value()->as_register_lo();
1961 Register cmpval = op->cmp_value()->as_register_lo();
1962 assert(cmpval == rax, "wrong register");
1963 assert(newval != noreg, "new val must be register");
1964 assert(cmpval != newval, "cmp and new values must be in different registers");
1965 assert(cmpval != addr, "cmp and addr must be in different registers");
1966 assert(newval != addr, "new value and addr must be in different registers");
1967 __ lock();
1968 __ cmpxchgq(newval, Address(addr, 0));
1969 #endif // _LP64
1970 } else {
1971 Unimplemented();
1972 }
1973 }
1974
1975 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1976 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1977 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1978
1979 Assembler::Condition acond, ncond;
1980 switch (condition) {
1981 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1982 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1983 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1984 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1985 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1986 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1987 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1988 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1989 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1990 ShouldNotReachHere();
1991 }
1992
1993 if (opr1->is_cpu_register()) {
1994 reg2reg(opr1, result);
1995 } else if (opr1->is_stack()) {
1996 stack2reg(opr1, result, result->type());
1997 } else if (opr1->is_constant()) {
1998 const2reg(opr1, result, lir_patch_none, nullptr);
1999 } else {
2000 ShouldNotReachHere();
2001 }
2002
2003 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2004 // optimized version that does not require a branch
2005 if (opr2->is_single_cpu()) {
2006 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2007 __ cmov(ncond, result->as_register(), opr2->as_register());
2008 } else if (opr2->is_double_cpu()) {
2009 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2010 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2011 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2012 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2013 } else if (opr2->is_single_stack()) {
2014 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2015 } else if (opr2->is_double_stack()) {
2016 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2017 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2018 } else {
2019 ShouldNotReachHere();
2020 }
2021
2022 } else {
2023 Label skip;
2024 __ jccb(acond, skip);
2025 if (opr2->is_cpu_register()) {
2026 reg2reg(opr2, result);
2027 } else if (opr2->is_stack()) {
2028 stack2reg(opr2, result, result->type());
2029 } else if (opr2->is_constant()) {
2030 const2reg(opr2, result, lir_patch_none, nullptr);
2031 } else {
2032 ShouldNotReachHere();
2033 }
2034 __ bind(skip);
2035 }
2036 }
2037
2038
2039 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2040 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2041
2042 if (left->is_single_cpu()) {
2043 assert(left == dest, "left and dest must be equal");
2044 Register lreg = left->as_register();
2045
2046 if (right->is_single_cpu()) {
2047 // cpu register - cpu register
2048 Register rreg = right->as_register();
2049 switch (code) {
2050 case lir_add: __ addl (lreg, rreg); break;
2051 case lir_sub: __ subl (lreg, rreg); break;
2052 case lir_mul: __ imull(lreg, rreg); break;
2053 default: ShouldNotReachHere();
2054 }
2055
2056 } else if (right->is_stack()) {
2057 // cpu register - stack
2058 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2059 switch (code) {
2060 case lir_add: __ addl(lreg, raddr); break;
2061 case lir_sub: __ subl(lreg, raddr); break;
2062 default: ShouldNotReachHere();
2063 }
2064
2065 } else if (right->is_constant()) {
2066 // cpu register - constant
2067 jint c = right->as_constant_ptr()->as_jint();
2068 switch (code) {
2069 case lir_add: {
2070 __ incrementl(lreg, c);
2071 break;
2072 }
2073 case lir_sub: {
2074 __ decrementl(lreg, c);
2075 break;
2076 }
2077 default: ShouldNotReachHere();
2078 }
2079
2080 } else {
2081 ShouldNotReachHere();
2082 }
2083
2084 } else if (left->is_double_cpu()) {
2085 assert(left == dest, "left and dest must be equal");
2086 Register lreg_lo = left->as_register_lo();
2087 Register lreg_hi = left->as_register_hi();
2088
2089 if (right->is_double_cpu()) {
2090 // cpu register - cpu register
2091 Register rreg_lo = right->as_register_lo();
2092 Register rreg_hi = right->as_register_hi();
2093 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2094 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2095 switch (code) {
2096 case lir_add:
2097 __ addptr(lreg_lo, rreg_lo);
2098 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2099 break;
2100 case lir_sub:
2101 __ subptr(lreg_lo, rreg_lo);
2102 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2103 break;
2104 case lir_mul:
2105 #ifdef _LP64
2106 __ imulq(lreg_lo, rreg_lo);
2107 #else
2108 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2109 __ imull(lreg_hi, rreg_lo);
2110 __ imull(rreg_hi, lreg_lo);
2111 __ addl (rreg_hi, lreg_hi);
2112 __ mull (rreg_lo);
2113 __ addl (lreg_hi, rreg_hi);
2114 #endif // _LP64
2115 break;
2116 default:
2117 ShouldNotReachHere();
2118 }
2119
2120 } else if (right->is_constant()) {
2121 // cpu register - constant
2122 #ifdef _LP64
2123 jlong c = right->as_constant_ptr()->as_jlong_bits();
2124 __ movptr(r10, (intptr_t) c);
2125 switch (code) {
2126 case lir_add:
2127 __ addptr(lreg_lo, r10);
2128 break;
2129 case lir_sub:
2130 __ subptr(lreg_lo, r10);
2131 break;
2132 default:
2133 ShouldNotReachHere();
2134 }
2135 #else
2136 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2137 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2138 switch (code) {
2139 case lir_add:
2140 __ addptr(lreg_lo, c_lo);
2141 __ adcl(lreg_hi, c_hi);
2142 break;
2143 case lir_sub:
2144 __ subptr(lreg_lo, c_lo);
2145 __ sbbl(lreg_hi, c_hi);
2146 break;
2147 default:
2148 ShouldNotReachHere();
2149 }
2150 #endif // _LP64
2151
2152 } else {
2153 ShouldNotReachHere();
2154 }
2155
2156 } else if (left->is_single_xmm()) {
2157 assert(left == dest, "left and dest must be equal");
2158 XMMRegister lreg = left->as_xmm_float_reg();
2159
2160 if (right->is_single_xmm()) {
2161 XMMRegister rreg = right->as_xmm_float_reg();
2162 switch (code) {
2163 case lir_add: __ addss(lreg, rreg); break;
2164 case lir_sub: __ subss(lreg, rreg); break;
2165 case lir_mul: __ mulss(lreg, rreg); break;
2166 case lir_div: __ divss(lreg, rreg); break;
2167 default: ShouldNotReachHere();
2168 }
2169 } else {
2170 Address raddr;
2171 if (right->is_single_stack()) {
2172 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2173 } else if (right->is_constant()) {
2174 // hack for now
2175 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2176 } else {
2177 ShouldNotReachHere();
2178 }
2179 switch (code) {
2180 case lir_add: __ addss(lreg, raddr); break;
2181 case lir_sub: __ subss(lreg, raddr); break;
2182 case lir_mul: __ mulss(lreg, raddr); break;
2183 case lir_div: __ divss(lreg, raddr); break;
2184 default: ShouldNotReachHere();
2185 }
2186 }
2187
2188 } else if (left->is_double_xmm()) {
2189 assert(left == dest, "left and dest must be equal");
2190
2191 XMMRegister lreg = left->as_xmm_double_reg();
2192 if (right->is_double_xmm()) {
2193 XMMRegister rreg = right->as_xmm_double_reg();
2194 switch (code) {
2195 case lir_add: __ addsd(lreg, rreg); break;
2196 case lir_sub: __ subsd(lreg, rreg); break;
2197 case lir_mul: __ mulsd(lreg, rreg); break;
2198 case lir_div: __ divsd(lreg, rreg); break;
2199 default: ShouldNotReachHere();
2200 }
2201 } else {
2202 Address raddr;
2203 if (right->is_double_stack()) {
2204 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2205 } else if (right->is_constant()) {
2206 // hack for now
2207 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2208 } else {
2209 ShouldNotReachHere();
2210 }
2211 switch (code) {
2212 case lir_add: __ addsd(lreg, raddr); break;
2213 case lir_sub: __ subsd(lreg, raddr); break;
2214 case lir_mul: __ mulsd(lreg, raddr); break;
2215 case lir_div: __ divsd(lreg, raddr); break;
2216 default: ShouldNotReachHere();
2217 }
2218 }
2219
2220 #ifndef _LP64
2221 } else if (left->is_single_fpu()) {
2222 assert(dest->is_single_fpu(), "fpu stack allocation required");
2223
2224 if (right->is_single_fpu()) {
2225 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2226
2227 } else {
2228 assert(left->fpu_regnr() == 0, "left must be on TOS");
2229 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2230
2231 Address raddr;
2232 if (right->is_single_stack()) {
2233 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2234 } else if (right->is_constant()) {
2235 address const_addr = float_constant(right->as_jfloat());
2236 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2237 // hack for now
2238 raddr = __ as_Address(InternalAddress(const_addr));
2239 } else {
2240 ShouldNotReachHere();
2241 }
2242
2243 switch (code) {
2244 case lir_add: __ fadd_s(raddr); break;
2245 case lir_sub: __ fsub_s(raddr); break;
2246 case lir_mul: __ fmul_s(raddr); break;
2247 case lir_div: __ fdiv_s(raddr); break;
2248 default: ShouldNotReachHere();
2249 }
2250 }
2251
2252 } else if (left->is_double_fpu()) {
2253 assert(dest->is_double_fpu(), "fpu stack allocation required");
2254
2255 if (code == lir_mul || code == lir_div) {
2256 // Double values require special handling for strictfp mul/div on x86
2257 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2258 __ fmulp(left->fpu_regnrLo() + 1);
2259 }
2260
2261 if (right->is_double_fpu()) {
2262 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2263
2264 } else {
2265 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2266 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2267
2268 Address raddr;
2269 if (right->is_double_stack()) {
2270 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2271 } else if (right->is_constant()) {
2272 // hack for now
2273 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2274 } else {
2275 ShouldNotReachHere();
2276 }
2277
2278 switch (code) {
2279 case lir_add: __ fadd_d(raddr); break;
2280 case lir_sub: __ fsub_d(raddr); break;
2281 case lir_mul: __ fmul_d(raddr); break;
2282 case lir_div: __ fdiv_d(raddr); break;
2283 default: ShouldNotReachHere();
2284 }
2285 }
2286
2287 if (code == lir_mul || code == lir_div) {
2288 // Double values require special handling for strictfp mul/div on x86
2289 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2290 __ fmulp(dest->fpu_regnrLo() + 1);
2291 }
2292 #endif // !_LP64
2293
2294 } else if (left->is_single_stack() || left->is_address()) {
2295 assert(left == dest, "left and dest must be equal");
2296
2297 Address laddr;
2298 if (left->is_single_stack()) {
2299 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2300 } else if (left->is_address()) {
2301 laddr = as_Address(left->as_address_ptr());
2302 } else {
2303 ShouldNotReachHere();
2304 }
2305
2306 if (right->is_single_cpu()) {
2307 Register rreg = right->as_register();
2308 switch (code) {
2309 case lir_add: __ addl(laddr, rreg); break;
2310 case lir_sub: __ subl(laddr, rreg); break;
2311 default: ShouldNotReachHere();
2312 }
2313 } else if (right->is_constant()) {
2314 jint c = right->as_constant_ptr()->as_jint();
2315 switch (code) {
2316 case lir_add: {
2317 __ incrementl(laddr, c);
2318 break;
2319 }
2320 case lir_sub: {
2321 __ decrementl(laddr, c);
2322 break;
2323 }
2324 default: ShouldNotReachHere();
2325 }
2326 } else {
2327 ShouldNotReachHere();
2328 }
2329
2330 } else {
2331 ShouldNotReachHere();
2332 }
2333 }
2334
2335 #ifndef _LP64
2336 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2337 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2338 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2339 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2340
2341 bool left_is_tos = (left_index == 0);
2342 bool dest_is_tos = (dest_index == 0);
2343 int non_tos_index = (left_is_tos ? right_index : left_index);
2344
2345 switch (code) {
2346 case lir_add:
2347 if (pop_fpu_stack) __ faddp(non_tos_index);
2348 else if (dest_is_tos) __ fadd (non_tos_index);
2349 else __ fadda(non_tos_index);
2350 break;
2351
2352 case lir_sub:
2353 if (left_is_tos) {
2354 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2355 else if (dest_is_tos) __ fsub (non_tos_index);
2356 else __ fsubra(non_tos_index);
2357 } else {
2358 if (pop_fpu_stack) __ fsubp (non_tos_index);
2359 else if (dest_is_tos) __ fsubr (non_tos_index);
2360 else __ fsuba (non_tos_index);
2361 }
2362 break;
2363
2364 case lir_mul:
2365 if (pop_fpu_stack) __ fmulp(non_tos_index);
2366 else if (dest_is_tos) __ fmul (non_tos_index);
2367 else __ fmula(non_tos_index);
2368 break;
2369
2370 case lir_div:
2371 if (left_is_tos) {
2372 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2373 else if (dest_is_tos) __ fdiv (non_tos_index);
2374 else __ fdivra(non_tos_index);
2375 } else {
2376 if (pop_fpu_stack) __ fdivp (non_tos_index);
2377 else if (dest_is_tos) __ fdivr (non_tos_index);
2378 else __ fdiva (non_tos_index);
2379 }
2380 break;
2381
2382 case lir_rem:
2383 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2384 __ fremr(noreg);
2385 break;
2386
2387 default:
2388 ShouldNotReachHere();
2389 }
2390 }
2391 #endif // _LP64
2392
2393
2394 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2395 if (value->is_double_xmm()) {
2396 switch(code) {
2397 case lir_abs :
2398 {
2399 #ifdef _LP64
2400 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2401 assert(tmp->is_valid(), "need temporary");
2402 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2403 } else
2404 #endif
2405 {
2406 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2407 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2408 }
2409 assert(!tmp->is_valid(), "do not need temporary");
2410 __ andpd(dest->as_xmm_double_reg(),
2411 ExternalAddress((address)double_signmask_pool),
2412 rscratch1);
2413 }
2414 }
2415 break;
2416
2417 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2418 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2419 default : ShouldNotReachHere();
2420 }
2421
2422 #ifndef _LP64
2423 } else if (value->is_double_fpu()) {
2424 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2425 switch(code) {
2426 case lir_abs : __ fabs() ; break;
2427 case lir_sqrt : __ fsqrt(); break;
2428 default : ShouldNotReachHere();
2429 }
2430 #endif // !_LP64
2431 } else if (code == lir_f2hf) {
2432 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2433 } else if (code == lir_hf2f) {
2434 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2435 } else {
2436 Unimplemented();
2437 }
2438 }
2439
2440 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2441 // assert(left->destroys_register(), "check");
2442 if (left->is_single_cpu()) {
2443 Register reg = left->as_register();
2444 if (right->is_constant()) {
2445 int val = right->as_constant_ptr()->as_jint();
2446 switch (code) {
2447 case lir_logic_and: __ andl (reg, val); break;
2448 case lir_logic_or: __ orl (reg, val); break;
2449 case lir_logic_xor: __ xorl (reg, val); break;
2450 default: ShouldNotReachHere();
2451 }
2452 } else if (right->is_stack()) {
2453 // added support for stack operands
2454 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2455 switch (code) {
2456 case lir_logic_and: __ andl (reg, raddr); break;
2457 case lir_logic_or: __ orl (reg, raddr); break;
2458 case lir_logic_xor: __ xorl (reg, raddr); break;
2459 default: ShouldNotReachHere();
2460 }
2461 } else {
2462 Register rright = right->as_register();
2463 switch (code) {
2464 case lir_logic_and: __ andptr (reg, rright); break;
2465 case lir_logic_or : __ orptr (reg, rright); break;
2466 case lir_logic_xor: __ xorptr (reg, rright); break;
2467 default: ShouldNotReachHere();
2468 }
2469 }
2470 move_regs(reg, dst->as_register());
2471 } else {
2472 Register l_lo = left->as_register_lo();
2473 Register l_hi = left->as_register_hi();
2474 if (right->is_constant()) {
2475 #ifdef _LP64
2476 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2477 switch (code) {
2478 case lir_logic_and:
2479 __ andq(l_lo, rscratch1);
2480 break;
2481 case lir_logic_or:
2482 __ orq(l_lo, rscratch1);
2483 break;
2484 case lir_logic_xor:
2485 __ xorq(l_lo, rscratch1);
2486 break;
2487 default: ShouldNotReachHere();
2488 }
2489 #else
2490 int r_lo = right->as_constant_ptr()->as_jint_lo();
2491 int r_hi = right->as_constant_ptr()->as_jint_hi();
2492 switch (code) {
2493 case lir_logic_and:
2494 __ andl(l_lo, r_lo);
2495 __ andl(l_hi, r_hi);
2496 break;
2497 case lir_logic_or:
2498 __ orl(l_lo, r_lo);
2499 __ orl(l_hi, r_hi);
2500 break;
2501 case lir_logic_xor:
2502 __ xorl(l_lo, r_lo);
2503 __ xorl(l_hi, r_hi);
2504 break;
2505 default: ShouldNotReachHere();
2506 }
2507 #endif // _LP64
2508 } else {
2509 #ifdef _LP64
2510 Register r_lo;
2511 if (is_reference_type(right->type())) {
2512 r_lo = right->as_register();
2513 } else {
2514 r_lo = right->as_register_lo();
2515 }
2516 #else
2517 Register r_lo = right->as_register_lo();
2518 Register r_hi = right->as_register_hi();
2519 assert(l_lo != r_hi, "overwriting registers");
2520 #endif
2521 switch (code) {
2522 case lir_logic_and:
2523 __ andptr(l_lo, r_lo);
2524 NOT_LP64(__ andptr(l_hi, r_hi);)
2525 break;
2526 case lir_logic_or:
2527 __ orptr(l_lo, r_lo);
2528 NOT_LP64(__ orptr(l_hi, r_hi);)
2529 break;
2530 case lir_logic_xor:
2531 __ xorptr(l_lo, r_lo);
2532 NOT_LP64(__ xorptr(l_hi, r_hi);)
2533 break;
2534 default: ShouldNotReachHere();
2535 }
2536 }
2537
2538 Register dst_lo = dst->as_register_lo();
2539 Register dst_hi = dst->as_register_hi();
2540
2541 #ifdef _LP64
2542 move_regs(l_lo, dst_lo);
2543 #else
2544 if (dst_lo == l_hi) {
2545 assert(dst_hi != l_lo, "overwriting registers");
2546 move_regs(l_hi, dst_hi);
2547 move_regs(l_lo, dst_lo);
2548 } else {
2549 assert(dst_lo != l_hi, "overwriting registers");
2550 move_regs(l_lo, dst_lo);
2551 move_regs(l_hi, dst_hi);
2552 }
2553 #endif // _LP64
2554 }
2555 }
2556
2557
2558 // we assume that rax, and rdx can be overwritten
2559 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2560
2561 assert(left->is_single_cpu(), "left must be register");
2562 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2563 assert(result->is_single_cpu(), "result must be register");
2564
2565 // assert(left->destroys_register(), "check");
2566 // assert(right->destroys_register(), "check");
2567
2568 Register lreg = left->as_register();
2569 Register dreg = result->as_register();
2570
2571 if (right->is_constant()) {
2572 jint divisor = right->as_constant_ptr()->as_jint();
2573 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2574 if (code == lir_idiv) {
2575 assert(lreg == rax, "must be rax,");
2576 assert(temp->as_register() == rdx, "tmp register must be rdx");
2577 __ cdql(); // sign extend into rdx:rax
2578 if (divisor == 2) {
2579 __ subl(lreg, rdx);
2580 } else {
2581 __ andl(rdx, divisor - 1);
2582 __ addl(lreg, rdx);
2583 }
2584 __ sarl(lreg, log2i_exact(divisor));
2585 move_regs(lreg, dreg);
2586 } else if (code == lir_irem) {
2587 Label done;
2588 __ mov(dreg, lreg);
2589 __ andl(dreg, 0x80000000 | (divisor - 1));
2590 __ jcc(Assembler::positive, done);
2591 __ decrement(dreg);
2592 __ orl(dreg, ~(divisor - 1));
2593 __ increment(dreg);
2594 __ bind(done);
2595 } else {
2596 ShouldNotReachHere();
2597 }
2598 } else {
2599 Register rreg = right->as_register();
2600 assert(lreg == rax, "left register must be rax,");
2601 assert(rreg != rdx, "right register must not be rdx");
2602 assert(temp->as_register() == rdx, "tmp register must be rdx");
2603
2604 move_regs(lreg, rax);
2605
2606 int idivl_offset = __ corrected_idivl(rreg);
2607 if (ImplicitDiv0Checks) {
2608 add_debug_info_for_div0(idivl_offset, info);
2609 }
2610 if (code == lir_irem) {
2611 move_regs(rdx, dreg); // result is in rdx
2612 } else {
2613 move_regs(rax, dreg);
2614 }
2615 }
2616 }
2617
2618
2619 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2620 if (opr1->is_single_cpu()) {
2621 Register reg1 = opr1->as_register();
2622 if (opr2->is_single_cpu()) {
2623 // cpu register - cpu register
2624 if (is_reference_type(opr1->type())) {
2625 __ cmpoop(reg1, opr2->as_register());
2626 } else {
2627 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2628 __ cmpl(reg1, opr2->as_register());
2629 }
2630 } else if (opr2->is_stack()) {
2631 // cpu register - stack
2632 if (is_reference_type(opr1->type())) {
2633 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2634 } else {
2635 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2636 }
2637 } else if (opr2->is_constant()) {
2638 // cpu register - constant
2639 LIR_Const* c = opr2->as_constant_ptr();
2640 if (c->type() == T_INT) {
2641 jint i = c->as_jint();
2642 if (i == 0) {
2643 __ testl(reg1, reg1);
2644 } else {
2645 __ cmpl(reg1, i);
2646 }
2647 } else if (c->type() == T_METADATA) {
2648 // All we need for now is a comparison with null for equality.
2649 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2650 Metadata* m = c->as_metadata();
2651 if (m == nullptr) {
2652 __ testptr(reg1, reg1);
2653 } else {
2654 ShouldNotReachHere();
2655 }
2656 } else if (is_reference_type(c->type())) {
2657 // In 64bit oops are single register
2658 jobject o = c->as_jobject();
2659 if (o == nullptr) {
2660 __ testptr(reg1, reg1);
2661 } else {
2662 __ cmpoop(reg1, o, rscratch1);
2663 }
2664 } else {
2665 fatal("unexpected type: %s", basictype_to_str(c->type()));
2666 }
2667 // cpu register - address
2668 } else if (opr2->is_address()) {
2669 if (op->info() != nullptr) {
2670 add_debug_info_for_null_check_here(op->info());
2671 }
2672 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2673 } else {
2674 ShouldNotReachHere();
2675 }
2676
2677 } else if(opr1->is_double_cpu()) {
2678 Register xlo = opr1->as_register_lo();
2679 Register xhi = opr1->as_register_hi();
2680 if (opr2->is_double_cpu()) {
2681 #ifdef _LP64
2682 __ cmpptr(xlo, opr2->as_register_lo());
2683 #else
2684 // cpu register - cpu register
2685 Register ylo = opr2->as_register_lo();
2686 Register yhi = opr2->as_register_hi();
2687 __ subl(xlo, ylo);
2688 __ sbbl(xhi, yhi);
2689 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2690 __ orl(xhi, xlo);
2691 }
2692 #endif // _LP64
2693 } else if (opr2->is_constant()) {
2694 // cpu register - constant 0
2695 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2696 #ifdef _LP64
2697 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2698 #else
2699 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2700 __ orl(xhi, xlo);
2701 #endif // _LP64
2702 } else {
2703 ShouldNotReachHere();
2704 }
2705
2706 } else if (opr1->is_single_xmm()) {
2707 XMMRegister reg1 = opr1->as_xmm_float_reg();
2708 if (opr2->is_single_xmm()) {
2709 // xmm register - xmm register
2710 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2711 } else if (opr2->is_stack()) {
2712 // xmm register - stack
2713 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2714 } else if (opr2->is_constant()) {
2715 // xmm register - constant
2716 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2717 } else if (opr2->is_address()) {
2718 // xmm register - address
2719 if (op->info() != nullptr) {
2720 add_debug_info_for_null_check_here(op->info());
2721 }
2722 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2723 } else {
2724 ShouldNotReachHere();
2725 }
2726
2727 } else if (opr1->is_double_xmm()) {
2728 XMMRegister reg1 = opr1->as_xmm_double_reg();
2729 if (opr2->is_double_xmm()) {
2730 // xmm register - xmm register
2731 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2732 } else if (opr2->is_stack()) {
2733 // xmm register - stack
2734 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2735 } else if (opr2->is_constant()) {
2736 // xmm register - constant
2737 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2738 } else if (opr2->is_address()) {
2739 // xmm register - address
2740 if (op->info() != nullptr) {
2741 add_debug_info_for_null_check_here(op->info());
2742 }
2743 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2744 } else {
2745 ShouldNotReachHere();
2746 }
2747
2748 #ifndef _LP64
2749 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2750 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2751 assert(opr2->is_fpu_register(), "both must be registers");
2752 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2753 #endif // LP64
2754
2755 } else if (opr1->is_address() && opr2->is_constant()) {
2756 LIR_Const* c = opr2->as_constant_ptr();
2757 #ifdef _LP64
2758 if (is_reference_type(c->type())) {
2759 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2760 __ movoop(rscratch1, c->as_jobject());
2761 }
2762 #endif // LP64
2763 if (op->info() != nullptr) {
2764 add_debug_info_for_null_check_here(op->info());
2765 }
2766 // special case: address - constant
2767 LIR_Address* addr = opr1->as_address_ptr();
2768 if (c->type() == T_INT) {
2769 __ cmpl(as_Address(addr), c->as_jint());
2770 } else if (is_reference_type(c->type())) {
2771 #ifdef _LP64
2772 // %%% Make this explode if addr isn't reachable until we figure out a
2773 // better strategy by giving noreg as the temp for as_Address
2774 __ cmpoop(rscratch1, as_Address(addr, noreg));
2775 #else
2776 __ cmpoop(as_Address(addr), c->as_jobject());
2777 #endif // _LP64
2778 } else {
2779 ShouldNotReachHere();
2780 }
2781
2782 } else {
2783 ShouldNotReachHere();
2784 }
2785 }
2786
2787 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2788 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2789 if (left->is_single_xmm()) {
2790 assert(right->is_single_xmm(), "must match");
2791 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2792 } else if (left->is_double_xmm()) {
2793 assert(right->is_double_xmm(), "must match");
2794 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2795
2796 } else {
2797 #ifdef _LP64
2798 ShouldNotReachHere();
2799 #else
2800 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2801 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2802
2803 assert(left->fpu() == 0, "left must be on TOS");
2804 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2805 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2806 #endif // LP64
2807 }
2808 } else {
2809 assert(code == lir_cmp_l2i, "check");
2810 #ifdef _LP64
2811 Label done;
2812 Register dest = dst->as_register();
2813 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2814 __ movl(dest, -1);
2815 __ jccb(Assembler::less, done);
2816 __ setb(Assembler::notZero, dest);
2817 __ movzbl(dest, dest);
2818 __ bind(done);
2819 #else
2820 __ lcmp2int(left->as_register_hi(),
2821 left->as_register_lo(),
2822 right->as_register_hi(),
2823 right->as_register_lo());
2824 move_regs(left->as_register_hi(), dst->as_register());
2825 #endif // _LP64
2826 }
2827 }
2828
2829
2830 void LIR_Assembler::align_call(LIR_Code code) {
2831 // make sure that the displacement word of the call ends up word aligned
2832 int offset = __ offset();
2833 switch (code) {
2834 case lir_static_call:
2835 case lir_optvirtual_call:
2836 case lir_dynamic_call:
2837 offset += NativeCall::displacement_offset;
2838 break;
2839 case lir_icvirtual_call:
2840 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2841 break;
2842 default: ShouldNotReachHere();
2843 }
2844 __ align(BytesPerWord, offset);
2845 }
2846
2847
2848 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2849 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2850 "must be aligned");
2851 __ call(AddressLiteral(op->addr(), rtype));
2852 add_call_info(code_offset(), op->info());
2853 __ post_call_nop();
2854 }
2855
2856
2857 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2858 __ ic_call(op->addr());
2859 add_call_info(code_offset(), op->info());
2860 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2861 "must be aligned");
2862 __ post_call_nop();
2863 }
2864
2865
2866 void LIR_Assembler::emit_static_call_stub() {
2867 address call_pc = __ pc();
2868 address stub = __ start_a_stub(call_stub_size());
2869 if (stub == nullptr) {
2870 bailout("static call stub overflow");
2871 return;
2872 }
2873
2874 int start = __ offset();
2875
2876 // make sure that the displacement word of the call ends up word aligned
2877 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2878 __ relocate(static_stub_Relocation::spec(call_pc));
2879 __ mov_metadata(rbx, (Metadata*)nullptr);
2880 // must be set to -1 at code generation time
2881 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2882 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2883 __ jump(RuntimeAddress(__ pc()));
2884
2885 assert(__ offset() - start <= call_stub_size(), "stub too big");
2886 __ end_a_stub();
2887 }
2888
2889
2890 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2891 assert(exceptionOop->as_register() == rax, "must match");
2892 assert(exceptionPC->as_register() == rdx, "must match");
2893
2894 // exception object is not added to oop map by LinearScan
2895 // (LinearScan assumes that no oops are in fixed registers)
2896 info->add_register_oop(exceptionOop);
2897 C1StubId unwind_id;
2898
2899 // get current pc information
2900 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2901 int pc_for_athrow_offset = __ offset();
2902 InternalAddress pc_for_athrow(__ pc());
2903 __ lea(exceptionPC->as_register(), pc_for_athrow);
2904 add_call_info(pc_for_athrow_offset, info); // for exception handler
2905
2906 __ verify_not_null_oop(rax);
2907 // search an exception handler (rax: exception oop, rdx: throwing pc)
2908 if (compilation()->has_fpu_code()) {
2909 unwind_id = C1StubId::handle_exception_id;
2910 } else {
2911 unwind_id = C1StubId::handle_exception_nofpu_id;
2912 }
2913 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2914
2915 // enough room for two byte trap
2916 __ nop();
2917 }
2918
2919
2920 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2921 assert(exceptionOop->as_register() == rax, "must match");
2922
2923 __ jmp(_unwind_handler_entry);
2924 }
2925
2926
2927 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2928
2929 // optimized version for linear scan:
2930 // * count must be already in ECX (guaranteed by LinearScan)
2931 // * left and dest must be equal
2932 // * tmp must be unused
2933 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2934 assert(left == dest, "left and dest must be equal");
2935 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2936
2937 if (left->is_single_cpu()) {
2938 Register value = left->as_register();
2939 assert(value != SHIFT_count, "left cannot be ECX");
2940
2941 switch (code) {
2942 case lir_shl: __ shll(value); break;
2943 case lir_shr: __ sarl(value); break;
2944 case lir_ushr: __ shrl(value); break;
2945 default: ShouldNotReachHere();
2946 }
2947 } else if (left->is_double_cpu()) {
2948 Register lo = left->as_register_lo();
2949 Register hi = left->as_register_hi();
2950 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2951 #ifdef _LP64
2952 switch (code) {
2953 case lir_shl: __ shlptr(lo); break;
2954 case lir_shr: __ sarptr(lo); break;
2955 case lir_ushr: __ shrptr(lo); break;
2956 default: ShouldNotReachHere();
2957 }
2958 #else
2959
2960 switch (code) {
2961 case lir_shl: __ lshl(hi, lo); break;
2962 case lir_shr: __ lshr(hi, lo, true); break;
2963 case lir_ushr: __ lshr(hi, lo, false); break;
2964 default: ShouldNotReachHere();
2965 }
2966 #endif // LP64
2967 } else {
2968 ShouldNotReachHere();
2969 }
2970 }
2971
2972
2973 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2974 if (dest->is_single_cpu()) {
2975 // first move left into dest so that left is not destroyed by the shift
2976 Register value = dest->as_register();
2977 count = count & 0x1F; // Java spec
2978
2979 move_regs(left->as_register(), value);
2980 switch (code) {
2981 case lir_shl: __ shll(value, count); break;
2982 case lir_shr: __ sarl(value, count); break;
2983 case lir_ushr: __ shrl(value, count); break;
2984 default: ShouldNotReachHere();
2985 }
2986 } else if (dest->is_double_cpu()) {
2987 #ifndef _LP64
2988 Unimplemented();
2989 #else
2990 // first move left into dest so that left is not destroyed by the shift
2991 Register value = dest->as_register_lo();
2992 count = count & 0x1F; // Java spec
2993
2994 move_regs(left->as_register_lo(), value);
2995 switch (code) {
2996 case lir_shl: __ shlptr(value, count); break;
2997 case lir_shr: __ sarptr(value, count); break;
2998 case lir_ushr: __ shrptr(value, count); break;
2999 default: ShouldNotReachHere();
3000 }
3001 #endif // _LP64
3002 } else {
3003 ShouldNotReachHere();
3004 }
3005 }
3006
3007
3008 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3009 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3010 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3011 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3012 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3013 }
3014
3015
3016 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3017 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3018 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3019 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3020 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3021 }
3022
3023
3024 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3025 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3026 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3027 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3028 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3029 }
3030
3031
3032 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3033 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3034 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3035 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3036 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3037 }
3038
3039
3040 // This code replaces a call to arraycopy; no exception may
3041 // be thrown in this code, they must be thrown in the System.arraycopy
3042 // activation frame; we could save some checks if this would not be the case
3043 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3044 ciArrayKlass* default_type = op->expected_type();
3045 Register src = op->src()->as_register();
3046 Register dst = op->dst()->as_register();
3047 Register src_pos = op->src_pos()->as_register();
3048 Register dst_pos = op->dst_pos()->as_register();
3049 Register length = op->length()->as_register();
3050 Register tmp = op->tmp()->as_register();
3051 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3052
3053 CodeStub* stub = op->stub();
3054 int flags = op->flags();
3055 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3056 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3057
3058 // if we don't know anything, just go through the generic arraycopy
3059 if (default_type == nullptr) {
3060 // save outgoing arguments on stack in case call to System.arraycopy is needed
3061 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3062 // for interpreter calling conventions. Now we have to do it in new style conventions.
3063 // For the moment until C1 gets the new register allocator I just force all the
3064 // args to the right place (except the register args) and then on the back side
3065 // reload the register args properly if we go slow path. Yuck
3066
3067 // These are proper for the calling convention
3068 store_parameter(length, 2);
3069 store_parameter(dst_pos, 1);
3070 store_parameter(dst, 0);
3071
3072 // these are just temporary placements until we need to reload
3073 store_parameter(src_pos, 3);
3074 store_parameter(src, 4);
3075 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3076
3077 address copyfunc_addr = StubRoutines::generic_arraycopy();
3078 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3079
3080 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3081 #ifdef _LP64
3082 // The arguments are in java calling convention so we can trivially shift them to C
3083 // convention
3084 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3085 __ mov(c_rarg0, j_rarg0);
3086 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3087 __ mov(c_rarg1, j_rarg1);
3088 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3089 __ mov(c_rarg2, j_rarg2);
3090 assert_different_registers(c_rarg3, j_rarg4);
3091 __ mov(c_rarg3, j_rarg3);
3092 #ifdef _WIN64
3093 // Allocate abi space for args but be sure to keep stack aligned
3094 __ subptr(rsp, 6*wordSize);
3095 store_parameter(j_rarg4, 4);
3096 #ifndef PRODUCT
3097 if (PrintC1Statistics) {
3098 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3099 }
3100 #endif
3101 __ call(RuntimeAddress(copyfunc_addr));
3102 __ addptr(rsp, 6*wordSize);
3103 #else
3104 __ mov(c_rarg4, j_rarg4);
3105 #ifndef PRODUCT
3106 if (PrintC1Statistics) {
3107 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3108 }
3109 #endif
3110 __ call(RuntimeAddress(copyfunc_addr));
3111 #endif // _WIN64
3112 #else
3113 __ push(length);
3114 __ push(dst_pos);
3115 __ push(dst);
3116 __ push(src_pos);
3117 __ push(src);
3118
3119 #ifndef PRODUCT
3120 if (PrintC1Statistics) {
3121 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3122 }
3123 #endif
3124 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3125
3126 #endif // _LP64
3127
3128 __ testl(rax, rax);
3129 __ jcc(Assembler::equal, *stub->continuation());
3130
3131 __ mov(tmp, rax);
3132 __ xorl(tmp, -1);
3133
3134 // Reload values from the stack so they are where the stub
3135 // expects them.
3136 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3137 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3138 __ movptr (length, Address(rsp, 2*BytesPerWord));
3139 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3140 __ movptr (src, Address(rsp, 4*BytesPerWord));
3141
3142 __ subl(length, tmp);
3143 __ addl(src_pos, tmp);
3144 __ addl(dst_pos, tmp);
3145 __ jmp(*stub->entry());
3146
3147 __ bind(*stub->continuation());
3148 return;
3149 }
3150
3151 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3152
3153 int elem_size = type2aelembytes(basic_type);
3154 Address::ScaleFactor scale;
3155
3156 switch (elem_size) {
3157 case 1 :
3158 scale = Address::times_1;
3159 break;
3160 case 2 :
3161 scale = Address::times_2;
3162 break;
3163 case 4 :
3164 scale = Address::times_4;
3165 break;
3166 case 8 :
3167 scale = Address::times_8;
3168 break;
3169 default:
3170 scale = Address::no_scale;
3171 ShouldNotReachHere();
3172 }
3173
3174 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3175 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3176 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3177 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3178
3179 // length and pos's are all sign extended at this point on 64bit
3180
3181 // test for null
3182 if (flags & LIR_OpArrayCopy::src_null_check) {
3183 __ testptr(src, src);
3184 __ jcc(Assembler::zero, *stub->entry());
3185 }
3186 if (flags & LIR_OpArrayCopy::dst_null_check) {
3187 __ testptr(dst, dst);
3188 __ jcc(Assembler::zero, *stub->entry());
3189 }
3190
3191 // If the compiler was not able to prove that exact type of the source or the destination
3192 // of the arraycopy is an array type, check at runtime if the source or the destination is
3193 // an instance type.
3194 if (flags & LIR_OpArrayCopy::type_check) {
3195 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3196 __ load_klass(tmp, dst, tmp_load_klass);
3197 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3198 __ jcc(Assembler::greaterEqual, *stub->entry());
3199 }
3200
3201 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3202 __ load_klass(tmp, src, tmp_load_klass);
3203 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3204 __ jcc(Assembler::greaterEqual, *stub->entry());
3205 }
3206 }
3207
3208 // check if negative
3209 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3210 __ testl(src_pos, src_pos);
3211 __ jcc(Assembler::less, *stub->entry());
3212 }
3213 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3214 __ testl(dst_pos, dst_pos);
3215 __ jcc(Assembler::less, *stub->entry());
3216 }
3217
3218 if (flags & LIR_OpArrayCopy::src_range_check) {
3219 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3220 __ cmpl(tmp, src_length_addr);
3221 __ jcc(Assembler::above, *stub->entry());
3222 }
3223 if (flags & LIR_OpArrayCopy::dst_range_check) {
3224 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3225 __ cmpl(tmp, dst_length_addr);
3226 __ jcc(Assembler::above, *stub->entry());
3227 }
3228
3229 if (flags & LIR_OpArrayCopy::length_positive_check) {
3230 __ testl(length, length);
3231 __ jcc(Assembler::less, *stub->entry());
3232 }
3233
3234 #ifdef _LP64
3235 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3236 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3237 #endif
3238
3239 if (flags & LIR_OpArrayCopy::type_check) {
3240 // We don't know the array types are compatible
3241 if (basic_type != T_OBJECT) {
3242 // Simple test for basic type arrays
3243 if (UseCompressedClassPointers) {
3244 __ movl(tmp, src_klass_addr);
3245 __ cmpl(tmp, dst_klass_addr);
3246 } else {
3247 __ movptr(tmp, src_klass_addr);
3248 __ cmpptr(tmp, dst_klass_addr);
3249 }
3250 __ jcc(Assembler::notEqual, *stub->entry());
3251 } else {
3252 // For object arrays, if src is a sub class of dst then we can
3253 // safely do the copy.
3254 Label cont, slow;
3255
3256 __ push(src);
3257 __ push(dst);
3258
3259 __ load_klass(src, src, tmp_load_klass);
3260 __ load_klass(dst, dst, tmp_load_klass);
3261
3262 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3263
3264 __ push(src);
3265 __ push(dst);
3266 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3267 __ pop(dst);
3268 __ pop(src);
3269
3270 __ testl(src, src);
3271 __ jcc(Assembler::notEqual, cont);
3272
3273 __ bind(slow);
3274 __ pop(dst);
3275 __ pop(src);
3276
3277 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3278 if (copyfunc_addr != nullptr) { // use stub if available
3279 // src is not a sub class of dst so we have to do a
3280 // per-element check.
3281
3282 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3283 if ((flags & mask) != mask) {
3284 // Check that at least both of them object arrays.
3285 assert(flags & mask, "one of the two should be known to be an object array");
3286
3287 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3288 __ load_klass(tmp, src, tmp_load_klass);
3289 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3290 __ load_klass(tmp, dst, tmp_load_klass);
3291 }
3292 int lh_offset = in_bytes(Klass::layout_helper_offset());
3293 Address klass_lh_addr(tmp, lh_offset);
3294 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3295 __ cmpl(klass_lh_addr, objArray_lh);
3296 __ jcc(Assembler::notEqual, *stub->entry());
3297 }
3298
3299 // Spill because stubs can use any register they like and it's
3300 // easier to restore just those that we care about.
3301 store_parameter(dst, 0);
3302 store_parameter(dst_pos, 1);
3303 store_parameter(length, 2);
3304 store_parameter(src_pos, 3);
3305 store_parameter(src, 4);
3306
3307 #ifndef _LP64
3308 __ movptr(tmp, dst_klass_addr);
3309 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3310 __ push(tmp);
3311 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3312 __ push(tmp);
3313 __ push(length);
3314 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3315 __ push(tmp);
3316 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3317 __ push(tmp);
3318
3319 __ call_VM_leaf(copyfunc_addr, 5);
3320 #else
3321 __ movl2ptr(length, length); //higher 32bits must be null
3322
3323 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3324 assert_different_registers(c_rarg0, dst, dst_pos, length);
3325 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3326 assert_different_registers(c_rarg1, dst, length);
3327
3328 __ mov(c_rarg2, length);
3329 assert_different_registers(c_rarg2, dst);
3330
3331 #ifdef _WIN64
3332 // Allocate abi space for args but be sure to keep stack aligned
3333 __ subptr(rsp, 6*wordSize);
3334 __ load_klass(c_rarg3, dst, tmp_load_klass);
3335 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3336 store_parameter(c_rarg3, 4);
3337 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3338 __ call(RuntimeAddress(copyfunc_addr));
3339 __ addptr(rsp, 6*wordSize);
3340 #else
3341 __ load_klass(c_rarg4, dst, tmp_load_klass);
3342 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3343 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3344 __ call(RuntimeAddress(copyfunc_addr));
3345 #endif
3346
3347 #endif
3348
3349 #ifndef PRODUCT
3350 if (PrintC1Statistics) {
3351 Label failed;
3352 __ testl(rax, rax);
3353 __ jcc(Assembler::notZero, failed);
3354 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3355 __ bind(failed);
3356 }
3357 #endif
3358
3359 __ testl(rax, rax);
3360 __ jcc(Assembler::zero, *stub->continuation());
3361
3362 #ifndef PRODUCT
3363 if (PrintC1Statistics) {
3364 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3365 }
3366 #endif
3367
3368 __ mov(tmp, rax);
3369
3370 __ xorl(tmp, -1);
3371
3372 // Restore previously spilled arguments
3373 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3374 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3375 __ movptr (length, Address(rsp, 2*BytesPerWord));
3376 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3377 __ movptr (src, Address(rsp, 4*BytesPerWord));
3378
3379
3380 __ subl(length, tmp);
3381 __ addl(src_pos, tmp);
3382 __ addl(dst_pos, tmp);
3383 }
3384
3385 __ jmp(*stub->entry());
3386
3387 __ bind(cont);
3388 __ pop(dst);
3389 __ pop(src);
3390 }
3391 }
3392
3393 #ifdef ASSERT
3394 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3395 // Sanity check the known type with the incoming class. For the
3396 // primitive case the types must match exactly with src.klass and
3397 // dst.klass each exactly matching the default type. For the
3398 // object array case, if no type check is needed then either the
3399 // dst type is exactly the expected type and the src type is a
3400 // subtype which we can't check or src is the same array as dst
3401 // but not necessarily exactly of type default_type.
3402 Label known_ok, halt;
3403 __ mov_metadata(tmp, default_type->constant_encoding());
3404 #ifdef _LP64
3405 if (UseCompressedClassPointers) {
3406 __ encode_klass_not_null(tmp, rscratch1);
3407 }
3408 #endif
3409
3410 if (basic_type != T_OBJECT) {
3411
3412 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3413 else __ cmpptr(tmp, dst_klass_addr);
3414 __ jcc(Assembler::notEqual, halt);
3415 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3416 else __ cmpptr(tmp, src_klass_addr);
3417 __ jcc(Assembler::equal, known_ok);
3418 } else {
3419 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3420 else __ cmpptr(tmp, dst_klass_addr);
3421 __ jcc(Assembler::equal, known_ok);
3422 __ cmpptr(src, dst);
3423 __ jcc(Assembler::equal, known_ok);
3424 }
3425 __ bind(halt);
3426 __ stop("incorrect type information in arraycopy");
3427 __ bind(known_ok);
3428 }
3429 #endif
3430
3431 #ifndef PRODUCT
3432 if (PrintC1Statistics) {
3433 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3434 }
3435 #endif
3436
3437 #ifdef _LP64
3438 assert_different_registers(c_rarg0, dst, dst_pos, length);
3439 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3440 assert_different_registers(c_rarg1, length);
3441 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3442 __ mov(c_rarg2, length);
3443
3444 #else
3445 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3446 store_parameter(tmp, 0);
3447 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3448 store_parameter(tmp, 1);
3449 store_parameter(length, 2);
3450 #endif // _LP64
3451
3452 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3453 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3454 const char *name;
3455 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3456 __ call_VM_leaf(entry, 0);
3457
3458 if (stub != nullptr) {
3459 __ bind(*stub->continuation());
3460 }
3461 }
3462
3463 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3464 assert(op->crc()->is_single_cpu(), "crc must be register");
3465 assert(op->val()->is_single_cpu(), "byte value must be register");
3466 assert(op->result_opr()->is_single_cpu(), "result must be register");
3467 Register crc = op->crc()->as_register();
3468 Register val = op->val()->as_register();
3469 Register res = op->result_opr()->as_register();
3470
3471 assert_different_registers(val, crc, res);
3472
3473 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3474 __ notl(crc); // ~crc
3475 __ update_byte_crc32(crc, val, res);
3476 __ notl(crc); // ~crc
3477 __ mov(res, crc);
3478 }
3479
3480 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3481 Register obj = op->obj_opr()->as_register(); // may not be an oop
3482 Register hdr = op->hdr_opr()->as_register();
3483 Register lock = op->lock_opr()->as_register();
3484 if (LockingMode == LM_MONITOR) {
3485 if (op->info() != nullptr) {
3486 add_debug_info_for_null_check_here(op->info());
3487 __ null_check(obj);
3488 }
3489 __ jmp(*op->stub()->entry());
3490 } else if (op->code() == lir_lock) {
3491 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3492 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3493 // add debug info for NullPointerException only if one is possible
3494 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3495 if (op->info() != nullptr) {
3496 add_debug_info_for_null_check(null_check_offset, op->info());
3497 }
3498 // done
3499 } else if (op->code() == lir_unlock) {
3500 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3501 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3502 } else {
3503 Unimplemented();
3504 }
3505 __ bind(*op->stub()->continuation());
3506 }
3507
3508 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3509 Register obj = op->obj()->as_pointer_register();
3510 Register result = op->result_opr()->as_pointer_register();
3511
3512 CodeEmitInfo* info = op->info();
3513 if (info != nullptr) {
3514 add_debug_info_for_null_check_here(info);
3515 }
3516
3517 #ifdef _LP64
3518 if (UseCompressedClassPointers) {
3519 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3520 __ decode_klass_not_null(result, rscratch1);
3521 } else
3522 #endif
3523 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3524 }
3525
3526 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3527 ciMethod* method = op->profiled_method();
3528 int bci = op->profiled_bci();
3529 ciMethod* callee = op->profiled_callee();
3530 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3531
3532 // Update counter for all call types
3533 ciMethodData* md = method->method_data_or_null();
3534 assert(md != nullptr, "Sanity");
3535 ciProfileData* data = md->bci_to_data(bci);
3536 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3537 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3538 Register mdo = op->mdo()->as_register();
3539 __ mov_metadata(mdo, md->constant_encoding());
3540 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3541 // Perform additional virtual call profiling for invokevirtual and
3542 // invokeinterface bytecodes
3543 if (op->should_profile_receiver_type()) {
3544 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3545 Register recv = op->recv()->as_register();
3546 assert_different_registers(mdo, recv);
3547 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3548 ciKlass* known_klass = op->known_holder();
3549 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3550 // We know the type that will be seen at this call site; we can
3551 // statically update the MethodData* rather than needing to do
3552 // dynamic tests on the receiver type
3553
3554 // NOTE: we should probably put a lock around this search to
3555 // avoid collisions by concurrent compilations
3556 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3557 uint i;
3558 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3559 ciKlass* receiver = vc_data->receiver(i);
3560 if (known_klass->equals(receiver)) {
3561 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3562 __ addptr(data_addr, DataLayout::counter_increment);
3563 return;
3564 }
3565 }
3566
3567 // Receiver type not found in profile data; select an empty slot
3568
3569 // Note that this is less efficient than it should be because it
3570 // always does a write to the receiver part of the
3571 // VirtualCallData rather than just the first time
3572 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3573 ciKlass* receiver = vc_data->receiver(i);
3574 if (receiver == nullptr) {
3575 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3576 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3577 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3578 __ addptr(data_addr, DataLayout::counter_increment);
3579 return;
3580 }
3581 }
3582 } else {
3583 __ load_klass(recv, recv, tmp_load_klass);
3584 Label update_done;
3585 type_profile_helper(mdo, md, data, recv, &update_done);
3586 // Receiver did not match any saved receiver and there is no empty row for it.
3587 // Increment total counter to indicate polymorphic case.
3588 __ addptr(counter_addr, DataLayout::counter_increment);
3589
3590 __ bind(update_done);
3591 }
3592 } else {
3593 // Static call
3594 __ addptr(counter_addr, DataLayout::counter_increment);
3595 }
3596 }
3597
3598 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3599 Register obj = op->obj()->as_register();
3600 Register tmp = op->tmp()->as_pointer_register();
3601 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3602 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3603 ciKlass* exact_klass = op->exact_klass();
3604 intptr_t current_klass = op->current_klass();
3605 bool not_null = op->not_null();
3606 bool no_conflict = op->no_conflict();
3607
3608 Label update, next, none;
3609
3610 bool do_null = !not_null;
3611 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3612 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3613
3614 assert(do_null || do_update, "why are we here?");
3615 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3616
3617 __ verify_oop(obj);
3618
3619 #ifdef ASSERT
3620 if (obj == tmp) {
3621 #ifdef _LP64
3622 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3623 #else
3624 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3625 #endif
3626 } else {
3627 #ifdef _LP64
3628 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3629 #else
3630 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3631 #endif
3632 }
3633 #endif
3634 if (do_null) {
3635 __ testptr(obj, obj);
3636 __ jccb(Assembler::notZero, update);
3637 if (!TypeEntries::was_null_seen(current_klass)) {
3638 __ testptr(mdo_addr, TypeEntries::null_seen);
3639 #ifndef ASSERT
3640 __ jccb(Assembler::notZero, next); // already set
3641 #else
3642 __ jcc(Assembler::notZero, next); // already set
3643 #endif
3644 // atomic update to prevent overwriting Klass* with 0
3645 __ lock();
3646 __ orptr(mdo_addr, TypeEntries::null_seen);
3647 }
3648 if (do_update) {
3649 #ifndef ASSERT
3650 __ jmpb(next);
3651 }
3652 #else
3653 __ jmp(next);
3654 }
3655 } else {
3656 __ testptr(obj, obj);
3657 __ jcc(Assembler::notZero, update);
3658 __ stop("unexpected null obj");
3659 #endif
3660 }
3661
3662 __ bind(update);
3663
3664 if (do_update) {
3665 #ifdef ASSERT
3666 if (exact_klass != nullptr) {
3667 Label ok;
3668 __ load_klass(tmp, obj, tmp_load_klass);
3669 __ push(tmp);
3670 __ mov_metadata(tmp, exact_klass->constant_encoding());
3671 __ cmpptr(tmp, Address(rsp, 0));
3672 __ jcc(Assembler::equal, ok);
3673 __ stop("exact klass and actual klass differ");
3674 __ bind(ok);
3675 __ pop(tmp);
3676 }
3677 #endif
3678 if (!no_conflict) {
3679 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3680 if (exact_klass != nullptr) {
3681 __ mov_metadata(tmp, exact_klass->constant_encoding());
3682 } else {
3683 __ load_klass(tmp, obj, tmp_load_klass);
3684 }
3685 #ifdef _LP64
3686 __ mov(rscratch1, tmp); // save original value before XOR
3687 #endif
3688 __ xorptr(tmp, mdo_addr);
3689 __ testptr(tmp, TypeEntries::type_klass_mask);
3690 // klass seen before, nothing to do. The unknown bit may have been
3691 // set already but no need to check.
3692 __ jccb(Assembler::zero, next);
3693
3694 __ testptr(tmp, TypeEntries::type_unknown);
3695 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3696
3697 if (TypeEntries::is_type_none(current_klass)) {
3698 __ testptr(mdo_addr, TypeEntries::type_mask);
3699 __ jccb(Assembler::zero, none);
3700 #ifdef _LP64
3701 // There is a chance that the checks above (re-reading profiling
3702 // data from memory) fail if another thread has just set the
3703 // profiling to this obj's klass
3704 __ mov(tmp, rscratch1); // get back original value before XOR
3705 __ xorptr(tmp, mdo_addr);
3706 __ testptr(tmp, TypeEntries::type_klass_mask);
3707 __ jccb(Assembler::zero, next);
3708 #endif
3709 }
3710 } else {
3711 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3712 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3713
3714 __ testptr(mdo_addr, TypeEntries::type_unknown);
3715 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3716 }
3717
3718 // different than before. Cannot keep accurate profile.
3719 __ orptr(mdo_addr, TypeEntries::type_unknown);
3720
3721 if (TypeEntries::is_type_none(current_klass)) {
3722 __ jmpb(next);
3723
3724 __ bind(none);
3725 // first time here. Set profile type.
3726 __ movptr(mdo_addr, tmp);
3727 #ifdef ASSERT
3728 __ andptr(tmp, TypeEntries::type_klass_mask);
3729 __ verify_klass_ptr(tmp);
3730 #endif
3731 }
3732 } else {
3733 // There's a single possible klass at this profile point
3734 assert(exact_klass != nullptr, "should be");
3735 if (TypeEntries::is_type_none(current_klass)) {
3736 __ mov_metadata(tmp, exact_klass->constant_encoding());
3737 __ xorptr(tmp, mdo_addr);
3738 __ testptr(tmp, TypeEntries::type_klass_mask);
3739 #ifdef ASSERT
3740 __ jcc(Assembler::zero, next);
3741
3742 {
3743 Label ok;
3744 __ push(tmp);
3745 __ testptr(mdo_addr, TypeEntries::type_mask);
3746 __ jcc(Assembler::zero, ok);
3747 // may have been set by another thread
3748 __ mov_metadata(tmp, exact_klass->constant_encoding());
3749 __ xorptr(tmp, mdo_addr);
3750 __ testptr(tmp, TypeEntries::type_mask);
3751 __ jcc(Assembler::zero, ok);
3752
3753 __ stop("unexpected profiling mismatch");
3754 __ bind(ok);
3755 __ pop(tmp);
3756 }
3757 #else
3758 __ jccb(Assembler::zero, next);
3759 #endif
3760 // first time here. Set profile type.
3761 __ movptr(mdo_addr, tmp);
3762 #ifdef ASSERT
3763 __ andptr(tmp, TypeEntries::type_klass_mask);
3764 __ verify_klass_ptr(tmp);
3765 #endif
3766 } else {
3767 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3768 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3769
3770 __ testptr(mdo_addr, TypeEntries::type_unknown);
3771 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3772
3773 __ orptr(mdo_addr, TypeEntries::type_unknown);
3774 }
3775 }
3776 }
3777 __ bind(next);
3778 }
3779
3780 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3781 Unimplemented();
3782 }
3783
3784
3785 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3786 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3787 }
3788
3789
3790 void LIR_Assembler::align_backward_branch_target() {
3791 __ align(BytesPerWord);
3792 }
3793
3794
3795 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3796 if (left->is_single_cpu()) {
3797 __ negl(left->as_register());
3798 move_regs(left->as_register(), dest->as_register());
3799
3800 } else if (left->is_double_cpu()) {
3801 Register lo = left->as_register_lo();
3802 #ifdef _LP64
3803 Register dst = dest->as_register_lo();
3804 __ movptr(dst, lo);
3805 __ negptr(dst);
3806 #else
3807 Register hi = left->as_register_hi();
3808 __ lneg(hi, lo);
3809 if (dest->as_register_lo() == hi) {
3810 assert(dest->as_register_hi() != lo, "destroying register");
3811 move_regs(hi, dest->as_register_hi());
3812 move_regs(lo, dest->as_register_lo());
3813 } else {
3814 move_regs(lo, dest->as_register_lo());
3815 move_regs(hi, dest->as_register_hi());
3816 }
3817 #endif // _LP64
3818
3819 } else if (dest->is_single_xmm()) {
3820 #ifdef _LP64
3821 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3822 assert(tmp->is_valid(), "need temporary");
3823 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3824 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3825 }
3826 else
3827 #endif
3828 {
3829 assert(!tmp->is_valid(), "do not need temporary");
3830 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3831 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3832 }
3833 __ xorps(dest->as_xmm_float_reg(),
3834 ExternalAddress((address)float_signflip_pool),
3835 rscratch1);
3836 }
3837 } else if (dest->is_double_xmm()) {
3838 #ifdef _LP64
3839 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3840 assert(tmp->is_valid(), "need temporary");
3841 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3842 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3843 }
3844 else
3845 #endif
3846 {
3847 assert(!tmp->is_valid(), "do not need temporary");
3848 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3849 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3850 }
3851 __ xorpd(dest->as_xmm_double_reg(),
3852 ExternalAddress((address)double_signflip_pool),
3853 rscratch1);
3854 }
3855 #ifndef _LP64
3856 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3857 assert(left->fpu() == 0, "arg must be on TOS");
3858 assert(dest->fpu() == 0, "dest must be TOS");
3859 __ fchs();
3860 #endif // !_LP64
3861
3862 } else {
3863 ShouldNotReachHere();
3864 }
3865 }
3866
3867
3868 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3869 assert(src->is_address(), "must be an address");
3870 assert(dest->is_register(), "must be a register");
3871
3872 PatchingStub* patch = nullptr;
3873 if (patch_code != lir_patch_none) {
3874 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3875 }
3876
3877 Register reg = dest->as_pointer_register();
3878 LIR_Address* addr = src->as_address_ptr();
3879 __ lea(reg, as_Address(addr));
3880
3881 if (patch != nullptr) {
3882 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3883 }
3884 }
3885
3886
3887
3888 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3889 assert(!tmp->is_valid(), "don't need temporary");
3890 __ call(RuntimeAddress(dest));
3891 if (info != nullptr) {
3892 add_call_info_here(info);
3893 }
3894 __ post_call_nop();
3895 }
3896
3897
3898 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3899 assert(type == T_LONG, "only for volatile long fields");
3900
3901 if (info != nullptr) {
3902 add_debug_info_for_null_check_here(info);
3903 }
3904
3905 if (src->is_double_xmm()) {
3906 if (dest->is_double_cpu()) {
3907 #ifdef _LP64
3908 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3909 #else
3910 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3911 __ psrlq(src->as_xmm_double_reg(), 32);
3912 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3913 #endif // _LP64
3914 } else if (dest->is_double_stack()) {
3915 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3916 } else if (dest->is_address()) {
3917 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3918 } else {
3919 ShouldNotReachHere();
3920 }
3921
3922 } else if (dest->is_double_xmm()) {
3923 if (src->is_double_stack()) {
3924 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3925 } else if (src->is_address()) {
3926 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3927 } else {
3928 ShouldNotReachHere();
3929 }
3930
3931 #ifndef _LP64
3932 } else if (src->is_double_fpu()) {
3933 assert(src->fpu_regnrLo() == 0, "must be TOS");
3934 if (dest->is_double_stack()) {
3935 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3936 } else if (dest->is_address()) {
3937 __ fistp_d(as_Address(dest->as_address_ptr()));
3938 } else {
3939 ShouldNotReachHere();
3940 }
3941
3942 } else if (dest->is_double_fpu()) {
3943 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3944 if (src->is_double_stack()) {
3945 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3946 } else if (src->is_address()) {
3947 __ fild_d(as_Address(src->as_address_ptr()));
3948 } else {
3949 ShouldNotReachHere();
3950 }
3951 #endif // !_LP64
3952
3953 } else {
3954 ShouldNotReachHere();
3955 }
3956 }
3957
3958 #ifdef ASSERT
3959 // emit run-time assertion
3960 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3961 assert(op->code() == lir_assert, "must be");
3962
3963 if (op->in_opr1()->is_valid()) {
3964 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3965 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3966 } else {
3967 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3968 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3969 }
3970
3971 Label ok;
3972 if (op->condition() != lir_cond_always) {
3973 Assembler::Condition acond = Assembler::zero;
3974 switch (op->condition()) {
3975 case lir_cond_equal: acond = Assembler::equal; break;
3976 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3977 case lir_cond_less: acond = Assembler::less; break;
3978 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3979 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3980 case lir_cond_greater: acond = Assembler::greater; break;
3981 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3982 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3983 default: ShouldNotReachHere();
3984 }
3985 __ jcc(acond, ok);
3986 }
3987 if (op->halt()) {
3988 const char* str = __ code_string(op->msg());
3989 __ stop(str);
3990 } else {
3991 breakpoint();
3992 }
3993 __ bind(ok);
3994 }
3995 #endif
3996
3997 void LIR_Assembler::membar() {
3998 // QQQ sparc TSO uses this,
3999 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4000 }
4001
4002 void LIR_Assembler::membar_acquire() {
4003 // No x86 machines currently require load fences
4004 }
4005
4006 void LIR_Assembler::membar_release() {
4007 // No x86 machines currently require store fences
4008 }
4009
4010 void LIR_Assembler::membar_loadload() {
4011 // no-op
4012 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4013 }
4014
4015 void LIR_Assembler::membar_storestore() {
4016 // no-op
4017 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4018 }
4019
4020 void LIR_Assembler::membar_loadstore() {
4021 // no-op
4022 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4023 }
4024
4025 void LIR_Assembler::membar_storeload() {
4026 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4027 }
4028
4029 void LIR_Assembler::on_spin_wait() {
4030 __ pause ();
4031 }
4032
4033 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4034 assert(result_reg->is_register(), "check");
4035 #ifdef _LP64
4036 // __ get_thread(result_reg->as_register_lo());
4037 __ mov(result_reg->as_register(), r15_thread);
4038 #else
4039 __ get_thread(result_reg->as_register());
4040 #endif // _LP64
4041 }
4042
4043
4044 void LIR_Assembler::peephole(LIR_List*) {
4045 // do nothing for now
4046 }
4047
4048 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4049 assert(data == dest, "xchg/xadd uses only 2 operands");
4050
4051 if (data->type() == T_INT) {
4052 if (code == lir_xadd) {
4053 __ lock();
4054 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4055 } else {
4056 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4057 }
4058 } else if (data->is_oop()) {
4059 assert (code == lir_xchg, "xadd for oops");
4060 Register obj = data->as_register();
4061 #ifdef _LP64
4062 if (UseCompressedOops) {
4063 __ encode_heap_oop(obj);
4064 __ xchgl(obj, as_Address(src->as_address_ptr()));
4065 __ decode_heap_oop(obj);
4066 } else {
4067 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4068 }
4069 #else
4070 __ xchgl(obj, as_Address(src->as_address_ptr()));
4071 #endif
4072 } else if (data->type() == T_LONG) {
4073 #ifdef _LP64
4074 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4075 if (code == lir_xadd) {
4076 __ lock();
4077 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4078 } else {
4079 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4080 }
4081 #else
4082 ShouldNotReachHere();
4083 #endif
4084 } else {
4085 ShouldNotReachHere();
4086 }
4087 }
4088
4089 #undef __