1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "code/aotCodeCache.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/threadIdentifier.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_x86.inline.hpp"
48
49
50 // These masks are used to provide 128-bit aligned bitmasks to the XMM
51 // instructions, to allow sign-masking or sign-bit flipping. They allow
52 // fast versions of NegF/NegD and AbsF/AbsD.
53
54 // Note: 'double' and 'long long' have 32-bits alignment on x86.
55 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
56 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
57 // of 128-bits operands for SSE instructions.
58 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
59 // Store the value to a 128-bits operand.
60 operand[0] = lo;
61 operand[1] = hi;
62 return operand;
63 }
64
65 // Buffer for 128-bits masks used by SSE instructions.
66 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
67
68 // Static initialization during VM startup.
69 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
70 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
71 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
72 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
73
74 #if INCLUDE_CDS
75 // publish external addresses defined in this file
76 void LIR_Assembler::init_AOTAddressTable(GrowableArray<address>& external_addresses) {
77 #define ADD(addr) external_addresses.append((address)(addr));
78 ADD(float_signmask_pool);
79 ADD(double_signmask_pool);
80 ADD(float_signflip_pool);
81 ADD(double_signflip_pool);
82 #undef ADD
83 }
84 #endif // INCLUDE_CDS
85
86 NEEDS_CLEANUP // remove this definitions ?
87 const Register SYNC_header = rax; // synchronization header
88 const Register SHIFT_count = rcx; // where count for shift operations must be
89
90 #define __ _masm->
91
92 static void select_different_registers(Register preserve,
93 Register extra,
94 Register &tmp1,
95 Register &tmp2,
96 Register &tmp3) {
97 if (tmp1 == preserve) {
98 assert_different_registers(tmp1, tmp2, tmp3, extra);
99 tmp1 = extra;
100 } else if (tmp2 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp2 = extra;
103 } else if (tmp3 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp3 = extra;
106 }
107 assert_different_registers(preserve, tmp1, tmp2, tmp3);
108 }
109
110
111
112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
113 if (opr->is_constant()) {
114 LIR_Const* constant = opr->as_constant_ptr();
115 switch (constant->type()) {
116 case T_INT: {
117 return true;
118 }
119
120 default:
121 return false;
122 }
123 }
124 return false;
125 }
126
127
128 LIR_Opr LIR_Assembler::receiverOpr() {
129 return FrameMap::receiver_opr;
130 }
131
132 LIR_Opr LIR_Assembler::osrBufferPointer() {
133 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
134 }
135
136 //--------------fpu register translations-----------------------
137
138
139 address LIR_Assembler::float_constant(float f) {
140 address const_addr = __ float_constant(f);
141 if (const_addr == nullptr) {
142 bailout("const section overflow");
143 return __ code()->consts()->start();
144 } else {
145 return const_addr;
146 }
147 }
148
149
150 address LIR_Assembler::double_constant(double d) {
151 address const_addr = __ double_constant(d);
152 if (const_addr == nullptr) {
153 bailout("const section overflow");
154 return __ code()->consts()->start();
155 } else {
156 return const_addr;
157 }
158 }
159
160 void LIR_Assembler::breakpoint() {
161 __ int3();
162 }
163
164 void LIR_Assembler::push(LIR_Opr opr) {
165 if (opr->is_single_cpu()) {
166 __ push_reg(opr->as_register());
167 } else if (opr->is_double_cpu()) {
168 __ push_reg(opr->as_register_lo());
169 } else if (opr->is_stack()) {
170 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
171 } else if (opr->is_constant()) {
172 LIR_Const* const_opr = opr->as_constant_ptr();
173 if (const_opr->type() == T_OBJECT) {
174 __ push_oop(const_opr->as_jobject(), rscratch1);
175 } else if (const_opr->type() == T_INT) {
176 __ push_jint(const_opr->as_jint());
177 } else {
178 ShouldNotReachHere();
179 }
180
181 } else {
182 ShouldNotReachHere();
183 }
184 }
185
186 void LIR_Assembler::pop(LIR_Opr opr) {
187 if (opr->is_single_cpu()) {
188 __ pop_reg(opr->as_register());
189 } else {
190 ShouldNotReachHere();
191 }
192 }
193
194 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
195 return addr->base()->is_illegal() && addr->index()->is_illegal();
196 }
197
198 //-------------------------------------------
199
200 Address LIR_Assembler::as_Address(LIR_Address* addr) {
201 return as_Address(addr, rscratch1);
202 }
203
204 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
205 if (addr->base()->is_illegal()) {
206 assert(addr->index()->is_illegal(), "must be illegal too");
207 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
208 if (! __ reachable(laddr)) {
209 __ movptr(tmp, laddr.addr());
210 Address res(tmp, 0);
211 return res;
212 } else {
213 return __ as_Address(laddr);
214 }
215 }
216
217 Register base = addr->base()->as_pointer_register();
218
219 if (addr->index()->is_illegal()) {
220 return Address( base, addr->disp());
221 } else if (addr->index()->is_cpu_register()) {
222 Register index = addr->index()->as_pointer_register();
223 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
224 } else if (addr->index()->is_constant()) {
225 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
226 assert(Assembler::is_simm32(addr_offset), "must be");
227
228 return Address(base, addr_offset);
229 } else {
230 Unimplemented();
231 return Address();
232 }
233 }
234
235
236 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
237 Address base = as_Address(addr);
238 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
239 }
240
241
242 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
243 return as_Address(addr);
244 }
245
246
247 void LIR_Assembler::osr_entry() {
248 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
249 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
250 ValueStack* entry_state = osr_entry->state();
251 int number_of_locks = entry_state->locks_size();
252
253 // we jump here if osr happens with the interpreter
254 // state set up to continue at the beginning of the
255 // loop that triggered osr - in particular, we have
256 // the following registers setup:
257 //
258 // rcx: osr buffer
259 //
260
261 // build frame
262 ciMethod* m = compilation()->method();
263 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
264
265 // OSR buffer is
266 //
267 // locals[nlocals-1..0]
268 // monitors[0..number_of_locks]
269 //
270 // locals is a direct copy of the interpreter frame so in the osr buffer
271 // so first slot in the local array is the last local from the interpreter
272 // and last slot is local[0] (receiver) from the interpreter
273 //
274 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
275 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
276 // in the interpreter frame (the method lock if a sync method)
277
278 // Initialize monitors in the compiled activation.
279 // rcx: pointer to osr buffer
280 //
281 // All other registers are dead at this point and the locals will be
282 // copied into place by code emitted in the IR.
283
284 Register OSR_buf = osrBufferPointer()->as_pointer_register();
285 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
286 int monitor_offset = BytesPerWord * method()->max_locals() +
287 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
288 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
289 // the OSR buffer using 2 word entries: first the lock and then
290 // the oop.
291 for (int i = 0; i < number_of_locks; i++) {
292 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
293 #ifdef ASSERT
294 // verify the interpreter's monitor has a non-null object
295 {
296 Label L;
297 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
298 __ jcc(Assembler::notZero, L);
299 __ stop("locked object is null");
300 __ bind(L);
301 }
302 #endif
303 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
304 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
305 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
306 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
307 }
308 }
309 }
310
311
312 // inline cache check; done before the frame is built.
313 int LIR_Assembler::check_icache() {
314 return __ ic_check(CodeEntryAlignment);
315 }
316
317 void LIR_Assembler::clinit_barrier(ciMethod* method) {
318 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
319 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
320
321 Label L_skip_barrier;
322 Register klass = rscratch1;
323
324 __ mov_metadata(klass, method->holder()->constant_encoding());
325 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
326
327 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
328
329 __ bind(L_skip_barrier);
330 }
331
332 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
333 jobject o = nullptr;
334 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
335 __ movoop(reg, o);
336 patching_epilog(patch, lir_patch_normal, reg, info);
337 }
338
339 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
340 Metadata* o = nullptr;
341 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
342 __ mov_metadata(reg, o);
343 patching_epilog(patch, lir_patch_normal, reg, info);
344 }
345
346 // This specifies the rsp decrement needed to build the frame
347 int LIR_Assembler::initial_frame_size_in_bytes() const {
348 // if rounding, must let FrameMap know!
349
350 // The frame_map records size in slots (32bit word)
351
352 // subtract two words to account for return address and link
353 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
354 }
355
356
357 int LIR_Assembler::emit_exception_handler() {
358 // generate code for exception handler
359 address handler_base = __ start_a_stub(exception_handler_size());
360 if (handler_base == nullptr) {
361 // not enough space left for the handler
362 bailout("exception handler overflow");
363 return -1;
364 }
365
366 int offset = code_offset();
367
368 // the exception oop and pc are in rax, and rdx
369 // no other registers need to be preserved, so invalidate them
370 __ invalidate_registers(false, true, true, false, true, true);
371
372 // check that there is really an exception
373 __ verify_not_null_oop(rax);
374
375 // search an exception handler (rax: exception oop, rdx: throwing pc)
376 __ call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
377 __ should_not_reach_here();
378 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
379 __ end_a_stub();
380
381 return offset;
382 }
383
384
385 // Emit the code to remove the frame from the stack in the exception
386 // unwind path.
387 int LIR_Assembler::emit_unwind_handler() {
388 #ifndef PRODUCT
389 if (CommentedAssembly) {
390 _masm->block_comment("Unwind handler");
391 }
392 #endif
393
394 int offset = code_offset();
395
396 // Fetch the exception from TLS and clear out exception related thread state
397 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
398 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), NULL_WORD);
399 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), NULL_WORD);
400
401 __ bind(_unwind_handler_entry);
402 __ verify_not_null_oop(rax);
403 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
404 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
405 }
406
407 // Perform needed unlocking
408 MonitorExitStub* stub = nullptr;
409 if (method()->is_synchronized()) {
410 monitor_address(0, FrameMap::rax_opr);
411 stub = new MonitorExitStub(FrameMap::rax_opr, 0);
412 __ unlock_object(rdi, rsi, rax, *stub->entry());
413 __ bind(*stub->continuation());
414 }
415
416 if (compilation()->env()->dtrace_method_probes()) {
417 __ mov(rdi, r15_thread);
418 __ mov_metadata(rsi, method()->constant_encoding());
419 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
420 }
421
422 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
423 __ mov(rax, rbx); // Restore the exception
424 }
425
426 // remove the activation and dispatch to the unwind handler
427 __ remove_frame(initial_frame_size_in_bytes());
428 __ jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
429
430 // Emit the slow path assembly
431 if (stub != nullptr) {
432 stub->emit_code(this);
433 }
434
435 return offset;
436 }
437
438
439 int LIR_Assembler::emit_deopt_handler() {
440 // generate code for exception handler
441 address handler_base = __ start_a_stub(deopt_handler_size());
442 if (handler_base == nullptr) {
443 // not enough space left for the handler
444 bailout("deopt handler overflow");
445 return -1;
446 }
447
448 int offset = code_offset();
449
450 Label start;
451 __ bind(start);
452
453 __ call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
454
455 int entry_offset = __ offset();
456
457 __ jmp(start);
458
459 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
460 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
461 "out of bounds read in post-call NOP check");
462 __ end_a_stub();
463
464 return entry_offset;
465 }
466
467 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
468 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
469 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
470 assert(result->fpu() == 0, "result must already be on TOS");
471 }
472
473 // Pop the stack before the safepoint code
474 __ remove_frame(initial_frame_size_in_bytes());
475
476 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
477 __ reserved_stack_check();
478 }
479
480 // Note: we do not need to round double result; float result has the right precision
481 // the poll sets the condition code, but no data registers
482
483 code_stub->set_safepoint_offset(__ offset());
484 __ relocate(relocInfo::poll_return_type);
485 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
486 __ ret(0);
487 }
488
489
490 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
491 guarantee(info != nullptr, "Shouldn't be null");
492 int offset = __ offset();
493 const Register poll_addr = rscratch1;
494 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
495 add_debug_info_for_branch(info);
496 __ relocate(relocInfo::poll_type);
497 address pre_pc = __ pc();
498 __ testl(rax, Address(poll_addr, 0));
499 address post_pc = __ pc();
500 guarantee(pointer_delta(post_pc, pre_pc, 1) == 3, "must be exact length");
501 return offset;
502 }
503
504
505 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
506 if (from_reg != to_reg) __ mov(to_reg, from_reg);
507 }
508
509 void LIR_Assembler::swap_reg(Register a, Register b) {
510 __ xchgptr(a, b);
511 }
512
513
514 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
515 assert(src->is_constant(), "should not call otherwise");
516 assert(dest->is_register(), "should not call otherwise");
517 LIR_Const* c = src->as_constant_ptr();
518
519 switch (c->type()) {
520 case T_INT: {
521 assert(patch_code == lir_patch_none, "no patching handled here");
522 __ movl(dest->as_register(), c->as_jint());
523 break;
524 }
525
526 case T_ADDRESS: {
527 assert(patch_code == lir_patch_none, "no patching handled here");
528 __ movptr(dest->as_register(), c->as_jint());
529 break;
530 }
531
532 case T_LONG: {
533 #if INCLUDE_CDS
534 if (AOTCodeCache::is_on_for_dump()) {
535 address b = c->as_pointer();
536 if (b == (address)ThreadIdentifier::unsafe_offset()) {
537 __ lea(dest->as_register_lo(), ExternalAddress(b));
538 break;
539 }
540 }
541 #endif
542 assert(patch_code == lir_patch_none, "no patching handled here");
543 #if INCLUDE_CDS
544 if (AOTCodeCache::is_on_for_dump()) {
545 address b = c->as_pointer();
546 if (b == (address)ThreadIdentifier::unsafe_offset()) {
547 __ lea(dest->as_register_lo(), ExternalAddress(b));
548 break;
549 }
550 if (AOTRuntimeConstants::contains(b)) {
551 __ load_aotrc_address(dest->as_register_lo(), b);
552 break;
553 }
554 }
555 #endif
556 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
557 break;
558 }
559
560 case T_OBJECT: {
561 if (patch_code != lir_patch_none) {
562 jobject2reg_with_patching(dest->as_register(), info);
563 } else {
564 __ movoop(dest->as_register(), c->as_jobject());
565 }
566 break;
567 }
568
569 case T_METADATA: {
570 if (patch_code != lir_patch_none) {
571 klass2reg_with_patching(dest->as_register(), info);
572 } else {
573 __ mov_metadata(dest->as_register(), c->as_metadata());
574 }
575 break;
576 }
577
578 case T_FLOAT: {
579 if (dest->is_single_xmm()) {
580 if (UseAVX <= 2 && c->is_zero_float()) {
581 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
582 } else {
583 __ movflt(dest->as_xmm_float_reg(),
584 InternalAddress(float_constant(c->as_jfloat())));
585 }
586 } else {
587 ShouldNotReachHere();
588 }
589 break;
590 }
591
592 case T_DOUBLE: {
593 if (dest->is_double_xmm()) {
594 if (UseAVX <= 2 && c->is_zero_double()) {
595 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
596 } else {
597 __ movdbl(dest->as_xmm_double_reg(),
598 InternalAddress(double_constant(c->as_jdouble())));
599 }
600 } else {
601 ShouldNotReachHere();
602 }
603 break;
604 }
605
606 default:
607 ShouldNotReachHere();
608 }
609 }
610
611 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
612 assert(src->is_constant(), "should not call otherwise");
613 assert(dest->is_stack(), "should not call otherwise");
614 LIR_Const* c = src->as_constant_ptr();
615
616 switch (c->type()) {
617 case T_INT: // fall through
618 case T_FLOAT:
619 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
620 break;
621
622 case T_ADDRESS:
623 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
624 break;
625
626 case T_OBJECT:
627 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
628 break;
629
630 case T_LONG: // fall through
631 case T_DOUBLE:
632 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
633 lo_word_offset_in_bytes),
634 (intptr_t)c->as_jlong_bits(),
635 rscratch1);
636 break;
637
638 default:
639 ShouldNotReachHere();
640 }
641 }
642
643 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
644 assert(src->is_constant(), "should not call otherwise");
645 assert(dest->is_address(), "should not call otherwise");
646 LIR_Const* c = src->as_constant_ptr();
647 LIR_Address* addr = dest->as_address_ptr();
648
649 int null_check_here = code_offset();
650 switch (type) {
651 case T_INT: // fall through
652 case T_FLOAT:
653 __ movl(as_Address(addr), c->as_jint_bits());
654 break;
655
656 case T_ADDRESS:
657 __ movptr(as_Address(addr), c->as_jint_bits());
658 break;
659
660 case T_OBJECT: // fall through
661 case T_ARRAY:
662 if (c->as_jobject() == nullptr) {
663 if (UseCompressedOops && !wide) {
664 __ movl(as_Address(addr), NULL_WORD);
665 } else {
666 __ xorptr(rscratch1, rscratch1);
667 null_check_here = code_offset();
668 __ movptr(as_Address(addr), rscratch1);
669 }
670 } else {
671 if (is_literal_address(addr)) {
672 ShouldNotReachHere();
673 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
674 } else {
675 __ movoop(rscratch1, c->as_jobject());
676 if (UseCompressedOops && !wide) {
677 __ encode_heap_oop(rscratch1);
678 null_check_here = code_offset();
679 __ movl(as_Address_lo(addr), rscratch1);
680 } else {
681 null_check_here = code_offset();
682 __ movptr(as_Address_lo(addr), rscratch1);
683 }
684 }
685 }
686 break;
687
688 case T_LONG: // fall through
689 case T_DOUBLE:
690 if (is_literal_address(addr)) {
691 ShouldNotReachHere();
692 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
693 } else {
694 __ movptr(r10, (intptr_t)c->as_jlong_bits());
695 null_check_here = code_offset();
696 __ movptr(as_Address_lo(addr), r10);
697 }
698 break;
699
700 case T_BOOLEAN:
701 __ movb(as_Address(addr), c->as_jint() & 1);
702 break;
703 case T_BYTE:
704 __ movb(as_Address(addr), c->as_jint() & 0xFF);
705 break;
706
707 case T_CHAR: // fall through
708 case T_SHORT:
709 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
710 break;
711
712 default:
713 ShouldNotReachHere();
714 };
715
716 if (info != nullptr) {
717 add_debug_info_for_null_check(null_check_here, info);
718 }
719 }
720
721
722 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
723 assert(src->is_register(), "should not call otherwise");
724 assert(dest->is_register(), "should not call otherwise");
725
726 // move between cpu-registers
727 if (dest->is_single_cpu()) {
728 if (src->type() == T_LONG) {
729 // Can do LONG -> OBJECT
730 move_regs(src->as_register_lo(), dest->as_register());
731 return;
732 }
733 assert(src->is_single_cpu(), "must match");
734 if (src->type() == T_OBJECT) {
735 __ verify_oop(src->as_register());
736 }
737 move_regs(src->as_register(), dest->as_register());
738
739 } else if (dest->is_double_cpu()) {
740 if (is_reference_type(src->type())) {
741 // Surprising to me but we can see move of a long to t_object
742 __ verify_oop(src->as_register());
743 move_regs(src->as_register(), dest->as_register_lo());
744 return;
745 }
746 assert(src->is_double_cpu(), "must match");
747 Register f_lo = src->as_register_lo();
748 Register f_hi = src->as_register_hi();
749 Register t_lo = dest->as_register_lo();
750 Register t_hi = dest->as_register_hi();
751 assert(f_hi == f_lo, "must be same");
752 assert(t_hi == t_lo, "must be same");
753 move_regs(f_lo, t_lo);
754
755 // move between xmm-registers
756 } else if (dest->is_single_xmm()) {
757 assert(src->is_single_xmm(), "must match");
758 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
759 } else if (dest->is_double_xmm()) {
760 assert(src->is_double_xmm(), "must match");
761 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
762
763 } else {
764 ShouldNotReachHere();
765 }
766 }
767
768 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
769 assert(src->is_register(), "should not call otherwise");
770 assert(dest->is_stack(), "should not call otherwise");
771
772 if (src->is_single_cpu()) {
773 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
774 if (is_reference_type(type)) {
775 __ verify_oop(src->as_register());
776 __ movptr (dst, src->as_register());
777 } else if (type == T_METADATA || type == T_ADDRESS) {
778 __ movptr (dst, src->as_register());
779 } else {
780 __ movl (dst, src->as_register());
781 }
782
783 } else if (src->is_double_cpu()) {
784 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
785 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
786 __ movptr (dstLO, src->as_register_lo());
787
788 } else if (src->is_single_xmm()) {
789 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
790 __ movflt(dst_addr, src->as_xmm_float_reg());
791
792 } else if (src->is_double_xmm()) {
793 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
794 __ movdbl(dst_addr, src->as_xmm_double_reg());
795
796 } else {
797 ShouldNotReachHere();
798 }
799 }
800
801
802 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
803 LIR_Address* to_addr = dest->as_address_ptr();
804 PatchingStub* patch = nullptr;
805 Register compressed_src = rscratch1;
806
807 if (is_reference_type(type)) {
808 __ verify_oop(src->as_register());
809 if (UseCompressedOops && !wide) {
810 __ movptr(compressed_src, src->as_register());
811 __ encode_heap_oop(compressed_src);
812 if (patch_code != lir_patch_none) {
813 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
814 }
815 }
816 }
817
818 if (patch_code != lir_patch_none) {
819 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
820 Address toa = as_Address(to_addr);
821 assert(toa.disp() != 0, "must have");
822 }
823
824 int null_check_here = code_offset();
825 switch (type) {
826 case T_FLOAT: {
827 assert(src->is_single_xmm(), "not a float");
828 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
829 break;
830 }
831
832 case T_DOUBLE: {
833 assert(src->is_double_xmm(), "not a double");
834 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
835 break;
836 }
837
838 case T_ARRAY: // fall through
839 case T_OBJECT: // fall through
840 if (UseCompressedOops && !wide) {
841 __ movl(as_Address(to_addr), compressed_src);
842 } else {
843 __ movptr(as_Address(to_addr), src->as_register());
844 }
845 break;
846 case T_ADDRESS:
847 __ movptr(as_Address(to_addr), src->as_register());
848 break;
849 case T_INT:
850 __ movl(as_Address(to_addr), src->as_register());
851 break;
852
853 case T_LONG: {
854 Register from_lo = src->as_register_lo();
855 Register from_hi = src->as_register_hi();
856 __ movptr(as_Address_lo(to_addr), from_lo);
857 break;
858 }
859
860 case T_BYTE: // fall through
861 case T_BOOLEAN: {
862 Register src_reg = src->as_register();
863 Address dst_addr = as_Address(to_addr);
864 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
865 __ movb(dst_addr, src_reg);
866 break;
867 }
868
869 case T_CHAR: // fall through
870 case T_SHORT:
871 __ movw(as_Address(to_addr), src->as_register());
872 break;
873
874 default:
875 ShouldNotReachHere();
876 }
877 if (info != nullptr) {
878 add_debug_info_for_null_check(null_check_here, info);
879 }
880
881 if (patch_code != lir_patch_none) {
882 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
883 }
884 }
885
886
887 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
888 assert(src->is_stack(), "should not call otherwise");
889 assert(dest->is_register(), "should not call otherwise");
890
891 if (dest->is_single_cpu()) {
892 if (is_reference_type(type)) {
893 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
894 __ verify_oop(dest->as_register());
895 } else if (type == T_METADATA || type == T_ADDRESS) {
896 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
897 } else {
898 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
899 }
900
901 } else if (dest->is_double_cpu()) {
902 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
903 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
904 __ movptr(dest->as_register_lo(), src_addr_LO);
905
906 } else if (dest->is_single_xmm()) {
907 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
908 __ movflt(dest->as_xmm_float_reg(), src_addr);
909
910 } else if (dest->is_double_xmm()) {
911 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
912 __ movdbl(dest->as_xmm_double_reg(), src_addr);
913
914 } else {
915 ShouldNotReachHere();
916 }
917 }
918
919
920 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
921 if (src->is_single_stack()) {
922 if (is_reference_type(type)) {
923 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
924 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
925 } else {
926 //no pushl on 64bits
927 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
928 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
929 }
930
931 } else if (src->is_double_stack()) {
932 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
933 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
934
935 } else {
936 ShouldNotReachHere();
937 }
938 }
939
940
941 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
942 assert(src->is_address(), "should not call otherwise");
943 assert(dest->is_register(), "should not call otherwise");
944
945 LIR_Address* addr = src->as_address_ptr();
946 Address from_addr = as_Address(addr);
947
948 if (addr->base()->type() == T_OBJECT) {
949 __ verify_oop(addr->base()->as_pointer_register());
950 }
951
952 switch (type) {
953 case T_BOOLEAN: // fall through
954 case T_BYTE: // fall through
955 case T_CHAR: // fall through
956 case T_SHORT:
957 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
958 // on pre P6 processors we may get partial register stalls
959 // so blow away the value of to_rinfo before loading a
960 // partial word into it. Do it here so that it precedes
961 // the potential patch point below.
962 __ xorptr(dest->as_register(), dest->as_register());
963 }
964 break;
965 default:
966 break;
967 }
968
969 PatchingStub* patch = nullptr;
970 if (patch_code != lir_patch_none) {
971 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
972 assert(from_addr.disp() != 0, "must have");
973 }
974 if (info != nullptr) {
975 add_debug_info_for_null_check_here(info);
976 }
977
978 switch (type) {
979 case T_FLOAT: {
980 if (dest->is_single_xmm()) {
981 __ movflt(dest->as_xmm_float_reg(), from_addr);
982 } else {
983 ShouldNotReachHere();
984 }
985 break;
986 }
987
988 case T_DOUBLE: {
989 if (dest->is_double_xmm()) {
990 __ movdbl(dest->as_xmm_double_reg(), from_addr);
991 } else {
992 ShouldNotReachHere();
993 }
994 break;
995 }
996
997 case T_OBJECT: // fall through
998 case T_ARRAY: // fall through
999 if (UseCompressedOops && !wide) {
1000 __ movl(dest->as_register(), from_addr);
1001 } else {
1002 __ movptr(dest->as_register(), from_addr);
1003 }
1004 break;
1005
1006 case T_ADDRESS:
1007 __ movptr(dest->as_register(), from_addr);
1008 break;
1009 case T_INT:
1010 __ movl(dest->as_register(), from_addr);
1011 break;
1012
1013 case T_LONG: {
1014 Register to_lo = dest->as_register_lo();
1015 Register to_hi = dest->as_register_hi();
1016 __ movptr(to_lo, as_Address_lo(addr));
1017 break;
1018 }
1019
1020 case T_BOOLEAN: // fall through
1021 case T_BYTE: {
1022 Register dest_reg = dest->as_register();
1023 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1024 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1025 __ movsbl(dest_reg, from_addr);
1026 } else {
1027 __ movb(dest_reg, from_addr);
1028 __ shll(dest_reg, 24);
1029 __ sarl(dest_reg, 24);
1030 }
1031 break;
1032 }
1033
1034 case T_CHAR: {
1035 Register dest_reg = dest->as_register();
1036 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1037 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1038 __ movzwl(dest_reg, from_addr);
1039 } else {
1040 __ movw(dest_reg, from_addr);
1041 }
1042 break;
1043 }
1044
1045 case T_SHORT: {
1046 Register dest_reg = dest->as_register();
1047 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1048 __ movswl(dest_reg, from_addr);
1049 } else {
1050 __ movw(dest_reg, from_addr);
1051 __ shll(dest_reg, 16);
1052 __ sarl(dest_reg, 16);
1053 }
1054 break;
1055 }
1056
1057 default:
1058 ShouldNotReachHere();
1059 }
1060
1061 if (patch != nullptr) {
1062 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1063 }
1064
1065 if (is_reference_type(type)) {
1066 if (UseCompressedOops && !wide) {
1067 __ decode_heap_oop(dest->as_register());
1068 }
1069
1070 __ verify_oop(dest->as_register());
1071 }
1072 }
1073
1074
1075 NEEDS_CLEANUP; // This could be static?
1076 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1077 int elem_size = type2aelembytes(type);
1078 switch (elem_size) {
1079 case 1: return Address::times_1;
1080 case 2: return Address::times_2;
1081 case 4: return Address::times_4;
1082 case 8: return Address::times_8;
1083 }
1084 ShouldNotReachHere();
1085 return Address::no_scale;
1086 }
1087
1088
1089 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1090 switch (op->code()) {
1091 case lir_idiv:
1092 case lir_irem:
1093 arithmetic_idiv(op->code(),
1094 op->in_opr1(),
1095 op->in_opr2(),
1096 op->in_opr3(),
1097 op->result_opr(),
1098 op->info());
1099 break;
1100 case lir_fmad:
1101 __ fmad(op->result_opr()->as_xmm_double_reg(),
1102 op->in_opr1()->as_xmm_double_reg(),
1103 op->in_opr2()->as_xmm_double_reg(),
1104 op->in_opr3()->as_xmm_double_reg());
1105 break;
1106 case lir_fmaf:
1107 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1108 op->in_opr1()->as_xmm_float_reg(),
1109 op->in_opr2()->as_xmm_float_reg(),
1110 op->in_opr3()->as_xmm_float_reg());
1111 break;
1112 default: ShouldNotReachHere(); break;
1113 }
1114 }
1115
1116 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1117 #ifdef ASSERT
1118 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1119 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1120 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1121 #endif
1122
1123 if (op->cond() == lir_cond_always) {
1124 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1125 __ jmp (*(op->label()));
1126 } else {
1127 Assembler::Condition acond = Assembler::zero;
1128 if (op->code() == lir_cond_float_branch) {
1129 assert(op->ublock() != nullptr, "must have unordered successor");
1130 __ jcc(Assembler::parity, *(op->ublock()->label()));
1131 switch(op->cond()) {
1132 case lir_cond_equal: acond = Assembler::equal; break;
1133 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1134 case lir_cond_less: acond = Assembler::below; break;
1135 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1136 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1137 case lir_cond_greater: acond = Assembler::above; break;
1138 default: ShouldNotReachHere();
1139 }
1140 } else {
1141 switch (op->cond()) {
1142 case lir_cond_equal: acond = Assembler::equal; break;
1143 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1144 case lir_cond_less: acond = Assembler::less; break;
1145 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1146 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1147 case lir_cond_greater: acond = Assembler::greater; break;
1148 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1149 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1150 default: ShouldNotReachHere();
1151 }
1152 }
1153 __ jcc(acond,*(op->label()));
1154 }
1155 }
1156
1157 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1158 LIR_Opr src = op->in_opr();
1159 LIR_Opr dest = op->result_opr();
1160
1161 switch (op->bytecode()) {
1162 case Bytecodes::_i2l:
1163 __ movl2ptr(dest->as_register_lo(), src->as_register());
1164 break;
1165
1166 case Bytecodes::_l2i:
1167 __ movl(dest->as_register(), src->as_register_lo());
1168 break;
1169
1170 case Bytecodes::_i2b:
1171 move_regs(src->as_register(), dest->as_register());
1172 __ sign_extend_byte(dest->as_register());
1173 break;
1174
1175 case Bytecodes::_i2c:
1176 move_regs(src->as_register(), dest->as_register());
1177 __ andl(dest->as_register(), 0xFFFF);
1178 break;
1179
1180 case Bytecodes::_i2s:
1181 move_regs(src->as_register(), dest->as_register());
1182 __ sign_extend_short(dest->as_register());
1183 break;
1184
1185 case Bytecodes::_f2d:
1186 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1187 break;
1188
1189 case Bytecodes::_d2f:
1190 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1191 break;
1192
1193 case Bytecodes::_i2f:
1194 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1195 break;
1196
1197 case Bytecodes::_i2d:
1198 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1199 break;
1200
1201 case Bytecodes::_l2f:
1202 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1203 break;
1204
1205 case Bytecodes::_l2d:
1206 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1207 break;
1208
1209 case Bytecodes::_f2i:
1210 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1211 break;
1212
1213 case Bytecodes::_d2i:
1214 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1215 break;
1216
1217 case Bytecodes::_f2l:
1218 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1219 break;
1220
1221 case Bytecodes::_d2l:
1222 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1223 break;
1224
1225 default: ShouldNotReachHere();
1226 }
1227 }
1228
1229 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1230 if (op->init_check()) {
1231 add_debug_info_for_null_check_here(op->stub()->info());
1232 // init_state needs acquire, but x86 is TSO, and so we are already good.
1233 __ cmpb(Address(op->klass()->as_register(),
1234 InstanceKlass::init_state_offset()),
1235 InstanceKlass::fully_initialized);
1236 __ jcc(Assembler::notEqual, *op->stub()->entry());
1237 }
1238 __ allocate_object(op->obj()->as_register(),
1239 op->tmp1()->as_register(),
1240 op->tmp2()->as_register(),
1241 op->header_size(),
1242 op->object_size(),
1243 op->klass()->as_register(),
1244 *op->stub()->entry());
1245 __ bind(*op->stub()->continuation());
1246 }
1247
1248 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1249 Register len = op->len()->as_register();
1250 __ movslq(len, len);
1251
1252 if (UseSlowPath ||
1253 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1254 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1255 __ jmp(*op->stub()->entry());
1256 } else {
1257 Register tmp1 = op->tmp1()->as_register();
1258 Register tmp2 = op->tmp2()->as_register();
1259 Register tmp3 = op->tmp3()->as_register();
1260 if (len == tmp1) {
1261 tmp1 = tmp3;
1262 } else if (len == tmp2) {
1263 tmp2 = tmp3;
1264 } else if (len == tmp3) {
1265 // everything is ok
1266 } else {
1267 __ mov(tmp3, len);
1268 }
1269 __ allocate_array(op->obj()->as_register(),
1270 len,
1271 tmp1,
1272 tmp2,
1273 arrayOopDesc::base_offset_in_bytes(op->type()),
1274 array_element_size(op->type()),
1275 op->klass()->as_register(),
1276 *op->stub()->entry(),
1277 op->zero_array());
1278 }
1279 __ bind(*op->stub()->continuation());
1280 }
1281
1282 void LIR_Assembler::type_profile_helper(Register mdo,
1283 ciMethodData *md, ciProfileData *data,
1284 Register recv) {
1285 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1286 __ profile_receiver_type(recv, mdo, mdp_offset);
1287 }
1288
1289 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1290 // we always need a stub for the failure case.
1291 CodeStub* stub = op->stub();
1292 Register obj = op->object()->as_register();
1293 Register k_RInfo = op->tmp1()->as_register();
1294 Register klass_RInfo = op->tmp2()->as_register();
1295 Register dst = op->result_opr()->as_register();
1296 ciKlass* k = op->klass();
1297 Register Rtmp1 = noreg;
1298 Register tmp_load_klass = rscratch1;
1299
1300 // check if it needs to be profiled
1301 ciMethodData* md = nullptr;
1302 ciProfileData* data = nullptr;
1303
1304 if (op->should_profile()) {
1305 ciMethod* method = op->profiled_method();
1306 assert(method != nullptr, "Should have method");
1307 int bci = op->profiled_bci();
1308 md = method->method_data_or_null();
1309 assert(md != nullptr, "Sanity");
1310 data = md->bci_to_data(bci);
1311 assert(data != nullptr, "need data for type check");
1312 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1313 }
1314 Label* success_target = success;
1315 Label* failure_target = failure;
1316
1317 if (obj == k_RInfo) {
1318 k_RInfo = dst;
1319 } else if (obj == klass_RInfo) {
1320 klass_RInfo = dst;
1321 }
1322 Rtmp1 = op->tmp3()->as_register();
1323 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1324
1325 assert_different_registers(obj, k_RInfo, klass_RInfo);
1326
1327 __ testptr(obj, obj);
1328 if (op->should_profile()) {
1329 Label not_null;
1330 Register mdo = klass_RInfo;
1331 __ mov_metadata(mdo, md->constant_encoding());
1332 __ jccb(Assembler::notEqual, not_null);
1333 // Object is null; update MDO and exit
1334 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1335 int header_bits = BitData::null_seen_byte_constant();
1336 __ orb(data_addr, header_bits);
1337 __ jmp(*obj_is_null);
1338 __ bind(not_null);
1339
1340 Register recv = k_RInfo;
1341 __ load_klass(recv, obj, tmp_load_klass);
1342 type_profile_helper(mdo, md, data, recv);
1343 } else {
1344 __ jcc(Assembler::equal, *obj_is_null);
1345 }
1346
1347 if (!k->is_loaded()) {
1348 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1349 } else {
1350 __ mov_metadata(k_RInfo, k->constant_encoding());
1351 }
1352 __ verify_oop(obj);
1353
1354 if (op->fast_check()) {
1355 // get object class
1356 // not a safepoint as obj null check happens earlier
1357 __ load_klass(Rtmp1, obj, tmp_load_klass);
1358 __ cmpptr(k_RInfo, Rtmp1);
1359 __ jcc(Assembler::notEqual, *failure_target);
1360 // successful cast, fall through to profile or jump
1361 } else {
1362 // get object class
1363 // not a safepoint as obj null check happens earlier
1364 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1365 if (k->is_loaded()) {
1366 // See if we get an immediate positive hit
1367 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1368 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1369 __ jcc(Assembler::notEqual, *failure_target);
1370 // successful cast, fall through to profile or jump
1371 } else {
1372 // See if we get an immediate positive hit
1373 __ jcc(Assembler::equal, *success_target);
1374 // check for self
1375 __ cmpptr(klass_RInfo, k_RInfo);
1376 __ jcc(Assembler::equal, *success_target);
1377
1378 __ push_ppx(klass_RInfo);
1379 __ push_ppx(k_RInfo);
1380 __ call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1381 __ pop_ppx(klass_RInfo);
1382 __ pop_ppx(klass_RInfo);
1383 // result is a boolean
1384 __ testl(klass_RInfo, klass_RInfo);
1385 __ jcc(Assembler::equal, *failure_target);
1386 // successful cast, fall through to profile or jump
1387 }
1388 } else {
1389 // perform the fast part of the checking logic
1390 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1391 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1392 __ push_ppx(klass_RInfo);
1393 __ push_ppx(k_RInfo);
1394 __ call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1395 __ pop_ppx(klass_RInfo);
1396 __ pop_ppx(k_RInfo);
1397 // result is a boolean
1398 __ testl(k_RInfo, k_RInfo);
1399 __ jcc(Assembler::equal, *failure_target);
1400 // successful cast, fall through to profile or jump
1401 }
1402 }
1403 __ jmp(*success);
1404 }
1405
1406
1407 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1408 Register tmp_load_klass = rscratch1;
1409 LIR_Code code = op->code();
1410 if (code == lir_store_check) {
1411 Register value = op->object()->as_register();
1412 Register array = op->array()->as_register();
1413 Register k_RInfo = op->tmp1()->as_register();
1414 Register klass_RInfo = op->tmp2()->as_register();
1415 Register Rtmp1 = op->tmp3()->as_register();
1416
1417 CodeStub* stub = op->stub();
1418
1419 // check if it needs to be profiled
1420 ciMethodData* md = nullptr;
1421 ciProfileData* data = nullptr;
1422
1423 if (op->should_profile()) {
1424 ciMethod* method = op->profiled_method();
1425 assert(method != nullptr, "Should have method");
1426 int bci = op->profiled_bci();
1427 md = method->method_data_or_null();
1428 assert(md != nullptr, "Sanity");
1429 data = md->bci_to_data(bci);
1430 assert(data != nullptr, "need data for type check");
1431 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1432 }
1433 Label done;
1434 Label* success_target = &done;
1435 Label* failure_target = stub->entry();
1436
1437 __ testptr(value, value);
1438 if (op->should_profile()) {
1439 Label not_null;
1440 Register mdo = klass_RInfo;
1441 __ mov_metadata(mdo, md->constant_encoding());
1442 __ jccb(Assembler::notEqual, not_null);
1443 // Object is null; update MDO and exit
1444 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1445 int header_bits = BitData::null_seen_byte_constant();
1446 __ orb(data_addr, header_bits);
1447 __ jmp(done);
1448 __ bind(not_null);
1449
1450 Register recv = k_RInfo;
1451 __ load_klass(recv, value, tmp_load_klass);
1452 type_profile_helper(mdo, md, data, recv);
1453 } else {
1454 __ jcc(Assembler::equal, done);
1455 }
1456
1457 add_debug_info_for_null_check_here(op->info_for_exception());
1458 __ load_klass(k_RInfo, array, tmp_load_klass);
1459 __ load_klass(klass_RInfo, value, tmp_load_klass);
1460
1461 // get instance klass (it's already uncompressed)
1462 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1463 // perform the fast part of the checking logic
1464 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1465 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1466 __ push_ppx(klass_RInfo);
1467 __ push_ppx(k_RInfo);
1468 __ call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1469 __ pop_ppx(klass_RInfo);
1470 __ pop_ppx(k_RInfo);
1471 // result is a boolean
1472 __ testl(k_RInfo, k_RInfo);
1473 __ jcc(Assembler::equal, *failure_target);
1474 // fall through to the success case
1475
1476 __ bind(done);
1477 } else
1478 if (code == lir_checkcast) {
1479 Register obj = op->object()->as_register();
1480 Register dst = op->result_opr()->as_register();
1481 Label success;
1482 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1483 __ bind(success);
1484 if (dst != obj) {
1485 __ mov(dst, obj);
1486 }
1487 } else
1488 if (code == lir_instanceof) {
1489 Register obj = op->object()->as_register();
1490 Register dst = op->result_opr()->as_register();
1491 Label success, failure, done;
1492 emit_typecheck_helper(op, &success, &failure, &failure);
1493 __ bind(failure);
1494 __ xorptr(dst, dst);
1495 __ jmpb(done);
1496 __ bind(success);
1497 __ movptr(dst, 1);
1498 __ bind(done);
1499 } else {
1500 ShouldNotReachHere();
1501 }
1502
1503 }
1504
1505
1506 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1507 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1508 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1509 Register newval = op->new_value()->as_register();
1510 Register cmpval = op->cmp_value()->as_register();
1511 assert(cmpval == rax, "wrong register");
1512 assert(newval != noreg, "new val must be register");
1513 assert(cmpval != newval, "cmp and new values must be in different registers");
1514 assert(cmpval != addr, "cmp and addr must be in different registers");
1515 assert(newval != addr, "new value and addr must be in different registers");
1516
1517 if (op->code() == lir_cas_obj) {
1518 if (UseCompressedOops) {
1519 __ encode_heap_oop(cmpval);
1520 __ mov(rscratch1, newval);
1521 __ encode_heap_oop(rscratch1);
1522 __ lock();
1523 // cmpval (rax) is implicitly used by this instruction
1524 __ cmpxchgl(rscratch1, Address(addr, 0));
1525 } else {
1526 __ lock();
1527 __ cmpxchgptr(newval, Address(addr, 0));
1528 }
1529 } else {
1530 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1531 __ lock();
1532 __ cmpxchgl(newval, Address(addr, 0));
1533 }
1534 } else if (op->code() == lir_cas_long) {
1535 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1536 Register newval = op->new_value()->as_register_lo();
1537 Register cmpval = op->cmp_value()->as_register_lo();
1538 assert(cmpval == rax, "wrong register");
1539 assert(newval != noreg, "new val must be register");
1540 assert(cmpval != newval, "cmp and new values must be in different registers");
1541 assert(cmpval != addr, "cmp and addr must be in different registers");
1542 assert(newval != addr, "new value and addr must be in different registers");
1543 __ lock();
1544 __ cmpxchgq(newval, Address(addr, 0));
1545 } else {
1546 Unimplemented();
1547 }
1548 }
1549
1550 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1551 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1552 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1553
1554 Assembler::Condition acond, ncond;
1555 switch (condition) {
1556 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1557 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1558 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1559 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1560 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1561 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1562 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1563 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1564 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1565 ShouldNotReachHere();
1566 }
1567
1568 if (opr1->is_cpu_register()) {
1569 reg2reg(opr1, result);
1570 } else if (opr1->is_stack()) {
1571 stack2reg(opr1, result, result->type());
1572 } else if (opr1->is_constant()) {
1573 const2reg(opr1, result, lir_patch_none, nullptr);
1574 } else {
1575 ShouldNotReachHere();
1576 }
1577
1578 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1579 // optimized version that does not require a branch
1580 if (opr2->is_single_cpu()) {
1581 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1582 __ cmov(ncond, result->as_register(), opr2->as_register());
1583 } else if (opr2->is_double_cpu()) {
1584 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1585 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1586 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1587 } else if (opr2->is_single_stack()) {
1588 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1589 } else if (opr2->is_double_stack()) {
1590 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1591 } else {
1592 ShouldNotReachHere();
1593 }
1594
1595 } else {
1596 Label skip;
1597 __ jccb(acond, skip);
1598 if (opr2->is_cpu_register()) {
1599 reg2reg(opr2, result);
1600 } else if (opr2->is_stack()) {
1601 stack2reg(opr2, result, result->type());
1602 } else if (opr2->is_constant()) {
1603 const2reg(opr2, result, lir_patch_none, nullptr);
1604 } else {
1605 ShouldNotReachHere();
1606 }
1607 __ bind(skip);
1608 }
1609 }
1610
1611
1612 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1613 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1614
1615 if (left->is_single_cpu()) {
1616 assert(left == dest, "left and dest must be equal");
1617 Register lreg = left->as_register();
1618
1619 if (right->is_single_cpu()) {
1620 // cpu register - cpu register
1621 Register rreg = right->as_register();
1622 switch (code) {
1623 case lir_add: __ addl (lreg, rreg); break;
1624 case lir_sub: __ subl (lreg, rreg); break;
1625 case lir_mul: __ imull(lreg, rreg); break;
1626 default: ShouldNotReachHere();
1627 }
1628
1629 } else if (right->is_stack()) {
1630 // cpu register - stack
1631 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1632 switch (code) {
1633 case lir_add: __ addl(lreg, raddr); break;
1634 case lir_sub: __ subl(lreg, raddr); break;
1635 default: ShouldNotReachHere();
1636 }
1637
1638 } else if (right->is_constant()) {
1639 // cpu register - constant
1640 jint c = right->as_constant_ptr()->as_jint();
1641 switch (code) {
1642 case lir_add: {
1643 __ incrementl(lreg, c);
1644 break;
1645 }
1646 case lir_sub: {
1647 __ decrementl(lreg, c);
1648 break;
1649 }
1650 default: ShouldNotReachHere();
1651 }
1652
1653 } else {
1654 ShouldNotReachHere();
1655 }
1656
1657 } else if (left->is_double_cpu()) {
1658 assert(left == dest, "left and dest must be equal");
1659 Register lreg_lo = left->as_register_lo();
1660 Register lreg_hi = left->as_register_hi();
1661
1662 if (right->is_double_cpu()) {
1663 // cpu register - cpu register
1664 Register rreg_lo = right->as_register_lo();
1665 Register rreg_hi = right->as_register_hi();
1666 assert_different_registers(lreg_lo, rreg_lo);
1667 switch (code) {
1668 case lir_add:
1669 __ addptr(lreg_lo, rreg_lo);
1670 break;
1671 case lir_sub:
1672 __ subptr(lreg_lo, rreg_lo);
1673 break;
1674 case lir_mul:
1675 __ imulq(lreg_lo, rreg_lo);
1676 break;
1677 default:
1678 ShouldNotReachHere();
1679 }
1680
1681 } else if (right->is_constant()) {
1682 // cpu register - constant
1683 jlong c = right->as_constant_ptr()->as_jlong_bits();
1684 __ movptr(r10, (intptr_t) c);
1685 switch (code) {
1686 case lir_add:
1687 __ addptr(lreg_lo, r10);
1688 break;
1689 case lir_sub:
1690 __ subptr(lreg_lo, r10);
1691 break;
1692 default:
1693 ShouldNotReachHere();
1694 }
1695
1696 } else {
1697 ShouldNotReachHere();
1698 }
1699
1700 } else if (left->is_single_xmm()) {
1701 assert(left == dest, "left and dest must be equal");
1702 XMMRegister lreg = left->as_xmm_float_reg();
1703
1704 if (right->is_single_xmm()) {
1705 XMMRegister rreg = right->as_xmm_float_reg();
1706 switch (code) {
1707 case lir_add: __ addss(lreg, rreg); break;
1708 case lir_sub: __ subss(lreg, rreg); break;
1709 case lir_mul: __ mulss(lreg, rreg); break;
1710 case lir_div: __ divss(lreg, rreg); break;
1711 default: ShouldNotReachHere();
1712 }
1713 } else {
1714 Address raddr;
1715 if (right->is_single_stack()) {
1716 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1717 } else if (right->is_constant()) {
1718 // hack for now
1719 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
1720 } else {
1721 ShouldNotReachHere();
1722 }
1723 switch (code) {
1724 case lir_add: __ addss(lreg, raddr); break;
1725 case lir_sub: __ subss(lreg, raddr); break;
1726 case lir_mul: __ mulss(lreg, raddr); break;
1727 case lir_div: __ divss(lreg, raddr); break;
1728 default: ShouldNotReachHere();
1729 }
1730 }
1731
1732 } else if (left->is_double_xmm()) {
1733 assert(left == dest, "left and dest must be equal");
1734
1735 XMMRegister lreg = left->as_xmm_double_reg();
1736 if (right->is_double_xmm()) {
1737 XMMRegister rreg = right->as_xmm_double_reg();
1738 switch (code) {
1739 case lir_add: __ addsd(lreg, rreg); break;
1740 case lir_sub: __ subsd(lreg, rreg); break;
1741 case lir_mul: __ mulsd(lreg, rreg); break;
1742 case lir_div: __ divsd(lreg, rreg); break;
1743 default: ShouldNotReachHere();
1744 }
1745 } else {
1746 Address raddr;
1747 if (right->is_double_stack()) {
1748 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1749 } else if (right->is_constant()) {
1750 // hack for now
1751 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
1752 } else {
1753 ShouldNotReachHere();
1754 }
1755 switch (code) {
1756 case lir_add: __ addsd(lreg, raddr); break;
1757 case lir_sub: __ subsd(lreg, raddr); break;
1758 case lir_mul: __ mulsd(lreg, raddr); break;
1759 case lir_div: __ divsd(lreg, raddr); break;
1760 default: ShouldNotReachHere();
1761 }
1762 }
1763
1764 } else if (left->is_single_stack() || left->is_address()) {
1765 assert(left == dest, "left and dest must be equal");
1766
1767 Address laddr;
1768 if (left->is_single_stack()) {
1769 laddr = frame_map()->address_for_slot(left->single_stack_ix());
1770 } else if (left->is_address()) {
1771 laddr = as_Address(left->as_address_ptr());
1772 } else {
1773 ShouldNotReachHere();
1774 }
1775
1776 if (right->is_single_cpu()) {
1777 Register rreg = right->as_register();
1778 switch (code) {
1779 case lir_add: __ addl(laddr, rreg); break;
1780 case lir_sub: __ subl(laddr, rreg); break;
1781 default: ShouldNotReachHere();
1782 }
1783 } else if (right->is_constant()) {
1784 jint c = right->as_constant_ptr()->as_jint();
1785 switch (code) {
1786 case lir_add: {
1787 __ incrementl(laddr, c);
1788 break;
1789 }
1790 case lir_sub: {
1791 __ decrementl(laddr, c);
1792 break;
1793 }
1794 default: ShouldNotReachHere();
1795 }
1796 } else {
1797 ShouldNotReachHere();
1798 }
1799
1800 } else {
1801 ShouldNotReachHere();
1802 }
1803 }
1804
1805
1806 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1807 if (value->is_double_xmm()) {
1808 switch(code) {
1809 case lir_abs :
1810 {
1811 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
1812 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
1813 }
1814 assert(!tmp->is_valid(), "do not need temporary");
1815 __ andpd(dest->as_xmm_double_reg(),
1816 ExternalAddress((address)double_signmask_pool),
1817 rscratch1);
1818 }
1819 break;
1820
1821 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
1822 // all other intrinsics are not available in the SSE instruction set, so FPU is used
1823 default : ShouldNotReachHere();
1824 }
1825
1826 } else if (code == lir_f2hf) {
1827 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
1828 } else if (code == lir_hf2f) {
1829 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
1830 } else {
1831 Unimplemented();
1832 }
1833 }
1834
1835 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1836 // assert(left->destroys_register(), "check");
1837 if (left->is_single_cpu()) {
1838 Register reg = left->as_register();
1839 if (right->is_constant()) {
1840 int val = right->as_constant_ptr()->as_jint();
1841 switch (code) {
1842 case lir_logic_and: __ andl (reg, val); break;
1843 case lir_logic_or: __ orl (reg, val); break;
1844 case lir_logic_xor: __ xorl (reg, val); break;
1845 default: ShouldNotReachHere();
1846 }
1847 } else if (right->is_stack()) {
1848 // added support for stack operands
1849 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1850 switch (code) {
1851 case lir_logic_and: __ andl (reg, raddr); break;
1852 case lir_logic_or: __ orl (reg, raddr); break;
1853 case lir_logic_xor: __ xorl (reg, raddr); break;
1854 default: ShouldNotReachHere();
1855 }
1856 } else {
1857 Register rright = right->as_register();
1858 switch (code) {
1859 case lir_logic_and: __ andptr (reg, rright); break;
1860 case lir_logic_or : __ orptr (reg, rright); break;
1861 case lir_logic_xor: __ xorptr (reg, rright); break;
1862 default: ShouldNotReachHere();
1863 }
1864 }
1865 move_regs(reg, dst->as_register());
1866 } else {
1867 Register l_lo = left->as_register_lo();
1868 Register l_hi = left->as_register_hi();
1869 if (right->is_constant()) {
1870 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
1871 switch (code) {
1872 case lir_logic_and:
1873 __ andq(l_lo, rscratch1);
1874 break;
1875 case lir_logic_or:
1876 __ orq(l_lo, rscratch1);
1877 break;
1878 case lir_logic_xor:
1879 __ xorq(l_lo, rscratch1);
1880 break;
1881 default: ShouldNotReachHere();
1882 }
1883 } else {
1884 Register r_lo;
1885 if (is_reference_type(right->type())) {
1886 r_lo = right->as_register();
1887 } else {
1888 r_lo = right->as_register_lo();
1889 }
1890 switch (code) {
1891 case lir_logic_and:
1892 __ andptr(l_lo, r_lo);
1893 break;
1894 case lir_logic_or:
1895 __ orptr(l_lo, r_lo);
1896 break;
1897 case lir_logic_xor:
1898 __ xorptr(l_lo, r_lo);
1899 break;
1900 default: ShouldNotReachHere();
1901 }
1902 }
1903
1904 Register dst_lo = dst->as_register_lo();
1905 Register dst_hi = dst->as_register_hi();
1906
1907 move_regs(l_lo, dst_lo);
1908 }
1909 }
1910
1911
1912 // we assume that rax, and rdx can be overwritten
1913 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1914
1915 assert(left->is_single_cpu(), "left must be register");
1916 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1917 assert(result->is_single_cpu(), "result must be register");
1918
1919 // assert(left->destroys_register(), "check");
1920 // assert(right->destroys_register(), "check");
1921
1922 Register lreg = left->as_register();
1923 Register dreg = result->as_register();
1924
1925 if (right->is_constant()) {
1926 jint divisor = right->as_constant_ptr()->as_jint();
1927 assert(divisor > 0 && is_power_of_2(divisor), "must be");
1928 if (code == lir_idiv) {
1929 assert(lreg == rax, "must be rax,");
1930 assert(temp->as_register() == rdx, "tmp register must be rdx");
1931 __ cdql(); // sign extend into rdx:rax
1932 if (divisor == 2) {
1933 __ subl(lreg, rdx);
1934 } else {
1935 __ andl(rdx, divisor - 1);
1936 __ addl(lreg, rdx);
1937 }
1938 __ sarl(lreg, log2i_exact(divisor));
1939 move_regs(lreg, dreg);
1940 } else if (code == lir_irem) {
1941 Label done;
1942 __ mov(dreg, lreg);
1943 __ andl(dreg, 0x80000000 | (divisor - 1));
1944 __ jcc(Assembler::positive, done);
1945 __ decrement(dreg);
1946 __ orl(dreg, ~(divisor - 1));
1947 __ increment(dreg);
1948 __ bind(done);
1949 } else {
1950 ShouldNotReachHere();
1951 }
1952 } else {
1953 Register rreg = right->as_register();
1954 assert(lreg == rax, "left register must be rax,");
1955 assert(rreg != rdx, "right register must not be rdx");
1956 assert(temp->as_register() == rdx, "tmp register must be rdx");
1957
1958 move_regs(lreg, rax);
1959
1960 int idivl_offset = __ corrected_idivl(rreg);
1961 if (ImplicitDiv0Checks) {
1962 add_debug_info_for_div0(idivl_offset, info);
1963 }
1964 if (code == lir_irem) {
1965 move_regs(rdx, dreg); // result is in rdx
1966 } else {
1967 move_regs(rax, dreg);
1968 }
1969 }
1970 }
1971
1972
1973 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1974 if (opr1->is_single_cpu()) {
1975 Register reg1 = opr1->as_register();
1976 if (opr2->is_single_cpu()) {
1977 // cpu register - cpu register
1978 if (is_reference_type(opr1->type())) {
1979 __ cmpoop(reg1, opr2->as_register());
1980 } else {
1981 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1982 __ cmpl(reg1, opr2->as_register());
1983 }
1984 } else if (opr2->is_stack()) {
1985 // cpu register - stack
1986 if (is_reference_type(opr1->type())) {
1987 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1988 } else {
1989 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1990 }
1991 } else if (opr2->is_constant()) {
1992 // cpu register - constant
1993 LIR_Const* c = opr2->as_constant_ptr();
1994 if (c->type() == T_INT) {
1995 jint i = c->as_jint();
1996 if (i == 0) {
1997 __ testl(reg1, reg1);
1998 } else {
1999 __ cmpl(reg1, i);
2000 }
2001 } else if (c->type() == T_METADATA) {
2002 // All we need for now is a comparison with null for equality.
2003 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2004 Metadata* m = c->as_metadata();
2005 if (m == nullptr) {
2006 __ testptr(reg1, reg1);
2007 } else {
2008 ShouldNotReachHere();
2009 }
2010 } else if (is_reference_type(c->type())) {
2011 // In 64bit oops are single register
2012 jobject o = c->as_jobject();
2013 if (o == nullptr) {
2014 __ testptr(reg1, reg1);
2015 } else {
2016 __ cmpoop(reg1, o, rscratch1);
2017 }
2018 } else {
2019 fatal("unexpected type: %s", basictype_to_str(c->type()));
2020 }
2021 // cpu register - address
2022 } else if (opr2->is_address()) {
2023 if (op->info() != nullptr) {
2024 add_debug_info_for_null_check_here(op->info());
2025 }
2026 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030
2031 } else if(opr1->is_double_cpu()) {
2032 Register xlo = opr1->as_register_lo();
2033 Register xhi = opr1->as_register_hi();
2034 if (opr2->is_double_cpu()) {
2035 __ cmpptr(xlo, opr2->as_register_lo());
2036 } else if (opr2->is_constant()) {
2037 // cpu register - constant 0
2038 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2039 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2040 } else {
2041 ShouldNotReachHere();
2042 }
2043
2044 } else if (opr1->is_single_xmm()) {
2045 XMMRegister reg1 = opr1->as_xmm_float_reg();
2046 if (opr2->is_single_xmm()) {
2047 // xmm register - xmm register
2048 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2049 } else if (opr2->is_stack()) {
2050 // xmm register - stack
2051 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2052 } else if (opr2->is_constant()) {
2053 // xmm register - constant
2054 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2055 } else if (opr2->is_address()) {
2056 // xmm register - address
2057 if (op->info() != nullptr) {
2058 add_debug_info_for_null_check_here(op->info());
2059 }
2060 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2061 } else {
2062 ShouldNotReachHere();
2063 }
2064
2065 } else if (opr1->is_double_xmm()) {
2066 XMMRegister reg1 = opr1->as_xmm_double_reg();
2067 if (opr2->is_double_xmm()) {
2068 // xmm register - xmm register
2069 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2070 } else if (opr2->is_stack()) {
2071 // xmm register - stack
2072 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2073 } else if (opr2->is_constant()) {
2074 // xmm register - constant
2075 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2076 } else if (opr2->is_address()) {
2077 // xmm register - address
2078 if (op->info() != nullptr) {
2079 add_debug_info_for_null_check_here(op->info());
2080 }
2081 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2082 } else {
2083 ShouldNotReachHere();
2084 }
2085
2086 } else if (opr1->is_address() && opr2->is_constant()) {
2087 LIR_Const* c = opr2->as_constant_ptr();
2088 if (is_reference_type(c->type())) {
2089 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2090 __ movoop(rscratch1, c->as_jobject());
2091 }
2092 if (op->info() != nullptr) {
2093 add_debug_info_for_null_check_here(op->info());
2094 }
2095 // special case: address - constant
2096 LIR_Address* addr = opr1->as_address_ptr();
2097 if (c->type() == T_INT) {
2098 __ cmpl(as_Address(addr), c->as_jint());
2099 } else if (is_reference_type(c->type())) {
2100 // %%% Make this explode if addr isn't reachable until we figure out a
2101 // better strategy by giving noreg as the temp for as_Address
2102 __ cmpoop(rscratch1, as_Address(addr, noreg));
2103 } else {
2104 ShouldNotReachHere();
2105 }
2106
2107 } else {
2108 ShouldNotReachHere();
2109 }
2110 }
2111
2112 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2113 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2114 if (left->is_single_xmm()) {
2115 assert(right->is_single_xmm(), "must match");
2116 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2117 } else if (left->is_double_xmm()) {
2118 assert(right->is_double_xmm(), "must match");
2119 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2120
2121 } else {
2122 ShouldNotReachHere();
2123 }
2124 } else {
2125 assert(code == lir_cmp_l2i, "check");
2126 Label done;
2127 Register dest = dst->as_register();
2128 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2129 __ movl(dest, -1);
2130 __ jccb(Assembler::less, done);
2131 __ setb(Assembler::notZero, dest);
2132 __ movzbl(dest, dest);
2133 __ bind(done);
2134 }
2135 }
2136
2137
2138 void LIR_Assembler::align_call(LIR_Code code) {
2139 // make sure that the displacement word of the call ends up word aligned
2140 int offset = __ offset();
2141 switch (code) {
2142 case lir_static_call:
2143 case lir_optvirtual_call:
2144 case lir_dynamic_call:
2145 offset += NativeCall::displacement_offset;
2146 break;
2147 case lir_icvirtual_call:
2148 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2149 break;
2150 default: ShouldNotReachHere();
2151 }
2152 __ align(BytesPerWord, offset);
2153 }
2154
2155
2156 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2157 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2158 "must be aligned");
2159 __ call(AddressLiteral(op->addr(), rtype));
2160 add_call_info(code_offset(), op->info());
2161 __ post_call_nop();
2162 }
2163
2164
2165 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2166 __ ic_call(op->addr());
2167 add_call_info(code_offset(), op->info());
2168 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2169 "must be aligned");
2170 __ post_call_nop();
2171 }
2172
2173
2174 void LIR_Assembler::emit_static_call_stub() {
2175 address call_pc = __ pc();
2176 address stub = __ start_a_stub(call_stub_size());
2177 if (stub == nullptr) {
2178 bailout("static call stub overflow");
2179 return;
2180 }
2181
2182 int start = __ offset();
2183
2184 // make sure that the displacement word of the call ends up word aligned
2185 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2186 __ relocate(static_stub_Relocation::spec(call_pc));
2187 __ mov_metadata(rbx, (Metadata*)nullptr);
2188 // must be set to -1 at code generation time
2189 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2190 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2191 __ jump(RuntimeAddress(__ pc()));
2192
2193 assert(__ offset() - start <= call_stub_size(), "stub too big");
2194 __ end_a_stub();
2195 }
2196
2197
2198 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2199 assert(exceptionOop->as_register() == rax, "must match");
2200 assert(exceptionPC->as_register() == rdx, "must match");
2201
2202 // exception object is not added to oop map by LinearScan
2203 // (LinearScan assumes that no oops are in fixed registers)
2204 info->add_register_oop(exceptionOop);
2205 StubId unwind_id;
2206
2207 // get current pc information
2208 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2209 int pc_for_athrow_offset = __ offset();
2210 InternalAddress pc_for_athrow(__ pc());
2211 __ lea(exceptionPC->as_register(), pc_for_athrow);
2212 add_call_info(pc_for_athrow_offset, info); // for exception handler
2213
2214 __ verify_not_null_oop(rax);
2215 // search an exception handler (rax: exception oop, rdx: throwing pc)
2216 if (compilation()->has_fpu_code()) {
2217 unwind_id = StubId::c1_handle_exception_id;
2218 } else {
2219 unwind_id = StubId::c1_handle_exception_nofpu_id;
2220 }
2221 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2222
2223 // enough room for two byte trap
2224 __ nop();
2225 }
2226
2227
2228 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2229 assert(exceptionOop->as_register() == rax, "must match");
2230
2231 __ jmp(_unwind_handler_entry);
2232 }
2233
2234
2235 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2236
2237 // optimized version for linear scan:
2238 // * count must be already in ECX (guaranteed by LinearScan)
2239 // * left and dest must be equal
2240 // * tmp must be unused
2241 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2242 assert(left == dest, "left and dest must be equal");
2243 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2244
2245 if (left->is_single_cpu()) {
2246 Register value = left->as_register();
2247 assert(value != SHIFT_count, "left cannot be ECX");
2248
2249 switch (code) {
2250 case lir_shl: __ shll(value); break;
2251 case lir_shr: __ sarl(value); break;
2252 case lir_ushr: __ shrl(value); break;
2253 default: ShouldNotReachHere();
2254 }
2255 } else if (left->is_double_cpu()) {
2256 Register lo = left->as_register_lo();
2257 Register hi = left->as_register_hi();
2258 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2259 switch (code) {
2260 case lir_shl: __ shlptr(lo); break;
2261 case lir_shr: __ sarptr(lo); break;
2262 case lir_ushr: __ shrptr(lo); break;
2263 default: ShouldNotReachHere();
2264 }
2265 } else {
2266 ShouldNotReachHere();
2267 }
2268 }
2269
2270
2271 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2272 if (dest->is_single_cpu()) {
2273 // first move left into dest so that left is not destroyed by the shift
2274 Register value = dest->as_register();
2275 count = count & 0x1F; // Java spec
2276
2277 move_regs(left->as_register(), value);
2278 switch (code) {
2279 case lir_shl: __ shll(value, count); break;
2280 case lir_shr: __ sarl(value, count); break;
2281 case lir_ushr: __ shrl(value, count); break;
2282 default: ShouldNotReachHere();
2283 }
2284 } else if (dest->is_double_cpu()) {
2285 // first move left into dest so that left is not destroyed by the shift
2286 Register value = dest->as_register_lo();
2287 count = count & 0x1F; // Java spec
2288
2289 move_regs(left->as_register_lo(), value);
2290 switch (code) {
2291 case lir_shl: __ shlptr(value, count); break;
2292 case lir_shr: __ sarptr(value, count); break;
2293 case lir_ushr: __ shrptr(value, count); break;
2294 default: ShouldNotReachHere();
2295 }
2296 } else {
2297 ShouldNotReachHere();
2298 }
2299 }
2300
2301
2302 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2303 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2304 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2305 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2306 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2307 }
2308
2309
2310 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2311 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2312 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2313 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2314 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2315 }
2316
2317
2318 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2319 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2320 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2321 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2322 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
2323 }
2324
2325
2326 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
2327 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2328 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2329 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2330 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
2331 }
2332
2333
2334 // This code replaces a call to arraycopy; no exception may
2335 // be thrown in this code, they must be thrown in the System.arraycopy
2336 // activation frame; we could save some checks if this would not be the case
2337 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2338 ciArrayKlass* default_type = op->expected_type();
2339 Register src = op->src()->as_register();
2340 Register dst = op->dst()->as_register();
2341 Register src_pos = op->src_pos()->as_register();
2342 Register dst_pos = op->dst_pos()->as_register();
2343 Register length = op->length()->as_register();
2344 Register tmp = op->tmp()->as_register();
2345 Register tmp_load_klass = rscratch1;
2346 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
2347
2348 CodeStub* stub = op->stub();
2349 int flags = op->flags();
2350 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2351 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2352
2353 // if we don't know anything, just go through the generic arraycopy
2354 if (default_type == nullptr) {
2355 // save outgoing arguments on stack in case call to System.arraycopy is needed
2356 // HACK ALERT. This code used to push the parameters in a hardwired fashion
2357 // for interpreter calling conventions. Now we have to do it in new style conventions.
2358 // For the moment until C1 gets the new register allocator I just force all the
2359 // args to the right place (except the register args) and then on the back side
2360 // reload the register args properly if we go slow path. Yuck
2361
2362 // These are proper for the calling convention
2363 store_parameter(length, 2);
2364 store_parameter(dst_pos, 1);
2365 store_parameter(dst, 0);
2366
2367 // these are just temporary placements until we need to reload
2368 store_parameter(src_pos, 3);
2369 store_parameter(src, 4);
2370
2371 address copyfunc_addr = StubRoutines::generic_arraycopy();
2372 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2373
2374 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
2375 // The arguments are in java calling convention so we can trivially shift them to C
2376 // convention
2377 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2378 __ mov(c_rarg0, j_rarg0);
2379 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2380 __ mov(c_rarg1, j_rarg1);
2381 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2382 __ mov(c_rarg2, j_rarg2);
2383 assert_different_registers(c_rarg3, j_rarg4);
2384 __ mov(c_rarg3, j_rarg3);
2385 #ifdef _WIN64
2386 // Allocate abi space for args but be sure to keep stack aligned
2387 __ subptr(rsp, 6*wordSize);
2388 store_parameter(j_rarg4, 4);
2389 #ifndef PRODUCT
2390 if (PrintC1Statistics) {
2391 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
2392 }
2393 #endif
2394 __ call(RuntimeAddress(copyfunc_addr));
2395 __ addptr(rsp, 6*wordSize);
2396 #else
2397 __ mov(c_rarg4, j_rarg4);
2398 #ifndef PRODUCT
2399 if (PrintC1Statistics) {
2400 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
2401 }
2402 #endif
2403 __ call(RuntimeAddress(copyfunc_addr));
2404 #endif // _WIN64
2405
2406 __ testl(rax, rax);
2407 __ jcc(Assembler::equal, *stub->continuation());
2408
2409 __ mov(tmp, rax);
2410 __ xorl(tmp, -1);
2411
2412 // Reload values from the stack so they are where the stub
2413 // expects them.
2414 __ movptr (dst, Address(rsp, 0*BytesPerWord));
2415 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
2416 __ movptr (length, Address(rsp, 2*BytesPerWord));
2417 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
2418 __ movptr (src, Address(rsp, 4*BytesPerWord));
2419
2420 __ subl(length, tmp);
2421 __ addl(src_pos, tmp);
2422 __ addl(dst_pos, tmp);
2423 __ jmp(*stub->entry());
2424
2425 __ bind(*stub->continuation());
2426 return;
2427 }
2428
2429 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2430
2431 int elem_size = type2aelembytes(basic_type);
2432 Address::ScaleFactor scale;
2433
2434 switch (elem_size) {
2435 case 1 :
2436 scale = Address::times_1;
2437 break;
2438 case 2 :
2439 scale = Address::times_2;
2440 break;
2441 case 4 :
2442 scale = Address::times_4;
2443 break;
2444 case 8 :
2445 scale = Address::times_8;
2446 break;
2447 default:
2448 scale = Address::no_scale;
2449 ShouldNotReachHere();
2450 }
2451
2452 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2453 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2454
2455 // length and pos's are all sign extended at this point on 64bit
2456
2457 // test for null
2458 if (flags & LIR_OpArrayCopy::src_null_check) {
2459 __ testptr(src, src);
2460 __ jcc(Assembler::zero, *stub->entry());
2461 }
2462 if (flags & LIR_OpArrayCopy::dst_null_check) {
2463 __ testptr(dst, dst);
2464 __ jcc(Assembler::zero, *stub->entry());
2465 }
2466
2467 // If the compiler was not able to prove that exact type of the source or the destination
2468 // of the arraycopy is an array type, check at runtime if the source or the destination is
2469 // an instance type.
2470 if (flags & LIR_OpArrayCopy::type_check) {
2471 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2472 __ load_klass(tmp, dst, tmp_load_klass);
2473 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
2474 __ jcc(Assembler::greaterEqual, *stub->entry());
2475 }
2476
2477 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2478 __ load_klass(tmp, src, tmp_load_klass);
2479 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
2480 __ jcc(Assembler::greaterEqual, *stub->entry());
2481 }
2482 }
2483
2484 // check if negative
2485 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2486 __ testl(src_pos, src_pos);
2487 __ jcc(Assembler::less, *stub->entry());
2488 }
2489 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2490 __ testl(dst_pos, dst_pos);
2491 __ jcc(Assembler::less, *stub->entry());
2492 }
2493
2494 if (flags & LIR_OpArrayCopy::src_range_check) {
2495 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
2496 __ cmpl(tmp, src_length_addr);
2497 __ jcc(Assembler::above, *stub->entry());
2498 }
2499 if (flags & LIR_OpArrayCopy::dst_range_check) {
2500 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
2501 __ cmpl(tmp, dst_length_addr);
2502 __ jcc(Assembler::above, *stub->entry());
2503 }
2504
2505 if (flags & LIR_OpArrayCopy::length_positive_check) {
2506 __ testl(length, length);
2507 __ jcc(Assembler::less, *stub->entry());
2508 }
2509
2510 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
2511 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
2512
2513 if (flags & LIR_OpArrayCopy::type_check) {
2514 // We don't know the array types are compatible
2515 if (basic_type != T_OBJECT) {
2516 // Simple test for basic type arrays
2517 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
2518 __ jcc(Assembler::notEqual, *stub->entry());
2519 } else {
2520 // For object arrays, if src is a sub class of dst then we can
2521 // safely do the copy.
2522 Label cont, slow;
2523
2524 __ push_ppx(src);
2525 __ push_ppx(dst);
2526
2527 __ load_klass(src, src, tmp_load_klass);
2528 __ load_klass(dst, dst, tmp_load_klass);
2529
2530 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2531
2532 __ push_ppx(src);
2533 __ push_ppx(dst);
2534 __ call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2535 __ pop_ppx(dst);
2536 __ pop_ppx(src);
2537
2538 __ testl(src, src);
2539 __ jcc(Assembler::notEqual, cont);
2540
2541 __ bind(slow);
2542 __ pop_ppx(dst);
2543 __ pop_ppx(src);
2544
2545 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2546 if (copyfunc_addr != nullptr) { // use stub if available
2547 // src is not a sub class of dst so we have to do a
2548 // per-element check.
2549
2550 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2551 if ((flags & mask) != mask) {
2552 // Check that at least both of them object arrays.
2553 assert(flags & mask, "one of the two should be known to be an object array");
2554
2555 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2556 __ load_klass(tmp, src, tmp_load_klass);
2557 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2558 __ load_klass(tmp, dst, tmp_load_klass);
2559 }
2560 int lh_offset = in_bytes(Klass::layout_helper_offset());
2561 Address klass_lh_addr(tmp, lh_offset);
2562 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2563 __ cmpl(klass_lh_addr, objArray_lh);
2564 __ jcc(Assembler::notEqual, *stub->entry());
2565 }
2566
2567 // Spill because stubs can use any register they like and it's
2568 // easier to restore just those that we care about.
2569 store_parameter(dst, 0);
2570 store_parameter(dst_pos, 1);
2571 store_parameter(length, 2);
2572 store_parameter(src_pos, 3);
2573 store_parameter(src, 4);
2574
2575 __ movl2ptr(length, length); //higher 32bits must be null
2576
2577 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2578 assert_different_registers(c_rarg0, dst, dst_pos, length);
2579 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2580 assert_different_registers(c_rarg1, dst, length);
2581
2582 __ mov(c_rarg2, length);
2583 assert_different_registers(c_rarg2, dst);
2584
2585 #ifdef _WIN64
2586 // Allocate abi space for args but be sure to keep stack aligned
2587 __ subptr(rsp, 6*wordSize);
2588 __ load_klass(c_rarg3, dst, tmp_load_klass);
2589 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
2590 store_parameter(c_rarg3, 4);
2591 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
2592 __ call(RuntimeAddress(copyfunc_addr));
2593 __ addptr(rsp, 6*wordSize);
2594 #else
2595 __ load_klass(c_rarg4, dst, tmp_load_klass);
2596 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2597 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2598 __ call(RuntimeAddress(copyfunc_addr));
2599 #endif
2600
2601 #ifndef PRODUCT
2602 if (PrintC1Statistics) {
2603 Label failed;
2604 __ testl(rax, rax);
2605 __ jcc(Assembler::notZero, failed);
2606 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
2607 __ bind(failed);
2608 }
2609 #endif
2610
2611 __ testl(rax, rax);
2612 __ jcc(Assembler::zero, *stub->continuation());
2613
2614 #ifndef PRODUCT
2615 if (PrintC1Statistics) {
2616 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
2617 }
2618 #endif
2619
2620 __ mov(tmp, rax);
2621
2622 __ xorl(tmp, -1);
2623
2624 // Restore previously spilled arguments
2625 __ movptr (dst, Address(rsp, 0*BytesPerWord));
2626 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
2627 __ movptr (length, Address(rsp, 2*BytesPerWord));
2628 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
2629 __ movptr (src, Address(rsp, 4*BytesPerWord));
2630
2631
2632 __ subl(length, tmp);
2633 __ addl(src_pos, tmp);
2634 __ addl(dst_pos, tmp);
2635 }
2636
2637 __ jmp(*stub->entry());
2638
2639 __ bind(cont);
2640 __ pop(dst);
2641 __ pop(src);
2642 }
2643 }
2644
2645 #ifdef ASSERT
2646 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2647 // Sanity check the known type with the incoming class. For the
2648 // primitive case the types must match exactly with src.klass and
2649 // dst.klass each exactly matching the default type. For the
2650 // object array case, if no type check is needed then either the
2651 // dst type is exactly the expected type and the src type is a
2652 // subtype which we can't check or src is the same array as dst
2653 // but not necessarily exactly of type default_type.
2654 Label known_ok, halt;
2655 __ mov_metadata(tmp, default_type->constant_encoding());
2656 __ encode_klass_not_null(tmp, rscratch1);
2657
2658 if (basic_type != T_OBJECT) {
2659 __ cmp_klass(tmp, dst, tmp2);
2660 __ jcc(Assembler::notEqual, halt);
2661 __ cmp_klass(tmp, src, tmp2);
2662 __ jcc(Assembler::equal, known_ok);
2663 } else {
2664 __ cmp_klass(tmp, dst, tmp2);
2665 __ jcc(Assembler::equal, known_ok);
2666 __ cmpptr(src, dst);
2667 __ jcc(Assembler::equal, known_ok);
2668 }
2669 __ bind(halt);
2670 __ stop("incorrect type information in arraycopy");
2671 __ bind(known_ok);
2672 }
2673 #endif
2674
2675 #ifndef PRODUCT
2676 if (PrintC1Statistics) {
2677 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
2678 }
2679 #endif
2680
2681 assert_different_registers(c_rarg0, dst, dst_pos, length);
2682 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2683 assert_different_registers(c_rarg1, length);
2684 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2685 __ mov(c_rarg2, length);
2686
2687 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2688 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2689 const char *name;
2690 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2691 __ call_VM_leaf(entry, 0);
2692
2693 if (stub != nullptr) {
2694 __ bind(*stub->continuation());
2695 }
2696 }
2697
2698 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2699 assert(op->crc()->is_single_cpu(), "crc must be register");
2700 assert(op->val()->is_single_cpu(), "byte value must be register");
2701 assert(op->result_opr()->is_single_cpu(), "result must be register");
2702 Register crc = op->crc()->as_register();
2703 Register val = op->val()->as_register();
2704 Register res = op->result_opr()->as_register();
2705
2706 assert_different_registers(val, crc, res);
2707
2708 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
2709 __ notl(crc); // ~crc
2710 __ update_byte_crc32(crc, val, res);
2711 __ notl(crc); // ~crc
2712 __ mov(res, crc);
2713 }
2714
2715 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2716 Register obj = op->obj_opr()->as_register(); // may not be an oop
2717 Register hdr = op->hdr_opr()->as_register();
2718 Register lock = op->lock_opr()->as_register();
2719 if (op->code() == lir_lock) {
2720 Register tmp = op->scratch_opr()->as_register();
2721 // add debug info for NullPointerException only if one is possible
2722 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2723 if (op->info() != nullptr) {
2724 add_debug_info_for_null_check(null_check_offset, op->info());
2725 }
2726 // done
2727 } else if (op->code() == lir_unlock) {
2728 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2729 } else {
2730 Unimplemented();
2731 }
2732 __ bind(*op->stub()->continuation());
2733 }
2734
2735 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2736 Register obj = op->obj()->as_pointer_register();
2737 Register result = op->result_opr()->as_pointer_register();
2738
2739 CodeEmitInfo* info = op->info();
2740 if (info != nullptr) {
2741 add_debug_info_for_null_check_here(info);
2742 }
2743
2744 __ load_klass(result, obj, rscratch1);
2745 }
2746
2747 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2748 ciMethod* method = op->profiled_method();
2749 int bci = op->profiled_bci();
2750 ciMethod* callee = op->profiled_callee();
2751 Register tmp_load_klass = rscratch1;
2752
2753 // Update counter for all call types
2754 ciMethodData* md = method->method_data_or_null();
2755 assert(md != nullptr, "Sanity");
2756 ciProfileData* data = md->bci_to_data(bci);
2757 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2758 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2759 Register mdo = op->mdo()->as_register();
2760 __ mov_metadata(mdo, md->constant_encoding());
2761 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2762 // Perform additional virtual call profiling for invokevirtual and
2763 // invokeinterface bytecodes
2764 if (op->should_profile_receiver_type()) {
2765 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2766 Register recv = op->recv()->as_register();
2767 assert_different_registers(mdo, recv);
2768 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2769 ciKlass* known_klass = op->known_holder();
2770 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2771 // We know the type that will be seen at this call site; we can
2772 // statically update the MethodData* rather than needing to do
2773 // dynamic tests on the receiver type.
2774 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2775 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2776 ciKlass* receiver = vc_data->receiver(i);
2777 if (known_klass->equals(receiver)) {
2778 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2779 __ addptr(data_addr, DataLayout::counter_increment);
2780 return;
2781 }
2782 }
2783 // Receiver type is not found in profile data.
2784 // Fall back to runtime helper to handle the rest at runtime.
2785 __ mov_metadata(recv, known_klass->constant_encoding());
2786 } else {
2787 __ load_klass(recv, recv, tmp_load_klass);
2788 }
2789 type_profile_helper(mdo, md, data, recv);
2790 } else {
2791 // Static call
2792 __ addptr(counter_addr, DataLayout::counter_increment);
2793 }
2794 }
2795
2796 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2797 Register obj = op->obj()->as_register();
2798 Register tmp = op->tmp()->as_pointer_register();
2799 Register tmp_load_klass = rscratch1;
2800 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2801 ciKlass* exact_klass = op->exact_klass();
2802 intptr_t current_klass = op->current_klass();
2803 bool not_null = op->not_null();
2804 bool no_conflict = op->no_conflict();
2805
2806 Label update, next, none;
2807
2808 bool do_null = !not_null;
2809 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2810 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2811
2812 assert(do_null || do_update, "why are we here?");
2813 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2814
2815 __ verify_oop(obj);
2816
2817 #ifdef ASSERT
2818 if (obj == tmp) {
2819 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
2820 } else {
2821 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
2822 }
2823 #endif
2824 if (do_null) {
2825 __ testptr(obj, obj);
2826 __ jccb(Assembler::notZero, update);
2827 if (!TypeEntries::was_null_seen(current_klass)) {
2828 __ testptr(mdo_addr, TypeEntries::null_seen);
2829 #ifndef ASSERT
2830 __ jccb(Assembler::notZero, next); // already set
2831 #else
2832 __ jcc(Assembler::notZero, next); // already set
2833 #endif
2834 // atomic update to prevent overwriting Klass* with 0
2835 __ lock();
2836 __ orptr(mdo_addr, TypeEntries::null_seen);
2837 }
2838 if (do_update) {
2839 #ifndef ASSERT
2840 __ jmpb(next);
2841 }
2842 #else
2843 __ jmp(next);
2844 }
2845 } else {
2846 __ testptr(obj, obj);
2847 __ jcc(Assembler::notZero, update);
2848 __ stop("unexpected null obj");
2849 #endif
2850 }
2851
2852 __ bind(update);
2853
2854 if (do_update) {
2855 #ifdef ASSERT
2856 if (exact_klass != nullptr) {
2857 Label ok;
2858 __ load_klass(tmp, obj, tmp_load_klass);
2859 __ push_ppx(tmp);
2860 __ mov_metadata(tmp, exact_klass->constant_encoding());
2861 __ cmpptr(tmp, Address(rsp, 0));
2862 __ jcc(Assembler::equal, ok);
2863 __ stop("exact klass and actual klass differ");
2864 __ bind(ok);
2865 __ pop_ppx(tmp);
2866 }
2867 #endif
2868 if (!no_conflict) {
2869 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2870 if (exact_klass != nullptr) {
2871 __ mov_metadata(tmp, exact_klass->constant_encoding());
2872 } else {
2873 __ load_klass(tmp, obj, tmp_load_klass);
2874 }
2875 __ mov(rscratch1, tmp); // save original value before XOR
2876 __ xorptr(tmp, mdo_addr);
2877 __ testptr(tmp, TypeEntries::type_klass_mask);
2878 // klass seen before, nothing to do. The unknown bit may have been
2879 // set already but no need to check.
2880 __ jccb(Assembler::zero, next);
2881
2882 __ testptr(tmp, TypeEntries::type_unknown);
2883 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2884
2885 if (TypeEntries::is_type_none(current_klass)) {
2886 __ testptr(mdo_addr, TypeEntries::type_mask);
2887 __ jccb(Assembler::zero, none);
2888 // There is a chance that the checks above (re-reading profiling
2889 // data from memory) fail if another thread has just set the
2890 // profiling to this obj's klass
2891 __ mov(tmp, rscratch1); // get back original value before XOR
2892 __ xorptr(tmp, mdo_addr);
2893 __ testptr(tmp, TypeEntries::type_klass_mask);
2894 __ jccb(Assembler::zero, next);
2895 }
2896 } else {
2897 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2898 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2899
2900 __ testptr(mdo_addr, TypeEntries::type_unknown);
2901 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2902 }
2903
2904 // different than before. Cannot keep accurate profile.
2905 __ orptr(mdo_addr, TypeEntries::type_unknown);
2906
2907 if (TypeEntries::is_type_none(current_klass)) {
2908 __ jmpb(next);
2909
2910 __ bind(none);
2911 // first time here. Set profile type.
2912 __ movptr(mdo_addr, tmp);
2913 #ifdef ASSERT
2914 __ andptr(tmp, TypeEntries::type_klass_mask);
2915 __ verify_klass_ptr(tmp);
2916 #endif
2917 }
2918 } else {
2919 // There's a single possible klass at this profile point
2920 assert(exact_klass != nullptr, "should be");
2921 if (TypeEntries::is_type_none(current_klass)) {
2922 __ mov_metadata(tmp, exact_klass->constant_encoding());
2923 __ xorptr(tmp, mdo_addr);
2924 __ testptr(tmp, TypeEntries::type_klass_mask);
2925 #ifdef ASSERT
2926 __ jcc(Assembler::zero, next);
2927
2928 {
2929 Label ok;
2930 __ push_ppx(tmp);
2931 __ testptr(mdo_addr, TypeEntries::type_mask);
2932 __ jcc(Assembler::zero, ok);
2933 // may have been set by another thread
2934 __ mov_metadata(tmp, exact_klass->constant_encoding());
2935 __ xorptr(tmp, mdo_addr);
2936 __ testptr(tmp, TypeEntries::type_mask);
2937 __ jcc(Assembler::zero, ok);
2938
2939 __ stop("unexpected profiling mismatch");
2940 __ bind(ok);
2941 __ pop_ppx(tmp);
2942 }
2943 #else
2944 __ jccb(Assembler::zero, next);
2945 #endif
2946 // first time here. Set profile type.
2947 __ movptr(mdo_addr, tmp);
2948 #ifdef ASSERT
2949 __ andptr(tmp, TypeEntries::type_klass_mask);
2950 __ verify_klass_ptr(tmp);
2951 #endif
2952 } else {
2953 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2954 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2955
2956 __ testptr(mdo_addr, TypeEntries::type_unknown);
2957 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2958
2959 __ orptr(mdo_addr, TypeEntries::type_unknown);
2960 }
2961 }
2962 }
2963 __ bind(next);
2964 }
2965
2966 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2967 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2968 }
2969
2970
2971 void LIR_Assembler::align_backward_branch_target() {
2972 __ align(BytesPerWord);
2973 }
2974
2975
2976 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2977 if (left->is_single_cpu()) {
2978 __ negl(left->as_register());
2979 move_regs(left->as_register(), dest->as_register());
2980
2981 } else if (left->is_double_cpu()) {
2982 Register lo = left->as_register_lo();
2983 Register dst = dest->as_register_lo();
2984 __ movptr(dst, lo);
2985 __ negptr(dst);
2986
2987 } else if (dest->is_single_xmm()) {
2988 assert(!tmp->is_valid(), "do not need temporary");
2989 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
2990 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
2991 }
2992 __ xorps(dest->as_xmm_float_reg(),
2993 ExternalAddress((address)float_signflip_pool),
2994 rscratch1);
2995 } else if (dest->is_double_xmm()) {
2996 assert(!tmp->is_valid(), "do not need temporary");
2997 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
2998 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
2999 }
3000 __ xorpd(dest->as_xmm_double_reg(),
3001 ExternalAddress((address)double_signflip_pool),
3002 rscratch1);
3003 } else {
3004 ShouldNotReachHere();
3005 }
3006 }
3007
3008
3009 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3010 assert(src->is_address(), "must be an address");
3011 assert(dest->is_register(), "must be a register");
3012
3013 PatchingStub* patch = nullptr;
3014 if (patch_code != lir_patch_none) {
3015 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3016 }
3017
3018 Register reg = dest->as_pointer_register();
3019 LIR_Address* addr = src->as_address_ptr();
3020 __ lea(reg, as_Address(addr));
3021
3022 if (patch != nullptr) {
3023 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3024 }
3025 }
3026
3027
3028
3029 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3030 assert(!tmp->is_valid(), "don't need temporary");
3031 __ call(RuntimeAddress(dest));
3032 if (info != nullptr) {
3033 add_call_info_here(info);
3034 }
3035 __ post_call_nop();
3036 }
3037
3038
3039 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3040 assert(type == T_LONG, "only for volatile long fields");
3041
3042 if (info != nullptr) {
3043 add_debug_info_for_null_check_here(info);
3044 }
3045
3046 if (src->is_double_xmm()) {
3047 if (dest->is_double_cpu()) {
3048 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3049 } else if (dest->is_double_stack()) {
3050 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3051 } else if (dest->is_address()) {
3052 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3053 } else {
3054 ShouldNotReachHere();
3055 }
3056
3057 } else if (dest->is_double_xmm()) {
3058 if (src->is_double_stack()) {
3059 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3060 } else if (src->is_address()) {
3061 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3062 } else {
3063 ShouldNotReachHere();
3064 }
3065
3066 } else {
3067 ShouldNotReachHere();
3068 }
3069 }
3070
3071 #ifdef ASSERT
3072 // emit run-time assertion
3073 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3074 assert(op->code() == lir_assert, "must be");
3075
3076 if (op->in_opr1()->is_valid()) {
3077 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3078 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3079 } else {
3080 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3081 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3082 }
3083
3084 Label ok;
3085 if (op->condition() != lir_cond_always) {
3086 Assembler::Condition acond = Assembler::zero;
3087 switch (op->condition()) {
3088 case lir_cond_equal: acond = Assembler::equal; break;
3089 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3090 case lir_cond_less: acond = Assembler::less; break;
3091 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3092 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3093 case lir_cond_greater: acond = Assembler::greater; break;
3094 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3095 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3096 default: ShouldNotReachHere();
3097 }
3098 __ jcc(acond, ok);
3099 }
3100 if (op->halt()) {
3101 const char* str = __ code_string(op->msg());
3102 __ stop(str);
3103 } else {
3104 breakpoint();
3105 }
3106 __ bind(ok);
3107 }
3108 #endif
3109
3110 void LIR_Assembler::membar() {
3111 // QQQ sparc TSO uses this,
3112 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3113 }
3114
3115 void LIR_Assembler::membar_acquire() {
3116 // No x86 machines currently require load fences
3117 }
3118
3119 void LIR_Assembler::membar_release() {
3120 // No x86 machines currently require store fences
3121 }
3122
3123 void LIR_Assembler::membar_loadload() {
3124 // no-op
3125 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3126 }
3127
3128 void LIR_Assembler::membar_storestore() {
3129 // no-op
3130 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3131 }
3132
3133 void LIR_Assembler::membar_loadstore() {
3134 // no-op
3135 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3136 }
3137
3138 void LIR_Assembler::membar_storeload() {
3139 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3140 }
3141
3142 void LIR_Assembler::on_spin_wait() {
3143 __ pause ();
3144 }
3145
3146 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3147 assert(result_reg->is_register(), "check");
3148 __ mov(result_reg->as_register(), r15_thread);
3149 }
3150
3151
3152 void LIR_Assembler::peephole(LIR_List*) {
3153 // do nothing for now
3154 }
3155
3156 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3157 assert(data == dest, "xchg/xadd uses only 2 operands");
3158
3159 if (data->type() == T_INT) {
3160 if (code == lir_xadd) {
3161 __ lock();
3162 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3163 } else {
3164 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3165 }
3166 } else if (data->is_oop()) {
3167 assert (code == lir_xchg, "xadd for oops");
3168 Register obj = data->as_register();
3169 if (UseCompressedOops) {
3170 __ encode_heap_oop(obj);
3171 __ xchgl(obj, as_Address(src->as_address_ptr()));
3172 __ decode_heap_oop(obj);
3173 } else {
3174 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3175 }
3176 } else if (data->type() == T_LONG) {
3177 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3178 if (code == lir_xadd) {
3179 __ lock();
3180 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3181 } else {
3182 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3183 }
3184 } else {
3185 ShouldNotReachHere();
3186 }
3187 }
3188
3189 #undef __