1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_CodeStubs.hpp"
  29 #include "c1/c1_Compilation.hpp"
  30 #include "c1/c1_LIRAssembler.hpp"
  31 #include "c1/c1_MacroAssembler.hpp"
  32 #include "c1/c1_Runtime1.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "ci/ciArrayKlass.hpp"
  35 #include "ci/ciInlineKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "compiler/oopMap.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/gc_globals.hpp"
  40 #include "nativeInst_x86.hpp"
  41 #include "oops/oop.inline.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/safepointMechanism.hpp"
  45 #include "runtime/sharedRuntime.hpp"
  46 #include "runtime/stubRoutines.hpp"
  47 #include "utilities/powerOfTwo.hpp"
  48 #include "vmreg_x86.inline.hpp"
  49 
  50 
  51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  52 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  53 // fast versions of NegF/NegD and AbsF/AbsD.
  54 
  55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  56 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  57   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  58   // of 128-bits operands for SSE instructions.
  59   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  60   // Store the value to a 128-bits operand.
  61   operand[0] = lo;
  62   operand[1] = hi;
  63   return operand;
  64 }
  65 
  66 // Buffer for 128-bits masks used by SSE instructions.
  67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  68 
  69 // Static initialization during VM startup.
  70 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  71 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  72 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  73 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  74 
  75 
  76 NEEDS_CLEANUP // remove this definitions ?
  77 const Register IC_Klass    = rax;   // where the IC klass is cached
  78 const Register SYNC_header = rax;   // synchronization header
  79 const Register SHIFT_count = rcx;   // where count for shift operations must be
  80 
  81 #define __ _masm->
  82 
  83 
  84 static void select_different_registers(Register preserve,
  85                                        Register extra,
  86                                        Register &tmp1,
  87                                        Register &tmp2) {
  88   if (tmp1 == preserve) {
  89     assert_different_registers(tmp1, tmp2, extra);
  90     tmp1 = extra;
  91   } else if (tmp2 == preserve) {
  92     assert_different_registers(tmp1, tmp2, extra);
  93     tmp2 = extra;
  94   }
  95   assert_different_registers(preserve, tmp1, tmp2);
  96 }
  97 
  98 
  99 
 100 static void select_different_registers(Register preserve,
 101                                        Register extra,
 102                                        Register &tmp1,
 103                                        Register &tmp2,
 104                                        Register &tmp3) {
 105   if (tmp1 == preserve) {
 106     assert_different_registers(tmp1, tmp2, tmp3, extra);
 107     tmp1 = extra;
 108   } else if (tmp2 == preserve) {
 109     assert_different_registers(tmp1, tmp2, tmp3, extra);
 110     tmp2 = extra;
 111   } else if (tmp3 == preserve) {
 112     assert_different_registers(tmp1, tmp2, tmp3, extra);
 113     tmp3 = extra;
 114   }
 115   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 116 }
 117 
 118 
 119 
 120 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 121   if (opr->is_constant()) {
 122     LIR_Const* constant = opr->as_constant_ptr();
 123     switch (constant->type()) {
 124       case T_INT: {
 125         return true;
 126       }
 127 
 128       default:
 129         return false;
 130     }
 131   }
 132   return false;
 133 }
 134 
 135 
 136 LIR_Opr LIR_Assembler::receiverOpr() {
 137   return FrameMap::receiver_opr;
 138 }
 139 
 140 LIR_Opr LIR_Assembler::osrBufferPointer() {
 141   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 142 }
 143 
 144 //--------------fpu register translations-----------------------
 145 
 146 
 147 address LIR_Assembler::float_constant(float f) {
 148   address const_addr = __ float_constant(f);
 149   if (const_addr == NULL) {
 150     bailout("const section overflow");
 151     return __ code()->consts()->start();
 152   } else {
 153     return const_addr;
 154   }
 155 }
 156 
 157 
 158 address LIR_Assembler::double_constant(double d) {
 159   address const_addr = __ double_constant(d);
 160   if (const_addr == NULL) {
 161     bailout("const section overflow");
 162     return __ code()->consts()->start();
 163   } else {
 164     return const_addr;
 165   }
 166 }
 167 
 168 #ifndef _LP64
 169 void LIR_Assembler::fpop() {
 170   __ fpop();
 171 }
 172 
 173 void LIR_Assembler::fxch(int i) {
 174   __ fxch(i);
 175 }
 176 
 177 void LIR_Assembler::fld(int i) {
 178   __ fld_s(i);
 179 }
 180 
 181 void LIR_Assembler::ffree(int i) {
 182   __ ffree(i);
 183 }
 184 #endif // !_LP64
 185 
 186 void LIR_Assembler::breakpoint() {
 187   __ int3();
 188 }
 189 
 190 void LIR_Assembler::push(LIR_Opr opr) {
 191   if (opr->is_single_cpu()) {
 192     __ push_reg(opr->as_register());
 193   } else if (opr->is_double_cpu()) {
 194     NOT_LP64(__ push_reg(opr->as_register_hi()));
 195     __ push_reg(opr->as_register_lo());
 196   } else if (opr->is_stack()) {
 197     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 198   } else if (opr->is_constant()) {
 199     LIR_Const* const_opr = opr->as_constant_ptr();
 200     if (const_opr->type() == T_OBJECT || const_opr->type() == T_PRIMITIVE_OBJECT) {
 201       __ push_oop(const_opr->as_jobject());
 202     } else if (const_opr->type() == T_INT) {
 203       __ push_jint(const_opr->as_jint());
 204     } else {
 205       ShouldNotReachHere();
 206     }
 207 
 208   } else {
 209     ShouldNotReachHere();
 210   }
 211 }
 212 
 213 void LIR_Assembler::pop(LIR_Opr opr) {
 214   if (opr->is_single_cpu()) {
 215     __ pop_reg(opr->as_register());
 216   } else {
 217     ShouldNotReachHere();
 218   }
 219 }
 220 
 221 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 222   return addr->base()->is_illegal() && addr->index()->is_illegal();
 223 }
 224 
 225 //-------------------------------------------
 226 
 227 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 228   return as_Address(addr, rscratch1);
 229 }
 230 
 231 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 232   if (addr->base()->is_illegal()) {
 233     assert(addr->index()->is_illegal(), "must be illegal too");
 234     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 235     if (! __ reachable(laddr)) {
 236       __ movptr(tmp, laddr.addr());
 237       Address res(tmp, 0);
 238       return res;
 239     } else {
 240       return __ as_Address(laddr);
 241     }
 242   }
 243 
 244   Register base = addr->base()->as_pointer_register();
 245 
 246   if (addr->index()->is_illegal()) {
 247     return Address( base, addr->disp());
 248   } else if (addr->index()->is_cpu_register()) {
 249     Register index = addr->index()->as_pointer_register();
 250     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 251   } else if (addr->index()->is_constant()) {
 252     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 253     assert(Assembler::is_simm32(addr_offset), "must be");
 254 
 255     return Address(base, addr_offset);
 256   } else {
 257     Unimplemented();
 258     return Address();
 259   }
 260 }
 261 
 262 
 263 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 264   Address base = as_Address(addr);
 265   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 266 }
 267 
 268 
 269 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 270   return as_Address(addr);
 271 }
 272 
 273 
 274 void LIR_Assembler::osr_entry() {
 275   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 276   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 277   ValueStack* entry_state = osr_entry->state();
 278   int number_of_locks = entry_state->locks_size();
 279 
 280   // we jump here if osr happens with the interpreter
 281   // state set up to continue at the beginning of the
 282   // loop that triggered osr - in particular, we have
 283   // the following registers setup:
 284   //
 285   // rcx: osr buffer
 286   //
 287 
 288   // build frame
 289   ciMethod* m = compilation()->method();
 290   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 291 
 292   // OSR buffer is
 293   //
 294   // locals[nlocals-1..0]
 295   // monitors[0..number_of_locks]
 296   //
 297   // locals is a direct copy of the interpreter frame so in the osr buffer
 298   // so first slot in the local array is the last local from the interpreter
 299   // and last slot is local[0] (receiver) from the interpreter
 300   //
 301   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 302   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 303   // in the interpreter frame (the method lock if a sync method)
 304 
 305   // Initialize monitors in the compiled activation.
 306   //   rcx: pointer to osr buffer
 307   //
 308   // All other registers are dead at this point and the locals will be
 309   // copied into place by code emitted in the IR.
 310 
 311   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 312   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 313     int monitor_offset = BytesPerWord * method()->max_locals() +
 314       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 315     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 316     // the OSR buffer using 2 word entries: first the lock and then
 317     // the oop.
 318     for (int i = 0; i < number_of_locks; i++) {
 319       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 320 #ifdef ASSERT
 321       // verify the interpreter's monitor has a non-null object
 322       {
 323         Label L;
 324         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 325         __ jcc(Assembler::notZero, L);
 326         __ stop("locked object is NULL");
 327         __ bind(L);
 328       }
 329 #endif
 330       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 331       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 332       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 333       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 334     }
 335   }
 336 }
 337 
 338 
 339 // inline cache check; done before the frame is built.
 340 int LIR_Assembler::check_icache() {
 341   Register receiver = FrameMap::receiver_opr->as_register();
 342   Register ic_klass = IC_Klass;
 343   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 344   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 345   if (!do_post_padding) {
 346     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 347     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 348   }
 349   int offset = __ offset();
 350   __ inline_cache_check(receiver, IC_Klass);
 351   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 352   if (do_post_padding) {
 353     // force alignment after the cache check.
 354     // It's been verified to be aligned if !VerifyOops
 355     __ align(CodeEntryAlignment);
 356   }
 357   return offset;
 358 }
 359 
 360 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 361   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 362   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 363 
 364   Label L_skip_barrier;
 365   Register klass = rscratch1;
 366   Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
 367   assert(thread != noreg, "x86_32 not implemented");
 368 
 369   __ mov_metadata(klass, method->holder()->constant_encoding());
 370   __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
 371 
 372   __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 373 
 374   __ bind(L_skip_barrier);
 375 }
 376 
 377 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 378   jobject o = NULL;
 379   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 380   __ movoop(reg, o);
 381   patching_epilog(patch, lir_patch_normal, reg, info);
 382 }
 383 
 384 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 385   Metadata* o = NULL;
 386   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 387   __ mov_metadata(reg, o);
 388   patching_epilog(patch, lir_patch_normal, reg, info);
 389 }
 390 
 391 // This specifies the rsp decrement needed to build the frame
 392 int LIR_Assembler::initial_frame_size_in_bytes() const {
 393   // if rounding, must let FrameMap know!
 394 
 395   // The frame_map records size in slots (32bit word)
 396 
 397   // subtract two words to account for return address and link
 398   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 399 }
 400 
 401 
 402 int LIR_Assembler::emit_exception_handler() {
 403   // if the last instruction is a call (typically to do a throw which
 404   // is coming at the end after block reordering) the return address
 405   // must still point into the code area in order to avoid assertion
 406   // failures when searching for the corresponding bci => add a nop
 407   // (was bug 5/14/1999 - gri)
 408   __ nop();
 409 
 410   // generate code for exception handler
 411   address handler_base = __ start_a_stub(exception_handler_size());
 412   if (handler_base == NULL) {
 413     // not enough space left for the handler
 414     bailout("exception handler overflow");
 415     return -1;
 416   }
 417 
 418   int offset = code_offset();
 419 
 420   // the exception oop and pc are in rax, and rdx
 421   // no other registers need to be preserved, so invalidate them
 422   __ invalidate_registers(false, true, true, false, true, true);
 423 
 424   // check that there is really an exception
 425   __ verify_not_null_oop(rax);
 426 
 427   // search an exception handler (rax: exception oop, rdx: throwing pc)
 428   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 429   __ should_not_reach_here();
 430   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 431   __ end_a_stub();
 432 
 433   return offset;
 434 }
 435 
 436 
 437 // Emit the code to remove the frame from the stack in the exception
 438 // unwind path.
 439 int LIR_Assembler::emit_unwind_handler() {
 440 #ifndef PRODUCT
 441   if (CommentedAssembly) {
 442     _masm->block_comment("Unwind handler");
 443   }
 444 #endif
 445 
 446   int offset = code_offset();
 447 
 448   // Fetch the exception from TLS and clear out exception related thread state
 449   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 450   NOT_LP64(__ get_thread(rsi));
 451   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 452   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 453   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 454 
 455   __ bind(_unwind_handler_entry);
 456   __ verify_not_null_oop(rax);
 457   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 458     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 459   }
 460 
 461   // Preform needed unlocking
 462   MonitorExitStub* stub = NULL;
 463   if (method()->is_synchronized()) {
 464     monitor_address(0, FrameMap::rax_opr);
 465     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 466     if (UseHeavyMonitors) {
 467       __ jmp(*stub->entry());
 468     } else {
 469       __ unlock_object(rdi, rsi, rax, *stub->entry());
 470     }
 471     __ bind(*stub->continuation());
 472   }
 473 
 474   if (compilation()->env()->dtrace_method_probes()) {
 475 #ifdef _LP64
 476     __ mov(rdi, r15_thread);
 477     __ mov_metadata(rsi, method()->constant_encoding());
 478 #else
 479     __ get_thread(rax);
 480     __ movptr(Address(rsp, 0), rax);
 481     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 482 #endif
 483     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 484   }
 485 
 486   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 487     __ mov(rax, rbx);  // Restore the exception
 488   }
 489 
 490   // remove the activation and dispatch to the unwind handler
 491   __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
 492   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 493 
 494   // Emit the slow path assembly
 495   if (stub != NULL) {
 496     stub->emit_code(this);
 497   }
 498 
 499   return offset;
 500 }
 501 
 502 
 503 int LIR_Assembler::emit_deopt_handler() {
 504   // if the last instruction is a call (typically to do a throw which
 505   // is coming at the end after block reordering) the return address
 506   // must still point into the code area in order to avoid assertion
 507   // failures when searching for the corresponding bci => add a nop
 508   // (was bug 5/14/1999 - gri)
 509   __ nop();
 510 
 511   // generate code for exception handler
 512   address handler_base = __ start_a_stub(deopt_handler_size());
 513   if (handler_base == NULL) {
 514     // not enough space left for the handler
 515     bailout("deopt handler overflow");
 516     return -1;
 517   }
 518 
 519   int offset = code_offset();
 520   InternalAddress here(__ pc());
 521 
 522   __ pushptr(here.addr());
 523   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 524   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 525   __ end_a_stub();
 526 
 527   return offset;
 528 }
 529 
 530 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 531   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 532   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 533     assert(result->fpu() == 0, "result must already be on TOS");
 534   }
 535 
 536   ciMethod* method = compilation()->method();
 537   if (InlineTypeReturnedAsFields && method->return_type()->is_inlinetype()) {
 538     ciInlineKlass* vk = method->return_type()->as_inline_klass();
 539     if (vk->can_be_returned_as_fields()) {
 540 #ifndef _LP64
 541       Unimplemented();
 542 #else
 543       address unpack_handler = vk->unpack_handler();
 544       assert(unpack_handler != NULL, "must be");
 545       __ call(RuntimeAddress(unpack_handler));
 546       // At this point, rax points to the value object (for interpreter or C1 caller).
 547       // The fields of the object are copied into registers (for C2 caller).
 548 #endif
 549     }
 550   }
 551 
 552   // Pop the stack before the safepoint code
 553   __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
 554 
 555   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 556     __ reserved_stack_check();
 557   }
 558 
 559   // Note: we do not need to round double result; float result has the right precision
 560   // the poll sets the condition code, but no data registers
 561 
 562 #ifdef _LP64
 563   const Register thread = r15_thread;
 564 #else
 565   const Register thread = rbx;
 566   __ get_thread(thread);
 567 #endif
 568   code_stub->set_safepoint_offset(__ offset());
 569   __ relocate(relocInfo::poll_return_type);
 570   __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
 571   __ ret(0);
 572 }
 573 
 574 
 575 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
 576   return (__ store_inline_type_fields_to_buf(vk, false));
 577 }
 578 
 579 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 580   guarantee(info != NULL, "Shouldn't be NULL");
 581   int offset = __ offset();
 582 #ifdef _LP64
 583   const Register poll_addr = rscratch1;
 584   __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
 585 #else
 586   assert(tmp->is_cpu_register(), "needed");
 587   const Register poll_addr = tmp->as_register();
 588   __ get_thread(poll_addr);
 589   __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
 590 #endif
 591   add_debug_info_for_branch(info);
 592   __ relocate(relocInfo::poll_type);
 593   address pre_pc = __ pc();
 594   __ testl(rax, Address(poll_addr, 0));
 595   address post_pc = __ pc();
 596   guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 597   return offset;
 598 }
 599 
 600 
 601 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 602   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 603 }
 604 
 605 void LIR_Assembler::swap_reg(Register a, Register b) {
 606   __ xchgptr(a, b);
 607 }
 608 
 609 
 610 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 611   assert(src->is_constant(), "should not call otherwise");
 612   assert(dest->is_register(), "should not call otherwise");
 613   LIR_Const* c = src->as_constant_ptr();
 614 
 615   switch (c->type()) {
 616     case T_INT: {
 617       assert(patch_code == lir_patch_none, "no patching handled here");
 618       __ movl(dest->as_register(), c->as_jint());
 619       break;
 620     }
 621 
 622     case T_ADDRESS: {
 623       assert(patch_code == lir_patch_none, "no patching handled here");
 624       __ movptr(dest->as_register(), c->as_jint());
 625       break;
 626     }
 627 
 628     case T_LONG: {
 629       assert(patch_code == lir_patch_none, "no patching handled here");
 630 #ifdef _LP64
 631       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 632 #else
 633       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 634       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 635 #endif // _LP64
 636       break;
 637     }
 638 
 639     case T_PRIMITIVE_OBJECT: // Fall through
 640     case T_OBJECT: {
 641       if (patch_code != lir_patch_none) {
 642         jobject2reg_with_patching(dest->as_register(), info);
 643       } else {
 644         __ movoop(dest->as_register(), c->as_jobject());
 645       }
 646       break;
 647     }
 648 
 649     case T_METADATA: {
 650       if (patch_code != lir_patch_none) {
 651         klass2reg_with_patching(dest->as_register(), info);
 652       } else {
 653         __ mov_metadata(dest->as_register(), c->as_metadata());
 654       }
 655       break;
 656     }
 657 
 658     case T_FLOAT: {
 659       if (dest->is_single_xmm()) {
 660         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
 661           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 662         } else {
 663           __ movflt(dest->as_xmm_float_reg(),
 664                    InternalAddress(float_constant(c->as_jfloat())));
 665         }
 666       } else {
 667 #ifndef _LP64
 668         assert(dest->is_single_fpu(), "must be");
 669         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 670         if (c->is_zero_float()) {
 671           __ fldz();
 672         } else if (c->is_one_float()) {
 673           __ fld1();
 674         } else {
 675           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 676         }
 677 #else
 678         ShouldNotReachHere();
 679 #endif // !_LP64
 680       }
 681       break;
 682     }
 683 
 684     case T_DOUBLE: {
 685       if (dest->is_double_xmm()) {
 686         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
 687           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 688         } else {
 689           __ movdbl(dest->as_xmm_double_reg(),
 690                     InternalAddress(double_constant(c->as_jdouble())));
 691         }
 692       } else {
 693 #ifndef _LP64
 694         assert(dest->is_double_fpu(), "must be");
 695         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 696         if (c->is_zero_double()) {
 697           __ fldz();
 698         } else if (c->is_one_double()) {
 699           __ fld1();
 700         } else {
 701           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 702         }
 703 #else
 704         ShouldNotReachHere();
 705 #endif // !_LP64
 706       }
 707       break;
 708     }
 709 
 710     default:
 711       ShouldNotReachHere();
 712   }
 713 }
 714 
 715 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 716   assert(src->is_constant(), "should not call otherwise");
 717   assert(dest->is_stack(), "should not call otherwise");
 718   LIR_Const* c = src->as_constant_ptr();
 719 
 720   switch (c->type()) {
 721     case T_INT:  // fall through
 722     case T_FLOAT:
 723       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 724       break;
 725 
 726     case T_ADDRESS:
 727       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 728       break;
 729 
 730     case T_PRIMITIVE_OBJECT: // Fall through
 731     case T_OBJECT:
 732       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 733       break;
 734 
 735     case T_LONG:  // fall through
 736     case T_DOUBLE:
 737 #ifdef _LP64
 738       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 739                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 740 #else
 741       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 742                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 743       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 744                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 745 #endif // _LP64
 746       break;
 747 
 748     default:
 749       ShouldNotReachHere();
 750   }
 751 }
 752 
 753 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 754   assert(src->is_constant(), "should not call otherwise");
 755   assert(dest->is_address(), "should not call otherwise");
 756   LIR_Const* c = src->as_constant_ptr();
 757   LIR_Address* addr = dest->as_address_ptr();
 758 
 759   int null_check_here = code_offset();
 760   switch (type) {
 761     case T_INT:    // fall through
 762     case T_FLOAT:
 763       __ movl(as_Address(addr), c->as_jint_bits());
 764       break;
 765 
 766     case T_ADDRESS:
 767       __ movptr(as_Address(addr), c->as_jint_bits());
 768       break;
 769 
 770     case T_PRIMITIVE_OBJECT: // fall through
 771     case T_OBJECT:  // fall through
 772     case T_ARRAY:
 773       if (c->as_jobject() == NULL) {
 774         if (UseCompressedOops && !wide) {
 775           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 776         } else {
 777 #ifdef _LP64
 778           __ xorptr(rscratch1, rscratch1);
 779           null_check_here = code_offset();
 780           __ movptr(as_Address(addr), rscratch1);
 781 #else
 782           __ movptr(as_Address(addr), NULL_WORD);
 783 #endif
 784         }
 785       } else {
 786         if (is_literal_address(addr)) {
 787           ShouldNotReachHere();
 788           __ movoop(as_Address(addr, noreg), c->as_jobject());
 789         } else {
 790 #ifdef _LP64
 791           __ movoop(rscratch1, c->as_jobject());
 792           if (UseCompressedOops && !wide) {
 793             __ encode_heap_oop(rscratch1);
 794             null_check_here = code_offset();
 795             __ movl(as_Address_lo(addr), rscratch1);
 796           } else {
 797             null_check_here = code_offset();
 798             __ movptr(as_Address_lo(addr), rscratch1);
 799           }
 800 #else
 801           __ movoop(as_Address(addr), c->as_jobject());
 802 #endif
 803         }
 804       }
 805       break;
 806 
 807     case T_LONG:    // fall through
 808     case T_DOUBLE:
 809 #ifdef _LP64
 810       if (is_literal_address(addr)) {
 811         ShouldNotReachHere();
 812         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 813       } else {
 814         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 815         null_check_here = code_offset();
 816         __ movptr(as_Address_lo(addr), r10);
 817       }
 818 #else
 819       // Always reachable in 32bit so this doesn't produce useless move literal
 820       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 821       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 822 #endif // _LP64
 823       break;
 824 
 825     case T_BOOLEAN: // fall through
 826     case T_BYTE:
 827       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 828       break;
 829 
 830     case T_CHAR:    // fall through
 831     case T_SHORT:
 832       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 833       break;
 834 
 835     default:
 836       ShouldNotReachHere();
 837   };
 838 
 839   if (info != NULL) {
 840     add_debug_info_for_null_check(null_check_here, info);
 841   }
 842 }
 843 
 844 
 845 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 846   assert(src->is_register(), "should not call otherwise");
 847   assert(dest->is_register(), "should not call otherwise");
 848 
 849   // move between cpu-registers
 850   if (dest->is_single_cpu()) {
 851 #ifdef _LP64
 852     if (src->type() == T_LONG) {
 853       // Can do LONG -> OBJECT
 854       move_regs(src->as_register_lo(), dest->as_register());
 855       return;
 856     }
 857 #endif
 858     assert(src->is_single_cpu(), "must match");
 859     if (src->type() == T_OBJECT || src->type() == T_PRIMITIVE_OBJECT) {
 860       __ verify_oop(src->as_register());
 861     }
 862     move_regs(src->as_register(), dest->as_register());
 863 
 864   } else if (dest->is_double_cpu()) {
 865 #ifdef _LP64
 866     if (is_reference_type(src->type())) {
 867       // Surprising to me but we can see move of a long to t_object
 868       __ verify_oop(src->as_register());
 869       move_regs(src->as_register(), dest->as_register_lo());
 870       return;
 871     }
 872 #endif
 873     assert(src->is_double_cpu(), "must match");
 874     Register f_lo = src->as_register_lo();
 875     Register f_hi = src->as_register_hi();
 876     Register t_lo = dest->as_register_lo();
 877     Register t_hi = dest->as_register_hi();
 878 #ifdef _LP64
 879     assert(f_hi == f_lo, "must be same");
 880     assert(t_hi == t_lo, "must be same");
 881     move_regs(f_lo, t_lo);
 882 #else
 883     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 884 
 885 
 886     if (f_lo == t_hi && f_hi == t_lo) {
 887       swap_reg(f_lo, f_hi);
 888     } else if (f_hi == t_lo) {
 889       assert(f_lo != t_hi, "overwriting register");
 890       move_regs(f_hi, t_hi);
 891       move_regs(f_lo, t_lo);
 892     } else {
 893       assert(f_hi != t_lo, "overwriting register");
 894       move_regs(f_lo, t_lo);
 895       move_regs(f_hi, t_hi);
 896     }
 897 #endif // LP64
 898 
 899 #ifndef _LP64
 900     // special moves from fpu-register to xmm-register
 901     // necessary for method results
 902   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 903     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 904     __ fld_s(Address(rsp, 0));
 905   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 906     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 907     __ fld_d(Address(rsp, 0));
 908   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 909     __ fstp_s(Address(rsp, 0));
 910     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 911   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 912     __ fstp_d(Address(rsp, 0));
 913     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 914 #endif // !_LP64
 915 
 916     // move between xmm-registers
 917   } else if (dest->is_single_xmm()) {
 918     assert(src->is_single_xmm(), "must match");
 919     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 920   } else if (dest->is_double_xmm()) {
 921     assert(src->is_double_xmm(), "must match");
 922     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 923 
 924 #ifndef _LP64
 925     // move between fpu-registers (no instruction necessary because of fpu-stack)
 926   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 927     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 928     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 929 #endif // !_LP64
 930 
 931   } else {
 932     ShouldNotReachHere();
 933   }
 934 }
 935 
 936 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 937   assert(src->is_register(), "should not call otherwise");
 938   assert(dest->is_stack(), "should not call otherwise");
 939 
 940   if (src->is_single_cpu()) {
 941     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 942     if (is_reference_type(type)) {
 943       __ verify_oop(src->as_register());
 944       __ movptr (dst, src->as_register());
 945     } else if (type == T_METADATA || type == T_ADDRESS) {
 946       __ movptr (dst, src->as_register());
 947     } else {
 948       __ movl (dst, src->as_register());
 949     }
 950 
 951   } else if (src->is_double_cpu()) {
 952     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 953     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 954     __ movptr (dstLO, src->as_register_lo());
 955     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 956 
 957   } else if (src->is_single_xmm()) {
 958     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 959     __ movflt(dst_addr, src->as_xmm_float_reg());
 960 
 961   } else if (src->is_double_xmm()) {
 962     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 963     __ movdbl(dst_addr, src->as_xmm_double_reg());
 964 
 965 #ifndef _LP64
 966   } else if (src->is_single_fpu()) {
 967     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 968     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 969     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 970     else                   __ fst_s  (dst_addr);
 971 
 972   } else if (src->is_double_fpu()) {
 973     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 974     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 975     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 976     else                   __ fst_d  (dst_addr);
 977 #endif // !_LP64
 978 
 979   } else {
 980     ShouldNotReachHere();
 981   }
 982 }
 983 
 984 
 985 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 986   LIR_Address* to_addr = dest->as_address_ptr();
 987   PatchingStub* patch = NULL;
 988   Register compressed_src = rscratch1;
 989 
 990   if (is_reference_type(type)) {
 991     __ verify_oop(src->as_register());
 992 #ifdef _LP64
 993     if (UseCompressedOops && !wide) {
 994       __ movptr(compressed_src, src->as_register());
 995       __ encode_heap_oop(compressed_src);
 996       if (patch_code != lir_patch_none) {
 997         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 998       }
 999     }
1000 #endif
1001   }
1002 
1003   if (patch_code != lir_patch_none) {
1004     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1005     Address toa = as_Address(to_addr);
1006     assert(toa.disp() != 0, "must have");
1007   }
1008 
1009   int null_check_here = code_offset();
1010   switch (type) {
1011     case T_FLOAT: {
1012 #ifdef _LP64
1013       assert(src->is_single_xmm(), "not a float");
1014       __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1015 #else
1016       if (src->is_single_xmm()) {
1017         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1018       } else {
1019         assert(src->is_single_fpu(), "must be");
1020         assert(src->fpu_regnr() == 0, "argument must be on TOS");
1021         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
1022         else                    __ fst_s (as_Address(to_addr));
1023       }
1024 #endif // _LP64
1025       break;
1026     }
1027 
1028     case T_DOUBLE: {
1029 #ifdef _LP64
1030       assert(src->is_double_xmm(), "not a double");
1031       __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1032 #else
1033       if (src->is_double_xmm()) {
1034         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1035       } else {
1036         assert(src->is_double_fpu(), "must be");
1037         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1038         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1039         else                    __ fst_d (as_Address(to_addr));
1040       }
1041 #endif // _LP64
1042       break;
1043     }
1044 
1045     case T_PRIMITIVE_OBJECT: // fall through
1046     case T_ARRAY:   // fall through
1047     case T_OBJECT:  // fall through
1048       if (UseCompressedOops && !wide) {
1049         __ movl(as_Address(to_addr), compressed_src);
1050       } else {
1051         __ movptr(as_Address(to_addr), src->as_register());
1052       }
1053       break;
1054     case T_METADATA:
1055       // We get here to store a method pointer to the stack to pass to
1056       // a dtrace runtime call. This can't work on 64 bit with
1057       // compressed klass ptrs: T_METADATA can be a compressed klass
1058       // ptr or a 64 bit method pointer.
1059       LP64_ONLY(ShouldNotReachHere());
1060       __ movptr(as_Address(to_addr), src->as_register());
1061       break;
1062     case T_ADDRESS:
1063       __ movptr(as_Address(to_addr), src->as_register());
1064       break;
1065     case T_INT:
1066       __ movl(as_Address(to_addr), src->as_register());
1067       break;
1068 
1069     case T_LONG: {
1070       Register from_lo = src->as_register_lo();
1071       Register from_hi = src->as_register_hi();
1072 #ifdef _LP64
1073       __ movptr(as_Address_lo(to_addr), from_lo);
1074 #else
1075       Register base = to_addr->base()->as_register();
1076       Register index = noreg;
1077       if (to_addr->index()->is_register()) {
1078         index = to_addr->index()->as_register();
1079       }
1080       if (base == from_lo || index == from_lo) {
1081         assert(base != from_hi, "can't be");
1082         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1083         __ movl(as_Address_hi(to_addr), from_hi);
1084         if (patch != NULL) {
1085           patching_epilog(patch, lir_patch_high, base, info);
1086           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1087           patch_code = lir_patch_low;
1088         }
1089         __ movl(as_Address_lo(to_addr), from_lo);
1090       } else {
1091         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1092         __ movl(as_Address_lo(to_addr), from_lo);
1093         if (patch != NULL) {
1094           patching_epilog(patch, lir_patch_low, base, info);
1095           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1096           patch_code = lir_patch_high;
1097         }
1098         __ movl(as_Address_hi(to_addr), from_hi);
1099       }
1100 #endif // _LP64
1101       break;
1102     }
1103 
1104     case T_BYTE:    // fall through
1105     case T_BOOLEAN: {
1106       Register src_reg = src->as_register();
1107       Address dst_addr = as_Address(to_addr);
1108       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1109       __ movb(dst_addr, src_reg);
1110       break;
1111     }
1112 
1113     case T_CHAR:    // fall through
1114     case T_SHORT:
1115       __ movw(as_Address(to_addr), src->as_register());
1116       break;
1117 
1118     default:
1119       ShouldNotReachHere();
1120   }
1121   if (info != NULL) {
1122     add_debug_info_for_null_check(null_check_here, info);
1123   }
1124 
1125   if (patch_code != lir_patch_none) {
1126     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1127   }
1128 }
1129 
1130 
1131 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1132   assert(src->is_stack(), "should not call otherwise");
1133   assert(dest->is_register(), "should not call otherwise");
1134 
1135   if (dest->is_single_cpu()) {
1136     if (is_reference_type(type)) {
1137       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1138       __ verify_oop(dest->as_register());
1139     } else if (type == T_METADATA || type == T_ADDRESS) {
1140       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1141     } else {
1142       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1143     }
1144 
1145   } else if (dest->is_double_cpu()) {
1146     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1147     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1148     __ movptr(dest->as_register_lo(), src_addr_LO);
1149     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1150 
1151   } else if (dest->is_single_xmm()) {
1152     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1153     __ movflt(dest->as_xmm_float_reg(), src_addr);
1154 
1155   } else if (dest->is_double_xmm()) {
1156     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1157     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1158 
1159 #ifndef _LP64
1160   } else if (dest->is_single_fpu()) {
1161     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1162     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1163     __ fld_s(src_addr);
1164 
1165   } else if (dest->is_double_fpu()) {
1166     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1167     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1168     __ fld_d(src_addr);
1169 #endif // _LP64
1170 
1171   } else {
1172     ShouldNotReachHere();
1173   }
1174 }
1175 
1176 
1177 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1178   if (src->is_single_stack()) {
1179     if (is_reference_type(type)) {
1180       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1181       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1182     } else {
1183 #ifndef _LP64
1184       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1185       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1186 #else
1187       //no pushl on 64bits
1188       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1189       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1190 #endif
1191     }
1192 
1193   } else if (src->is_double_stack()) {
1194 #ifdef _LP64
1195     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1196     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1197 #else
1198     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1199     // push and pop the part at src + wordSize, adding wordSize for the previous push
1200     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1201     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1202     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1203 #endif // _LP64
1204 
1205   } else {
1206     ShouldNotReachHere();
1207   }
1208 }
1209 
1210 
1211 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1212   assert(src->is_address(), "should not call otherwise");
1213   assert(dest->is_register(), "should not call otherwise");
1214 
1215   LIR_Address* addr = src->as_address_ptr();
1216   Address from_addr = as_Address(addr);
1217 
1218   if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_PRIMITIVE_OBJECT) {
1219     __ verify_oop(addr->base()->as_pointer_register());
1220   }
1221 
1222   switch (type) {
1223     case T_BOOLEAN: // fall through
1224     case T_BYTE:    // fall through
1225     case T_CHAR:    // fall through
1226     case T_SHORT:
1227       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1228         // on pre P6 processors we may get partial register stalls
1229         // so blow away the value of to_rinfo before loading a
1230         // partial word into it.  Do it here so that it precedes
1231         // the potential patch point below.
1232         __ xorptr(dest->as_register(), dest->as_register());
1233       }
1234       break;
1235    default:
1236      break;
1237   }
1238 
1239   PatchingStub* patch = NULL;
1240   if (patch_code != lir_patch_none) {
1241     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1242     assert(from_addr.disp() != 0, "must have");
1243   }
1244   if (info != NULL) {
1245     add_debug_info_for_null_check_here(info);
1246   }
1247 
1248   switch (type) {
1249     case T_FLOAT: {
1250       if (dest->is_single_xmm()) {
1251         __ movflt(dest->as_xmm_float_reg(), from_addr);
1252       } else {
1253 #ifndef _LP64
1254         assert(dest->is_single_fpu(), "must be");
1255         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1256         __ fld_s(from_addr);
1257 #else
1258         ShouldNotReachHere();
1259 #endif // !LP64
1260       }
1261       break;
1262     }
1263 
1264     case T_DOUBLE: {
1265       if (dest->is_double_xmm()) {
1266         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1267       } else {
1268 #ifndef _LP64
1269         assert(dest->is_double_fpu(), "must be");
1270         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1271         __ fld_d(from_addr);
1272 #else
1273         ShouldNotReachHere();
1274 #endif // !LP64
1275       }
1276       break;
1277     }
1278 
1279     case T_PRIMITIVE_OBJECT: // fall through
1280     case T_OBJECT:  // fall through
1281     case T_ARRAY:   // fall through
1282       if (UseCompressedOops && !wide) {
1283         __ movl(dest->as_register(), from_addr);
1284       } else {
1285         __ movptr(dest->as_register(), from_addr);
1286       }
1287       break;
1288 
1289     case T_ADDRESS:
1290       __ movptr(dest->as_register(), from_addr);
1291       break;
1292     case T_INT:
1293       __ movl(dest->as_register(), from_addr);
1294       break;
1295 
1296     case T_LONG: {
1297       Register to_lo = dest->as_register_lo();
1298       Register to_hi = dest->as_register_hi();
1299 #ifdef _LP64
1300       __ movptr(to_lo, as_Address_lo(addr));
1301 #else
1302       Register base = addr->base()->as_register();
1303       Register index = noreg;
1304       if (addr->index()->is_register()) {
1305         index = addr->index()->as_register();
1306       }
1307       if ((base == to_lo && index == to_hi) ||
1308           (base == to_hi && index == to_lo)) {
1309         // addresses with 2 registers are only formed as a result of
1310         // array access so this code will never have to deal with
1311         // patches or null checks.
1312         assert(info == NULL && patch == NULL, "must be");
1313         __ lea(to_hi, as_Address(addr));
1314         __ movl(to_lo, Address(to_hi, 0));
1315         __ movl(to_hi, Address(to_hi, BytesPerWord));
1316       } else if (base == to_lo || index == to_lo) {
1317         assert(base != to_hi, "can't be");
1318         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1319         __ movl(to_hi, as_Address_hi(addr));
1320         if (patch != NULL) {
1321           patching_epilog(patch, lir_patch_high, base, info);
1322           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1323           patch_code = lir_patch_low;
1324         }
1325         __ movl(to_lo, as_Address_lo(addr));
1326       } else {
1327         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1328         __ movl(to_lo, as_Address_lo(addr));
1329         if (patch != NULL) {
1330           patching_epilog(patch, lir_patch_low, base, info);
1331           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1332           patch_code = lir_patch_high;
1333         }
1334         __ movl(to_hi, as_Address_hi(addr));
1335       }
1336 #endif // _LP64
1337       break;
1338     }
1339 
1340     case T_BOOLEAN: // fall through
1341     case T_BYTE: {
1342       Register dest_reg = dest->as_register();
1343       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1344       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1345         __ movsbl(dest_reg, from_addr);
1346       } else {
1347         __ movb(dest_reg, from_addr);
1348         __ shll(dest_reg, 24);
1349         __ sarl(dest_reg, 24);
1350       }
1351       break;
1352     }
1353 
1354     case T_CHAR: {
1355       Register dest_reg = dest->as_register();
1356       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1357       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1358         __ movzwl(dest_reg, from_addr);
1359       } else {
1360         __ movw(dest_reg, from_addr);
1361       }
1362       break;
1363     }
1364 
1365     case T_SHORT: {
1366       Register dest_reg = dest->as_register();
1367       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1368         __ movswl(dest_reg, from_addr);
1369       } else {
1370         __ movw(dest_reg, from_addr);
1371         __ shll(dest_reg, 16);
1372         __ sarl(dest_reg, 16);
1373       }
1374       break;
1375     }
1376 
1377     default:
1378       ShouldNotReachHere();
1379   }
1380 
1381   if (patch != NULL) {
1382     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1383   }
1384 
1385   if (is_reference_type(type)) {
1386 #ifdef _LP64
1387     if (UseCompressedOops && !wide) {
1388       __ decode_heap_oop(dest->as_register());
1389     }
1390 #endif
1391 
1392     // Load barrier has not yet been applied, so ZGC can't verify the oop here
1393     if (!UseZGC) {
1394       __ verify_oop(dest->as_register());
1395     }
1396   }
1397 }
1398 
1399 
1400 NEEDS_CLEANUP; // This could be static?
1401 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1402   int elem_size = type2aelembytes(type);
1403   switch (elem_size) {
1404     case 1: return Address::times_1;
1405     case 2: return Address::times_2;
1406     case 4: return Address::times_4;
1407     case 8: return Address::times_8;
1408   }
1409   ShouldNotReachHere();
1410   return Address::no_scale;
1411 }
1412 
1413 
1414 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1415   switch (op->code()) {
1416     case lir_idiv:
1417     case lir_irem:
1418       arithmetic_idiv(op->code(),
1419                       op->in_opr1(),
1420                       op->in_opr2(),
1421                       op->in_opr3(),
1422                       op->result_opr(),
1423                       op->info());
1424       break;
1425     case lir_fmad:
1426       __ fmad(op->result_opr()->as_xmm_double_reg(),
1427               op->in_opr1()->as_xmm_double_reg(),
1428               op->in_opr2()->as_xmm_double_reg(),
1429               op->in_opr3()->as_xmm_double_reg());
1430       break;
1431     case lir_fmaf:
1432       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1433               op->in_opr1()->as_xmm_float_reg(),
1434               op->in_opr2()->as_xmm_float_reg(),
1435               op->in_opr3()->as_xmm_float_reg());
1436       break;
1437     default:      ShouldNotReachHere(); break;
1438   }
1439 }
1440 
1441 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1442 #ifdef ASSERT
1443   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1444   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1445   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1446 #endif
1447 
1448   if (op->cond() == lir_cond_always) {
1449     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1450     __ jmp (*(op->label()));
1451   } else {
1452     Assembler::Condition acond = Assembler::zero;
1453     if (op->code() == lir_cond_float_branch) {
1454       assert(op->ublock() != NULL, "must have unordered successor");
1455       __ jcc(Assembler::parity, *(op->ublock()->label()));
1456       switch(op->cond()) {
1457         case lir_cond_equal:        acond = Assembler::equal;      break;
1458         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1459         case lir_cond_less:         acond = Assembler::below;      break;
1460         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1461         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1462         case lir_cond_greater:      acond = Assembler::above;      break;
1463         default:                         ShouldNotReachHere();
1464       }
1465     } else {
1466       switch (op->cond()) {
1467         case lir_cond_equal:        acond = Assembler::equal;       break;
1468         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1469         case lir_cond_less:         acond = Assembler::less;        break;
1470         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1471         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1472         case lir_cond_greater:      acond = Assembler::greater;     break;
1473         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1474         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1475         default:                         ShouldNotReachHere();
1476       }
1477     }
1478     __ jcc(acond,*(op->label()));
1479   }
1480 }
1481 
1482 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1483   LIR_Opr src  = op->in_opr();
1484   LIR_Opr dest = op->result_opr();
1485 
1486   switch (op->bytecode()) {
1487     case Bytecodes::_i2l:
1488 #ifdef _LP64
1489       __ movl2ptr(dest->as_register_lo(), src->as_register());
1490 #else
1491       move_regs(src->as_register(), dest->as_register_lo());
1492       move_regs(src->as_register(), dest->as_register_hi());
1493       __ sarl(dest->as_register_hi(), 31);
1494 #endif // LP64
1495       break;
1496 
1497     case Bytecodes::_l2i:
1498 #ifdef _LP64
1499       __ movl(dest->as_register(), src->as_register_lo());
1500 #else
1501       move_regs(src->as_register_lo(), dest->as_register());
1502 #endif
1503       break;
1504 
1505     case Bytecodes::_i2b:
1506       move_regs(src->as_register(), dest->as_register());
1507       __ sign_extend_byte(dest->as_register());
1508       break;
1509 
1510     case Bytecodes::_i2c:
1511       move_regs(src->as_register(), dest->as_register());
1512       __ andl(dest->as_register(), 0xFFFF);
1513       break;
1514 
1515     case Bytecodes::_i2s:
1516       move_regs(src->as_register(), dest->as_register());
1517       __ sign_extend_short(dest->as_register());
1518       break;
1519 
1520 
1521 #ifdef _LP64
1522     case Bytecodes::_f2d:
1523       __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1524       break;
1525 
1526     case Bytecodes::_d2f:
1527       __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1528       break;
1529 
1530     case Bytecodes::_i2f:
1531       __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1532       break;
1533 
1534     case Bytecodes::_i2d:
1535       __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1536       break;
1537 
1538     case Bytecodes::_l2f:
1539       __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1540       break;
1541 
1542     case Bytecodes::_l2d:
1543       __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1544       break;
1545 
1546     case Bytecodes::_f2i:
1547       __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1548       break;
1549 
1550     case Bytecodes::_d2i:
1551       __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1552       break;
1553 
1554     case Bytecodes::_f2l:
1555       __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1556       break;
1557 
1558     case Bytecodes::_d2l:
1559       __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1560       break;
1561 #else
1562     case Bytecodes::_f2d:
1563     case Bytecodes::_d2f:
1564       if (dest->is_single_xmm()) {
1565         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1566       } else if (dest->is_double_xmm()) {
1567         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1568       } else {
1569         assert(src->fpu() == dest->fpu(), "register must be equal");
1570         // do nothing (float result is rounded later through spilling)
1571       }
1572       break;
1573 
1574     case Bytecodes::_i2f:
1575     case Bytecodes::_i2d:
1576       if (dest->is_single_xmm()) {
1577         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1578       } else if (dest->is_double_xmm()) {
1579         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1580       } else {
1581         assert(dest->fpu() == 0, "result must be on TOS");
1582         __ movl(Address(rsp, 0), src->as_register());
1583         __ fild_s(Address(rsp, 0));
1584       }
1585       break;
1586 
1587     case Bytecodes::_l2f:
1588     case Bytecodes::_l2d:
1589       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1590       assert(dest->fpu() == 0, "result must be on TOS");
1591       __ movptr(Address(rsp, 0),          src->as_register_lo());
1592       __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1593       __ fild_d(Address(rsp, 0));
1594       // float result is rounded later through spilling
1595       break;
1596 
1597     case Bytecodes::_f2i:
1598     case Bytecodes::_d2i:
1599       if (src->is_single_xmm()) {
1600         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1601       } else if (src->is_double_xmm()) {
1602         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1603       } else {
1604         assert(src->fpu() == 0, "input must be on TOS");
1605         __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1606         __ fist_s(Address(rsp, 0));
1607         __ movl(dest->as_register(), Address(rsp, 0));
1608         __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1609       }
1610       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1611       assert(op->stub() != NULL, "stub required");
1612       __ cmpl(dest->as_register(), 0x80000000);
1613       __ jcc(Assembler::equal, *op->stub()->entry());
1614       __ bind(*op->stub()->continuation());
1615       break;
1616 
1617     case Bytecodes::_f2l:
1618     case Bytecodes::_d2l:
1619       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1620       assert(src->fpu() == 0, "input must be on TOS");
1621       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1622 
1623       // instruction sequence too long to inline it here
1624       {
1625         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1626       }
1627       break;
1628 #endif // _LP64
1629 
1630     default: ShouldNotReachHere();
1631   }
1632 }
1633 
1634 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1635   if (op->init_check()) {
1636     add_debug_info_for_null_check_here(op->stub()->info());
1637     __ cmpb(Address(op->klass()->as_register(),
1638                     InstanceKlass::init_state_offset()),
1639                     InstanceKlass::fully_initialized);
1640     __ jcc(Assembler::notEqual, *op->stub()->entry());
1641   }
1642   __ allocate_object(op->obj()->as_register(),
1643                      op->tmp1()->as_register(),
1644                      op->tmp2()->as_register(),
1645                      op->header_size(),
1646                      op->object_size(),
1647                      op->klass()->as_register(),
1648                      *op->stub()->entry());
1649   __ bind(*op->stub()->continuation());
1650 }
1651 
1652 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1653   Register len =  op->len()->as_register();
1654   LP64_ONLY( __ movslq(len, len); )
1655 
1656   if (UseSlowPath || op->type() == T_PRIMITIVE_OBJECT ||
1657       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1658       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1659     __ jmp(*op->stub()->entry());
1660   } else {
1661     Register tmp1 = op->tmp1()->as_register();
1662     Register tmp2 = op->tmp2()->as_register();
1663     Register tmp3 = op->tmp3()->as_register();
1664     if (len == tmp1) {
1665       tmp1 = tmp3;
1666     } else if (len == tmp2) {
1667       tmp2 = tmp3;
1668     } else if (len == tmp3) {
1669       // everything is ok
1670     } else {
1671       __ mov(tmp3, len);
1672     }
1673     __ allocate_array(op->obj()->as_register(),
1674                       len,
1675                       tmp1,
1676                       tmp2,
1677                       arrayOopDesc::header_size(op->type()),
1678                       array_element_size(op->type()),
1679                       op->klass()->as_register(),
1680                       *op->stub()->entry());
1681   }
1682   __ bind(*op->stub()->continuation());
1683 }
1684 
1685 void LIR_Assembler::type_profile_helper(Register mdo,
1686                                         ciMethodData *md, ciProfileData *data,
1687                                         Register recv, Label* update_done) {
1688   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1689     Label next_test;
1690     // See if the receiver is receiver[n].
1691     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1692     __ jccb(Assembler::notEqual, next_test);
1693     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1694     __ addptr(data_addr, DataLayout::counter_increment);
1695     __ jmp(*update_done);
1696     __ bind(next_test);
1697   }
1698 
1699   // Didn't find receiver; find next empty slot and fill it in
1700   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1701     Label next_test;
1702     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1703     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1704     __ jccb(Assembler::notEqual, next_test);
1705     __ movptr(recv_addr, recv);
1706     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1707     __ jmp(*update_done);
1708     __ bind(next_test);
1709   }
1710 }
1711 
1712 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1713   // we always need a stub for the failure case.
1714   CodeStub* stub = op->stub();
1715   Register obj = op->object()->as_register();
1716   Register k_RInfo = op->tmp1()->as_register();
1717   Register klass_RInfo = op->tmp2()->as_register();
1718   Register dst = op->result_opr()->as_register();
1719   ciKlass* k = op->klass();
1720   Register Rtmp1 = noreg;
1721   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1722 
1723   // check if it needs to be profiled
1724   ciMethodData* md = NULL;
1725   ciProfileData* data = NULL;
1726 
1727   if (op->should_profile()) {
1728     ciMethod* method = op->profiled_method();
1729     assert(method != NULL, "Should have method");
1730     int bci = op->profiled_bci();
1731     md = method->method_data_or_null();
1732     assert(md != NULL, "Sanity");
1733     data = md->bci_to_data(bci);
1734     assert(data != NULL,                "need data for type check");
1735     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1736   }
1737   Label profile_cast_success, profile_cast_failure;
1738   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1739   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1740 
1741   if (obj == k_RInfo) {
1742     k_RInfo = dst;
1743   } else if (obj == klass_RInfo) {
1744     klass_RInfo = dst;
1745   }
1746   if (k->is_loaded() && !UseCompressedClassPointers) {
1747     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1748   } else {
1749     Rtmp1 = op->tmp3()->as_register();
1750     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1751   }
1752 
1753   assert_different_registers(obj, k_RInfo, klass_RInfo);
1754 
1755   if (op->need_null_check()) {
1756     __ cmpptr(obj, (int32_t)NULL_WORD);
1757     if (op->should_profile()) {
1758       Label not_null;
1759       __ jccb(Assembler::notEqual, not_null);
1760       // Object is null; update MDO and exit
1761       Register mdo  = klass_RInfo;
1762       __ mov_metadata(mdo, md->constant_encoding());
1763       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1764       int header_bits = BitData::null_seen_byte_constant();
1765       __ orb(data_addr, header_bits);
1766       __ jmp(*obj_is_null);
1767       __ bind(not_null);
1768     } else {
1769       __ jcc(Assembler::equal, *obj_is_null);
1770     }
1771   }
1772 
1773   if (!k->is_loaded()) {
1774     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1775   } else {
1776 #ifdef _LP64
1777     __ mov_metadata(k_RInfo, k->constant_encoding());
1778 #endif // _LP64
1779   }
1780   __ verify_oop(obj);
1781 
1782   if (op->fast_check()) {
1783     // get object class
1784     // not a safepoint as obj null check happens earlier
1785 #ifdef _LP64
1786     if (UseCompressedClassPointers) {
1787       __ load_klass(Rtmp1, obj, tmp_load_klass);
1788       __ cmpptr(k_RInfo, Rtmp1);
1789     } else {
1790       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1791     }
1792 #else
1793     if (k->is_loaded()) {
1794       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1795     } else {
1796       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1797     }
1798 #endif
1799     __ jcc(Assembler::notEqual, *failure_target);
1800     // successful cast, fall through to profile or jump
1801   } else {
1802     // get object class
1803     // not a safepoint as obj null check happens earlier
1804     __ load_klass(klass_RInfo, obj, tmp_load_klass);
1805     if (k->is_loaded()) {
1806       // See if we get an immediate positive hit
1807 #ifdef _LP64
1808       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1809 #else
1810       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1811 #endif // _LP64
1812       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1813         __ jcc(Assembler::notEqual, *failure_target);
1814         // successful cast, fall through to profile or jump
1815       } else {
1816         // See if we get an immediate positive hit
1817         __ jcc(Assembler::equal, *success_target);
1818         // check for self
1819 #ifdef _LP64
1820         __ cmpptr(klass_RInfo, k_RInfo);
1821 #else
1822         __ cmpklass(klass_RInfo, k->constant_encoding());
1823 #endif // _LP64
1824         __ jcc(Assembler::equal, *success_target);
1825 
1826         __ push(klass_RInfo);
1827 #ifdef _LP64
1828         __ push(k_RInfo);
1829 #else
1830         __ pushklass(k->constant_encoding());
1831 #endif // _LP64
1832         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1833         __ pop(klass_RInfo);
1834         __ pop(klass_RInfo);
1835         // result is a boolean
1836         __ cmpl(klass_RInfo, 0);
1837         __ jcc(Assembler::equal, *failure_target);
1838         // successful cast, fall through to profile or jump
1839       }
1840     } else {
1841       // perform the fast part of the checking logic
1842       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1843       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1844       __ push(klass_RInfo);
1845       __ push(k_RInfo);
1846       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1847       __ pop(klass_RInfo);
1848       __ pop(k_RInfo);
1849       // result is a boolean
1850       __ cmpl(k_RInfo, 0);
1851       __ jcc(Assembler::equal, *failure_target);
1852       // successful cast, fall through to profile or jump
1853     }
1854   }
1855   if (op->should_profile()) {
1856     Register mdo  = klass_RInfo, recv = k_RInfo;
1857     __ bind(profile_cast_success);
1858     __ mov_metadata(mdo, md->constant_encoding());
1859     __ load_klass(recv, obj, tmp_load_klass);
1860     type_profile_helper(mdo, md, data, recv, success);
1861     __ jmp(*success);
1862 
1863     __ bind(profile_cast_failure);
1864     __ mov_metadata(mdo, md->constant_encoding());
1865     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1866     __ subptr(counter_addr, DataLayout::counter_increment);
1867     __ jmp(*failure);
1868   }
1869   __ jmp(*success);
1870 }
1871 
1872 
1873 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1874   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1875   LIR_Code code = op->code();
1876   if (code == lir_store_check) {
1877     Register value = op->object()->as_register();
1878     Register array = op->array()->as_register();
1879     Register k_RInfo = op->tmp1()->as_register();
1880     Register klass_RInfo = op->tmp2()->as_register();
1881     Register Rtmp1 = op->tmp3()->as_register();
1882 
1883     CodeStub* stub = op->stub();
1884 
1885     // check if it needs to be profiled
1886     ciMethodData* md = NULL;
1887     ciProfileData* data = NULL;
1888 
1889     if (op->should_profile()) {
1890       ciMethod* method = op->profiled_method();
1891       assert(method != NULL, "Should have method");
1892       int bci = op->profiled_bci();
1893       md = method->method_data_or_null();
1894       assert(md != NULL, "Sanity");
1895       data = md->bci_to_data(bci);
1896       assert(data != NULL,                "need data for type check");
1897       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1898     }
1899     Label profile_cast_success, profile_cast_failure, done;
1900     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1901     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1902 
1903     __ cmpptr(value, (int32_t)NULL_WORD);
1904     if (op->should_profile()) {
1905       Label not_null;
1906       __ jccb(Assembler::notEqual, not_null);
1907       // Object is null; update MDO and exit
1908       Register mdo  = klass_RInfo;
1909       __ mov_metadata(mdo, md->constant_encoding());
1910       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1911       int header_bits = BitData::null_seen_byte_constant();
1912       __ orb(data_addr, header_bits);
1913       __ jmp(done);
1914       __ bind(not_null);
1915     } else {
1916       __ jcc(Assembler::equal, done);
1917     }
1918 
1919     add_debug_info_for_null_check_here(op->info_for_exception());
1920     __ load_klass(k_RInfo, array, tmp_load_klass);
1921     __ load_klass(klass_RInfo, value, tmp_load_klass);
1922 
1923     // get instance klass (it's already uncompressed)
1924     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1925     // perform the fast part of the checking logic
1926     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1927     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1928     __ push(klass_RInfo);
1929     __ push(k_RInfo);
1930     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1931     __ pop(klass_RInfo);
1932     __ pop(k_RInfo);
1933     // result is a boolean
1934     __ cmpl(k_RInfo, 0);
1935     __ jcc(Assembler::equal, *failure_target);
1936     // fall through to the success case
1937 
1938     if (op->should_profile()) {
1939       Register mdo  = klass_RInfo, recv = k_RInfo;
1940       __ bind(profile_cast_success);
1941       __ mov_metadata(mdo, md->constant_encoding());
1942       __ load_klass(recv, value, tmp_load_klass);
1943       type_profile_helper(mdo, md, data, recv, &done);
1944       __ jmpb(done);
1945 
1946       __ bind(profile_cast_failure);
1947       __ mov_metadata(mdo, md->constant_encoding());
1948       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1949       __ subptr(counter_addr, DataLayout::counter_increment);
1950       __ jmp(*stub->entry());
1951     }
1952 
1953     __ bind(done);
1954   } else
1955     if (code == lir_checkcast) {
1956       Register obj = op->object()->as_register();
1957       Register dst = op->result_opr()->as_register();
1958       Label success;
1959       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1960       __ bind(success);
1961       if (dst != obj) {
1962         __ mov(dst, obj);
1963       }
1964     } else
1965       if (code == lir_instanceof) {
1966         Register obj = op->object()->as_register();
1967         Register dst = op->result_opr()->as_register();
1968         Label success, failure, done;
1969         emit_typecheck_helper(op, &success, &failure, &failure);
1970         __ bind(failure);
1971         __ xorptr(dst, dst);
1972         __ jmpb(done);
1973         __ bind(success);
1974         __ movptr(dst, 1);
1975         __ bind(done);
1976       } else {
1977         ShouldNotReachHere();
1978       }
1979 
1980 }
1981 
1982 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1983   // We are loading/storing from/to an array that *may* be flattened (the
1984   // declared type is Object[], abstract[], interface[] or VT.ref[]).
1985   // If this array is flattened, take the slow path.
1986   Register klass = op->tmp()->as_register();
1987   if (UseArrayMarkWordCheck) {
1988     __ test_flattened_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1989   } else {
1990     Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1991     __ load_klass(klass, op->array()->as_register(), tmp_load_klass);
1992     __ movl(klass, Address(klass, Klass::layout_helper_offset()));
1993     __ testl(klass, Klass::_lh_array_tag_flat_value_bit_inplace);
1994     __ jcc(Assembler::notZero, *op->stub()->entry());
1995   }
1996   if (!op->value()->is_illegal()) {
1997     // The array is not flattened, but it might be null-free. If we are storing
1998     // a null into a null-free array, take the slow path (which will throw NPE).
1999     Label skip;
2000     __ cmpptr(op->value()->as_register(), (int32_t)NULL_WORD);
2001     __ jcc(Assembler::notEqual, skip);
2002     if (UseArrayMarkWordCheck) {
2003       __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
2004     } else {
2005       __ testl(klass, Klass::_lh_null_free_array_bit_inplace);
2006       __ jcc(Assembler::notZero, *op->stub()->entry());
2007     }
2008     __ bind(skip);
2009   }
2010 }
2011 
2012 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
2013   // We are storing into an array that *may* be null-free (the declared type is
2014   // Object[], abstract[], interface[] or VT.ref[]).
2015   if (UseArrayMarkWordCheck) {
2016     Label test_mark_word;
2017     Register tmp = op->tmp()->as_register();
2018     __ movptr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
2019     __ testl(tmp, markWord::unlocked_value);
2020     __ jccb(Assembler::notZero, test_mark_word);
2021     __ load_prototype_header(tmp, op->array()->as_register(), rscratch1);
2022     __ bind(test_mark_word);
2023     __ testl(tmp, markWord::null_free_array_bit_in_place);
2024   } else {
2025     Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
2026     Register klass = op->tmp()->as_register();
2027     __ load_klass(klass, op->array()->as_register(), tmp_load_klass);
2028     __ movl(klass, Address(klass, Klass::layout_helper_offset()));
2029     __ testl(klass, Klass::_lh_null_free_array_bit_inplace);
2030   }
2031 }
2032 
2033 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
2034   Label L_oops_equal;
2035   Label L_oops_not_equal;
2036   Label L_end;
2037 
2038   Register left  = op->left()->as_register();
2039   Register right = op->right()->as_register();
2040 
2041   __ cmpptr(left, right);
2042   __ jcc(Assembler::equal, L_oops_equal);
2043 
2044   // (1) Null check -- if one of the operands is null, the other must not be null (because
2045   //     the two references are not equal), so they are not substitutable,
2046   //     FIXME: do null check only if the operand is nullable
2047   __ testptr(left, right);
2048   __ jcc(Assembler::zero, L_oops_not_equal);
2049 
2050   ciKlass* left_klass = op->left_klass();
2051   ciKlass* right_klass = op->right_klass();
2052 
2053   // (2) Inline type check -- if either of the operands is not a inline type,
2054   //     they are not substitutable. We do this only if we are not sure that the
2055   //     operands are inline type
2056   if ((left_klass == NULL || right_klass == NULL) ||// The klass is still unloaded, or came from a Phi node.
2057       !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
2058     Register tmp1  = op->tmp1()->as_register();
2059     __ movptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2060     __ andptr(tmp1, Address(left, oopDesc::mark_offset_in_bytes()));
2061     __ andptr(tmp1, Address(right, oopDesc::mark_offset_in_bytes()));
2062     __ cmpptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2063     __ jcc(Assembler::notEqual, L_oops_not_equal);
2064   }
2065 
2066   // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
2067   if (left_klass != NULL && left_klass->is_inlinetype() && left_klass == right_klass) {
2068     // No need to load klass -- the operands are statically known to be the same inline klass.
2069     __ jmp(*op->stub()->entry());
2070   } else {
2071     Register left_klass_op = op->left_klass_op()->as_register();
2072     Register right_klass_op = op->right_klass_op()->as_register();
2073 
2074     if (UseCompressedClassPointers) {
2075       __ movl(left_klass_op,  Address(left,  oopDesc::klass_offset_in_bytes()));
2076       __ movl(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2077       __ cmpl(left_klass_op, right_klass_op);
2078     } else {
2079       __ movptr(left_klass_op,  Address(left,  oopDesc::klass_offset_in_bytes()));
2080       __ movptr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2081       __ cmpptr(left_klass_op, right_klass_op);
2082     }
2083 
2084     __ jcc(Assembler::equal, *op->stub()->entry()); // same klass -> do slow check
2085     // fall through to L_oops_not_equal
2086   }
2087 
2088   __ bind(L_oops_not_equal);
2089   move(op->not_equal_result(), op->result_opr());
2090   __ jmp(L_end);
2091 
2092   __ bind(L_oops_equal);
2093   move(op->equal_result(), op->result_opr());
2094   __ jmp(L_end);
2095 
2096   // We've returned from the stub. RAX contains 0x0 IFF the two
2097   // operands are not substitutable. (Don't compare against 0x1 in case the
2098   // C compiler is naughty)
2099   __ bind(*op->stub()->continuation());
2100   __ cmpl(rax, 0);
2101   __ jcc(Assembler::equal, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
2102   move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
2103   // fall-through
2104   __ bind(L_end);
2105 }
2106 
2107 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2108   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
2109     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
2110     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
2111     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
2112     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
2113     Register addr = op->addr()->as_register();
2114     __ lock();
2115     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
2116 
2117   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
2118     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
2119     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2120     Register newval = op->new_value()->as_register();
2121     Register cmpval = op->cmp_value()->as_register();
2122     assert(cmpval == rax, "wrong register");
2123     assert(newval != NULL, "new val must be register");
2124     assert(cmpval != newval, "cmp and new values must be in different registers");
2125     assert(cmpval != addr, "cmp and addr must be in different registers");
2126     assert(newval != addr, "new value and addr must be in different registers");
2127 
2128     if ( op->code() == lir_cas_obj) {
2129 #ifdef _LP64
2130       if (UseCompressedOops) {
2131         __ encode_heap_oop(cmpval);
2132         __ mov(rscratch1, newval);
2133         __ encode_heap_oop(rscratch1);
2134         __ lock();
2135         // cmpval (rax) is implicitly used by this instruction
2136         __ cmpxchgl(rscratch1, Address(addr, 0));
2137       } else
2138 #endif
2139       {
2140         __ lock();
2141         __ cmpxchgptr(newval, Address(addr, 0));
2142       }
2143     } else {
2144       assert(op->code() == lir_cas_int, "lir_cas_int expected");
2145       __ lock();
2146       __ cmpxchgl(newval, Address(addr, 0));
2147     }
2148 #ifdef _LP64
2149   } else if (op->code() == lir_cas_long) {
2150     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2151     Register newval = op->new_value()->as_register_lo();
2152     Register cmpval = op->cmp_value()->as_register_lo();
2153     assert(cmpval == rax, "wrong register");
2154     assert(newval != NULL, "new val must be register");
2155     assert(cmpval != newval, "cmp and new values must be in different registers");
2156     assert(cmpval != addr, "cmp and addr must be in different registers");
2157     assert(newval != addr, "new value and addr must be in different registers");
2158     __ lock();
2159     __ cmpxchgq(newval, Address(addr, 0));
2160 #endif // _LP64
2161   } else {
2162     Unimplemented();
2163   }
2164 }
2165 
2166 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
2167   assert(dst->is_cpu_register(), "must be");
2168   assert(dst->type() == src->type(), "must be");
2169 
2170   if (src->is_cpu_register()) {
2171     reg2reg(src, dst);
2172   } else if (src->is_stack()) {
2173     stack2reg(src, dst, dst->type());
2174   } else if (src->is_constant()) {
2175     const2reg(src, dst, lir_patch_none, NULL);
2176   } else {
2177     ShouldNotReachHere();
2178   }
2179 }
2180 
2181 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2182   Assembler::Condition acond, ncond;
2183   switch (condition) {
2184     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
2185     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
2186     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
2187     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
2188     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
2189     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
2190     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
2191     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
2192     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
2193                                 ShouldNotReachHere();
2194   }
2195 
2196   if (opr1->is_cpu_register()) {
2197     reg2reg(opr1, result);
2198   } else if (opr1->is_stack()) {
2199     stack2reg(opr1, result, result->type());
2200   } else if (opr1->is_constant()) {
2201     const2reg(opr1, result, lir_patch_none, NULL);
2202   } else {
2203     ShouldNotReachHere();
2204   }
2205 
2206   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2207     // optimized version that does not require a branch
2208     if (opr2->is_single_cpu()) {
2209       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2210       __ cmov(ncond, result->as_register(), opr2->as_register());
2211     } else if (opr2->is_double_cpu()) {
2212       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2213       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2214       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2215       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2216     } else if (opr2->is_single_stack()) {
2217       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2218     } else if (opr2->is_double_stack()) {
2219       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2220       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2221     } else {
2222       ShouldNotReachHere();
2223     }
2224 
2225   } else {
2226     Label skip;
2227     __ jcc (acond, skip);
2228     if (opr2->is_cpu_register()) {
2229       reg2reg(opr2, result);
2230     } else if (opr2->is_stack()) {
2231       stack2reg(opr2, result, result->type());
2232     } else if (opr2->is_constant()) {
2233       const2reg(opr2, result, lir_patch_none, NULL);
2234     } else {
2235       ShouldNotReachHere();
2236     }
2237     __ bind(skip);
2238   }
2239 }
2240 
2241 
2242 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2243   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2244 
2245   if (left->is_single_cpu()) {
2246     assert(left == dest, "left and dest must be equal");
2247     Register lreg = left->as_register();
2248 
2249     if (right->is_single_cpu()) {
2250       // cpu register - cpu register
2251       Register rreg = right->as_register();
2252       switch (code) {
2253         case lir_add: __ addl (lreg, rreg); break;
2254         case lir_sub: __ subl (lreg, rreg); break;
2255         case lir_mul: __ imull(lreg, rreg); break;
2256         default:      ShouldNotReachHere();
2257       }
2258 
2259     } else if (right->is_stack()) {
2260       // cpu register - stack
2261       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2262       switch (code) {
2263         case lir_add: __ addl(lreg, raddr); break;
2264         case lir_sub: __ subl(lreg, raddr); break;
2265         default:      ShouldNotReachHere();
2266       }
2267 
2268     } else if (right->is_constant()) {
2269       // cpu register - constant
2270       jint c = right->as_constant_ptr()->as_jint();
2271       switch (code) {
2272         case lir_add: {
2273           __ incrementl(lreg, c);
2274           break;
2275         }
2276         case lir_sub: {
2277           __ decrementl(lreg, c);
2278           break;
2279         }
2280         default: ShouldNotReachHere();
2281       }
2282 
2283     } else {
2284       ShouldNotReachHere();
2285     }
2286 
2287   } else if (left->is_double_cpu()) {
2288     assert(left == dest, "left and dest must be equal");
2289     Register lreg_lo = left->as_register_lo();
2290     Register lreg_hi = left->as_register_hi();
2291 
2292     if (right->is_double_cpu()) {
2293       // cpu register - cpu register
2294       Register rreg_lo = right->as_register_lo();
2295       Register rreg_hi = right->as_register_hi();
2296       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2297       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2298       switch (code) {
2299         case lir_add:
2300           __ addptr(lreg_lo, rreg_lo);
2301           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2302           break;
2303         case lir_sub:
2304           __ subptr(lreg_lo, rreg_lo);
2305           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2306           break;
2307         case lir_mul:
2308 #ifdef _LP64
2309           __ imulq(lreg_lo, rreg_lo);
2310 #else
2311           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2312           __ imull(lreg_hi, rreg_lo);
2313           __ imull(rreg_hi, lreg_lo);
2314           __ addl (rreg_hi, lreg_hi);
2315           __ mull (rreg_lo);
2316           __ addl (lreg_hi, rreg_hi);
2317 #endif // _LP64
2318           break;
2319         default:
2320           ShouldNotReachHere();
2321       }
2322 
2323     } else if (right->is_constant()) {
2324       // cpu register - constant
2325 #ifdef _LP64
2326       jlong c = right->as_constant_ptr()->as_jlong_bits();
2327       __ movptr(r10, (intptr_t) c);
2328       switch (code) {
2329         case lir_add:
2330           __ addptr(lreg_lo, r10);
2331           break;
2332         case lir_sub:
2333           __ subptr(lreg_lo, r10);
2334           break;
2335         default:
2336           ShouldNotReachHere();
2337       }
2338 #else
2339       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2340       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2341       switch (code) {
2342         case lir_add:
2343           __ addptr(lreg_lo, c_lo);
2344           __ adcl(lreg_hi, c_hi);
2345           break;
2346         case lir_sub:
2347           __ subptr(lreg_lo, c_lo);
2348           __ sbbl(lreg_hi, c_hi);
2349           break;
2350         default:
2351           ShouldNotReachHere();
2352       }
2353 #endif // _LP64
2354 
2355     } else {
2356       ShouldNotReachHere();
2357     }
2358 
2359   } else if (left->is_single_xmm()) {
2360     assert(left == dest, "left and dest must be equal");
2361     XMMRegister lreg = left->as_xmm_float_reg();
2362 
2363     if (right->is_single_xmm()) {
2364       XMMRegister rreg = right->as_xmm_float_reg();
2365       switch (code) {
2366         case lir_add: __ addss(lreg, rreg);  break;
2367         case lir_sub: __ subss(lreg, rreg);  break;
2368         case lir_mul: __ mulss(lreg, rreg);  break;
2369         case lir_div: __ divss(lreg, rreg);  break;
2370         default: ShouldNotReachHere();
2371       }
2372     } else {
2373       Address raddr;
2374       if (right->is_single_stack()) {
2375         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2376       } else if (right->is_constant()) {
2377         // hack for now
2378         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2379       } else {
2380         ShouldNotReachHere();
2381       }
2382       switch (code) {
2383         case lir_add: __ addss(lreg, raddr);  break;
2384         case lir_sub: __ subss(lreg, raddr);  break;
2385         case lir_mul: __ mulss(lreg, raddr);  break;
2386         case lir_div: __ divss(lreg, raddr);  break;
2387         default: ShouldNotReachHere();
2388       }
2389     }
2390 
2391   } else if (left->is_double_xmm()) {
2392     assert(left == dest, "left and dest must be equal");
2393 
2394     XMMRegister lreg = left->as_xmm_double_reg();
2395     if (right->is_double_xmm()) {
2396       XMMRegister rreg = right->as_xmm_double_reg();
2397       switch (code) {
2398         case lir_add: __ addsd(lreg, rreg);  break;
2399         case lir_sub: __ subsd(lreg, rreg);  break;
2400         case lir_mul: __ mulsd(lreg, rreg);  break;
2401         case lir_div: __ divsd(lreg, rreg);  break;
2402         default: ShouldNotReachHere();
2403       }
2404     } else {
2405       Address raddr;
2406       if (right->is_double_stack()) {
2407         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2408       } else if (right->is_constant()) {
2409         // hack for now
2410         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2411       } else {
2412         ShouldNotReachHere();
2413       }
2414       switch (code) {
2415         case lir_add: __ addsd(lreg, raddr);  break;
2416         case lir_sub: __ subsd(lreg, raddr);  break;
2417         case lir_mul: __ mulsd(lreg, raddr);  break;
2418         case lir_div: __ divsd(lreg, raddr);  break;
2419         default: ShouldNotReachHere();
2420       }
2421     }
2422 
2423 #ifndef _LP64
2424   } else if (left->is_single_fpu()) {
2425     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2426 
2427     if (right->is_single_fpu()) {
2428       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2429 
2430     } else {
2431       assert(left->fpu_regnr() == 0, "left must be on TOS");
2432       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2433 
2434       Address raddr;
2435       if (right->is_single_stack()) {
2436         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2437       } else if (right->is_constant()) {
2438         address const_addr = float_constant(right->as_jfloat());
2439         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2440         // hack for now
2441         raddr = __ as_Address(InternalAddress(const_addr));
2442       } else {
2443         ShouldNotReachHere();
2444       }
2445 
2446       switch (code) {
2447         case lir_add: __ fadd_s(raddr); break;
2448         case lir_sub: __ fsub_s(raddr); break;
2449         case lir_mul: __ fmul_s(raddr); break;
2450         case lir_div: __ fdiv_s(raddr); break;
2451         default:      ShouldNotReachHere();
2452       }
2453     }
2454 
2455   } else if (left->is_double_fpu()) {
2456     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2457 
2458     if (code == lir_mul || code == lir_div) {
2459       // Double values require special handling for strictfp mul/div on x86
2460       __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2461       __ fmulp(left->fpu_regnrLo() + 1);
2462     }
2463 
2464     if (right->is_double_fpu()) {
2465       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2466 
2467     } else {
2468       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2469       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2470 
2471       Address raddr;
2472       if (right->is_double_stack()) {
2473         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2474       } else if (right->is_constant()) {
2475         // hack for now
2476         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2477       } else {
2478         ShouldNotReachHere();
2479       }
2480 
2481       switch (code) {
2482         case lir_add: __ fadd_d(raddr); break;
2483         case lir_sub: __ fsub_d(raddr); break;
2484         case lir_mul: __ fmul_d(raddr); break;
2485         case lir_div: __ fdiv_d(raddr); break;
2486         default: ShouldNotReachHere();
2487       }
2488     }
2489 
2490     if (code == lir_mul || code == lir_div) {
2491       // Double values require special handling for strictfp mul/div on x86
2492       __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2493       __ fmulp(dest->fpu_regnrLo() + 1);
2494     }
2495 #endif // !_LP64
2496 
2497   } else if (left->is_single_stack() || left->is_address()) {
2498     assert(left == dest, "left and dest must be equal");
2499 
2500     Address laddr;
2501     if (left->is_single_stack()) {
2502       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2503     } else if (left->is_address()) {
2504       laddr = as_Address(left->as_address_ptr());
2505     } else {
2506       ShouldNotReachHere();
2507     }
2508 
2509     if (right->is_single_cpu()) {
2510       Register rreg = right->as_register();
2511       switch (code) {
2512         case lir_add: __ addl(laddr, rreg); break;
2513         case lir_sub: __ subl(laddr, rreg); break;
2514         default:      ShouldNotReachHere();
2515       }
2516     } else if (right->is_constant()) {
2517       jint c = right->as_constant_ptr()->as_jint();
2518       switch (code) {
2519         case lir_add: {
2520           __ incrementl(laddr, c);
2521           break;
2522         }
2523         case lir_sub: {
2524           __ decrementl(laddr, c);
2525           break;
2526         }
2527         default: ShouldNotReachHere();
2528       }
2529     } else {
2530       ShouldNotReachHere();
2531     }
2532 
2533   } else {
2534     ShouldNotReachHere();
2535   }
2536 }
2537 
2538 #ifndef _LP64
2539 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2540   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2541   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2542   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2543 
2544   bool left_is_tos = (left_index == 0);
2545   bool dest_is_tos = (dest_index == 0);
2546   int non_tos_index = (left_is_tos ? right_index : left_index);
2547 
2548   switch (code) {
2549     case lir_add:
2550       if (pop_fpu_stack)       __ faddp(non_tos_index);
2551       else if (dest_is_tos)    __ fadd (non_tos_index);
2552       else                     __ fadda(non_tos_index);
2553       break;
2554 
2555     case lir_sub:
2556       if (left_is_tos) {
2557         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2558         else if (dest_is_tos)  __ fsub  (non_tos_index);
2559         else                   __ fsubra(non_tos_index);
2560       } else {
2561         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2562         else if (dest_is_tos)  __ fsubr (non_tos_index);
2563         else                   __ fsuba (non_tos_index);
2564       }
2565       break;
2566 
2567     case lir_mul:
2568       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2569       else if (dest_is_tos)    __ fmul (non_tos_index);
2570       else                     __ fmula(non_tos_index);
2571       break;
2572 
2573     case lir_div:
2574       if (left_is_tos) {
2575         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2576         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2577         else                   __ fdivra(non_tos_index);
2578       } else {
2579         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2580         else if (dest_is_tos)  __ fdivr (non_tos_index);
2581         else                   __ fdiva (non_tos_index);
2582       }
2583       break;
2584 
2585     case lir_rem:
2586       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2587       __ fremr(noreg);
2588       break;
2589 
2590     default:
2591       ShouldNotReachHere();
2592   }
2593 }
2594 #endif // _LP64
2595 
2596 
2597 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2598   if (value->is_double_xmm()) {
2599     switch(code) {
2600       case lir_abs :
2601         {
2602 #ifdef _LP64
2603           if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2604             assert(tmp->is_valid(), "need temporary");
2605             __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2606           } else
2607 #endif
2608           {
2609             if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2610               __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2611             }
2612             assert(!tmp->is_valid(), "do not need temporary");
2613             __ andpd(dest->as_xmm_double_reg(),
2614                      ExternalAddress((address)double_signmask_pool));
2615           }
2616         }
2617         break;
2618 
2619       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2620       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2621       default      : ShouldNotReachHere();
2622     }
2623 
2624 #ifndef _LP64
2625   } else if (value->is_double_fpu()) {
2626     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2627     switch(code) {
2628       case lir_abs   : __ fabs() ; break;
2629       case lir_sqrt  : __ fsqrt(); break;
2630       default      : ShouldNotReachHere();
2631     }
2632 #endif // !_LP64
2633   } else {
2634     Unimplemented();
2635   }
2636 }
2637 
2638 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2639   // assert(left->destroys_register(), "check");
2640   if (left->is_single_cpu()) {
2641     Register reg = left->as_register();
2642     if (right->is_constant()) {
2643       int val = right->as_constant_ptr()->as_jint();
2644       switch (code) {
2645         case lir_logic_and: __ andl (reg, val); break;
2646         case lir_logic_or:  __ orl  (reg, val); break;
2647         case lir_logic_xor: __ xorl (reg, val); break;
2648         default: ShouldNotReachHere();
2649       }
2650     } else if (right->is_stack()) {
2651       // added support for stack operands
2652       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2653       switch (code) {
2654         case lir_logic_and: __ andl (reg, raddr); break;
2655         case lir_logic_or:  __ orl  (reg, raddr); break;
2656         case lir_logic_xor: __ xorl (reg, raddr); break;
2657         default: ShouldNotReachHere();
2658       }
2659     } else {
2660       Register rright = right->as_register();
2661       switch (code) {
2662         case lir_logic_and: __ andptr (reg, rright); break;
2663         case lir_logic_or : __ orptr  (reg, rright); break;
2664         case lir_logic_xor: __ xorptr (reg, rright); break;
2665         default: ShouldNotReachHere();
2666       }
2667     }
2668     move_regs(reg, dst->as_register());
2669   } else {
2670     Register l_lo = left->as_register_lo();
2671     Register l_hi = left->as_register_hi();
2672     if (right->is_constant()) {
2673 #ifdef _LP64
2674       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2675       switch (code) {
2676         case lir_logic_and:
2677           __ andq(l_lo, rscratch1);
2678           break;
2679         case lir_logic_or:
2680           __ orq(l_lo, rscratch1);
2681           break;
2682         case lir_logic_xor:
2683           __ xorq(l_lo, rscratch1);
2684           break;
2685         default: ShouldNotReachHere();
2686       }
2687 #else
2688       int r_lo = right->as_constant_ptr()->as_jint_lo();
2689       int r_hi = right->as_constant_ptr()->as_jint_hi();
2690       switch (code) {
2691         case lir_logic_and:
2692           __ andl(l_lo, r_lo);
2693           __ andl(l_hi, r_hi);
2694           break;
2695         case lir_logic_or:
2696           __ orl(l_lo, r_lo);
2697           __ orl(l_hi, r_hi);
2698           break;
2699         case lir_logic_xor:
2700           __ xorl(l_lo, r_lo);
2701           __ xorl(l_hi, r_hi);
2702           break;
2703         default: ShouldNotReachHere();
2704       }
2705 #endif // _LP64
2706     } else {
2707 #ifdef _LP64
2708       Register r_lo;
2709       if (is_reference_type(right->type())) {
2710         r_lo = right->as_register();
2711       } else {
2712         r_lo = right->as_register_lo();
2713       }
2714 #else
2715       Register r_lo = right->as_register_lo();
2716       Register r_hi = right->as_register_hi();
2717       assert(l_lo != r_hi, "overwriting registers");
2718 #endif
2719       switch (code) {
2720         case lir_logic_and:
2721           __ andptr(l_lo, r_lo);
2722           NOT_LP64(__ andptr(l_hi, r_hi);)
2723           break;
2724         case lir_logic_or:
2725           __ orptr(l_lo, r_lo);
2726           NOT_LP64(__ orptr(l_hi, r_hi);)
2727           break;
2728         case lir_logic_xor:
2729           __ xorptr(l_lo, r_lo);
2730           NOT_LP64(__ xorptr(l_hi, r_hi);)
2731           break;
2732         default: ShouldNotReachHere();
2733       }
2734     }
2735 
2736     Register dst_lo = dst->as_register_lo();
2737     Register dst_hi = dst->as_register_hi();
2738 
2739 #ifdef _LP64
2740     move_regs(l_lo, dst_lo);
2741 #else
2742     if (dst_lo == l_hi) {
2743       assert(dst_hi != l_lo, "overwriting registers");
2744       move_regs(l_hi, dst_hi);
2745       move_regs(l_lo, dst_lo);
2746     } else {
2747       assert(dst_lo != l_hi, "overwriting registers");
2748       move_regs(l_lo, dst_lo);
2749       move_regs(l_hi, dst_hi);
2750     }
2751 #endif // _LP64
2752   }
2753 }
2754 
2755 
2756 // we assume that rax, and rdx can be overwritten
2757 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2758 
2759   assert(left->is_single_cpu(),   "left must be register");
2760   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2761   assert(result->is_single_cpu(), "result must be register");
2762 
2763   //  assert(left->destroys_register(), "check");
2764   //  assert(right->destroys_register(), "check");
2765 
2766   Register lreg = left->as_register();
2767   Register dreg = result->as_register();
2768 
2769   if (right->is_constant()) {
2770     jint divisor = right->as_constant_ptr()->as_jint();
2771     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2772     if (code == lir_idiv) {
2773       assert(lreg == rax, "must be rax,");
2774       assert(temp->as_register() == rdx, "tmp register must be rdx");
2775       __ cdql(); // sign extend into rdx:rax
2776       if (divisor == 2) {
2777         __ subl(lreg, rdx);
2778       } else {
2779         __ andl(rdx, divisor - 1);
2780         __ addl(lreg, rdx);
2781       }
2782       __ sarl(lreg, log2i_exact(divisor));
2783       move_regs(lreg, dreg);
2784     } else if (code == lir_irem) {
2785       Label done;
2786       __ mov(dreg, lreg);
2787       __ andl(dreg, 0x80000000 | (divisor - 1));
2788       __ jcc(Assembler::positive, done);
2789       __ decrement(dreg);
2790       __ orl(dreg, ~(divisor - 1));
2791       __ increment(dreg);
2792       __ bind(done);
2793     } else {
2794       ShouldNotReachHere();
2795     }
2796   } else {
2797     Register rreg = right->as_register();
2798     assert(lreg == rax, "left register must be rax,");
2799     assert(rreg != rdx, "right register must not be rdx");
2800     assert(temp->as_register() == rdx, "tmp register must be rdx");
2801 
2802     move_regs(lreg, rax);
2803 
2804     int idivl_offset = __ corrected_idivl(rreg);
2805     if (ImplicitDiv0Checks) {
2806       add_debug_info_for_div0(idivl_offset, info);
2807     }
2808     if (code == lir_irem) {
2809       move_regs(rdx, dreg); // result is in rdx
2810     } else {
2811       move_regs(rax, dreg);
2812     }
2813   }
2814 }
2815 
2816 
2817 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2818   if (opr1->is_single_cpu()) {
2819     Register reg1 = opr1->as_register();
2820     if (opr2->is_single_cpu()) {
2821       // cpu register - cpu register
2822       if (is_reference_type(opr1->type())) {
2823         __ cmpoop(reg1, opr2->as_register());
2824       } else {
2825         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2826         __ cmpl(reg1, opr2->as_register());
2827       }
2828     } else if (opr2->is_stack()) {
2829       // cpu register - stack
2830       if (is_reference_type(opr1->type())) {
2831         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2832       } else {
2833         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2834       }
2835     } else if (opr2->is_constant()) {
2836       // cpu register - constant
2837       LIR_Const* c = opr2->as_constant_ptr();
2838       if (c->type() == T_INT) {
2839         __ cmpl(reg1, c->as_jint());
2840       } else if (c->type() == T_METADATA) {
2841         // All we need for now is a comparison with NULL for equality.
2842         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2843         Metadata* m = c->as_metadata();
2844         if (m == NULL) {
2845           __ cmpptr(reg1, (int32_t)0);
2846         } else {
2847           ShouldNotReachHere();
2848         }
2849       } else if (is_reference_type(c->type())) {
2850         // In 64bit oops are single register
2851         jobject o = c->as_jobject();
2852         if (o == NULL) {
2853           __ cmpptr(reg1, (int32_t)NULL_WORD);
2854         } else {
2855           __ cmpoop(reg1, o);
2856         }
2857       } else {
2858         fatal("unexpected type: %s", basictype_to_str(c->type()));
2859       }
2860       // cpu register - address
2861     } else if (opr2->is_address()) {
2862       if (op->info() != NULL) {
2863         add_debug_info_for_null_check_here(op->info());
2864       }
2865       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2866     } else {
2867       ShouldNotReachHere();
2868     }
2869 
2870   } else if(opr1->is_double_cpu()) {
2871     Register xlo = opr1->as_register_lo();
2872     Register xhi = opr1->as_register_hi();
2873     if (opr2->is_double_cpu()) {
2874 #ifdef _LP64
2875       __ cmpptr(xlo, opr2->as_register_lo());
2876 #else
2877       // cpu register - cpu register
2878       Register ylo = opr2->as_register_lo();
2879       Register yhi = opr2->as_register_hi();
2880       __ subl(xlo, ylo);
2881       __ sbbl(xhi, yhi);
2882       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2883         __ orl(xhi, xlo);
2884       }
2885 #endif // _LP64
2886     } else if (opr2->is_constant()) {
2887       // cpu register - constant 0
2888       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2889 #ifdef _LP64
2890       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2891 #else
2892       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2893       __ orl(xhi, xlo);
2894 #endif // _LP64
2895     } else {
2896       ShouldNotReachHere();
2897     }
2898 
2899   } else if (opr1->is_single_xmm()) {
2900     XMMRegister reg1 = opr1->as_xmm_float_reg();
2901     if (opr2->is_single_xmm()) {
2902       // xmm register - xmm register
2903       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2904     } else if (opr2->is_stack()) {
2905       // xmm register - stack
2906       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2907     } else if (opr2->is_constant()) {
2908       // xmm register - constant
2909       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2910     } else if (opr2->is_address()) {
2911       // xmm register - address
2912       if (op->info() != NULL) {
2913         add_debug_info_for_null_check_here(op->info());
2914       }
2915       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2916     } else {
2917       ShouldNotReachHere();
2918     }
2919 
2920   } else if (opr1->is_double_xmm()) {
2921     XMMRegister reg1 = opr1->as_xmm_double_reg();
2922     if (opr2->is_double_xmm()) {
2923       // xmm register - xmm register
2924       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2925     } else if (opr2->is_stack()) {
2926       // xmm register - stack
2927       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2928     } else if (opr2->is_constant()) {
2929       // xmm register - constant
2930       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2931     } else if (opr2->is_address()) {
2932       // xmm register - address
2933       if (op->info() != NULL) {
2934         add_debug_info_for_null_check_here(op->info());
2935       }
2936       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2937     } else {
2938       ShouldNotReachHere();
2939     }
2940 
2941 #ifndef _LP64
2942   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2943     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2944     assert(opr2->is_fpu_register(), "both must be registers");
2945     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2946 #endif // LP64
2947 
2948   } else if (opr1->is_address() && opr2->is_constant()) {
2949     LIR_Const* c = opr2->as_constant_ptr();
2950 #ifdef _LP64
2951     if (is_reference_type(c->type())) {
2952       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2953       __ movoop(rscratch1, c->as_jobject());
2954     }
2955 #endif // LP64
2956     if (op->info() != NULL) {
2957       add_debug_info_for_null_check_here(op->info());
2958     }
2959     // special case: address - constant
2960     LIR_Address* addr = opr1->as_address_ptr();
2961     if (c->type() == T_INT) {
2962       __ cmpl(as_Address(addr), c->as_jint());
2963     } else if (is_reference_type(c->type())) {
2964 #ifdef _LP64
2965       // %%% Make this explode if addr isn't reachable until we figure out a
2966       // better strategy by giving noreg as the temp for as_Address
2967       __ cmpoop(rscratch1, as_Address(addr, noreg));
2968 #else
2969       __ cmpoop(as_Address(addr), c->as_jobject());
2970 #endif // _LP64
2971     } else {
2972       ShouldNotReachHere();
2973     }
2974 
2975   } else {
2976     ShouldNotReachHere();
2977   }
2978 }
2979 
2980 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2981   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2982     if (left->is_single_xmm()) {
2983       assert(right->is_single_xmm(), "must match");
2984       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2985     } else if (left->is_double_xmm()) {
2986       assert(right->is_double_xmm(), "must match");
2987       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2988 
2989     } else {
2990 #ifdef _LP64
2991       ShouldNotReachHere();
2992 #else
2993       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2994       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2995 
2996       assert(left->fpu() == 0, "left must be on TOS");
2997       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2998                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2999 #endif // LP64
3000     }
3001   } else {
3002     assert(code == lir_cmp_l2i, "check");
3003 #ifdef _LP64
3004     Label done;
3005     Register dest = dst->as_register();
3006     __ cmpptr(left->as_register_lo(), right->as_register_lo());
3007     __ movl(dest, -1);
3008     __ jccb(Assembler::less, done);
3009     __ set_byte_if_not_zero(dest);
3010     __ movzbl(dest, dest);
3011     __ bind(done);
3012 #else
3013     __ lcmp2int(left->as_register_hi(),
3014                 left->as_register_lo(),
3015                 right->as_register_hi(),
3016                 right->as_register_lo());
3017     move_regs(left->as_register_hi(), dst->as_register());
3018 #endif // _LP64
3019   }
3020 }
3021 
3022 
3023 void LIR_Assembler::align_call(LIR_Code code) {
3024   // make sure that the displacement word of the call ends up word aligned
3025   int offset = __ offset();
3026   switch (code) {
3027   case lir_static_call:
3028   case lir_optvirtual_call:
3029   case lir_dynamic_call:
3030     offset += NativeCall::displacement_offset;
3031     break;
3032   case lir_icvirtual_call:
3033     offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
3034     break;
3035   default: ShouldNotReachHere();
3036   }
3037   __ align(BytesPerWord, offset);
3038 }
3039 
3040 
3041 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
3042   assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
3043          "must be aligned");
3044   __ call(AddressLiteral(op->addr(), rtype));
3045   add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3046 }
3047 
3048 
3049 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
3050   __ ic_call(op->addr());
3051   add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3052   assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
3053          "must be aligned");
3054 }
3055 
3056 
3057 void LIR_Assembler::emit_static_call_stub() {
3058   address call_pc = __ pc();
3059   address stub = __ start_a_stub(call_stub_size());
3060   if (stub == NULL) {
3061     bailout("static call stub overflow");
3062     return;
3063   }
3064 
3065   int start = __ offset();
3066 
3067   // make sure that the displacement word of the call ends up word aligned
3068   __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
3069   __ relocate(static_stub_Relocation::spec(call_pc));
3070   __ mov_metadata(rbx, (Metadata*)NULL);
3071   // must be set to -1 at code generation time
3072   assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
3073   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
3074   __ jump(RuntimeAddress(__ pc()));
3075 
3076   assert(__ offset() - start <= call_stub_size(), "stub too big");
3077   __ end_a_stub();
3078 }
3079 
3080 
3081 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
3082   assert(exceptionOop->as_register() == rax, "must match");
3083   assert(exceptionPC->as_register() == rdx, "must match");
3084 
3085   // exception object is not added to oop map by LinearScan
3086   // (LinearScan assumes that no oops are in fixed registers)
3087   info->add_register_oop(exceptionOop);
3088   Runtime1::StubID unwind_id;
3089 
3090   // get current pc information
3091   // pc is only needed if the method has an exception handler, the unwind code does not need it.
3092   int pc_for_athrow_offset = __ offset();
3093   InternalAddress pc_for_athrow(__ pc());
3094   __ lea(exceptionPC->as_register(), pc_for_athrow);
3095   add_call_info(pc_for_athrow_offset, info); // for exception handler
3096 
3097   __ verify_not_null_oop(rax);
3098   // search an exception handler (rax: exception oop, rdx: throwing pc)
3099   if (compilation()->has_fpu_code()) {
3100     unwind_id = Runtime1::handle_exception_id;
3101   } else {
3102     unwind_id = Runtime1::handle_exception_nofpu_id;
3103   }
3104   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
3105 
3106   // enough room for two byte trap
3107   __ nop();
3108 }
3109 
3110 
3111 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
3112   assert(exceptionOop->as_register() == rax, "must match");
3113 
3114   __ jmp(_unwind_handler_entry);
3115 }
3116 
3117 
3118 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3119 
3120   // optimized version for linear scan:
3121   // * count must be already in ECX (guaranteed by LinearScan)
3122   // * left and dest must be equal
3123   // * tmp must be unused
3124   assert(count->as_register() == SHIFT_count, "count must be in ECX");
3125   assert(left == dest, "left and dest must be equal");
3126   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3127 
3128   if (left->is_single_cpu()) {
3129     Register value = left->as_register();
3130     assert(value != SHIFT_count, "left cannot be ECX");
3131 
3132     switch (code) {
3133       case lir_shl:  __ shll(value); break;
3134       case lir_shr:  __ sarl(value); break;
3135       case lir_ushr: __ shrl(value); break;
3136       default: ShouldNotReachHere();
3137     }
3138   } else if (left->is_double_cpu()) {
3139     Register lo = left->as_register_lo();
3140     Register hi = left->as_register_hi();
3141     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3142 #ifdef _LP64
3143     switch (code) {
3144       case lir_shl:  __ shlptr(lo);        break;
3145       case lir_shr:  __ sarptr(lo);        break;
3146       case lir_ushr: __ shrptr(lo);        break;
3147       default: ShouldNotReachHere();
3148     }
3149 #else
3150 
3151     switch (code) {
3152       case lir_shl:  __ lshl(hi, lo);        break;
3153       case lir_shr:  __ lshr(hi, lo, true);  break;
3154       case lir_ushr: __ lshr(hi, lo, false); break;
3155       default: ShouldNotReachHere();
3156     }
3157 #endif // LP64
3158   } else {
3159     ShouldNotReachHere();
3160   }
3161 }
3162 
3163 
3164 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3165   if (dest->is_single_cpu()) {
3166     // first move left into dest so that left is not destroyed by the shift
3167     Register value = dest->as_register();
3168     count = count & 0x1F; // Java spec
3169 
3170     move_regs(left->as_register(), value);
3171     switch (code) {
3172       case lir_shl:  __ shll(value, count); break;
3173       case lir_shr:  __ sarl(value, count); break;
3174       case lir_ushr: __ shrl(value, count); break;
3175       default: ShouldNotReachHere();
3176     }
3177   } else if (dest->is_double_cpu()) {
3178 #ifndef _LP64
3179     Unimplemented();
3180 #else
3181     // first move left into dest so that left is not destroyed by the shift
3182     Register value = dest->as_register_lo();
3183     count = count & 0x1F; // Java spec
3184 
3185     move_regs(left->as_register_lo(), value);
3186     switch (code) {
3187       case lir_shl:  __ shlptr(value, count); break;
3188       case lir_shr:  __ sarptr(value, count); break;
3189       case lir_ushr: __ shrptr(value, count); break;
3190       default: ShouldNotReachHere();
3191     }
3192 #endif // _LP64
3193   } else {
3194     ShouldNotReachHere();
3195   }
3196 }
3197 
3198 
3199 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3200   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3201   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3202   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3203   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3204 }
3205 
3206 
3207 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3208   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3209   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3210   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3211   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3212 }
3213 
3214 
3215 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
3216   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3217   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3218   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3219   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3220 }
3221 
3222 
3223 void LIR_Assembler::store_parameter(Metadata* m,  int offset_from_rsp_in_words) {
3224   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3225   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3226   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3227   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3228 }
3229 
3230 
3231 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
3232   if (null_check) {
3233     __ testptr(obj, obj);
3234     __ jcc(Assembler::zero, *slow_path->entry());
3235   }
3236   if (UseArrayMarkWordCheck) {
3237     if (is_dest) {
3238       __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
3239     } else {
3240       __ test_flattened_array_oop(obj, tmp, *slow_path->entry());
3241     }
3242   } else {
3243     Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3244     __ load_klass(tmp, obj, tmp_load_klass);
3245     __ movl(tmp, Address(tmp, Klass::layout_helper_offset()));
3246     if (is_dest) {
3247       // Take the slow path if it's a null_free destination array, in case the source array contains NULLs.
3248       __ testl(tmp, Klass::_lh_null_free_array_bit_inplace);
3249     } else {
3250       __ testl(tmp, Klass::_lh_array_tag_flat_value_bit_inplace);
3251     }
3252     __ jcc(Assembler::notZero, *slow_path->entry());
3253   }
3254 }
3255 
3256 
3257 // This code replaces a call to arraycopy; no exception may
3258 // be thrown in this code, they must be thrown in the System.arraycopy
3259 // activation frame; we could save some checks if this would not be the case
3260 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3261   ciArrayKlass* default_type = op->expected_type();
3262   Register src = op->src()->as_register();
3263   Register dst = op->dst()->as_register();
3264   Register src_pos = op->src_pos()->as_register();
3265   Register dst_pos = op->dst_pos()->as_register();
3266   Register length  = op->length()->as_register();
3267   Register tmp = op->tmp()->as_register();
3268   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3269 
3270   CodeStub* stub = op->stub();
3271   int flags = op->flags();
3272   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3273   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3274 
3275   if (flags & LIR_OpArrayCopy::always_slow_path) {
3276     __ jmp(*stub->entry());
3277     __ bind(*stub->continuation());
3278     return;
3279   }
3280 
3281   // if we don't know anything, just go through the generic arraycopy
3282   if (default_type == NULL) {
3283     // save outgoing arguments on stack in case call to System.arraycopy is needed
3284     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3285     // for interpreter calling conventions. Now we have to do it in new style conventions.
3286     // For the moment until C1 gets the new register allocator I just force all the
3287     // args to the right place (except the register args) and then on the back side
3288     // reload the register args properly if we go slow path. Yuck
3289 
3290     // These are proper for the calling convention
3291     store_parameter(length, 2);
3292     store_parameter(dst_pos, 1);
3293     store_parameter(dst, 0);
3294 
3295     // these are just temporary placements until we need to reload
3296     store_parameter(src_pos, 3);
3297     store_parameter(src, 4);
3298     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3299 
3300     address copyfunc_addr = StubRoutines::generic_arraycopy();
3301     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3302 
3303     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3304 #ifdef _LP64
3305     // The arguments are in java calling convention so we can trivially shift them to C
3306     // convention
3307     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3308     __ mov(c_rarg0, j_rarg0);
3309     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3310     __ mov(c_rarg1, j_rarg1);
3311     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3312     __ mov(c_rarg2, j_rarg2);
3313     assert_different_registers(c_rarg3, j_rarg4);
3314     __ mov(c_rarg3, j_rarg3);
3315 #ifdef _WIN64
3316     // Allocate abi space for args but be sure to keep stack aligned
3317     __ subptr(rsp, 6*wordSize);
3318     store_parameter(j_rarg4, 4);
3319 #ifndef PRODUCT
3320     if (PrintC1Statistics) {
3321       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3322     }
3323 #endif
3324     __ call(RuntimeAddress(copyfunc_addr));
3325     __ addptr(rsp, 6*wordSize);
3326 #else
3327     __ mov(c_rarg4, j_rarg4);
3328 #ifndef PRODUCT
3329     if (PrintC1Statistics) {
3330       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3331     }
3332 #endif
3333     __ call(RuntimeAddress(copyfunc_addr));
3334 #endif // _WIN64
3335 #else
3336     __ push(length);
3337     __ push(dst_pos);
3338     __ push(dst);
3339     __ push(src_pos);
3340     __ push(src);
3341 
3342 #ifndef PRODUCT
3343     if (PrintC1Statistics) {
3344       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3345     }
3346 #endif
3347     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3348 
3349 #endif // _LP64
3350 
3351     __ cmpl(rax, 0);
3352     __ jcc(Assembler::equal, *stub->continuation());
3353 
3354     __ mov(tmp, rax);
3355     __ xorl(tmp, -1);
3356 
3357     // Reload values from the stack so they are where the stub
3358     // expects them.
3359     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3360     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3361     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3362     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3363     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3364 
3365     __ subl(length, tmp);
3366     __ addl(src_pos, tmp);
3367     __ addl(dst_pos, tmp);
3368     __ jmp(*stub->entry());
3369 
3370     __ bind(*stub->continuation());
3371     return;
3372   }
3373 
3374   // Handle inline type arrays
3375   if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
3376     arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
3377   }
3378   if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
3379     arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
3380   }
3381 
3382   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3383 
3384   int elem_size = type2aelembytes(basic_type);
3385   Address::ScaleFactor scale;
3386 
3387   switch (elem_size) {
3388     case 1 :
3389       scale = Address::times_1;
3390       break;
3391     case 2 :
3392       scale = Address::times_2;
3393       break;
3394     case 4 :
3395       scale = Address::times_4;
3396       break;
3397     case 8 :
3398       scale = Address::times_8;
3399       break;
3400     default:
3401       scale = Address::no_scale;
3402       ShouldNotReachHere();
3403   }
3404 
3405   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3406   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3407   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3408   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3409 
3410   // length and pos's are all sign extended at this point on 64bit
3411 
3412   // test for NULL
3413   if (flags & LIR_OpArrayCopy::src_null_check) {
3414     __ testptr(src, src);
3415     __ jcc(Assembler::zero, *stub->entry());
3416   }
3417   if (flags & LIR_OpArrayCopy::dst_null_check) {
3418     __ testptr(dst, dst);
3419     __ jcc(Assembler::zero, *stub->entry());
3420   }
3421 
3422   // If the compiler was not able to prove that exact type of the source or the destination
3423   // of the arraycopy is an array type, check at runtime if the source or the destination is
3424   // an instance type.
3425   if (flags & LIR_OpArrayCopy::type_check) {
3426     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3427       __ load_klass(tmp, dst, tmp_load_klass);
3428       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3429       __ jcc(Assembler::greaterEqual, *stub->entry());
3430     }
3431 
3432     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3433       __ load_klass(tmp, src, tmp_load_klass);
3434       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3435       __ jcc(Assembler::greaterEqual, *stub->entry());
3436     }
3437   }
3438 
3439   // check if negative
3440   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3441     __ testl(src_pos, src_pos);
3442     __ jcc(Assembler::less, *stub->entry());
3443   }
3444   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3445     __ testl(dst_pos, dst_pos);
3446     __ jcc(Assembler::less, *stub->entry());
3447   }
3448 
3449   if (flags & LIR_OpArrayCopy::src_range_check) {
3450     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3451     __ cmpl(tmp, src_length_addr);
3452     __ jcc(Assembler::above, *stub->entry());
3453   }
3454   if (flags & LIR_OpArrayCopy::dst_range_check) {
3455     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3456     __ cmpl(tmp, dst_length_addr);
3457     __ jcc(Assembler::above, *stub->entry());
3458   }
3459 
3460   if (flags & LIR_OpArrayCopy::length_positive_check) {
3461     __ testl(length, length);
3462     __ jcc(Assembler::less, *stub->entry());
3463   }
3464 
3465 #ifdef _LP64
3466   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3467   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3468 #endif
3469 
3470   if (flags & LIR_OpArrayCopy::type_check) {
3471     // We don't know the array types are compatible
3472     if (basic_type != T_OBJECT) {
3473       // Simple test for basic type arrays
3474       if (UseCompressedClassPointers) {
3475         __ movl(tmp, src_klass_addr);
3476         __ cmpl(tmp, dst_klass_addr);
3477       } else {
3478         __ movptr(tmp, src_klass_addr);
3479         __ cmpptr(tmp, dst_klass_addr);
3480       }
3481       __ jcc(Assembler::notEqual, *stub->entry());
3482     } else {
3483       // For object arrays, if src is a sub class of dst then we can
3484       // safely do the copy.
3485       Label cont, slow;
3486 
3487       __ push(src);
3488       __ push(dst);
3489 
3490       __ load_klass(src, src, tmp_load_klass);
3491       __ load_klass(dst, dst, tmp_load_klass);
3492 
3493       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3494 
3495       __ push(src);
3496       __ push(dst);
3497       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3498       __ pop(dst);
3499       __ pop(src);
3500 
3501       __ cmpl(src, 0);
3502       __ jcc(Assembler::notEqual, cont);
3503 
3504       __ bind(slow);
3505       __ pop(dst);
3506       __ pop(src);
3507 
3508       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3509       if (copyfunc_addr != NULL) { // use stub if available
3510         // src is not a sub class of dst so we have to do a
3511         // per-element check.
3512 
3513         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3514         if ((flags & mask) != mask) {
3515           // Check that at least both of them object arrays.
3516           assert(flags & mask, "one of the two should be known to be an object array");
3517 
3518           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3519             __ load_klass(tmp, src, tmp_load_klass);
3520           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3521             __ load_klass(tmp, dst, tmp_load_klass);
3522           }
3523           int lh_offset = in_bytes(Klass::layout_helper_offset());
3524           Address klass_lh_addr(tmp, lh_offset);
3525           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3526           __ cmpl(klass_lh_addr, objArray_lh);
3527           __ jcc(Assembler::notEqual, *stub->entry());
3528         }
3529 
3530        // Spill because stubs can use any register they like and it's
3531        // easier to restore just those that we care about.
3532        store_parameter(dst, 0);
3533        store_parameter(dst_pos, 1);
3534        store_parameter(length, 2);
3535        store_parameter(src_pos, 3);
3536        store_parameter(src, 4);
3537 
3538 #ifndef _LP64
3539         __ movptr(tmp, dst_klass_addr);
3540         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3541         __ push(tmp);
3542         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3543         __ push(tmp);
3544         __ push(length);
3545         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3546         __ push(tmp);
3547         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3548         __ push(tmp);
3549 
3550         __ call_VM_leaf(copyfunc_addr, 5);
3551 #else
3552         __ movl2ptr(length, length); //higher 32bits must be null
3553 
3554         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3555         assert_different_registers(c_rarg0, dst, dst_pos, length);
3556         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3557         assert_different_registers(c_rarg1, dst, length);
3558 
3559         __ mov(c_rarg2, length);
3560         assert_different_registers(c_rarg2, dst);
3561 
3562 #ifdef _WIN64
3563         // Allocate abi space for args but be sure to keep stack aligned
3564         __ subptr(rsp, 6*wordSize);
3565         __ load_klass(c_rarg3, dst, tmp_load_klass);
3566         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3567         store_parameter(c_rarg3, 4);
3568         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3569         __ call(RuntimeAddress(copyfunc_addr));
3570         __ addptr(rsp, 6*wordSize);
3571 #else
3572         __ load_klass(c_rarg4, dst, tmp_load_klass);
3573         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3574         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3575         __ call(RuntimeAddress(copyfunc_addr));
3576 #endif
3577 
3578 #endif
3579 
3580 #ifndef PRODUCT
3581         if (PrintC1Statistics) {
3582           Label failed;
3583           __ testl(rax, rax);
3584           __ jcc(Assembler::notZero, failed);
3585           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3586           __ bind(failed);
3587         }
3588 #endif
3589 
3590         __ testl(rax, rax);
3591         __ jcc(Assembler::zero, *stub->continuation());
3592 
3593 #ifndef PRODUCT
3594         if (PrintC1Statistics) {
3595           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3596         }
3597 #endif
3598 
3599         __ mov(tmp, rax);
3600 
3601         __ xorl(tmp, -1);
3602 
3603         // Restore previously spilled arguments
3604         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3605         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3606         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3607         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3608         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3609 
3610 
3611         __ subl(length, tmp);
3612         __ addl(src_pos, tmp);
3613         __ addl(dst_pos, tmp);
3614       }
3615 
3616       __ jmp(*stub->entry());
3617 
3618       __ bind(cont);
3619       __ pop(dst);
3620       __ pop(src);
3621     }
3622   }
3623 
3624 #ifdef ASSERT
3625   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3626     // Sanity check the known type with the incoming class.  For the
3627     // primitive case the types must match exactly with src.klass and
3628     // dst.klass each exactly matching the default type.  For the
3629     // object array case, if no type check is needed then either the
3630     // dst type is exactly the expected type and the src type is a
3631     // subtype which we can't check or src is the same array as dst
3632     // but not necessarily exactly of type default_type.
3633     Label known_ok, halt;
3634     __ mov_metadata(tmp, default_type->constant_encoding());
3635 #ifdef _LP64
3636     if (UseCompressedClassPointers) {
3637       __ encode_klass_not_null(tmp, rscratch1);
3638     }
3639 #endif
3640 
3641     if (basic_type != T_OBJECT) {
3642 
3643       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3644       else                   __ cmpptr(tmp, dst_klass_addr);
3645       __ jcc(Assembler::notEqual, halt);
3646       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3647       else                   __ cmpptr(tmp, src_klass_addr);
3648       __ jcc(Assembler::equal, known_ok);
3649     } else {
3650       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3651       else                   __ cmpptr(tmp, dst_klass_addr);
3652       __ jcc(Assembler::equal, known_ok);
3653       __ cmpptr(src, dst);
3654       __ jcc(Assembler::equal, known_ok);
3655     }
3656     __ bind(halt);
3657     __ stop("incorrect type information in arraycopy");
3658     __ bind(known_ok);
3659   }
3660 #endif
3661 
3662 #ifndef PRODUCT
3663   if (PrintC1Statistics) {
3664     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3665   }
3666 #endif
3667 
3668 #ifdef _LP64
3669   assert_different_registers(c_rarg0, dst, dst_pos, length);
3670   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3671   assert_different_registers(c_rarg1, length);
3672   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3673   __ mov(c_rarg2, length);
3674 
3675 #else
3676   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3677   store_parameter(tmp, 0);
3678   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3679   store_parameter(tmp, 1);
3680   store_parameter(length, 2);
3681 #endif // _LP64
3682 
3683   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3684   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3685   const char *name;
3686   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3687   __ call_VM_leaf(entry, 0);
3688 
3689   __ bind(*stub->continuation());
3690 }
3691 
3692 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3693   assert(op->crc()->is_single_cpu(),  "crc must be register");
3694   assert(op->val()->is_single_cpu(),  "byte value must be register");
3695   assert(op->result_opr()->is_single_cpu(), "result must be register");
3696   Register crc = op->crc()->as_register();
3697   Register val = op->val()->as_register();
3698   Register res = op->result_opr()->as_register();
3699 
3700   assert_different_registers(val, crc, res);
3701 
3702   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3703   __ notl(crc); // ~crc
3704   __ update_byte_crc32(crc, val, res);
3705   __ notl(crc); // ~crc
3706   __ mov(res, crc);
3707 }
3708 
3709 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3710   Register obj = op->obj_opr()->as_register();  // may not be an oop
3711   Register hdr = op->hdr_opr()->as_register();
3712   Register lock = op->lock_opr()->as_register();
3713   if (UseHeavyMonitors) {
3714     __ jmp(*op->stub()->entry());
3715   } else if (op->code() == lir_lock) {
3716     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3717     // add debug info for NullPointerException only if one is possible
3718     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
3719     if (op->info() != NULL) {
3720       add_debug_info_for_null_check(null_check_offset, op->info());
3721     }
3722     // done
3723   } else if (op->code() == lir_unlock) {
3724     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3725     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3726   } else {
3727     Unimplemented();
3728   }
3729   __ bind(*op->stub()->continuation());
3730 }
3731 
3732 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3733   Register obj = op->obj()->as_pointer_register();
3734   Register result = op->result_opr()->as_pointer_register();
3735 
3736   CodeEmitInfo* info = op->info();
3737   if (info != NULL) {
3738     add_debug_info_for_null_check_here(info);
3739   }
3740 
3741 #ifdef _LP64
3742   if (UseCompressedClassPointers) {
3743     __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3744     __ decode_klass_not_null(result, rscratch1);
3745   } else
3746 #endif
3747     __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3748 }
3749 
3750 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3751   ciMethod* method = op->profiled_method();
3752   int bci          = op->profiled_bci();
3753   ciMethod* callee = op->profiled_callee();
3754   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3755 
3756   // Update counter for all call types
3757   ciMethodData* md = method->method_data_or_null();
3758   assert(md != NULL, "Sanity");
3759   ciProfileData* data = md->bci_to_data(bci);
3760   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3761   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3762   Register mdo  = op->mdo()->as_register();
3763   __ mov_metadata(mdo, md->constant_encoding());
3764   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3765   // Perform additional virtual call profiling for invokevirtual and
3766   // invokeinterface bytecodes
3767   if (op->should_profile_receiver_type()) {
3768     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3769     Register recv = op->recv()->as_register();
3770     assert_different_registers(mdo, recv);
3771     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3772     ciKlass* known_klass = op->known_holder();
3773     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3774       // We know the type that will be seen at this call site; we can
3775       // statically update the MethodData* rather than needing to do
3776       // dynamic tests on the receiver type
3777 
3778       // NOTE: we should probably put a lock around this search to
3779       // avoid collisions by concurrent compilations
3780       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3781       uint i;
3782       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3783         ciKlass* receiver = vc_data->receiver(i);
3784         if (known_klass->equals(receiver)) {
3785           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3786           __ addptr(data_addr, DataLayout::counter_increment);
3787           return;
3788         }
3789       }
3790 
3791       // Receiver type not found in profile data; select an empty slot
3792 
3793       // Note that this is less efficient than it should be because it
3794       // always does a write to the receiver part of the
3795       // VirtualCallData rather than just the first time
3796       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3797         ciKlass* receiver = vc_data->receiver(i);
3798         if (receiver == NULL) {
3799           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3800           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3801           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3802           __ addptr(data_addr, DataLayout::counter_increment);
3803           return;
3804         }
3805       }
3806     } else {
3807       __ load_klass(recv, recv, tmp_load_klass);
3808       Label update_done;
3809       type_profile_helper(mdo, md, data, recv, &update_done);
3810       // Receiver did not match any saved receiver and there is no empty row for it.
3811       // Increment total counter to indicate polymorphic case.
3812       __ addptr(counter_addr, DataLayout::counter_increment);
3813 
3814       __ bind(update_done);
3815     }
3816   } else {
3817     // Static call
3818     __ addptr(counter_addr, DataLayout::counter_increment);
3819   }
3820 }
3821 
3822 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3823   Register obj = op->obj()->as_register();
3824   Register tmp = op->tmp()->as_pointer_register();
3825   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3826   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3827   ciKlass* exact_klass = op->exact_klass();
3828   intptr_t current_klass = op->current_klass();
3829   bool not_null = op->not_null();
3830   bool no_conflict = op->no_conflict();
3831 
3832   Label update, next, none;
3833 
3834   bool do_null = !not_null;
3835   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3836   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3837 
3838   assert(do_null || do_update, "why are we here?");
3839   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3840 
3841   __ verify_oop(obj);
3842 
3843   if (tmp != obj) {
3844     __ mov(tmp, obj);
3845   }
3846   if (do_null) {
3847     __ testptr(tmp, tmp);
3848     __ jccb(Assembler::notZero, update);
3849     if (!TypeEntries::was_null_seen(current_klass)) {
3850       __ orptr(mdo_addr, TypeEntries::null_seen);
3851     }
3852     if (do_update) {
3853 #ifndef ASSERT
3854       __ jmpb(next);
3855     }
3856 #else
3857       __ jmp(next);
3858     }
3859   } else {
3860     __ testptr(tmp, tmp);
3861     __ jcc(Assembler::notZero, update);
3862     __ stop("unexpect null obj");
3863 #endif
3864   }
3865 
3866   __ bind(update);
3867 
3868   if (do_update) {
3869 #ifdef ASSERT
3870     if (exact_klass != NULL) {
3871       Label ok;
3872       __ load_klass(tmp, tmp, tmp_load_klass);
3873       __ push(tmp);
3874       __ mov_metadata(tmp, exact_klass->constant_encoding());
3875       __ cmpptr(tmp, Address(rsp, 0));
3876       __ jcc(Assembler::equal, ok);
3877       __ stop("exact klass and actual klass differ");
3878       __ bind(ok);
3879       __ pop(tmp);
3880     }
3881 #endif
3882     if (!no_conflict) {
3883       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3884         if (exact_klass != NULL) {
3885           __ mov_metadata(tmp, exact_klass->constant_encoding());
3886         } else {
3887           __ load_klass(tmp, tmp, tmp_load_klass);
3888         }
3889 
3890         __ xorptr(tmp, mdo_addr);
3891         __ testptr(tmp, TypeEntries::type_klass_mask);
3892         // klass seen before, nothing to do. The unknown bit may have been
3893         // set already but no need to check.
3894         __ jccb(Assembler::zero, next);
3895 
3896         __ testptr(tmp, TypeEntries::type_unknown);
3897         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3898 
3899         if (TypeEntries::is_type_none(current_klass)) {
3900           __ cmpptr(mdo_addr, 0);
3901           __ jccb(Assembler::equal, none);
3902           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3903           __ jccb(Assembler::equal, none);
3904           // There is a chance that the checks above (re-reading profiling
3905           // data from memory) fail if another thread has just set the
3906           // profiling to this obj's klass
3907           __ xorptr(tmp, mdo_addr);
3908           __ testptr(tmp, TypeEntries::type_klass_mask);
3909           __ jccb(Assembler::zero, next);
3910         }
3911       } else {
3912         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3913                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3914 
3915         __ movptr(tmp, mdo_addr);
3916         __ testptr(tmp, TypeEntries::type_unknown);
3917         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3918       }
3919 
3920       // different than before. Cannot keep accurate profile.
3921       __ orptr(mdo_addr, TypeEntries::type_unknown);
3922 
3923       if (TypeEntries::is_type_none(current_klass)) {
3924         __ jmpb(next);
3925 
3926         __ bind(none);
3927         // first time here. Set profile type.
3928         __ movptr(mdo_addr, tmp);
3929       }
3930     } else {
3931       // There's a single possible klass at this profile point
3932       assert(exact_klass != NULL, "should be");
3933       if (TypeEntries::is_type_none(current_klass)) {
3934         __ mov_metadata(tmp, exact_klass->constant_encoding());
3935         __ xorptr(tmp, mdo_addr);
3936         __ testptr(tmp, TypeEntries::type_klass_mask);
3937 #ifdef ASSERT
3938         __ jcc(Assembler::zero, next);
3939 
3940         {
3941           Label ok;
3942           __ push(tmp);
3943           __ cmpptr(mdo_addr, 0);
3944           __ jcc(Assembler::equal, ok);
3945           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3946           __ jcc(Assembler::equal, ok);
3947           // may have been set by another thread
3948           __ mov_metadata(tmp, exact_klass->constant_encoding());
3949           __ xorptr(tmp, mdo_addr);
3950           __ testptr(tmp, TypeEntries::type_mask);
3951           __ jcc(Assembler::zero, ok);
3952 
3953           __ stop("unexpected profiling mismatch");
3954           __ bind(ok);
3955           __ pop(tmp);
3956         }
3957 #else
3958         __ jccb(Assembler::zero, next);
3959 #endif
3960         // first time here. Set profile type.
3961         __ movptr(mdo_addr, tmp);
3962       } else {
3963         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3964                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3965 
3966         __ movptr(tmp, mdo_addr);
3967         __ testptr(tmp, TypeEntries::type_unknown);
3968         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3969 
3970         __ orptr(mdo_addr, TypeEntries::type_unknown);
3971       }
3972     }
3973 
3974     __ bind(next);
3975   }
3976 }
3977 
3978 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3979   Register obj = op->obj()->as_register();
3980   Register tmp = op->tmp()->as_pointer_register();
3981   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3982   bool not_null = op->not_null();
3983   int flag = op->flag();
3984 
3985   Label not_inline_type;
3986   if (!not_null) {
3987     __ testptr(obj, obj);
3988     __ jccb(Assembler::zero, not_inline_type);
3989   }
3990 
3991   __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3992 
3993   __ orb(mdo_addr, flag);
3994 
3995   __ bind(not_inline_type);
3996 }
3997 
3998 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3999   Unimplemented();
4000 }
4001 
4002 
4003 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
4004   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
4005 }
4006 
4007 
4008 void LIR_Assembler::align_backward_branch_target() {
4009   __ align(BytesPerWord);
4010 }
4011 
4012 
4013 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
4014   if (left->is_single_cpu()) {
4015     __ negl(left->as_register());
4016     move_regs(left->as_register(), dest->as_register());
4017 
4018   } else if (left->is_double_cpu()) {
4019     Register lo = left->as_register_lo();
4020 #ifdef _LP64
4021     Register dst = dest->as_register_lo();
4022     __ movptr(dst, lo);
4023     __ negptr(dst);
4024 #else
4025     Register hi = left->as_register_hi();
4026     __ lneg(hi, lo);
4027     if (dest->as_register_lo() == hi) {
4028       assert(dest->as_register_hi() != lo, "destroying register");
4029       move_regs(hi, dest->as_register_hi());
4030       move_regs(lo, dest->as_register_lo());
4031     } else {
4032       move_regs(lo, dest->as_register_lo());
4033       move_regs(hi, dest->as_register_hi());
4034     }
4035 #endif // _LP64
4036 
4037   } else if (dest->is_single_xmm()) {
4038 #ifdef _LP64
4039     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4040       assert(tmp->is_valid(), "need temporary");
4041       assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
4042       __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
4043     }
4044     else
4045 #endif
4046     {
4047       assert(!tmp->is_valid(), "do not need temporary");
4048       if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
4049         __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
4050       }
4051       __ xorps(dest->as_xmm_float_reg(),
4052                ExternalAddress((address)float_signflip_pool));
4053     }
4054   } else if (dest->is_double_xmm()) {
4055 #ifdef _LP64
4056     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4057       assert(tmp->is_valid(), "need temporary");
4058       assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
4059       __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
4060     }
4061     else
4062 #endif
4063     {
4064       assert(!tmp->is_valid(), "do not need temporary");
4065       if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
4066         __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
4067       }
4068       __ xorpd(dest->as_xmm_double_reg(),
4069                ExternalAddress((address)double_signflip_pool));
4070     }
4071 #ifndef _LP64
4072   } else if (left->is_single_fpu() || left->is_double_fpu()) {
4073     assert(left->fpu() == 0, "arg must be on TOS");
4074     assert(dest->fpu() == 0, "dest must be TOS");
4075     __ fchs();
4076 #endif // !_LP64
4077 
4078   } else {
4079     ShouldNotReachHere();
4080   }
4081 }
4082 
4083 
4084 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
4085   assert(src->is_address(), "must be an address");
4086   assert(dest->is_register(), "must be a register");
4087 
4088   PatchingStub* patch = NULL;
4089   if (patch_code != lir_patch_none) {
4090     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
4091   }
4092 
4093   Register reg = dest->as_pointer_register();
4094   LIR_Address* addr = src->as_address_ptr();
4095   __ lea(reg, as_Address(addr));
4096 
4097   if (patch != NULL) {
4098     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
4099   }
4100 }
4101 
4102 
4103 
4104 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
4105   assert(!tmp->is_valid(), "don't need temporary");
4106   __ call(RuntimeAddress(dest));
4107   if (info != NULL) {
4108     add_call_info_here(info);
4109   }
4110 }
4111 
4112 
4113 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
4114   assert(type == T_LONG, "only for volatile long fields");
4115 
4116   if (info != NULL) {
4117     add_debug_info_for_null_check_here(info);
4118   }
4119 
4120   if (src->is_double_xmm()) {
4121     if (dest->is_double_cpu()) {
4122 #ifdef _LP64
4123       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
4124 #else
4125       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
4126       __ psrlq(src->as_xmm_double_reg(), 32);
4127       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
4128 #endif // _LP64
4129     } else if (dest->is_double_stack()) {
4130       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
4131     } else if (dest->is_address()) {
4132       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
4133     } else {
4134       ShouldNotReachHere();
4135     }
4136 
4137   } else if (dest->is_double_xmm()) {
4138     if (src->is_double_stack()) {
4139       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
4140     } else if (src->is_address()) {
4141       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
4142     } else {
4143       ShouldNotReachHere();
4144     }
4145 
4146 #ifndef _LP64
4147   } else if (src->is_double_fpu()) {
4148     assert(src->fpu_regnrLo() == 0, "must be TOS");
4149     if (dest->is_double_stack()) {
4150       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
4151     } else if (dest->is_address()) {
4152       __ fistp_d(as_Address(dest->as_address_ptr()));
4153     } else {
4154       ShouldNotReachHere();
4155     }
4156 
4157   } else if (dest->is_double_fpu()) {
4158     assert(dest->fpu_regnrLo() == 0, "must be TOS");
4159     if (src->is_double_stack()) {
4160       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
4161     } else if (src->is_address()) {
4162       __ fild_d(as_Address(src->as_address_ptr()));
4163     } else {
4164       ShouldNotReachHere();
4165     }
4166 #endif // !_LP64
4167 
4168   } else {
4169     ShouldNotReachHere();
4170   }
4171 }
4172 
4173 #ifdef ASSERT
4174 // emit run-time assertion
4175 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
4176   assert(op->code() == lir_assert, "must be");
4177 
4178   if (op->in_opr1()->is_valid()) {
4179     assert(op->in_opr2()->is_valid(), "both operands must be valid");
4180     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
4181   } else {
4182     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
4183     assert(op->condition() == lir_cond_always, "no other conditions allowed");
4184   }
4185 
4186   Label ok;
4187   if (op->condition() != lir_cond_always) {
4188     Assembler::Condition acond = Assembler::zero;
4189     switch (op->condition()) {
4190       case lir_cond_equal:        acond = Assembler::equal;       break;
4191       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
4192       case lir_cond_less:         acond = Assembler::less;        break;
4193       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
4194       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
4195       case lir_cond_greater:      acond = Assembler::greater;     break;
4196       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
4197       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
4198       default:                    ShouldNotReachHere();
4199     }
4200     __ jcc(acond, ok);
4201   }
4202   if (op->halt()) {
4203     const char* str = __ code_string(op->msg());
4204     __ stop(str);
4205   } else {
4206     breakpoint();
4207   }
4208   __ bind(ok);
4209 }
4210 #endif
4211 
4212 void LIR_Assembler::membar() {
4213   // QQQ sparc TSO uses this,
4214   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4215 }
4216 
4217 void LIR_Assembler::membar_acquire() {
4218   // No x86 machines currently require load fences
4219 }
4220 
4221 void LIR_Assembler::membar_release() {
4222   // No x86 machines currently require store fences
4223 }
4224 
4225 void LIR_Assembler::membar_loadload() {
4226   // no-op
4227   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4228 }
4229 
4230 void LIR_Assembler::membar_storestore() {
4231   // no-op
4232   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4233 }
4234 
4235 void LIR_Assembler::membar_loadstore() {
4236   // no-op
4237   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4238 }
4239 
4240 void LIR_Assembler::membar_storeload() {
4241   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4242 }
4243 
4244 void LIR_Assembler::on_spin_wait() {
4245   __ pause ();
4246 }
4247 
4248 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4249   assert(result_reg->is_register(), "check");
4250 #ifdef _LP64
4251   // __ get_thread(result_reg->as_register_lo());
4252   __ mov(result_reg->as_register(), r15_thread);
4253 #else
4254   __ get_thread(result_reg->as_register());
4255 #endif // _LP64
4256 }
4257 
4258 void LIR_Assembler::check_orig_pc() {
4259   __ cmpptr(frame_map()->address_for_orig_pc_addr(), (int32_t)NULL_WORD);
4260 }
4261 
4262 void LIR_Assembler::peephole(LIR_List*) {
4263   // do nothing for now
4264 }
4265 
4266 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4267   assert(data == dest, "xchg/xadd uses only 2 operands");
4268 
4269   if (data->type() == T_INT) {
4270     if (code == lir_xadd) {
4271       __ lock();
4272       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4273     } else {
4274       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4275     }
4276   } else if (data->is_oop()) {
4277     assert (code == lir_xchg, "xadd for oops");
4278     Register obj = data->as_register();
4279 #ifdef _LP64
4280     if (UseCompressedOops) {
4281       __ encode_heap_oop(obj);
4282       __ xchgl(obj, as_Address(src->as_address_ptr()));
4283       __ decode_heap_oop(obj);
4284     } else {
4285       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4286     }
4287 #else
4288     __ xchgl(obj, as_Address(src->as_address_ptr()));
4289 #endif
4290   } else if (data->type() == T_LONG) {
4291 #ifdef _LP64
4292     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4293     if (code == lir_xadd) {
4294       __ lock();
4295       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4296     } else {
4297       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4298     }
4299 #else
4300     ShouldNotReachHere();
4301 #endif
4302   } else {
4303     ShouldNotReachHere();
4304   }
4305 }
4306 
4307 #undef __