1 /*
2 * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "compiler/oopMap.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_x86.hpp"
41 #include "oops/oop.inline.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register IC_Klass = rax; // where the IC klass is cached
78 const Register SYNC_header = rax; // synchronization header
79 const Register SHIFT_count = rcx; // where count for shift operations must be
80
81 #define __ _masm->
82
83
84 static void select_different_registers(Register preserve,
85 Register extra,
86 Register &tmp1,
87 Register &tmp2) {
88 if (tmp1 == preserve) {
89 assert_different_registers(tmp1, tmp2, extra);
90 tmp1 = extra;
91 } else if (tmp2 == preserve) {
92 assert_different_registers(tmp1, tmp2, extra);
93 tmp2 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2);
96 }
97
98
99
100 static void select_different_registers(Register preserve,
101 Register extra,
102 Register &tmp1,
103 Register &tmp2,
104 Register &tmp3) {
105 if (tmp1 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp1 = extra;
108 } else if (tmp2 == preserve) {
109 assert_different_registers(tmp1, tmp2, tmp3, extra);
110 tmp2 = extra;
111 } else if (tmp3 == preserve) {
112 assert_different_registers(tmp1, tmp2, tmp3, extra);
113 tmp3 = extra;
114 }
115 assert_different_registers(preserve, tmp1, tmp2, tmp3);
116 }
117
118
119
120 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
121 if (opr->is_constant()) {
122 LIR_Const* constant = opr->as_constant_ptr();
123 switch (constant->type()) {
124 case T_INT: {
125 return true;
126 }
127
128 default:
129 return false;
130 }
131 }
132 return false;
133 }
134
135
136 LIR_Opr LIR_Assembler::receiverOpr() {
137 return FrameMap::receiver_opr;
138 }
139
140 LIR_Opr LIR_Assembler::osrBufferPointer() {
141 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
142 }
143
144 //--------------fpu register translations-----------------------
145
146
147 address LIR_Assembler::float_constant(float f) {
148 address const_addr = __ float_constant(f);
149 if (const_addr == nullptr) {
150 bailout("const section overflow");
151 return __ code()->consts()->start();
152 } else {
153 return const_addr;
154 }
155 }
156
157
158 address LIR_Assembler::double_constant(double d) {
159 address const_addr = __ double_constant(d);
160 if (const_addr == nullptr) {
161 bailout("const section overflow");
162 return __ code()->consts()->start();
163 } else {
164 return const_addr;
165 }
166 }
167
168 #ifndef _LP64
169 void LIR_Assembler::fpop() {
170 __ fpop();
171 }
172
173 void LIR_Assembler::fxch(int i) {
174 __ fxch(i);
175 }
176
177 void LIR_Assembler::fld(int i) {
178 __ fld_s(i);
179 }
180
181 void LIR_Assembler::ffree(int i) {
182 __ ffree(i);
183 }
184 #endif // !_LP64
185
186 void LIR_Assembler::breakpoint() {
187 __ int3();
188 }
189
190 void LIR_Assembler::push(LIR_Opr opr) {
191 if (opr->is_single_cpu()) {
192 __ push_reg(opr->as_register());
193 } else if (opr->is_double_cpu()) {
194 NOT_LP64(__ push_reg(opr->as_register_hi()));
195 __ push_reg(opr->as_register_lo());
196 } else if (opr->is_stack()) {
197 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
198 } else if (opr->is_constant()) {
199 LIR_Const* const_opr = opr->as_constant_ptr();
200 if (const_opr->type() == T_OBJECT || const_opr->type() == T_PRIMITIVE_OBJECT) {
201 __ push_oop(const_opr->as_jobject(), rscratch1);
202 } else if (const_opr->type() == T_INT) {
203 __ push_jint(const_opr->as_jint());
204 } else {
205 ShouldNotReachHere();
206 }
207
208 } else {
209 ShouldNotReachHere();
210 }
211 }
212
213 void LIR_Assembler::pop(LIR_Opr opr) {
214 if (opr->is_single_cpu()) {
215 __ pop_reg(opr->as_register());
216 } else {
217 ShouldNotReachHere();
218 }
219 }
220
221 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
222 return addr->base()->is_illegal() && addr->index()->is_illegal();
223 }
224
225 //-------------------------------------------
226
227 Address LIR_Assembler::as_Address(LIR_Address* addr) {
228 return as_Address(addr, rscratch1);
229 }
230
231 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
232 if (addr->base()->is_illegal()) {
233 assert(addr->index()->is_illegal(), "must be illegal too");
234 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
235 if (! __ reachable(laddr)) {
236 __ movptr(tmp, laddr.addr());
237 Address res(tmp, 0);
238 return res;
239 } else {
240 return __ as_Address(laddr);
241 }
242 }
243
244 Register base = addr->base()->as_pointer_register();
245
246 if (addr->index()->is_illegal()) {
247 return Address( base, addr->disp());
248 } else if (addr->index()->is_cpu_register()) {
249 Register index = addr->index()->as_pointer_register();
250 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
251 } else if (addr->index()->is_constant()) {
252 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
253 assert(Assembler::is_simm32(addr_offset), "must be");
254
255 return Address(base, addr_offset);
256 } else {
257 Unimplemented();
258 return Address();
259 }
260 }
261
262
263 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
264 Address base = as_Address(addr);
265 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
266 }
267
268
269 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
270 return as_Address(addr);
271 }
272
273
274 void LIR_Assembler::osr_entry() {
275 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
276 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
277 ValueStack* entry_state = osr_entry->state();
278 int number_of_locks = entry_state->locks_size();
279
280 // we jump here if osr happens with the interpreter
281 // state set up to continue at the beginning of the
282 // loop that triggered osr - in particular, we have
283 // the following registers setup:
284 //
285 // rcx: osr buffer
286 //
287
288 // build frame
289 ciMethod* m = compilation()->method();
290 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
291
292 // OSR buffer is
293 //
294 // locals[nlocals-1..0]
295 // monitors[0..number_of_locks]
296 //
297 // locals is a direct copy of the interpreter frame so in the osr buffer
298 // so first slot in the local array is the last local from the interpreter
299 // and last slot is local[0] (receiver) from the interpreter
300 //
301 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
302 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
303 // in the interpreter frame (the method lock if a sync method)
304
305 // Initialize monitors in the compiled activation.
306 // rcx: pointer to osr buffer
307 //
308 // All other registers are dead at this point and the locals will be
309 // copied into place by code emitted in the IR.
310
311 Register OSR_buf = osrBufferPointer()->as_pointer_register();
312 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
313 int monitor_offset = BytesPerWord * method()->max_locals() +
314 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
315 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
316 // the OSR buffer using 2 word entries: first the lock and then
317 // the oop.
318 for (int i = 0; i < number_of_locks; i++) {
319 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
320 #ifdef ASSERT
321 // verify the interpreter's monitor has a non-null object
322 {
323 Label L;
324 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
325 __ jcc(Assembler::notZero, L);
326 __ stop("locked object is null");
327 __ bind(L);
328 }
329 #endif
330 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
331 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
333 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
334 }
335 }
336 }
337
338
339 // inline cache check; done before the frame is built.
340 int LIR_Assembler::check_icache() {
341 Register receiver = FrameMap::receiver_opr->as_register();
342 Register ic_klass = IC_Klass;
343 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
344 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
345 if (!do_post_padding) {
346 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
347 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
348 }
349 int offset = __ offset();
350 __ inline_cache_check(receiver, IC_Klass);
351 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
352 if (do_post_padding) {
353 // force alignment after the cache check.
354 // It's been verified to be aligned if !VerifyOops
355 __ align(CodeEntryAlignment);
356 }
357 return offset;
358 }
359
360 void LIR_Assembler::clinit_barrier(ciMethod* method) {
361 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
362 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
363
364 Label L_skip_barrier;
365 Register klass = rscratch1;
366 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
367 assert(thread != noreg, "x86_32 not implemented");
368
369 __ mov_metadata(klass, method->holder()->constant_encoding());
370 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
371
372 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
373
374 __ bind(L_skip_barrier);
375 }
376
377 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
378 jobject o = nullptr;
379 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
380 __ movoop(reg, o);
381 patching_epilog(patch, lir_patch_normal, reg, info);
382 }
383
384 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
385 Metadata* o = nullptr;
386 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
387 __ mov_metadata(reg, o);
388 patching_epilog(patch, lir_patch_normal, reg, info);
389 }
390
391 // This specifies the rsp decrement needed to build the frame
392 int LIR_Assembler::initial_frame_size_in_bytes() const {
393 // if rounding, must let FrameMap know!
394
395 // The frame_map records size in slots (32bit word)
396
397 // subtract two words to account for return address and link
398 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
399 }
400
401
402 int LIR_Assembler::emit_exception_handler() {
403 // generate code for exception handler
404 address handler_base = __ start_a_stub(exception_handler_size());
405 if (handler_base == nullptr) {
406 // not enough space left for the handler
407 bailout("exception handler overflow");
408 return -1;
409 }
410
411 int offset = code_offset();
412
413 // the exception oop and pc are in rax, and rdx
414 // no other registers need to be preserved, so invalidate them
415 __ invalidate_registers(false, true, true, false, true, true);
416
417 // check that there is really an exception
418 __ verify_not_null_oop(rax);
419
420 // search an exception handler (rax: exception oop, rdx: throwing pc)
421 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
422 __ should_not_reach_here();
423 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
424 __ end_a_stub();
425
426 return offset;
427 }
428
429
430 // Emit the code to remove the frame from the stack in the exception
431 // unwind path.
432 int LIR_Assembler::emit_unwind_handler() {
433 #ifndef PRODUCT
434 if (CommentedAssembly) {
435 _masm->block_comment("Unwind handler");
436 }
437 #endif
438
439 int offset = code_offset();
440
441 // Fetch the exception from TLS and clear out exception related thread state
442 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
443 NOT_LP64(__ get_thread(thread));
444 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
445 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
446 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
447
448 __ bind(_unwind_handler_entry);
449 __ verify_not_null_oop(rax);
450 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
451 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
452 }
453
454 // Perform needed unlocking
455 MonitorExitStub* stub = nullptr;
456 if (method()->is_synchronized()) {
457 monitor_address(0, FrameMap::rax_opr);
458 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
459 if (LockingMode == LM_MONITOR) {
460 __ jmp(*stub->entry());
461 } else {
462 __ unlock_object(rdi, rsi, rax, *stub->entry());
463 }
464 __ bind(*stub->continuation());
465 }
466
467 if (compilation()->env()->dtrace_method_probes()) {
468 #ifdef _LP64
469 __ mov(rdi, r15_thread);
470 __ mov_metadata(rsi, method()->constant_encoding());
471 #else
472 __ get_thread(rax);
473 __ movptr(Address(rsp, 0), rax);
474 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
475 #endif
476 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
477 }
478
479 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
480 __ mov(rax, rbx); // Restore the exception
481 }
482
483 // remove the activation and dispatch to the unwind handler
484 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
485 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
486
487 // Emit the slow path assembly
488 if (stub != nullptr) {
489 stub->emit_code(this);
490 }
491
492 return offset;
493 }
494
495
496 int LIR_Assembler::emit_deopt_handler() {
497 // generate code for exception handler
498 address handler_base = __ start_a_stub(deopt_handler_size());
499 if (handler_base == nullptr) {
500 // not enough space left for the handler
501 bailout("deopt handler overflow");
502 return -1;
503 }
504
505 int offset = code_offset();
506 InternalAddress here(__ pc());
507
508 __ pushptr(here.addr(), rscratch1);
509 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
510 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
511 __ end_a_stub();
512
513 return offset;
514 }
515
516 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
517 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
518 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
519 assert(result->fpu() == 0, "result must already be on TOS");
520 }
521 if (InlineTypeReturnedAsFields) {
522 #ifndef _LP64
523 Unimplemented();
524 #endif
525 // Check if we are returning an non-null inline type and load its fields into registers
526 ciType* return_type = compilation()->method()->return_type();
527 if (return_type->is_inlinetype()) {
528 ciInlineKlass* vk = return_type->as_inline_klass();
529 if (vk->can_be_returned_as_fields()) {
530 address unpack_handler = vk->unpack_handler();
531 assert(unpack_handler != nullptr, "must be");
532 __ call(RuntimeAddress(unpack_handler));
533 }
534 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
535 Label skip;
536 __ test_oop_is_not_inline_type(rax, rscratch1, skip);
537
538 // Load fields from a buffered value with an inline class specific handler
539 __ load_klass(rdi, rax, rscratch1);
540 __ movptr(rdi, Address(rdi, InstanceKlass::adr_inlineklass_fixed_block_offset()));
541 __ movptr(rdi, Address(rdi, InlineKlass::unpack_handler_offset()));
542 // Unpack handler can be null if inline type is not scalarizable in returns
543 __ testptr(rdi, rdi);
544 __ jcc(Assembler::zero, skip);
545 __ call(rdi);
546
547 __ bind(skip);
548 }
549 // At this point, rax points to the value object (for interpreter or C1 caller).
550 // The fields of the object are copied into registers (for C2 caller).
551 }
552
553 // Pop the stack before the safepoint code
554 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
555
556 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
557 __ reserved_stack_check();
558 }
559
560 // Note: we do not need to round double result; float result has the right precision
561 // the poll sets the condition code, but no data registers
562
563 #ifdef _LP64
564 const Register thread = r15_thread;
565 #else
566 const Register thread = rbx;
567 __ get_thread(thread);
568 #endif
569 code_stub->set_safepoint_offset(__ offset());
570 __ relocate(relocInfo::poll_return_type);
571 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
572 __ ret(0);
573 }
574
575
576 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
577 return (__ store_inline_type_fields_to_buf(vk, false));
578 }
579
580 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
581 guarantee(info != nullptr, "Shouldn't be null");
582 int offset = __ offset();
583 #ifdef _LP64
584 const Register poll_addr = rscratch1;
585 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
586 #else
587 assert(tmp->is_cpu_register(), "needed");
588 const Register poll_addr = tmp->as_register();
589 __ get_thread(poll_addr);
590 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
591 #endif
592 add_debug_info_for_branch(info);
593 __ relocate(relocInfo::poll_type);
594 address pre_pc = __ pc();
595 __ testl(rax, Address(poll_addr, 0));
596 address post_pc = __ pc();
597 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
598 return offset;
599 }
600
601
602 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
603 if (from_reg != to_reg) __ mov(to_reg, from_reg);
604 }
605
606 void LIR_Assembler::swap_reg(Register a, Register b) {
607 __ xchgptr(a, b);
608 }
609
610
611 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
612 assert(src->is_constant(), "should not call otherwise");
613 assert(dest->is_register(), "should not call otherwise");
614 LIR_Const* c = src->as_constant_ptr();
615
616 switch (c->type()) {
617 case T_INT: {
618 assert(patch_code == lir_patch_none, "no patching handled here");
619 __ movl(dest->as_register(), c->as_jint());
620 break;
621 }
622
623 case T_ADDRESS: {
624 assert(patch_code == lir_patch_none, "no patching handled here");
625 __ movptr(dest->as_register(), c->as_jint());
626 break;
627 }
628
629 case T_LONG: {
630 assert(patch_code == lir_patch_none, "no patching handled here");
631 #ifdef _LP64
632 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
633 #else
634 __ movptr(dest->as_register_lo(), c->as_jint_lo());
635 __ movptr(dest->as_register_hi(), c->as_jint_hi());
636 #endif // _LP64
637 break;
638 }
639
640 case T_PRIMITIVE_OBJECT: // Fall through
641 case T_OBJECT: {
642 if (patch_code != lir_patch_none) {
643 jobject2reg_with_patching(dest->as_register(), info);
644 } else {
645 __ movoop(dest->as_register(), c->as_jobject());
646 }
647 break;
648 }
649
650 case T_METADATA: {
651 if (patch_code != lir_patch_none) {
652 klass2reg_with_patching(dest->as_register(), info);
653 } else {
654 __ mov_metadata(dest->as_register(), c->as_metadata());
655 }
656 break;
657 }
658
659 case T_FLOAT: {
660 if (dest->is_single_xmm()) {
661 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
662 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
663 } else {
664 __ movflt(dest->as_xmm_float_reg(),
665 InternalAddress(float_constant(c->as_jfloat())));
666 }
667 } else {
668 #ifndef _LP64
669 assert(dest->is_single_fpu(), "must be");
670 assert(dest->fpu_regnr() == 0, "dest must be TOS");
671 if (c->is_zero_float()) {
672 __ fldz();
673 } else if (c->is_one_float()) {
674 __ fld1();
675 } else {
676 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
677 }
678 #else
679 ShouldNotReachHere();
680 #endif // !_LP64
681 }
682 break;
683 }
684
685 case T_DOUBLE: {
686 if (dest->is_double_xmm()) {
687 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
688 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
689 } else {
690 __ movdbl(dest->as_xmm_double_reg(),
691 InternalAddress(double_constant(c->as_jdouble())));
692 }
693 } else {
694 #ifndef _LP64
695 assert(dest->is_double_fpu(), "must be");
696 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
697 if (c->is_zero_double()) {
698 __ fldz();
699 } else if (c->is_one_double()) {
700 __ fld1();
701 } else {
702 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
703 }
704 #else
705 ShouldNotReachHere();
706 #endif // !_LP64
707 }
708 break;
709 }
710
711 default:
712 ShouldNotReachHere();
713 }
714 }
715
716 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
717 assert(src->is_constant(), "should not call otherwise");
718 assert(dest->is_stack(), "should not call otherwise");
719 LIR_Const* c = src->as_constant_ptr();
720
721 switch (c->type()) {
722 case T_INT: // fall through
723 case T_FLOAT:
724 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
725 break;
726
727 case T_ADDRESS:
728 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
729 break;
730
731 case T_PRIMITIVE_OBJECT: // Fall through
732 case T_OBJECT:
733 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
734 break;
735
736 case T_LONG: // fall through
737 case T_DOUBLE:
738 #ifdef _LP64
739 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
740 lo_word_offset_in_bytes),
741 (intptr_t)c->as_jlong_bits(),
742 rscratch1);
743 #else
744 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
745 lo_word_offset_in_bytes), c->as_jint_lo_bits());
746 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
747 hi_word_offset_in_bytes), c->as_jint_hi_bits());
748 #endif // _LP64
749 break;
750
751 default:
752 ShouldNotReachHere();
753 }
754 }
755
756 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
757 assert(src->is_constant(), "should not call otherwise");
758 assert(dest->is_address(), "should not call otherwise");
759 LIR_Const* c = src->as_constant_ptr();
760 LIR_Address* addr = dest->as_address_ptr();
761
762 int null_check_here = code_offset();
763 switch (type) {
764 case T_INT: // fall through
765 case T_FLOAT:
766 __ movl(as_Address(addr), c->as_jint_bits());
767 break;
768
769 case T_ADDRESS:
770 __ movptr(as_Address(addr), c->as_jint_bits());
771 break;
772
773 case T_PRIMITIVE_OBJECT: // fall through
774 case T_OBJECT: // fall through
775 case T_ARRAY:
776 if (c->as_jobject() == nullptr) {
777 if (UseCompressedOops && !wide) {
778 __ movl(as_Address(addr), NULL_WORD);
779 } else {
780 #ifdef _LP64
781 __ xorptr(rscratch1, rscratch1);
782 null_check_here = code_offset();
783 __ movptr(as_Address(addr), rscratch1);
784 #else
785 __ movptr(as_Address(addr), NULL_WORD);
786 #endif
787 }
788 } else {
789 if (is_literal_address(addr)) {
790 ShouldNotReachHere();
791 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
792 } else {
793 #ifdef _LP64
794 __ movoop(rscratch1, c->as_jobject());
795 if (UseCompressedOops && !wide) {
796 __ encode_heap_oop(rscratch1);
797 null_check_here = code_offset();
798 __ movl(as_Address_lo(addr), rscratch1);
799 } else {
800 null_check_here = code_offset();
801 __ movptr(as_Address_lo(addr), rscratch1);
802 }
803 #else
804 __ movoop(as_Address(addr), c->as_jobject(), noreg);
805 #endif
806 }
807 }
808 break;
809
810 case T_LONG: // fall through
811 case T_DOUBLE:
812 #ifdef _LP64
813 if (is_literal_address(addr)) {
814 ShouldNotReachHere();
815 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
816 } else {
817 __ movptr(r10, (intptr_t)c->as_jlong_bits());
818 null_check_here = code_offset();
819 __ movptr(as_Address_lo(addr), r10);
820 }
821 #else
822 // Always reachable in 32bit so this doesn't produce useless move literal
823 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
824 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
825 #endif // _LP64
826 break;
827
828 case T_BOOLEAN: // fall through
829 case T_BYTE:
830 __ movb(as_Address(addr), c->as_jint() & 0xFF);
831 break;
832
833 case T_CHAR: // fall through
834 case T_SHORT:
835 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
836 break;
837
838 default:
839 ShouldNotReachHere();
840 };
841
842 if (info != nullptr) {
843 add_debug_info_for_null_check(null_check_here, info);
844 }
845 }
846
847
848 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
849 assert(src->is_register(), "should not call otherwise");
850 assert(dest->is_register(), "should not call otherwise");
851
852 // move between cpu-registers
853 if (dest->is_single_cpu()) {
854 #ifdef _LP64
855 if (src->type() == T_LONG) {
856 // Can do LONG -> OBJECT
857 move_regs(src->as_register_lo(), dest->as_register());
858 return;
859 }
860 #endif
861 assert(src->is_single_cpu(), "must match");
862 if (src->type() == T_OBJECT || src->type() == T_PRIMITIVE_OBJECT) {
863 __ verify_oop(src->as_register());
864 }
865 move_regs(src->as_register(), dest->as_register());
866
867 } else if (dest->is_double_cpu()) {
868 #ifdef _LP64
869 if (is_reference_type(src->type())) {
870 // Surprising to me but we can see move of a long to t_object
871 __ verify_oop(src->as_register());
872 move_regs(src->as_register(), dest->as_register_lo());
873 return;
874 }
875 #endif
876 assert(src->is_double_cpu(), "must match");
877 Register f_lo = src->as_register_lo();
878 Register f_hi = src->as_register_hi();
879 Register t_lo = dest->as_register_lo();
880 Register t_hi = dest->as_register_hi();
881 #ifdef _LP64
882 assert(f_hi == f_lo, "must be same");
883 assert(t_hi == t_lo, "must be same");
884 move_regs(f_lo, t_lo);
885 #else
886 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
887
888
889 if (f_lo == t_hi && f_hi == t_lo) {
890 swap_reg(f_lo, f_hi);
891 } else if (f_hi == t_lo) {
892 assert(f_lo != t_hi, "overwriting register");
893 move_regs(f_hi, t_hi);
894 move_regs(f_lo, t_lo);
895 } else {
896 assert(f_hi != t_lo, "overwriting register");
897 move_regs(f_lo, t_lo);
898 move_regs(f_hi, t_hi);
899 }
900 #endif // LP64
901
902 #ifndef _LP64
903 // special moves from fpu-register to xmm-register
904 // necessary for method results
905 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
906 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
907 __ fld_s(Address(rsp, 0));
908 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
909 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
910 __ fld_d(Address(rsp, 0));
911 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
912 __ fstp_s(Address(rsp, 0));
913 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
914 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
915 __ fstp_d(Address(rsp, 0));
916 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
917 #endif // !_LP64
918
919 // move between xmm-registers
920 } else if (dest->is_single_xmm()) {
921 assert(src->is_single_xmm(), "must match");
922 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
923 } else if (dest->is_double_xmm()) {
924 assert(src->is_double_xmm(), "must match");
925 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
926
927 #ifndef _LP64
928 // move between fpu-registers (no instruction necessary because of fpu-stack)
929 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
930 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
931 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
932 #endif // !_LP64
933
934 } else {
935 ShouldNotReachHere();
936 }
937 }
938
939 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
940 assert(src->is_register(), "should not call otherwise");
941 assert(dest->is_stack(), "should not call otherwise");
942
943 if (src->is_single_cpu()) {
944 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
945 if (is_reference_type(type)) {
946 __ verify_oop(src->as_register());
947 __ movptr (dst, src->as_register());
948 } else if (type == T_METADATA || type == T_ADDRESS) {
949 __ movptr (dst, src->as_register());
950 } else {
951 __ movl (dst, src->as_register());
952 }
953
954 } else if (src->is_double_cpu()) {
955 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
956 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
957 __ movptr (dstLO, src->as_register_lo());
958 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
959
960 } else if (src->is_single_xmm()) {
961 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
962 __ movflt(dst_addr, src->as_xmm_float_reg());
963
964 } else if (src->is_double_xmm()) {
965 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
966 __ movdbl(dst_addr, src->as_xmm_double_reg());
967
968 #ifndef _LP64
969 } else if (src->is_single_fpu()) {
970 assert(src->fpu_regnr() == 0, "argument must be on TOS");
971 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
972 if (pop_fpu_stack) __ fstp_s (dst_addr);
973 else __ fst_s (dst_addr);
974
975 } else if (src->is_double_fpu()) {
976 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
977 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
978 if (pop_fpu_stack) __ fstp_d (dst_addr);
979 else __ fst_d (dst_addr);
980 #endif // !_LP64
981
982 } else {
983 ShouldNotReachHere();
984 }
985 }
986
987
988 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
989 LIR_Address* to_addr = dest->as_address_ptr();
990 PatchingStub* patch = nullptr;
991 Register compressed_src = rscratch1;
992
993 if (is_reference_type(type)) {
994 __ verify_oop(src->as_register());
995 #ifdef _LP64
996 if (UseCompressedOops && !wide) {
997 __ movptr(compressed_src, src->as_register());
998 __ encode_heap_oop(compressed_src);
999 if (patch_code != lir_patch_none) {
1000 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1001 }
1002 }
1003 #endif
1004 }
1005
1006 if (patch_code != lir_patch_none) {
1007 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1008 Address toa = as_Address(to_addr);
1009 assert(toa.disp() != 0, "must have");
1010 }
1011
1012 int null_check_here = code_offset();
1013 switch (type) {
1014 case T_FLOAT: {
1015 #ifdef _LP64
1016 assert(src->is_single_xmm(), "not a float");
1017 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1018 #else
1019 if (src->is_single_xmm()) {
1020 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1021 } else {
1022 assert(src->is_single_fpu(), "must be");
1023 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1024 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1025 else __ fst_s (as_Address(to_addr));
1026 }
1027 #endif // _LP64
1028 break;
1029 }
1030
1031 case T_DOUBLE: {
1032 #ifdef _LP64
1033 assert(src->is_double_xmm(), "not a double");
1034 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1035 #else
1036 if (src->is_double_xmm()) {
1037 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1038 } else {
1039 assert(src->is_double_fpu(), "must be");
1040 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1041 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1042 else __ fst_d (as_Address(to_addr));
1043 }
1044 #endif // _LP64
1045 break;
1046 }
1047
1048 case T_PRIMITIVE_OBJECT: // fall through
1049 case T_ARRAY: // fall through
1050 case T_OBJECT: // fall through
1051 if (UseCompressedOops && !wide) {
1052 __ movl(as_Address(to_addr), compressed_src);
1053 } else {
1054 __ movptr(as_Address(to_addr), src->as_register());
1055 }
1056 break;
1057 case T_METADATA:
1058 // We get here to store a method pointer to the stack to pass to
1059 // a dtrace runtime call. This can't work on 64 bit with
1060 // compressed klass ptrs: T_METADATA can be a compressed klass
1061 // ptr or a 64 bit method pointer.
1062 LP64_ONLY(ShouldNotReachHere());
1063 __ movptr(as_Address(to_addr), src->as_register());
1064 break;
1065 case T_ADDRESS:
1066 __ movptr(as_Address(to_addr), src->as_register());
1067 break;
1068 case T_INT:
1069 __ movl(as_Address(to_addr), src->as_register());
1070 break;
1071
1072 case T_LONG: {
1073 Register from_lo = src->as_register_lo();
1074 Register from_hi = src->as_register_hi();
1075 #ifdef _LP64
1076 __ movptr(as_Address_lo(to_addr), from_lo);
1077 #else
1078 Register base = to_addr->base()->as_register();
1079 Register index = noreg;
1080 if (to_addr->index()->is_register()) {
1081 index = to_addr->index()->as_register();
1082 }
1083 if (base == from_lo || index == from_lo) {
1084 assert(base != from_hi, "can't be");
1085 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1086 __ movl(as_Address_hi(to_addr), from_hi);
1087 if (patch != nullptr) {
1088 patching_epilog(patch, lir_patch_high, base, info);
1089 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1090 patch_code = lir_patch_low;
1091 }
1092 __ movl(as_Address_lo(to_addr), from_lo);
1093 } else {
1094 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1095 __ movl(as_Address_lo(to_addr), from_lo);
1096 if (patch != nullptr) {
1097 patching_epilog(patch, lir_patch_low, base, info);
1098 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1099 patch_code = lir_patch_high;
1100 }
1101 __ movl(as_Address_hi(to_addr), from_hi);
1102 }
1103 #endif // _LP64
1104 break;
1105 }
1106
1107 case T_BYTE: // fall through
1108 case T_BOOLEAN: {
1109 Register src_reg = src->as_register();
1110 Address dst_addr = as_Address(to_addr);
1111 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1112 __ movb(dst_addr, src_reg);
1113 break;
1114 }
1115
1116 case T_CHAR: // fall through
1117 case T_SHORT:
1118 __ movw(as_Address(to_addr), src->as_register());
1119 break;
1120
1121 default:
1122 ShouldNotReachHere();
1123 }
1124 if (info != nullptr) {
1125 add_debug_info_for_null_check(null_check_here, info);
1126 }
1127
1128 if (patch_code != lir_patch_none) {
1129 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1130 }
1131 }
1132
1133
1134 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1135 assert(src->is_stack(), "should not call otherwise");
1136 assert(dest->is_register(), "should not call otherwise");
1137
1138 if (dest->is_single_cpu()) {
1139 if (is_reference_type(type)) {
1140 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1141 __ verify_oop(dest->as_register());
1142 } else if (type == T_METADATA || type == T_ADDRESS) {
1143 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1144 } else {
1145 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1146 }
1147
1148 } else if (dest->is_double_cpu()) {
1149 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1150 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1151 __ movptr(dest->as_register_lo(), src_addr_LO);
1152 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1153
1154 } else if (dest->is_single_xmm()) {
1155 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1156 __ movflt(dest->as_xmm_float_reg(), src_addr);
1157
1158 } else if (dest->is_double_xmm()) {
1159 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1160 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1161
1162 #ifndef _LP64
1163 } else if (dest->is_single_fpu()) {
1164 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1165 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1166 __ fld_s(src_addr);
1167
1168 } else if (dest->is_double_fpu()) {
1169 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1170 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1171 __ fld_d(src_addr);
1172 #endif // _LP64
1173
1174 } else {
1175 ShouldNotReachHere();
1176 }
1177 }
1178
1179
1180 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1181 if (src->is_single_stack()) {
1182 if (is_reference_type(type)) {
1183 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1184 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1185 } else {
1186 #ifndef _LP64
1187 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1188 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1189 #else
1190 //no pushl on 64bits
1191 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1192 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1193 #endif
1194 }
1195
1196 } else if (src->is_double_stack()) {
1197 #ifdef _LP64
1198 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1199 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1200 #else
1201 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1202 // push and pop the part at src + wordSize, adding wordSize for the previous push
1203 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1204 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1205 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1206 #endif // _LP64
1207
1208 } else {
1209 ShouldNotReachHere();
1210 }
1211 }
1212
1213
1214 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1215 assert(src->is_address(), "should not call otherwise");
1216 assert(dest->is_register(), "should not call otherwise");
1217
1218 LIR_Address* addr = src->as_address_ptr();
1219 Address from_addr = as_Address(addr);
1220
1221 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_PRIMITIVE_OBJECT) {
1222 __ verify_oop(addr->base()->as_pointer_register());
1223 }
1224
1225 switch (type) {
1226 case T_BOOLEAN: // fall through
1227 case T_BYTE: // fall through
1228 case T_CHAR: // fall through
1229 case T_SHORT:
1230 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1231 // on pre P6 processors we may get partial register stalls
1232 // so blow away the value of to_rinfo before loading a
1233 // partial word into it. Do it here so that it precedes
1234 // the potential patch point below.
1235 __ xorptr(dest->as_register(), dest->as_register());
1236 }
1237 break;
1238 default:
1239 break;
1240 }
1241
1242 PatchingStub* patch = nullptr;
1243 if (patch_code != lir_patch_none) {
1244 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1245 assert(from_addr.disp() != 0, "must have");
1246 }
1247 if (info != nullptr) {
1248 add_debug_info_for_null_check_here(info);
1249 }
1250
1251 switch (type) {
1252 case T_FLOAT: {
1253 if (dest->is_single_xmm()) {
1254 __ movflt(dest->as_xmm_float_reg(), from_addr);
1255 } else {
1256 #ifndef _LP64
1257 assert(dest->is_single_fpu(), "must be");
1258 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1259 __ fld_s(from_addr);
1260 #else
1261 ShouldNotReachHere();
1262 #endif // !LP64
1263 }
1264 break;
1265 }
1266
1267 case T_DOUBLE: {
1268 if (dest->is_double_xmm()) {
1269 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1270 } else {
1271 #ifndef _LP64
1272 assert(dest->is_double_fpu(), "must be");
1273 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1274 __ fld_d(from_addr);
1275 #else
1276 ShouldNotReachHere();
1277 #endif // !LP64
1278 }
1279 break;
1280 }
1281
1282 case T_PRIMITIVE_OBJECT: // fall through
1283 case T_OBJECT: // fall through
1284 case T_ARRAY: // fall through
1285 if (UseCompressedOops && !wide) {
1286 __ movl(dest->as_register(), from_addr);
1287 } else {
1288 __ movptr(dest->as_register(), from_addr);
1289 }
1290 break;
1291
1292 case T_ADDRESS:
1293 __ movptr(dest->as_register(), from_addr);
1294 break;
1295 case T_INT:
1296 __ movl(dest->as_register(), from_addr);
1297 break;
1298
1299 case T_LONG: {
1300 Register to_lo = dest->as_register_lo();
1301 Register to_hi = dest->as_register_hi();
1302 #ifdef _LP64
1303 __ movptr(to_lo, as_Address_lo(addr));
1304 #else
1305 Register base = addr->base()->as_register();
1306 Register index = noreg;
1307 if (addr->index()->is_register()) {
1308 index = addr->index()->as_register();
1309 }
1310 if ((base == to_lo && index == to_hi) ||
1311 (base == to_hi && index == to_lo)) {
1312 // addresses with 2 registers are only formed as a result of
1313 // array access so this code will never have to deal with
1314 // patches or null checks.
1315 assert(info == nullptr && patch == nullptr, "must be");
1316 __ lea(to_hi, as_Address(addr));
1317 __ movl(to_lo, Address(to_hi, 0));
1318 __ movl(to_hi, Address(to_hi, BytesPerWord));
1319 } else if (base == to_lo || index == to_lo) {
1320 assert(base != to_hi, "can't be");
1321 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1322 __ movl(to_hi, as_Address_hi(addr));
1323 if (patch != nullptr) {
1324 patching_epilog(patch, lir_patch_high, base, info);
1325 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1326 patch_code = lir_patch_low;
1327 }
1328 __ movl(to_lo, as_Address_lo(addr));
1329 } else {
1330 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1331 __ movl(to_lo, as_Address_lo(addr));
1332 if (patch != nullptr) {
1333 patching_epilog(patch, lir_patch_low, base, info);
1334 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1335 patch_code = lir_patch_high;
1336 }
1337 __ movl(to_hi, as_Address_hi(addr));
1338 }
1339 #endif // _LP64
1340 break;
1341 }
1342
1343 case T_BOOLEAN: // fall through
1344 case T_BYTE: {
1345 Register dest_reg = dest->as_register();
1346 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1347 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1348 __ movsbl(dest_reg, from_addr);
1349 } else {
1350 __ movb(dest_reg, from_addr);
1351 __ shll(dest_reg, 24);
1352 __ sarl(dest_reg, 24);
1353 }
1354 break;
1355 }
1356
1357 case T_CHAR: {
1358 Register dest_reg = dest->as_register();
1359 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1360 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1361 __ movzwl(dest_reg, from_addr);
1362 } else {
1363 __ movw(dest_reg, from_addr);
1364 }
1365 break;
1366 }
1367
1368 case T_SHORT: {
1369 Register dest_reg = dest->as_register();
1370 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1371 __ movswl(dest_reg, from_addr);
1372 } else {
1373 __ movw(dest_reg, from_addr);
1374 __ shll(dest_reg, 16);
1375 __ sarl(dest_reg, 16);
1376 }
1377 break;
1378 }
1379
1380 default:
1381 ShouldNotReachHere();
1382 }
1383
1384 if (patch != nullptr) {
1385 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1386 }
1387
1388 if (is_reference_type(type)) {
1389 #ifdef _LP64
1390 if (UseCompressedOops && !wide) {
1391 __ decode_heap_oop(dest->as_register());
1392 }
1393 #endif
1394
1395 if (!(UseZGC && !ZGenerational)) {
1396 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1397 __ verify_oop(dest->as_register());
1398 }
1399 }
1400 }
1401
1402
1403 NEEDS_CLEANUP; // This could be static?
1404 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1405 int elem_size = type2aelembytes(type);
1406 switch (elem_size) {
1407 case 1: return Address::times_1;
1408 case 2: return Address::times_2;
1409 case 4: return Address::times_4;
1410 case 8: return Address::times_8;
1411 }
1412 ShouldNotReachHere();
1413 return Address::no_scale;
1414 }
1415
1416
1417 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1418 switch (op->code()) {
1419 case lir_idiv:
1420 case lir_irem:
1421 arithmetic_idiv(op->code(),
1422 op->in_opr1(),
1423 op->in_opr2(),
1424 op->in_opr3(),
1425 op->result_opr(),
1426 op->info());
1427 break;
1428 case lir_fmad:
1429 __ fmad(op->result_opr()->as_xmm_double_reg(),
1430 op->in_opr1()->as_xmm_double_reg(),
1431 op->in_opr2()->as_xmm_double_reg(),
1432 op->in_opr3()->as_xmm_double_reg());
1433 break;
1434 case lir_fmaf:
1435 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1436 op->in_opr1()->as_xmm_float_reg(),
1437 op->in_opr2()->as_xmm_float_reg(),
1438 op->in_opr3()->as_xmm_float_reg());
1439 break;
1440 default: ShouldNotReachHere(); break;
1441 }
1442 }
1443
1444 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1445 #ifdef ASSERT
1446 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1447 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1448 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1449 #endif
1450
1451 if (op->cond() == lir_cond_always) {
1452 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1453 __ jmp (*(op->label()));
1454 } else {
1455 Assembler::Condition acond = Assembler::zero;
1456 if (op->code() == lir_cond_float_branch) {
1457 assert(op->ublock() != nullptr, "must have unordered successor");
1458 __ jcc(Assembler::parity, *(op->ublock()->label()));
1459 switch(op->cond()) {
1460 case lir_cond_equal: acond = Assembler::equal; break;
1461 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1462 case lir_cond_less: acond = Assembler::below; break;
1463 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1464 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1465 case lir_cond_greater: acond = Assembler::above; break;
1466 default: ShouldNotReachHere();
1467 }
1468 } else {
1469 switch (op->cond()) {
1470 case lir_cond_equal: acond = Assembler::equal; break;
1471 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1472 case lir_cond_less: acond = Assembler::less; break;
1473 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1474 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1475 case lir_cond_greater: acond = Assembler::greater; break;
1476 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1477 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1478 default: ShouldNotReachHere();
1479 }
1480 }
1481 __ jcc(acond,*(op->label()));
1482 }
1483 }
1484
1485 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1486 LIR_Opr src = op->in_opr();
1487 LIR_Opr dest = op->result_opr();
1488
1489 switch (op->bytecode()) {
1490 case Bytecodes::_i2l:
1491 #ifdef _LP64
1492 __ movl2ptr(dest->as_register_lo(), src->as_register());
1493 #else
1494 move_regs(src->as_register(), dest->as_register_lo());
1495 move_regs(src->as_register(), dest->as_register_hi());
1496 __ sarl(dest->as_register_hi(), 31);
1497 #endif // LP64
1498 break;
1499
1500 case Bytecodes::_l2i:
1501 #ifdef _LP64
1502 __ movl(dest->as_register(), src->as_register_lo());
1503 #else
1504 move_regs(src->as_register_lo(), dest->as_register());
1505 #endif
1506 break;
1507
1508 case Bytecodes::_i2b:
1509 move_regs(src->as_register(), dest->as_register());
1510 __ sign_extend_byte(dest->as_register());
1511 break;
1512
1513 case Bytecodes::_i2c:
1514 move_regs(src->as_register(), dest->as_register());
1515 __ andl(dest->as_register(), 0xFFFF);
1516 break;
1517
1518 case Bytecodes::_i2s:
1519 move_regs(src->as_register(), dest->as_register());
1520 __ sign_extend_short(dest->as_register());
1521 break;
1522
1523
1524 #ifdef _LP64
1525 case Bytecodes::_f2d:
1526 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1527 break;
1528
1529 case Bytecodes::_d2f:
1530 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1531 break;
1532
1533 case Bytecodes::_i2f:
1534 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1535 break;
1536
1537 case Bytecodes::_i2d:
1538 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1539 break;
1540
1541 case Bytecodes::_l2f:
1542 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1543 break;
1544
1545 case Bytecodes::_l2d:
1546 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1547 break;
1548
1549 case Bytecodes::_f2i:
1550 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1551 break;
1552
1553 case Bytecodes::_d2i:
1554 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1555 break;
1556
1557 case Bytecodes::_f2l:
1558 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1559 break;
1560
1561 case Bytecodes::_d2l:
1562 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1563 break;
1564 #else
1565 case Bytecodes::_f2d:
1566 case Bytecodes::_d2f:
1567 if (dest->is_single_xmm()) {
1568 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1569 } else if (dest->is_double_xmm()) {
1570 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1571 } else {
1572 assert(src->fpu() == dest->fpu(), "register must be equal");
1573 // do nothing (float result is rounded later through spilling)
1574 }
1575 break;
1576
1577 case Bytecodes::_i2f:
1578 case Bytecodes::_i2d:
1579 if (dest->is_single_xmm()) {
1580 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1581 } else if (dest->is_double_xmm()) {
1582 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1583 } else {
1584 assert(dest->fpu() == 0, "result must be on TOS");
1585 __ movl(Address(rsp, 0), src->as_register());
1586 __ fild_s(Address(rsp, 0));
1587 }
1588 break;
1589
1590 case Bytecodes::_l2f:
1591 case Bytecodes::_l2d:
1592 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1593 assert(dest->fpu() == 0, "result must be on TOS");
1594 __ movptr(Address(rsp, 0), src->as_register_lo());
1595 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1596 __ fild_d(Address(rsp, 0));
1597 // float result is rounded later through spilling
1598 break;
1599
1600 case Bytecodes::_f2i:
1601 case Bytecodes::_d2i:
1602 if (src->is_single_xmm()) {
1603 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1604 } else if (src->is_double_xmm()) {
1605 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1606 } else {
1607 assert(src->fpu() == 0, "input must be on TOS");
1608 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1609 __ fist_s(Address(rsp, 0));
1610 __ movl(dest->as_register(), Address(rsp, 0));
1611 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1612 }
1613 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1614 assert(op->stub() != nullptr, "stub required");
1615 __ cmpl(dest->as_register(), 0x80000000);
1616 __ jcc(Assembler::equal, *op->stub()->entry());
1617 __ bind(*op->stub()->continuation());
1618 break;
1619
1620 case Bytecodes::_f2l:
1621 case Bytecodes::_d2l:
1622 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1623 assert(src->fpu() == 0, "input must be on TOS");
1624 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1625
1626 // instruction sequence too long to inline it here
1627 {
1628 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1629 }
1630 break;
1631 #endif // _LP64
1632
1633 default: ShouldNotReachHere();
1634 }
1635 }
1636
1637 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1638 if (op->init_check()) {
1639 add_debug_info_for_null_check_here(op->stub()->info());
1640 __ cmpb(Address(op->klass()->as_register(),
1641 InstanceKlass::init_state_offset()),
1642 InstanceKlass::fully_initialized);
1643 __ jcc(Assembler::notEqual, *op->stub()->entry());
1644 }
1645 __ allocate_object(op->obj()->as_register(),
1646 op->tmp1()->as_register(),
1647 op->tmp2()->as_register(),
1648 op->header_size(),
1649 op->object_size(),
1650 op->klass()->as_register(),
1651 *op->stub()->entry());
1652 __ bind(*op->stub()->continuation());
1653 }
1654
1655 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1656 Register len = op->len()->as_register();
1657 LP64_ONLY( __ movslq(len, len); )
1658
1659 if (UseSlowPath || op->type() == T_PRIMITIVE_OBJECT ||
1660 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1661 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1662 __ jmp(*op->stub()->entry());
1663 } else {
1664 Register tmp1 = op->tmp1()->as_register();
1665 Register tmp2 = op->tmp2()->as_register();
1666 Register tmp3 = op->tmp3()->as_register();
1667 if (len == tmp1) {
1668 tmp1 = tmp3;
1669 } else if (len == tmp2) {
1670 tmp2 = tmp3;
1671 } else if (len == tmp3) {
1672 // everything is ok
1673 } else {
1674 __ mov(tmp3, len);
1675 }
1676 __ allocate_array(op->obj()->as_register(),
1677 len,
1678 tmp1,
1679 tmp2,
1680 arrayOopDesc::header_size(op->type()),
1681 array_element_size(op->type()),
1682 op->klass()->as_register(),
1683 *op->stub()->entry());
1684 }
1685 __ bind(*op->stub()->continuation());
1686 }
1687
1688 void LIR_Assembler::type_profile_helper(Register mdo,
1689 ciMethodData *md, ciProfileData *data,
1690 Register recv, Label* update_done) {
1691 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1692 Label next_test;
1693 // See if the receiver is receiver[n].
1694 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1695 __ jccb(Assembler::notEqual, next_test);
1696 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1697 __ addptr(data_addr, DataLayout::counter_increment);
1698 __ jmp(*update_done);
1699 __ bind(next_test);
1700 }
1701
1702 // Didn't find receiver; find next empty slot and fill it in
1703 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1704 Label next_test;
1705 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1706 __ cmpptr(recv_addr, NULL_WORD);
1707 __ jccb(Assembler::notEqual, next_test);
1708 __ movptr(recv_addr, recv);
1709 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1710 __ jmp(*update_done);
1711 __ bind(next_test);
1712 }
1713 }
1714
1715 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1716 // we always need a stub for the failure case.
1717 CodeStub* stub = op->stub();
1718 Register obj = op->object()->as_register();
1719 Register k_RInfo = op->tmp1()->as_register();
1720 Register klass_RInfo = op->tmp2()->as_register();
1721 Register dst = op->result_opr()->as_register();
1722 ciKlass* k = op->klass();
1723 Register Rtmp1 = noreg;
1724 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1725
1726 // check if it needs to be profiled
1727 ciMethodData* md = nullptr;
1728 ciProfileData* data = nullptr;
1729
1730 if (op->should_profile()) {
1731 ciMethod* method = op->profiled_method();
1732 assert(method != nullptr, "Should have method");
1733 int bci = op->profiled_bci();
1734 md = method->method_data_or_null();
1735 assert(md != nullptr, "Sanity");
1736 data = md->bci_to_data(bci);
1737 assert(data != nullptr, "need data for type check");
1738 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1739 }
1740 Label profile_cast_success, profile_cast_failure;
1741 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1742 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1743
1744 if (obj == k_RInfo) {
1745 k_RInfo = dst;
1746 } else if (obj == klass_RInfo) {
1747 klass_RInfo = dst;
1748 }
1749 if (k->is_loaded() && !UseCompressedClassPointers) {
1750 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1751 } else {
1752 Rtmp1 = op->tmp3()->as_register();
1753 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1754 }
1755
1756 assert_different_registers(obj, k_RInfo, klass_RInfo);
1757
1758 if (op->need_null_check()) {
1759 __ cmpptr(obj, NULL_WORD);
1760 if (op->should_profile()) {
1761 Label not_null;
1762 __ jccb(Assembler::notEqual, not_null);
1763 // Object is null; update MDO and exit
1764 Register mdo = klass_RInfo;
1765 __ mov_metadata(mdo, md->constant_encoding());
1766 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1767 int header_bits = BitData::null_seen_byte_constant();
1768 __ orb(data_addr, header_bits);
1769 __ jmp(*obj_is_null);
1770 __ bind(not_null);
1771 } else {
1772 __ jcc(Assembler::equal, *obj_is_null);
1773 }
1774 }
1775
1776 if (!k->is_loaded()) {
1777 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1778 } else {
1779 #ifdef _LP64
1780 __ mov_metadata(k_RInfo, k->constant_encoding());
1781 #endif // _LP64
1782 }
1783 __ verify_oop(obj);
1784
1785 if (op->fast_check()) {
1786 // get object class
1787 // not a safepoint as obj null check happens earlier
1788 #ifdef _LP64
1789 if (UseCompressedClassPointers) {
1790 __ load_klass(Rtmp1, obj, tmp_load_klass);
1791 __ cmpptr(k_RInfo, Rtmp1);
1792 } else {
1793 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1794 }
1795 #else
1796 if (k->is_loaded()) {
1797 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1798 } else {
1799 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1800 }
1801 #endif
1802 __ jcc(Assembler::notEqual, *failure_target);
1803 // successful cast, fall through to profile or jump
1804 } else {
1805 // get object class
1806 // not a safepoint as obj null check happens earlier
1807 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1808 if (k->is_loaded()) {
1809 // See if we get an immediate positive hit
1810 #ifdef _LP64
1811 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1812 #else
1813 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1814 #endif // _LP64
1815 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1816 __ jcc(Assembler::notEqual, *failure_target);
1817 // successful cast, fall through to profile or jump
1818 } else {
1819 // See if we get an immediate positive hit
1820 __ jcc(Assembler::equal, *success_target);
1821 // check for self
1822 #ifdef _LP64
1823 __ cmpptr(klass_RInfo, k_RInfo);
1824 #else
1825 __ cmpklass(klass_RInfo, k->constant_encoding());
1826 #endif // _LP64
1827 __ jcc(Assembler::equal, *success_target);
1828
1829 __ push(klass_RInfo);
1830 #ifdef _LP64
1831 __ push(k_RInfo);
1832 #else
1833 __ pushklass(k->constant_encoding(), noreg);
1834 #endif // _LP64
1835 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1836 __ pop(klass_RInfo);
1837 __ pop(klass_RInfo);
1838 // result is a boolean
1839 __ cmpl(klass_RInfo, 0);
1840 __ jcc(Assembler::equal, *failure_target);
1841 // successful cast, fall through to profile or jump
1842 }
1843 } else {
1844 // perform the fast part of the checking logic
1845 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1846 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1847 __ push(klass_RInfo);
1848 __ push(k_RInfo);
1849 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1850 __ pop(klass_RInfo);
1851 __ pop(k_RInfo);
1852 // result is a boolean
1853 __ cmpl(k_RInfo, 0);
1854 __ jcc(Assembler::equal, *failure_target);
1855 // successful cast, fall through to profile or jump
1856 }
1857 }
1858 if (op->should_profile()) {
1859 Register mdo = klass_RInfo, recv = k_RInfo;
1860 __ bind(profile_cast_success);
1861 __ mov_metadata(mdo, md->constant_encoding());
1862 __ load_klass(recv, obj, tmp_load_klass);
1863 type_profile_helper(mdo, md, data, recv, success);
1864 __ jmp(*success);
1865
1866 __ bind(profile_cast_failure);
1867 __ mov_metadata(mdo, md->constant_encoding());
1868 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1869 __ subptr(counter_addr, DataLayout::counter_increment);
1870 __ jmp(*failure);
1871 }
1872 __ jmp(*success);
1873 }
1874
1875
1876 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1877 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1878 LIR_Code code = op->code();
1879 if (code == lir_store_check) {
1880 Register value = op->object()->as_register();
1881 Register array = op->array()->as_register();
1882 Register k_RInfo = op->tmp1()->as_register();
1883 Register klass_RInfo = op->tmp2()->as_register();
1884 Register Rtmp1 = op->tmp3()->as_register();
1885
1886 CodeStub* stub = op->stub();
1887
1888 // check if it needs to be profiled
1889 ciMethodData* md = nullptr;
1890 ciProfileData* data = nullptr;
1891
1892 if (op->should_profile()) {
1893 ciMethod* method = op->profiled_method();
1894 assert(method != nullptr, "Should have method");
1895 int bci = op->profiled_bci();
1896 md = method->method_data_or_null();
1897 assert(md != nullptr, "Sanity");
1898 data = md->bci_to_data(bci);
1899 assert(data != nullptr, "need data for type check");
1900 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1901 }
1902 Label profile_cast_success, profile_cast_failure, done;
1903 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1904 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1905
1906 __ cmpptr(value, NULL_WORD);
1907 if (op->should_profile()) {
1908 Label not_null;
1909 __ jccb(Assembler::notEqual, not_null);
1910 // Object is null; update MDO and exit
1911 Register mdo = klass_RInfo;
1912 __ mov_metadata(mdo, md->constant_encoding());
1913 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1914 int header_bits = BitData::null_seen_byte_constant();
1915 __ orb(data_addr, header_bits);
1916 __ jmp(done);
1917 __ bind(not_null);
1918 } else {
1919 __ jcc(Assembler::equal, done);
1920 }
1921
1922 add_debug_info_for_null_check_here(op->info_for_exception());
1923 __ load_klass(k_RInfo, array, tmp_load_klass);
1924 __ load_klass(klass_RInfo, value, tmp_load_klass);
1925
1926 // get instance klass (it's already uncompressed)
1927 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1928 // perform the fast part of the checking logic
1929 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1930 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1931 __ push(klass_RInfo);
1932 __ push(k_RInfo);
1933 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1934 __ pop(klass_RInfo);
1935 __ pop(k_RInfo);
1936 // result is a boolean
1937 __ cmpl(k_RInfo, 0);
1938 __ jcc(Assembler::equal, *failure_target);
1939 // fall through to the success case
1940
1941 if (op->should_profile()) {
1942 Register mdo = klass_RInfo, recv = k_RInfo;
1943 __ bind(profile_cast_success);
1944 __ mov_metadata(mdo, md->constant_encoding());
1945 __ load_klass(recv, value, tmp_load_klass);
1946 type_profile_helper(mdo, md, data, recv, &done);
1947 __ jmpb(done);
1948
1949 __ bind(profile_cast_failure);
1950 __ mov_metadata(mdo, md->constant_encoding());
1951 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1952 __ subptr(counter_addr, DataLayout::counter_increment);
1953 __ jmp(*stub->entry());
1954 }
1955
1956 __ bind(done);
1957 } else
1958 if (code == lir_checkcast) {
1959 Register obj = op->object()->as_register();
1960 Register dst = op->result_opr()->as_register();
1961 Label success;
1962 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1963 __ bind(success);
1964 if (dst != obj) {
1965 __ mov(dst, obj);
1966 }
1967 } else
1968 if (code == lir_instanceof) {
1969 Register obj = op->object()->as_register();
1970 Register dst = op->result_opr()->as_register();
1971 Label success, failure, done;
1972 emit_typecheck_helper(op, &success, &failure, &failure);
1973 __ bind(failure);
1974 __ xorptr(dst, dst);
1975 __ jmpb(done);
1976 __ bind(success);
1977 __ movptr(dst, 1);
1978 __ bind(done);
1979 } else {
1980 ShouldNotReachHere();
1981 }
1982
1983 }
1984
1985 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1986 // We are loading/storing from/to an array that *may* be flattened (the
1987 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1988 // If this array is flattened, take the slow path.
1989 Register klass = op->tmp()->as_register();
1990 if (UseArrayMarkWordCheck) {
1991 __ test_flattened_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1992 } else {
1993 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1994 __ load_klass(klass, op->array()->as_register(), tmp_load_klass);
1995 __ movl(klass, Address(klass, Klass::layout_helper_offset()));
1996 __ testl(klass, Klass::_lh_array_tag_flat_value_bit_inplace);
1997 __ jcc(Assembler::notZero, *op->stub()->entry());
1998 }
1999 if (!op->value()->is_illegal()) {
2000 // The array is not flattened, but it might be null-free. If we are storing
2001 // a null into a null-free array, take the slow path (which will throw NPE).
2002 Label skip;
2003 __ cmpptr(op->value()->as_register(), NULL_WORD);
2004 __ jcc(Assembler::notEqual, skip);
2005 if (UseArrayMarkWordCheck) {
2006 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
2007 } else {
2008 __ testl(klass, Klass::_lh_null_free_array_bit_inplace);
2009 __ jcc(Assembler::notZero, *op->stub()->entry());
2010 }
2011 __ bind(skip);
2012 }
2013 }
2014
2015 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
2016 // We are storing into an array that *may* be null-free (the declared type is
2017 // Object[], abstract[], interface[] or VT.ref[]).
2018 if (UseArrayMarkWordCheck) {
2019 Label test_mark_word;
2020 Register tmp = op->tmp()->as_register();
2021 __ movptr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
2022 __ testl(tmp, markWord::unlocked_value);
2023 __ jccb(Assembler::notZero, test_mark_word);
2024 __ load_prototype_header(tmp, op->array()->as_register(), rscratch1);
2025 __ bind(test_mark_word);
2026 __ testl(tmp, markWord::null_free_array_bit_in_place);
2027 } else {
2028 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
2029 Register klass = op->tmp()->as_register();
2030 __ load_klass(klass, op->array()->as_register(), tmp_load_klass);
2031 __ movl(klass, Address(klass, Klass::layout_helper_offset()));
2032 __ testl(klass, Klass::_lh_null_free_array_bit_inplace);
2033 }
2034 }
2035
2036 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
2037 Label L_oops_equal;
2038 Label L_oops_not_equal;
2039 Label L_end;
2040
2041 Register left = op->left()->as_register();
2042 Register right = op->right()->as_register();
2043
2044 __ cmpptr(left, right);
2045 __ jcc(Assembler::equal, L_oops_equal);
2046
2047 // (1) Null check -- if one of the operands is null, the other must not be null (because
2048 // the two references are not equal), so they are not substitutable,
2049 // FIXME: do null check only if the operand is nullable
2050 __ testptr(left, right);
2051 __ jcc(Assembler::zero, L_oops_not_equal);
2052
2053 ciKlass* left_klass = op->left_klass();
2054 ciKlass* right_klass = op->right_klass();
2055
2056 // (2) Inline type check -- if either of the operands is not a inline type,
2057 // they are not substitutable. We do this only if we are not sure that the
2058 // operands are inline type
2059 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
2060 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
2061 Register tmp1 = op->tmp1()->as_register();
2062 __ movptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2063 __ andptr(tmp1, Address(left, oopDesc::mark_offset_in_bytes()));
2064 __ andptr(tmp1, Address(right, oopDesc::mark_offset_in_bytes()));
2065 __ cmpptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2066 __ jcc(Assembler::notEqual, L_oops_not_equal);
2067 }
2068
2069 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
2070 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
2071 // No need to load klass -- the operands are statically known to be the same inline klass.
2072 __ jmp(*op->stub()->entry());
2073 } else {
2074 Register left_klass_op = op->left_klass_op()->as_register();
2075 Register right_klass_op = op->right_klass_op()->as_register();
2076
2077 if (UseCompressedClassPointers) {
2078 __ movl(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
2079 __ movl(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2080 __ cmpl(left_klass_op, right_klass_op);
2081 } else {
2082 __ movptr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
2083 __ movptr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2084 __ cmpptr(left_klass_op, right_klass_op);
2085 }
2086
2087 __ jcc(Assembler::equal, *op->stub()->entry()); // same klass -> do slow check
2088 // fall through to L_oops_not_equal
2089 }
2090
2091 __ bind(L_oops_not_equal);
2092 move(op->not_equal_result(), op->result_opr());
2093 __ jmp(L_end);
2094
2095 __ bind(L_oops_equal);
2096 move(op->equal_result(), op->result_opr());
2097 __ jmp(L_end);
2098
2099 // We've returned from the stub. RAX contains 0x0 IFF the two
2100 // operands are not substitutable. (Don't compare against 0x1 in case the
2101 // C compiler is naughty)
2102 __ bind(*op->stub()->continuation());
2103 __ cmpl(rax, 0);
2104 __ jcc(Assembler::equal, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
2105 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
2106 // fall-through
2107 __ bind(L_end);
2108 }
2109
2110 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2111 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
2112 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
2113 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
2114 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
2115 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
2116 Register addr = op->addr()->as_register();
2117 __ lock();
2118 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
2119
2120 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
2121 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
2122 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2123 Register newval = op->new_value()->as_register();
2124 Register cmpval = op->cmp_value()->as_register();
2125 assert(cmpval == rax, "wrong register");
2126 assert(newval != noreg, "new val must be register");
2127 assert(cmpval != newval, "cmp and new values must be in different registers");
2128 assert(cmpval != addr, "cmp and addr must be in different registers");
2129 assert(newval != addr, "new value and addr must be in different registers");
2130
2131 if ( op->code() == lir_cas_obj) {
2132 #ifdef _LP64
2133 if (UseCompressedOops) {
2134 __ encode_heap_oop(cmpval);
2135 __ mov(rscratch1, newval);
2136 __ encode_heap_oop(rscratch1);
2137 __ lock();
2138 // cmpval (rax) is implicitly used by this instruction
2139 __ cmpxchgl(rscratch1, Address(addr, 0));
2140 } else
2141 #endif
2142 {
2143 __ lock();
2144 __ cmpxchgptr(newval, Address(addr, 0));
2145 }
2146 } else {
2147 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2148 __ lock();
2149 __ cmpxchgl(newval, Address(addr, 0));
2150 }
2151 #ifdef _LP64
2152 } else if (op->code() == lir_cas_long) {
2153 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2154 Register newval = op->new_value()->as_register_lo();
2155 Register cmpval = op->cmp_value()->as_register_lo();
2156 assert(cmpval == rax, "wrong register");
2157 assert(newval != noreg, "new val must be register");
2158 assert(cmpval != newval, "cmp and new values must be in different registers");
2159 assert(cmpval != addr, "cmp and addr must be in different registers");
2160 assert(newval != addr, "new value and addr must be in different registers");
2161 __ lock();
2162 __ cmpxchgq(newval, Address(addr, 0));
2163 #endif // _LP64
2164 } else {
2165 Unimplemented();
2166 }
2167 }
2168
2169 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
2170 assert(dst->is_cpu_register(), "must be");
2171 assert(dst->type() == src->type(), "must be");
2172
2173 if (src->is_cpu_register()) {
2174 reg2reg(src, dst);
2175 } else if (src->is_stack()) {
2176 stack2reg(src, dst, dst->type());
2177 } else if (src->is_constant()) {
2178 const2reg(src, dst, lir_patch_none, nullptr);
2179 } else {
2180 ShouldNotReachHere();
2181 }
2182 }
2183
2184 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
2185 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
2186 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
2187
2188 Assembler::Condition acond, ncond;
2189 switch (condition) {
2190 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2191 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2192 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2193 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2194 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2195 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2196 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2197 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2198 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2199 ShouldNotReachHere();
2200 }
2201
2202 if (opr1->is_cpu_register()) {
2203 reg2reg(opr1, result);
2204 } else if (opr1->is_stack()) {
2205 stack2reg(opr1, result, result->type());
2206 } else if (opr1->is_constant()) {
2207 const2reg(opr1, result, lir_patch_none, nullptr);
2208 } else {
2209 ShouldNotReachHere();
2210 }
2211
2212 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2213 // optimized version that does not require a branch
2214 if (opr2->is_single_cpu()) {
2215 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2216 __ cmov(ncond, result->as_register(), opr2->as_register());
2217 } else if (opr2->is_double_cpu()) {
2218 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2219 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2220 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2221 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2222 } else if (opr2->is_single_stack()) {
2223 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2224 } else if (opr2->is_double_stack()) {
2225 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2226 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2227 } else {
2228 ShouldNotReachHere();
2229 }
2230
2231 } else {
2232 Label skip;
2233 __ jcc (acond, skip);
2234 if (opr2->is_cpu_register()) {
2235 reg2reg(opr2, result);
2236 } else if (opr2->is_stack()) {
2237 stack2reg(opr2, result, result->type());
2238 } else if (opr2->is_constant()) {
2239 const2reg(opr2, result, lir_patch_none, nullptr);
2240 } else {
2241 ShouldNotReachHere();
2242 }
2243 __ bind(skip);
2244 }
2245 }
2246
2247
2248 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2249 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2250
2251 if (left->is_single_cpu()) {
2252 assert(left == dest, "left and dest must be equal");
2253 Register lreg = left->as_register();
2254
2255 if (right->is_single_cpu()) {
2256 // cpu register - cpu register
2257 Register rreg = right->as_register();
2258 switch (code) {
2259 case lir_add: __ addl (lreg, rreg); break;
2260 case lir_sub: __ subl (lreg, rreg); break;
2261 case lir_mul: __ imull(lreg, rreg); break;
2262 default: ShouldNotReachHere();
2263 }
2264
2265 } else if (right->is_stack()) {
2266 // cpu register - stack
2267 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2268 switch (code) {
2269 case lir_add: __ addl(lreg, raddr); break;
2270 case lir_sub: __ subl(lreg, raddr); break;
2271 default: ShouldNotReachHere();
2272 }
2273
2274 } else if (right->is_constant()) {
2275 // cpu register - constant
2276 jint c = right->as_constant_ptr()->as_jint();
2277 switch (code) {
2278 case lir_add: {
2279 __ incrementl(lreg, c);
2280 break;
2281 }
2282 case lir_sub: {
2283 __ decrementl(lreg, c);
2284 break;
2285 }
2286 default: ShouldNotReachHere();
2287 }
2288
2289 } else {
2290 ShouldNotReachHere();
2291 }
2292
2293 } else if (left->is_double_cpu()) {
2294 assert(left == dest, "left and dest must be equal");
2295 Register lreg_lo = left->as_register_lo();
2296 Register lreg_hi = left->as_register_hi();
2297
2298 if (right->is_double_cpu()) {
2299 // cpu register - cpu register
2300 Register rreg_lo = right->as_register_lo();
2301 Register rreg_hi = right->as_register_hi();
2302 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2303 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2304 switch (code) {
2305 case lir_add:
2306 __ addptr(lreg_lo, rreg_lo);
2307 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2308 break;
2309 case lir_sub:
2310 __ subptr(lreg_lo, rreg_lo);
2311 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2312 break;
2313 case lir_mul:
2314 #ifdef _LP64
2315 __ imulq(lreg_lo, rreg_lo);
2316 #else
2317 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2318 __ imull(lreg_hi, rreg_lo);
2319 __ imull(rreg_hi, lreg_lo);
2320 __ addl (rreg_hi, lreg_hi);
2321 __ mull (rreg_lo);
2322 __ addl (lreg_hi, rreg_hi);
2323 #endif // _LP64
2324 break;
2325 default:
2326 ShouldNotReachHere();
2327 }
2328
2329 } else if (right->is_constant()) {
2330 // cpu register - constant
2331 #ifdef _LP64
2332 jlong c = right->as_constant_ptr()->as_jlong_bits();
2333 __ movptr(r10, (intptr_t) c);
2334 switch (code) {
2335 case lir_add:
2336 __ addptr(lreg_lo, r10);
2337 break;
2338 case lir_sub:
2339 __ subptr(lreg_lo, r10);
2340 break;
2341 default:
2342 ShouldNotReachHere();
2343 }
2344 #else
2345 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2346 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2347 switch (code) {
2348 case lir_add:
2349 __ addptr(lreg_lo, c_lo);
2350 __ adcl(lreg_hi, c_hi);
2351 break;
2352 case lir_sub:
2353 __ subptr(lreg_lo, c_lo);
2354 __ sbbl(lreg_hi, c_hi);
2355 break;
2356 default:
2357 ShouldNotReachHere();
2358 }
2359 #endif // _LP64
2360
2361 } else {
2362 ShouldNotReachHere();
2363 }
2364
2365 } else if (left->is_single_xmm()) {
2366 assert(left == dest, "left and dest must be equal");
2367 XMMRegister lreg = left->as_xmm_float_reg();
2368
2369 if (right->is_single_xmm()) {
2370 XMMRegister rreg = right->as_xmm_float_reg();
2371 switch (code) {
2372 case lir_add: __ addss(lreg, rreg); break;
2373 case lir_sub: __ subss(lreg, rreg); break;
2374 case lir_mul: __ mulss(lreg, rreg); break;
2375 case lir_div: __ divss(lreg, rreg); break;
2376 default: ShouldNotReachHere();
2377 }
2378 } else {
2379 Address raddr;
2380 if (right->is_single_stack()) {
2381 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2382 } else if (right->is_constant()) {
2383 // hack for now
2384 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2385 } else {
2386 ShouldNotReachHere();
2387 }
2388 switch (code) {
2389 case lir_add: __ addss(lreg, raddr); break;
2390 case lir_sub: __ subss(lreg, raddr); break;
2391 case lir_mul: __ mulss(lreg, raddr); break;
2392 case lir_div: __ divss(lreg, raddr); break;
2393 default: ShouldNotReachHere();
2394 }
2395 }
2396
2397 } else if (left->is_double_xmm()) {
2398 assert(left == dest, "left and dest must be equal");
2399
2400 XMMRegister lreg = left->as_xmm_double_reg();
2401 if (right->is_double_xmm()) {
2402 XMMRegister rreg = right->as_xmm_double_reg();
2403 switch (code) {
2404 case lir_add: __ addsd(lreg, rreg); break;
2405 case lir_sub: __ subsd(lreg, rreg); break;
2406 case lir_mul: __ mulsd(lreg, rreg); break;
2407 case lir_div: __ divsd(lreg, rreg); break;
2408 default: ShouldNotReachHere();
2409 }
2410 } else {
2411 Address raddr;
2412 if (right->is_double_stack()) {
2413 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2414 } else if (right->is_constant()) {
2415 // hack for now
2416 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2417 } else {
2418 ShouldNotReachHere();
2419 }
2420 switch (code) {
2421 case lir_add: __ addsd(lreg, raddr); break;
2422 case lir_sub: __ subsd(lreg, raddr); break;
2423 case lir_mul: __ mulsd(lreg, raddr); break;
2424 case lir_div: __ divsd(lreg, raddr); break;
2425 default: ShouldNotReachHere();
2426 }
2427 }
2428
2429 #ifndef _LP64
2430 } else if (left->is_single_fpu()) {
2431 assert(dest->is_single_fpu(), "fpu stack allocation required");
2432
2433 if (right->is_single_fpu()) {
2434 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2435
2436 } else {
2437 assert(left->fpu_regnr() == 0, "left must be on TOS");
2438 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2439
2440 Address raddr;
2441 if (right->is_single_stack()) {
2442 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2443 } else if (right->is_constant()) {
2444 address const_addr = float_constant(right->as_jfloat());
2445 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2446 // hack for now
2447 raddr = __ as_Address(InternalAddress(const_addr));
2448 } else {
2449 ShouldNotReachHere();
2450 }
2451
2452 switch (code) {
2453 case lir_add: __ fadd_s(raddr); break;
2454 case lir_sub: __ fsub_s(raddr); break;
2455 case lir_mul: __ fmul_s(raddr); break;
2456 case lir_div: __ fdiv_s(raddr); break;
2457 default: ShouldNotReachHere();
2458 }
2459 }
2460
2461 } else if (left->is_double_fpu()) {
2462 assert(dest->is_double_fpu(), "fpu stack allocation required");
2463
2464 if (code == lir_mul || code == lir_div) {
2465 // Double values require special handling for strictfp mul/div on x86
2466 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2467 __ fmulp(left->fpu_regnrLo() + 1);
2468 }
2469
2470 if (right->is_double_fpu()) {
2471 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2472
2473 } else {
2474 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2475 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2476
2477 Address raddr;
2478 if (right->is_double_stack()) {
2479 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2480 } else if (right->is_constant()) {
2481 // hack for now
2482 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2483 } else {
2484 ShouldNotReachHere();
2485 }
2486
2487 switch (code) {
2488 case lir_add: __ fadd_d(raddr); break;
2489 case lir_sub: __ fsub_d(raddr); break;
2490 case lir_mul: __ fmul_d(raddr); break;
2491 case lir_div: __ fdiv_d(raddr); break;
2492 default: ShouldNotReachHere();
2493 }
2494 }
2495
2496 if (code == lir_mul || code == lir_div) {
2497 // Double values require special handling for strictfp mul/div on x86
2498 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2499 __ fmulp(dest->fpu_regnrLo() + 1);
2500 }
2501 #endif // !_LP64
2502
2503 } else if (left->is_single_stack() || left->is_address()) {
2504 assert(left == dest, "left and dest must be equal");
2505
2506 Address laddr;
2507 if (left->is_single_stack()) {
2508 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2509 } else if (left->is_address()) {
2510 laddr = as_Address(left->as_address_ptr());
2511 } else {
2512 ShouldNotReachHere();
2513 }
2514
2515 if (right->is_single_cpu()) {
2516 Register rreg = right->as_register();
2517 switch (code) {
2518 case lir_add: __ addl(laddr, rreg); break;
2519 case lir_sub: __ subl(laddr, rreg); break;
2520 default: ShouldNotReachHere();
2521 }
2522 } else if (right->is_constant()) {
2523 jint c = right->as_constant_ptr()->as_jint();
2524 switch (code) {
2525 case lir_add: {
2526 __ incrementl(laddr, c);
2527 break;
2528 }
2529 case lir_sub: {
2530 __ decrementl(laddr, c);
2531 break;
2532 }
2533 default: ShouldNotReachHere();
2534 }
2535 } else {
2536 ShouldNotReachHere();
2537 }
2538
2539 } else {
2540 ShouldNotReachHere();
2541 }
2542 }
2543
2544 #ifndef _LP64
2545 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2546 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2547 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2548 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2549
2550 bool left_is_tos = (left_index == 0);
2551 bool dest_is_tos = (dest_index == 0);
2552 int non_tos_index = (left_is_tos ? right_index : left_index);
2553
2554 switch (code) {
2555 case lir_add:
2556 if (pop_fpu_stack) __ faddp(non_tos_index);
2557 else if (dest_is_tos) __ fadd (non_tos_index);
2558 else __ fadda(non_tos_index);
2559 break;
2560
2561 case lir_sub:
2562 if (left_is_tos) {
2563 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2564 else if (dest_is_tos) __ fsub (non_tos_index);
2565 else __ fsubra(non_tos_index);
2566 } else {
2567 if (pop_fpu_stack) __ fsubp (non_tos_index);
2568 else if (dest_is_tos) __ fsubr (non_tos_index);
2569 else __ fsuba (non_tos_index);
2570 }
2571 break;
2572
2573 case lir_mul:
2574 if (pop_fpu_stack) __ fmulp(non_tos_index);
2575 else if (dest_is_tos) __ fmul (non_tos_index);
2576 else __ fmula(non_tos_index);
2577 break;
2578
2579 case lir_div:
2580 if (left_is_tos) {
2581 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2582 else if (dest_is_tos) __ fdiv (non_tos_index);
2583 else __ fdivra(non_tos_index);
2584 } else {
2585 if (pop_fpu_stack) __ fdivp (non_tos_index);
2586 else if (dest_is_tos) __ fdivr (non_tos_index);
2587 else __ fdiva (non_tos_index);
2588 }
2589 break;
2590
2591 case lir_rem:
2592 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2593 __ fremr(noreg);
2594 break;
2595
2596 default:
2597 ShouldNotReachHere();
2598 }
2599 }
2600 #endif // _LP64
2601
2602
2603 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2604 if (value->is_double_xmm()) {
2605 switch(code) {
2606 case lir_abs :
2607 {
2608 #ifdef _LP64
2609 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2610 assert(tmp->is_valid(), "need temporary");
2611 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2612 } else
2613 #endif
2614 {
2615 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2616 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2617 }
2618 assert(!tmp->is_valid(), "do not need temporary");
2619 __ andpd(dest->as_xmm_double_reg(),
2620 ExternalAddress((address)double_signmask_pool),
2621 rscratch1);
2622 }
2623 }
2624 break;
2625
2626 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2627 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2628 default : ShouldNotReachHere();
2629 }
2630
2631 #ifndef _LP64
2632 } else if (value->is_double_fpu()) {
2633 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2634 switch(code) {
2635 case lir_abs : __ fabs() ; break;
2636 case lir_sqrt : __ fsqrt(); break;
2637 default : ShouldNotReachHere();
2638 }
2639 #endif // !_LP64
2640 } else if (code == lir_f2hf) {
2641 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2642 } else if (code == lir_hf2f) {
2643 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2644 } else {
2645 Unimplemented();
2646 }
2647 }
2648
2649 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2650 // assert(left->destroys_register(), "check");
2651 if (left->is_single_cpu()) {
2652 Register reg = left->as_register();
2653 if (right->is_constant()) {
2654 int val = right->as_constant_ptr()->as_jint();
2655 switch (code) {
2656 case lir_logic_and: __ andl (reg, val); break;
2657 case lir_logic_or: __ orl (reg, val); break;
2658 case lir_logic_xor: __ xorl (reg, val); break;
2659 default: ShouldNotReachHere();
2660 }
2661 } else if (right->is_stack()) {
2662 // added support for stack operands
2663 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2664 switch (code) {
2665 case lir_logic_and: __ andl (reg, raddr); break;
2666 case lir_logic_or: __ orl (reg, raddr); break;
2667 case lir_logic_xor: __ xorl (reg, raddr); break;
2668 default: ShouldNotReachHere();
2669 }
2670 } else {
2671 Register rright = right->as_register();
2672 switch (code) {
2673 case lir_logic_and: __ andptr (reg, rright); break;
2674 case lir_logic_or : __ orptr (reg, rright); break;
2675 case lir_logic_xor: __ xorptr (reg, rright); break;
2676 default: ShouldNotReachHere();
2677 }
2678 }
2679 move_regs(reg, dst->as_register());
2680 } else {
2681 Register l_lo = left->as_register_lo();
2682 Register l_hi = left->as_register_hi();
2683 if (right->is_constant()) {
2684 #ifdef _LP64
2685 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2686 switch (code) {
2687 case lir_logic_and:
2688 __ andq(l_lo, rscratch1);
2689 break;
2690 case lir_logic_or:
2691 __ orq(l_lo, rscratch1);
2692 break;
2693 case lir_logic_xor:
2694 __ xorq(l_lo, rscratch1);
2695 break;
2696 default: ShouldNotReachHere();
2697 }
2698 #else
2699 int r_lo = right->as_constant_ptr()->as_jint_lo();
2700 int r_hi = right->as_constant_ptr()->as_jint_hi();
2701 switch (code) {
2702 case lir_logic_and:
2703 __ andl(l_lo, r_lo);
2704 __ andl(l_hi, r_hi);
2705 break;
2706 case lir_logic_or:
2707 __ orl(l_lo, r_lo);
2708 __ orl(l_hi, r_hi);
2709 break;
2710 case lir_logic_xor:
2711 __ xorl(l_lo, r_lo);
2712 __ xorl(l_hi, r_hi);
2713 break;
2714 default: ShouldNotReachHere();
2715 }
2716 #endif // _LP64
2717 } else {
2718 #ifdef _LP64
2719 Register r_lo;
2720 if (is_reference_type(right->type())) {
2721 r_lo = right->as_register();
2722 } else {
2723 r_lo = right->as_register_lo();
2724 }
2725 #else
2726 Register r_lo = right->as_register_lo();
2727 Register r_hi = right->as_register_hi();
2728 assert(l_lo != r_hi, "overwriting registers");
2729 #endif
2730 switch (code) {
2731 case lir_logic_and:
2732 __ andptr(l_lo, r_lo);
2733 NOT_LP64(__ andptr(l_hi, r_hi);)
2734 break;
2735 case lir_logic_or:
2736 __ orptr(l_lo, r_lo);
2737 NOT_LP64(__ orptr(l_hi, r_hi);)
2738 break;
2739 case lir_logic_xor:
2740 __ xorptr(l_lo, r_lo);
2741 NOT_LP64(__ xorptr(l_hi, r_hi);)
2742 break;
2743 default: ShouldNotReachHere();
2744 }
2745 }
2746
2747 Register dst_lo = dst->as_register_lo();
2748 Register dst_hi = dst->as_register_hi();
2749
2750 #ifdef _LP64
2751 move_regs(l_lo, dst_lo);
2752 #else
2753 if (dst_lo == l_hi) {
2754 assert(dst_hi != l_lo, "overwriting registers");
2755 move_regs(l_hi, dst_hi);
2756 move_regs(l_lo, dst_lo);
2757 } else {
2758 assert(dst_lo != l_hi, "overwriting registers");
2759 move_regs(l_lo, dst_lo);
2760 move_regs(l_hi, dst_hi);
2761 }
2762 #endif // _LP64
2763 }
2764 }
2765
2766
2767 // we assume that rax, and rdx can be overwritten
2768 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2769
2770 assert(left->is_single_cpu(), "left must be register");
2771 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2772 assert(result->is_single_cpu(), "result must be register");
2773
2774 // assert(left->destroys_register(), "check");
2775 // assert(right->destroys_register(), "check");
2776
2777 Register lreg = left->as_register();
2778 Register dreg = result->as_register();
2779
2780 if (right->is_constant()) {
2781 jint divisor = right->as_constant_ptr()->as_jint();
2782 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2783 if (code == lir_idiv) {
2784 assert(lreg == rax, "must be rax,");
2785 assert(temp->as_register() == rdx, "tmp register must be rdx");
2786 __ cdql(); // sign extend into rdx:rax
2787 if (divisor == 2) {
2788 __ subl(lreg, rdx);
2789 } else {
2790 __ andl(rdx, divisor - 1);
2791 __ addl(lreg, rdx);
2792 }
2793 __ sarl(lreg, log2i_exact(divisor));
2794 move_regs(lreg, dreg);
2795 } else if (code == lir_irem) {
2796 Label done;
2797 __ mov(dreg, lreg);
2798 __ andl(dreg, 0x80000000 | (divisor - 1));
2799 __ jcc(Assembler::positive, done);
2800 __ decrement(dreg);
2801 __ orl(dreg, ~(divisor - 1));
2802 __ increment(dreg);
2803 __ bind(done);
2804 } else {
2805 ShouldNotReachHere();
2806 }
2807 } else {
2808 Register rreg = right->as_register();
2809 assert(lreg == rax, "left register must be rax,");
2810 assert(rreg != rdx, "right register must not be rdx");
2811 assert(temp->as_register() == rdx, "tmp register must be rdx");
2812
2813 move_regs(lreg, rax);
2814
2815 int idivl_offset = __ corrected_idivl(rreg);
2816 if (ImplicitDiv0Checks) {
2817 add_debug_info_for_div0(idivl_offset, info);
2818 }
2819 if (code == lir_irem) {
2820 move_regs(rdx, dreg); // result is in rdx
2821 } else {
2822 move_regs(rax, dreg);
2823 }
2824 }
2825 }
2826
2827
2828 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2829 if (opr1->is_single_cpu()) {
2830 Register reg1 = opr1->as_register();
2831 if (opr2->is_single_cpu()) {
2832 // cpu register - cpu register
2833 if (is_reference_type(opr1->type())) {
2834 __ cmpoop(reg1, opr2->as_register());
2835 } else {
2836 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2837 __ cmpl(reg1, opr2->as_register());
2838 }
2839 } else if (opr2->is_stack()) {
2840 // cpu register - stack
2841 if (is_reference_type(opr1->type())) {
2842 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2843 } else {
2844 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2845 }
2846 } else if (opr2->is_constant()) {
2847 // cpu register - constant
2848 LIR_Const* c = opr2->as_constant_ptr();
2849 if (c->type() == T_INT) {
2850 __ cmpl(reg1, c->as_jint());
2851 } else if (c->type() == T_METADATA) {
2852 // All we need for now is a comparison with null for equality.
2853 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2854 Metadata* m = c->as_metadata();
2855 if (m == nullptr) {
2856 __ cmpptr(reg1, NULL_WORD);
2857 } else {
2858 ShouldNotReachHere();
2859 }
2860 } else if (is_reference_type(c->type())) {
2861 // In 64bit oops are single register
2862 jobject o = c->as_jobject();
2863 if (o == nullptr) {
2864 __ cmpptr(reg1, NULL_WORD);
2865 } else {
2866 __ cmpoop(reg1, o, rscratch1);
2867 }
2868 } else {
2869 fatal("unexpected type: %s", basictype_to_str(c->type()));
2870 }
2871 // cpu register - address
2872 } else if (opr2->is_address()) {
2873 if (op->info() != nullptr) {
2874 add_debug_info_for_null_check_here(op->info());
2875 }
2876 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2877 } else {
2878 ShouldNotReachHere();
2879 }
2880
2881 } else if(opr1->is_double_cpu()) {
2882 Register xlo = opr1->as_register_lo();
2883 Register xhi = opr1->as_register_hi();
2884 if (opr2->is_double_cpu()) {
2885 #ifdef _LP64
2886 __ cmpptr(xlo, opr2->as_register_lo());
2887 #else
2888 // cpu register - cpu register
2889 Register ylo = opr2->as_register_lo();
2890 Register yhi = opr2->as_register_hi();
2891 __ subl(xlo, ylo);
2892 __ sbbl(xhi, yhi);
2893 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2894 __ orl(xhi, xlo);
2895 }
2896 #endif // _LP64
2897 } else if (opr2->is_constant()) {
2898 // cpu register - constant 0
2899 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2900 #ifdef _LP64
2901 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2902 #else
2903 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2904 __ orl(xhi, xlo);
2905 #endif // _LP64
2906 } else {
2907 ShouldNotReachHere();
2908 }
2909
2910 } else if (opr1->is_single_xmm()) {
2911 XMMRegister reg1 = opr1->as_xmm_float_reg();
2912 if (opr2->is_single_xmm()) {
2913 // xmm register - xmm register
2914 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2915 } else if (opr2->is_stack()) {
2916 // xmm register - stack
2917 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2918 } else if (opr2->is_constant()) {
2919 // xmm register - constant
2920 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2921 } else if (opr2->is_address()) {
2922 // xmm register - address
2923 if (op->info() != nullptr) {
2924 add_debug_info_for_null_check_here(op->info());
2925 }
2926 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2927 } else {
2928 ShouldNotReachHere();
2929 }
2930
2931 } else if (opr1->is_double_xmm()) {
2932 XMMRegister reg1 = opr1->as_xmm_double_reg();
2933 if (opr2->is_double_xmm()) {
2934 // xmm register - xmm register
2935 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2936 } else if (opr2->is_stack()) {
2937 // xmm register - stack
2938 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2939 } else if (opr2->is_constant()) {
2940 // xmm register - constant
2941 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2942 } else if (opr2->is_address()) {
2943 // xmm register - address
2944 if (op->info() != nullptr) {
2945 add_debug_info_for_null_check_here(op->info());
2946 }
2947 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2948 } else {
2949 ShouldNotReachHere();
2950 }
2951
2952 #ifndef _LP64
2953 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2954 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2955 assert(opr2->is_fpu_register(), "both must be registers");
2956 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2957 #endif // LP64
2958
2959 } else if (opr1->is_address() && opr2->is_constant()) {
2960 LIR_Const* c = opr2->as_constant_ptr();
2961 #ifdef _LP64
2962 if (is_reference_type(c->type())) {
2963 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2964 __ movoop(rscratch1, c->as_jobject());
2965 }
2966 #endif // LP64
2967 if (op->info() != nullptr) {
2968 add_debug_info_for_null_check_here(op->info());
2969 }
2970 // special case: address - constant
2971 LIR_Address* addr = opr1->as_address_ptr();
2972 if (c->type() == T_INT) {
2973 __ cmpl(as_Address(addr), c->as_jint());
2974 } else if (is_reference_type(c->type())) {
2975 #ifdef _LP64
2976 // %%% Make this explode if addr isn't reachable until we figure out a
2977 // better strategy by giving noreg as the temp for as_Address
2978 __ cmpoop(rscratch1, as_Address(addr, noreg));
2979 #else
2980 __ cmpoop(as_Address(addr), c->as_jobject());
2981 #endif // _LP64
2982 } else {
2983 ShouldNotReachHere();
2984 }
2985
2986 } else {
2987 ShouldNotReachHere();
2988 }
2989 }
2990
2991 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2992 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2993 if (left->is_single_xmm()) {
2994 assert(right->is_single_xmm(), "must match");
2995 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2996 } else if (left->is_double_xmm()) {
2997 assert(right->is_double_xmm(), "must match");
2998 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2999
3000 } else {
3001 #ifdef _LP64
3002 ShouldNotReachHere();
3003 #else
3004 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
3005 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
3006
3007 assert(left->fpu() == 0, "left must be on TOS");
3008 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
3009 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
3010 #endif // LP64
3011 }
3012 } else {
3013 assert(code == lir_cmp_l2i, "check");
3014 #ifdef _LP64
3015 Label done;
3016 Register dest = dst->as_register();
3017 __ cmpptr(left->as_register_lo(), right->as_register_lo());
3018 __ movl(dest, -1);
3019 __ jccb(Assembler::less, done);
3020 __ set_byte_if_not_zero(dest);
3021 __ movzbl(dest, dest);
3022 __ bind(done);
3023 #else
3024 __ lcmp2int(left->as_register_hi(),
3025 left->as_register_lo(),
3026 right->as_register_hi(),
3027 right->as_register_lo());
3028 move_regs(left->as_register_hi(), dst->as_register());
3029 #endif // _LP64
3030 }
3031 }
3032
3033
3034 void LIR_Assembler::align_call(LIR_Code code) {
3035 // make sure that the displacement word of the call ends up word aligned
3036 int offset = __ offset();
3037 switch (code) {
3038 case lir_static_call:
3039 case lir_optvirtual_call:
3040 case lir_dynamic_call:
3041 offset += NativeCall::displacement_offset;
3042 break;
3043 case lir_icvirtual_call:
3044 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
3045 break;
3046 default: ShouldNotReachHere();
3047 }
3048 __ align(BytesPerWord, offset);
3049 }
3050
3051
3052 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
3053 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
3054 "must be aligned");
3055 __ call(AddressLiteral(op->addr(), rtype));
3056 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3057 __ post_call_nop();
3058 }
3059
3060
3061 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
3062 __ ic_call(op->addr());
3063 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3064 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
3065 "must be aligned");
3066 __ post_call_nop();
3067 }
3068
3069
3070 void LIR_Assembler::emit_static_call_stub() {
3071 address call_pc = __ pc();
3072 address stub = __ start_a_stub(call_stub_size());
3073 if (stub == nullptr) {
3074 bailout("static call stub overflow");
3075 return;
3076 }
3077
3078 int start = __ offset();
3079
3080 // make sure that the displacement word of the call ends up word aligned
3081 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
3082 __ relocate(static_stub_Relocation::spec(call_pc));
3083 __ mov_metadata(rbx, (Metadata*)nullptr);
3084 // must be set to -1 at code generation time
3085 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
3086 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
3087 __ jump(RuntimeAddress(__ pc()));
3088
3089 assert(__ offset() - start <= call_stub_size(), "stub too big");
3090 __ end_a_stub();
3091 }
3092
3093
3094 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
3095 assert(exceptionOop->as_register() == rax, "must match");
3096 assert(exceptionPC->as_register() == rdx, "must match");
3097
3098 // exception object is not added to oop map by LinearScan
3099 // (LinearScan assumes that no oops are in fixed registers)
3100 info->add_register_oop(exceptionOop);
3101 Runtime1::StubID unwind_id;
3102
3103 // get current pc information
3104 // pc is only needed if the method has an exception handler, the unwind code does not need it.
3105 int pc_for_athrow_offset = __ offset();
3106 InternalAddress pc_for_athrow(__ pc());
3107 __ lea(exceptionPC->as_register(), pc_for_athrow);
3108 add_call_info(pc_for_athrow_offset, info); // for exception handler
3109
3110 __ verify_not_null_oop(rax);
3111 // search an exception handler (rax: exception oop, rdx: throwing pc)
3112 if (compilation()->has_fpu_code()) {
3113 unwind_id = Runtime1::handle_exception_id;
3114 } else {
3115 unwind_id = Runtime1::handle_exception_nofpu_id;
3116 }
3117 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
3118
3119 // enough room for two byte trap
3120 __ nop();
3121 }
3122
3123
3124 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
3125 assert(exceptionOop->as_register() == rax, "must match");
3126
3127 __ jmp(_unwind_handler_entry);
3128 }
3129
3130
3131 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3132
3133 // optimized version for linear scan:
3134 // * count must be already in ECX (guaranteed by LinearScan)
3135 // * left and dest must be equal
3136 // * tmp must be unused
3137 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3138 assert(left == dest, "left and dest must be equal");
3139 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3140
3141 if (left->is_single_cpu()) {
3142 Register value = left->as_register();
3143 assert(value != SHIFT_count, "left cannot be ECX");
3144
3145 switch (code) {
3146 case lir_shl: __ shll(value); break;
3147 case lir_shr: __ sarl(value); break;
3148 case lir_ushr: __ shrl(value); break;
3149 default: ShouldNotReachHere();
3150 }
3151 } else if (left->is_double_cpu()) {
3152 Register lo = left->as_register_lo();
3153 Register hi = left->as_register_hi();
3154 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3155 #ifdef _LP64
3156 switch (code) {
3157 case lir_shl: __ shlptr(lo); break;
3158 case lir_shr: __ sarptr(lo); break;
3159 case lir_ushr: __ shrptr(lo); break;
3160 default: ShouldNotReachHere();
3161 }
3162 #else
3163
3164 switch (code) {
3165 case lir_shl: __ lshl(hi, lo); break;
3166 case lir_shr: __ lshr(hi, lo, true); break;
3167 case lir_ushr: __ lshr(hi, lo, false); break;
3168 default: ShouldNotReachHere();
3169 }
3170 #endif // LP64
3171 } else {
3172 ShouldNotReachHere();
3173 }
3174 }
3175
3176
3177 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3178 if (dest->is_single_cpu()) {
3179 // first move left into dest so that left is not destroyed by the shift
3180 Register value = dest->as_register();
3181 count = count & 0x1F; // Java spec
3182
3183 move_regs(left->as_register(), value);
3184 switch (code) {
3185 case lir_shl: __ shll(value, count); break;
3186 case lir_shr: __ sarl(value, count); break;
3187 case lir_ushr: __ shrl(value, count); break;
3188 default: ShouldNotReachHere();
3189 }
3190 } else if (dest->is_double_cpu()) {
3191 #ifndef _LP64
3192 Unimplemented();
3193 #else
3194 // first move left into dest so that left is not destroyed by the shift
3195 Register value = dest->as_register_lo();
3196 count = count & 0x1F; // Java spec
3197
3198 move_regs(left->as_register_lo(), value);
3199 switch (code) {
3200 case lir_shl: __ shlptr(value, count); break;
3201 case lir_shr: __ sarptr(value, count); break;
3202 case lir_ushr: __ shrptr(value, count); break;
3203 default: ShouldNotReachHere();
3204 }
3205 #endif // _LP64
3206 } else {
3207 ShouldNotReachHere();
3208 }
3209 }
3210
3211
3212 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3213 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3214 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3215 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3216 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3217 }
3218
3219
3220 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3221 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3222 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3223 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3224 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3225 }
3226
3227
3228 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3229 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3230 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3231 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3232 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3233 }
3234
3235
3236 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3237 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3238 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3239 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3240 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3241 }
3242
3243
3244 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
3245 if (null_check) {
3246 __ testptr(obj, obj);
3247 __ jcc(Assembler::zero, *slow_path->entry());
3248 }
3249 if (UseArrayMarkWordCheck) {
3250 if (is_dest) {
3251 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
3252 } else {
3253 __ test_flattened_array_oop(obj, tmp, *slow_path->entry());
3254 }
3255 } else {
3256 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3257 __ load_klass(tmp, obj, tmp_load_klass);
3258 __ movl(tmp, Address(tmp, Klass::layout_helper_offset()));
3259 if (is_dest) {
3260 // Take the slow path if it's a null_free destination array, in case the source array contains nullptrs.
3261 __ testl(tmp, Klass::_lh_null_free_array_bit_inplace);
3262 } else {
3263 __ testl(tmp, Klass::_lh_array_tag_flat_value_bit_inplace);
3264 }
3265 __ jcc(Assembler::notZero, *slow_path->entry());
3266 }
3267 }
3268
3269
3270 // This code replaces a call to arraycopy; no exception may
3271 // be thrown in this code, they must be thrown in the System.arraycopy
3272 // activation frame; we could save some checks if this would not be the case
3273 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3274 ciArrayKlass* default_type = op->expected_type();
3275 Register src = op->src()->as_register();
3276 Register dst = op->dst()->as_register();
3277 Register src_pos = op->src_pos()->as_register();
3278 Register dst_pos = op->dst_pos()->as_register();
3279 Register length = op->length()->as_register();
3280 Register tmp = op->tmp()->as_register();
3281 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3282
3283 CodeStub* stub = op->stub();
3284 int flags = op->flags();
3285 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3286 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3287
3288 if (flags & LIR_OpArrayCopy::always_slow_path) {
3289 __ jmp(*stub->entry());
3290 __ bind(*stub->continuation());
3291 return;
3292 }
3293
3294 // if we don't know anything, just go through the generic arraycopy
3295 if (default_type == nullptr) {
3296 // save outgoing arguments on stack in case call to System.arraycopy is needed
3297 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3298 // for interpreter calling conventions. Now we have to do it in new style conventions.
3299 // For the moment until C1 gets the new register allocator I just force all the
3300 // args to the right place (except the register args) and then on the back side
3301 // reload the register args properly if we go slow path. Yuck
3302
3303 // These are proper for the calling convention
3304 store_parameter(length, 2);
3305 store_parameter(dst_pos, 1);
3306 store_parameter(dst, 0);
3307
3308 // these are just temporary placements until we need to reload
3309 store_parameter(src_pos, 3);
3310 store_parameter(src, 4);
3311 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3312
3313 address copyfunc_addr = StubRoutines::generic_arraycopy();
3314 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3315
3316 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3317 #ifdef _LP64
3318 // The arguments are in java calling convention so we can trivially shift them to C
3319 // convention
3320 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3321 __ mov(c_rarg0, j_rarg0);
3322 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3323 __ mov(c_rarg1, j_rarg1);
3324 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3325 __ mov(c_rarg2, j_rarg2);
3326 assert_different_registers(c_rarg3, j_rarg4);
3327 __ mov(c_rarg3, j_rarg3);
3328 #ifdef _WIN64
3329 // Allocate abi space for args but be sure to keep stack aligned
3330 __ subptr(rsp, 6*wordSize);
3331 store_parameter(j_rarg4, 4);
3332 #ifndef PRODUCT
3333 if (PrintC1Statistics) {
3334 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3335 }
3336 #endif
3337 __ call(RuntimeAddress(copyfunc_addr));
3338 __ addptr(rsp, 6*wordSize);
3339 #else
3340 __ mov(c_rarg4, j_rarg4);
3341 #ifndef PRODUCT
3342 if (PrintC1Statistics) {
3343 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3344 }
3345 #endif
3346 __ call(RuntimeAddress(copyfunc_addr));
3347 #endif // _WIN64
3348 #else
3349 __ push(length);
3350 __ push(dst_pos);
3351 __ push(dst);
3352 __ push(src_pos);
3353 __ push(src);
3354
3355 #ifndef PRODUCT
3356 if (PrintC1Statistics) {
3357 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3358 }
3359 #endif
3360 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3361
3362 #endif // _LP64
3363
3364 __ cmpl(rax, 0);
3365 __ jcc(Assembler::equal, *stub->continuation());
3366
3367 __ mov(tmp, rax);
3368 __ xorl(tmp, -1);
3369
3370 // Reload values from the stack so they are where the stub
3371 // expects them.
3372 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3373 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3374 __ movptr (length, Address(rsp, 2*BytesPerWord));
3375 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3376 __ movptr (src, Address(rsp, 4*BytesPerWord));
3377
3378 __ subl(length, tmp);
3379 __ addl(src_pos, tmp);
3380 __ addl(dst_pos, tmp);
3381 __ jmp(*stub->entry());
3382
3383 __ bind(*stub->continuation());
3384 return;
3385 }
3386
3387 // Handle inline type arrays
3388 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
3389 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
3390 }
3391 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
3392 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
3393 }
3394
3395 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3396
3397 int elem_size = type2aelembytes(basic_type);
3398 Address::ScaleFactor scale;
3399
3400 switch (elem_size) {
3401 case 1 :
3402 scale = Address::times_1;
3403 break;
3404 case 2 :
3405 scale = Address::times_2;
3406 break;
3407 case 4 :
3408 scale = Address::times_4;
3409 break;
3410 case 8 :
3411 scale = Address::times_8;
3412 break;
3413 default:
3414 scale = Address::no_scale;
3415 ShouldNotReachHere();
3416 }
3417
3418 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3419 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3420 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3421 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3422
3423 // length and pos's are all sign extended at this point on 64bit
3424
3425 // test for null
3426 if (flags & LIR_OpArrayCopy::src_null_check) {
3427 __ testptr(src, src);
3428 __ jcc(Assembler::zero, *stub->entry());
3429 }
3430 if (flags & LIR_OpArrayCopy::dst_null_check) {
3431 __ testptr(dst, dst);
3432 __ jcc(Assembler::zero, *stub->entry());
3433 }
3434
3435 // If the compiler was not able to prove that exact type of the source or the destination
3436 // of the arraycopy is an array type, check at runtime if the source or the destination is
3437 // an instance type.
3438 if (flags & LIR_OpArrayCopy::type_check) {
3439 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3440 __ load_klass(tmp, dst, tmp_load_klass);
3441 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3442 __ jcc(Assembler::greaterEqual, *stub->entry());
3443 }
3444
3445 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3446 __ load_klass(tmp, src, tmp_load_klass);
3447 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3448 __ jcc(Assembler::greaterEqual, *stub->entry());
3449 }
3450 }
3451
3452 // check if negative
3453 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3454 __ testl(src_pos, src_pos);
3455 __ jcc(Assembler::less, *stub->entry());
3456 }
3457 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3458 __ testl(dst_pos, dst_pos);
3459 __ jcc(Assembler::less, *stub->entry());
3460 }
3461
3462 if (flags & LIR_OpArrayCopy::src_range_check) {
3463 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3464 __ cmpl(tmp, src_length_addr);
3465 __ jcc(Assembler::above, *stub->entry());
3466 }
3467 if (flags & LIR_OpArrayCopy::dst_range_check) {
3468 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3469 __ cmpl(tmp, dst_length_addr);
3470 __ jcc(Assembler::above, *stub->entry());
3471 }
3472
3473 if (flags & LIR_OpArrayCopy::length_positive_check) {
3474 __ testl(length, length);
3475 __ jcc(Assembler::less, *stub->entry());
3476 }
3477
3478 #ifdef _LP64
3479 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3480 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3481 #endif
3482
3483 if (flags & LIR_OpArrayCopy::type_check) {
3484 // We don't know the array types are compatible
3485 if (basic_type != T_OBJECT) {
3486 // Simple test for basic type arrays
3487 if (UseCompressedClassPointers) {
3488 __ movl(tmp, src_klass_addr);
3489 __ cmpl(tmp, dst_klass_addr);
3490 } else {
3491 __ movptr(tmp, src_klass_addr);
3492 __ cmpptr(tmp, dst_klass_addr);
3493 }
3494 __ jcc(Assembler::notEqual, *stub->entry());
3495 } else {
3496 // For object arrays, if src is a sub class of dst then we can
3497 // safely do the copy.
3498 Label cont, slow;
3499
3500 __ push(src);
3501 __ push(dst);
3502
3503 __ load_klass(src, src, tmp_load_klass);
3504 __ load_klass(dst, dst, tmp_load_klass);
3505
3506 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3507
3508 __ push(src);
3509 __ push(dst);
3510 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3511 __ pop(dst);
3512 __ pop(src);
3513
3514 __ cmpl(src, 0);
3515 __ jcc(Assembler::notEqual, cont);
3516
3517 __ bind(slow);
3518 __ pop(dst);
3519 __ pop(src);
3520
3521 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3522 if (copyfunc_addr != nullptr) { // use stub if available
3523 // src is not a sub class of dst so we have to do a
3524 // per-element check.
3525
3526 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3527 if ((flags & mask) != mask) {
3528 // Check that at least both of them object arrays.
3529 assert(flags & mask, "one of the two should be known to be an object array");
3530
3531 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3532 __ load_klass(tmp, src, tmp_load_klass);
3533 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3534 __ load_klass(tmp, dst, tmp_load_klass);
3535 }
3536 int lh_offset = in_bytes(Klass::layout_helper_offset());
3537 Address klass_lh_addr(tmp, lh_offset);
3538 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3539 __ cmpl(klass_lh_addr, objArray_lh);
3540 __ jcc(Assembler::notEqual, *stub->entry());
3541 }
3542
3543 // Spill because stubs can use any register they like and it's
3544 // easier to restore just those that we care about.
3545 store_parameter(dst, 0);
3546 store_parameter(dst_pos, 1);
3547 store_parameter(length, 2);
3548 store_parameter(src_pos, 3);
3549 store_parameter(src, 4);
3550
3551 #ifndef _LP64
3552 __ movptr(tmp, dst_klass_addr);
3553 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3554 __ push(tmp);
3555 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3556 __ push(tmp);
3557 __ push(length);
3558 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3559 __ push(tmp);
3560 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3561 __ push(tmp);
3562
3563 __ call_VM_leaf(copyfunc_addr, 5);
3564 #else
3565 __ movl2ptr(length, length); //higher 32bits must be null
3566
3567 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3568 assert_different_registers(c_rarg0, dst, dst_pos, length);
3569 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3570 assert_different_registers(c_rarg1, dst, length);
3571
3572 __ mov(c_rarg2, length);
3573 assert_different_registers(c_rarg2, dst);
3574
3575 #ifdef _WIN64
3576 // Allocate abi space for args but be sure to keep stack aligned
3577 __ subptr(rsp, 6*wordSize);
3578 __ load_klass(c_rarg3, dst, tmp_load_klass);
3579 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3580 store_parameter(c_rarg3, 4);
3581 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3582 __ call(RuntimeAddress(copyfunc_addr));
3583 __ addptr(rsp, 6*wordSize);
3584 #else
3585 __ load_klass(c_rarg4, dst, tmp_load_klass);
3586 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3587 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3588 __ call(RuntimeAddress(copyfunc_addr));
3589 #endif
3590
3591 #endif
3592
3593 #ifndef PRODUCT
3594 if (PrintC1Statistics) {
3595 Label failed;
3596 __ testl(rax, rax);
3597 __ jcc(Assembler::notZero, failed);
3598 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3599 __ bind(failed);
3600 }
3601 #endif
3602
3603 __ testl(rax, rax);
3604 __ jcc(Assembler::zero, *stub->continuation());
3605
3606 #ifndef PRODUCT
3607 if (PrintC1Statistics) {
3608 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3609 }
3610 #endif
3611
3612 __ mov(tmp, rax);
3613
3614 __ xorl(tmp, -1);
3615
3616 // Restore previously spilled arguments
3617 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3618 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3619 __ movptr (length, Address(rsp, 2*BytesPerWord));
3620 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3621 __ movptr (src, Address(rsp, 4*BytesPerWord));
3622
3623
3624 __ subl(length, tmp);
3625 __ addl(src_pos, tmp);
3626 __ addl(dst_pos, tmp);
3627 }
3628
3629 __ jmp(*stub->entry());
3630
3631 __ bind(cont);
3632 __ pop(dst);
3633 __ pop(src);
3634 }
3635 }
3636
3637 #ifdef ASSERT
3638 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3639 // Sanity check the known type with the incoming class. For the
3640 // primitive case the types must match exactly with src.klass and
3641 // dst.klass each exactly matching the default type. For the
3642 // object array case, if no type check is needed then either the
3643 // dst type is exactly the expected type and the src type is a
3644 // subtype which we can't check or src is the same array as dst
3645 // but not necessarily exactly of type default_type.
3646 Label known_ok, halt;
3647 __ mov_metadata(tmp, default_type->constant_encoding());
3648 #ifdef _LP64
3649 if (UseCompressedClassPointers) {
3650 __ encode_klass_not_null(tmp, rscratch1);
3651 }
3652 #endif
3653
3654 if (basic_type != T_OBJECT) {
3655
3656 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3657 else __ cmpptr(tmp, dst_klass_addr);
3658 __ jcc(Assembler::notEqual, halt);
3659 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3660 else __ cmpptr(tmp, src_klass_addr);
3661 __ jcc(Assembler::equal, known_ok);
3662 } else {
3663 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3664 else __ cmpptr(tmp, dst_klass_addr);
3665 __ jcc(Assembler::equal, known_ok);
3666 __ cmpptr(src, dst);
3667 __ jcc(Assembler::equal, known_ok);
3668 }
3669 __ bind(halt);
3670 __ stop("incorrect type information in arraycopy");
3671 __ bind(known_ok);
3672 }
3673 #endif
3674
3675 #ifndef PRODUCT
3676 if (PrintC1Statistics) {
3677 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3678 }
3679 #endif
3680
3681 #ifdef _LP64
3682 assert_different_registers(c_rarg0, dst, dst_pos, length);
3683 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3684 assert_different_registers(c_rarg1, length);
3685 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3686 __ mov(c_rarg2, length);
3687
3688 #else
3689 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3690 store_parameter(tmp, 0);
3691 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3692 store_parameter(tmp, 1);
3693 store_parameter(length, 2);
3694 #endif // _LP64
3695
3696 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3697 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3698 const char *name;
3699 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3700 __ call_VM_leaf(entry, 0);
3701
3702 __ bind(*stub->continuation());
3703 }
3704
3705 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3706 assert(op->crc()->is_single_cpu(), "crc must be register");
3707 assert(op->val()->is_single_cpu(), "byte value must be register");
3708 assert(op->result_opr()->is_single_cpu(), "result must be register");
3709 Register crc = op->crc()->as_register();
3710 Register val = op->val()->as_register();
3711 Register res = op->result_opr()->as_register();
3712
3713 assert_different_registers(val, crc, res);
3714
3715 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3716 __ notl(crc); // ~crc
3717 __ update_byte_crc32(crc, val, res);
3718 __ notl(crc); // ~crc
3719 __ mov(res, crc);
3720 }
3721
3722 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3723 Register obj = op->obj_opr()->as_register(); // may not be an oop
3724 Register hdr = op->hdr_opr()->as_register();
3725 Register lock = op->lock_opr()->as_register();
3726 if (LockingMode == LM_MONITOR) {
3727 if (op->info() != nullptr) {
3728 add_debug_info_for_null_check_here(op->info());
3729 __ null_check(obj);
3730 }
3731 __ jmp(*op->stub()->entry());
3732 } else if (op->code() == lir_lock) {
3733 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3734 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3735 // add debug info for NullPointerException only if one is possible
3736 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3737 if (op->info() != nullptr) {
3738 add_debug_info_for_null_check(null_check_offset, op->info());
3739 }
3740 // done
3741 } else if (op->code() == lir_unlock) {
3742 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3743 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3744 } else {
3745 Unimplemented();
3746 }
3747 __ bind(*op->stub()->continuation());
3748 }
3749
3750 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3751 Register obj = op->obj()->as_pointer_register();
3752 Register result = op->result_opr()->as_pointer_register();
3753
3754 CodeEmitInfo* info = op->info();
3755 if (info != nullptr) {
3756 add_debug_info_for_null_check_here(info);
3757 }
3758
3759 #ifdef _LP64
3760 if (UseCompressedClassPointers) {
3761 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3762 __ decode_klass_not_null(result, rscratch1);
3763 } else
3764 #endif
3765 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3766 }
3767
3768 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3769 ciMethod* method = op->profiled_method();
3770 int bci = op->profiled_bci();
3771 ciMethod* callee = op->profiled_callee();
3772 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3773
3774 // Update counter for all call types
3775 ciMethodData* md = method->method_data_or_null();
3776 assert(md != nullptr, "Sanity");
3777 ciProfileData* data = md->bci_to_data(bci);
3778 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3779 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3780 Register mdo = op->mdo()->as_register();
3781 __ mov_metadata(mdo, md->constant_encoding());
3782 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3783 // Perform additional virtual call profiling for invokevirtual and
3784 // invokeinterface bytecodes
3785 if (op->should_profile_receiver_type()) {
3786 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3787 Register recv = op->recv()->as_register();
3788 assert_different_registers(mdo, recv);
3789 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3790 ciKlass* known_klass = op->known_holder();
3791 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3792 // We know the type that will be seen at this call site; we can
3793 // statically update the MethodData* rather than needing to do
3794 // dynamic tests on the receiver type
3795
3796 // NOTE: we should probably put a lock around this search to
3797 // avoid collisions by concurrent compilations
3798 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3799 uint i;
3800 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3801 ciKlass* receiver = vc_data->receiver(i);
3802 if (known_klass->equals(receiver)) {
3803 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3804 __ addptr(data_addr, DataLayout::counter_increment);
3805 return;
3806 }
3807 }
3808
3809 // Receiver type not found in profile data; select an empty slot
3810
3811 // Note that this is less efficient than it should be because it
3812 // always does a write to the receiver part of the
3813 // VirtualCallData rather than just the first time
3814 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3815 ciKlass* receiver = vc_data->receiver(i);
3816 if (receiver == nullptr) {
3817 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3818 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3819 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3820 __ addptr(data_addr, DataLayout::counter_increment);
3821 return;
3822 }
3823 }
3824 } else {
3825 __ load_klass(recv, recv, tmp_load_klass);
3826 Label update_done;
3827 type_profile_helper(mdo, md, data, recv, &update_done);
3828 // Receiver did not match any saved receiver and there is no empty row for it.
3829 // Increment total counter to indicate polymorphic case.
3830 __ addptr(counter_addr, DataLayout::counter_increment);
3831
3832 __ bind(update_done);
3833 }
3834 } else {
3835 // Static call
3836 __ addptr(counter_addr, DataLayout::counter_increment);
3837 }
3838 }
3839
3840 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3841 Register obj = op->obj()->as_register();
3842 Register tmp = op->tmp()->as_pointer_register();
3843 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3844 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3845 ciKlass* exact_klass = op->exact_klass();
3846 intptr_t current_klass = op->current_klass();
3847 bool not_null = op->not_null();
3848 bool no_conflict = op->no_conflict();
3849
3850 Label update, next, none;
3851
3852 bool do_null = !not_null;
3853 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3854 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3855
3856 assert(do_null || do_update, "why are we here?");
3857 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3858
3859 __ verify_oop(obj);
3860
3861 if (tmp != obj) {
3862 __ mov(tmp, obj);
3863 }
3864 if (do_null) {
3865 __ testptr(tmp, tmp);
3866 __ jccb(Assembler::notZero, update);
3867 if (!TypeEntries::was_null_seen(current_klass)) {
3868 __ orptr(mdo_addr, TypeEntries::null_seen);
3869 }
3870 if (do_update) {
3871 #ifndef ASSERT
3872 __ jmpb(next);
3873 }
3874 #else
3875 __ jmp(next);
3876 }
3877 } else {
3878 __ testptr(tmp, tmp);
3879 __ jcc(Assembler::notZero, update);
3880 __ stop("unexpected null obj");
3881 #endif
3882 }
3883
3884 __ bind(update);
3885
3886 if (do_update) {
3887 #ifdef ASSERT
3888 if (exact_klass != nullptr) {
3889 Label ok;
3890 __ load_klass(tmp, tmp, tmp_load_klass);
3891 __ push(tmp);
3892 __ mov_metadata(tmp, exact_klass->constant_encoding());
3893 __ cmpptr(tmp, Address(rsp, 0));
3894 __ jcc(Assembler::equal, ok);
3895 __ stop("exact klass and actual klass differ");
3896 __ bind(ok);
3897 __ pop(tmp);
3898 }
3899 #endif
3900 if (!no_conflict) {
3901 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3902 if (exact_klass != nullptr) {
3903 __ mov_metadata(tmp, exact_klass->constant_encoding());
3904 } else {
3905 __ load_klass(tmp, tmp, tmp_load_klass);
3906 }
3907
3908 __ xorptr(tmp, mdo_addr);
3909 __ testptr(tmp, TypeEntries::type_klass_mask);
3910 // klass seen before, nothing to do. The unknown bit may have been
3911 // set already but no need to check.
3912 __ jccb(Assembler::zero, next);
3913
3914 __ testptr(tmp, TypeEntries::type_unknown);
3915 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3916
3917 if (TypeEntries::is_type_none(current_klass)) {
3918 __ cmpptr(mdo_addr, 0);
3919 __ jccb(Assembler::equal, none);
3920 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3921 __ jccb(Assembler::equal, none);
3922 // There is a chance that the checks above (re-reading profiling
3923 // data from memory) fail if another thread has just set the
3924 // profiling to this obj's klass
3925 __ xorptr(tmp, mdo_addr);
3926 __ testptr(tmp, TypeEntries::type_klass_mask);
3927 __ jccb(Assembler::zero, next);
3928 }
3929 } else {
3930 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3931 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3932
3933 __ movptr(tmp, mdo_addr);
3934 __ testptr(tmp, TypeEntries::type_unknown);
3935 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3936 }
3937
3938 // different than before. Cannot keep accurate profile.
3939 __ orptr(mdo_addr, TypeEntries::type_unknown);
3940
3941 if (TypeEntries::is_type_none(current_klass)) {
3942 __ jmpb(next);
3943
3944 __ bind(none);
3945 // first time here. Set profile type.
3946 __ movptr(mdo_addr, tmp);
3947 }
3948 } else {
3949 // There's a single possible klass at this profile point
3950 assert(exact_klass != nullptr, "should be");
3951 if (TypeEntries::is_type_none(current_klass)) {
3952 __ mov_metadata(tmp, exact_klass->constant_encoding());
3953 __ xorptr(tmp, mdo_addr);
3954 __ testptr(tmp, TypeEntries::type_klass_mask);
3955 #ifdef ASSERT
3956 __ jcc(Assembler::zero, next);
3957
3958 {
3959 Label ok;
3960 __ push(tmp);
3961 __ cmpptr(mdo_addr, 0);
3962 __ jcc(Assembler::equal, ok);
3963 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3964 __ jcc(Assembler::equal, ok);
3965 // may have been set by another thread
3966 __ mov_metadata(tmp, exact_klass->constant_encoding());
3967 __ xorptr(tmp, mdo_addr);
3968 __ testptr(tmp, TypeEntries::type_mask);
3969 __ jcc(Assembler::zero, ok);
3970
3971 __ stop("unexpected profiling mismatch");
3972 __ bind(ok);
3973 __ pop(tmp);
3974 }
3975 #else
3976 __ jccb(Assembler::zero, next);
3977 #endif
3978 // first time here. Set profile type.
3979 __ movptr(mdo_addr, tmp);
3980 } else {
3981 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3982 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3983
3984 __ movptr(tmp, mdo_addr);
3985 __ testptr(tmp, TypeEntries::type_unknown);
3986 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3987
3988 __ orptr(mdo_addr, TypeEntries::type_unknown);
3989 }
3990 }
3991
3992 __ bind(next);
3993 }
3994 }
3995
3996 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3997 Register obj = op->obj()->as_register();
3998 Register tmp = op->tmp()->as_pointer_register();
3999 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
4000 bool not_null = op->not_null();
4001 int flag = op->flag();
4002
4003 Label not_inline_type;
4004 if (!not_null) {
4005 __ testptr(obj, obj);
4006 __ jccb(Assembler::zero, not_inline_type);
4007 }
4008
4009 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
4010
4011 __ orb(mdo_addr, flag);
4012
4013 __ bind(not_inline_type);
4014 }
4015
4016 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
4017 Unimplemented();
4018 }
4019
4020
4021 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
4022 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
4023 }
4024
4025
4026 void LIR_Assembler::align_backward_branch_target() {
4027 __ align(BytesPerWord);
4028 }
4029
4030
4031 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
4032 if (left->is_single_cpu()) {
4033 __ negl(left->as_register());
4034 move_regs(left->as_register(), dest->as_register());
4035
4036 } else if (left->is_double_cpu()) {
4037 Register lo = left->as_register_lo();
4038 #ifdef _LP64
4039 Register dst = dest->as_register_lo();
4040 __ movptr(dst, lo);
4041 __ negptr(dst);
4042 #else
4043 Register hi = left->as_register_hi();
4044 __ lneg(hi, lo);
4045 if (dest->as_register_lo() == hi) {
4046 assert(dest->as_register_hi() != lo, "destroying register");
4047 move_regs(hi, dest->as_register_hi());
4048 move_regs(lo, dest->as_register_lo());
4049 } else {
4050 move_regs(lo, dest->as_register_lo());
4051 move_regs(hi, dest->as_register_hi());
4052 }
4053 #endif // _LP64
4054
4055 } else if (dest->is_single_xmm()) {
4056 #ifdef _LP64
4057 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4058 assert(tmp->is_valid(), "need temporary");
4059 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
4060 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
4061 }
4062 else
4063 #endif
4064 {
4065 assert(!tmp->is_valid(), "do not need temporary");
4066 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
4067 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
4068 }
4069 __ xorps(dest->as_xmm_float_reg(),
4070 ExternalAddress((address)float_signflip_pool),
4071 rscratch1);
4072 }
4073 } else if (dest->is_double_xmm()) {
4074 #ifdef _LP64
4075 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4076 assert(tmp->is_valid(), "need temporary");
4077 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
4078 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
4079 }
4080 else
4081 #endif
4082 {
4083 assert(!tmp->is_valid(), "do not need temporary");
4084 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
4085 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
4086 }
4087 __ xorpd(dest->as_xmm_double_reg(),
4088 ExternalAddress((address)double_signflip_pool),
4089 rscratch1);
4090 }
4091 #ifndef _LP64
4092 } else if (left->is_single_fpu() || left->is_double_fpu()) {
4093 assert(left->fpu() == 0, "arg must be on TOS");
4094 assert(dest->fpu() == 0, "dest must be TOS");
4095 __ fchs();
4096 #endif // !_LP64
4097
4098 } else {
4099 ShouldNotReachHere();
4100 }
4101 }
4102
4103
4104 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
4105 assert(src->is_address(), "must be an address");
4106 assert(dest->is_register(), "must be a register");
4107
4108 PatchingStub* patch = nullptr;
4109 if (patch_code != lir_patch_none) {
4110 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
4111 }
4112
4113 Register reg = dest->as_pointer_register();
4114 LIR_Address* addr = src->as_address_ptr();
4115 __ lea(reg, as_Address(addr));
4116
4117 if (patch != nullptr) {
4118 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
4119 }
4120 }
4121
4122
4123
4124 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
4125 assert(!tmp->is_valid(), "don't need temporary");
4126 __ call(RuntimeAddress(dest));
4127 if (info != nullptr) {
4128 add_call_info_here(info);
4129 }
4130 __ post_call_nop();
4131 }
4132
4133
4134 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
4135 assert(type == T_LONG, "only for volatile long fields");
4136
4137 if (info != nullptr) {
4138 add_debug_info_for_null_check_here(info);
4139 }
4140
4141 if (src->is_double_xmm()) {
4142 if (dest->is_double_cpu()) {
4143 #ifdef _LP64
4144 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
4145 #else
4146 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
4147 __ psrlq(src->as_xmm_double_reg(), 32);
4148 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
4149 #endif // _LP64
4150 } else if (dest->is_double_stack()) {
4151 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
4152 } else if (dest->is_address()) {
4153 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
4154 } else {
4155 ShouldNotReachHere();
4156 }
4157
4158 } else if (dest->is_double_xmm()) {
4159 if (src->is_double_stack()) {
4160 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
4161 } else if (src->is_address()) {
4162 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
4163 } else {
4164 ShouldNotReachHere();
4165 }
4166
4167 #ifndef _LP64
4168 } else if (src->is_double_fpu()) {
4169 assert(src->fpu_regnrLo() == 0, "must be TOS");
4170 if (dest->is_double_stack()) {
4171 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
4172 } else if (dest->is_address()) {
4173 __ fistp_d(as_Address(dest->as_address_ptr()));
4174 } else {
4175 ShouldNotReachHere();
4176 }
4177
4178 } else if (dest->is_double_fpu()) {
4179 assert(dest->fpu_regnrLo() == 0, "must be TOS");
4180 if (src->is_double_stack()) {
4181 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
4182 } else if (src->is_address()) {
4183 __ fild_d(as_Address(src->as_address_ptr()));
4184 } else {
4185 ShouldNotReachHere();
4186 }
4187 #endif // !_LP64
4188
4189 } else {
4190 ShouldNotReachHere();
4191 }
4192 }
4193
4194 #ifdef ASSERT
4195 // emit run-time assertion
4196 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
4197 assert(op->code() == lir_assert, "must be");
4198
4199 if (op->in_opr1()->is_valid()) {
4200 assert(op->in_opr2()->is_valid(), "both operands must be valid");
4201 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
4202 } else {
4203 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
4204 assert(op->condition() == lir_cond_always, "no other conditions allowed");
4205 }
4206
4207 Label ok;
4208 if (op->condition() != lir_cond_always) {
4209 Assembler::Condition acond = Assembler::zero;
4210 switch (op->condition()) {
4211 case lir_cond_equal: acond = Assembler::equal; break;
4212 case lir_cond_notEqual: acond = Assembler::notEqual; break;
4213 case lir_cond_less: acond = Assembler::less; break;
4214 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
4215 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
4216 case lir_cond_greater: acond = Assembler::greater; break;
4217 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
4218 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
4219 default: ShouldNotReachHere();
4220 }
4221 __ jcc(acond, ok);
4222 }
4223 if (op->halt()) {
4224 const char* str = __ code_string(op->msg());
4225 __ stop(str);
4226 } else {
4227 breakpoint();
4228 }
4229 __ bind(ok);
4230 }
4231 #endif
4232
4233 void LIR_Assembler::membar() {
4234 // QQQ sparc TSO uses this,
4235 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4236 }
4237
4238 void LIR_Assembler::membar_acquire() {
4239 // No x86 machines currently require load fences
4240 }
4241
4242 void LIR_Assembler::membar_release() {
4243 // No x86 machines currently require store fences
4244 }
4245
4246 void LIR_Assembler::membar_loadload() {
4247 // no-op
4248 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4249 }
4250
4251 void LIR_Assembler::membar_storestore() {
4252 // no-op
4253 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4254 }
4255
4256 void LIR_Assembler::membar_loadstore() {
4257 // no-op
4258 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4259 }
4260
4261 void LIR_Assembler::membar_storeload() {
4262 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4263 }
4264
4265 void LIR_Assembler::on_spin_wait() {
4266 __ pause ();
4267 }
4268
4269 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4270 assert(result_reg->is_register(), "check");
4271 #ifdef _LP64
4272 // __ get_thread(result_reg->as_register_lo());
4273 __ mov(result_reg->as_register(), r15_thread);
4274 #else
4275 __ get_thread(result_reg->as_register());
4276 #endif // _LP64
4277 }
4278
4279 void LIR_Assembler::check_orig_pc() {
4280 __ cmpptr(frame_map()->address_for_orig_pc_addr(), NULL_WORD);
4281 }
4282
4283 void LIR_Assembler::peephole(LIR_List*) {
4284 // do nothing for now
4285 }
4286
4287 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4288 assert(data == dest, "xchg/xadd uses only 2 operands");
4289
4290 if (data->type() == T_INT) {
4291 if (code == lir_xadd) {
4292 __ lock();
4293 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4294 } else {
4295 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4296 }
4297 } else if (data->is_oop()) {
4298 assert (code == lir_xchg, "xadd for oops");
4299 Register obj = data->as_register();
4300 #ifdef _LP64
4301 if (UseCompressedOops) {
4302 __ encode_heap_oop(obj);
4303 __ xchgl(obj, as_Address(src->as_address_ptr()));
4304 __ decode_heap_oop(obj);
4305 } else {
4306 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4307 }
4308 #else
4309 __ xchgl(obj, as_Address(src->as_address_ptr()));
4310 #endif
4311 } else if (data->type() == T_LONG) {
4312 #ifdef _LP64
4313 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4314 if (code == lir_xadd) {
4315 __ lock();
4316 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4317 } else {
4318 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4319 }
4320 #else
4321 ShouldNotReachHere();
4322 #endif
4323 } else {
4324 ShouldNotReachHere();
4325 }
4326 }
4327
4328 #undef __