1 /*
2 * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "compiler/oopMap.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_x86.hpp"
41 #include "oops/oop.inline.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register SYNC_header = rax; // synchronization header
78 const Register SHIFT_count = rcx; // where count for shift operations must be
79
80 #define __ _masm->
81
82
83 static void select_different_registers(Register preserve,
84 Register extra,
85 Register &tmp1,
86 Register &tmp2) {
87 if (tmp1 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp1 = extra;
90 } else if (tmp2 == preserve) {
91 assert_different_registers(tmp1, tmp2, extra);
92 tmp2 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2);
95 }
96
97
98
99 static void select_different_registers(Register preserve,
100 Register extra,
101 Register &tmp1,
102 Register &tmp2,
103 Register &tmp3) {
104 if (tmp1 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp1 = extra;
107 } else if (tmp2 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp2 = extra;
110 } else if (tmp3 == preserve) {
111 assert_different_registers(tmp1, tmp2, tmp3, extra);
112 tmp3 = extra;
113 }
114 assert_different_registers(preserve, tmp1, tmp2, tmp3);
115 }
116
117
118
119 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
120 if (opr->is_constant()) {
121 LIR_Const* constant = opr->as_constant_ptr();
122 switch (constant->type()) {
123 case T_INT: {
124 return true;
125 }
126
127 default:
128 return false;
129 }
130 }
131 return false;
132 }
133
134
135 LIR_Opr LIR_Assembler::receiverOpr() {
136 return FrameMap::receiver_opr;
137 }
138
139 LIR_Opr LIR_Assembler::osrBufferPointer() {
140 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
141 }
142
143 //--------------fpu register translations-----------------------
144
145
146 address LIR_Assembler::float_constant(float f) {
147 address const_addr = __ float_constant(f);
148 if (const_addr == nullptr) {
149 bailout("const section overflow");
150 return __ code()->consts()->start();
151 } else {
152 return const_addr;
153 }
154 }
155
156
157 address LIR_Assembler::double_constant(double d) {
158 address const_addr = __ double_constant(d);
159 if (const_addr == nullptr) {
160 bailout("const section overflow");
161 return __ code()->consts()->start();
162 } else {
163 return const_addr;
164 }
165 }
166
167 #ifndef _LP64
168 void LIR_Assembler::fpop() {
169 __ fpop();
170 }
171
172 void LIR_Assembler::fxch(int i) {
173 __ fxch(i);
174 }
175
176 void LIR_Assembler::fld(int i) {
177 __ fld_s(i);
178 }
179
180 void LIR_Assembler::ffree(int i) {
181 __ ffree(i);
182 }
183 #endif // !_LP64
184
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
188
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject(), rscratch1);
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
206
207 } else {
208 ShouldNotReachHere();
209 }
210 }
211
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
219
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
223
224 //-------------------------------------------
225
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
242
243 Register base = addr->base()->as_pointer_register();
244
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
253
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
260
261
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
266
267
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
271
272
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
278
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
286
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
290
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
303
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
309
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is null");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
336
337
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 return __ ic_check(CodeEntryAlignment);
341 }
342
343 void LIR_Assembler::clinit_barrier(ciMethod* method) {
344 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
345 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
346
347 Label L_skip_barrier;
348 Register klass = rscratch1;
349 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
350 assert(thread != noreg, "x86_32 not implemented");
351
352 __ mov_metadata(klass, method->holder()->constant_encoding());
353 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
354
355 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
356
357 __ bind(L_skip_barrier);
358 }
359
360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
361 jobject o = nullptr;
362 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
363 __ movoop(reg, o);
364 patching_epilog(patch, lir_patch_normal, reg, info);
365 }
366
367 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
368 Metadata* o = nullptr;
369 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
370 __ mov_metadata(reg, o);
371 patching_epilog(patch, lir_patch_normal, reg, info);
372 }
373
374 // This specifies the rsp decrement needed to build the frame
375 int LIR_Assembler::initial_frame_size_in_bytes() const {
376 // if rounding, must let FrameMap know!
377
378 // The frame_map records size in slots (32bit word)
379
380 // subtract two words to account for return address and link
381 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
382 }
383
384
385 int LIR_Assembler::emit_exception_handler() {
386 // generate code for exception handler
387 address handler_base = __ start_a_stub(exception_handler_size());
388 if (handler_base == nullptr) {
389 // not enough space left for the handler
390 bailout("exception handler overflow");
391 return -1;
392 }
393
394 int offset = code_offset();
395
396 // the exception oop and pc are in rax, and rdx
397 // no other registers need to be preserved, so invalidate them
398 __ invalidate_registers(false, true, true, false, true, true);
399
400 // check that there is really an exception
401 __ verify_not_null_oop(rax);
402
403 // search an exception handler (rax: exception oop, rdx: throwing pc)
404 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
405 __ should_not_reach_here();
406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
407 __ end_a_stub();
408
409 return offset;
410 }
411
412
413 // Emit the code to remove the frame from the stack in the exception
414 // unwind path.
415 int LIR_Assembler::emit_unwind_handler() {
416 #ifndef PRODUCT
417 if (CommentedAssembly) {
418 _masm->block_comment("Unwind handler");
419 }
420 #endif
421
422 int offset = code_offset();
423
424 // Fetch the exception from TLS and clear out exception related thread state
425 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
426 NOT_LP64(__ get_thread(thread));
427 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
428 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
429 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
430
431 __ bind(_unwind_handler_entry);
432 __ verify_not_null_oop(rax);
433 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
434 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
435 }
436
437 // Perform needed unlocking
438 MonitorExitStub* stub = nullptr;
439 if (method()->is_synchronized()) {
440 monitor_address(0, FrameMap::rax_opr);
441 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
442 if (LockingMode == LM_MONITOR) {
443 __ jmp(*stub->entry());
444 } else {
445 __ unlock_object(rdi, rsi, rax, *stub->entry());
446 }
447 __ bind(*stub->continuation());
448 }
449
450 if (compilation()->env()->dtrace_method_probes()) {
451 #ifdef _LP64
452 __ mov(rdi, r15_thread);
453 __ mov_metadata(rsi, method()->constant_encoding());
454 #else
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
458 #endif
459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
460 }
461
462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
463 __ mov(rax, rbx); // Restore the exception
464 }
465
466 // remove the activation and dispatch to the unwind handler
467 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
468 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
469
470 // Emit the slow path assembly
471 if (stub != nullptr) {
472 stub->emit_code(this);
473 }
474
475 return offset;
476 }
477
478
479 int LIR_Assembler::emit_deopt_handler() {
480 // generate code for exception handler
481 address handler_base = __ start_a_stub(deopt_handler_size());
482 if (handler_base == nullptr) {
483 // not enough space left for the handler
484 bailout("deopt handler overflow");
485 return -1;
486 }
487
488 int offset = code_offset();
489 InternalAddress here(__ pc());
490
491 __ pushptr(here.addr(), rscratch1);
492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
493 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
494 __ end_a_stub();
495
496 return offset;
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
501 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
502 assert(result->fpu() == 0, "result must already be on TOS");
503 }
504 if (InlineTypeReturnedAsFields) {
505 #ifndef _LP64
506 Unimplemented();
507 #endif
508 // Check if we are returning an non-null inline type and load its fields into registers
509 ciType* return_type = compilation()->method()->return_type();
510 if (return_type->is_inlinetype()) {
511 ciInlineKlass* vk = return_type->as_inline_klass();
512 if (vk->can_be_returned_as_fields()) {
513 address unpack_handler = vk->unpack_handler();
514 assert(unpack_handler != nullptr, "must be");
515 __ call(RuntimeAddress(unpack_handler));
516 }
517 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
518 Label skip;
519 __ test_oop_is_not_inline_type(rax, rscratch1, skip);
520
521 // Load fields from a buffered value with an inline class specific handler
522 __ load_klass(rdi, rax, rscratch1);
523 __ movptr(rdi, Address(rdi, InstanceKlass::adr_inlineklass_fixed_block_offset()));
524 __ movptr(rdi, Address(rdi, InlineKlass::unpack_handler_offset()));
525 // Unpack handler can be null if inline type is not scalarizable in returns
526 __ testptr(rdi, rdi);
527 __ jcc(Assembler::zero, skip);
528 __ call(rdi);
529
530 __ bind(skip);
531 }
532 // At this point, rax points to the value object (for interpreter or C1 caller).
533 // The fields of the object are copied into registers (for C2 caller).
534 }
535
536 // Pop the stack before the safepoint code
537 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
538
539 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
540 __ reserved_stack_check();
541 }
542
543 // Note: we do not need to round double result; float result has the right precision
544 // the poll sets the condition code, but no data registers
545
546 #ifdef _LP64
547 const Register thread = r15_thread;
548 #else
549 const Register thread = rbx;
550 __ get_thread(thread);
551 #endif
552 code_stub->set_safepoint_offset(__ offset());
553 __ relocate(relocInfo::poll_return_type);
554 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
555 __ ret(0);
556 }
557
558
559 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
560 return (__ store_inline_type_fields_to_buf(vk, false));
561 }
562
563 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
564 guarantee(info != nullptr, "Shouldn't be null");
565 int offset = __ offset();
566 #ifdef _LP64
567 const Register poll_addr = rscratch1;
568 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
569 #else
570 assert(tmp->is_cpu_register(), "needed");
571 const Register poll_addr = tmp->as_register();
572 __ get_thread(poll_addr);
573 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
574 #endif
575 add_debug_info_for_branch(info);
576 __ relocate(relocInfo::poll_type);
577 address pre_pc = __ pc();
578 __ testl(rax, Address(poll_addr, 0));
579 address post_pc = __ pc();
580 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
581 return offset;
582 }
583
584
585 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
586 if (from_reg != to_reg) __ mov(to_reg, from_reg);
587 }
588
589 void LIR_Assembler::swap_reg(Register a, Register b) {
590 __ xchgptr(a, b);
591 }
592
593
594 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
595 assert(src->is_constant(), "should not call otherwise");
596 assert(dest->is_register(), "should not call otherwise");
597 LIR_Const* c = src->as_constant_ptr();
598
599 switch (c->type()) {
600 case T_INT: {
601 assert(patch_code == lir_patch_none, "no patching handled here");
602 __ movl(dest->as_register(), c->as_jint());
603 break;
604 }
605
606 case T_ADDRESS: {
607 assert(patch_code == lir_patch_none, "no patching handled here");
608 __ movptr(dest->as_register(), c->as_jint());
609 break;
610 }
611
612 case T_LONG: {
613 assert(patch_code == lir_patch_none, "no patching handled here");
614 #ifdef _LP64
615 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
616 #else
617 __ movptr(dest->as_register_lo(), c->as_jint_lo());
618 __ movptr(dest->as_register_hi(), c->as_jint_hi());
619 #endif // _LP64
620 break;
621 }
622
623 case T_OBJECT: {
624 if (patch_code != lir_patch_none) {
625 jobject2reg_with_patching(dest->as_register(), info);
626 } else {
627 __ movoop(dest->as_register(), c->as_jobject());
628 }
629 break;
630 }
631
632 case T_METADATA: {
633 if (patch_code != lir_patch_none) {
634 klass2reg_with_patching(dest->as_register(), info);
635 } else {
636 __ mov_metadata(dest->as_register(), c->as_metadata());
637 }
638 break;
639 }
640
641 case T_FLOAT: {
642 if (dest->is_single_xmm()) {
643 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
644 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
645 } else {
646 __ movflt(dest->as_xmm_float_reg(),
647 InternalAddress(float_constant(c->as_jfloat())));
648 }
649 } else {
650 #ifndef _LP64
651 assert(dest->is_single_fpu(), "must be");
652 assert(dest->fpu_regnr() == 0, "dest must be TOS");
653 if (c->is_zero_float()) {
654 __ fldz();
655 } else if (c->is_one_float()) {
656 __ fld1();
657 } else {
658 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
659 }
660 #else
661 ShouldNotReachHere();
662 #endif // !_LP64
663 }
664 break;
665 }
666
667 case T_DOUBLE: {
668 if (dest->is_double_xmm()) {
669 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
670 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
671 } else {
672 __ movdbl(dest->as_xmm_double_reg(),
673 InternalAddress(double_constant(c->as_jdouble())));
674 }
675 } else {
676 #ifndef _LP64
677 assert(dest->is_double_fpu(), "must be");
678 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
679 if (c->is_zero_double()) {
680 __ fldz();
681 } else if (c->is_one_double()) {
682 __ fld1();
683 } else {
684 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
685 }
686 #else
687 ShouldNotReachHere();
688 #endif // !_LP64
689 }
690 break;
691 }
692
693 default:
694 ShouldNotReachHere();
695 }
696 }
697
698 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
699 assert(src->is_constant(), "should not call otherwise");
700 assert(dest->is_stack(), "should not call otherwise");
701 LIR_Const* c = src->as_constant_ptr();
702
703 switch (c->type()) {
704 case T_INT: // fall through
705 case T_FLOAT:
706 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
707 break;
708
709 case T_ADDRESS:
710 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
711 break;
712
713 case T_OBJECT:
714 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
715 break;
716
717 case T_LONG: // fall through
718 case T_DOUBLE:
719 #ifdef _LP64
720 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
721 lo_word_offset_in_bytes),
722 (intptr_t)c->as_jlong_bits(),
723 rscratch1);
724 #else
725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
726 lo_word_offset_in_bytes), c->as_jint_lo_bits());
727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
728 hi_word_offset_in_bytes), c->as_jint_hi_bits());
729 #endif // _LP64
730 break;
731
732 default:
733 ShouldNotReachHere();
734 }
735 }
736
737 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
738 assert(src->is_constant(), "should not call otherwise");
739 assert(dest->is_address(), "should not call otherwise");
740 LIR_Const* c = src->as_constant_ptr();
741 LIR_Address* addr = dest->as_address_ptr();
742
743 int null_check_here = code_offset();
744 switch (type) {
745 case T_INT: // fall through
746 case T_FLOAT:
747 __ movl(as_Address(addr), c->as_jint_bits());
748 break;
749
750 case T_ADDRESS:
751 __ movptr(as_Address(addr), c->as_jint_bits());
752 break;
753
754 case T_OBJECT: // fall through
755 case T_ARRAY:
756 if (c->as_jobject() == nullptr) {
757 if (UseCompressedOops && !wide) {
758 __ movl(as_Address(addr), NULL_WORD);
759 } else {
760 #ifdef _LP64
761 __ xorptr(rscratch1, rscratch1);
762 null_check_here = code_offset();
763 __ movptr(as_Address(addr), rscratch1);
764 #else
765 __ movptr(as_Address(addr), NULL_WORD);
766 #endif
767 }
768 } else {
769 if (is_literal_address(addr)) {
770 ShouldNotReachHere();
771 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
772 } else {
773 #ifdef _LP64
774 __ movoop(rscratch1, c->as_jobject());
775 if (UseCompressedOops && !wide) {
776 __ encode_heap_oop(rscratch1);
777 null_check_here = code_offset();
778 __ movl(as_Address_lo(addr), rscratch1);
779 } else {
780 null_check_here = code_offset();
781 __ movptr(as_Address_lo(addr), rscratch1);
782 }
783 #else
784 __ movoop(as_Address(addr), c->as_jobject(), noreg);
785 #endif
786 }
787 }
788 break;
789
790 case T_LONG: // fall through
791 case T_DOUBLE:
792 #ifdef _LP64
793 if (is_literal_address(addr)) {
794 ShouldNotReachHere();
795 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
796 } else {
797 __ movptr(r10, (intptr_t)c->as_jlong_bits());
798 null_check_here = code_offset();
799 __ movptr(as_Address_lo(addr), r10);
800 }
801 #else
802 // Always reachable in 32bit so this doesn't produce useless move literal
803 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
804 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
805 #endif // _LP64
806 break;
807
808 case T_BOOLEAN: // fall through
809 case T_BYTE:
810 __ movb(as_Address(addr), c->as_jint() & 0xFF);
811 break;
812
813 case T_CHAR: // fall through
814 case T_SHORT:
815 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
816 break;
817
818 default:
819 ShouldNotReachHere();
820 };
821
822 if (info != nullptr) {
823 add_debug_info_for_null_check(null_check_here, info);
824 }
825 }
826
827
828 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
829 assert(src->is_register(), "should not call otherwise");
830 assert(dest->is_register(), "should not call otherwise");
831
832 // move between cpu-registers
833 if (dest->is_single_cpu()) {
834 #ifdef _LP64
835 if (src->type() == T_LONG) {
836 // Can do LONG -> OBJECT
837 move_regs(src->as_register_lo(), dest->as_register());
838 return;
839 }
840 #endif
841 assert(src->is_single_cpu(), "must match");
842 if (src->type() == T_OBJECT) {
843 __ verify_oop(src->as_register());
844 }
845 move_regs(src->as_register(), dest->as_register());
846
847 } else if (dest->is_double_cpu()) {
848 #ifdef _LP64
849 if (is_reference_type(src->type())) {
850 // Surprising to me but we can see move of a long to t_object
851 __ verify_oop(src->as_register());
852 move_regs(src->as_register(), dest->as_register_lo());
853 return;
854 }
855 #endif
856 assert(src->is_double_cpu(), "must match");
857 Register f_lo = src->as_register_lo();
858 Register f_hi = src->as_register_hi();
859 Register t_lo = dest->as_register_lo();
860 Register t_hi = dest->as_register_hi();
861 #ifdef _LP64
862 assert(f_hi == f_lo, "must be same");
863 assert(t_hi == t_lo, "must be same");
864 move_regs(f_lo, t_lo);
865 #else
866 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
867
868
869 if (f_lo == t_hi && f_hi == t_lo) {
870 swap_reg(f_lo, f_hi);
871 } else if (f_hi == t_lo) {
872 assert(f_lo != t_hi, "overwriting register");
873 move_regs(f_hi, t_hi);
874 move_regs(f_lo, t_lo);
875 } else {
876 assert(f_hi != t_lo, "overwriting register");
877 move_regs(f_lo, t_lo);
878 move_regs(f_hi, t_hi);
879 }
880 #endif // LP64
881
882 #ifndef _LP64
883 // special moves from fpu-register to xmm-register
884 // necessary for method results
885 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
886 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
887 __ fld_s(Address(rsp, 0));
888 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
889 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
890 __ fld_d(Address(rsp, 0));
891 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
892 __ fstp_s(Address(rsp, 0));
893 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
894 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
895 __ fstp_d(Address(rsp, 0));
896 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
897 #endif // !_LP64
898
899 // move between xmm-registers
900 } else if (dest->is_single_xmm()) {
901 assert(src->is_single_xmm(), "must match");
902 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
903 } else if (dest->is_double_xmm()) {
904 assert(src->is_double_xmm(), "must match");
905 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
906
907 #ifndef _LP64
908 // move between fpu-registers (no instruction necessary because of fpu-stack)
909 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
910 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
911 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
912 #endif // !_LP64
913
914 } else {
915 ShouldNotReachHere();
916 }
917 }
918
919 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
920 assert(src->is_register(), "should not call otherwise");
921 assert(dest->is_stack(), "should not call otherwise");
922
923 if (src->is_single_cpu()) {
924 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
925 if (is_reference_type(type)) {
926 __ verify_oop(src->as_register());
927 __ movptr (dst, src->as_register());
928 } else if (type == T_METADATA || type == T_ADDRESS) {
929 __ movptr (dst, src->as_register());
930 } else {
931 __ movl (dst, src->as_register());
932 }
933
934 } else if (src->is_double_cpu()) {
935 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
936 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
937 __ movptr (dstLO, src->as_register_lo());
938 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
939
940 } else if (src->is_single_xmm()) {
941 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
942 __ movflt(dst_addr, src->as_xmm_float_reg());
943
944 } else if (src->is_double_xmm()) {
945 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
946 __ movdbl(dst_addr, src->as_xmm_double_reg());
947
948 #ifndef _LP64
949 } else if (src->is_single_fpu()) {
950 assert(src->fpu_regnr() == 0, "argument must be on TOS");
951 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
952 if (pop_fpu_stack) __ fstp_s (dst_addr);
953 else __ fst_s (dst_addr);
954
955 } else if (src->is_double_fpu()) {
956 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
957 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
958 if (pop_fpu_stack) __ fstp_d (dst_addr);
959 else __ fst_d (dst_addr);
960 #endif // !_LP64
961
962 } else {
963 ShouldNotReachHere();
964 }
965 }
966
967
968 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
969 LIR_Address* to_addr = dest->as_address_ptr();
970 PatchingStub* patch = nullptr;
971 Register compressed_src = rscratch1;
972
973 if (is_reference_type(type)) {
974 __ verify_oop(src->as_register());
975 #ifdef _LP64
976 if (UseCompressedOops && !wide) {
977 __ movptr(compressed_src, src->as_register());
978 __ encode_heap_oop(compressed_src);
979 if (patch_code != lir_patch_none) {
980 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
981 }
982 }
983 #endif
984 }
985
986 if (patch_code != lir_patch_none) {
987 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
988 Address toa = as_Address(to_addr);
989 assert(toa.disp() != 0, "must have");
990 }
991
992 int null_check_here = code_offset();
993 switch (type) {
994 case T_FLOAT: {
995 #ifdef _LP64
996 assert(src->is_single_xmm(), "not a float");
997 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
998 #else
999 if (src->is_single_xmm()) {
1000 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1001 } else {
1002 assert(src->is_single_fpu(), "must be");
1003 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1004 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1005 else __ fst_s (as_Address(to_addr));
1006 }
1007 #endif // _LP64
1008 break;
1009 }
1010
1011 case T_DOUBLE: {
1012 #ifdef _LP64
1013 assert(src->is_double_xmm(), "not a double");
1014 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1015 #else
1016 if (src->is_double_xmm()) {
1017 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1018 } else {
1019 assert(src->is_double_fpu(), "must be");
1020 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1021 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1022 else __ fst_d (as_Address(to_addr));
1023 }
1024 #endif // _LP64
1025 break;
1026 }
1027
1028 case T_ARRAY: // fall through
1029 case T_OBJECT: // fall through
1030 if (UseCompressedOops && !wide) {
1031 __ movl(as_Address(to_addr), compressed_src);
1032 } else {
1033 __ movptr(as_Address(to_addr), src->as_register());
1034 }
1035 break;
1036 case T_METADATA:
1037 // We get here to store a method pointer to the stack to pass to
1038 // a dtrace runtime call. This can't work on 64 bit with
1039 // compressed klass ptrs: T_METADATA can be a compressed klass
1040 // ptr or a 64 bit method pointer.
1041 LP64_ONLY(ShouldNotReachHere());
1042 __ movptr(as_Address(to_addr), src->as_register());
1043 break;
1044 case T_ADDRESS:
1045 __ movptr(as_Address(to_addr), src->as_register());
1046 break;
1047 case T_INT:
1048 __ movl(as_Address(to_addr), src->as_register());
1049 break;
1050
1051 case T_LONG: {
1052 Register from_lo = src->as_register_lo();
1053 Register from_hi = src->as_register_hi();
1054 #ifdef _LP64
1055 __ movptr(as_Address_lo(to_addr), from_lo);
1056 #else
1057 Register base = to_addr->base()->as_register();
1058 Register index = noreg;
1059 if (to_addr->index()->is_register()) {
1060 index = to_addr->index()->as_register();
1061 }
1062 if (base == from_lo || index == from_lo) {
1063 assert(base != from_hi, "can't be");
1064 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1065 __ movl(as_Address_hi(to_addr), from_hi);
1066 if (patch != nullptr) {
1067 patching_epilog(patch, lir_patch_high, base, info);
1068 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1069 patch_code = lir_patch_low;
1070 }
1071 __ movl(as_Address_lo(to_addr), from_lo);
1072 } else {
1073 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1074 __ movl(as_Address_lo(to_addr), from_lo);
1075 if (patch != nullptr) {
1076 patching_epilog(patch, lir_patch_low, base, info);
1077 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1078 patch_code = lir_patch_high;
1079 }
1080 __ movl(as_Address_hi(to_addr), from_hi);
1081 }
1082 #endif // _LP64
1083 break;
1084 }
1085
1086 case T_BYTE: // fall through
1087 case T_BOOLEAN: {
1088 Register src_reg = src->as_register();
1089 Address dst_addr = as_Address(to_addr);
1090 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1091 __ movb(dst_addr, src_reg);
1092 break;
1093 }
1094
1095 case T_CHAR: // fall through
1096 case T_SHORT:
1097 __ movw(as_Address(to_addr), src->as_register());
1098 break;
1099
1100 default:
1101 ShouldNotReachHere();
1102 }
1103 if (info != nullptr) {
1104 add_debug_info_for_null_check(null_check_here, info);
1105 }
1106
1107 if (patch_code != lir_patch_none) {
1108 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1109 }
1110 }
1111
1112
1113 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1114 assert(src->is_stack(), "should not call otherwise");
1115 assert(dest->is_register(), "should not call otherwise");
1116
1117 if (dest->is_single_cpu()) {
1118 if (is_reference_type(type)) {
1119 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1120 __ verify_oop(dest->as_register());
1121 } else if (type == T_METADATA || type == T_ADDRESS) {
1122 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1123 } else {
1124 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1125 }
1126
1127 } else if (dest->is_double_cpu()) {
1128 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1129 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1130 __ movptr(dest->as_register_lo(), src_addr_LO);
1131 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1132
1133 } else if (dest->is_single_xmm()) {
1134 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1135 __ movflt(dest->as_xmm_float_reg(), src_addr);
1136
1137 } else if (dest->is_double_xmm()) {
1138 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1139 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1140
1141 #ifndef _LP64
1142 } else if (dest->is_single_fpu()) {
1143 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1144 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1145 __ fld_s(src_addr);
1146
1147 } else if (dest->is_double_fpu()) {
1148 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1149 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1150 __ fld_d(src_addr);
1151 #endif // _LP64
1152
1153 } else {
1154 ShouldNotReachHere();
1155 }
1156 }
1157
1158
1159 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1160 if (src->is_single_stack()) {
1161 if (is_reference_type(type)) {
1162 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1163 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1164 } else {
1165 #ifndef _LP64
1166 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1167 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1168 #else
1169 //no pushl on 64bits
1170 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1171 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1172 #endif
1173 }
1174
1175 } else if (src->is_double_stack()) {
1176 #ifdef _LP64
1177 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1178 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1179 #else
1180 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1181 // push and pop the part at src + wordSize, adding wordSize for the previous push
1182 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1183 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1184 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1185 #endif // _LP64
1186
1187 } else {
1188 ShouldNotReachHere();
1189 }
1190 }
1191
1192
1193 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1194 assert(src->is_address(), "should not call otherwise");
1195 assert(dest->is_register(), "should not call otherwise");
1196
1197 LIR_Address* addr = src->as_address_ptr();
1198 Address from_addr = as_Address(addr);
1199
1200 if (addr->base()->type() == T_OBJECT) {
1201 __ verify_oop(addr->base()->as_pointer_register());
1202 }
1203
1204 switch (type) {
1205 case T_BOOLEAN: // fall through
1206 case T_BYTE: // fall through
1207 case T_CHAR: // fall through
1208 case T_SHORT:
1209 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1210 // on pre P6 processors we may get partial register stalls
1211 // so blow away the value of to_rinfo before loading a
1212 // partial word into it. Do it here so that it precedes
1213 // the potential patch point below.
1214 __ xorptr(dest->as_register(), dest->as_register());
1215 }
1216 break;
1217 default:
1218 break;
1219 }
1220
1221 PatchingStub* patch = nullptr;
1222 if (patch_code != lir_patch_none) {
1223 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1224 assert(from_addr.disp() != 0, "must have");
1225 }
1226 if (info != nullptr) {
1227 add_debug_info_for_null_check_here(info);
1228 }
1229
1230 switch (type) {
1231 case T_FLOAT: {
1232 if (dest->is_single_xmm()) {
1233 __ movflt(dest->as_xmm_float_reg(), from_addr);
1234 } else {
1235 #ifndef _LP64
1236 assert(dest->is_single_fpu(), "must be");
1237 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1238 __ fld_s(from_addr);
1239 #else
1240 ShouldNotReachHere();
1241 #endif // !LP64
1242 }
1243 break;
1244 }
1245
1246 case T_DOUBLE: {
1247 if (dest->is_double_xmm()) {
1248 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1249 } else {
1250 #ifndef _LP64
1251 assert(dest->is_double_fpu(), "must be");
1252 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1253 __ fld_d(from_addr);
1254 #else
1255 ShouldNotReachHere();
1256 #endif // !LP64
1257 }
1258 break;
1259 }
1260
1261 case T_OBJECT: // fall through
1262 case T_ARRAY: // fall through
1263 if (UseCompressedOops && !wide) {
1264 __ movl(dest->as_register(), from_addr);
1265 } else {
1266 __ movptr(dest->as_register(), from_addr);
1267 }
1268 break;
1269
1270 case T_ADDRESS:
1271 __ movptr(dest->as_register(), from_addr);
1272 break;
1273 case T_INT:
1274 __ movl(dest->as_register(), from_addr);
1275 break;
1276
1277 case T_LONG: {
1278 Register to_lo = dest->as_register_lo();
1279 Register to_hi = dest->as_register_hi();
1280 #ifdef _LP64
1281 __ movptr(to_lo, as_Address_lo(addr));
1282 #else
1283 Register base = addr->base()->as_register();
1284 Register index = noreg;
1285 if (addr->index()->is_register()) {
1286 index = addr->index()->as_register();
1287 }
1288 if ((base == to_lo && index == to_hi) ||
1289 (base == to_hi && index == to_lo)) {
1290 // addresses with 2 registers are only formed as a result of
1291 // array access so this code will never have to deal with
1292 // patches or null checks.
1293 assert(info == nullptr && patch == nullptr, "must be");
1294 __ lea(to_hi, as_Address(addr));
1295 __ movl(to_lo, Address(to_hi, 0));
1296 __ movl(to_hi, Address(to_hi, BytesPerWord));
1297 } else if (base == to_lo || index == to_lo) {
1298 assert(base != to_hi, "can't be");
1299 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1300 __ movl(to_hi, as_Address_hi(addr));
1301 if (patch != nullptr) {
1302 patching_epilog(patch, lir_patch_high, base, info);
1303 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1304 patch_code = lir_patch_low;
1305 }
1306 __ movl(to_lo, as_Address_lo(addr));
1307 } else {
1308 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1309 __ movl(to_lo, as_Address_lo(addr));
1310 if (patch != nullptr) {
1311 patching_epilog(patch, lir_patch_low, base, info);
1312 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1313 patch_code = lir_patch_high;
1314 }
1315 __ movl(to_hi, as_Address_hi(addr));
1316 }
1317 #endif // _LP64
1318 break;
1319 }
1320
1321 case T_BOOLEAN: // fall through
1322 case T_BYTE: {
1323 Register dest_reg = dest->as_register();
1324 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326 __ movsbl(dest_reg, from_addr);
1327 } else {
1328 __ movb(dest_reg, from_addr);
1329 __ shll(dest_reg, 24);
1330 __ sarl(dest_reg, 24);
1331 }
1332 break;
1333 }
1334
1335 case T_CHAR: {
1336 Register dest_reg = dest->as_register();
1337 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1338 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1339 __ movzwl(dest_reg, from_addr);
1340 } else {
1341 __ movw(dest_reg, from_addr);
1342 }
1343 break;
1344 }
1345
1346 case T_SHORT: {
1347 Register dest_reg = dest->as_register();
1348 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1349 __ movswl(dest_reg, from_addr);
1350 } else {
1351 __ movw(dest_reg, from_addr);
1352 __ shll(dest_reg, 16);
1353 __ sarl(dest_reg, 16);
1354 }
1355 break;
1356 }
1357
1358 default:
1359 ShouldNotReachHere();
1360 }
1361
1362 if (patch != nullptr) {
1363 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1364 }
1365
1366 if (is_reference_type(type)) {
1367 #ifdef _LP64
1368 if (UseCompressedOops && !wide) {
1369 __ decode_heap_oop(dest->as_register());
1370 }
1371 #endif
1372
1373 if (!(UseZGC && !ZGenerational)) {
1374 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1375 __ verify_oop(dest->as_register());
1376 }
1377 }
1378 }
1379
1380
1381 NEEDS_CLEANUP; // This could be static?
1382 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1383 int elem_size = type2aelembytes(type);
1384 switch (elem_size) {
1385 case 1: return Address::times_1;
1386 case 2: return Address::times_2;
1387 case 4: return Address::times_4;
1388 case 8: return Address::times_8;
1389 }
1390 ShouldNotReachHere();
1391 return Address::no_scale;
1392 }
1393
1394
1395 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1396 switch (op->code()) {
1397 case lir_idiv:
1398 case lir_irem:
1399 arithmetic_idiv(op->code(),
1400 op->in_opr1(),
1401 op->in_opr2(),
1402 op->in_opr3(),
1403 op->result_opr(),
1404 op->info());
1405 break;
1406 case lir_fmad:
1407 __ fmad(op->result_opr()->as_xmm_double_reg(),
1408 op->in_opr1()->as_xmm_double_reg(),
1409 op->in_opr2()->as_xmm_double_reg(),
1410 op->in_opr3()->as_xmm_double_reg());
1411 break;
1412 case lir_fmaf:
1413 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1414 op->in_opr1()->as_xmm_float_reg(),
1415 op->in_opr2()->as_xmm_float_reg(),
1416 op->in_opr3()->as_xmm_float_reg());
1417 break;
1418 default: ShouldNotReachHere(); break;
1419 }
1420 }
1421
1422 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1423 #ifdef ASSERT
1424 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1425 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1426 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1427 #endif
1428
1429 if (op->cond() == lir_cond_always) {
1430 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1431 __ jmp (*(op->label()));
1432 } else {
1433 Assembler::Condition acond = Assembler::zero;
1434 if (op->code() == lir_cond_float_branch) {
1435 assert(op->ublock() != nullptr, "must have unordered successor");
1436 __ jcc(Assembler::parity, *(op->ublock()->label()));
1437 switch(op->cond()) {
1438 case lir_cond_equal: acond = Assembler::equal; break;
1439 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1440 case lir_cond_less: acond = Assembler::below; break;
1441 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1442 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1443 case lir_cond_greater: acond = Assembler::above; break;
1444 default: ShouldNotReachHere();
1445 }
1446 } else {
1447 switch (op->cond()) {
1448 case lir_cond_equal: acond = Assembler::equal; break;
1449 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1450 case lir_cond_less: acond = Assembler::less; break;
1451 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1452 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1453 case lir_cond_greater: acond = Assembler::greater; break;
1454 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1455 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1456 default: ShouldNotReachHere();
1457 }
1458 }
1459 __ jcc(acond,*(op->label()));
1460 }
1461 }
1462
1463 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1464 LIR_Opr src = op->in_opr();
1465 LIR_Opr dest = op->result_opr();
1466
1467 switch (op->bytecode()) {
1468 case Bytecodes::_i2l:
1469 #ifdef _LP64
1470 __ movl2ptr(dest->as_register_lo(), src->as_register());
1471 #else
1472 move_regs(src->as_register(), dest->as_register_lo());
1473 move_regs(src->as_register(), dest->as_register_hi());
1474 __ sarl(dest->as_register_hi(), 31);
1475 #endif // LP64
1476 break;
1477
1478 case Bytecodes::_l2i:
1479 #ifdef _LP64
1480 __ movl(dest->as_register(), src->as_register_lo());
1481 #else
1482 move_regs(src->as_register_lo(), dest->as_register());
1483 #endif
1484 break;
1485
1486 case Bytecodes::_i2b:
1487 move_regs(src->as_register(), dest->as_register());
1488 __ sign_extend_byte(dest->as_register());
1489 break;
1490
1491 case Bytecodes::_i2c:
1492 move_regs(src->as_register(), dest->as_register());
1493 __ andl(dest->as_register(), 0xFFFF);
1494 break;
1495
1496 case Bytecodes::_i2s:
1497 move_regs(src->as_register(), dest->as_register());
1498 __ sign_extend_short(dest->as_register());
1499 break;
1500
1501
1502 #ifdef _LP64
1503 case Bytecodes::_f2d:
1504 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1505 break;
1506
1507 case Bytecodes::_d2f:
1508 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1509 break;
1510
1511 case Bytecodes::_i2f:
1512 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1513 break;
1514
1515 case Bytecodes::_i2d:
1516 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1517 break;
1518
1519 case Bytecodes::_l2f:
1520 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1521 break;
1522
1523 case Bytecodes::_l2d:
1524 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1525 break;
1526
1527 case Bytecodes::_f2i:
1528 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1529 break;
1530
1531 case Bytecodes::_d2i:
1532 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1533 break;
1534
1535 case Bytecodes::_f2l:
1536 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1537 break;
1538
1539 case Bytecodes::_d2l:
1540 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1541 break;
1542 #else
1543 case Bytecodes::_f2d:
1544 case Bytecodes::_d2f:
1545 if (dest->is_single_xmm()) {
1546 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1547 } else if (dest->is_double_xmm()) {
1548 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1549 } else {
1550 assert(src->fpu() == dest->fpu(), "register must be equal");
1551 // do nothing (float result is rounded later through spilling)
1552 }
1553 break;
1554
1555 case Bytecodes::_i2f:
1556 case Bytecodes::_i2d:
1557 if (dest->is_single_xmm()) {
1558 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1559 } else if (dest->is_double_xmm()) {
1560 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1561 } else {
1562 assert(dest->fpu() == 0, "result must be on TOS");
1563 __ movl(Address(rsp, 0), src->as_register());
1564 __ fild_s(Address(rsp, 0));
1565 }
1566 break;
1567
1568 case Bytecodes::_l2f:
1569 case Bytecodes::_l2d:
1570 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1571 assert(dest->fpu() == 0, "result must be on TOS");
1572 __ movptr(Address(rsp, 0), src->as_register_lo());
1573 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1574 __ fild_d(Address(rsp, 0));
1575 // float result is rounded later through spilling
1576 break;
1577
1578 case Bytecodes::_f2i:
1579 case Bytecodes::_d2i:
1580 if (src->is_single_xmm()) {
1581 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1582 } else if (src->is_double_xmm()) {
1583 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1584 } else {
1585 assert(src->fpu() == 0, "input must be on TOS");
1586 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1587 __ fist_s(Address(rsp, 0));
1588 __ movl(dest->as_register(), Address(rsp, 0));
1589 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1590 }
1591 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1592 assert(op->stub() != nullptr, "stub required");
1593 __ cmpl(dest->as_register(), 0x80000000);
1594 __ jcc(Assembler::equal, *op->stub()->entry());
1595 __ bind(*op->stub()->continuation());
1596 break;
1597
1598 case Bytecodes::_f2l:
1599 case Bytecodes::_d2l:
1600 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1601 assert(src->fpu() == 0, "input must be on TOS");
1602 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1603
1604 // instruction sequence too long to inline it here
1605 {
1606 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1607 }
1608 break;
1609 #endif // _LP64
1610
1611 default: ShouldNotReachHere();
1612 }
1613 }
1614
1615 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1616 if (op->init_check()) {
1617 add_debug_info_for_null_check_here(op->stub()->info());
1618 __ cmpb(Address(op->klass()->as_register(),
1619 InstanceKlass::init_state_offset()),
1620 InstanceKlass::fully_initialized);
1621 __ jcc(Assembler::notEqual, *op->stub()->entry());
1622 }
1623 __ allocate_object(op->obj()->as_register(),
1624 op->tmp1()->as_register(),
1625 op->tmp2()->as_register(),
1626 op->header_size(),
1627 op->object_size(),
1628 op->klass()->as_register(),
1629 *op->stub()->entry());
1630 __ bind(*op->stub()->continuation());
1631 }
1632
1633 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1634 Register len = op->len()->as_register();
1635 LP64_ONLY( __ movslq(len, len); )
1636
1637 if (UseSlowPath || op->is_null_free() ||
1638 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1639 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1640 __ jmp(*op->stub()->entry());
1641 } else {
1642 Register tmp1 = op->tmp1()->as_register();
1643 Register tmp2 = op->tmp2()->as_register();
1644 Register tmp3 = op->tmp3()->as_register();
1645 if (len == tmp1) {
1646 tmp1 = tmp3;
1647 } else if (len == tmp2) {
1648 tmp2 = tmp3;
1649 } else if (len == tmp3) {
1650 // everything is ok
1651 } else {
1652 __ mov(tmp3, len);
1653 }
1654 __ allocate_array(op->obj()->as_register(),
1655 len,
1656 tmp1,
1657 tmp2,
1658 arrayOopDesc::header_size(op->type()),
1659 array_element_size(op->type()),
1660 op->klass()->as_register(),
1661 *op->stub()->entry());
1662 }
1663 __ bind(*op->stub()->continuation());
1664 }
1665
1666 void LIR_Assembler::type_profile_helper(Register mdo,
1667 ciMethodData *md, ciProfileData *data,
1668 Register recv, Label* update_done) {
1669 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1670 Label next_test;
1671 // See if the receiver is receiver[n].
1672 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1673 __ jccb(Assembler::notEqual, next_test);
1674 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1675 __ addptr(data_addr, DataLayout::counter_increment);
1676 __ jmp(*update_done);
1677 __ bind(next_test);
1678 }
1679
1680 // Didn't find receiver; find next empty slot and fill it in
1681 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1682 Label next_test;
1683 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1684 __ cmpptr(recv_addr, NULL_WORD);
1685 __ jccb(Assembler::notEqual, next_test);
1686 __ movptr(recv_addr, recv);
1687 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1688 __ jmp(*update_done);
1689 __ bind(next_test);
1690 }
1691 }
1692
1693 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1694 // we always need a stub for the failure case.
1695 CodeStub* stub = op->stub();
1696 Register obj = op->object()->as_register();
1697 Register k_RInfo = op->tmp1()->as_register();
1698 Register klass_RInfo = op->tmp2()->as_register();
1699 Register dst = op->result_opr()->as_register();
1700 ciKlass* k = op->klass();
1701 Register Rtmp1 = noreg;
1702 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1703
1704 // check if it needs to be profiled
1705 ciMethodData* md = nullptr;
1706 ciProfileData* data = nullptr;
1707
1708 if (op->should_profile()) {
1709 ciMethod* method = op->profiled_method();
1710 assert(method != nullptr, "Should have method");
1711 int bci = op->profiled_bci();
1712 md = method->method_data_or_null();
1713 assert(md != nullptr, "Sanity");
1714 data = md->bci_to_data(bci);
1715 assert(data != nullptr, "need data for type check");
1716 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1717 }
1718 Label* success_target = success;
1719 Label* failure_target = failure;
1720
1721 if (obj == k_RInfo) {
1722 k_RInfo = dst;
1723 } else if (obj == klass_RInfo) {
1724 klass_RInfo = dst;
1725 }
1726 if (k->is_loaded() && !UseCompressedClassPointers) {
1727 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1728 } else {
1729 Rtmp1 = op->tmp3()->as_register();
1730 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1731 }
1732
1733 assert_different_registers(obj, k_RInfo, klass_RInfo);
1734
1735 if (op->need_null_check()) {
1736 __ testptr(obj, obj);
1737 if (op->should_profile()) {
1738 Label not_null;
1739 Register mdo = klass_RInfo;
1740 __ mov_metadata(mdo, md->constant_encoding());
1741 __ jccb(Assembler::notEqual, not_null);
1742 // Object is null; update MDO and exit
1743 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1744 int header_bits = BitData::null_seen_byte_constant();
1745 __ orb(data_addr, header_bits);
1746 __ jmp(*obj_is_null);
1747 __ bind(not_null);
1748
1749 Label update_done;
1750 Register recv = k_RInfo;
1751 __ load_klass(recv, obj, tmp_load_klass);
1752 type_profile_helper(mdo, md, data, recv, &update_done);
1753
1754 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1755 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1756
1757 __ bind(update_done);
1758 } else {
1759 __ jcc(Assembler::equal, *obj_is_null);
1760 }
1761 }
1762
1763 if (!k->is_loaded()) {
1764 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1765 } else {
1766 #ifdef _LP64
1767 __ mov_metadata(k_RInfo, k->constant_encoding());
1768 #endif // _LP64
1769 }
1770 __ verify_oop(obj);
1771
1772 if (op->fast_check()) {
1773 // get object class
1774 // not a safepoint as obj null check happens earlier
1775 #ifdef _LP64
1776 if (UseCompressedClassPointers) {
1777 __ load_klass(Rtmp1, obj, tmp_load_klass);
1778 __ cmpptr(k_RInfo, Rtmp1);
1779 } else {
1780 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1781 }
1782 #else
1783 if (k->is_loaded()) {
1784 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1785 } else {
1786 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1787 }
1788 #endif
1789 __ jcc(Assembler::notEqual, *failure_target);
1790 // successful cast, fall through to profile or jump
1791 } else {
1792 // get object class
1793 // not a safepoint as obj null check happens earlier
1794 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1795 if (k->is_loaded()) {
1796 // See if we get an immediate positive hit
1797 #ifdef _LP64
1798 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1799 #else
1800 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1801 #endif // _LP64
1802 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1803 __ jcc(Assembler::notEqual, *failure_target);
1804 // successful cast, fall through to profile or jump
1805 } else {
1806 // See if we get an immediate positive hit
1807 __ jcc(Assembler::equal, *success_target);
1808 // check for self
1809 #ifdef _LP64
1810 __ cmpptr(klass_RInfo, k_RInfo);
1811 #else
1812 __ cmpklass(klass_RInfo, k->constant_encoding());
1813 #endif // _LP64
1814 __ jcc(Assembler::equal, *success_target);
1815
1816 __ push(klass_RInfo);
1817 #ifdef _LP64
1818 __ push(k_RInfo);
1819 #else
1820 __ pushklass(k->constant_encoding(), noreg);
1821 #endif // _LP64
1822 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1823 __ pop(klass_RInfo);
1824 __ pop(klass_RInfo);
1825 // result is a boolean
1826 __ testl(klass_RInfo, klass_RInfo);
1827 __ jcc(Assembler::equal, *failure_target);
1828 // successful cast, fall through to profile or jump
1829 }
1830 } else {
1831 // perform the fast part of the checking logic
1832 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1833 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1834 __ push(klass_RInfo);
1835 __ push(k_RInfo);
1836 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1837 __ pop(klass_RInfo);
1838 __ pop(k_RInfo);
1839 // result is a boolean
1840 __ testl(k_RInfo, k_RInfo);
1841 __ jcc(Assembler::equal, *failure_target);
1842 // successful cast, fall through to profile or jump
1843 }
1844 }
1845 __ jmp(*success);
1846 }
1847
1848
1849 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1850 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1851 LIR_Code code = op->code();
1852 if (code == lir_store_check) {
1853 Register value = op->object()->as_register();
1854 Register array = op->array()->as_register();
1855 Register k_RInfo = op->tmp1()->as_register();
1856 Register klass_RInfo = op->tmp2()->as_register();
1857 Register Rtmp1 = op->tmp3()->as_register();
1858
1859 CodeStub* stub = op->stub();
1860
1861 // check if it needs to be profiled
1862 ciMethodData* md = nullptr;
1863 ciProfileData* data = nullptr;
1864
1865 if (op->should_profile()) {
1866 ciMethod* method = op->profiled_method();
1867 assert(method != nullptr, "Should have method");
1868 int bci = op->profiled_bci();
1869 md = method->method_data_or_null();
1870 assert(md != nullptr, "Sanity");
1871 data = md->bci_to_data(bci);
1872 assert(data != nullptr, "need data for type check");
1873 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1874 }
1875 Label done;
1876 Label* success_target = &done;
1877 Label* failure_target = stub->entry();
1878
1879 __ testptr(value, value);
1880 if (op->should_profile()) {
1881 Label not_null;
1882 Register mdo = klass_RInfo;
1883 __ mov_metadata(mdo, md->constant_encoding());
1884 __ jccb(Assembler::notEqual, not_null);
1885 // Object is null; update MDO and exit
1886 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1887 int header_bits = BitData::null_seen_byte_constant();
1888 __ orb(data_addr, header_bits);
1889 __ jmp(done);
1890 __ bind(not_null);
1891
1892 Label update_done;
1893 Register recv = k_RInfo;
1894 __ load_klass(recv, value, tmp_load_klass);
1895 type_profile_helper(mdo, md, data, recv, &update_done);
1896
1897 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1898 __ addptr(counter_addr, DataLayout::counter_increment);
1899 __ bind(update_done);
1900 } else {
1901 __ jcc(Assembler::equal, done);
1902 }
1903
1904 add_debug_info_for_null_check_here(op->info_for_exception());
1905 __ load_klass(k_RInfo, array, tmp_load_klass);
1906 __ load_klass(klass_RInfo, value, tmp_load_klass);
1907
1908 // get instance klass (it's already uncompressed)
1909 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1910 // perform the fast part of the checking logic
1911 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1912 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1913 __ push(klass_RInfo);
1914 __ push(k_RInfo);
1915 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1916 __ pop(klass_RInfo);
1917 __ pop(k_RInfo);
1918 // result is a boolean
1919 __ testl(k_RInfo, k_RInfo);
1920 __ jcc(Assembler::equal, *failure_target);
1921 // fall through to the success case
1922
1923 __ bind(done);
1924 } else
1925 if (code == lir_checkcast) {
1926 Register obj = op->object()->as_register();
1927 Register dst = op->result_opr()->as_register();
1928 Label success;
1929 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1930 __ bind(success);
1931 if (dst != obj) {
1932 __ mov(dst, obj);
1933 }
1934 } else
1935 if (code == lir_instanceof) {
1936 Register obj = op->object()->as_register();
1937 Register dst = op->result_opr()->as_register();
1938 Label success, failure, done;
1939 emit_typecheck_helper(op, &success, &failure, &failure);
1940 __ bind(failure);
1941 __ xorptr(dst, dst);
1942 __ jmpb(done);
1943 __ bind(success);
1944 __ movptr(dst, 1);
1945 __ bind(done);
1946 } else {
1947 ShouldNotReachHere();
1948 }
1949
1950 }
1951
1952 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1953 // We are loading/storing from/to an array that *may* be a flat array (the
1954 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1955 // If this array is a flat array, take the slow path.
1956 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1957 if (!op->value()->is_illegal()) {
1958 // The array is not a flat array, but it might be null-free. If we are storing
1959 // a null into a null-free array, take the slow path (which will throw NPE).
1960 Label skip;
1961 __ cmpptr(op->value()->as_register(), NULL_WORD);
1962 __ jcc(Assembler::notEqual, skip);
1963 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1964 __ bind(skip);
1965 }
1966 }
1967
1968 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1969 // We are storing into an array that *may* be null-free (the declared type is
1970 // Object[], abstract[], interface[] or VT.ref[]).
1971 Label test_mark_word;
1972 Register tmp = op->tmp()->as_register();
1973 __ movptr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1974 __ testl(tmp, markWord::unlocked_value);
1975 __ jccb(Assembler::notZero, test_mark_word);
1976 __ load_prototype_header(tmp, op->array()->as_register(), rscratch1);
1977 __ bind(test_mark_word);
1978 __ testl(tmp, markWord::null_free_array_bit_in_place);
1979 }
1980
1981 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1982 Label L_oops_equal;
1983 Label L_oops_not_equal;
1984 Label L_end;
1985
1986 Register left = op->left()->as_register();
1987 Register right = op->right()->as_register();
1988
1989 __ cmpptr(left, right);
1990 __ jcc(Assembler::equal, L_oops_equal);
1991
1992 // (1) Null check -- if one of the operands is null, the other must not be null (because
1993 // the two references are not equal), so they are not substitutable,
1994 // FIXME: do null check only if the operand is nullable
1995 __ testptr(left, right);
1996 __ jcc(Assembler::zero, L_oops_not_equal);
1997
1998 ciKlass* left_klass = op->left_klass();
1999 ciKlass* right_klass = op->right_klass();
2000
2001 // (2) Inline type check -- if either of the operands is not a inline type,
2002 // they are not substitutable. We do this only if we are not sure that the
2003 // operands are inline type
2004 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
2005 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
2006 Register tmp1 = op->tmp1()->as_register();
2007 __ movptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2008 __ andptr(tmp1, Address(left, oopDesc::mark_offset_in_bytes()));
2009 __ andptr(tmp1, Address(right, oopDesc::mark_offset_in_bytes()));
2010 __ cmpptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2011 __ jcc(Assembler::notEqual, L_oops_not_equal);
2012 }
2013
2014 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
2015 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
2016 // No need to load klass -- the operands are statically known to be the same inline klass.
2017 __ jmp(*op->stub()->entry());
2018 } else {
2019 Register left_klass_op = op->left_klass_op()->as_register();
2020 Register right_klass_op = op->right_klass_op()->as_register();
2021
2022 if (UseCompressedClassPointers) {
2023 __ movl(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
2024 __ movl(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2025 __ cmpl(left_klass_op, right_klass_op);
2026 } else {
2027 __ movptr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
2028 __ movptr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2029 __ cmpptr(left_klass_op, right_klass_op);
2030 }
2031
2032 __ jcc(Assembler::equal, *op->stub()->entry()); // same klass -> do slow check
2033 // fall through to L_oops_not_equal
2034 }
2035
2036 __ bind(L_oops_not_equal);
2037 move(op->not_equal_result(), op->result_opr());
2038 __ jmp(L_end);
2039
2040 __ bind(L_oops_equal);
2041 move(op->equal_result(), op->result_opr());
2042 __ jmp(L_end);
2043
2044 // We've returned from the stub. RAX contains 0x0 IFF the two
2045 // operands are not substitutable. (Don't compare against 0x1 in case the
2046 // C compiler is naughty)
2047 __ bind(*op->stub()->continuation());
2048 __ cmpl(rax, 0);
2049 __ jcc(Assembler::equal, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
2050 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
2051 // fall-through
2052 __ bind(L_end);
2053 }
2054
2055 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2056 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
2057 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
2058 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
2059 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
2060 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
2061 Register addr = op->addr()->as_register();
2062 __ lock();
2063 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
2064
2065 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
2066 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
2067 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2068 Register newval = op->new_value()->as_register();
2069 Register cmpval = op->cmp_value()->as_register();
2070 assert(cmpval == rax, "wrong register");
2071 assert(newval != noreg, "new val must be register");
2072 assert(cmpval != newval, "cmp and new values must be in different registers");
2073 assert(cmpval != addr, "cmp and addr must be in different registers");
2074 assert(newval != addr, "new value and addr must be in different registers");
2075
2076 if ( op->code() == lir_cas_obj) {
2077 #ifdef _LP64
2078 if (UseCompressedOops) {
2079 __ encode_heap_oop(cmpval);
2080 __ mov(rscratch1, newval);
2081 __ encode_heap_oop(rscratch1);
2082 __ lock();
2083 // cmpval (rax) is implicitly used by this instruction
2084 __ cmpxchgl(rscratch1, Address(addr, 0));
2085 } else
2086 #endif
2087 {
2088 __ lock();
2089 __ cmpxchgptr(newval, Address(addr, 0));
2090 }
2091 } else {
2092 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2093 __ lock();
2094 __ cmpxchgl(newval, Address(addr, 0));
2095 }
2096 #ifdef _LP64
2097 } else if (op->code() == lir_cas_long) {
2098 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2099 Register newval = op->new_value()->as_register_lo();
2100 Register cmpval = op->cmp_value()->as_register_lo();
2101 assert(cmpval == rax, "wrong register");
2102 assert(newval != noreg, "new val must be register");
2103 assert(cmpval != newval, "cmp and new values must be in different registers");
2104 assert(cmpval != addr, "cmp and addr must be in different registers");
2105 assert(newval != addr, "new value and addr must be in different registers");
2106 __ lock();
2107 __ cmpxchgq(newval, Address(addr, 0));
2108 #endif // _LP64
2109 } else {
2110 Unimplemented();
2111 }
2112 }
2113
2114 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
2115 assert(dst->is_cpu_register(), "must be");
2116 assert(dst->type() == src->type(), "must be");
2117
2118 if (src->is_cpu_register()) {
2119 reg2reg(src, dst);
2120 } else if (src->is_stack()) {
2121 stack2reg(src, dst, dst->type());
2122 } else if (src->is_constant()) {
2123 const2reg(src, dst, lir_patch_none, nullptr);
2124 } else {
2125 ShouldNotReachHere();
2126 }
2127 }
2128
2129 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
2130 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
2131 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
2132
2133 Assembler::Condition acond, ncond;
2134 switch (condition) {
2135 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2136 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2137 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2138 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2139 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2140 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2141 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2142 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2143 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2144 ShouldNotReachHere();
2145 }
2146
2147 if (opr1->is_cpu_register()) {
2148 reg2reg(opr1, result);
2149 } else if (opr1->is_stack()) {
2150 stack2reg(opr1, result, result->type());
2151 } else if (opr1->is_constant()) {
2152 const2reg(opr1, result, lir_patch_none, nullptr);
2153 } else {
2154 ShouldNotReachHere();
2155 }
2156
2157 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2158 // optimized version that does not require a branch
2159 if (opr2->is_single_cpu()) {
2160 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2161 __ cmov(ncond, result->as_register(), opr2->as_register());
2162 } else if (opr2->is_double_cpu()) {
2163 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2164 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2165 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2166 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2167 } else if (opr2->is_single_stack()) {
2168 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2169 } else if (opr2->is_double_stack()) {
2170 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2171 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2172 } else {
2173 ShouldNotReachHere();
2174 }
2175
2176 } else {
2177 Label skip;
2178 __ jccb(acond, skip);
2179 if (opr2->is_cpu_register()) {
2180 reg2reg(opr2, result);
2181 } else if (opr2->is_stack()) {
2182 stack2reg(opr2, result, result->type());
2183 } else if (opr2->is_constant()) {
2184 const2reg(opr2, result, lir_patch_none, nullptr);
2185 } else {
2186 ShouldNotReachHere();
2187 }
2188 __ bind(skip);
2189 }
2190 }
2191
2192
2193 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2194 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2195
2196 if (left->is_single_cpu()) {
2197 assert(left == dest, "left and dest must be equal");
2198 Register lreg = left->as_register();
2199
2200 if (right->is_single_cpu()) {
2201 // cpu register - cpu register
2202 Register rreg = right->as_register();
2203 switch (code) {
2204 case lir_add: __ addl (lreg, rreg); break;
2205 case lir_sub: __ subl (lreg, rreg); break;
2206 case lir_mul: __ imull(lreg, rreg); break;
2207 default: ShouldNotReachHere();
2208 }
2209
2210 } else if (right->is_stack()) {
2211 // cpu register - stack
2212 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2213 switch (code) {
2214 case lir_add: __ addl(lreg, raddr); break;
2215 case lir_sub: __ subl(lreg, raddr); break;
2216 default: ShouldNotReachHere();
2217 }
2218
2219 } else if (right->is_constant()) {
2220 // cpu register - constant
2221 jint c = right->as_constant_ptr()->as_jint();
2222 switch (code) {
2223 case lir_add: {
2224 __ incrementl(lreg, c);
2225 break;
2226 }
2227 case lir_sub: {
2228 __ decrementl(lreg, c);
2229 break;
2230 }
2231 default: ShouldNotReachHere();
2232 }
2233
2234 } else {
2235 ShouldNotReachHere();
2236 }
2237
2238 } else if (left->is_double_cpu()) {
2239 assert(left == dest, "left and dest must be equal");
2240 Register lreg_lo = left->as_register_lo();
2241 Register lreg_hi = left->as_register_hi();
2242
2243 if (right->is_double_cpu()) {
2244 // cpu register - cpu register
2245 Register rreg_lo = right->as_register_lo();
2246 Register rreg_hi = right->as_register_hi();
2247 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2248 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2249 switch (code) {
2250 case lir_add:
2251 __ addptr(lreg_lo, rreg_lo);
2252 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2253 break;
2254 case lir_sub:
2255 __ subptr(lreg_lo, rreg_lo);
2256 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2257 break;
2258 case lir_mul:
2259 #ifdef _LP64
2260 __ imulq(lreg_lo, rreg_lo);
2261 #else
2262 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2263 __ imull(lreg_hi, rreg_lo);
2264 __ imull(rreg_hi, lreg_lo);
2265 __ addl (rreg_hi, lreg_hi);
2266 __ mull (rreg_lo);
2267 __ addl (lreg_hi, rreg_hi);
2268 #endif // _LP64
2269 break;
2270 default:
2271 ShouldNotReachHere();
2272 }
2273
2274 } else if (right->is_constant()) {
2275 // cpu register - constant
2276 #ifdef _LP64
2277 jlong c = right->as_constant_ptr()->as_jlong_bits();
2278 __ movptr(r10, (intptr_t) c);
2279 switch (code) {
2280 case lir_add:
2281 __ addptr(lreg_lo, r10);
2282 break;
2283 case lir_sub:
2284 __ subptr(lreg_lo, r10);
2285 break;
2286 default:
2287 ShouldNotReachHere();
2288 }
2289 #else
2290 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2291 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2292 switch (code) {
2293 case lir_add:
2294 __ addptr(lreg_lo, c_lo);
2295 __ adcl(lreg_hi, c_hi);
2296 break;
2297 case lir_sub:
2298 __ subptr(lreg_lo, c_lo);
2299 __ sbbl(lreg_hi, c_hi);
2300 break;
2301 default:
2302 ShouldNotReachHere();
2303 }
2304 #endif // _LP64
2305
2306 } else {
2307 ShouldNotReachHere();
2308 }
2309
2310 } else if (left->is_single_xmm()) {
2311 assert(left == dest, "left and dest must be equal");
2312 XMMRegister lreg = left->as_xmm_float_reg();
2313
2314 if (right->is_single_xmm()) {
2315 XMMRegister rreg = right->as_xmm_float_reg();
2316 switch (code) {
2317 case lir_add: __ addss(lreg, rreg); break;
2318 case lir_sub: __ subss(lreg, rreg); break;
2319 case lir_mul: __ mulss(lreg, rreg); break;
2320 case lir_div: __ divss(lreg, rreg); break;
2321 default: ShouldNotReachHere();
2322 }
2323 } else {
2324 Address raddr;
2325 if (right->is_single_stack()) {
2326 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2327 } else if (right->is_constant()) {
2328 // hack for now
2329 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2330 } else {
2331 ShouldNotReachHere();
2332 }
2333 switch (code) {
2334 case lir_add: __ addss(lreg, raddr); break;
2335 case lir_sub: __ subss(lreg, raddr); break;
2336 case lir_mul: __ mulss(lreg, raddr); break;
2337 case lir_div: __ divss(lreg, raddr); break;
2338 default: ShouldNotReachHere();
2339 }
2340 }
2341
2342 } else if (left->is_double_xmm()) {
2343 assert(left == dest, "left and dest must be equal");
2344
2345 XMMRegister lreg = left->as_xmm_double_reg();
2346 if (right->is_double_xmm()) {
2347 XMMRegister rreg = right->as_xmm_double_reg();
2348 switch (code) {
2349 case lir_add: __ addsd(lreg, rreg); break;
2350 case lir_sub: __ subsd(lreg, rreg); break;
2351 case lir_mul: __ mulsd(lreg, rreg); break;
2352 case lir_div: __ divsd(lreg, rreg); break;
2353 default: ShouldNotReachHere();
2354 }
2355 } else {
2356 Address raddr;
2357 if (right->is_double_stack()) {
2358 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2359 } else if (right->is_constant()) {
2360 // hack for now
2361 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2362 } else {
2363 ShouldNotReachHere();
2364 }
2365 switch (code) {
2366 case lir_add: __ addsd(lreg, raddr); break;
2367 case lir_sub: __ subsd(lreg, raddr); break;
2368 case lir_mul: __ mulsd(lreg, raddr); break;
2369 case lir_div: __ divsd(lreg, raddr); break;
2370 default: ShouldNotReachHere();
2371 }
2372 }
2373
2374 #ifndef _LP64
2375 } else if (left->is_single_fpu()) {
2376 assert(dest->is_single_fpu(), "fpu stack allocation required");
2377
2378 if (right->is_single_fpu()) {
2379 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2380
2381 } else {
2382 assert(left->fpu_regnr() == 0, "left must be on TOS");
2383 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2384
2385 Address raddr;
2386 if (right->is_single_stack()) {
2387 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2388 } else if (right->is_constant()) {
2389 address const_addr = float_constant(right->as_jfloat());
2390 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2391 // hack for now
2392 raddr = __ as_Address(InternalAddress(const_addr));
2393 } else {
2394 ShouldNotReachHere();
2395 }
2396
2397 switch (code) {
2398 case lir_add: __ fadd_s(raddr); break;
2399 case lir_sub: __ fsub_s(raddr); break;
2400 case lir_mul: __ fmul_s(raddr); break;
2401 case lir_div: __ fdiv_s(raddr); break;
2402 default: ShouldNotReachHere();
2403 }
2404 }
2405
2406 } else if (left->is_double_fpu()) {
2407 assert(dest->is_double_fpu(), "fpu stack allocation required");
2408
2409 if (code == lir_mul || code == lir_div) {
2410 // Double values require special handling for strictfp mul/div on x86
2411 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2412 __ fmulp(left->fpu_regnrLo() + 1);
2413 }
2414
2415 if (right->is_double_fpu()) {
2416 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2417
2418 } else {
2419 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2420 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2421
2422 Address raddr;
2423 if (right->is_double_stack()) {
2424 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2425 } else if (right->is_constant()) {
2426 // hack for now
2427 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2428 } else {
2429 ShouldNotReachHere();
2430 }
2431
2432 switch (code) {
2433 case lir_add: __ fadd_d(raddr); break;
2434 case lir_sub: __ fsub_d(raddr); break;
2435 case lir_mul: __ fmul_d(raddr); break;
2436 case lir_div: __ fdiv_d(raddr); break;
2437 default: ShouldNotReachHere();
2438 }
2439 }
2440
2441 if (code == lir_mul || code == lir_div) {
2442 // Double values require special handling for strictfp mul/div on x86
2443 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2444 __ fmulp(dest->fpu_regnrLo() + 1);
2445 }
2446 #endif // !_LP64
2447
2448 } else if (left->is_single_stack() || left->is_address()) {
2449 assert(left == dest, "left and dest must be equal");
2450
2451 Address laddr;
2452 if (left->is_single_stack()) {
2453 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2454 } else if (left->is_address()) {
2455 laddr = as_Address(left->as_address_ptr());
2456 } else {
2457 ShouldNotReachHere();
2458 }
2459
2460 if (right->is_single_cpu()) {
2461 Register rreg = right->as_register();
2462 switch (code) {
2463 case lir_add: __ addl(laddr, rreg); break;
2464 case lir_sub: __ subl(laddr, rreg); break;
2465 default: ShouldNotReachHere();
2466 }
2467 } else if (right->is_constant()) {
2468 jint c = right->as_constant_ptr()->as_jint();
2469 switch (code) {
2470 case lir_add: {
2471 __ incrementl(laddr, c);
2472 break;
2473 }
2474 case lir_sub: {
2475 __ decrementl(laddr, c);
2476 break;
2477 }
2478 default: ShouldNotReachHere();
2479 }
2480 } else {
2481 ShouldNotReachHere();
2482 }
2483
2484 } else {
2485 ShouldNotReachHere();
2486 }
2487 }
2488
2489 #ifndef _LP64
2490 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2491 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2492 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2493 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2494
2495 bool left_is_tos = (left_index == 0);
2496 bool dest_is_tos = (dest_index == 0);
2497 int non_tos_index = (left_is_tos ? right_index : left_index);
2498
2499 switch (code) {
2500 case lir_add:
2501 if (pop_fpu_stack) __ faddp(non_tos_index);
2502 else if (dest_is_tos) __ fadd (non_tos_index);
2503 else __ fadda(non_tos_index);
2504 break;
2505
2506 case lir_sub:
2507 if (left_is_tos) {
2508 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2509 else if (dest_is_tos) __ fsub (non_tos_index);
2510 else __ fsubra(non_tos_index);
2511 } else {
2512 if (pop_fpu_stack) __ fsubp (non_tos_index);
2513 else if (dest_is_tos) __ fsubr (non_tos_index);
2514 else __ fsuba (non_tos_index);
2515 }
2516 break;
2517
2518 case lir_mul:
2519 if (pop_fpu_stack) __ fmulp(non_tos_index);
2520 else if (dest_is_tos) __ fmul (non_tos_index);
2521 else __ fmula(non_tos_index);
2522 break;
2523
2524 case lir_div:
2525 if (left_is_tos) {
2526 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2527 else if (dest_is_tos) __ fdiv (non_tos_index);
2528 else __ fdivra(non_tos_index);
2529 } else {
2530 if (pop_fpu_stack) __ fdivp (non_tos_index);
2531 else if (dest_is_tos) __ fdivr (non_tos_index);
2532 else __ fdiva (non_tos_index);
2533 }
2534 break;
2535
2536 case lir_rem:
2537 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2538 __ fremr(noreg);
2539 break;
2540
2541 default:
2542 ShouldNotReachHere();
2543 }
2544 }
2545 #endif // _LP64
2546
2547
2548 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2549 if (value->is_double_xmm()) {
2550 switch(code) {
2551 case lir_abs :
2552 {
2553 #ifdef _LP64
2554 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2555 assert(tmp->is_valid(), "need temporary");
2556 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2557 } else
2558 #endif
2559 {
2560 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2561 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2562 }
2563 assert(!tmp->is_valid(), "do not need temporary");
2564 __ andpd(dest->as_xmm_double_reg(),
2565 ExternalAddress((address)double_signmask_pool),
2566 rscratch1);
2567 }
2568 }
2569 break;
2570
2571 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2572 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2573 default : ShouldNotReachHere();
2574 }
2575
2576 #ifndef _LP64
2577 } else if (value->is_double_fpu()) {
2578 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2579 switch(code) {
2580 case lir_abs : __ fabs() ; break;
2581 case lir_sqrt : __ fsqrt(); break;
2582 default : ShouldNotReachHere();
2583 }
2584 #endif // !_LP64
2585 } else if (code == lir_f2hf) {
2586 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2587 } else if (code == lir_hf2f) {
2588 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2589 } else {
2590 Unimplemented();
2591 }
2592 }
2593
2594 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2595 // assert(left->destroys_register(), "check");
2596 if (left->is_single_cpu()) {
2597 Register reg = left->as_register();
2598 if (right->is_constant()) {
2599 int val = right->as_constant_ptr()->as_jint();
2600 switch (code) {
2601 case lir_logic_and: __ andl (reg, val); break;
2602 case lir_logic_or: __ orl (reg, val); break;
2603 case lir_logic_xor: __ xorl (reg, val); break;
2604 default: ShouldNotReachHere();
2605 }
2606 } else if (right->is_stack()) {
2607 // added support for stack operands
2608 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2609 switch (code) {
2610 case lir_logic_and: __ andl (reg, raddr); break;
2611 case lir_logic_or: __ orl (reg, raddr); break;
2612 case lir_logic_xor: __ xorl (reg, raddr); break;
2613 default: ShouldNotReachHere();
2614 }
2615 } else {
2616 Register rright = right->as_register();
2617 switch (code) {
2618 case lir_logic_and: __ andptr (reg, rright); break;
2619 case lir_logic_or : __ orptr (reg, rright); break;
2620 case lir_logic_xor: __ xorptr (reg, rright); break;
2621 default: ShouldNotReachHere();
2622 }
2623 }
2624 move_regs(reg, dst->as_register());
2625 } else {
2626 Register l_lo = left->as_register_lo();
2627 Register l_hi = left->as_register_hi();
2628 if (right->is_constant()) {
2629 #ifdef _LP64
2630 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2631 switch (code) {
2632 case lir_logic_and:
2633 __ andq(l_lo, rscratch1);
2634 break;
2635 case lir_logic_or:
2636 __ orq(l_lo, rscratch1);
2637 break;
2638 case lir_logic_xor:
2639 __ xorq(l_lo, rscratch1);
2640 break;
2641 default: ShouldNotReachHere();
2642 }
2643 #else
2644 int r_lo = right->as_constant_ptr()->as_jint_lo();
2645 int r_hi = right->as_constant_ptr()->as_jint_hi();
2646 switch (code) {
2647 case lir_logic_and:
2648 __ andl(l_lo, r_lo);
2649 __ andl(l_hi, r_hi);
2650 break;
2651 case lir_logic_or:
2652 __ orl(l_lo, r_lo);
2653 __ orl(l_hi, r_hi);
2654 break;
2655 case lir_logic_xor:
2656 __ xorl(l_lo, r_lo);
2657 __ xorl(l_hi, r_hi);
2658 break;
2659 default: ShouldNotReachHere();
2660 }
2661 #endif // _LP64
2662 } else {
2663 #ifdef _LP64
2664 Register r_lo;
2665 if (is_reference_type(right->type())) {
2666 r_lo = right->as_register();
2667 } else {
2668 r_lo = right->as_register_lo();
2669 }
2670 #else
2671 Register r_lo = right->as_register_lo();
2672 Register r_hi = right->as_register_hi();
2673 assert(l_lo != r_hi, "overwriting registers");
2674 #endif
2675 switch (code) {
2676 case lir_logic_and:
2677 __ andptr(l_lo, r_lo);
2678 NOT_LP64(__ andptr(l_hi, r_hi);)
2679 break;
2680 case lir_logic_or:
2681 __ orptr(l_lo, r_lo);
2682 NOT_LP64(__ orptr(l_hi, r_hi);)
2683 break;
2684 case lir_logic_xor:
2685 __ xorptr(l_lo, r_lo);
2686 NOT_LP64(__ xorptr(l_hi, r_hi);)
2687 break;
2688 default: ShouldNotReachHere();
2689 }
2690 }
2691
2692 Register dst_lo = dst->as_register_lo();
2693 Register dst_hi = dst->as_register_hi();
2694
2695 #ifdef _LP64
2696 move_regs(l_lo, dst_lo);
2697 #else
2698 if (dst_lo == l_hi) {
2699 assert(dst_hi != l_lo, "overwriting registers");
2700 move_regs(l_hi, dst_hi);
2701 move_regs(l_lo, dst_lo);
2702 } else {
2703 assert(dst_lo != l_hi, "overwriting registers");
2704 move_regs(l_lo, dst_lo);
2705 move_regs(l_hi, dst_hi);
2706 }
2707 #endif // _LP64
2708 }
2709 }
2710
2711
2712 // we assume that rax, and rdx can be overwritten
2713 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2714
2715 assert(left->is_single_cpu(), "left must be register");
2716 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2717 assert(result->is_single_cpu(), "result must be register");
2718
2719 // assert(left->destroys_register(), "check");
2720 // assert(right->destroys_register(), "check");
2721
2722 Register lreg = left->as_register();
2723 Register dreg = result->as_register();
2724
2725 if (right->is_constant()) {
2726 jint divisor = right->as_constant_ptr()->as_jint();
2727 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2728 if (code == lir_idiv) {
2729 assert(lreg == rax, "must be rax,");
2730 assert(temp->as_register() == rdx, "tmp register must be rdx");
2731 __ cdql(); // sign extend into rdx:rax
2732 if (divisor == 2) {
2733 __ subl(lreg, rdx);
2734 } else {
2735 __ andl(rdx, divisor - 1);
2736 __ addl(lreg, rdx);
2737 }
2738 __ sarl(lreg, log2i_exact(divisor));
2739 move_regs(lreg, dreg);
2740 } else if (code == lir_irem) {
2741 Label done;
2742 __ mov(dreg, lreg);
2743 __ andl(dreg, 0x80000000 | (divisor - 1));
2744 __ jcc(Assembler::positive, done);
2745 __ decrement(dreg);
2746 __ orl(dreg, ~(divisor - 1));
2747 __ increment(dreg);
2748 __ bind(done);
2749 } else {
2750 ShouldNotReachHere();
2751 }
2752 } else {
2753 Register rreg = right->as_register();
2754 assert(lreg == rax, "left register must be rax,");
2755 assert(rreg != rdx, "right register must not be rdx");
2756 assert(temp->as_register() == rdx, "tmp register must be rdx");
2757
2758 move_regs(lreg, rax);
2759
2760 int idivl_offset = __ corrected_idivl(rreg);
2761 if (ImplicitDiv0Checks) {
2762 add_debug_info_for_div0(idivl_offset, info);
2763 }
2764 if (code == lir_irem) {
2765 move_regs(rdx, dreg); // result is in rdx
2766 } else {
2767 move_regs(rax, dreg);
2768 }
2769 }
2770 }
2771
2772
2773 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2774 if (opr1->is_single_cpu()) {
2775 Register reg1 = opr1->as_register();
2776 if (opr2->is_single_cpu()) {
2777 // cpu register - cpu register
2778 if (is_reference_type(opr1->type())) {
2779 __ cmpoop(reg1, opr2->as_register());
2780 } else {
2781 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2782 __ cmpl(reg1, opr2->as_register());
2783 }
2784 } else if (opr2->is_stack()) {
2785 // cpu register - stack
2786 if (is_reference_type(opr1->type())) {
2787 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2788 } else {
2789 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2790 }
2791 } else if (opr2->is_constant()) {
2792 // cpu register - constant
2793 LIR_Const* c = opr2->as_constant_ptr();
2794 if (c->type() == T_INT) {
2795 jint i = c->as_jint();
2796 if (i == 0) {
2797 __ testl(reg1, reg1);
2798 } else {
2799 __ cmpl(reg1, i);
2800 }
2801 } else if (c->type() == T_METADATA) {
2802 // All we need for now is a comparison with null for equality.
2803 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2804 Metadata* m = c->as_metadata();
2805 if (m == nullptr) {
2806 __ testptr(reg1, reg1);
2807 } else {
2808 ShouldNotReachHere();
2809 }
2810 } else if (is_reference_type(c->type())) {
2811 // In 64bit oops are single register
2812 jobject o = c->as_jobject();
2813 if (o == nullptr) {
2814 __ testptr(reg1, reg1);
2815 } else {
2816 __ cmpoop(reg1, o, rscratch1);
2817 }
2818 } else {
2819 fatal("unexpected type: %s", basictype_to_str(c->type()));
2820 }
2821 // cpu register - address
2822 } else if (opr2->is_address()) {
2823 if (op->info() != nullptr) {
2824 add_debug_info_for_null_check_here(op->info());
2825 }
2826 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2827 } else {
2828 ShouldNotReachHere();
2829 }
2830
2831 } else if(opr1->is_double_cpu()) {
2832 Register xlo = opr1->as_register_lo();
2833 Register xhi = opr1->as_register_hi();
2834 if (opr2->is_double_cpu()) {
2835 #ifdef _LP64
2836 __ cmpptr(xlo, opr2->as_register_lo());
2837 #else
2838 // cpu register - cpu register
2839 Register ylo = opr2->as_register_lo();
2840 Register yhi = opr2->as_register_hi();
2841 __ subl(xlo, ylo);
2842 __ sbbl(xhi, yhi);
2843 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2844 __ orl(xhi, xlo);
2845 }
2846 #endif // _LP64
2847 } else if (opr2->is_constant()) {
2848 // cpu register - constant 0
2849 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2850 #ifdef _LP64
2851 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2852 #else
2853 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2854 __ orl(xhi, xlo);
2855 #endif // _LP64
2856 } else {
2857 ShouldNotReachHere();
2858 }
2859
2860 } else if (opr1->is_single_xmm()) {
2861 XMMRegister reg1 = opr1->as_xmm_float_reg();
2862 if (opr2->is_single_xmm()) {
2863 // xmm register - xmm register
2864 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2865 } else if (opr2->is_stack()) {
2866 // xmm register - stack
2867 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2868 } else if (opr2->is_constant()) {
2869 // xmm register - constant
2870 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2871 } else if (opr2->is_address()) {
2872 // xmm register - address
2873 if (op->info() != nullptr) {
2874 add_debug_info_for_null_check_here(op->info());
2875 }
2876 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2877 } else {
2878 ShouldNotReachHere();
2879 }
2880
2881 } else if (opr1->is_double_xmm()) {
2882 XMMRegister reg1 = opr1->as_xmm_double_reg();
2883 if (opr2->is_double_xmm()) {
2884 // xmm register - xmm register
2885 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2886 } else if (opr2->is_stack()) {
2887 // xmm register - stack
2888 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2889 } else if (opr2->is_constant()) {
2890 // xmm register - constant
2891 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2892 } else if (opr2->is_address()) {
2893 // xmm register - address
2894 if (op->info() != nullptr) {
2895 add_debug_info_for_null_check_here(op->info());
2896 }
2897 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2898 } else {
2899 ShouldNotReachHere();
2900 }
2901
2902 #ifndef _LP64
2903 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2904 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2905 assert(opr2->is_fpu_register(), "both must be registers");
2906 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2907 #endif // LP64
2908
2909 } else if (opr1->is_address() && opr2->is_constant()) {
2910 LIR_Const* c = opr2->as_constant_ptr();
2911 #ifdef _LP64
2912 if (is_reference_type(c->type())) {
2913 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2914 __ movoop(rscratch1, c->as_jobject());
2915 }
2916 #endif // LP64
2917 if (op->info() != nullptr) {
2918 add_debug_info_for_null_check_here(op->info());
2919 }
2920 // special case: address - constant
2921 LIR_Address* addr = opr1->as_address_ptr();
2922 if (c->type() == T_INT) {
2923 __ cmpl(as_Address(addr), c->as_jint());
2924 } else if (is_reference_type(c->type())) {
2925 #ifdef _LP64
2926 // %%% Make this explode if addr isn't reachable until we figure out a
2927 // better strategy by giving noreg as the temp for as_Address
2928 __ cmpoop(rscratch1, as_Address(addr, noreg));
2929 #else
2930 __ cmpoop(as_Address(addr), c->as_jobject());
2931 #endif // _LP64
2932 } else {
2933 ShouldNotReachHere();
2934 }
2935
2936 } else {
2937 ShouldNotReachHere();
2938 }
2939 }
2940
2941 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2942 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2943 if (left->is_single_xmm()) {
2944 assert(right->is_single_xmm(), "must match");
2945 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2946 } else if (left->is_double_xmm()) {
2947 assert(right->is_double_xmm(), "must match");
2948 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2949
2950 } else {
2951 #ifdef _LP64
2952 ShouldNotReachHere();
2953 #else
2954 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2955 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2956
2957 assert(left->fpu() == 0, "left must be on TOS");
2958 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2959 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2960 #endif // LP64
2961 }
2962 } else {
2963 assert(code == lir_cmp_l2i, "check");
2964 #ifdef _LP64
2965 Label done;
2966 Register dest = dst->as_register();
2967 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2968 __ movl(dest, -1);
2969 __ jccb(Assembler::less, done);
2970 __ setb(Assembler::notZero, dest);
2971 __ movzbl(dest, dest);
2972 __ bind(done);
2973 #else
2974 __ lcmp2int(left->as_register_hi(),
2975 left->as_register_lo(),
2976 right->as_register_hi(),
2977 right->as_register_lo());
2978 move_regs(left->as_register_hi(), dst->as_register());
2979 #endif // _LP64
2980 }
2981 }
2982
2983
2984 void LIR_Assembler::align_call(LIR_Code code) {
2985 // make sure that the displacement word of the call ends up word aligned
2986 int offset = __ offset();
2987 switch (code) {
2988 case lir_static_call:
2989 case lir_optvirtual_call:
2990 case lir_dynamic_call:
2991 offset += NativeCall::displacement_offset;
2992 break;
2993 case lir_icvirtual_call:
2994 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2995 break;
2996 default: ShouldNotReachHere();
2997 }
2998 __ align(BytesPerWord, offset);
2999 }
3000
3001
3002 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
3003 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
3004 "must be aligned");
3005 __ call(AddressLiteral(op->addr(), rtype));
3006 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3007 __ post_call_nop();
3008 }
3009
3010
3011 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
3012 __ ic_call(op->addr());
3013 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3014 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
3015 "must be aligned");
3016 __ post_call_nop();
3017 }
3018
3019
3020 void LIR_Assembler::emit_static_call_stub() {
3021 address call_pc = __ pc();
3022 address stub = __ start_a_stub(call_stub_size());
3023 if (stub == nullptr) {
3024 bailout("static call stub overflow");
3025 return;
3026 }
3027
3028 int start = __ offset();
3029
3030 // make sure that the displacement word of the call ends up word aligned
3031 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
3032 __ relocate(static_stub_Relocation::spec(call_pc));
3033 __ mov_metadata(rbx, (Metadata*)nullptr);
3034 // must be set to -1 at code generation time
3035 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
3036 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
3037 __ jump(RuntimeAddress(__ pc()));
3038
3039 assert(__ offset() - start <= call_stub_size(), "stub too big");
3040 __ end_a_stub();
3041 }
3042
3043
3044 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
3045 assert(exceptionOop->as_register() == rax, "must match");
3046 assert(exceptionPC->as_register() == rdx, "must match");
3047
3048 // exception object is not added to oop map by LinearScan
3049 // (LinearScan assumes that no oops are in fixed registers)
3050 info->add_register_oop(exceptionOop);
3051 Runtime1::StubID unwind_id;
3052
3053 // get current pc information
3054 // pc is only needed if the method has an exception handler, the unwind code does not need it.
3055 int pc_for_athrow_offset = __ offset();
3056 InternalAddress pc_for_athrow(__ pc());
3057 __ lea(exceptionPC->as_register(), pc_for_athrow);
3058 add_call_info(pc_for_athrow_offset, info); // for exception handler
3059
3060 __ verify_not_null_oop(rax);
3061 // search an exception handler (rax: exception oop, rdx: throwing pc)
3062 if (compilation()->has_fpu_code()) {
3063 unwind_id = Runtime1::handle_exception_id;
3064 } else {
3065 unwind_id = Runtime1::handle_exception_nofpu_id;
3066 }
3067 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
3068
3069 // enough room for two byte trap
3070 __ nop();
3071 }
3072
3073
3074 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
3075 assert(exceptionOop->as_register() == rax, "must match");
3076
3077 __ jmp(_unwind_handler_entry);
3078 }
3079
3080
3081 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3082
3083 // optimized version for linear scan:
3084 // * count must be already in ECX (guaranteed by LinearScan)
3085 // * left and dest must be equal
3086 // * tmp must be unused
3087 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3088 assert(left == dest, "left and dest must be equal");
3089 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3090
3091 if (left->is_single_cpu()) {
3092 Register value = left->as_register();
3093 assert(value != SHIFT_count, "left cannot be ECX");
3094
3095 switch (code) {
3096 case lir_shl: __ shll(value); break;
3097 case lir_shr: __ sarl(value); break;
3098 case lir_ushr: __ shrl(value); break;
3099 default: ShouldNotReachHere();
3100 }
3101 } else if (left->is_double_cpu()) {
3102 Register lo = left->as_register_lo();
3103 Register hi = left->as_register_hi();
3104 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3105 #ifdef _LP64
3106 switch (code) {
3107 case lir_shl: __ shlptr(lo); break;
3108 case lir_shr: __ sarptr(lo); break;
3109 case lir_ushr: __ shrptr(lo); break;
3110 default: ShouldNotReachHere();
3111 }
3112 #else
3113
3114 switch (code) {
3115 case lir_shl: __ lshl(hi, lo); break;
3116 case lir_shr: __ lshr(hi, lo, true); break;
3117 case lir_ushr: __ lshr(hi, lo, false); break;
3118 default: ShouldNotReachHere();
3119 }
3120 #endif // LP64
3121 } else {
3122 ShouldNotReachHere();
3123 }
3124 }
3125
3126
3127 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3128 if (dest->is_single_cpu()) {
3129 // first move left into dest so that left is not destroyed by the shift
3130 Register value = dest->as_register();
3131 count = count & 0x1F; // Java spec
3132
3133 move_regs(left->as_register(), value);
3134 switch (code) {
3135 case lir_shl: __ shll(value, count); break;
3136 case lir_shr: __ sarl(value, count); break;
3137 case lir_ushr: __ shrl(value, count); break;
3138 default: ShouldNotReachHere();
3139 }
3140 } else if (dest->is_double_cpu()) {
3141 #ifndef _LP64
3142 Unimplemented();
3143 #else
3144 // first move left into dest so that left is not destroyed by the shift
3145 Register value = dest->as_register_lo();
3146 count = count & 0x1F; // Java spec
3147
3148 move_regs(left->as_register_lo(), value);
3149 switch (code) {
3150 case lir_shl: __ shlptr(value, count); break;
3151 case lir_shr: __ sarptr(value, count); break;
3152 case lir_ushr: __ shrptr(value, count); break;
3153 default: ShouldNotReachHere();
3154 }
3155 #endif // _LP64
3156 } else {
3157 ShouldNotReachHere();
3158 }
3159 }
3160
3161
3162 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3163 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3164 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3165 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3166 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3167 }
3168
3169
3170 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3171 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3172 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3173 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3174 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3175 }
3176
3177
3178 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3179 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3180 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3181 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3182 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3183 }
3184
3185
3186 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3187 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3188 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3189 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3190 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3191 }
3192
3193
3194 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
3195 if (null_check) {
3196 __ testptr(obj, obj);
3197 __ jcc(Assembler::zero, *slow_path->entry());
3198 }
3199 if (is_dest) {
3200 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
3201 } else {
3202 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
3203 }
3204 }
3205
3206
3207 // This code replaces a call to arraycopy; no exception may
3208 // be thrown in this code, they must be thrown in the System.arraycopy
3209 // activation frame; we could save some checks if this would not be the case
3210 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3211 ciArrayKlass* default_type = op->expected_type();
3212 Register src = op->src()->as_register();
3213 Register dst = op->dst()->as_register();
3214 Register src_pos = op->src_pos()->as_register();
3215 Register dst_pos = op->dst_pos()->as_register();
3216 Register length = op->length()->as_register();
3217 Register tmp = op->tmp()->as_register();
3218 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3219
3220 CodeStub* stub = op->stub();
3221 int flags = op->flags();
3222 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3223 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3224
3225 if (flags & LIR_OpArrayCopy::always_slow_path) {
3226 __ jmp(*stub->entry());
3227 __ bind(*stub->continuation());
3228 return;
3229 }
3230
3231 // if we don't know anything, just go through the generic arraycopy
3232 if (default_type == nullptr) {
3233 // save outgoing arguments on stack in case call to System.arraycopy is needed
3234 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3235 // for interpreter calling conventions. Now we have to do it in new style conventions.
3236 // For the moment until C1 gets the new register allocator I just force all the
3237 // args to the right place (except the register args) and then on the back side
3238 // reload the register args properly if we go slow path. Yuck
3239
3240 // These are proper for the calling convention
3241 store_parameter(length, 2);
3242 store_parameter(dst_pos, 1);
3243 store_parameter(dst, 0);
3244
3245 // these are just temporary placements until we need to reload
3246 store_parameter(src_pos, 3);
3247 store_parameter(src, 4);
3248 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3249
3250 address copyfunc_addr = StubRoutines::generic_arraycopy();
3251 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3252
3253 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3254 #ifdef _LP64
3255 // The arguments are in java calling convention so we can trivially shift them to C
3256 // convention
3257 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3258 __ mov(c_rarg0, j_rarg0);
3259 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3260 __ mov(c_rarg1, j_rarg1);
3261 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3262 __ mov(c_rarg2, j_rarg2);
3263 assert_different_registers(c_rarg3, j_rarg4);
3264 __ mov(c_rarg3, j_rarg3);
3265 #ifdef _WIN64
3266 // Allocate abi space for args but be sure to keep stack aligned
3267 __ subptr(rsp, 6*wordSize);
3268 store_parameter(j_rarg4, 4);
3269 #ifndef PRODUCT
3270 if (PrintC1Statistics) {
3271 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3272 }
3273 #endif
3274 __ call(RuntimeAddress(copyfunc_addr));
3275 __ addptr(rsp, 6*wordSize);
3276 #else
3277 __ mov(c_rarg4, j_rarg4);
3278 #ifndef PRODUCT
3279 if (PrintC1Statistics) {
3280 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3281 }
3282 #endif
3283 __ call(RuntimeAddress(copyfunc_addr));
3284 #endif // _WIN64
3285 #else
3286 __ push(length);
3287 __ push(dst_pos);
3288 __ push(dst);
3289 __ push(src_pos);
3290 __ push(src);
3291
3292 #ifndef PRODUCT
3293 if (PrintC1Statistics) {
3294 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3295 }
3296 #endif
3297 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3298
3299 #endif // _LP64
3300
3301 __ testl(rax, rax);
3302 __ jcc(Assembler::equal, *stub->continuation());
3303
3304 __ mov(tmp, rax);
3305 __ xorl(tmp, -1);
3306
3307 // Reload values from the stack so they are where the stub
3308 // expects them.
3309 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3310 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3311 __ movptr (length, Address(rsp, 2*BytesPerWord));
3312 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3313 __ movptr (src, Address(rsp, 4*BytesPerWord));
3314
3315 __ subl(length, tmp);
3316 __ addl(src_pos, tmp);
3317 __ addl(dst_pos, tmp);
3318 __ jmp(*stub->entry());
3319
3320 __ bind(*stub->continuation());
3321 return;
3322 }
3323
3324 // Handle inline type arrays
3325 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
3326 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
3327 }
3328 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
3329 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
3330 }
3331
3332 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3333
3334 int elem_size = type2aelembytes(basic_type);
3335 Address::ScaleFactor scale;
3336
3337 switch (elem_size) {
3338 case 1 :
3339 scale = Address::times_1;
3340 break;
3341 case 2 :
3342 scale = Address::times_2;
3343 break;
3344 case 4 :
3345 scale = Address::times_4;
3346 break;
3347 case 8 :
3348 scale = Address::times_8;
3349 break;
3350 default:
3351 scale = Address::no_scale;
3352 ShouldNotReachHere();
3353 }
3354
3355 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3356 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3357 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3358 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3359
3360 // length and pos's are all sign extended at this point on 64bit
3361
3362 // test for null
3363 if (flags & LIR_OpArrayCopy::src_null_check) {
3364 __ testptr(src, src);
3365 __ jcc(Assembler::zero, *stub->entry());
3366 }
3367 if (flags & LIR_OpArrayCopy::dst_null_check) {
3368 __ testptr(dst, dst);
3369 __ jcc(Assembler::zero, *stub->entry());
3370 }
3371
3372 // If the compiler was not able to prove that exact type of the source or the destination
3373 // of the arraycopy is an array type, check at runtime if the source or the destination is
3374 // an instance type.
3375 if (flags & LIR_OpArrayCopy::type_check) {
3376 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3377 __ load_klass(tmp, dst, tmp_load_klass);
3378 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3379 __ jcc(Assembler::greaterEqual, *stub->entry());
3380 }
3381
3382 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3383 __ load_klass(tmp, src, tmp_load_klass);
3384 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3385 __ jcc(Assembler::greaterEqual, *stub->entry());
3386 }
3387 }
3388
3389 // check if negative
3390 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3391 __ testl(src_pos, src_pos);
3392 __ jcc(Assembler::less, *stub->entry());
3393 }
3394 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3395 __ testl(dst_pos, dst_pos);
3396 __ jcc(Assembler::less, *stub->entry());
3397 }
3398
3399 if (flags & LIR_OpArrayCopy::src_range_check) {
3400 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3401 __ cmpl(tmp, src_length_addr);
3402 __ jcc(Assembler::above, *stub->entry());
3403 }
3404 if (flags & LIR_OpArrayCopy::dst_range_check) {
3405 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3406 __ cmpl(tmp, dst_length_addr);
3407 __ jcc(Assembler::above, *stub->entry());
3408 }
3409
3410 if (flags & LIR_OpArrayCopy::length_positive_check) {
3411 __ testl(length, length);
3412 __ jcc(Assembler::less, *stub->entry());
3413 }
3414
3415 #ifdef _LP64
3416 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3417 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3418 #endif
3419
3420 if (flags & LIR_OpArrayCopy::type_check) {
3421 // We don't know the array types are compatible
3422 if (basic_type != T_OBJECT) {
3423 // Simple test for basic type arrays
3424 if (UseCompressedClassPointers) {
3425 __ movl(tmp, src_klass_addr);
3426 __ cmpl(tmp, dst_klass_addr);
3427 } else {
3428 __ movptr(tmp, src_klass_addr);
3429 __ cmpptr(tmp, dst_klass_addr);
3430 }
3431 __ jcc(Assembler::notEqual, *stub->entry());
3432 } else {
3433 // For object arrays, if src is a sub class of dst then we can
3434 // safely do the copy.
3435 Label cont, slow;
3436
3437 __ push(src);
3438 __ push(dst);
3439
3440 __ load_klass(src, src, tmp_load_klass);
3441 __ load_klass(dst, dst, tmp_load_klass);
3442
3443 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3444
3445 __ push(src);
3446 __ push(dst);
3447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3448 __ pop(dst);
3449 __ pop(src);
3450
3451 __ testl(src, src);
3452 __ jcc(Assembler::notEqual, cont);
3453
3454 __ bind(slow);
3455 __ pop(dst);
3456 __ pop(src);
3457
3458 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3459 if (copyfunc_addr != nullptr) { // use stub if available
3460 // src is not a sub class of dst so we have to do a
3461 // per-element check.
3462
3463 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3464 if ((flags & mask) != mask) {
3465 // Check that at least both of them object arrays.
3466 assert(flags & mask, "one of the two should be known to be an object array");
3467
3468 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3469 __ load_klass(tmp, src, tmp_load_klass);
3470 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3471 __ load_klass(tmp, dst, tmp_load_klass);
3472 }
3473 int lh_offset = in_bytes(Klass::layout_helper_offset());
3474 Address klass_lh_addr(tmp, lh_offset);
3475 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3476 __ cmpl(klass_lh_addr, objArray_lh);
3477 __ jcc(Assembler::notEqual, *stub->entry());
3478 }
3479
3480 // Spill because stubs can use any register they like and it's
3481 // easier to restore just those that we care about.
3482 store_parameter(dst, 0);
3483 store_parameter(dst_pos, 1);
3484 store_parameter(length, 2);
3485 store_parameter(src_pos, 3);
3486 store_parameter(src, 4);
3487
3488 #ifndef _LP64
3489 __ movptr(tmp, dst_klass_addr);
3490 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3491 __ push(tmp);
3492 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3493 __ push(tmp);
3494 __ push(length);
3495 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3496 __ push(tmp);
3497 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3498 __ push(tmp);
3499
3500 __ call_VM_leaf(copyfunc_addr, 5);
3501 #else
3502 __ movl2ptr(length, length); //higher 32bits must be null
3503
3504 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3505 assert_different_registers(c_rarg0, dst, dst_pos, length);
3506 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3507 assert_different_registers(c_rarg1, dst, length);
3508
3509 __ mov(c_rarg2, length);
3510 assert_different_registers(c_rarg2, dst);
3511
3512 #ifdef _WIN64
3513 // Allocate abi space for args but be sure to keep stack aligned
3514 __ subptr(rsp, 6*wordSize);
3515 __ load_klass(c_rarg3, dst, tmp_load_klass);
3516 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3517 store_parameter(c_rarg3, 4);
3518 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3519 __ call(RuntimeAddress(copyfunc_addr));
3520 __ addptr(rsp, 6*wordSize);
3521 #else
3522 __ load_klass(c_rarg4, dst, tmp_load_klass);
3523 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3524 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3525 __ call(RuntimeAddress(copyfunc_addr));
3526 #endif
3527
3528 #endif
3529
3530 #ifndef PRODUCT
3531 if (PrintC1Statistics) {
3532 Label failed;
3533 __ testl(rax, rax);
3534 __ jcc(Assembler::notZero, failed);
3535 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3536 __ bind(failed);
3537 }
3538 #endif
3539
3540 __ testl(rax, rax);
3541 __ jcc(Assembler::zero, *stub->continuation());
3542
3543 #ifndef PRODUCT
3544 if (PrintC1Statistics) {
3545 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3546 }
3547 #endif
3548
3549 __ mov(tmp, rax);
3550
3551 __ xorl(tmp, -1);
3552
3553 // Restore previously spilled arguments
3554 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3555 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3556 __ movptr (length, Address(rsp, 2*BytesPerWord));
3557 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3558 __ movptr (src, Address(rsp, 4*BytesPerWord));
3559
3560
3561 __ subl(length, tmp);
3562 __ addl(src_pos, tmp);
3563 __ addl(dst_pos, tmp);
3564 }
3565
3566 __ jmp(*stub->entry());
3567
3568 __ bind(cont);
3569 __ pop(dst);
3570 __ pop(src);
3571 }
3572 }
3573
3574 #ifdef ASSERT
3575 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3576 // Sanity check the known type with the incoming class. For the
3577 // primitive case the types must match exactly with src.klass and
3578 // dst.klass each exactly matching the default type. For the
3579 // object array case, if no type check is needed then either the
3580 // dst type is exactly the expected type and the src type is a
3581 // subtype which we can't check or src is the same array as dst
3582 // but not necessarily exactly of type default_type.
3583 Label known_ok, halt;
3584 __ mov_metadata(tmp, default_type->constant_encoding());
3585 #ifdef _LP64
3586 if (UseCompressedClassPointers) {
3587 __ encode_klass_not_null(tmp, rscratch1);
3588 }
3589 #endif
3590
3591 if (basic_type != T_OBJECT) {
3592
3593 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3594 else __ cmpptr(tmp, dst_klass_addr);
3595 __ jcc(Assembler::notEqual, halt);
3596 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3597 else __ cmpptr(tmp, src_klass_addr);
3598 __ jcc(Assembler::equal, known_ok);
3599 } else {
3600 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3601 else __ cmpptr(tmp, dst_klass_addr);
3602 __ jcc(Assembler::equal, known_ok);
3603 __ cmpptr(src, dst);
3604 __ jcc(Assembler::equal, known_ok);
3605 }
3606 __ bind(halt);
3607 __ stop("incorrect type information in arraycopy");
3608 __ bind(known_ok);
3609 }
3610 #endif
3611
3612 #ifndef PRODUCT
3613 if (PrintC1Statistics) {
3614 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3615 }
3616 #endif
3617
3618 #ifdef _LP64
3619 assert_different_registers(c_rarg0, dst, dst_pos, length);
3620 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3621 assert_different_registers(c_rarg1, length);
3622 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3623 __ mov(c_rarg2, length);
3624
3625 #else
3626 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3627 store_parameter(tmp, 0);
3628 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3629 store_parameter(tmp, 1);
3630 store_parameter(length, 2);
3631 #endif // _LP64
3632
3633 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3634 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3635 const char *name;
3636 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3637 __ call_VM_leaf(entry, 0);
3638
3639 __ bind(*stub->continuation());
3640 }
3641
3642 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3643 assert(op->crc()->is_single_cpu(), "crc must be register");
3644 assert(op->val()->is_single_cpu(), "byte value must be register");
3645 assert(op->result_opr()->is_single_cpu(), "result must be register");
3646 Register crc = op->crc()->as_register();
3647 Register val = op->val()->as_register();
3648 Register res = op->result_opr()->as_register();
3649
3650 assert_different_registers(val, crc, res);
3651
3652 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3653 __ notl(crc); // ~crc
3654 __ update_byte_crc32(crc, val, res);
3655 __ notl(crc); // ~crc
3656 __ mov(res, crc);
3657 }
3658
3659 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3660 Register obj = op->obj_opr()->as_register(); // may not be an oop
3661 Register hdr = op->hdr_opr()->as_register();
3662 Register lock = op->lock_opr()->as_register();
3663 if (LockingMode == LM_MONITOR) {
3664 if (op->info() != nullptr) {
3665 add_debug_info_for_null_check_here(op->info());
3666 __ null_check(obj);
3667 }
3668 __ jmp(*op->stub()->entry());
3669 } else if (op->code() == lir_lock) {
3670 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3671 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3672 // add debug info for NullPointerException only if one is possible
3673 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3674 if (op->info() != nullptr) {
3675 add_debug_info_for_null_check(null_check_offset, op->info());
3676 }
3677 // done
3678 } else if (op->code() == lir_unlock) {
3679 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3680 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3681 } else {
3682 Unimplemented();
3683 }
3684 __ bind(*op->stub()->continuation());
3685 }
3686
3687 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3688 Register obj = op->obj()->as_pointer_register();
3689 Register result = op->result_opr()->as_pointer_register();
3690
3691 CodeEmitInfo* info = op->info();
3692 if (info != nullptr) {
3693 add_debug_info_for_null_check_here(info);
3694 }
3695
3696 #ifdef _LP64
3697 if (UseCompressedClassPointers) {
3698 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3699 __ decode_klass_not_null(result, rscratch1);
3700 } else
3701 #endif
3702 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3703 }
3704
3705 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3706 ciMethod* method = op->profiled_method();
3707 int bci = op->profiled_bci();
3708 ciMethod* callee = op->profiled_callee();
3709 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3710
3711 // Update counter for all call types
3712 ciMethodData* md = method->method_data_or_null();
3713 assert(md != nullptr, "Sanity");
3714 ciProfileData* data = md->bci_to_data(bci);
3715 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3716 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3717 Register mdo = op->mdo()->as_register();
3718 __ mov_metadata(mdo, md->constant_encoding());
3719 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3720 // Perform additional virtual call profiling for invokevirtual and
3721 // invokeinterface bytecodes
3722 if (op->should_profile_receiver_type()) {
3723 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3724 Register recv = op->recv()->as_register();
3725 assert_different_registers(mdo, recv);
3726 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3727 ciKlass* known_klass = op->known_holder();
3728 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3729 // We know the type that will be seen at this call site; we can
3730 // statically update the MethodData* rather than needing to do
3731 // dynamic tests on the receiver type
3732
3733 // NOTE: we should probably put a lock around this search to
3734 // avoid collisions by concurrent compilations
3735 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3736 uint i;
3737 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3738 ciKlass* receiver = vc_data->receiver(i);
3739 if (known_klass->equals(receiver)) {
3740 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3741 __ addptr(data_addr, DataLayout::counter_increment);
3742 return;
3743 }
3744 }
3745
3746 // Receiver type not found in profile data; select an empty slot
3747
3748 // Note that this is less efficient than it should be because it
3749 // always does a write to the receiver part of the
3750 // VirtualCallData rather than just the first time
3751 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3752 ciKlass* receiver = vc_data->receiver(i);
3753 if (receiver == nullptr) {
3754 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3755 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3756 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3757 __ addptr(data_addr, DataLayout::counter_increment);
3758 return;
3759 }
3760 }
3761 } else {
3762 __ load_klass(recv, recv, tmp_load_klass);
3763 Label update_done;
3764 type_profile_helper(mdo, md, data, recv, &update_done);
3765 // Receiver did not match any saved receiver and there is no empty row for it.
3766 // Increment total counter to indicate polymorphic case.
3767 __ addptr(counter_addr, DataLayout::counter_increment);
3768
3769 __ bind(update_done);
3770 }
3771 } else {
3772 // Static call
3773 __ addptr(counter_addr, DataLayout::counter_increment);
3774 }
3775 }
3776
3777 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3778 Register obj = op->obj()->as_register();
3779 Register tmp = op->tmp()->as_pointer_register();
3780 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3781 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3782 ciKlass* exact_klass = op->exact_klass();
3783 intptr_t current_klass = op->current_klass();
3784 bool not_null = op->not_null();
3785 bool no_conflict = op->no_conflict();
3786
3787 Label update, next, none;
3788
3789 bool do_null = !not_null;
3790 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3791 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3792
3793 assert(do_null || do_update, "why are we here?");
3794 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3795
3796 __ verify_oop(obj);
3797
3798 #ifdef ASSERT
3799 if (obj == tmp) {
3800 #ifdef _LP64
3801 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3802 #else
3803 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3804 #endif
3805 } else {
3806 #ifdef _LP64
3807 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3808 #else
3809 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3810 #endif
3811 }
3812 #endif
3813 if (do_null) {
3814 __ testptr(obj, obj);
3815 __ jccb(Assembler::notZero, update);
3816 if (!TypeEntries::was_null_seen(current_klass)) {
3817 __ testptr(mdo_addr, TypeEntries::null_seen);
3818 #ifndef ASSERT
3819 __ jccb(Assembler::notZero, next); // already set
3820 #else
3821 __ jcc(Assembler::notZero, next); // already set
3822 #endif
3823 // atomic update to prevent overwriting Klass* with 0
3824 __ lock();
3825 __ orptr(mdo_addr, TypeEntries::null_seen);
3826 }
3827 if (do_update) {
3828 #ifndef ASSERT
3829 __ jmpb(next);
3830 }
3831 #else
3832 __ jmp(next);
3833 }
3834 } else {
3835 __ testptr(obj, obj);
3836 __ jcc(Assembler::notZero, update);
3837 __ stop("unexpected null obj");
3838 #endif
3839 }
3840
3841 __ bind(update);
3842
3843 if (do_update) {
3844 #ifdef ASSERT
3845 if (exact_klass != nullptr) {
3846 Label ok;
3847 __ load_klass(tmp, obj, tmp_load_klass);
3848 __ push(tmp);
3849 __ mov_metadata(tmp, exact_klass->constant_encoding());
3850 __ cmpptr(tmp, Address(rsp, 0));
3851 __ jcc(Assembler::equal, ok);
3852 __ stop("exact klass and actual klass differ");
3853 __ bind(ok);
3854 __ pop(tmp);
3855 }
3856 #endif
3857 if (!no_conflict) {
3858 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3859 if (exact_klass != nullptr) {
3860 __ mov_metadata(tmp, exact_klass->constant_encoding());
3861 } else {
3862 __ load_klass(tmp, obj, tmp_load_klass);
3863 }
3864 #ifdef _LP64
3865 __ mov(rscratch1, tmp); // save original value before XOR
3866 #endif
3867 __ xorptr(tmp, mdo_addr);
3868 __ testptr(tmp, TypeEntries::type_klass_mask);
3869 // klass seen before, nothing to do. The unknown bit may have been
3870 // set already but no need to check.
3871 __ jccb(Assembler::zero, next);
3872
3873 __ testptr(tmp, TypeEntries::type_unknown);
3874 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3875
3876 if (TypeEntries::is_type_none(current_klass)) {
3877 __ testptr(mdo_addr, TypeEntries::type_mask);
3878 __ jccb(Assembler::zero, none);
3879 #ifdef _LP64
3880 // There is a chance that the checks above (re-reading profiling
3881 // data from memory) fail if another thread has just set the
3882 // profiling to this obj's klass
3883 __ mov(tmp, rscratch1); // get back original value before XOR
3884 __ xorptr(tmp, mdo_addr);
3885 __ testptr(tmp, TypeEntries::type_klass_mask);
3886 __ jccb(Assembler::zero, next);
3887 #endif
3888 }
3889 } else {
3890 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3891 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3892
3893 __ testptr(mdo_addr, TypeEntries::type_unknown);
3894 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3895 }
3896
3897 // different than before. Cannot keep accurate profile.
3898 __ orptr(mdo_addr, TypeEntries::type_unknown);
3899
3900 if (TypeEntries::is_type_none(current_klass)) {
3901 __ jmpb(next);
3902
3903 __ bind(none);
3904 // first time here. Set profile type.
3905 __ movptr(mdo_addr, tmp);
3906 #ifdef ASSERT
3907 __ andptr(tmp, TypeEntries::type_klass_mask);
3908 __ verify_klass_ptr(tmp);
3909 #endif
3910 }
3911 } else {
3912 // There's a single possible klass at this profile point
3913 assert(exact_klass != nullptr, "should be");
3914 if (TypeEntries::is_type_none(current_klass)) {
3915 __ mov_metadata(tmp, exact_klass->constant_encoding());
3916 __ xorptr(tmp, mdo_addr);
3917 __ testptr(tmp, TypeEntries::type_klass_mask);
3918 #ifdef ASSERT
3919 __ jcc(Assembler::zero, next);
3920
3921 {
3922 Label ok;
3923 __ push(tmp);
3924 __ testptr(mdo_addr, TypeEntries::type_mask);
3925 __ jcc(Assembler::zero, ok);
3926 // may have been set by another thread
3927 __ mov_metadata(tmp, exact_klass->constant_encoding());
3928 __ xorptr(tmp, mdo_addr);
3929 __ testptr(tmp, TypeEntries::type_mask);
3930 __ jcc(Assembler::zero, ok);
3931
3932 __ stop("unexpected profiling mismatch");
3933 __ bind(ok);
3934 __ pop(tmp);
3935 }
3936 #else
3937 __ jccb(Assembler::zero, next);
3938 #endif
3939 // first time here. Set profile type.
3940 __ movptr(mdo_addr, tmp);
3941 #ifdef ASSERT
3942 __ andptr(tmp, TypeEntries::type_klass_mask);
3943 __ verify_klass_ptr(tmp);
3944 #endif
3945 } else {
3946 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3947 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3948
3949 __ testptr(mdo_addr, TypeEntries::type_unknown);
3950 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3951
3952 __ orptr(mdo_addr, TypeEntries::type_unknown);
3953 }
3954 }
3955 }
3956 __ bind(next);
3957 }
3958
3959 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3960 Register obj = op->obj()->as_register();
3961 Register tmp = op->tmp()->as_pointer_register();
3962 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3963 bool not_null = op->not_null();
3964 int flag = op->flag();
3965
3966 Label not_inline_type;
3967 if (!not_null) {
3968 __ testptr(obj, obj);
3969 __ jccb(Assembler::zero, not_inline_type);
3970 }
3971
3972 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3973
3974 __ orb(mdo_addr, flag);
3975
3976 __ bind(not_inline_type);
3977 }
3978
3979 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3980 Unimplemented();
3981 }
3982
3983
3984 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3985 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3986 }
3987
3988
3989 void LIR_Assembler::align_backward_branch_target() {
3990 __ align(BytesPerWord);
3991 }
3992
3993
3994 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3995 if (left->is_single_cpu()) {
3996 __ negl(left->as_register());
3997 move_regs(left->as_register(), dest->as_register());
3998
3999 } else if (left->is_double_cpu()) {
4000 Register lo = left->as_register_lo();
4001 #ifdef _LP64
4002 Register dst = dest->as_register_lo();
4003 __ movptr(dst, lo);
4004 __ negptr(dst);
4005 #else
4006 Register hi = left->as_register_hi();
4007 __ lneg(hi, lo);
4008 if (dest->as_register_lo() == hi) {
4009 assert(dest->as_register_hi() != lo, "destroying register");
4010 move_regs(hi, dest->as_register_hi());
4011 move_regs(lo, dest->as_register_lo());
4012 } else {
4013 move_regs(lo, dest->as_register_lo());
4014 move_regs(hi, dest->as_register_hi());
4015 }
4016 #endif // _LP64
4017
4018 } else if (dest->is_single_xmm()) {
4019 #ifdef _LP64
4020 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4021 assert(tmp->is_valid(), "need temporary");
4022 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
4023 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
4024 }
4025 else
4026 #endif
4027 {
4028 assert(!tmp->is_valid(), "do not need temporary");
4029 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
4030 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
4031 }
4032 __ xorps(dest->as_xmm_float_reg(),
4033 ExternalAddress((address)float_signflip_pool),
4034 rscratch1);
4035 }
4036 } else if (dest->is_double_xmm()) {
4037 #ifdef _LP64
4038 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4039 assert(tmp->is_valid(), "need temporary");
4040 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
4041 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
4042 }
4043 else
4044 #endif
4045 {
4046 assert(!tmp->is_valid(), "do not need temporary");
4047 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
4048 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
4049 }
4050 __ xorpd(dest->as_xmm_double_reg(),
4051 ExternalAddress((address)double_signflip_pool),
4052 rscratch1);
4053 }
4054 #ifndef _LP64
4055 } else if (left->is_single_fpu() || left->is_double_fpu()) {
4056 assert(left->fpu() == 0, "arg must be on TOS");
4057 assert(dest->fpu() == 0, "dest must be TOS");
4058 __ fchs();
4059 #endif // !_LP64
4060
4061 } else {
4062 ShouldNotReachHere();
4063 }
4064 }
4065
4066
4067 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
4068 assert(src->is_address(), "must be an address");
4069 assert(dest->is_register(), "must be a register");
4070
4071 PatchingStub* patch = nullptr;
4072 if (patch_code != lir_patch_none) {
4073 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
4074 }
4075
4076 Register reg = dest->as_pointer_register();
4077 LIR_Address* addr = src->as_address_ptr();
4078 __ lea(reg, as_Address(addr));
4079
4080 if (patch != nullptr) {
4081 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
4082 }
4083 }
4084
4085
4086
4087 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
4088 assert(!tmp->is_valid(), "don't need temporary");
4089 __ call(RuntimeAddress(dest));
4090 if (info != nullptr) {
4091 add_call_info_here(info);
4092 }
4093 __ post_call_nop();
4094 }
4095
4096
4097 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
4098 assert(type == T_LONG, "only for volatile long fields");
4099
4100 if (info != nullptr) {
4101 add_debug_info_for_null_check_here(info);
4102 }
4103
4104 if (src->is_double_xmm()) {
4105 if (dest->is_double_cpu()) {
4106 #ifdef _LP64
4107 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
4108 #else
4109 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
4110 __ psrlq(src->as_xmm_double_reg(), 32);
4111 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
4112 #endif // _LP64
4113 } else if (dest->is_double_stack()) {
4114 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
4115 } else if (dest->is_address()) {
4116 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
4117 } else {
4118 ShouldNotReachHere();
4119 }
4120
4121 } else if (dest->is_double_xmm()) {
4122 if (src->is_double_stack()) {
4123 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
4124 } else if (src->is_address()) {
4125 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
4126 } else {
4127 ShouldNotReachHere();
4128 }
4129
4130 #ifndef _LP64
4131 } else if (src->is_double_fpu()) {
4132 assert(src->fpu_regnrLo() == 0, "must be TOS");
4133 if (dest->is_double_stack()) {
4134 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
4135 } else if (dest->is_address()) {
4136 __ fistp_d(as_Address(dest->as_address_ptr()));
4137 } else {
4138 ShouldNotReachHere();
4139 }
4140
4141 } else if (dest->is_double_fpu()) {
4142 assert(dest->fpu_regnrLo() == 0, "must be TOS");
4143 if (src->is_double_stack()) {
4144 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
4145 } else if (src->is_address()) {
4146 __ fild_d(as_Address(src->as_address_ptr()));
4147 } else {
4148 ShouldNotReachHere();
4149 }
4150 #endif // !_LP64
4151
4152 } else {
4153 ShouldNotReachHere();
4154 }
4155 }
4156
4157 #ifdef ASSERT
4158 // emit run-time assertion
4159 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
4160 assert(op->code() == lir_assert, "must be");
4161
4162 if (op->in_opr1()->is_valid()) {
4163 assert(op->in_opr2()->is_valid(), "both operands must be valid");
4164 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
4165 } else {
4166 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
4167 assert(op->condition() == lir_cond_always, "no other conditions allowed");
4168 }
4169
4170 Label ok;
4171 if (op->condition() != lir_cond_always) {
4172 Assembler::Condition acond = Assembler::zero;
4173 switch (op->condition()) {
4174 case lir_cond_equal: acond = Assembler::equal; break;
4175 case lir_cond_notEqual: acond = Assembler::notEqual; break;
4176 case lir_cond_less: acond = Assembler::less; break;
4177 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
4178 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
4179 case lir_cond_greater: acond = Assembler::greater; break;
4180 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
4181 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
4182 default: ShouldNotReachHere();
4183 }
4184 __ jcc(acond, ok);
4185 }
4186 if (op->halt()) {
4187 const char* str = __ code_string(op->msg());
4188 __ stop(str);
4189 } else {
4190 breakpoint();
4191 }
4192 __ bind(ok);
4193 }
4194 #endif
4195
4196 void LIR_Assembler::membar() {
4197 // QQQ sparc TSO uses this,
4198 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4199 }
4200
4201 void LIR_Assembler::membar_acquire() {
4202 // No x86 machines currently require load fences
4203 }
4204
4205 void LIR_Assembler::membar_release() {
4206 // No x86 machines currently require store fences
4207 }
4208
4209 void LIR_Assembler::membar_loadload() {
4210 // no-op
4211 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4212 }
4213
4214 void LIR_Assembler::membar_storestore() {
4215 // no-op
4216 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4217 }
4218
4219 void LIR_Assembler::membar_loadstore() {
4220 // no-op
4221 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4222 }
4223
4224 void LIR_Assembler::membar_storeload() {
4225 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4226 }
4227
4228 void LIR_Assembler::on_spin_wait() {
4229 __ pause ();
4230 }
4231
4232 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4233 assert(result_reg->is_register(), "check");
4234 #ifdef _LP64
4235 // __ get_thread(result_reg->as_register_lo());
4236 __ mov(result_reg->as_register(), r15_thread);
4237 #else
4238 __ get_thread(result_reg->as_register());
4239 #endif // _LP64
4240 }
4241
4242 void LIR_Assembler::check_orig_pc() {
4243 __ cmpptr(frame_map()->address_for_orig_pc_addr(), NULL_WORD);
4244 }
4245
4246 void LIR_Assembler::peephole(LIR_List*) {
4247 // do nothing for now
4248 }
4249
4250 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4251 assert(data == dest, "xchg/xadd uses only 2 operands");
4252
4253 if (data->type() == T_INT) {
4254 if (code == lir_xadd) {
4255 __ lock();
4256 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4257 } else {
4258 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4259 }
4260 } else if (data->is_oop()) {
4261 assert (code == lir_xchg, "xadd for oops");
4262 Register obj = data->as_register();
4263 #ifdef _LP64
4264 if (UseCompressedOops) {
4265 __ encode_heap_oop(obj);
4266 __ xchgl(obj, as_Address(src->as_address_ptr()));
4267 __ decode_heap_oop(obj);
4268 } else {
4269 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4270 }
4271 #else
4272 __ xchgl(obj, as_Address(src->as_address_ptr()));
4273 #endif
4274 } else if (data->type() == T_LONG) {
4275 #ifdef _LP64
4276 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4277 if (code == lir_xadd) {
4278 __ lock();
4279 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4280 } else {
4281 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4282 }
4283 #else
4284 ShouldNotReachHere();
4285 #endif
4286 } else {
4287 ShouldNotReachHere();
4288 }
4289 }
4290
4291 #undef __