1 /* 2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_CodeStubs.hpp" 29 #include "c1/c1_Compilation.hpp" 30 #include "c1/c1_LIRAssembler.hpp" 31 #include "c1/c1_MacroAssembler.hpp" 32 #include "c1/c1_Runtime1.hpp" 33 #include "c1/c1_ValueStack.hpp" 34 #include "ci/ciArrayKlass.hpp" 35 #include "ci/ciInlineKlass.hpp" 36 #include "ci/ciInstance.hpp" 37 #include "compiler/oopMap.hpp" 38 #include "gc/shared/collectedHeap.hpp" 39 #include "gc/shared/gc_globals.hpp" 40 #include "nativeInst_x86.hpp" 41 #include "oops/oop.inline.hpp" 42 #include "oops/objArrayKlass.hpp" 43 #include "runtime/frame.inline.hpp" 44 #include "runtime/safepointMechanism.hpp" 45 #include "runtime/sharedRuntime.hpp" 46 #include "runtime/stubRoutines.hpp" 47 #include "utilities/powerOfTwo.hpp" 48 #include "vmreg_x86.inline.hpp" 49 50 51 // These masks are used to provide 128-bit aligned bitmasks to the XMM 52 // instructions, to allow sign-masking or sign-bit flipping. They allow 53 // fast versions of NegF/NegD and AbsF/AbsD. 54 55 // Note: 'double' and 'long long' have 32-bits alignment on x86. 56 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 58 // of 128-bits operands for SSE instructions. 59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 60 // Store the value to a 128-bits operand. 61 operand[0] = lo; 62 operand[1] = hi; 63 return operand; 64 } 65 66 // Buffer for 128-bits masks used by SSE instructions. 67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 68 69 // Static initialization during VM startup. 70 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 71 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 72 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 73 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 74 75 76 NEEDS_CLEANUP // remove this definitions ? 77 const Register SYNC_header = rax; // synchronization header 78 const Register SHIFT_count = rcx; // where count for shift operations must be 79 80 #define __ _masm-> 81 82 83 static void select_different_registers(Register preserve, 84 Register extra, 85 Register &tmp1, 86 Register &tmp2) { 87 if (tmp1 == preserve) { 88 assert_different_registers(tmp1, tmp2, extra); 89 tmp1 = extra; 90 } else if (tmp2 == preserve) { 91 assert_different_registers(tmp1, tmp2, extra); 92 tmp2 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2); 95 } 96 97 98 99 static void select_different_registers(Register preserve, 100 Register extra, 101 Register &tmp1, 102 Register &tmp2, 103 Register &tmp3) { 104 if (tmp1 == preserve) { 105 assert_different_registers(tmp1, tmp2, tmp3, extra); 106 tmp1 = extra; 107 } else if (tmp2 == preserve) { 108 assert_different_registers(tmp1, tmp2, tmp3, extra); 109 tmp2 = extra; 110 } else if (tmp3 == preserve) { 111 assert_different_registers(tmp1, tmp2, tmp3, extra); 112 tmp3 = extra; 113 } 114 assert_different_registers(preserve, tmp1, tmp2, tmp3); 115 } 116 117 118 119 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 120 if (opr->is_constant()) { 121 LIR_Const* constant = opr->as_constant_ptr(); 122 switch (constant->type()) { 123 case T_INT: { 124 return true; 125 } 126 127 default: 128 return false; 129 } 130 } 131 return false; 132 } 133 134 135 LIR_Opr LIR_Assembler::receiverOpr() { 136 return FrameMap::receiver_opr; 137 } 138 139 LIR_Opr LIR_Assembler::osrBufferPointer() { 140 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 141 } 142 143 //--------------fpu register translations----------------------- 144 145 146 address LIR_Assembler::float_constant(float f) { 147 address const_addr = __ float_constant(f); 148 if (const_addr == nullptr) { 149 bailout("const section overflow"); 150 return __ code()->consts()->start(); 151 } else { 152 return const_addr; 153 } 154 } 155 156 157 address LIR_Assembler::double_constant(double d) { 158 address const_addr = __ double_constant(d); 159 if (const_addr == nullptr) { 160 bailout("const section overflow"); 161 return __ code()->consts()->start(); 162 } else { 163 return const_addr; 164 } 165 } 166 167 #ifndef _LP64 168 void LIR_Assembler::fpop() { 169 __ fpop(); 170 } 171 172 void LIR_Assembler::fxch(int i) { 173 __ fxch(i); 174 } 175 176 void LIR_Assembler::fld(int i) { 177 __ fld_s(i); 178 } 179 180 void LIR_Assembler::ffree(int i) { 181 __ ffree(i); 182 } 183 #endif // !_LP64 184 185 void LIR_Assembler::breakpoint() { 186 __ int3(); 187 } 188 189 void LIR_Assembler::push(LIR_Opr opr) { 190 if (opr->is_single_cpu()) { 191 __ push_reg(opr->as_register()); 192 } else if (opr->is_double_cpu()) { 193 NOT_LP64(__ push_reg(opr->as_register_hi())); 194 __ push_reg(opr->as_register_lo()); 195 } else if (opr->is_stack()) { 196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 197 } else if (opr->is_constant()) { 198 LIR_Const* const_opr = opr->as_constant_ptr(); 199 if (const_opr->type() == T_OBJECT) { 200 __ push_oop(const_opr->as_jobject(), rscratch1); 201 } else if (const_opr->type() == T_INT) { 202 __ push_jint(const_opr->as_jint()); 203 } else { 204 ShouldNotReachHere(); 205 } 206 207 } else { 208 ShouldNotReachHere(); 209 } 210 } 211 212 void LIR_Assembler::pop(LIR_Opr opr) { 213 if (opr->is_single_cpu()) { 214 __ pop_reg(opr->as_register()); 215 } else { 216 ShouldNotReachHere(); 217 } 218 } 219 220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 221 return addr->base()->is_illegal() && addr->index()->is_illegal(); 222 } 223 224 //------------------------------------------- 225 226 Address LIR_Assembler::as_Address(LIR_Address* addr) { 227 return as_Address(addr, rscratch1); 228 } 229 230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 231 if (addr->base()->is_illegal()) { 232 assert(addr->index()->is_illegal(), "must be illegal too"); 233 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 234 if (! __ reachable(laddr)) { 235 __ movptr(tmp, laddr.addr()); 236 Address res(tmp, 0); 237 return res; 238 } else { 239 return __ as_Address(laddr); 240 } 241 } 242 243 Register base = addr->base()->as_pointer_register(); 244 245 if (addr->index()->is_illegal()) { 246 return Address( base, addr->disp()); 247 } else if (addr->index()->is_cpu_register()) { 248 Register index = addr->index()->as_pointer_register(); 249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 250 } else if (addr->index()->is_constant()) { 251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 252 assert(Assembler::is_simm32(addr_offset), "must be"); 253 254 return Address(base, addr_offset); 255 } else { 256 Unimplemented(); 257 return Address(); 258 } 259 } 260 261 262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 263 Address base = as_Address(addr); 264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 265 } 266 267 268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 269 return as_Address(addr); 270 } 271 272 273 void LIR_Assembler::osr_entry() { 274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 275 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 276 ValueStack* entry_state = osr_entry->state(); 277 int number_of_locks = entry_state->locks_size(); 278 279 // we jump here if osr happens with the interpreter 280 // state set up to continue at the beginning of the 281 // loop that triggered osr - in particular, we have 282 // the following registers setup: 283 // 284 // rcx: osr buffer 285 // 286 287 // build frame 288 ciMethod* m = compilation()->method(); 289 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 290 291 // OSR buffer is 292 // 293 // locals[nlocals-1..0] 294 // monitors[0..number_of_locks] 295 // 296 // locals is a direct copy of the interpreter frame so in the osr buffer 297 // so first slot in the local array is the last local from the interpreter 298 // and last slot is local[0] (receiver) from the interpreter 299 // 300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 302 // in the interpreter frame (the method lock if a sync method) 303 304 // Initialize monitors in the compiled activation. 305 // rcx: pointer to osr buffer 306 // 307 // All other registers are dead at this point and the locals will be 308 // copied into place by code emitted in the IR. 309 310 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 312 int monitor_offset = BytesPerWord * method()->max_locals() + 313 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 315 // the OSR buffer using 2 word entries: first the lock and then 316 // the oop. 317 for (int i = 0; i < number_of_locks; i++) { 318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 319 #ifdef ASSERT 320 // verify the interpreter's monitor has a non-null object 321 { 322 Label L; 323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD); 324 __ jcc(Assembler::notZero, L); 325 __ stop("locked object is null"); 326 __ bind(L); 327 } 328 #endif 329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 332 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 333 } 334 } 335 } 336 337 338 // inline cache check; done before the frame is built. 339 int LIR_Assembler::check_icache() { 340 return __ ic_check(CodeEntryAlignment); 341 } 342 343 void LIR_Assembler::clinit_barrier(ciMethod* method) { 344 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 345 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 346 347 Label L_skip_barrier; 348 Register klass = rscratch1; 349 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg ); 350 assert(thread != noreg, "x86_32 not implemented"); 351 352 __ mov_metadata(klass, method->holder()->constant_encoding()); 353 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/); 354 355 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 356 357 __ bind(L_skip_barrier); 358 } 359 360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 361 jobject o = nullptr; 362 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 363 __ movoop(reg, o); 364 patching_epilog(patch, lir_patch_normal, reg, info); 365 } 366 367 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 368 Metadata* o = nullptr; 369 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 370 __ mov_metadata(reg, o); 371 patching_epilog(patch, lir_patch_normal, reg, info); 372 } 373 374 // This specifies the rsp decrement needed to build the frame 375 int LIR_Assembler::initial_frame_size_in_bytes() const { 376 // if rounding, must let FrameMap know! 377 378 // The frame_map records size in slots (32bit word) 379 380 // subtract two words to account for return address and link 381 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 382 } 383 384 385 int LIR_Assembler::emit_exception_handler() { 386 // generate code for exception handler 387 address handler_base = __ start_a_stub(exception_handler_size()); 388 if (handler_base == nullptr) { 389 // not enough space left for the handler 390 bailout("exception handler overflow"); 391 return -1; 392 } 393 394 int offset = code_offset(); 395 396 // the exception oop and pc are in rax, and rdx 397 // no other registers need to be preserved, so invalidate them 398 __ invalidate_registers(false, true, true, false, true, true); 399 400 // check that there is really an exception 401 __ verify_not_null_oop(rax); 402 403 // search an exception handler (rax: exception oop, rdx: throwing pc) 404 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 405 __ should_not_reach_here(); 406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 407 __ end_a_stub(); 408 409 return offset; 410 } 411 412 413 // Emit the code to remove the frame from the stack in the exception 414 // unwind path. 415 int LIR_Assembler::emit_unwind_handler() { 416 #ifndef PRODUCT 417 if (CommentedAssembly) { 418 _masm->block_comment("Unwind handler"); 419 } 420 #endif 421 422 int offset = code_offset(); 423 424 // Fetch the exception from TLS and clear out exception related thread state 425 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 426 NOT_LP64(__ get_thread(thread)); 427 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 428 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD); 429 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD); 430 431 __ bind(_unwind_handler_entry); 432 __ verify_not_null_oop(rax); 433 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 434 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 435 } 436 437 // Perform needed unlocking 438 MonitorExitStub* stub = nullptr; 439 if (method()->is_synchronized()) { 440 monitor_address(0, FrameMap::rax_opr); 441 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 442 if (LockingMode == LM_MONITOR) { 443 __ jmp(*stub->entry()); 444 } else { 445 __ unlock_object(rdi, rsi, rax, *stub->entry()); 446 } 447 __ bind(*stub->continuation()); 448 } 449 450 if (compilation()->env()->dtrace_method_probes()) { 451 #ifdef _LP64 452 __ mov(rdi, r15_thread); 453 __ mov_metadata(rsi, method()->constant_encoding()); 454 #else 455 __ get_thread(rax); 456 __ movptr(Address(rsp, 0), rax); 457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg); 458 #endif 459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 460 } 461 462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 463 __ mov(rax, rbx); // Restore the exception 464 } 465 466 // remove the activation and dispatch to the unwind handler 467 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair()); 468 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 469 470 // Emit the slow path assembly 471 if (stub != nullptr) { 472 stub->emit_code(this); 473 } 474 475 return offset; 476 } 477 478 479 int LIR_Assembler::emit_deopt_handler() { 480 // generate code for exception handler 481 address handler_base = __ start_a_stub(deopt_handler_size()); 482 if (handler_base == nullptr) { 483 // not enough space left for the handler 484 bailout("deopt handler overflow"); 485 return -1; 486 } 487 488 int offset = code_offset(); 489 InternalAddress here(__ pc()); 490 491 __ pushptr(here.addr(), rscratch1); 492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 493 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 494 __ end_a_stub(); 495 496 return offset; 497 } 498 499 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 501 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 502 assert(result->fpu() == 0, "result must already be on TOS"); 503 } 504 if (InlineTypeReturnedAsFields) { 505 #ifndef _LP64 506 Unimplemented(); 507 #endif 508 // Check if we are returning an non-null inline type and load its fields into registers 509 ciType* return_type = compilation()->method()->return_type(); 510 if (return_type->is_inlinetype()) { 511 ciInlineKlass* vk = return_type->as_inline_klass(); 512 if (vk->can_be_returned_as_fields()) { 513 address unpack_handler = vk->unpack_handler(); 514 assert(unpack_handler != nullptr, "must be"); 515 __ call(RuntimeAddress(unpack_handler)); 516 } 517 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) { 518 Label skip; 519 __ test_oop_is_not_inline_type(rax, rscratch1, skip); 520 521 // Load fields from a buffered value with an inline class specific handler 522 __ load_klass(rdi, rax, rscratch1); 523 __ movptr(rdi, Address(rdi, InstanceKlass::adr_inlineklass_fixed_block_offset())); 524 __ movptr(rdi, Address(rdi, InlineKlass::unpack_handler_offset())); 525 // Unpack handler can be null if inline type is not scalarizable in returns 526 __ testptr(rdi, rdi); 527 __ jcc(Assembler::zero, skip); 528 __ call(rdi); 529 530 __ bind(skip); 531 } 532 // At this point, rax points to the value object (for interpreter or C1 caller). 533 // The fields of the object are copied into registers (for C2 caller). 534 } 535 536 // Pop the stack before the safepoint code 537 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair()); 538 539 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 540 __ reserved_stack_check(); 541 } 542 543 // Note: we do not need to round double result; float result has the right precision 544 // the poll sets the condition code, but no data registers 545 546 #ifdef _LP64 547 const Register thread = r15_thread; 548 #else 549 const Register thread = rbx; 550 __ get_thread(thread); 551 #endif 552 code_stub->set_safepoint_offset(__ offset()); 553 __ relocate(relocInfo::poll_return_type); 554 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */); 555 __ ret(0); 556 } 557 558 559 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) { 560 return (__ store_inline_type_fields_to_buf(vk, false)); 561 } 562 563 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 564 guarantee(info != nullptr, "Shouldn't be null"); 565 int offset = __ offset(); 566 #ifdef _LP64 567 const Register poll_addr = rscratch1; 568 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset())); 569 #else 570 assert(tmp->is_cpu_register(), "needed"); 571 const Register poll_addr = tmp->as_register(); 572 __ get_thread(poll_addr); 573 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset()))); 574 #endif 575 add_debug_info_for_branch(info); 576 __ relocate(relocInfo::poll_type); 577 address pre_pc = __ pc(); 578 __ testl(rax, Address(poll_addr, 0)); 579 address post_pc = __ pc(); 580 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 581 return offset; 582 } 583 584 585 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 586 if (from_reg != to_reg) __ mov(to_reg, from_reg); 587 } 588 589 void LIR_Assembler::swap_reg(Register a, Register b) { 590 __ xchgptr(a, b); 591 } 592 593 594 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 595 assert(src->is_constant(), "should not call otherwise"); 596 assert(dest->is_register(), "should not call otherwise"); 597 LIR_Const* c = src->as_constant_ptr(); 598 599 switch (c->type()) { 600 case T_INT: { 601 assert(patch_code == lir_patch_none, "no patching handled here"); 602 __ movl(dest->as_register(), c->as_jint()); 603 break; 604 } 605 606 case T_ADDRESS: { 607 assert(patch_code == lir_patch_none, "no patching handled here"); 608 __ movptr(dest->as_register(), c->as_jint()); 609 break; 610 } 611 612 case T_LONG: { 613 assert(patch_code == lir_patch_none, "no patching handled here"); 614 #ifdef _LP64 615 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 616 #else 617 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 618 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 619 #endif // _LP64 620 break; 621 } 622 623 case T_OBJECT: { 624 if (patch_code != lir_patch_none) { 625 jobject2reg_with_patching(dest->as_register(), info); 626 } else { 627 __ movoop(dest->as_register(), c->as_jobject()); 628 } 629 break; 630 } 631 632 case T_METADATA: { 633 if (patch_code != lir_patch_none) { 634 klass2reg_with_patching(dest->as_register(), info); 635 } else { 636 __ mov_metadata(dest->as_register(), c->as_metadata()); 637 } 638 break; 639 } 640 641 case T_FLOAT: { 642 if (dest->is_single_xmm()) { 643 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) { 644 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 645 } else { 646 __ movflt(dest->as_xmm_float_reg(), 647 InternalAddress(float_constant(c->as_jfloat()))); 648 } 649 } else { 650 #ifndef _LP64 651 assert(dest->is_single_fpu(), "must be"); 652 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 653 if (c->is_zero_float()) { 654 __ fldz(); 655 } else if (c->is_one_float()) { 656 __ fld1(); 657 } else { 658 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 659 } 660 #else 661 ShouldNotReachHere(); 662 #endif // !_LP64 663 } 664 break; 665 } 666 667 case T_DOUBLE: { 668 if (dest->is_double_xmm()) { 669 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) { 670 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 671 } else { 672 __ movdbl(dest->as_xmm_double_reg(), 673 InternalAddress(double_constant(c->as_jdouble()))); 674 } 675 } else { 676 #ifndef _LP64 677 assert(dest->is_double_fpu(), "must be"); 678 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 679 if (c->is_zero_double()) { 680 __ fldz(); 681 } else if (c->is_one_double()) { 682 __ fld1(); 683 } else { 684 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 685 } 686 #else 687 ShouldNotReachHere(); 688 #endif // !_LP64 689 } 690 break; 691 } 692 693 default: 694 ShouldNotReachHere(); 695 } 696 } 697 698 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 699 assert(src->is_constant(), "should not call otherwise"); 700 assert(dest->is_stack(), "should not call otherwise"); 701 LIR_Const* c = src->as_constant_ptr(); 702 703 switch (c->type()) { 704 case T_INT: // fall through 705 case T_FLOAT: 706 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 707 break; 708 709 case T_ADDRESS: 710 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 711 break; 712 713 case T_OBJECT: 714 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1); 715 break; 716 717 case T_LONG: // fall through 718 case T_DOUBLE: 719 #ifdef _LP64 720 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 721 lo_word_offset_in_bytes), 722 (intptr_t)c->as_jlong_bits(), 723 rscratch1); 724 #else 725 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 726 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 727 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 728 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 729 #endif // _LP64 730 break; 731 732 default: 733 ShouldNotReachHere(); 734 } 735 } 736 737 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 738 assert(src->is_constant(), "should not call otherwise"); 739 assert(dest->is_address(), "should not call otherwise"); 740 LIR_Const* c = src->as_constant_ptr(); 741 LIR_Address* addr = dest->as_address_ptr(); 742 743 int null_check_here = code_offset(); 744 switch (type) { 745 case T_INT: // fall through 746 case T_FLOAT: 747 __ movl(as_Address(addr), c->as_jint_bits()); 748 break; 749 750 case T_ADDRESS: 751 __ movptr(as_Address(addr), c->as_jint_bits()); 752 break; 753 754 case T_OBJECT: // fall through 755 case T_ARRAY: 756 if (c->as_jobject() == nullptr) { 757 if (UseCompressedOops && !wide) { 758 __ movl(as_Address(addr), NULL_WORD); 759 } else { 760 #ifdef _LP64 761 __ xorptr(rscratch1, rscratch1); 762 null_check_here = code_offset(); 763 __ movptr(as_Address(addr), rscratch1); 764 #else 765 __ movptr(as_Address(addr), NULL_WORD); 766 #endif 767 } 768 } else { 769 if (is_literal_address(addr)) { 770 ShouldNotReachHere(); 771 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1); 772 } else { 773 #ifdef _LP64 774 __ movoop(rscratch1, c->as_jobject()); 775 if (UseCompressedOops && !wide) { 776 __ encode_heap_oop(rscratch1); 777 null_check_here = code_offset(); 778 __ movl(as_Address_lo(addr), rscratch1); 779 } else { 780 null_check_here = code_offset(); 781 __ movptr(as_Address_lo(addr), rscratch1); 782 } 783 #else 784 __ movoop(as_Address(addr), c->as_jobject(), noreg); 785 #endif 786 } 787 } 788 break; 789 790 case T_LONG: // fall through 791 case T_DOUBLE: 792 #ifdef _LP64 793 if (is_literal_address(addr)) { 794 ShouldNotReachHere(); 795 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 796 } else { 797 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 798 null_check_here = code_offset(); 799 __ movptr(as_Address_lo(addr), r10); 800 } 801 #else 802 // Always reachable in 32bit so this doesn't produce useless move literal 803 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 804 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 805 #endif // _LP64 806 break; 807 808 case T_BOOLEAN: // fall through 809 case T_BYTE: 810 __ movb(as_Address(addr), c->as_jint() & 0xFF); 811 break; 812 813 case T_CHAR: // fall through 814 case T_SHORT: 815 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 816 break; 817 818 default: 819 ShouldNotReachHere(); 820 }; 821 822 if (info != nullptr) { 823 add_debug_info_for_null_check(null_check_here, info); 824 } 825 } 826 827 828 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 829 assert(src->is_register(), "should not call otherwise"); 830 assert(dest->is_register(), "should not call otherwise"); 831 832 // move between cpu-registers 833 if (dest->is_single_cpu()) { 834 #ifdef _LP64 835 if (src->type() == T_LONG) { 836 // Can do LONG -> OBJECT 837 move_regs(src->as_register_lo(), dest->as_register()); 838 return; 839 } 840 #endif 841 assert(src->is_single_cpu(), "must match"); 842 if (src->type() == T_OBJECT) { 843 __ verify_oop(src->as_register()); 844 } 845 move_regs(src->as_register(), dest->as_register()); 846 847 } else if (dest->is_double_cpu()) { 848 #ifdef _LP64 849 if (is_reference_type(src->type())) { 850 // Surprising to me but we can see move of a long to t_object 851 __ verify_oop(src->as_register()); 852 move_regs(src->as_register(), dest->as_register_lo()); 853 return; 854 } 855 #endif 856 assert(src->is_double_cpu(), "must match"); 857 Register f_lo = src->as_register_lo(); 858 Register f_hi = src->as_register_hi(); 859 Register t_lo = dest->as_register_lo(); 860 Register t_hi = dest->as_register_hi(); 861 #ifdef _LP64 862 assert(f_hi == f_lo, "must be same"); 863 assert(t_hi == t_lo, "must be same"); 864 move_regs(f_lo, t_lo); 865 #else 866 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 867 868 869 if (f_lo == t_hi && f_hi == t_lo) { 870 swap_reg(f_lo, f_hi); 871 } else if (f_hi == t_lo) { 872 assert(f_lo != t_hi, "overwriting register"); 873 move_regs(f_hi, t_hi); 874 move_regs(f_lo, t_lo); 875 } else { 876 assert(f_hi != t_lo, "overwriting register"); 877 move_regs(f_lo, t_lo); 878 move_regs(f_hi, t_hi); 879 } 880 #endif // LP64 881 882 #ifndef _LP64 883 // special moves from fpu-register to xmm-register 884 // necessary for method results 885 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 886 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 887 __ fld_s(Address(rsp, 0)); 888 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 889 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 890 __ fld_d(Address(rsp, 0)); 891 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 892 __ fstp_s(Address(rsp, 0)); 893 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 894 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 895 __ fstp_d(Address(rsp, 0)); 896 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 897 #endif // !_LP64 898 899 // move between xmm-registers 900 } else if (dest->is_single_xmm()) { 901 assert(src->is_single_xmm(), "must match"); 902 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 903 } else if (dest->is_double_xmm()) { 904 assert(src->is_double_xmm(), "must match"); 905 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 906 907 #ifndef _LP64 908 // move between fpu-registers (no instruction necessary because of fpu-stack) 909 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 910 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 911 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 912 #endif // !_LP64 913 914 } else { 915 ShouldNotReachHere(); 916 } 917 } 918 919 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 920 assert(src->is_register(), "should not call otherwise"); 921 assert(dest->is_stack(), "should not call otherwise"); 922 923 if (src->is_single_cpu()) { 924 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 925 if (is_reference_type(type)) { 926 __ verify_oop(src->as_register()); 927 __ movptr (dst, src->as_register()); 928 } else if (type == T_METADATA || type == T_ADDRESS) { 929 __ movptr (dst, src->as_register()); 930 } else { 931 __ movl (dst, src->as_register()); 932 } 933 934 } else if (src->is_double_cpu()) { 935 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 936 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 937 __ movptr (dstLO, src->as_register_lo()); 938 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 939 940 } else if (src->is_single_xmm()) { 941 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 942 __ movflt(dst_addr, src->as_xmm_float_reg()); 943 944 } else if (src->is_double_xmm()) { 945 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 946 __ movdbl(dst_addr, src->as_xmm_double_reg()); 947 948 #ifndef _LP64 949 } else if (src->is_single_fpu()) { 950 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 951 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 952 if (pop_fpu_stack) __ fstp_s (dst_addr); 953 else __ fst_s (dst_addr); 954 955 } else if (src->is_double_fpu()) { 956 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 957 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 958 if (pop_fpu_stack) __ fstp_d (dst_addr); 959 else __ fst_d (dst_addr); 960 #endif // !_LP64 961 962 } else { 963 ShouldNotReachHere(); 964 } 965 } 966 967 968 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { 969 LIR_Address* to_addr = dest->as_address_ptr(); 970 PatchingStub* patch = nullptr; 971 Register compressed_src = rscratch1; 972 973 if (is_reference_type(type)) { 974 __ verify_oop(src->as_register()); 975 #ifdef _LP64 976 if (UseCompressedOops && !wide) { 977 __ movptr(compressed_src, src->as_register()); 978 __ encode_heap_oop(compressed_src); 979 if (patch_code != lir_patch_none) { 980 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 981 } 982 } 983 #endif 984 } 985 986 if (patch_code != lir_patch_none) { 987 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 988 Address toa = as_Address(to_addr); 989 assert(toa.disp() != 0, "must have"); 990 } 991 992 int null_check_here = code_offset(); 993 switch (type) { 994 case T_FLOAT: { 995 #ifdef _LP64 996 assert(src->is_single_xmm(), "not a float"); 997 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 998 #else 999 if (src->is_single_xmm()) { 1000 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 1001 } else { 1002 assert(src->is_single_fpu(), "must be"); 1003 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 1004 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 1005 else __ fst_s (as_Address(to_addr)); 1006 } 1007 #endif // _LP64 1008 break; 1009 } 1010 1011 case T_DOUBLE: { 1012 #ifdef _LP64 1013 assert(src->is_double_xmm(), "not a double"); 1014 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1015 #else 1016 if (src->is_double_xmm()) { 1017 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1018 } else { 1019 assert(src->is_double_fpu(), "must be"); 1020 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1021 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1022 else __ fst_d (as_Address(to_addr)); 1023 } 1024 #endif // _LP64 1025 break; 1026 } 1027 1028 case T_ARRAY: // fall through 1029 case T_OBJECT: // fall through 1030 if (UseCompressedOops && !wide) { 1031 __ movl(as_Address(to_addr), compressed_src); 1032 } else { 1033 __ movptr(as_Address(to_addr), src->as_register()); 1034 } 1035 break; 1036 case T_METADATA: 1037 // We get here to store a method pointer to the stack to pass to 1038 // a dtrace runtime call. This can't work on 64 bit with 1039 // compressed klass ptrs: T_METADATA can be a compressed klass 1040 // ptr or a 64 bit method pointer. 1041 LP64_ONLY(ShouldNotReachHere()); 1042 __ movptr(as_Address(to_addr), src->as_register()); 1043 break; 1044 case T_ADDRESS: 1045 __ movptr(as_Address(to_addr), src->as_register()); 1046 break; 1047 case T_INT: 1048 __ movl(as_Address(to_addr), src->as_register()); 1049 break; 1050 1051 case T_LONG: { 1052 Register from_lo = src->as_register_lo(); 1053 Register from_hi = src->as_register_hi(); 1054 #ifdef _LP64 1055 __ movptr(as_Address_lo(to_addr), from_lo); 1056 #else 1057 Register base = to_addr->base()->as_register(); 1058 Register index = noreg; 1059 if (to_addr->index()->is_register()) { 1060 index = to_addr->index()->as_register(); 1061 } 1062 if (base == from_lo || index == from_lo) { 1063 assert(base != from_hi, "can't be"); 1064 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1065 __ movl(as_Address_hi(to_addr), from_hi); 1066 if (patch != nullptr) { 1067 patching_epilog(patch, lir_patch_high, base, info); 1068 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1069 patch_code = lir_patch_low; 1070 } 1071 __ movl(as_Address_lo(to_addr), from_lo); 1072 } else { 1073 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1074 __ movl(as_Address_lo(to_addr), from_lo); 1075 if (patch != nullptr) { 1076 patching_epilog(patch, lir_patch_low, base, info); 1077 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1078 patch_code = lir_patch_high; 1079 } 1080 __ movl(as_Address_hi(to_addr), from_hi); 1081 } 1082 #endif // _LP64 1083 break; 1084 } 1085 1086 case T_BYTE: // fall through 1087 case T_BOOLEAN: { 1088 Register src_reg = src->as_register(); 1089 Address dst_addr = as_Address(to_addr); 1090 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1091 __ movb(dst_addr, src_reg); 1092 break; 1093 } 1094 1095 case T_CHAR: // fall through 1096 case T_SHORT: 1097 __ movw(as_Address(to_addr), src->as_register()); 1098 break; 1099 1100 default: 1101 ShouldNotReachHere(); 1102 } 1103 if (info != nullptr) { 1104 add_debug_info_for_null_check(null_check_here, info); 1105 } 1106 1107 if (patch_code != lir_patch_none) { 1108 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1109 } 1110 } 1111 1112 1113 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1114 assert(src->is_stack(), "should not call otherwise"); 1115 assert(dest->is_register(), "should not call otherwise"); 1116 1117 if (dest->is_single_cpu()) { 1118 if (is_reference_type(type)) { 1119 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1120 __ verify_oop(dest->as_register()); 1121 } else if (type == T_METADATA || type == T_ADDRESS) { 1122 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1123 } else { 1124 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1125 } 1126 1127 } else if (dest->is_double_cpu()) { 1128 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1129 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1130 __ movptr(dest->as_register_lo(), src_addr_LO); 1131 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1132 1133 } else if (dest->is_single_xmm()) { 1134 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1135 __ movflt(dest->as_xmm_float_reg(), src_addr); 1136 1137 } else if (dest->is_double_xmm()) { 1138 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1139 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1140 1141 #ifndef _LP64 1142 } else if (dest->is_single_fpu()) { 1143 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1144 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1145 __ fld_s(src_addr); 1146 1147 } else if (dest->is_double_fpu()) { 1148 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1149 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1150 __ fld_d(src_addr); 1151 #endif // _LP64 1152 1153 } else { 1154 ShouldNotReachHere(); 1155 } 1156 } 1157 1158 1159 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1160 if (src->is_single_stack()) { 1161 if (is_reference_type(type)) { 1162 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1163 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1164 } else { 1165 #ifndef _LP64 1166 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1167 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1168 #else 1169 //no pushl on 64bits 1170 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1171 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1172 #endif 1173 } 1174 1175 } else if (src->is_double_stack()) { 1176 #ifdef _LP64 1177 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1178 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1179 #else 1180 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1181 // push and pop the part at src + wordSize, adding wordSize for the previous push 1182 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1183 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1184 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1185 #endif // _LP64 1186 1187 } else { 1188 ShouldNotReachHere(); 1189 } 1190 } 1191 1192 1193 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 1194 assert(src->is_address(), "should not call otherwise"); 1195 assert(dest->is_register(), "should not call otherwise"); 1196 1197 LIR_Address* addr = src->as_address_ptr(); 1198 Address from_addr = as_Address(addr); 1199 1200 if (addr->base()->type() == T_OBJECT) { 1201 __ verify_oop(addr->base()->as_pointer_register()); 1202 } 1203 1204 switch (type) { 1205 case T_BOOLEAN: // fall through 1206 case T_BYTE: // fall through 1207 case T_CHAR: // fall through 1208 case T_SHORT: 1209 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1210 // on pre P6 processors we may get partial register stalls 1211 // so blow away the value of to_rinfo before loading a 1212 // partial word into it. Do it here so that it precedes 1213 // the potential patch point below. 1214 __ xorptr(dest->as_register(), dest->as_register()); 1215 } 1216 break; 1217 default: 1218 break; 1219 } 1220 1221 PatchingStub* patch = nullptr; 1222 if (patch_code != lir_patch_none) { 1223 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1224 assert(from_addr.disp() != 0, "must have"); 1225 } 1226 if (info != nullptr) { 1227 add_debug_info_for_null_check_here(info); 1228 } 1229 1230 switch (type) { 1231 case T_FLOAT: { 1232 if (dest->is_single_xmm()) { 1233 __ movflt(dest->as_xmm_float_reg(), from_addr); 1234 } else { 1235 #ifndef _LP64 1236 assert(dest->is_single_fpu(), "must be"); 1237 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1238 __ fld_s(from_addr); 1239 #else 1240 ShouldNotReachHere(); 1241 #endif // !LP64 1242 } 1243 break; 1244 } 1245 1246 case T_DOUBLE: { 1247 if (dest->is_double_xmm()) { 1248 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1249 } else { 1250 #ifndef _LP64 1251 assert(dest->is_double_fpu(), "must be"); 1252 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1253 __ fld_d(from_addr); 1254 #else 1255 ShouldNotReachHere(); 1256 #endif // !LP64 1257 } 1258 break; 1259 } 1260 1261 case T_OBJECT: // fall through 1262 case T_ARRAY: // fall through 1263 if (UseCompressedOops && !wide) { 1264 __ movl(dest->as_register(), from_addr); 1265 } else { 1266 __ movptr(dest->as_register(), from_addr); 1267 } 1268 break; 1269 1270 case T_ADDRESS: 1271 __ movptr(dest->as_register(), from_addr); 1272 break; 1273 case T_INT: 1274 __ movl(dest->as_register(), from_addr); 1275 break; 1276 1277 case T_LONG: { 1278 Register to_lo = dest->as_register_lo(); 1279 Register to_hi = dest->as_register_hi(); 1280 #ifdef _LP64 1281 __ movptr(to_lo, as_Address_lo(addr)); 1282 #else 1283 Register base = addr->base()->as_register(); 1284 Register index = noreg; 1285 if (addr->index()->is_register()) { 1286 index = addr->index()->as_register(); 1287 } 1288 if ((base == to_lo && index == to_hi) || 1289 (base == to_hi && index == to_lo)) { 1290 // addresses with 2 registers are only formed as a result of 1291 // array access so this code will never have to deal with 1292 // patches or null checks. 1293 assert(info == nullptr && patch == nullptr, "must be"); 1294 __ lea(to_hi, as_Address(addr)); 1295 __ movl(to_lo, Address(to_hi, 0)); 1296 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1297 } else if (base == to_lo || index == to_lo) { 1298 assert(base != to_hi, "can't be"); 1299 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1300 __ movl(to_hi, as_Address_hi(addr)); 1301 if (patch != nullptr) { 1302 patching_epilog(patch, lir_patch_high, base, info); 1303 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1304 patch_code = lir_patch_low; 1305 } 1306 __ movl(to_lo, as_Address_lo(addr)); 1307 } else { 1308 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1309 __ movl(to_lo, as_Address_lo(addr)); 1310 if (patch != nullptr) { 1311 patching_epilog(patch, lir_patch_low, base, info); 1312 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1313 patch_code = lir_patch_high; 1314 } 1315 __ movl(to_hi, as_Address_hi(addr)); 1316 } 1317 #endif // _LP64 1318 break; 1319 } 1320 1321 case T_BOOLEAN: // fall through 1322 case T_BYTE: { 1323 Register dest_reg = dest->as_register(); 1324 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1326 __ movsbl(dest_reg, from_addr); 1327 } else { 1328 __ movb(dest_reg, from_addr); 1329 __ shll(dest_reg, 24); 1330 __ sarl(dest_reg, 24); 1331 } 1332 break; 1333 } 1334 1335 case T_CHAR: { 1336 Register dest_reg = dest->as_register(); 1337 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1338 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1339 __ movzwl(dest_reg, from_addr); 1340 } else { 1341 __ movw(dest_reg, from_addr); 1342 } 1343 break; 1344 } 1345 1346 case T_SHORT: { 1347 Register dest_reg = dest->as_register(); 1348 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1349 __ movswl(dest_reg, from_addr); 1350 } else { 1351 __ movw(dest_reg, from_addr); 1352 __ shll(dest_reg, 16); 1353 __ sarl(dest_reg, 16); 1354 } 1355 break; 1356 } 1357 1358 default: 1359 ShouldNotReachHere(); 1360 } 1361 1362 if (patch != nullptr) { 1363 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1364 } 1365 1366 if (is_reference_type(type)) { 1367 #ifdef _LP64 1368 if (UseCompressedOops && !wide) { 1369 __ decode_heap_oop(dest->as_register()); 1370 } 1371 #endif 1372 1373 if (!(UseZGC && !ZGenerational)) { 1374 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1375 __ verify_oop(dest->as_register()); 1376 } 1377 } 1378 } 1379 1380 1381 NEEDS_CLEANUP; // This could be static? 1382 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1383 int elem_size = type2aelembytes(type); 1384 switch (elem_size) { 1385 case 1: return Address::times_1; 1386 case 2: return Address::times_2; 1387 case 4: return Address::times_4; 1388 case 8: return Address::times_8; 1389 } 1390 ShouldNotReachHere(); 1391 return Address::no_scale; 1392 } 1393 1394 1395 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1396 switch (op->code()) { 1397 case lir_idiv: 1398 case lir_irem: 1399 arithmetic_idiv(op->code(), 1400 op->in_opr1(), 1401 op->in_opr2(), 1402 op->in_opr3(), 1403 op->result_opr(), 1404 op->info()); 1405 break; 1406 case lir_fmad: 1407 __ fmad(op->result_opr()->as_xmm_double_reg(), 1408 op->in_opr1()->as_xmm_double_reg(), 1409 op->in_opr2()->as_xmm_double_reg(), 1410 op->in_opr3()->as_xmm_double_reg()); 1411 break; 1412 case lir_fmaf: 1413 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1414 op->in_opr1()->as_xmm_float_reg(), 1415 op->in_opr2()->as_xmm_float_reg(), 1416 op->in_opr3()->as_xmm_float_reg()); 1417 break; 1418 default: ShouldNotReachHere(); break; 1419 } 1420 } 1421 1422 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1423 #ifdef ASSERT 1424 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label"); 1425 if (op->block() != nullptr) _branch_target_blocks.append(op->block()); 1426 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock()); 1427 #endif 1428 1429 if (op->cond() == lir_cond_always) { 1430 if (op->info() != nullptr) add_debug_info_for_branch(op->info()); 1431 __ jmp (*(op->label())); 1432 } else { 1433 Assembler::Condition acond = Assembler::zero; 1434 if (op->code() == lir_cond_float_branch) { 1435 assert(op->ublock() != nullptr, "must have unordered successor"); 1436 __ jcc(Assembler::parity, *(op->ublock()->label())); 1437 switch(op->cond()) { 1438 case lir_cond_equal: acond = Assembler::equal; break; 1439 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1440 case lir_cond_less: acond = Assembler::below; break; 1441 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1442 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1443 case lir_cond_greater: acond = Assembler::above; break; 1444 default: ShouldNotReachHere(); 1445 } 1446 } else { 1447 switch (op->cond()) { 1448 case lir_cond_equal: acond = Assembler::equal; break; 1449 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1450 case lir_cond_less: acond = Assembler::less; break; 1451 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1452 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1453 case lir_cond_greater: acond = Assembler::greater; break; 1454 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1455 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1456 default: ShouldNotReachHere(); 1457 } 1458 } 1459 __ jcc(acond,*(op->label())); 1460 } 1461 } 1462 1463 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1464 LIR_Opr src = op->in_opr(); 1465 LIR_Opr dest = op->result_opr(); 1466 1467 switch (op->bytecode()) { 1468 case Bytecodes::_i2l: 1469 #ifdef _LP64 1470 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1471 #else 1472 move_regs(src->as_register(), dest->as_register_lo()); 1473 move_regs(src->as_register(), dest->as_register_hi()); 1474 __ sarl(dest->as_register_hi(), 31); 1475 #endif // LP64 1476 break; 1477 1478 case Bytecodes::_l2i: 1479 #ifdef _LP64 1480 __ movl(dest->as_register(), src->as_register_lo()); 1481 #else 1482 move_regs(src->as_register_lo(), dest->as_register()); 1483 #endif 1484 break; 1485 1486 case Bytecodes::_i2b: 1487 move_regs(src->as_register(), dest->as_register()); 1488 __ sign_extend_byte(dest->as_register()); 1489 break; 1490 1491 case Bytecodes::_i2c: 1492 move_regs(src->as_register(), dest->as_register()); 1493 __ andl(dest->as_register(), 0xFFFF); 1494 break; 1495 1496 case Bytecodes::_i2s: 1497 move_regs(src->as_register(), dest->as_register()); 1498 __ sign_extend_short(dest->as_register()); 1499 break; 1500 1501 1502 #ifdef _LP64 1503 case Bytecodes::_f2d: 1504 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1505 break; 1506 1507 case Bytecodes::_d2f: 1508 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1509 break; 1510 1511 case Bytecodes::_i2f: 1512 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1513 break; 1514 1515 case Bytecodes::_i2d: 1516 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1517 break; 1518 1519 case Bytecodes::_l2f: 1520 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo()); 1521 break; 1522 1523 case Bytecodes::_l2d: 1524 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo()); 1525 break; 1526 1527 case Bytecodes::_f2i: 1528 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg()); 1529 break; 1530 1531 case Bytecodes::_d2i: 1532 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg()); 1533 break; 1534 1535 case Bytecodes::_f2l: 1536 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg()); 1537 break; 1538 1539 case Bytecodes::_d2l: 1540 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg()); 1541 break; 1542 #else 1543 case Bytecodes::_f2d: 1544 case Bytecodes::_d2f: 1545 if (dest->is_single_xmm()) { 1546 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1547 } else if (dest->is_double_xmm()) { 1548 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1549 } else { 1550 assert(src->fpu() == dest->fpu(), "register must be equal"); 1551 // do nothing (float result is rounded later through spilling) 1552 } 1553 break; 1554 1555 case Bytecodes::_i2f: 1556 case Bytecodes::_i2d: 1557 if (dest->is_single_xmm()) { 1558 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1559 } else if (dest->is_double_xmm()) { 1560 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1561 } else { 1562 assert(dest->fpu() == 0, "result must be on TOS"); 1563 __ movl(Address(rsp, 0), src->as_register()); 1564 __ fild_s(Address(rsp, 0)); 1565 } 1566 break; 1567 1568 case Bytecodes::_l2f: 1569 case Bytecodes::_l2d: 1570 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1571 assert(dest->fpu() == 0, "result must be on TOS"); 1572 __ movptr(Address(rsp, 0), src->as_register_lo()); 1573 __ movl(Address(rsp, BytesPerWord), src->as_register_hi()); 1574 __ fild_d(Address(rsp, 0)); 1575 // float result is rounded later through spilling 1576 break; 1577 1578 case Bytecodes::_f2i: 1579 case Bytecodes::_d2i: 1580 if (src->is_single_xmm()) { 1581 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1582 } else if (src->is_double_xmm()) { 1583 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1584 } else { 1585 assert(src->fpu() == 0, "input must be on TOS"); 1586 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc())); 1587 __ fist_s(Address(rsp, 0)); 1588 __ movl(dest->as_register(), Address(rsp, 0)); 1589 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std())); 1590 } 1591 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1592 assert(op->stub() != nullptr, "stub required"); 1593 __ cmpl(dest->as_register(), 0x80000000); 1594 __ jcc(Assembler::equal, *op->stub()->entry()); 1595 __ bind(*op->stub()->continuation()); 1596 break; 1597 1598 case Bytecodes::_f2l: 1599 case Bytecodes::_d2l: 1600 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1601 assert(src->fpu() == 0, "input must be on TOS"); 1602 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1603 1604 // instruction sequence too long to inline it here 1605 { 1606 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1607 } 1608 break; 1609 #endif // _LP64 1610 1611 default: ShouldNotReachHere(); 1612 } 1613 } 1614 1615 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1616 if (op->init_check()) { 1617 add_debug_info_for_null_check_here(op->stub()->info()); 1618 __ cmpb(Address(op->klass()->as_register(), 1619 InstanceKlass::init_state_offset()), 1620 InstanceKlass::fully_initialized); 1621 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1622 } 1623 __ allocate_object(op->obj()->as_register(), 1624 op->tmp1()->as_register(), 1625 op->tmp2()->as_register(), 1626 op->header_size(), 1627 op->object_size(), 1628 op->klass()->as_register(), 1629 *op->stub()->entry()); 1630 __ bind(*op->stub()->continuation()); 1631 } 1632 1633 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1634 Register len = op->len()->as_register(); 1635 LP64_ONLY( __ movslq(len, len); ) 1636 1637 if (UseSlowPath || op->is_null_free() || 1638 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1639 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1640 __ jmp(*op->stub()->entry()); 1641 } else { 1642 Register tmp1 = op->tmp1()->as_register(); 1643 Register tmp2 = op->tmp2()->as_register(); 1644 Register tmp3 = op->tmp3()->as_register(); 1645 if (len == tmp1) { 1646 tmp1 = tmp3; 1647 } else if (len == tmp2) { 1648 tmp2 = tmp3; 1649 } else if (len == tmp3) { 1650 // everything is ok 1651 } else { 1652 __ mov(tmp3, len); 1653 } 1654 __ allocate_array(op->obj()->as_register(), 1655 len, 1656 tmp1, 1657 tmp2, 1658 arrayOopDesc::base_offset_in_bytes(op->type()), 1659 array_element_size(op->type()), 1660 op->klass()->as_register(), 1661 *op->stub()->entry(), 1662 op->zero_array()); 1663 } 1664 __ bind(*op->stub()->continuation()); 1665 } 1666 1667 void LIR_Assembler::type_profile_helper(Register mdo, 1668 ciMethodData *md, ciProfileData *data, 1669 Register recv, Label* update_done) { 1670 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1671 Label next_test; 1672 // See if the receiver is receiver[n]. 1673 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1674 __ jccb(Assembler::notEqual, next_test); 1675 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1676 __ addptr(data_addr, DataLayout::counter_increment); 1677 __ jmp(*update_done); 1678 __ bind(next_test); 1679 } 1680 1681 // Didn't find receiver; find next empty slot and fill it in 1682 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1683 Label next_test; 1684 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1685 __ cmpptr(recv_addr, NULL_WORD); 1686 __ jccb(Assembler::notEqual, next_test); 1687 __ movptr(recv_addr, recv); 1688 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1689 __ jmp(*update_done); 1690 __ bind(next_test); 1691 } 1692 } 1693 1694 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1695 // we always need a stub for the failure case. 1696 CodeStub* stub = op->stub(); 1697 Register obj = op->object()->as_register(); 1698 Register k_RInfo = op->tmp1()->as_register(); 1699 Register klass_RInfo = op->tmp2()->as_register(); 1700 Register dst = op->result_opr()->as_register(); 1701 ciKlass* k = op->klass(); 1702 Register Rtmp1 = noreg; 1703 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 1704 1705 // check if it needs to be profiled 1706 ciMethodData* md = nullptr; 1707 ciProfileData* data = nullptr; 1708 1709 if (op->should_profile()) { 1710 ciMethod* method = op->profiled_method(); 1711 assert(method != nullptr, "Should have method"); 1712 int bci = op->profiled_bci(); 1713 md = method->method_data_or_null(); 1714 assert(md != nullptr, "Sanity"); 1715 data = md->bci_to_data(bci); 1716 assert(data != nullptr, "need data for type check"); 1717 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1718 } 1719 Label* success_target = success; 1720 Label* failure_target = failure; 1721 1722 if (obj == k_RInfo) { 1723 k_RInfo = dst; 1724 } else if (obj == klass_RInfo) { 1725 klass_RInfo = dst; 1726 } 1727 if (k->is_loaded() && !UseCompressedClassPointers) { 1728 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1729 } else { 1730 Rtmp1 = op->tmp3()->as_register(); 1731 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1732 } 1733 1734 assert_different_registers(obj, k_RInfo, klass_RInfo); 1735 1736 if (op->need_null_check()) { 1737 __ testptr(obj, obj); 1738 if (op->should_profile()) { 1739 Label not_null; 1740 Register mdo = klass_RInfo; 1741 __ mov_metadata(mdo, md->constant_encoding()); 1742 __ jccb(Assembler::notEqual, not_null); 1743 // Object is null; update MDO and exit 1744 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1745 int header_bits = BitData::null_seen_byte_constant(); 1746 __ orb(data_addr, header_bits); 1747 __ jmp(*obj_is_null); 1748 __ bind(not_null); 1749 1750 Label update_done; 1751 Register recv = k_RInfo; 1752 __ load_klass(recv, obj, tmp_load_klass); 1753 type_profile_helper(mdo, md, data, recv, &update_done); 1754 1755 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1756 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment); 1757 1758 __ bind(update_done); 1759 } else { 1760 __ jcc(Assembler::equal, *obj_is_null); 1761 } 1762 } 1763 1764 if (!k->is_loaded()) { 1765 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1766 } else { 1767 #ifdef _LP64 1768 __ mov_metadata(k_RInfo, k->constant_encoding()); 1769 #endif // _LP64 1770 } 1771 __ verify_oop(obj); 1772 1773 if (op->fast_check()) { 1774 // get object class 1775 // not a safepoint as obj null check happens earlier 1776 #ifdef _LP64 1777 if (UseCompressedClassPointers) { 1778 __ load_klass(Rtmp1, obj, tmp_load_klass); 1779 __ cmpptr(k_RInfo, Rtmp1); 1780 } else { 1781 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1782 } 1783 #else 1784 if (k->is_loaded()) { 1785 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1786 } else { 1787 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1788 } 1789 #endif 1790 __ jcc(Assembler::notEqual, *failure_target); 1791 // successful cast, fall through to profile or jump 1792 } else { 1793 // get object class 1794 // not a safepoint as obj null check happens earlier 1795 __ load_klass(klass_RInfo, obj, tmp_load_klass); 1796 if (k->is_loaded()) { 1797 // See if we get an immediate positive hit 1798 #ifdef _LP64 1799 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1800 #else 1801 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1802 #endif // _LP64 1803 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1804 __ jcc(Assembler::notEqual, *failure_target); 1805 // successful cast, fall through to profile or jump 1806 } else { 1807 // See if we get an immediate positive hit 1808 __ jcc(Assembler::equal, *success_target); 1809 // check for self 1810 #ifdef _LP64 1811 __ cmpptr(klass_RInfo, k_RInfo); 1812 #else 1813 __ cmpklass(klass_RInfo, k->constant_encoding()); 1814 #endif // _LP64 1815 __ jcc(Assembler::equal, *success_target); 1816 1817 __ push(klass_RInfo); 1818 #ifdef _LP64 1819 __ push(k_RInfo); 1820 #else 1821 __ pushklass(k->constant_encoding(), noreg); 1822 #endif // _LP64 1823 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1824 __ pop(klass_RInfo); 1825 __ pop(klass_RInfo); 1826 // result is a boolean 1827 __ testl(klass_RInfo, klass_RInfo); 1828 __ jcc(Assembler::equal, *failure_target); 1829 // successful cast, fall through to profile or jump 1830 } 1831 } else { 1832 // perform the fast part of the checking logic 1833 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1834 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1835 __ push(klass_RInfo); 1836 __ push(k_RInfo); 1837 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1838 __ pop(klass_RInfo); 1839 __ pop(k_RInfo); 1840 // result is a boolean 1841 __ testl(k_RInfo, k_RInfo); 1842 __ jcc(Assembler::equal, *failure_target); 1843 // successful cast, fall through to profile or jump 1844 } 1845 } 1846 __ jmp(*success); 1847 } 1848 1849 1850 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1851 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 1852 LIR_Code code = op->code(); 1853 if (code == lir_store_check) { 1854 Register value = op->object()->as_register(); 1855 Register array = op->array()->as_register(); 1856 Register k_RInfo = op->tmp1()->as_register(); 1857 Register klass_RInfo = op->tmp2()->as_register(); 1858 Register Rtmp1 = op->tmp3()->as_register(); 1859 1860 CodeStub* stub = op->stub(); 1861 1862 // check if it needs to be profiled 1863 ciMethodData* md = nullptr; 1864 ciProfileData* data = nullptr; 1865 1866 if (op->should_profile()) { 1867 ciMethod* method = op->profiled_method(); 1868 assert(method != nullptr, "Should have method"); 1869 int bci = op->profiled_bci(); 1870 md = method->method_data_or_null(); 1871 assert(md != nullptr, "Sanity"); 1872 data = md->bci_to_data(bci); 1873 assert(data != nullptr, "need data for type check"); 1874 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1875 } 1876 Label done; 1877 Label* success_target = &done; 1878 Label* failure_target = stub->entry(); 1879 1880 __ testptr(value, value); 1881 if (op->should_profile()) { 1882 Label not_null; 1883 Register mdo = klass_RInfo; 1884 __ mov_metadata(mdo, md->constant_encoding()); 1885 __ jccb(Assembler::notEqual, not_null); 1886 // Object is null; update MDO and exit 1887 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1888 int header_bits = BitData::null_seen_byte_constant(); 1889 __ orb(data_addr, header_bits); 1890 __ jmp(done); 1891 __ bind(not_null); 1892 1893 Label update_done; 1894 Register recv = k_RInfo; 1895 __ load_klass(recv, value, tmp_load_klass); 1896 type_profile_helper(mdo, md, data, recv, &update_done); 1897 1898 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1899 __ addptr(counter_addr, DataLayout::counter_increment); 1900 __ bind(update_done); 1901 } else { 1902 __ jcc(Assembler::equal, done); 1903 } 1904 1905 add_debug_info_for_null_check_here(op->info_for_exception()); 1906 __ load_klass(k_RInfo, array, tmp_load_klass); 1907 __ load_klass(klass_RInfo, value, tmp_load_klass); 1908 1909 // get instance klass (it's already uncompressed) 1910 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1911 // perform the fast part of the checking logic 1912 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1913 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1914 __ push(klass_RInfo); 1915 __ push(k_RInfo); 1916 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1917 __ pop(klass_RInfo); 1918 __ pop(k_RInfo); 1919 // result is a boolean 1920 __ testl(k_RInfo, k_RInfo); 1921 __ jcc(Assembler::equal, *failure_target); 1922 // fall through to the success case 1923 1924 __ bind(done); 1925 } else 1926 if (code == lir_checkcast) { 1927 Register obj = op->object()->as_register(); 1928 Register dst = op->result_opr()->as_register(); 1929 Label success; 1930 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1931 __ bind(success); 1932 if (dst != obj) { 1933 __ mov(dst, obj); 1934 } 1935 } else 1936 if (code == lir_instanceof) { 1937 Register obj = op->object()->as_register(); 1938 Register dst = op->result_opr()->as_register(); 1939 Label success, failure, done; 1940 emit_typecheck_helper(op, &success, &failure, &failure); 1941 __ bind(failure); 1942 __ xorptr(dst, dst); 1943 __ jmpb(done); 1944 __ bind(success); 1945 __ movptr(dst, 1); 1946 __ bind(done); 1947 } else { 1948 ShouldNotReachHere(); 1949 } 1950 1951 } 1952 1953 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) { 1954 // We are loading/storing from/to an array that *may* be a flat array (the 1955 // declared type is Object[], abstract[], interface[] or VT.ref[]). 1956 // If this array is a flat array, take the slow path. 1957 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry()); 1958 if (!op->value()->is_illegal()) { 1959 // The array is not a flat array, but it might be null-free. If we are storing 1960 // a null into a null-free array, take the slow path (which will throw NPE). 1961 Label skip; 1962 __ cmpptr(op->value()->as_register(), NULL_WORD); 1963 __ jcc(Assembler::notEqual, skip); 1964 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry()); 1965 __ bind(skip); 1966 } 1967 } 1968 1969 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) { 1970 // We are storing into an array that *may* be null-free (the declared type is 1971 // Object[], abstract[], interface[] or VT.ref[]). 1972 Label test_mark_word; 1973 Register tmp = op->tmp()->as_register(); 1974 __ movptr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes())); 1975 __ testl(tmp, markWord::unlocked_value); 1976 __ jccb(Assembler::notZero, test_mark_word); 1977 __ load_prototype_header(tmp, op->array()->as_register(), rscratch1); 1978 __ bind(test_mark_word); 1979 __ testl(tmp, markWord::null_free_array_bit_in_place); 1980 } 1981 1982 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) { 1983 Label L_oops_equal; 1984 Label L_oops_not_equal; 1985 Label L_end; 1986 1987 Register left = op->left()->as_register(); 1988 Register right = op->right()->as_register(); 1989 1990 __ cmpptr(left, right); 1991 __ jcc(Assembler::equal, L_oops_equal); 1992 1993 // (1) Null check -- if one of the operands is null, the other must not be null (because 1994 // the two references are not equal), so they are not substitutable, 1995 // FIXME: do null check only if the operand is nullable 1996 __ testptr(left, right); 1997 __ jcc(Assembler::zero, L_oops_not_equal); 1998 1999 ciKlass* left_klass = op->left_klass(); 2000 ciKlass* right_klass = op->right_klass(); 2001 2002 // (2) Inline type check -- if either of the operands is not a inline type, 2003 // they are not substitutable. We do this only if we are not sure that the 2004 // operands are inline type 2005 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node. 2006 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) { 2007 Register tmp1 = op->tmp1()->as_register(); 2008 __ movptr(tmp1, (intptr_t)markWord::inline_type_pattern); 2009 __ andptr(tmp1, Address(left, oopDesc::mark_offset_in_bytes())); 2010 __ andptr(tmp1, Address(right, oopDesc::mark_offset_in_bytes())); 2011 __ cmpptr(tmp1, (intptr_t)markWord::inline_type_pattern); 2012 __ jcc(Assembler::notEqual, L_oops_not_equal); 2013 } 2014 2015 // (3) Same klass check: if the operands are of different klasses, they are not substitutable. 2016 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) { 2017 // No need to load klass -- the operands are statically known to be the same inline klass. 2018 __ jmp(*op->stub()->entry()); 2019 } else { 2020 Register left_klass_op = op->left_klass_op()->as_register(); 2021 Register right_klass_op = op->right_klass_op()->as_register(); 2022 2023 if (UseCompressedClassPointers) { 2024 __ movl(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes())); 2025 __ movl(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes())); 2026 __ cmpl(left_klass_op, right_klass_op); 2027 } else { 2028 __ movptr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes())); 2029 __ movptr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes())); 2030 __ cmpptr(left_klass_op, right_klass_op); 2031 } 2032 2033 __ jcc(Assembler::equal, *op->stub()->entry()); // same klass -> do slow check 2034 // fall through to L_oops_not_equal 2035 } 2036 2037 __ bind(L_oops_not_equal); 2038 move(op->not_equal_result(), op->result_opr()); 2039 __ jmp(L_end); 2040 2041 __ bind(L_oops_equal); 2042 move(op->equal_result(), op->result_opr()); 2043 __ jmp(L_end); 2044 2045 // We've returned from the stub. RAX contains 0x0 IFF the two 2046 // operands are not substitutable. (Don't compare against 0x1 in case the 2047 // C compiler is naughty) 2048 __ bind(*op->stub()->continuation()); 2049 __ cmpl(rax, 0); 2050 __ jcc(Assembler::equal, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal 2051 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal 2052 // fall-through 2053 __ bind(L_end); 2054 } 2055 2056 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2057 if (LP64_ONLY(false &&) op->code() == lir_cas_long) { 2058 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 2059 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 2060 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 2061 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 2062 Register addr = op->addr()->as_register(); 2063 __ lock(); 2064 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 2065 2066 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 2067 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 2068 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 2069 Register newval = op->new_value()->as_register(); 2070 Register cmpval = op->cmp_value()->as_register(); 2071 assert(cmpval == rax, "wrong register"); 2072 assert(newval != noreg, "new val must be register"); 2073 assert(cmpval != newval, "cmp and new values must be in different registers"); 2074 assert(cmpval != addr, "cmp and addr must be in different registers"); 2075 assert(newval != addr, "new value and addr must be in different registers"); 2076 2077 if ( op->code() == lir_cas_obj) { 2078 #ifdef _LP64 2079 if (UseCompressedOops) { 2080 __ encode_heap_oop(cmpval); 2081 __ mov(rscratch1, newval); 2082 __ encode_heap_oop(rscratch1); 2083 __ lock(); 2084 // cmpval (rax) is implicitly used by this instruction 2085 __ cmpxchgl(rscratch1, Address(addr, 0)); 2086 } else 2087 #endif 2088 { 2089 __ lock(); 2090 __ cmpxchgptr(newval, Address(addr, 0)); 2091 } 2092 } else { 2093 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 2094 __ lock(); 2095 __ cmpxchgl(newval, Address(addr, 0)); 2096 } 2097 #ifdef _LP64 2098 } else if (op->code() == lir_cas_long) { 2099 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 2100 Register newval = op->new_value()->as_register_lo(); 2101 Register cmpval = op->cmp_value()->as_register_lo(); 2102 assert(cmpval == rax, "wrong register"); 2103 assert(newval != noreg, "new val must be register"); 2104 assert(cmpval != newval, "cmp and new values must be in different registers"); 2105 assert(cmpval != addr, "cmp and addr must be in different registers"); 2106 assert(newval != addr, "new value and addr must be in different registers"); 2107 __ lock(); 2108 __ cmpxchgq(newval, Address(addr, 0)); 2109 #endif // _LP64 2110 } else { 2111 Unimplemented(); 2112 } 2113 } 2114 2115 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) { 2116 assert(dst->is_cpu_register(), "must be"); 2117 assert(dst->type() == src->type(), "must be"); 2118 2119 if (src->is_cpu_register()) { 2120 reg2reg(src, dst); 2121 } else if (src->is_stack()) { 2122 stack2reg(src, dst, dst->type()); 2123 } else if (src->is_constant()) { 2124 const2reg(src, dst, lir_patch_none, nullptr); 2125 } else { 2126 ShouldNotReachHere(); 2127 } 2128 } 2129 2130 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 2131 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 2132 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86"); 2133 2134 Assembler::Condition acond, ncond; 2135 switch (condition) { 2136 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 2137 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 2138 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 2139 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 2140 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 2141 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 2142 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 2143 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 2144 default: acond = Assembler::equal; ncond = Assembler::notEqual; 2145 ShouldNotReachHere(); 2146 } 2147 2148 if (opr1->is_cpu_register()) { 2149 reg2reg(opr1, result); 2150 } else if (opr1->is_stack()) { 2151 stack2reg(opr1, result, result->type()); 2152 } else if (opr1->is_constant()) { 2153 const2reg(opr1, result, lir_patch_none, nullptr); 2154 } else { 2155 ShouldNotReachHere(); 2156 } 2157 2158 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2159 // optimized version that does not require a branch 2160 if (opr2->is_single_cpu()) { 2161 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2162 __ cmov(ncond, result->as_register(), opr2->as_register()); 2163 } else if (opr2->is_double_cpu()) { 2164 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2165 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2166 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2167 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2168 } else if (opr2->is_single_stack()) { 2169 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2170 } else if (opr2->is_double_stack()) { 2171 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2172 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2173 } else { 2174 ShouldNotReachHere(); 2175 } 2176 2177 } else { 2178 Label skip; 2179 __ jccb(acond, skip); 2180 if (opr2->is_cpu_register()) { 2181 reg2reg(opr2, result); 2182 } else if (opr2->is_stack()) { 2183 stack2reg(opr2, result, result->type()); 2184 } else if (opr2->is_constant()) { 2185 const2reg(opr2, result, lir_patch_none, nullptr); 2186 } else { 2187 ShouldNotReachHere(); 2188 } 2189 __ bind(skip); 2190 } 2191 } 2192 2193 2194 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2195 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2196 2197 if (left->is_single_cpu()) { 2198 assert(left == dest, "left and dest must be equal"); 2199 Register lreg = left->as_register(); 2200 2201 if (right->is_single_cpu()) { 2202 // cpu register - cpu register 2203 Register rreg = right->as_register(); 2204 switch (code) { 2205 case lir_add: __ addl (lreg, rreg); break; 2206 case lir_sub: __ subl (lreg, rreg); break; 2207 case lir_mul: __ imull(lreg, rreg); break; 2208 default: ShouldNotReachHere(); 2209 } 2210 2211 } else if (right->is_stack()) { 2212 // cpu register - stack 2213 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2214 switch (code) { 2215 case lir_add: __ addl(lreg, raddr); break; 2216 case lir_sub: __ subl(lreg, raddr); break; 2217 default: ShouldNotReachHere(); 2218 } 2219 2220 } else if (right->is_constant()) { 2221 // cpu register - constant 2222 jint c = right->as_constant_ptr()->as_jint(); 2223 switch (code) { 2224 case lir_add: { 2225 __ incrementl(lreg, c); 2226 break; 2227 } 2228 case lir_sub: { 2229 __ decrementl(lreg, c); 2230 break; 2231 } 2232 default: ShouldNotReachHere(); 2233 } 2234 2235 } else { 2236 ShouldNotReachHere(); 2237 } 2238 2239 } else if (left->is_double_cpu()) { 2240 assert(left == dest, "left and dest must be equal"); 2241 Register lreg_lo = left->as_register_lo(); 2242 Register lreg_hi = left->as_register_hi(); 2243 2244 if (right->is_double_cpu()) { 2245 // cpu register - cpu register 2246 Register rreg_lo = right->as_register_lo(); 2247 Register rreg_hi = right->as_register_hi(); 2248 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2249 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2250 switch (code) { 2251 case lir_add: 2252 __ addptr(lreg_lo, rreg_lo); 2253 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2254 break; 2255 case lir_sub: 2256 __ subptr(lreg_lo, rreg_lo); 2257 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2258 break; 2259 case lir_mul: 2260 #ifdef _LP64 2261 __ imulq(lreg_lo, rreg_lo); 2262 #else 2263 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2264 __ imull(lreg_hi, rreg_lo); 2265 __ imull(rreg_hi, lreg_lo); 2266 __ addl (rreg_hi, lreg_hi); 2267 __ mull (rreg_lo); 2268 __ addl (lreg_hi, rreg_hi); 2269 #endif // _LP64 2270 break; 2271 default: 2272 ShouldNotReachHere(); 2273 } 2274 2275 } else if (right->is_constant()) { 2276 // cpu register - constant 2277 #ifdef _LP64 2278 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2279 __ movptr(r10, (intptr_t) c); 2280 switch (code) { 2281 case lir_add: 2282 __ addptr(lreg_lo, r10); 2283 break; 2284 case lir_sub: 2285 __ subptr(lreg_lo, r10); 2286 break; 2287 default: 2288 ShouldNotReachHere(); 2289 } 2290 #else 2291 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2292 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2293 switch (code) { 2294 case lir_add: 2295 __ addptr(lreg_lo, c_lo); 2296 __ adcl(lreg_hi, c_hi); 2297 break; 2298 case lir_sub: 2299 __ subptr(lreg_lo, c_lo); 2300 __ sbbl(lreg_hi, c_hi); 2301 break; 2302 default: 2303 ShouldNotReachHere(); 2304 } 2305 #endif // _LP64 2306 2307 } else { 2308 ShouldNotReachHere(); 2309 } 2310 2311 } else if (left->is_single_xmm()) { 2312 assert(left == dest, "left and dest must be equal"); 2313 XMMRegister lreg = left->as_xmm_float_reg(); 2314 2315 if (right->is_single_xmm()) { 2316 XMMRegister rreg = right->as_xmm_float_reg(); 2317 switch (code) { 2318 case lir_add: __ addss(lreg, rreg); break; 2319 case lir_sub: __ subss(lreg, rreg); break; 2320 case lir_mul: __ mulss(lreg, rreg); break; 2321 case lir_div: __ divss(lreg, rreg); break; 2322 default: ShouldNotReachHere(); 2323 } 2324 } else { 2325 Address raddr; 2326 if (right->is_single_stack()) { 2327 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2328 } else if (right->is_constant()) { 2329 // hack for now 2330 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2331 } else { 2332 ShouldNotReachHere(); 2333 } 2334 switch (code) { 2335 case lir_add: __ addss(lreg, raddr); break; 2336 case lir_sub: __ subss(lreg, raddr); break; 2337 case lir_mul: __ mulss(lreg, raddr); break; 2338 case lir_div: __ divss(lreg, raddr); break; 2339 default: ShouldNotReachHere(); 2340 } 2341 } 2342 2343 } else if (left->is_double_xmm()) { 2344 assert(left == dest, "left and dest must be equal"); 2345 2346 XMMRegister lreg = left->as_xmm_double_reg(); 2347 if (right->is_double_xmm()) { 2348 XMMRegister rreg = right->as_xmm_double_reg(); 2349 switch (code) { 2350 case lir_add: __ addsd(lreg, rreg); break; 2351 case lir_sub: __ subsd(lreg, rreg); break; 2352 case lir_mul: __ mulsd(lreg, rreg); break; 2353 case lir_div: __ divsd(lreg, rreg); break; 2354 default: ShouldNotReachHere(); 2355 } 2356 } else { 2357 Address raddr; 2358 if (right->is_double_stack()) { 2359 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2360 } else if (right->is_constant()) { 2361 // hack for now 2362 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2363 } else { 2364 ShouldNotReachHere(); 2365 } 2366 switch (code) { 2367 case lir_add: __ addsd(lreg, raddr); break; 2368 case lir_sub: __ subsd(lreg, raddr); break; 2369 case lir_mul: __ mulsd(lreg, raddr); break; 2370 case lir_div: __ divsd(lreg, raddr); break; 2371 default: ShouldNotReachHere(); 2372 } 2373 } 2374 2375 #ifndef _LP64 2376 } else if (left->is_single_fpu()) { 2377 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2378 2379 if (right->is_single_fpu()) { 2380 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2381 2382 } else { 2383 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2384 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2385 2386 Address raddr; 2387 if (right->is_single_stack()) { 2388 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2389 } else if (right->is_constant()) { 2390 address const_addr = float_constant(right->as_jfloat()); 2391 assert(const_addr != nullptr, "incorrect float/double constant maintenance"); 2392 // hack for now 2393 raddr = __ as_Address(InternalAddress(const_addr)); 2394 } else { 2395 ShouldNotReachHere(); 2396 } 2397 2398 switch (code) { 2399 case lir_add: __ fadd_s(raddr); break; 2400 case lir_sub: __ fsub_s(raddr); break; 2401 case lir_mul: __ fmul_s(raddr); break; 2402 case lir_div: __ fdiv_s(raddr); break; 2403 default: ShouldNotReachHere(); 2404 } 2405 } 2406 2407 } else if (left->is_double_fpu()) { 2408 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2409 2410 if (code == lir_mul || code == lir_div) { 2411 // Double values require special handling for strictfp mul/div on x86 2412 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1())); 2413 __ fmulp(left->fpu_regnrLo() + 1); 2414 } 2415 2416 if (right->is_double_fpu()) { 2417 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2418 2419 } else { 2420 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2421 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2422 2423 Address raddr; 2424 if (right->is_double_stack()) { 2425 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2426 } else if (right->is_constant()) { 2427 // hack for now 2428 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2429 } else { 2430 ShouldNotReachHere(); 2431 } 2432 2433 switch (code) { 2434 case lir_add: __ fadd_d(raddr); break; 2435 case lir_sub: __ fsub_d(raddr); break; 2436 case lir_mul: __ fmul_d(raddr); break; 2437 case lir_div: __ fdiv_d(raddr); break; 2438 default: ShouldNotReachHere(); 2439 } 2440 } 2441 2442 if (code == lir_mul || code == lir_div) { 2443 // Double values require special handling for strictfp mul/div on x86 2444 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2())); 2445 __ fmulp(dest->fpu_regnrLo() + 1); 2446 } 2447 #endif // !_LP64 2448 2449 } else if (left->is_single_stack() || left->is_address()) { 2450 assert(left == dest, "left and dest must be equal"); 2451 2452 Address laddr; 2453 if (left->is_single_stack()) { 2454 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2455 } else if (left->is_address()) { 2456 laddr = as_Address(left->as_address_ptr()); 2457 } else { 2458 ShouldNotReachHere(); 2459 } 2460 2461 if (right->is_single_cpu()) { 2462 Register rreg = right->as_register(); 2463 switch (code) { 2464 case lir_add: __ addl(laddr, rreg); break; 2465 case lir_sub: __ subl(laddr, rreg); break; 2466 default: ShouldNotReachHere(); 2467 } 2468 } else if (right->is_constant()) { 2469 jint c = right->as_constant_ptr()->as_jint(); 2470 switch (code) { 2471 case lir_add: { 2472 __ incrementl(laddr, c); 2473 break; 2474 } 2475 case lir_sub: { 2476 __ decrementl(laddr, c); 2477 break; 2478 } 2479 default: ShouldNotReachHere(); 2480 } 2481 } else { 2482 ShouldNotReachHere(); 2483 } 2484 2485 } else { 2486 ShouldNotReachHere(); 2487 } 2488 } 2489 2490 #ifndef _LP64 2491 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2492 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2493 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2494 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2495 2496 bool left_is_tos = (left_index == 0); 2497 bool dest_is_tos = (dest_index == 0); 2498 int non_tos_index = (left_is_tos ? right_index : left_index); 2499 2500 switch (code) { 2501 case lir_add: 2502 if (pop_fpu_stack) __ faddp(non_tos_index); 2503 else if (dest_is_tos) __ fadd (non_tos_index); 2504 else __ fadda(non_tos_index); 2505 break; 2506 2507 case lir_sub: 2508 if (left_is_tos) { 2509 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2510 else if (dest_is_tos) __ fsub (non_tos_index); 2511 else __ fsubra(non_tos_index); 2512 } else { 2513 if (pop_fpu_stack) __ fsubp (non_tos_index); 2514 else if (dest_is_tos) __ fsubr (non_tos_index); 2515 else __ fsuba (non_tos_index); 2516 } 2517 break; 2518 2519 case lir_mul: 2520 if (pop_fpu_stack) __ fmulp(non_tos_index); 2521 else if (dest_is_tos) __ fmul (non_tos_index); 2522 else __ fmula(non_tos_index); 2523 break; 2524 2525 case lir_div: 2526 if (left_is_tos) { 2527 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2528 else if (dest_is_tos) __ fdiv (non_tos_index); 2529 else __ fdivra(non_tos_index); 2530 } else { 2531 if (pop_fpu_stack) __ fdivp (non_tos_index); 2532 else if (dest_is_tos) __ fdivr (non_tos_index); 2533 else __ fdiva (non_tos_index); 2534 } 2535 break; 2536 2537 case lir_rem: 2538 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2539 __ fremr(noreg); 2540 break; 2541 2542 default: 2543 ShouldNotReachHere(); 2544 } 2545 } 2546 #endif // _LP64 2547 2548 2549 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 2550 if (value->is_double_xmm()) { 2551 switch(code) { 2552 case lir_abs : 2553 { 2554 #ifdef _LP64 2555 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 2556 assert(tmp->is_valid(), "need temporary"); 2557 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2); 2558 } else 2559 #endif 2560 { 2561 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2562 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2563 } 2564 assert(!tmp->is_valid(), "do not need temporary"); 2565 __ andpd(dest->as_xmm_double_reg(), 2566 ExternalAddress((address)double_signmask_pool), 2567 rscratch1); 2568 } 2569 } 2570 break; 2571 2572 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2573 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2574 default : ShouldNotReachHere(); 2575 } 2576 2577 #ifndef _LP64 2578 } else if (value->is_double_fpu()) { 2579 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2580 switch(code) { 2581 case lir_abs : __ fabs() ; break; 2582 case lir_sqrt : __ fsqrt(); break; 2583 default : ShouldNotReachHere(); 2584 } 2585 #endif // !_LP64 2586 } else if (code == lir_f2hf) { 2587 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 2588 } else if (code == lir_hf2f) { 2589 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register()); 2590 } else { 2591 Unimplemented(); 2592 } 2593 } 2594 2595 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2596 // assert(left->destroys_register(), "check"); 2597 if (left->is_single_cpu()) { 2598 Register reg = left->as_register(); 2599 if (right->is_constant()) { 2600 int val = right->as_constant_ptr()->as_jint(); 2601 switch (code) { 2602 case lir_logic_and: __ andl (reg, val); break; 2603 case lir_logic_or: __ orl (reg, val); break; 2604 case lir_logic_xor: __ xorl (reg, val); break; 2605 default: ShouldNotReachHere(); 2606 } 2607 } else if (right->is_stack()) { 2608 // added support for stack operands 2609 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2610 switch (code) { 2611 case lir_logic_and: __ andl (reg, raddr); break; 2612 case lir_logic_or: __ orl (reg, raddr); break; 2613 case lir_logic_xor: __ xorl (reg, raddr); break; 2614 default: ShouldNotReachHere(); 2615 } 2616 } else { 2617 Register rright = right->as_register(); 2618 switch (code) { 2619 case lir_logic_and: __ andptr (reg, rright); break; 2620 case lir_logic_or : __ orptr (reg, rright); break; 2621 case lir_logic_xor: __ xorptr (reg, rright); break; 2622 default: ShouldNotReachHere(); 2623 } 2624 } 2625 move_regs(reg, dst->as_register()); 2626 } else { 2627 Register l_lo = left->as_register_lo(); 2628 Register l_hi = left->as_register_hi(); 2629 if (right->is_constant()) { 2630 #ifdef _LP64 2631 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2632 switch (code) { 2633 case lir_logic_and: 2634 __ andq(l_lo, rscratch1); 2635 break; 2636 case lir_logic_or: 2637 __ orq(l_lo, rscratch1); 2638 break; 2639 case lir_logic_xor: 2640 __ xorq(l_lo, rscratch1); 2641 break; 2642 default: ShouldNotReachHere(); 2643 } 2644 #else 2645 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2646 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2647 switch (code) { 2648 case lir_logic_and: 2649 __ andl(l_lo, r_lo); 2650 __ andl(l_hi, r_hi); 2651 break; 2652 case lir_logic_or: 2653 __ orl(l_lo, r_lo); 2654 __ orl(l_hi, r_hi); 2655 break; 2656 case lir_logic_xor: 2657 __ xorl(l_lo, r_lo); 2658 __ xorl(l_hi, r_hi); 2659 break; 2660 default: ShouldNotReachHere(); 2661 } 2662 #endif // _LP64 2663 } else { 2664 #ifdef _LP64 2665 Register r_lo; 2666 if (is_reference_type(right->type())) { 2667 r_lo = right->as_register(); 2668 } else { 2669 r_lo = right->as_register_lo(); 2670 } 2671 #else 2672 Register r_lo = right->as_register_lo(); 2673 Register r_hi = right->as_register_hi(); 2674 assert(l_lo != r_hi, "overwriting registers"); 2675 #endif 2676 switch (code) { 2677 case lir_logic_and: 2678 __ andptr(l_lo, r_lo); 2679 NOT_LP64(__ andptr(l_hi, r_hi);) 2680 break; 2681 case lir_logic_or: 2682 __ orptr(l_lo, r_lo); 2683 NOT_LP64(__ orptr(l_hi, r_hi);) 2684 break; 2685 case lir_logic_xor: 2686 __ xorptr(l_lo, r_lo); 2687 NOT_LP64(__ xorptr(l_hi, r_hi);) 2688 break; 2689 default: ShouldNotReachHere(); 2690 } 2691 } 2692 2693 Register dst_lo = dst->as_register_lo(); 2694 Register dst_hi = dst->as_register_hi(); 2695 2696 #ifdef _LP64 2697 move_regs(l_lo, dst_lo); 2698 #else 2699 if (dst_lo == l_hi) { 2700 assert(dst_hi != l_lo, "overwriting registers"); 2701 move_regs(l_hi, dst_hi); 2702 move_regs(l_lo, dst_lo); 2703 } else { 2704 assert(dst_lo != l_hi, "overwriting registers"); 2705 move_regs(l_lo, dst_lo); 2706 move_regs(l_hi, dst_hi); 2707 } 2708 #endif // _LP64 2709 } 2710 } 2711 2712 2713 // we assume that rax, and rdx can be overwritten 2714 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2715 2716 assert(left->is_single_cpu(), "left must be register"); 2717 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2718 assert(result->is_single_cpu(), "result must be register"); 2719 2720 // assert(left->destroys_register(), "check"); 2721 // assert(right->destroys_register(), "check"); 2722 2723 Register lreg = left->as_register(); 2724 Register dreg = result->as_register(); 2725 2726 if (right->is_constant()) { 2727 jint divisor = right->as_constant_ptr()->as_jint(); 2728 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2729 if (code == lir_idiv) { 2730 assert(lreg == rax, "must be rax,"); 2731 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2732 __ cdql(); // sign extend into rdx:rax 2733 if (divisor == 2) { 2734 __ subl(lreg, rdx); 2735 } else { 2736 __ andl(rdx, divisor - 1); 2737 __ addl(lreg, rdx); 2738 } 2739 __ sarl(lreg, log2i_exact(divisor)); 2740 move_regs(lreg, dreg); 2741 } else if (code == lir_irem) { 2742 Label done; 2743 __ mov(dreg, lreg); 2744 __ andl(dreg, 0x80000000 | (divisor - 1)); 2745 __ jcc(Assembler::positive, done); 2746 __ decrement(dreg); 2747 __ orl(dreg, ~(divisor - 1)); 2748 __ increment(dreg); 2749 __ bind(done); 2750 } else { 2751 ShouldNotReachHere(); 2752 } 2753 } else { 2754 Register rreg = right->as_register(); 2755 assert(lreg == rax, "left register must be rax,"); 2756 assert(rreg != rdx, "right register must not be rdx"); 2757 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2758 2759 move_regs(lreg, rax); 2760 2761 int idivl_offset = __ corrected_idivl(rreg); 2762 if (ImplicitDiv0Checks) { 2763 add_debug_info_for_div0(idivl_offset, info); 2764 } 2765 if (code == lir_irem) { 2766 move_regs(rdx, dreg); // result is in rdx 2767 } else { 2768 move_regs(rax, dreg); 2769 } 2770 } 2771 } 2772 2773 2774 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2775 if (opr1->is_single_cpu()) { 2776 Register reg1 = opr1->as_register(); 2777 if (opr2->is_single_cpu()) { 2778 // cpu register - cpu register 2779 if (is_reference_type(opr1->type())) { 2780 __ cmpoop(reg1, opr2->as_register()); 2781 } else { 2782 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 2783 __ cmpl(reg1, opr2->as_register()); 2784 } 2785 } else if (opr2->is_stack()) { 2786 // cpu register - stack 2787 if (is_reference_type(opr1->type())) { 2788 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2789 } else { 2790 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2791 } 2792 } else if (opr2->is_constant()) { 2793 // cpu register - constant 2794 LIR_Const* c = opr2->as_constant_ptr(); 2795 if (c->type() == T_INT) { 2796 jint i = c->as_jint(); 2797 if (i == 0) { 2798 __ testl(reg1, reg1); 2799 } else { 2800 __ cmpl(reg1, i); 2801 } 2802 } else if (c->type() == T_METADATA) { 2803 // All we need for now is a comparison with null for equality. 2804 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 2805 Metadata* m = c->as_metadata(); 2806 if (m == nullptr) { 2807 __ testptr(reg1, reg1); 2808 } else { 2809 ShouldNotReachHere(); 2810 } 2811 } else if (is_reference_type(c->type())) { 2812 // In 64bit oops are single register 2813 jobject o = c->as_jobject(); 2814 if (o == nullptr) { 2815 __ testptr(reg1, reg1); 2816 } else { 2817 __ cmpoop(reg1, o, rscratch1); 2818 } 2819 } else { 2820 fatal("unexpected type: %s", basictype_to_str(c->type())); 2821 } 2822 // cpu register - address 2823 } else if (opr2->is_address()) { 2824 if (op->info() != nullptr) { 2825 add_debug_info_for_null_check_here(op->info()); 2826 } 2827 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2828 } else { 2829 ShouldNotReachHere(); 2830 } 2831 2832 } else if(opr1->is_double_cpu()) { 2833 Register xlo = opr1->as_register_lo(); 2834 Register xhi = opr1->as_register_hi(); 2835 if (opr2->is_double_cpu()) { 2836 #ifdef _LP64 2837 __ cmpptr(xlo, opr2->as_register_lo()); 2838 #else 2839 // cpu register - cpu register 2840 Register ylo = opr2->as_register_lo(); 2841 Register yhi = opr2->as_register_hi(); 2842 __ subl(xlo, ylo); 2843 __ sbbl(xhi, yhi); 2844 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2845 __ orl(xhi, xlo); 2846 } 2847 #endif // _LP64 2848 } else if (opr2->is_constant()) { 2849 // cpu register - constant 0 2850 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2851 #ifdef _LP64 2852 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2853 #else 2854 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2855 __ orl(xhi, xlo); 2856 #endif // _LP64 2857 } else { 2858 ShouldNotReachHere(); 2859 } 2860 2861 } else if (opr1->is_single_xmm()) { 2862 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2863 if (opr2->is_single_xmm()) { 2864 // xmm register - xmm register 2865 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2866 } else if (opr2->is_stack()) { 2867 // xmm register - stack 2868 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2869 } else if (opr2->is_constant()) { 2870 // xmm register - constant 2871 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2872 } else if (opr2->is_address()) { 2873 // xmm register - address 2874 if (op->info() != nullptr) { 2875 add_debug_info_for_null_check_here(op->info()); 2876 } 2877 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2878 } else { 2879 ShouldNotReachHere(); 2880 } 2881 2882 } else if (opr1->is_double_xmm()) { 2883 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2884 if (opr2->is_double_xmm()) { 2885 // xmm register - xmm register 2886 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2887 } else if (opr2->is_stack()) { 2888 // xmm register - stack 2889 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2890 } else if (opr2->is_constant()) { 2891 // xmm register - constant 2892 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2893 } else if (opr2->is_address()) { 2894 // xmm register - address 2895 if (op->info() != nullptr) { 2896 add_debug_info_for_null_check_here(op->info()); 2897 } 2898 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2899 } else { 2900 ShouldNotReachHere(); 2901 } 2902 2903 #ifndef _LP64 2904 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2905 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2906 assert(opr2->is_fpu_register(), "both must be registers"); 2907 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2908 #endif // LP64 2909 2910 } else if (opr1->is_address() && opr2->is_constant()) { 2911 LIR_Const* c = opr2->as_constant_ptr(); 2912 #ifdef _LP64 2913 if (is_reference_type(c->type())) { 2914 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2915 __ movoop(rscratch1, c->as_jobject()); 2916 } 2917 #endif // LP64 2918 if (op->info() != nullptr) { 2919 add_debug_info_for_null_check_here(op->info()); 2920 } 2921 // special case: address - constant 2922 LIR_Address* addr = opr1->as_address_ptr(); 2923 if (c->type() == T_INT) { 2924 __ cmpl(as_Address(addr), c->as_jint()); 2925 } else if (is_reference_type(c->type())) { 2926 #ifdef _LP64 2927 // %%% Make this explode if addr isn't reachable until we figure out a 2928 // better strategy by giving noreg as the temp for as_Address 2929 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2930 #else 2931 __ cmpoop(as_Address(addr), c->as_jobject()); 2932 #endif // _LP64 2933 } else { 2934 ShouldNotReachHere(); 2935 } 2936 2937 } else { 2938 ShouldNotReachHere(); 2939 } 2940 } 2941 2942 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2943 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2944 if (left->is_single_xmm()) { 2945 assert(right->is_single_xmm(), "must match"); 2946 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2947 } else if (left->is_double_xmm()) { 2948 assert(right->is_double_xmm(), "must match"); 2949 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2950 2951 } else { 2952 #ifdef _LP64 2953 ShouldNotReachHere(); 2954 #else 2955 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2956 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2957 2958 assert(left->fpu() == 0, "left must be on TOS"); 2959 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2960 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2961 #endif // LP64 2962 } 2963 } else { 2964 assert(code == lir_cmp_l2i, "check"); 2965 #ifdef _LP64 2966 Label done; 2967 Register dest = dst->as_register(); 2968 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2969 __ movl(dest, -1); 2970 __ jccb(Assembler::less, done); 2971 __ setb(Assembler::notZero, dest); 2972 __ movzbl(dest, dest); 2973 __ bind(done); 2974 #else 2975 __ lcmp2int(left->as_register_hi(), 2976 left->as_register_lo(), 2977 right->as_register_hi(), 2978 right->as_register_lo()); 2979 move_regs(left->as_register_hi(), dst->as_register()); 2980 #endif // _LP64 2981 } 2982 } 2983 2984 2985 void LIR_Assembler::align_call(LIR_Code code) { 2986 // make sure that the displacement word of the call ends up word aligned 2987 int offset = __ offset(); 2988 switch (code) { 2989 case lir_static_call: 2990 case lir_optvirtual_call: 2991 case lir_dynamic_call: 2992 offset += NativeCall::displacement_offset; 2993 break; 2994 case lir_icvirtual_call: 2995 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex; 2996 break; 2997 default: ShouldNotReachHere(); 2998 } 2999 __ align(BytesPerWord, offset); 3000 } 3001 3002 3003 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 3004 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 3005 "must be aligned"); 3006 __ call(AddressLiteral(op->addr(), rtype)); 3007 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields()); 3008 __ post_call_nop(); 3009 } 3010 3011 3012 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 3013 __ ic_call(op->addr()); 3014 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields()); 3015 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 3016 "must be aligned"); 3017 __ post_call_nop(); 3018 } 3019 3020 3021 void LIR_Assembler::emit_static_call_stub() { 3022 address call_pc = __ pc(); 3023 address stub = __ start_a_stub(call_stub_size()); 3024 if (stub == nullptr) { 3025 bailout("static call stub overflow"); 3026 return; 3027 } 3028 3029 int start = __ offset(); 3030 3031 // make sure that the displacement word of the call ends up word aligned 3032 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset); 3033 __ relocate(static_stub_Relocation::spec(call_pc)); 3034 __ mov_metadata(rbx, (Metadata*)nullptr); 3035 // must be set to -1 at code generation time 3036 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned"); 3037 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 3038 __ jump(RuntimeAddress(__ pc())); 3039 3040 assert(__ offset() - start <= call_stub_size(), "stub too big"); 3041 __ end_a_stub(); 3042 } 3043 3044 3045 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 3046 assert(exceptionOop->as_register() == rax, "must match"); 3047 assert(exceptionPC->as_register() == rdx, "must match"); 3048 3049 // exception object is not added to oop map by LinearScan 3050 // (LinearScan assumes that no oops are in fixed registers) 3051 info->add_register_oop(exceptionOop); 3052 Runtime1::StubID unwind_id; 3053 3054 // get current pc information 3055 // pc is only needed if the method has an exception handler, the unwind code does not need it. 3056 int pc_for_athrow_offset = __ offset(); 3057 InternalAddress pc_for_athrow(__ pc()); 3058 __ lea(exceptionPC->as_register(), pc_for_athrow); 3059 add_call_info(pc_for_athrow_offset, info); // for exception handler 3060 3061 __ verify_not_null_oop(rax); 3062 // search an exception handler (rax: exception oop, rdx: throwing pc) 3063 if (compilation()->has_fpu_code()) { 3064 unwind_id = Runtime1::handle_exception_id; 3065 } else { 3066 unwind_id = Runtime1::handle_exception_nofpu_id; 3067 } 3068 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 3069 3070 // enough room for two byte trap 3071 __ nop(); 3072 } 3073 3074 3075 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 3076 assert(exceptionOop->as_register() == rax, "must match"); 3077 3078 __ jmp(_unwind_handler_entry); 3079 } 3080 3081 3082 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 3083 3084 // optimized version for linear scan: 3085 // * count must be already in ECX (guaranteed by LinearScan) 3086 // * left and dest must be equal 3087 // * tmp must be unused 3088 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 3089 assert(left == dest, "left and dest must be equal"); 3090 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 3091 3092 if (left->is_single_cpu()) { 3093 Register value = left->as_register(); 3094 assert(value != SHIFT_count, "left cannot be ECX"); 3095 3096 switch (code) { 3097 case lir_shl: __ shll(value); break; 3098 case lir_shr: __ sarl(value); break; 3099 case lir_ushr: __ shrl(value); break; 3100 default: ShouldNotReachHere(); 3101 } 3102 } else if (left->is_double_cpu()) { 3103 Register lo = left->as_register_lo(); 3104 Register hi = left->as_register_hi(); 3105 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 3106 #ifdef _LP64 3107 switch (code) { 3108 case lir_shl: __ shlptr(lo); break; 3109 case lir_shr: __ sarptr(lo); break; 3110 case lir_ushr: __ shrptr(lo); break; 3111 default: ShouldNotReachHere(); 3112 } 3113 #else 3114 3115 switch (code) { 3116 case lir_shl: __ lshl(hi, lo); break; 3117 case lir_shr: __ lshr(hi, lo, true); break; 3118 case lir_ushr: __ lshr(hi, lo, false); break; 3119 default: ShouldNotReachHere(); 3120 } 3121 #endif // LP64 3122 } else { 3123 ShouldNotReachHere(); 3124 } 3125 } 3126 3127 3128 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 3129 if (dest->is_single_cpu()) { 3130 // first move left into dest so that left is not destroyed by the shift 3131 Register value = dest->as_register(); 3132 count = count & 0x1F; // Java spec 3133 3134 move_regs(left->as_register(), value); 3135 switch (code) { 3136 case lir_shl: __ shll(value, count); break; 3137 case lir_shr: __ sarl(value, count); break; 3138 case lir_ushr: __ shrl(value, count); break; 3139 default: ShouldNotReachHere(); 3140 } 3141 } else if (dest->is_double_cpu()) { 3142 #ifndef _LP64 3143 Unimplemented(); 3144 #else 3145 // first move left into dest so that left is not destroyed by the shift 3146 Register value = dest->as_register_lo(); 3147 count = count & 0x1F; // Java spec 3148 3149 move_regs(left->as_register_lo(), value); 3150 switch (code) { 3151 case lir_shl: __ shlptr(value, count); break; 3152 case lir_shr: __ sarptr(value, count); break; 3153 case lir_ushr: __ shrptr(value, count); break; 3154 default: ShouldNotReachHere(); 3155 } 3156 #endif // _LP64 3157 } else { 3158 ShouldNotReachHere(); 3159 } 3160 } 3161 3162 3163 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3164 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3165 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3166 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3167 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3168 } 3169 3170 3171 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3172 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3173 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3174 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3175 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3176 } 3177 3178 3179 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3180 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3181 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3182 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3183 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1); 3184 } 3185 3186 3187 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3188 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3189 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3190 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3191 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1); 3192 } 3193 3194 3195 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) { 3196 if (null_check) { 3197 __ testptr(obj, obj); 3198 __ jcc(Assembler::zero, *slow_path->entry()); 3199 } 3200 if (is_dest) { 3201 __ test_null_free_array_oop(obj, tmp, *slow_path->entry()); 3202 } else { 3203 __ test_flat_array_oop(obj, tmp, *slow_path->entry()); 3204 } 3205 } 3206 3207 3208 // This code replaces a call to arraycopy; no exception may 3209 // be thrown in this code, they must be thrown in the System.arraycopy 3210 // activation frame; we could save some checks if this would not be the case 3211 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3212 ciArrayKlass* default_type = op->expected_type(); 3213 Register src = op->src()->as_register(); 3214 Register dst = op->dst()->as_register(); 3215 Register src_pos = op->src_pos()->as_register(); 3216 Register dst_pos = op->dst_pos()->as_register(); 3217 Register length = op->length()->as_register(); 3218 Register tmp = op->tmp()->as_register(); 3219 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3220 3221 CodeStub* stub = op->stub(); 3222 int flags = op->flags(); 3223 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL; 3224 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 3225 3226 if (flags & LIR_OpArrayCopy::always_slow_path) { 3227 __ jmp(*stub->entry()); 3228 __ bind(*stub->continuation()); 3229 return; 3230 } 3231 3232 // if we don't know anything, just go through the generic arraycopy 3233 if (default_type == nullptr) { 3234 // save outgoing arguments on stack in case call to System.arraycopy is needed 3235 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3236 // for interpreter calling conventions. Now we have to do it in new style conventions. 3237 // For the moment until C1 gets the new register allocator I just force all the 3238 // args to the right place (except the register args) and then on the back side 3239 // reload the register args properly if we go slow path. Yuck 3240 3241 // These are proper for the calling convention 3242 store_parameter(length, 2); 3243 store_parameter(dst_pos, 1); 3244 store_parameter(dst, 0); 3245 3246 // these are just temporary placements until we need to reload 3247 store_parameter(src_pos, 3); 3248 store_parameter(src, 4); 3249 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3250 3251 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3252 assert(copyfunc_addr != nullptr, "generic arraycopy stub required"); 3253 3254 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3255 #ifdef _LP64 3256 // The arguments are in java calling convention so we can trivially shift them to C 3257 // convention 3258 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3259 __ mov(c_rarg0, j_rarg0); 3260 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3261 __ mov(c_rarg1, j_rarg1); 3262 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3263 __ mov(c_rarg2, j_rarg2); 3264 assert_different_registers(c_rarg3, j_rarg4); 3265 __ mov(c_rarg3, j_rarg3); 3266 #ifdef _WIN64 3267 // Allocate abi space for args but be sure to keep stack aligned 3268 __ subptr(rsp, 6*wordSize); 3269 store_parameter(j_rarg4, 4); 3270 #ifndef PRODUCT 3271 if (PrintC1Statistics) { 3272 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3273 } 3274 #endif 3275 __ call(RuntimeAddress(copyfunc_addr)); 3276 __ addptr(rsp, 6*wordSize); 3277 #else 3278 __ mov(c_rarg4, j_rarg4); 3279 #ifndef PRODUCT 3280 if (PrintC1Statistics) { 3281 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3282 } 3283 #endif 3284 __ call(RuntimeAddress(copyfunc_addr)); 3285 #endif // _WIN64 3286 #else 3287 __ push(length); 3288 __ push(dst_pos); 3289 __ push(dst); 3290 __ push(src_pos); 3291 __ push(src); 3292 3293 #ifndef PRODUCT 3294 if (PrintC1Statistics) { 3295 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1); 3296 } 3297 #endif 3298 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3299 3300 #endif // _LP64 3301 3302 __ testl(rax, rax); 3303 __ jcc(Assembler::equal, *stub->continuation()); 3304 3305 __ mov(tmp, rax); 3306 __ xorl(tmp, -1); 3307 3308 // Reload values from the stack so they are where the stub 3309 // expects them. 3310 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3311 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3312 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3313 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3314 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3315 3316 __ subl(length, tmp); 3317 __ addl(src_pos, tmp); 3318 __ addl(dst_pos, tmp); 3319 __ jmp(*stub->entry()); 3320 3321 __ bind(*stub->continuation()); 3322 return; 3323 } 3324 3325 // Handle inline type arrays 3326 if (flags & LIR_OpArrayCopy::src_inlinetype_check) { 3327 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check)); 3328 } 3329 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) { 3330 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check)); 3331 } 3332 3333 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3334 3335 int elem_size = type2aelembytes(basic_type); 3336 Address::ScaleFactor scale; 3337 3338 switch (elem_size) { 3339 case 1 : 3340 scale = Address::times_1; 3341 break; 3342 case 2 : 3343 scale = Address::times_2; 3344 break; 3345 case 4 : 3346 scale = Address::times_4; 3347 break; 3348 case 8 : 3349 scale = Address::times_8; 3350 break; 3351 default: 3352 scale = Address::no_scale; 3353 ShouldNotReachHere(); 3354 } 3355 3356 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3357 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3358 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3359 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3360 3361 // length and pos's are all sign extended at this point on 64bit 3362 3363 // test for null 3364 if (flags & LIR_OpArrayCopy::src_null_check) { 3365 __ testptr(src, src); 3366 __ jcc(Assembler::zero, *stub->entry()); 3367 } 3368 if (flags & LIR_OpArrayCopy::dst_null_check) { 3369 __ testptr(dst, dst); 3370 __ jcc(Assembler::zero, *stub->entry()); 3371 } 3372 3373 // If the compiler was not able to prove that exact type of the source or the destination 3374 // of the arraycopy is an array type, check at runtime if the source or the destination is 3375 // an instance type. 3376 if (flags & LIR_OpArrayCopy::type_check) { 3377 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3378 __ load_klass(tmp, dst, tmp_load_klass); 3379 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3380 __ jcc(Assembler::greaterEqual, *stub->entry()); 3381 } 3382 3383 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3384 __ load_klass(tmp, src, tmp_load_klass); 3385 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3386 __ jcc(Assembler::greaterEqual, *stub->entry()); 3387 } 3388 } 3389 3390 // check if negative 3391 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3392 __ testl(src_pos, src_pos); 3393 __ jcc(Assembler::less, *stub->entry()); 3394 } 3395 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3396 __ testl(dst_pos, dst_pos); 3397 __ jcc(Assembler::less, *stub->entry()); 3398 } 3399 3400 if (flags & LIR_OpArrayCopy::src_range_check) { 3401 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3402 __ cmpl(tmp, src_length_addr); 3403 __ jcc(Assembler::above, *stub->entry()); 3404 } 3405 if (flags & LIR_OpArrayCopy::dst_range_check) { 3406 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3407 __ cmpl(tmp, dst_length_addr); 3408 __ jcc(Assembler::above, *stub->entry()); 3409 } 3410 3411 if (flags & LIR_OpArrayCopy::length_positive_check) { 3412 __ testl(length, length); 3413 __ jcc(Assembler::less, *stub->entry()); 3414 } 3415 3416 #ifdef _LP64 3417 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3418 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3419 #endif 3420 3421 if (flags & LIR_OpArrayCopy::type_check) { 3422 // We don't know the array types are compatible 3423 if (basic_type != T_OBJECT) { 3424 // Simple test for basic type arrays 3425 if (UseCompressedClassPointers) { 3426 __ movl(tmp, src_klass_addr); 3427 __ cmpl(tmp, dst_klass_addr); 3428 } else { 3429 __ movptr(tmp, src_klass_addr); 3430 __ cmpptr(tmp, dst_klass_addr); 3431 } 3432 __ jcc(Assembler::notEqual, *stub->entry()); 3433 } else { 3434 // For object arrays, if src is a sub class of dst then we can 3435 // safely do the copy. 3436 Label cont, slow; 3437 3438 __ push(src); 3439 __ push(dst); 3440 3441 __ load_klass(src, src, tmp_load_klass); 3442 __ load_klass(dst, dst, tmp_load_klass); 3443 3444 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr); 3445 3446 __ push(src); 3447 __ push(dst); 3448 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3449 __ pop(dst); 3450 __ pop(src); 3451 3452 __ testl(src, src); 3453 __ jcc(Assembler::notEqual, cont); 3454 3455 __ bind(slow); 3456 __ pop(dst); 3457 __ pop(src); 3458 3459 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3460 if (copyfunc_addr != nullptr) { // use stub if available 3461 // src is not a sub class of dst so we have to do a 3462 // per-element check. 3463 3464 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3465 if ((flags & mask) != mask) { 3466 // Check that at least both of them object arrays. 3467 assert(flags & mask, "one of the two should be known to be an object array"); 3468 3469 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3470 __ load_klass(tmp, src, tmp_load_klass); 3471 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3472 __ load_klass(tmp, dst, tmp_load_klass); 3473 } 3474 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3475 Address klass_lh_addr(tmp, lh_offset); 3476 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3477 __ cmpl(klass_lh_addr, objArray_lh); 3478 __ jcc(Assembler::notEqual, *stub->entry()); 3479 } 3480 3481 // Spill because stubs can use any register they like and it's 3482 // easier to restore just those that we care about. 3483 store_parameter(dst, 0); 3484 store_parameter(dst_pos, 1); 3485 store_parameter(length, 2); 3486 store_parameter(src_pos, 3); 3487 store_parameter(src, 4); 3488 3489 #ifndef _LP64 3490 __ movptr(tmp, dst_klass_addr); 3491 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3492 __ push(tmp); 3493 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3494 __ push(tmp); 3495 __ push(length); 3496 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3497 __ push(tmp); 3498 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3499 __ push(tmp); 3500 3501 __ call_VM_leaf(copyfunc_addr, 5); 3502 #else 3503 __ movl2ptr(length, length); //higher 32bits must be null 3504 3505 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3506 assert_different_registers(c_rarg0, dst, dst_pos, length); 3507 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3508 assert_different_registers(c_rarg1, dst, length); 3509 3510 __ mov(c_rarg2, length); 3511 assert_different_registers(c_rarg2, dst); 3512 3513 #ifdef _WIN64 3514 // Allocate abi space for args but be sure to keep stack aligned 3515 __ subptr(rsp, 6*wordSize); 3516 __ load_klass(c_rarg3, dst, tmp_load_klass); 3517 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3518 store_parameter(c_rarg3, 4); 3519 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3520 __ call(RuntimeAddress(copyfunc_addr)); 3521 __ addptr(rsp, 6*wordSize); 3522 #else 3523 __ load_klass(c_rarg4, dst, tmp_load_klass); 3524 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3525 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3526 __ call(RuntimeAddress(copyfunc_addr)); 3527 #endif 3528 3529 #endif 3530 3531 #ifndef PRODUCT 3532 if (PrintC1Statistics) { 3533 Label failed; 3534 __ testl(rax, rax); 3535 __ jcc(Assembler::notZero, failed); 3536 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1); 3537 __ bind(failed); 3538 } 3539 #endif 3540 3541 __ testl(rax, rax); 3542 __ jcc(Assembler::zero, *stub->continuation()); 3543 3544 #ifndef PRODUCT 3545 if (PrintC1Statistics) { 3546 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1); 3547 } 3548 #endif 3549 3550 __ mov(tmp, rax); 3551 3552 __ xorl(tmp, -1); 3553 3554 // Restore previously spilled arguments 3555 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3556 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3557 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3558 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3559 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3560 3561 3562 __ subl(length, tmp); 3563 __ addl(src_pos, tmp); 3564 __ addl(dst_pos, tmp); 3565 } 3566 3567 __ jmp(*stub->entry()); 3568 3569 __ bind(cont); 3570 __ pop(dst); 3571 __ pop(src); 3572 } 3573 } 3574 3575 #ifdef ASSERT 3576 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3577 // Sanity check the known type with the incoming class. For the 3578 // primitive case the types must match exactly with src.klass and 3579 // dst.klass each exactly matching the default type. For the 3580 // object array case, if no type check is needed then either the 3581 // dst type is exactly the expected type and the src type is a 3582 // subtype which we can't check or src is the same array as dst 3583 // but not necessarily exactly of type default_type. 3584 Label known_ok, halt; 3585 __ mov_metadata(tmp, default_type->constant_encoding()); 3586 #ifdef _LP64 3587 if (UseCompressedClassPointers) { 3588 __ encode_klass_not_null(tmp, rscratch1); 3589 } 3590 #endif 3591 3592 if (basic_type != T_OBJECT) { 3593 3594 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3595 else __ cmpptr(tmp, dst_klass_addr); 3596 __ jcc(Assembler::notEqual, halt); 3597 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3598 else __ cmpptr(tmp, src_klass_addr); 3599 __ jcc(Assembler::equal, known_ok); 3600 } else { 3601 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3602 else __ cmpptr(tmp, dst_klass_addr); 3603 __ jcc(Assembler::equal, known_ok); 3604 __ cmpptr(src, dst); 3605 __ jcc(Assembler::equal, known_ok); 3606 } 3607 __ bind(halt); 3608 __ stop("incorrect type information in arraycopy"); 3609 __ bind(known_ok); 3610 } 3611 #endif 3612 3613 #ifndef PRODUCT 3614 if (PrintC1Statistics) { 3615 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1); 3616 } 3617 #endif 3618 3619 #ifdef _LP64 3620 assert_different_registers(c_rarg0, dst, dst_pos, length); 3621 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3622 assert_different_registers(c_rarg1, length); 3623 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3624 __ mov(c_rarg2, length); 3625 3626 #else 3627 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3628 store_parameter(tmp, 0); 3629 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3630 store_parameter(tmp, 1); 3631 store_parameter(length, 2); 3632 #endif // _LP64 3633 3634 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3635 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3636 const char *name; 3637 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3638 __ call_VM_leaf(entry, 0); 3639 3640 if (stub != nullptr) { 3641 __ bind(*stub->continuation()); 3642 } 3643 } 3644 3645 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3646 assert(op->crc()->is_single_cpu(), "crc must be register"); 3647 assert(op->val()->is_single_cpu(), "byte value must be register"); 3648 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3649 Register crc = op->crc()->as_register(); 3650 Register val = op->val()->as_register(); 3651 Register res = op->result_opr()->as_register(); 3652 3653 assert_different_registers(val, crc, res); 3654 3655 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3656 __ notl(crc); // ~crc 3657 __ update_byte_crc32(crc, val, res); 3658 __ notl(crc); // ~crc 3659 __ mov(res, crc); 3660 } 3661 3662 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3663 Register obj = op->obj_opr()->as_register(); // may not be an oop 3664 Register hdr = op->hdr_opr()->as_register(); 3665 Register lock = op->lock_opr()->as_register(); 3666 if (LockingMode == LM_MONITOR) { 3667 if (op->info() != nullptr) { 3668 add_debug_info_for_null_check_here(op->info()); 3669 __ null_check(obj); 3670 } 3671 __ jmp(*op->stub()->entry()); 3672 } else if (op->code() == lir_lock) { 3673 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3674 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg; 3675 // add debug info for NullPointerException only if one is possible 3676 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry()); 3677 if (op->info() != nullptr) { 3678 add_debug_info_for_null_check(null_check_offset, op->info()); 3679 } 3680 // done 3681 } else if (op->code() == lir_unlock) { 3682 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3683 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3684 } else { 3685 Unimplemented(); 3686 } 3687 __ bind(*op->stub()->continuation()); 3688 } 3689 3690 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 3691 Register obj = op->obj()->as_pointer_register(); 3692 Register result = op->result_opr()->as_pointer_register(); 3693 3694 CodeEmitInfo* info = op->info(); 3695 if (info != nullptr) { 3696 add_debug_info_for_null_check_here(info); 3697 } 3698 3699 #ifdef _LP64 3700 if (UseCompressedClassPointers) { 3701 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes())); 3702 __ decode_klass_not_null(result, rscratch1); 3703 } else 3704 #endif 3705 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes())); 3706 } 3707 3708 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3709 ciMethod* method = op->profiled_method(); 3710 int bci = op->profiled_bci(); 3711 ciMethod* callee = op->profiled_callee(); 3712 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3713 3714 // Update counter for all call types 3715 ciMethodData* md = method->method_data_or_null(); 3716 assert(md != nullptr, "Sanity"); 3717 ciProfileData* data = md->bci_to_data(bci); 3718 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls"); 3719 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3720 Register mdo = op->mdo()->as_register(); 3721 __ mov_metadata(mdo, md->constant_encoding()); 3722 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3723 // Perform additional virtual call profiling for invokevirtual and 3724 // invokeinterface bytecodes 3725 if (op->should_profile_receiver_type()) { 3726 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3727 Register recv = op->recv()->as_register(); 3728 assert_different_registers(mdo, recv); 3729 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3730 ciKlass* known_klass = op->known_holder(); 3731 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) { 3732 // We know the type that will be seen at this call site; we can 3733 // statically update the MethodData* rather than needing to do 3734 // dynamic tests on the receiver type 3735 3736 // NOTE: we should probably put a lock around this search to 3737 // avoid collisions by concurrent compilations 3738 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3739 uint i; 3740 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3741 ciKlass* receiver = vc_data->receiver(i); 3742 if (known_klass->equals(receiver)) { 3743 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3744 __ addptr(data_addr, DataLayout::counter_increment); 3745 return; 3746 } 3747 } 3748 3749 // Receiver type not found in profile data; select an empty slot 3750 3751 // Note that this is less efficient than it should be because it 3752 // always does a write to the receiver part of the 3753 // VirtualCallData rather than just the first time 3754 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3755 ciKlass* receiver = vc_data->receiver(i); 3756 if (receiver == nullptr) { 3757 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3758 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1); 3759 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3760 __ addptr(data_addr, DataLayout::counter_increment); 3761 return; 3762 } 3763 } 3764 } else { 3765 __ load_klass(recv, recv, tmp_load_klass); 3766 Label update_done; 3767 type_profile_helper(mdo, md, data, recv, &update_done); 3768 // Receiver did not match any saved receiver and there is no empty row for it. 3769 // Increment total counter to indicate polymorphic case. 3770 __ addptr(counter_addr, DataLayout::counter_increment); 3771 3772 __ bind(update_done); 3773 } 3774 } else { 3775 // Static call 3776 __ addptr(counter_addr, DataLayout::counter_increment); 3777 } 3778 } 3779 3780 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3781 Register obj = op->obj()->as_register(); 3782 Register tmp = op->tmp()->as_pointer_register(); 3783 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg); 3784 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3785 ciKlass* exact_klass = op->exact_klass(); 3786 intptr_t current_klass = op->current_klass(); 3787 bool not_null = op->not_null(); 3788 bool no_conflict = op->no_conflict(); 3789 3790 Label update, next, none; 3791 3792 bool do_null = !not_null; 3793 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3794 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3795 3796 assert(do_null || do_update, "why are we here?"); 3797 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3798 3799 __ verify_oop(obj); 3800 3801 #ifdef ASSERT 3802 if (obj == tmp) { 3803 #ifdef _LP64 3804 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index()); 3805 #else 3806 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index()); 3807 #endif 3808 } else { 3809 #ifdef _LP64 3810 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index()); 3811 #else 3812 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index()); 3813 #endif 3814 } 3815 #endif 3816 if (do_null) { 3817 __ testptr(obj, obj); 3818 __ jccb(Assembler::notZero, update); 3819 if (!TypeEntries::was_null_seen(current_klass)) { 3820 __ testptr(mdo_addr, TypeEntries::null_seen); 3821 #ifndef ASSERT 3822 __ jccb(Assembler::notZero, next); // already set 3823 #else 3824 __ jcc(Assembler::notZero, next); // already set 3825 #endif 3826 // atomic update to prevent overwriting Klass* with 0 3827 __ lock(); 3828 __ orptr(mdo_addr, TypeEntries::null_seen); 3829 } 3830 if (do_update) { 3831 #ifndef ASSERT 3832 __ jmpb(next); 3833 } 3834 #else 3835 __ jmp(next); 3836 } 3837 } else { 3838 __ testptr(obj, obj); 3839 __ jcc(Assembler::notZero, update); 3840 __ stop("unexpected null obj"); 3841 #endif 3842 } 3843 3844 __ bind(update); 3845 3846 if (do_update) { 3847 #ifdef ASSERT 3848 if (exact_klass != nullptr) { 3849 Label ok; 3850 __ load_klass(tmp, obj, tmp_load_klass); 3851 __ push(tmp); 3852 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3853 __ cmpptr(tmp, Address(rsp, 0)); 3854 __ jcc(Assembler::equal, ok); 3855 __ stop("exact klass and actual klass differ"); 3856 __ bind(ok); 3857 __ pop(tmp); 3858 } 3859 #endif 3860 if (!no_conflict) { 3861 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) { 3862 if (exact_klass != nullptr) { 3863 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3864 } else { 3865 __ load_klass(tmp, obj, tmp_load_klass); 3866 } 3867 #ifdef _LP64 3868 __ mov(rscratch1, tmp); // save original value before XOR 3869 #endif 3870 __ xorptr(tmp, mdo_addr); 3871 __ testptr(tmp, TypeEntries::type_klass_mask); 3872 // klass seen before, nothing to do. The unknown bit may have been 3873 // set already but no need to check. 3874 __ jccb(Assembler::zero, next); 3875 3876 __ testptr(tmp, TypeEntries::type_unknown); 3877 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3878 3879 if (TypeEntries::is_type_none(current_klass)) { 3880 __ testptr(mdo_addr, TypeEntries::type_mask); 3881 __ jccb(Assembler::zero, none); 3882 #ifdef _LP64 3883 // There is a chance that the checks above (re-reading profiling 3884 // data from memory) fail if another thread has just set the 3885 // profiling to this obj's klass 3886 __ mov(tmp, rscratch1); // get back original value before XOR 3887 __ xorptr(tmp, mdo_addr); 3888 __ testptr(tmp, TypeEntries::type_klass_mask); 3889 __ jccb(Assembler::zero, next); 3890 #endif 3891 } 3892 } else { 3893 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 3894 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3895 3896 __ testptr(mdo_addr, TypeEntries::type_unknown); 3897 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3898 } 3899 3900 // different than before. Cannot keep accurate profile. 3901 __ orptr(mdo_addr, TypeEntries::type_unknown); 3902 3903 if (TypeEntries::is_type_none(current_klass)) { 3904 __ jmpb(next); 3905 3906 __ bind(none); 3907 // first time here. Set profile type. 3908 __ movptr(mdo_addr, tmp); 3909 #ifdef ASSERT 3910 __ andptr(tmp, TypeEntries::type_klass_mask); 3911 __ verify_klass_ptr(tmp); 3912 #endif 3913 } 3914 } else { 3915 // There's a single possible klass at this profile point 3916 assert(exact_klass != nullptr, "should be"); 3917 if (TypeEntries::is_type_none(current_klass)) { 3918 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3919 __ xorptr(tmp, mdo_addr); 3920 __ testptr(tmp, TypeEntries::type_klass_mask); 3921 #ifdef ASSERT 3922 __ jcc(Assembler::zero, next); 3923 3924 { 3925 Label ok; 3926 __ push(tmp); 3927 __ testptr(mdo_addr, TypeEntries::type_mask); 3928 __ jcc(Assembler::zero, ok); 3929 // may have been set by another thread 3930 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3931 __ xorptr(tmp, mdo_addr); 3932 __ testptr(tmp, TypeEntries::type_mask); 3933 __ jcc(Assembler::zero, ok); 3934 3935 __ stop("unexpected profiling mismatch"); 3936 __ bind(ok); 3937 __ pop(tmp); 3938 } 3939 #else 3940 __ jccb(Assembler::zero, next); 3941 #endif 3942 // first time here. Set profile type. 3943 __ movptr(mdo_addr, tmp); 3944 #ifdef ASSERT 3945 __ andptr(tmp, TypeEntries::type_klass_mask); 3946 __ verify_klass_ptr(tmp); 3947 #endif 3948 } else { 3949 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 3950 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3951 3952 __ testptr(mdo_addr, TypeEntries::type_unknown); 3953 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3954 3955 __ orptr(mdo_addr, TypeEntries::type_unknown); 3956 } 3957 } 3958 } 3959 __ bind(next); 3960 } 3961 3962 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) { 3963 Register obj = op->obj()->as_register(); 3964 Register tmp = op->tmp()->as_pointer_register(); 3965 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3966 bool not_null = op->not_null(); 3967 int flag = op->flag(); 3968 3969 Label not_inline_type; 3970 if (!not_null) { 3971 __ testptr(obj, obj); 3972 __ jccb(Assembler::zero, not_inline_type); 3973 } 3974 3975 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type); 3976 3977 __ orb(mdo_addr, flag); 3978 3979 __ bind(not_inline_type); 3980 } 3981 3982 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3983 Unimplemented(); 3984 } 3985 3986 3987 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3988 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3989 } 3990 3991 3992 void LIR_Assembler::align_backward_branch_target() { 3993 __ align(BytesPerWord); 3994 } 3995 3996 3997 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 3998 if (left->is_single_cpu()) { 3999 __ negl(left->as_register()); 4000 move_regs(left->as_register(), dest->as_register()); 4001 4002 } else if (left->is_double_cpu()) { 4003 Register lo = left->as_register_lo(); 4004 #ifdef _LP64 4005 Register dst = dest->as_register_lo(); 4006 __ movptr(dst, lo); 4007 __ negptr(dst); 4008 #else 4009 Register hi = left->as_register_hi(); 4010 __ lneg(hi, lo); 4011 if (dest->as_register_lo() == hi) { 4012 assert(dest->as_register_hi() != lo, "destroying register"); 4013 move_regs(hi, dest->as_register_hi()); 4014 move_regs(lo, dest->as_register_lo()); 4015 } else { 4016 move_regs(lo, dest->as_register_lo()); 4017 move_regs(hi, dest->as_register_hi()); 4018 } 4019 #endif // _LP64 4020 4021 } else if (dest->is_single_xmm()) { 4022 #ifdef _LP64 4023 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 4024 assert(tmp->is_valid(), "need temporary"); 4025 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 4026 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2); 4027 } 4028 else 4029 #endif 4030 { 4031 assert(!tmp->is_valid(), "do not need temporary"); 4032 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 4033 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 4034 } 4035 __ xorps(dest->as_xmm_float_reg(), 4036 ExternalAddress((address)float_signflip_pool), 4037 rscratch1); 4038 } 4039 } else if (dest->is_double_xmm()) { 4040 #ifdef _LP64 4041 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 4042 assert(tmp->is_valid(), "need temporary"); 4043 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg()); 4044 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2); 4045 } 4046 else 4047 #endif 4048 { 4049 assert(!tmp->is_valid(), "do not need temporary"); 4050 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 4051 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 4052 } 4053 __ xorpd(dest->as_xmm_double_reg(), 4054 ExternalAddress((address)double_signflip_pool), 4055 rscratch1); 4056 } 4057 #ifndef _LP64 4058 } else if (left->is_single_fpu() || left->is_double_fpu()) { 4059 assert(left->fpu() == 0, "arg must be on TOS"); 4060 assert(dest->fpu() == 0, "dest must be TOS"); 4061 __ fchs(); 4062 #endif // !_LP64 4063 4064 } else { 4065 ShouldNotReachHere(); 4066 } 4067 } 4068 4069 4070 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 4071 assert(src->is_address(), "must be an address"); 4072 assert(dest->is_register(), "must be a register"); 4073 4074 PatchingStub* patch = nullptr; 4075 if (patch_code != lir_patch_none) { 4076 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 4077 } 4078 4079 Register reg = dest->as_pointer_register(); 4080 LIR_Address* addr = src->as_address_ptr(); 4081 __ lea(reg, as_Address(addr)); 4082 4083 if (patch != nullptr) { 4084 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 4085 } 4086 } 4087 4088 4089 4090 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 4091 assert(!tmp->is_valid(), "don't need temporary"); 4092 __ call(RuntimeAddress(dest)); 4093 if (info != nullptr) { 4094 add_call_info_here(info); 4095 } 4096 __ post_call_nop(); 4097 } 4098 4099 4100 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 4101 assert(type == T_LONG, "only for volatile long fields"); 4102 4103 if (info != nullptr) { 4104 add_debug_info_for_null_check_here(info); 4105 } 4106 4107 if (src->is_double_xmm()) { 4108 if (dest->is_double_cpu()) { 4109 #ifdef _LP64 4110 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 4111 #else 4112 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 4113 __ psrlq(src->as_xmm_double_reg(), 32); 4114 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 4115 #endif // _LP64 4116 } else if (dest->is_double_stack()) { 4117 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 4118 } else if (dest->is_address()) { 4119 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 4120 } else { 4121 ShouldNotReachHere(); 4122 } 4123 4124 } else if (dest->is_double_xmm()) { 4125 if (src->is_double_stack()) { 4126 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 4127 } else if (src->is_address()) { 4128 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 4129 } else { 4130 ShouldNotReachHere(); 4131 } 4132 4133 #ifndef _LP64 4134 } else if (src->is_double_fpu()) { 4135 assert(src->fpu_regnrLo() == 0, "must be TOS"); 4136 if (dest->is_double_stack()) { 4137 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 4138 } else if (dest->is_address()) { 4139 __ fistp_d(as_Address(dest->as_address_ptr())); 4140 } else { 4141 ShouldNotReachHere(); 4142 } 4143 4144 } else if (dest->is_double_fpu()) { 4145 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 4146 if (src->is_double_stack()) { 4147 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 4148 } else if (src->is_address()) { 4149 __ fild_d(as_Address(src->as_address_ptr())); 4150 } else { 4151 ShouldNotReachHere(); 4152 } 4153 #endif // !_LP64 4154 4155 } else { 4156 ShouldNotReachHere(); 4157 } 4158 } 4159 4160 #ifdef ASSERT 4161 // emit run-time assertion 4162 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 4163 assert(op->code() == lir_assert, "must be"); 4164 4165 if (op->in_opr1()->is_valid()) { 4166 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 4167 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 4168 } else { 4169 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 4170 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 4171 } 4172 4173 Label ok; 4174 if (op->condition() != lir_cond_always) { 4175 Assembler::Condition acond = Assembler::zero; 4176 switch (op->condition()) { 4177 case lir_cond_equal: acond = Assembler::equal; break; 4178 case lir_cond_notEqual: acond = Assembler::notEqual; break; 4179 case lir_cond_less: acond = Assembler::less; break; 4180 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 4181 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 4182 case lir_cond_greater: acond = Assembler::greater; break; 4183 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 4184 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 4185 default: ShouldNotReachHere(); 4186 } 4187 __ jcc(acond, ok); 4188 } 4189 if (op->halt()) { 4190 const char* str = __ code_string(op->msg()); 4191 __ stop(str); 4192 } else { 4193 breakpoint(); 4194 } 4195 __ bind(ok); 4196 } 4197 #endif 4198 4199 void LIR_Assembler::membar() { 4200 // QQQ sparc TSO uses this, 4201 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4202 } 4203 4204 void LIR_Assembler::membar_acquire() { 4205 // No x86 machines currently require load fences 4206 } 4207 4208 void LIR_Assembler::membar_release() { 4209 // No x86 machines currently require store fences 4210 } 4211 4212 void LIR_Assembler::membar_loadload() { 4213 // no-op 4214 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 4215 } 4216 4217 void LIR_Assembler::membar_storestore() { 4218 // no-op 4219 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 4220 } 4221 4222 void LIR_Assembler::membar_loadstore() { 4223 // no-op 4224 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 4225 } 4226 4227 void LIR_Assembler::membar_storeload() { 4228 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4229 } 4230 4231 void LIR_Assembler::on_spin_wait() { 4232 __ pause (); 4233 } 4234 4235 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 4236 assert(result_reg->is_register(), "check"); 4237 #ifdef _LP64 4238 // __ get_thread(result_reg->as_register_lo()); 4239 __ mov(result_reg->as_register(), r15_thread); 4240 #else 4241 __ get_thread(result_reg->as_register()); 4242 #endif // _LP64 4243 } 4244 4245 void LIR_Assembler::check_orig_pc() { 4246 __ cmpptr(frame_map()->address_for_orig_pc_addr(), NULL_WORD); 4247 } 4248 4249 void LIR_Assembler::peephole(LIR_List*) { 4250 // do nothing for now 4251 } 4252 4253 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 4254 assert(data == dest, "xchg/xadd uses only 2 operands"); 4255 4256 if (data->type() == T_INT) { 4257 if (code == lir_xadd) { 4258 __ lock(); 4259 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 4260 } else { 4261 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 4262 } 4263 } else if (data->is_oop()) { 4264 assert (code == lir_xchg, "xadd for oops"); 4265 Register obj = data->as_register(); 4266 #ifdef _LP64 4267 if (UseCompressedOops) { 4268 __ encode_heap_oop(obj); 4269 __ xchgl(obj, as_Address(src->as_address_ptr())); 4270 __ decode_heap_oop(obj); 4271 } else { 4272 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4273 } 4274 #else 4275 __ xchgl(obj, as_Address(src->as_address_ptr())); 4276 #endif 4277 } else if (data->type() == T_LONG) { 4278 #ifdef _LP64 4279 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4280 if (code == lir_xadd) { 4281 __ lock(); 4282 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4283 } else { 4284 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4285 } 4286 #else 4287 ShouldNotReachHere(); 4288 #endif 4289 } else { 4290 ShouldNotReachHere(); 4291 } 4292 } 4293 4294 #undef __