1 /*
2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "compiler/oopMap.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_x86.hpp"
41 #include "oops/oop.inline.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register IC_Klass = rax; // where the IC klass is cached
78 const Register SYNC_header = rax; // synchronization header
79 const Register SHIFT_count = rcx; // where count for shift operations must be
80
81 #define __ _masm->
82
83
84 static void select_different_registers(Register preserve,
85 Register extra,
86 Register &tmp1,
87 Register &tmp2) {
88 if (tmp1 == preserve) {
89 assert_different_registers(tmp1, tmp2, extra);
90 tmp1 = extra;
91 } else if (tmp2 == preserve) {
92 assert_different_registers(tmp1, tmp2, extra);
93 tmp2 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2);
96 }
97
98
99
100 static void select_different_registers(Register preserve,
101 Register extra,
102 Register &tmp1,
103 Register &tmp2,
104 Register &tmp3) {
105 if (tmp1 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp1 = extra;
108 } else if (tmp2 == preserve) {
109 assert_different_registers(tmp1, tmp2, tmp3, extra);
110 tmp2 = extra;
111 } else if (tmp3 == preserve) {
112 assert_different_registers(tmp1, tmp2, tmp3, extra);
113 tmp3 = extra;
114 }
115 assert_different_registers(preserve, tmp1, tmp2, tmp3);
116 }
117
118
119
120 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
121 if (opr->is_constant()) {
122 LIR_Const* constant = opr->as_constant_ptr();
123 switch (constant->type()) {
124 case T_INT: {
125 return true;
126 }
127
128 default:
129 return false;
130 }
131 }
132 return false;
133 }
134
135
136 LIR_Opr LIR_Assembler::receiverOpr() {
137 return FrameMap::receiver_opr;
138 }
139
140 LIR_Opr LIR_Assembler::osrBufferPointer() {
141 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
142 }
143
144 //--------------fpu register translations-----------------------
145
146
147 address LIR_Assembler::float_constant(float f) {
148 address const_addr = __ float_constant(f);
149 if (const_addr == NULL) {
150 bailout("const section overflow");
151 return __ code()->consts()->start();
152 } else {
153 return const_addr;
154 }
155 }
156
157
158 address LIR_Assembler::double_constant(double d) {
159 address const_addr = __ double_constant(d);
160 if (const_addr == NULL) {
161 bailout("const section overflow");
162 return __ code()->consts()->start();
163 } else {
164 return const_addr;
165 }
166 }
167
168 #ifndef _LP64
169 void LIR_Assembler::fpop() {
170 __ fpop();
171 }
172
173 void LIR_Assembler::fxch(int i) {
174 __ fxch(i);
175 }
176
177 void LIR_Assembler::fld(int i) {
178 __ fld_s(i);
179 }
180
181 void LIR_Assembler::ffree(int i) {
182 __ ffree(i);
183 }
184 #endif // !_LP64
185
186 void LIR_Assembler::breakpoint() {
187 __ int3();
188 }
189
190 void LIR_Assembler::push(LIR_Opr opr) {
191 if (opr->is_single_cpu()) {
192 __ push_reg(opr->as_register());
193 } else if (opr->is_double_cpu()) {
194 NOT_LP64(__ push_reg(opr->as_register_hi()));
195 __ push_reg(opr->as_register_lo());
196 } else if (opr->is_stack()) {
197 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
198 } else if (opr->is_constant()) {
199 LIR_Const* const_opr = opr->as_constant_ptr();
200 if (const_opr->type() == T_OBJECT || const_opr->type() == T_INLINE_TYPE) {
201 __ push_oop(const_opr->as_jobject());
202 } else if (const_opr->type() == T_INT) {
203 __ push_jint(const_opr->as_jint());
204 } else {
205 ShouldNotReachHere();
206 }
207
208 } else {
209 ShouldNotReachHere();
210 }
211 }
212
213 void LIR_Assembler::pop(LIR_Opr opr) {
214 if (opr->is_single_cpu()) {
215 __ pop_reg(opr->as_register());
216 } else {
217 ShouldNotReachHere();
218 }
219 }
220
221 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
222 return addr->base()->is_illegal() && addr->index()->is_illegal();
223 }
224
225 //-------------------------------------------
226
227 Address LIR_Assembler::as_Address(LIR_Address* addr) {
228 return as_Address(addr, rscratch1);
229 }
230
231 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
232 if (addr->base()->is_illegal()) {
233 assert(addr->index()->is_illegal(), "must be illegal too");
234 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
235 if (! __ reachable(laddr)) {
236 __ movptr(tmp, laddr.addr());
237 Address res(tmp, 0);
238 return res;
239 } else {
240 return __ as_Address(laddr);
241 }
242 }
243
244 Register base = addr->base()->as_pointer_register();
245
246 if (addr->index()->is_illegal()) {
247 return Address( base, addr->disp());
248 } else if (addr->index()->is_cpu_register()) {
249 Register index = addr->index()->as_pointer_register();
250 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
251 } else if (addr->index()->is_constant()) {
252 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
253 assert(Assembler::is_simm32(addr_offset), "must be");
254
255 return Address(base, addr_offset);
256 } else {
257 Unimplemented();
258 return Address();
259 }
260 }
261
262
263 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
264 Address base = as_Address(addr);
265 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
266 }
267
268
269 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
270 return as_Address(addr);
271 }
272
273
274 void LIR_Assembler::osr_entry() {
275 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
276 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
277 ValueStack* entry_state = osr_entry->state();
278 int number_of_locks = entry_state->locks_size();
279
280 // we jump here if osr happens with the interpreter
281 // state set up to continue at the beginning of the
282 // loop that triggered osr - in particular, we have
283 // the following registers setup:
284 //
285 // rcx: osr buffer
286 //
287
288 // build frame
289 ciMethod* m = compilation()->method();
290 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
291
292 // OSR buffer is
293 //
294 // locals[nlocals-1..0]
295 // monitors[0..number_of_locks]
296 //
297 // locals is a direct copy of the interpreter frame so in the osr buffer
298 // so first slot in the local array is the last local from the interpreter
299 // and last slot is local[0] (receiver) from the interpreter
300 //
301 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
302 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
303 // in the interpreter frame (the method lock if a sync method)
304
305 // Initialize monitors in the compiled activation.
306 // rcx: pointer to osr buffer
307 //
308 // All other registers are dead at this point and the locals will be
309 // copied into place by code emitted in the IR.
310
311 Register OSR_buf = osrBufferPointer()->as_pointer_register();
312 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
313 int monitor_offset = BytesPerWord * method()->max_locals() +
314 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
315 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
316 // the OSR buffer using 2 word entries: first the lock and then
317 // the oop.
318 for (int i = 0; i < number_of_locks; i++) {
319 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
320 #ifdef ASSERT
321 // verify the interpreter's monitor has a non-null object
322 {
323 Label L;
324 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
325 __ jcc(Assembler::notZero, L);
326 __ stop("locked object is NULL");
327 __ bind(L);
328 }
329 #endif
330 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
331 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
333 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
334 }
335 }
336 }
337
338
339 // inline cache check; done before the frame is built.
340 int LIR_Assembler::check_icache() {
341 Register receiver = FrameMap::receiver_opr->as_register();
342 Register ic_klass = IC_Klass;
343 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
344 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
345 if (!do_post_padding) {
346 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
347 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
348 }
349 int offset = __ offset();
350 __ inline_cache_check(receiver, IC_Klass);
351 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
352 if (do_post_padding) {
353 // force alignment after the cache check.
354 // It's been verified to be aligned if !VerifyOops
355 __ align(CodeEntryAlignment);
356 }
357 return offset;
358 }
359
360 void LIR_Assembler::clinit_barrier(ciMethod* method) {
361 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
362 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
363
364 Label L_skip_barrier;
365 Register klass = rscratch1;
366 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
367 assert(thread != noreg, "x86_32 not implemented");
368
369 __ mov_metadata(klass, method->holder()->constant_encoding());
370 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
371
372 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
373
374 __ bind(L_skip_barrier);
375 }
376
377 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
378 jobject o = NULL;
379 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
380 __ movoop(reg, o);
381 patching_epilog(patch, lir_patch_normal, reg, info);
382 }
383
384 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
385 Metadata* o = NULL;
386 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
387 __ mov_metadata(reg, o);
388 patching_epilog(patch, lir_patch_normal, reg, info);
389 }
390
391 // This specifies the rsp decrement needed to build the frame
392 int LIR_Assembler::initial_frame_size_in_bytes() const {
393 // if rounding, must let FrameMap know!
394
395 // The frame_map records size in slots (32bit word)
396
397 // subtract two words to account for return address and link
398 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
399 }
400
401
402 int LIR_Assembler::emit_exception_handler() {
403 // if the last instruction is a call (typically to do a throw which
404 // is coming at the end after block reordering) the return address
405 // must still point into the code area in order to avoid assertion
406 // failures when searching for the corresponding bci => add a nop
407 // (was bug 5/14/1999 - gri)
408 __ nop();
409
410 // generate code for exception handler
411 address handler_base = __ start_a_stub(exception_handler_size());
412 if (handler_base == NULL) {
413 // not enough space left for the handler
414 bailout("exception handler overflow");
415 return -1;
416 }
417
418 int offset = code_offset();
419
420 // the exception oop and pc are in rax, and rdx
421 // no other registers need to be preserved, so invalidate them
422 __ invalidate_registers(false, true, true, false, true, true);
423
424 // check that there is really an exception
425 __ verify_not_null_oop(rax);
426
427 // search an exception handler (rax: exception oop, rdx: throwing pc)
428 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
429 __ should_not_reach_here();
430 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
431 __ end_a_stub();
432
433 return offset;
434 }
435
436
437 // Emit the code to remove the frame from the stack in the exception
438 // unwind path.
439 int LIR_Assembler::emit_unwind_handler() {
440 #ifndef PRODUCT
441 if (CommentedAssembly) {
442 _masm->block_comment("Unwind handler");
443 }
444 #endif
445
446 int offset = code_offset();
447
448 // Fetch the exception from TLS and clear out exception related thread state
449 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
450 NOT_LP64(__ get_thread(rsi));
451 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
452 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
453 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
454
455 __ bind(_unwind_handler_entry);
456 __ verify_not_null_oop(rax);
457 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
458 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
459 }
460
461 // Preform needed unlocking
462 MonitorExitStub* stub = NULL;
463 if (method()->is_synchronized()) {
464 monitor_address(0, FrameMap::rax_opr);
465 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
466 __ unlock_object(rdi, rsi, rax, *stub->entry());
467 __ bind(*stub->continuation());
468 }
469
470 if (compilation()->env()->dtrace_method_probes()) {
471 #ifdef _LP64
472 __ mov(rdi, r15_thread);
473 __ mov_metadata(rsi, method()->constant_encoding());
474 #else
475 __ get_thread(rax);
476 __ movptr(Address(rsp, 0), rax);
477 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
478 #endif
479 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
480 }
481
482 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
483 __ mov(rax, rbx); // Restore the exception
484 }
485
486 // remove the activation and dispatch to the unwind handler
487 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
488 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
489
490 // Emit the slow path assembly
491 if (stub != NULL) {
492 stub->emit_code(this);
493 }
494
495 return offset;
496 }
497
498
499 int LIR_Assembler::emit_deopt_handler() {
500 // if the last instruction is a call (typically to do a throw which
501 // is coming at the end after block reordering) the return address
502 // must still point into the code area in order to avoid assertion
503 // failures when searching for the corresponding bci => add a nop
504 // (was bug 5/14/1999 - gri)
505 __ nop();
506
507 // generate code for exception handler
508 address handler_base = __ start_a_stub(deopt_handler_size());
509 if (handler_base == NULL) {
510 // not enough space left for the handler
511 bailout("deopt handler overflow");
512 return -1;
513 }
514
515 int offset = code_offset();
516 InternalAddress here(__ pc());
517
518 __ pushptr(here.addr());
519 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
520 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
521 __ end_a_stub();
522
523 return offset;
524 }
525
526 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
527 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
528 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
529 assert(result->fpu() == 0, "result must already be on TOS");
530 }
531
532 ciMethod* method = compilation()->method();
533 if (InlineTypeReturnedAsFields && method->signature()->returns_null_free_inline_type()) {
534 ciInlineKlass* vk = method->return_type()->as_inline_klass();
535 if (vk->can_be_returned_as_fields()) {
536 #ifndef _LP64
537 Unimplemented();
538 #else
539 address unpack_handler = vk->unpack_handler();
540 assert(unpack_handler != NULL, "must be");
541 __ call(RuntimeAddress(unpack_handler));
542 // At this point, rax points to the value object (for interpreter or C1 caller).
543 // The fields of the object are copied into registers (for C2 caller).
544 #endif
545 }
546 }
547
548 // Pop the stack before the safepoint code
549 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
550
551 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
552 __ reserved_stack_check();
553 }
554
555 // Note: we do not need to round double result; float result has the right precision
556 // the poll sets the condition code, but no data registers
557
558 #ifdef _LP64
559 const Register thread = r15_thread;
560 #else
561 const Register thread = rbx;
562 __ get_thread(thread);
563 #endif
564 code_stub->set_safepoint_offset(__ offset());
565 __ relocate(relocInfo::poll_return_type);
566 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
567 __ ret(0);
568 }
569
570
571 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
572 return (__ store_inline_type_fields_to_buf(vk, false));
573 }
574
575 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
576 guarantee(info != NULL, "Shouldn't be NULL");
577 int offset = __ offset();
578 #ifdef _LP64
579 const Register poll_addr = rscratch1;
580 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
581 #else
582 assert(tmp->is_cpu_register(), "needed");
583 const Register poll_addr = tmp->as_register();
584 __ get_thread(poll_addr);
585 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
586 #endif
587 add_debug_info_for_branch(info);
588 __ relocate(relocInfo::poll_type);
589 address pre_pc = __ pc();
590 __ testl(rax, Address(poll_addr, 0));
591 address post_pc = __ pc();
592 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
593 return offset;
594 }
595
596
597 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
598 if (from_reg != to_reg) __ mov(to_reg, from_reg);
599 }
600
601 void LIR_Assembler::swap_reg(Register a, Register b) {
602 __ xchgptr(a, b);
603 }
604
605
606 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
607 assert(src->is_constant(), "should not call otherwise");
608 assert(dest->is_register(), "should not call otherwise");
609 LIR_Const* c = src->as_constant_ptr();
610
611 switch (c->type()) {
612 case T_INT: {
613 assert(patch_code == lir_patch_none, "no patching handled here");
614 __ movl(dest->as_register(), c->as_jint());
615 break;
616 }
617
618 case T_ADDRESS: {
619 assert(patch_code == lir_patch_none, "no patching handled here");
620 __ movptr(dest->as_register(), c->as_jint());
621 break;
622 }
623
624 case T_LONG: {
625 assert(patch_code == lir_patch_none, "no patching handled here");
626 #ifdef _LP64
627 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
628 #else
629 __ movptr(dest->as_register_lo(), c->as_jint_lo());
630 __ movptr(dest->as_register_hi(), c->as_jint_hi());
631 #endif // _LP64
632 break;
633 }
634
635 case T_INLINE_TYPE: // Fall through
636 case T_OBJECT: {
637 if (patch_code != lir_patch_none) {
638 jobject2reg_with_patching(dest->as_register(), info);
639 } else {
640 __ movoop(dest->as_register(), c->as_jobject());
641 }
642 break;
643 }
644
645 case T_METADATA: {
646 if (patch_code != lir_patch_none) {
647 klass2reg_with_patching(dest->as_register(), info);
648 } else {
649 __ mov_metadata(dest->as_register(), c->as_metadata());
650 }
651 break;
652 }
653
654 case T_FLOAT: {
655 if (dest->is_single_xmm()) {
656 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
657 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
658 } else {
659 __ movflt(dest->as_xmm_float_reg(),
660 InternalAddress(float_constant(c->as_jfloat())));
661 }
662 } else {
663 #ifndef _LP64
664 assert(dest->is_single_fpu(), "must be");
665 assert(dest->fpu_regnr() == 0, "dest must be TOS");
666 if (c->is_zero_float()) {
667 __ fldz();
668 } else if (c->is_one_float()) {
669 __ fld1();
670 } else {
671 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
672 }
673 #else
674 ShouldNotReachHere();
675 #endif // !_LP64
676 }
677 break;
678 }
679
680 case T_DOUBLE: {
681 if (dest->is_double_xmm()) {
682 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
683 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
684 } else {
685 __ movdbl(dest->as_xmm_double_reg(),
686 InternalAddress(double_constant(c->as_jdouble())));
687 }
688 } else {
689 #ifndef _LP64
690 assert(dest->is_double_fpu(), "must be");
691 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
692 if (c->is_zero_double()) {
693 __ fldz();
694 } else if (c->is_one_double()) {
695 __ fld1();
696 } else {
697 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
698 }
699 #else
700 ShouldNotReachHere();
701 #endif // !_LP64
702 }
703 break;
704 }
705
706 default:
707 ShouldNotReachHere();
708 }
709 }
710
711 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
712 assert(src->is_constant(), "should not call otherwise");
713 assert(dest->is_stack(), "should not call otherwise");
714 LIR_Const* c = src->as_constant_ptr();
715
716 switch (c->type()) {
717 case T_INT: // fall through
718 case T_FLOAT:
719 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
720 break;
721
722 case T_ADDRESS:
723 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
724 break;
725
726 case T_INLINE_TYPE: // Fall through
727 case T_OBJECT:
728 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
729 break;
730
731 case T_LONG: // fall through
732 case T_DOUBLE:
733 #ifdef _LP64
734 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
735 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
736 #else
737 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
738 lo_word_offset_in_bytes), c->as_jint_lo_bits());
739 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
740 hi_word_offset_in_bytes), c->as_jint_hi_bits());
741 #endif // _LP64
742 break;
743
744 default:
745 ShouldNotReachHere();
746 }
747 }
748
749 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
750 assert(src->is_constant(), "should not call otherwise");
751 assert(dest->is_address(), "should not call otherwise");
752 LIR_Const* c = src->as_constant_ptr();
753 LIR_Address* addr = dest->as_address_ptr();
754
755 int null_check_here = code_offset();
756 switch (type) {
757 case T_INT: // fall through
758 case T_FLOAT:
759 __ movl(as_Address(addr), c->as_jint_bits());
760 break;
761
762 case T_ADDRESS:
763 __ movptr(as_Address(addr), c->as_jint_bits());
764 break;
765
766 case T_INLINE_TYPE: // fall through
767 case T_OBJECT: // fall through
768 case T_ARRAY:
769 if (c->as_jobject() == NULL) {
770 if (UseCompressedOops && !wide) {
771 __ movl(as_Address(addr), (int32_t)NULL_WORD);
772 } else {
773 #ifdef _LP64
774 __ xorptr(rscratch1, rscratch1);
775 null_check_here = code_offset();
776 __ movptr(as_Address(addr), rscratch1);
777 #else
778 __ movptr(as_Address(addr), NULL_WORD);
779 #endif
780 }
781 } else {
782 if (is_literal_address(addr)) {
783 ShouldNotReachHere();
784 __ movoop(as_Address(addr, noreg), c->as_jobject());
785 } else {
786 #ifdef _LP64
787 __ movoop(rscratch1, c->as_jobject());
788 if (UseCompressedOops && !wide) {
789 __ encode_heap_oop(rscratch1);
790 null_check_here = code_offset();
791 __ movl(as_Address_lo(addr), rscratch1);
792 } else {
793 null_check_here = code_offset();
794 __ movptr(as_Address_lo(addr), rscratch1);
795 }
796 #else
797 __ movoop(as_Address(addr), c->as_jobject());
798 #endif
799 }
800 }
801 break;
802
803 case T_LONG: // fall through
804 case T_DOUBLE:
805 #ifdef _LP64
806 if (is_literal_address(addr)) {
807 ShouldNotReachHere();
808 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
809 } else {
810 __ movptr(r10, (intptr_t)c->as_jlong_bits());
811 null_check_here = code_offset();
812 __ movptr(as_Address_lo(addr), r10);
813 }
814 #else
815 // Always reachable in 32bit so this doesn't produce useless move literal
816 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
817 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
818 #endif // _LP64
819 break;
820
821 case T_BOOLEAN: // fall through
822 case T_BYTE:
823 __ movb(as_Address(addr), c->as_jint() & 0xFF);
824 break;
825
826 case T_CHAR: // fall through
827 case T_SHORT:
828 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
829 break;
830
831 default:
832 ShouldNotReachHere();
833 };
834
835 if (info != NULL) {
836 add_debug_info_for_null_check(null_check_here, info);
837 }
838 }
839
840
841 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
842 assert(src->is_register(), "should not call otherwise");
843 assert(dest->is_register(), "should not call otherwise");
844
845 // move between cpu-registers
846 if (dest->is_single_cpu()) {
847 #ifdef _LP64
848 if (src->type() == T_LONG) {
849 // Can do LONG -> OBJECT
850 move_regs(src->as_register_lo(), dest->as_register());
851 return;
852 }
853 #endif
854 assert(src->is_single_cpu(), "must match");
855 if (src->type() == T_OBJECT || src->type() == T_INLINE_TYPE) {
856 __ verify_oop(src->as_register());
857 }
858 move_regs(src->as_register(), dest->as_register());
859
860 } else if (dest->is_double_cpu()) {
861 #ifdef _LP64
862 if (is_reference_type(src->type())) {
863 // Surprising to me but we can see move of a long to t_object
864 __ verify_oop(src->as_register());
865 move_regs(src->as_register(), dest->as_register_lo());
866 return;
867 }
868 #endif
869 assert(src->is_double_cpu(), "must match");
870 Register f_lo = src->as_register_lo();
871 Register f_hi = src->as_register_hi();
872 Register t_lo = dest->as_register_lo();
873 Register t_hi = dest->as_register_hi();
874 #ifdef _LP64
875 assert(f_hi == f_lo, "must be same");
876 assert(t_hi == t_lo, "must be same");
877 move_regs(f_lo, t_lo);
878 #else
879 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
880
881
882 if (f_lo == t_hi && f_hi == t_lo) {
883 swap_reg(f_lo, f_hi);
884 } else if (f_hi == t_lo) {
885 assert(f_lo != t_hi, "overwriting register");
886 move_regs(f_hi, t_hi);
887 move_regs(f_lo, t_lo);
888 } else {
889 assert(f_hi != t_lo, "overwriting register");
890 move_regs(f_lo, t_lo);
891 move_regs(f_hi, t_hi);
892 }
893 #endif // LP64
894
895 #ifndef _LP64
896 // special moves from fpu-register to xmm-register
897 // necessary for method results
898 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
899 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
900 __ fld_s(Address(rsp, 0));
901 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
902 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
903 __ fld_d(Address(rsp, 0));
904 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
905 __ fstp_s(Address(rsp, 0));
906 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
907 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
908 __ fstp_d(Address(rsp, 0));
909 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
910 #endif // !_LP64
911
912 // move between xmm-registers
913 } else if (dest->is_single_xmm()) {
914 assert(src->is_single_xmm(), "must match");
915 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
916 } else if (dest->is_double_xmm()) {
917 assert(src->is_double_xmm(), "must match");
918 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
919
920 #ifndef _LP64
921 // move between fpu-registers (no instruction necessary because of fpu-stack)
922 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
923 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
924 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
925 #endif // !_LP64
926
927 } else {
928 ShouldNotReachHere();
929 }
930 }
931
932 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
933 assert(src->is_register(), "should not call otherwise");
934 assert(dest->is_stack(), "should not call otherwise");
935
936 if (src->is_single_cpu()) {
937 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
938 if (is_reference_type(type)) {
939 __ verify_oop(src->as_register());
940 __ movptr (dst, src->as_register());
941 } else if (type == T_METADATA || type == T_ADDRESS) {
942 __ movptr (dst, src->as_register());
943 } else {
944 __ movl (dst, src->as_register());
945 }
946
947 } else if (src->is_double_cpu()) {
948 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
949 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
950 __ movptr (dstLO, src->as_register_lo());
951 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
952
953 } else if (src->is_single_xmm()) {
954 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
955 __ movflt(dst_addr, src->as_xmm_float_reg());
956
957 } else if (src->is_double_xmm()) {
958 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
959 __ movdbl(dst_addr, src->as_xmm_double_reg());
960
961 #ifndef _LP64
962 } else if (src->is_single_fpu()) {
963 assert(src->fpu_regnr() == 0, "argument must be on TOS");
964 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
965 if (pop_fpu_stack) __ fstp_s (dst_addr);
966 else __ fst_s (dst_addr);
967
968 } else if (src->is_double_fpu()) {
969 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
970 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
971 if (pop_fpu_stack) __ fstp_d (dst_addr);
972 else __ fst_d (dst_addr);
973 #endif // !_LP64
974
975 } else {
976 ShouldNotReachHere();
977 }
978 }
979
980
981 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
982 LIR_Address* to_addr = dest->as_address_ptr();
983 PatchingStub* patch = NULL;
984 Register compressed_src = rscratch1;
985
986 if (is_reference_type(type)) {
987 __ verify_oop(src->as_register());
988 #ifdef _LP64
989 if (UseCompressedOops && !wide) {
990 __ movptr(compressed_src, src->as_register());
991 __ encode_heap_oop(compressed_src);
992 if (patch_code != lir_patch_none) {
993 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
994 }
995 }
996 #endif
997 }
998
999 if (patch_code != lir_patch_none) {
1000 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1001 Address toa = as_Address(to_addr);
1002 assert(toa.disp() != 0, "must have");
1003 }
1004
1005 int null_check_here = code_offset();
1006 switch (type) {
1007 case T_FLOAT: {
1008 #ifdef _LP64
1009 assert(src->is_single_xmm(), "not a float");
1010 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1011 #else
1012 if (src->is_single_xmm()) {
1013 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1014 } else {
1015 assert(src->is_single_fpu(), "must be");
1016 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1017 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1018 else __ fst_s (as_Address(to_addr));
1019 }
1020 #endif // _LP64
1021 break;
1022 }
1023
1024 case T_DOUBLE: {
1025 #ifdef _LP64
1026 assert(src->is_double_xmm(), "not a double");
1027 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1028 #else
1029 if (src->is_double_xmm()) {
1030 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1031 } else {
1032 assert(src->is_double_fpu(), "must be");
1033 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1034 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1035 else __ fst_d (as_Address(to_addr));
1036 }
1037 #endif // _LP64
1038 break;
1039 }
1040
1041 case T_INLINE_TYPE: // fall through
1042 case T_ARRAY: // fall through
1043 case T_OBJECT: // fall through
1044 if (UseCompressedOops && !wide) {
1045 __ movl(as_Address(to_addr), compressed_src);
1046 } else {
1047 __ movptr(as_Address(to_addr), src->as_register());
1048 }
1049 break;
1050 case T_METADATA:
1051 // We get here to store a method pointer to the stack to pass to
1052 // a dtrace runtime call. This can't work on 64 bit with
1053 // compressed klass ptrs: T_METADATA can be a compressed klass
1054 // ptr or a 64 bit method pointer.
1055 LP64_ONLY(ShouldNotReachHere());
1056 __ movptr(as_Address(to_addr), src->as_register());
1057 break;
1058 case T_ADDRESS:
1059 __ movptr(as_Address(to_addr), src->as_register());
1060 break;
1061 case T_INT:
1062 __ movl(as_Address(to_addr), src->as_register());
1063 break;
1064
1065 case T_LONG: {
1066 Register from_lo = src->as_register_lo();
1067 Register from_hi = src->as_register_hi();
1068 #ifdef _LP64
1069 __ movptr(as_Address_lo(to_addr), from_lo);
1070 #else
1071 Register base = to_addr->base()->as_register();
1072 Register index = noreg;
1073 if (to_addr->index()->is_register()) {
1074 index = to_addr->index()->as_register();
1075 }
1076 if (base == from_lo || index == from_lo) {
1077 assert(base != from_hi, "can't be");
1078 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1079 __ movl(as_Address_hi(to_addr), from_hi);
1080 if (patch != NULL) {
1081 patching_epilog(patch, lir_patch_high, base, info);
1082 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1083 patch_code = lir_patch_low;
1084 }
1085 __ movl(as_Address_lo(to_addr), from_lo);
1086 } else {
1087 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1088 __ movl(as_Address_lo(to_addr), from_lo);
1089 if (patch != NULL) {
1090 patching_epilog(patch, lir_patch_low, base, info);
1091 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1092 patch_code = lir_patch_high;
1093 }
1094 __ movl(as_Address_hi(to_addr), from_hi);
1095 }
1096 #endif // _LP64
1097 break;
1098 }
1099
1100 case T_BYTE: // fall through
1101 case T_BOOLEAN: {
1102 Register src_reg = src->as_register();
1103 Address dst_addr = as_Address(to_addr);
1104 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1105 __ movb(dst_addr, src_reg);
1106 break;
1107 }
1108
1109 case T_CHAR: // fall through
1110 case T_SHORT:
1111 __ movw(as_Address(to_addr), src->as_register());
1112 break;
1113
1114 default:
1115 ShouldNotReachHere();
1116 }
1117 if (info != NULL) {
1118 add_debug_info_for_null_check(null_check_here, info);
1119 }
1120
1121 if (patch_code != lir_patch_none) {
1122 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1123 }
1124 }
1125
1126
1127 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1128 assert(src->is_stack(), "should not call otherwise");
1129 assert(dest->is_register(), "should not call otherwise");
1130
1131 if (dest->is_single_cpu()) {
1132 if (is_reference_type(type)) {
1133 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1134 __ verify_oop(dest->as_register());
1135 } else if (type == T_METADATA || type == T_ADDRESS) {
1136 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1137 } else {
1138 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1139 }
1140
1141 } else if (dest->is_double_cpu()) {
1142 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1143 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1144 __ movptr(dest->as_register_lo(), src_addr_LO);
1145 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1146
1147 } else if (dest->is_single_xmm()) {
1148 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1149 __ movflt(dest->as_xmm_float_reg(), src_addr);
1150
1151 } else if (dest->is_double_xmm()) {
1152 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1153 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1154
1155 #ifndef _LP64
1156 } else if (dest->is_single_fpu()) {
1157 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1158 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1159 __ fld_s(src_addr);
1160
1161 } else if (dest->is_double_fpu()) {
1162 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1163 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1164 __ fld_d(src_addr);
1165 #endif // _LP64
1166
1167 } else {
1168 ShouldNotReachHere();
1169 }
1170 }
1171
1172
1173 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1174 if (src->is_single_stack()) {
1175 if (is_reference_type(type)) {
1176 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1177 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1178 } else {
1179 #ifndef _LP64
1180 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1181 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1182 #else
1183 //no pushl on 64bits
1184 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1185 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1186 #endif
1187 }
1188
1189 } else if (src->is_double_stack()) {
1190 #ifdef _LP64
1191 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1192 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1193 #else
1194 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1195 // push and pop the part at src + wordSize, adding wordSize for the previous push
1196 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1197 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1198 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1199 #endif // _LP64
1200
1201 } else {
1202 ShouldNotReachHere();
1203 }
1204 }
1205
1206
1207 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1208 assert(src->is_address(), "should not call otherwise");
1209 assert(dest->is_register(), "should not call otherwise");
1210
1211 LIR_Address* addr = src->as_address_ptr();
1212 Address from_addr = as_Address(addr);
1213 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1214
1215 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_INLINE_TYPE) {
1216 __ verify_oop(addr->base()->as_pointer_register());
1217 }
1218
1219 switch (type) {
1220 case T_BOOLEAN: // fall through
1221 case T_BYTE: // fall through
1222 case T_CHAR: // fall through
1223 case T_SHORT:
1224 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1225 // on pre P6 processors we may get partial register stalls
1226 // so blow away the value of to_rinfo before loading a
1227 // partial word into it. Do it here so that it precedes
1228 // the potential patch point below.
1229 __ xorptr(dest->as_register(), dest->as_register());
1230 }
1231 break;
1232 default:
1233 break;
1234 }
1235
1236 PatchingStub* patch = NULL;
1237 if (patch_code != lir_patch_none) {
1238 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1239 assert(from_addr.disp() != 0, "must have");
1240 }
1241 if (info != NULL) {
1242 add_debug_info_for_null_check_here(info);
1243 }
1244
1245 switch (type) {
1246 case T_FLOAT: {
1247 if (dest->is_single_xmm()) {
1248 __ movflt(dest->as_xmm_float_reg(), from_addr);
1249 } else {
1250 #ifndef _LP64
1251 assert(dest->is_single_fpu(), "must be");
1252 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1253 __ fld_s(from_addr);
1254 #else
1255 ShouldNotReachHere();
1256 #endif // !LP64
1257 }
1258 break;
1259 }
1260
1261 case T_DOUBLE: {
1262 if (dest->is_double_xmm()) {
1263 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1264 } else {
1265 #ifndef _LP64
1266 assert(dest->is_double_fpu(), "must be");
1267 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1268 __ fld_d(from_addr);
1269 #else
1270 ShouldNotReachHere();
1271 #endif // !LP64
1272 }
1273 break;
1274 }
1275
1276 case T_INLINE_TYPE: // fall through
1277 case T_OBJECT: // fall through
1278 case T_ARRAY: // fall through
1279 if (UseCompressedOops && !wide) {
1280 __ movl(dest->as_register(), from_addr);
1281 } else {
1282 __ movptr(dest->as_register(), from_addr);
1283 }
1284 break;
1285
1286 case T_ADDRESS:
1287 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1288 __ movl(dest->as_register(), from_addr);
1289 } else {
1290 __ movptr(dest->as_register(), from_addr);
1291 }
1292 break;
1293 case T_INT:
1294 __ movl(dest->as_register(), from_addr);
1295 break;
1296
1297 case T_LONG: {
1298 Register to_lo = dest->as_register_lo();
1299 Register to_hi = dest->as_register_hi();
1300 #ifdef _LP64
1301 __ movptr(to_lo, as_Address_lo(addr));
1302 #else
1303 Register base = addr->base()->as_register();
1304 Register index = noreg;
1305 if (addr->index()->is_register()) {
1306 index = addr->index()->as_register();
1307 }
1308 if ((base == to_lo && index == to_hi) ||
1309 (base == to_hi && index == to_lo)) {
1310 // addresses with 2 registers are only formed as a result of
1311 // array access so this code will never have to deal with
1312 // patches or null checks.
1313 assert(info == NULL && patch == NULL, "must be");
1314 __ lea(to_hi, as_Address(addr));
1315 __ movl(to_lo, Address(to_hi, 0));
1316 __ movl(to_hi, Address(to_hi, BytesPerWord));
1317 } else if (base == to_lo || index == to_lo) {
1318 assert(base != to_hi, "can't be");
1319 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1320 __ movl(to_hi, as_Address_hi(addr));
1321 if (patch != NULL) {
1322 patching_epilog(patch, lir_patch_high, base, info);
1323 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1324 patch_code = lir_patch_low;
1325 }
1326 __ movl(to_lo, as_Address_lo(addr));
1327 } else {
1328 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1329 __ movl(to_lo, as_Address_lo(addr));
1330 if (patch != NULL) {
1331 patching_epilog(patch, lir_patch_low, base, info);
1332 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1333 patch_code = lir_patch_high;
1334 }
1335 __ movl(to_hi, as_Address_hi(addr));
1336 }
1337 #endif // _LP64
1338 break;
1339 }
1340
1341 case T_BOOLEAN: // fall through
1342 case T_BYTE: {
1343 Register dest_reg = dest->as_register();
1344 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1345 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1346 __ movsbl(dest_reg, from_addr);
1347 } else {
1348 __ movb(dest_reg, from_addr);
1349 __ shll(dest_reg, 24);
1350 __ sarl(dest_reg, 24);
1351 }
1352 break;
1353 }
1354
1355 case T_CHAR: {
1356 Register dest_reg = dest->as_register();
1357 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1358 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1359 __ movzwl(dest_reg, from_addr);
1360 } else {
1361 __ movw(dest_reg, from_addr);
1362 }
1363 break;
1364 }
1365
1366 case T_SHORT: {
1367 Register dest_reg = dest->as_register();
1368 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1369 __ movswl(dest_reg, from_addr);
1370 } else {
1371 __ movw(dest_reg, from_addr);
1372 __ shll(dest_reg, 16);
1373 __ sarl(dest_reg, 16);
1374 }
1375 break;
1376 }
1377
1378 default:
1379 ShouldNotReachHere();
1380 }
1381
1382 if (patch != NULL) {
1383 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1384 }
1385
1386 if (is_reference_type(type)) {
1387 #ifdef _LP64
1388 if (UseCompressedOops && !wide) {
1389 __ decode_heap_oop(dest->as_register());
1390 }
1391 #endif
1392
1393 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1394 if (!UseZGC) {
1395 __ verify_oop(dest->as_register());
1396 }
1397 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1398 #ifdef _LP64
1399 if (UseCompressedClassPointers) {
1400 __ decode_klass_not_null(dest->as_register(), tmp_load_klass);
1401 }
1402 #endif
1403 }
1404 }
1405
1406
1407 NEEDS_CLEANUP; // This could be static?
1408 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1409 int elem_size = type2aelembytes(type);
1410 switch (elem_size) {
1411 case 1: return Address::times_1;
1412 case 2: return Address::times_2;
1413 case 4: return Address::times_4;
1414 case 8: return Address::times_8;
1415 }
1416 ShouldNotReachHere();
1417 return Address::no_scale;
1418 }
1419
1420
1421 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1422 switch (op->code()) {
1423 case lir_idiv:
1424 case lir_irem:
1425 arithmetic_idiv(op->code(),
1426 op->in_opr1(),
1427 op->in_opr2(),
1428 op->in_opr3(),
1429 op->result_opr(),
1430 op->info());
1431 break;
1432 case lir_fmad:
1433 __ fmad(op->result_opr()->as_xmm_double_reg(),
1434 op->in_opr1()->as_xmm_double_reg(),
1435 op->in_opr2()->as_xmm_double_reg(),
1436 op->in_opr3()->as_xmm_double_reg());
1437 break;
1438 case lir_fmaf:
1439 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1440 op->in_opr1()->as_xmm_float_reg(),
1441 op->in_opr2()->as_xmm_float_reg(),
1442 op->in_opr3()->as_xmm_float_reg());
1443 break;
1444 default: ShouldNotReachHere(); break;
1445 }
1446 }
1447
1448 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1449 #ifdef ASSERT
1450 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1451 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1452 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1453 #endif
1454
1455 if (op->cond() == lir_cond_always) {
1456 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1457 __ jmp (*(op->label()));
1458 } else {
1459 Assembler::Condition acond = Assembler::zero;
1460 if (op->code() == lir_cond_float_branch) {
1461 assert(op->ublock() != NULL, "must have unordered successor");
1462 __ jcc(Assembler::parity, *(op->ublock()->label()));
1463 switch(op->cond()) {
1464 case lir_cond_equal: acond = Assembler::equal; break;
1465 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1466 case lir_cond_less: acond = Assembler::below; break;
1467 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1468 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1469 case lir_cond_greater: acond = Assembler::above; break;
1470 default: ShouldNotReachHere();
1471 }
1472 } else {
1473 switch (op->cond()) {
1474 case lir_cond_equal: acond = Assembler::equal; break;
1475 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1476 case lir_cond_less: acond = Assembler::less; break;
1477 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1478 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1479 case lir_cond_greater: acond = Assembler::greater; break;
1480 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1481 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1482 default: ShouldNotReachHere();
1483 }
1484 }
1485 __ jcc(acond,*(op->label()));
1486 }
1487 }
1488
1489 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1490 LIR_Opr src = op->in_opr();
1491 LIR_Opr dest = op->result_opr();
1492
1493 switch (op->bytecode()) {
1494 case Bytecodes::_i2l:
1495 #ifdef _LP64
1496 __ movl2ptr(dest->as_register_lo(), src->as_register());
1497 #else
1498 move_regs(src->as_register(), dest->as_register_lo());
1499 move_regs(src->as_register(), dest->as_register_hi());
1500 __ sarl(dest->as_register_hi(), 31);
1501 #endif // LP64
1502 break;
1503
1504 case Bytecodes::_l2i:
1505 #ifdef _LP64
1506 __ movl(dest->as_register(), src->as_register_lo());
1507 #else
1508 move_regs(src->as_register_lo(), dest->as_register());
1509 #endif
1510 break;
1511
1512 case Bytecodes::_i2b:
1513 move_regs(src->as_register(), dest->as_register());
1514 __ sign_extend_byte(dest->as_register());
1515 break;
1516
1517 case Bytecodes::_i2c:
1518 move_regs(src->as_register(), dest->as_register());
1519 __ andl(dest->as_register(), 0xFFFF);
1520 break;
1521
1522 case Bytecodes::_i2s:
1523 move_regs(src->as_register(), dest->as_register());
1524 __ sign_extend_short(dest->as_register());
1525 break;
1526
1527
1528 #ifdef _LP64
1529 case Bytecodes::_f2d:
1530 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1531 break;
1532
1533 case Bytecodes::_d2f:
1534 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1535 break;
1536
1537 case Bytecodes::_i2f:
1538 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1539 break;
1540
1541 case Bytecodes::_i2d:
1542 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1543 break;
1544
1545 case Bytecodes::_l2f:
1546 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1547 break;
1548
1549 case Bytecodes::_l2d:
1550 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1551 break;
1552
1553 case Bytecodes::_f2i:
1554 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1555 break;
1556
1557 case Bytecodes::_d2i:
1558 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1559 break;
1560
1561 case Bytecodes::_f2l:
1562 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1563 break;
1564
1565 case Bytecodes::_d2l:
1566 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1567 break;
1568 #else
1569 case Bytecodes::_f2d:
1570 case Bytecodes::_d2f:
1571 if (dest->is_single_xmm()) {
1572 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1573 } else if (dest->is_double_xmm()) {
1574 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1575 } else {
1576 assert(src->fpu() == dest->fpu(), "register must be equal");
1577 // do nothing (float result is rounded later through spilling)
1578 }
1579 break;
1580
1581 case Bytecodes::_i2f:
1582 case Bytecodes::_i2d:
1583 if (dest->is_single_xmm()) {
1584 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1585 } else if (dest->is_double_xmm()) {
1586 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1587 } else {
1588 assert(dest->fpu() == 0, "result must be on TOS");
1589 __ movl(Address(rsp, 0), src->as_register());
1590 __ fild_s(Address(rsp, 0));
1591 }
1592 break;
1593
1594 case Bytecodes::_l2f:
1595 case Bytecodes::_l2d:
1596 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1597 assert(dest->fpu() == 0, "result must be on TOS");
1598 __ movptr(Address(rsp, 0), src->as_register_lo());
1599 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1600 __ fild_d(Address(rsp, 0));
1601 // float result is rounded later through spilling
1602 break;
1603
1604 case Bytecodes::_f2i:
1605 case Bytecodes::_d2i:
1606 if (src->is_single_xmm()) {
1607 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1608 } else if (src->is_double_xmm()) {
1609 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1610 } else {
1611 assert(src->fpu() == 0, "input must be on TOS");
1612 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1613 __ fist_s(Address(rsp, 0));
1614 __ movl(dest->as_register(), Address(rsp, 0));
1615 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1616 }
1617 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1618 assert(op->stub() != NULL, "stub required");
1619 __ cmpl(dest->as_register(), 0x80000000);
1620 __ jcc(Assembler::equal, *op->stub()->entry());
1621 __ bind(*op->stub()->continuation());
1622 break;
1623
1624 case Bytecodes::_f2l:
1625 case Bytecodes::_d2l:
1626 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1627 assert(src->fpu() == 0, "input must be on TOS");
1628 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1629
1630 // instruction sequence too long to inline it here
1631 {
1632 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1633 }
1634 break;
1635 #endif // _LP64
1636
1637 default: ShouldNotReachHere();
1638 }
1639 }
1640
1641 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1642 if (op->init_check()) {
1643 add_debug_info_for_null_check_here(op->stub()->info());
1644 __ cmpb(Address(op->klass()->as_register(),
1645 InstanceKlass::init_state_offset()),
1646 InstanceKlass::fully_initialized);
1647 __ jcc(Assembler::notEqual, *op->stub()->entry());
1648 }
1649 __ allocate_object(op->obj()->as_register(),
1650 op->tmp1()->as_register(),
1651 op->tmp2()->as_register(),
1652 op->header_size(),
1653 op->object_size(),
1654 op->klass()->as_register(),
1655 *op->stub()->entry());
1656 __ bind(*op->stub()->continuation());
1657 }
1658
1659 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1660 Register len = op->len()->as_register();
1661 LP64_ONLY( __ movslq(len, len); )
1662
1663 if (UseSlowPath || op->type() == T_INLINE_TYPE ||
1664 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1665 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1666 __ jmp(*op->stub()->entry());
1667 } else {
1668 Register tmp1 = op->tmp1()->as_register();
1669 Register tmp2 = op->tmp2()->as_register();
1670 Register tmp3 = op->tmp3()->as_register();
1671 if (len == tmp1) {
1672 tmp1 = tmp3;
1673 } else if (len == tmp2) {
1674 tmp2 = tmp3;
1675 } else if (len == tmp3) {
1676 // everything is ok
1677 } else {
1678 __ mov(tmp3, len);
1679 }
1680 __ allocate_array(op->obj()->as_register(),
1681 len,
1682 tmp1,
1683 tmp2,
1684 arrayOopDesc::header_size(op->type()),
1685 array_element_size(op->type()),
1686 op->klass()->as_register(),
1687 *op->stub()->entry());
1688 }
1689 __ bind(*op->stub()->continuation());
1690 }
1691
1692 void LIR_Assembler::type_profile_helper(Register mdo,
1693 ciMethodData *md, ciProfileData *data,
1694 Register recv, Label* update_done) {
1695 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1696 Label next_test;
1697 // See if the receiver is receiver[n].
1698 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1699 __ jccb(Assembler::notEqual, next_test);
1700 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1701 __ addptr(data_addr, DataLayout::counter_increment);
1702 __ jmp(*update_done);
1703 __ bind(next_test);
1704 }
1705
1706 // Didn't find receiver; find next empty slot and fill it in
1707 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1708 Label next_test;
1709 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1710 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1711 __ jccb(Assembler::notEqual, next_test);
1712 __ movptr(recv_addr, recv);
1713 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1714 __ jmp(*update_done);
1715 __ bind(next_test);
1716 }
1717 }
1718
1719 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1720 // we always need a stub for the failure case.
1721 CodeStub* stub = op->stub();
1722 Register obj = op->object()->as_register();
1723 Register k_RInfo = op->tmp1()->as_register();
1724 Register klass_RInfo = op->tmp2()->as_register();
1725 Register dst = op->result_opr()->as_register();
1726 ciKlass* k = op->klass();
1727 Register Rtmp1 = noreg;
1728 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1729
1730 // check if it needs to be profiled
1731 ciMethodData* md = NULL;
1732 ciProfileData* data = NULL;
1733
1734 if (op->should_profile()) {
1735 ciMethod* method = op->profiled_method();
1736 assert(method != NULL, "Should have method");
1737 int bci = op->profiled_bci();
1738 md = method->method_data_or_null();
1739 assert(md != NULL, "Sanity");
1740 data = md->bci_to_data(bci);
1741 assert(data != NULL, "need data for type check");
1742 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1743 }
1744 Label profile_cast_success, profile_cast_failure;
1745 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1746 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1747
1748 if (obj == k_RInfo) {
1749 k_RInfo = dst;
1750 } else if (obj == klass_RInfo) {
1751 klass_RInfo = dst;
1752 }
1753 if (k->is_loaded() && !UseCompressedClassPointers) {
1754 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1755 } else {
1756 Rtmp1 = op->tmp3()->as_register();
1757 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1758 }
1759
1760 assert_different_registers(obj, k_RInfo, klass_RInfo);
1761
1762 if (op->need_null_check()) {
1763 __ cmpptr(obj, (int32_t)NULL_WORD);
1764 if (op->should_profile()) {
1765 Label not_null;
1766 __ jccb(Assembler::notEqual, not_null);
1767 // Object is null; update MDO and exit
1768 Register mdo = klass_RInfo;
1769 __ mov_metadata(mdo, md->constant_encoding());
1770 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1771 int header_bits = BitData::null_seen_byte_constant();
1772 __ orb(data_addr, header_bits);
1773 __ jmp(*obj_is_null);
1774 __ bind(not_null);
1775 } else {
1776 __ jcc(Assembler::equal, *obj_is_null);
1777 }
1778 }
1779
1780 if (!k->is_loaded()) {
1781 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1782 } else {
1783 #ifdef _LP64
1784 __ mov_metadata(k_RInfo, k->constant_encoding());
1785 #endif // _LP64
1786 }
1787 __ verify_oop(obj);
1788
1789 if (op->fast_check()) {
1790 // get object class
1791 // not a safepoint as obj null check happens earlier
1792 #ifdef _LP64
1793 if (UseCompressedClassPointers) {
1794 __ load_klass(Rtmp1, obj, tmp_load_klass);
1795 __ cmpptr(k_RInfo, Rtmp1);
1796 } else {
1797 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1798 }
1799 #else
1800 if (k->is_loaded()) {
1801 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1802 } else {
1803 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1804 }
1805 #endif
1806 __ jcc(Assembler::notEqual, *failure_target);
1807 // successful cast, fall through to profile or jump
1808 } else {
1809 // get object class
1810 // not a safepoint as obj null check happens earlier
1811 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1812 if (k->is_loaded()) {
1813 // See if we get an immediate positive hit
1814 #ifdef _LP64
1815 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1816 #else
1817 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1818 #endif // _LP64
1819 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1820 __ jcc(Assembler::notEqual, *failure_target);
1821 // successful cast, fall through to profile or jump
1822 } else {
1823 // See if we get an immediate positive hit
1824 __ jcc(Assembler::equal, *success_target);
1825 // check for self
1826 #ifdef _LP64
1827 __ cmpptr(klass_RInfo, k_RInfo);
1828 #else
1829 __ cmpklass(klass_RInfo, k->constant_encoding());
1830 #endif // _LP64
1831 __ jcc(Assembler::equal, *success_target);
1832
1833 __ push(klass_RInfo);
1834 #ifdef _LP64
1835 __ push(k_RInfo);
1836 #else
1837 __ pushklass(k->constant_encoding());
1838 #endif // _LP64
1839 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1840 __ pop(klass_RInfo);
1841 __ pop(klass_RInfo);
1842 // result is a boolean
1843 __ cmpl(klass_RInfo, 0);
1844 __ jcc(Assembler::equal, *failure_target);
1845 // successful cast, fall through to profile or jump
1846 }
1847 } else {
1848 // perform the fast part of the checking logic
1849 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1850 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1851 __ push(klass_RInfo);
1852 __ push(k_RInfo);
1853 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1854 __ pop(klass_RInfo);
1855 __ pop(k_RInfo);
1856 // result is a boolean
1857 __ cmpl(k_RInfo, 0);
1858 __ jcc(Assembler::equal, *failure_target);
1859 // successful cast, fall through to profile or jump
1860 }
1861 }
1862 if (op->should_profile()) {
1863 Register mdo = klass_RInfo, recv = k_RInfo;
1864 __ bind(profile_cast_success);
1865 __ mov_metadata(mdo, md->constant_encoding());
1866 __ load_klass(recv, obj, tmp_load_klass);
1867 type_profile_helper(mdo, md, data, recv, success);
1868 __ jmp(*success);
1869
1870 __ bind(profile_cast_failure);
1871 __ mov_metadata(mdo, md->constant_encoding());
1872 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1873 __ subptr(counter_addr, DataLayout::counter_increment);
1874 __ jmp(*failure);
1875 }
1876 __ jmp(*success);
1877 }
1878
1879
1880 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1881 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1882 LIR_Code code = op->code();
1883 if (code == lir_store_check) {
1884 Register value = op->object()->as_register();
1885 Register array = op->array()->as_register();
1886 Register k_RInfo = op->tmp1()->as_register();
1887 Register klass_RInfo = op->tmp2()->as_register();
1888 Register Rtmp1 = op->tmp3()->as_register();
1889
1890 CodeStub* stub = op->stub();
1891
1892 // check if it needs to be profiled
1893 ciMethodData* md = NULL;
1894 ciProfileData* data = NULL;
1895
1896 if (op->should_profile()) {
1897 ciMethod* method = op->profiled_method();
1898 assert(method != NULL, "Should have method");
1899 int bci = op->profiled_bci();
1900 md = method->method_data_or_null();
1901 assert(md != NULL, "Sanity");
1902 data = md->bci_to_data(bci);
1903 assert(data != NULL, "need data for type check");
1904 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1905 }
1906 Label profile_cast_success, profile_cast_failure, done;
1907 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1908 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1909
1910 __ cmpptr(value, (int32_t)NULL_WORD);
1911 if (op->should_profile()) {
1912 Label not_null;
1913 __ jccb(Assembler::notEqual, not_null);
1914 // Object is null; update MDO and exit
1915 Register mdo = klass_RInfo;
1916 __ mov_metadata(mdo, md->constant_encoding());
1917 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1918 int header_bits = BitData::null_seen_byte_constant();
1919 __ orb(data_addr, header_bits);
1920 __ jmp(done);
1921 __ bind(not_null);
1922 } else {
1923 __ jcc(Assembler::equal, done);
1924 }
1925
1926 add_debug_info_for_null_check_here(op->info_for_exception());
1927 __ load_klass(k_RInfo, array, tmp_load_klass);
1928 __ load_klass(klass_RInfo, value, tmp_load_klass);
1929
1930 // get instance klass (it's already uncompressed)
1931 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1932 // perform the fast part of the checking logic
1933 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1934 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1935 __ push(klass_RInfo);
1936 __ push(k_RInfo);
1937 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1938 __ pop(klass_RInfo);
1939 __ pop(k_RInfo);
1940 // result is a boolean
1941 __ cmpl(k_RInfo, 0);
1942 __ jcc(Assembler::equal, *failure_target);
1943 // fall through to the success case
1944
1945 if (op->should_profile()) {
1946 Register mdo = klass_RInfo, recv = k_RInfo;
1947 __ bind(profile_cast_success);
1948 __ mov_metadata(mdo, md->constant_encoding());
1949 __ load_klass(recv, value, tmp_load_klass);
1950 type_profile_helper(mdo, md, data, recv, &done);
1951 __ jmpb(done);
1952
1953 __ bind(profile_cast_failure);
1954 __ mov_metadata(mdo, md->constant_encoding());
1955 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1956 __ subptr(counter_addr, DataLayout::counter_increment);
1957 __ jmp(*stub->entry());
1958 }
1959
1960 __ bind(done);
1961 } else
1962 if (code == lir_checkcast) {
1963 Register obj = op->object()->as_register();
1964 Register dst = op->result_opr()->as_register();
1965 Label success;
1966 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1967 __ bind(success);
1968 if (dst != obj) {
1969 __ mov(dst, obj);
1970 }
1971 } else
1972 if (code == lir_instanceof) {
1973 Register obj = op->object()->as_register();
1974 Register dst = op->result_opr()->as_register();
1975 Label success, failure, done;
1976 emit_typecheck_helper(op, &success, &failure, &failure);
1977 __ bind(failure);
1978 __ xorptr(dst, dst);
1979 __ jmpb(done);
1980 __ bind(success);
1981 __ movptr(dst, 1);
1982 __ bind(done);
1983 } else {
1984 ShouldNotReachHere();
1985 }
1986
1987 }
1988
1989 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1990 // We are loading/storing from/to an array that *may* be flattened (the
1991 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1992 // If this array is flattened, take the slow path.
1993 Register klass = op->tmp()->as_register();
1994 if (UseArrayMarkWordCheck) {
1995 __ test_flattened_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1996 } else {
1997 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1998 __ load_klass(klass, op->array()->as_register(), tmp_load_klass);
1999 __ movl(klass, Address(klass, Klass::layout_helper_offset()));
2000 __ testl(klass, Klass::_lh_array_tag_flat_value_bit_inplace);
2001 __ jcc(Assembler::notZero, *op->stub()->entry());
2002 }
2003 if (!op->value()->is_illegal()) {
2004 // The array is not flattened, but it might be null-free. If we are storing
2005 // a null into a null-free array, take the slow path (which will throw NPE).
2006 Label skip;
2007 __ cmpptr(op->value()->as_register(), (int32_t)NULL_WORD);
2008 __ jcc(Assembler::notEqual, skip);
2009 if (UseArrayMarkWordCheck) {
2010 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
2011 } else {
2012 __ testl(klass, Klass::_lh_null_free_array_bit_inplace);
2013 __ jcc(Assembler::notZero, *op->stub()->entry());
2014 }
2015 __ bind(skip);
2016 }
2017 }
2018
2019 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
2020 // We are storing into an array that *may* be null-free (the declared type is
2021 // Object[], abstract[], interface[] or VT.ref[]).
2022 if (UseArrayMarkWordCheck) {
2023 Label test_mark_word;
2024 Register tmp = op->tmp()->as_register();
2025 __ movptr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
2026 __ testl(tmp, markWord::unlocked_value);
2027 __ jccb(Assembler::notZero, test_mark_word);
2028 __ load_prototype_header(tmp, op->array()->as_register(), rscratch1);
2029 __ bind(test_mark_word);
2030 __ testl(tmp, markWord::null_free_array_bit_in_place);
2031 } else {
2032 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
2033 Register klass = op->tmp()->as_register();
2034 __ load_klass(klass, op->array()->as_register(), tmp_load_klass);
2035 __ movl(klass, Address(klass, Klass::layout_helper_offset()));
2036 __ testl(klass, Klass::_lh_null_free_array_bit_inplace);
2037 }
2038 }
2039
2040 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
2041 Label L_oops_equal;
2042 Label L_oops_not_equal;
2043 Label L_end;
2044
2045 Register left = op->left()->as_register();
2046 Register right = op->right()->as_register();
2047
2048 __ cmpptr(left, right);
2049 __ jcc(Assembler::equal, L_oops_equal);
2050
2051 // (1) Null check -- if one of the operands is null, the other must not be null (because
2052 // the two references are not equal), so they are not substitutable,
2053 // FIXME: do null check only if the operand is nullable
2054 __ testptr(left, right);
2055 __ jcc(Assembler::zero, L_oops_not_equal);
2056
2057 ciKlass* left_klass = op->left_klass();
2058 ciKlass* right_klass = op->right_klass();
2059
2060 // (2) Inline type check -- if either of the operands is not a inline type,
2061 // they are not substitutable. We do this only if we are not sure that the
2062 // operands are inline type
2063 if ((left_klass == NULL || right_klass == NULL) ||// The klass is still unloaded, or came from a Phi node.
2064 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
2065 Register tmp1 = op->tmp1()->as_register();
2066 __ movptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2067 __ andptr(tmp1, Address(left, oopDesc::mark_offset_in_bytes()));
2068 __ andptr(tmp1, Address(right, oopDesc::mark_offset_in_bytes()));
2069 __ cmpptr(tmp1, (intptr_t)markWord::inline_type_pattern);
2070 __ jcc(Assembler::notEqual, L_oops_not_equal);
2071 }
2072
2073 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
2074 if (left_klass != NULL && left_klass->is_inlinetype() && left_klass == right_klass) {
2075 // No need to load klass -- the operands are statically known to be the same inline klass.
2076 __ jmp(*op->stub()->entry());
2077 } else {
2078 Register left_klass_op = op->left_klass_op()->as_register();
2079 Register right_klass_op = op->right_klass_op()->as_register();
2080
2081 if (UseCompressedClassPointers) {
2082 __ movl(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
2083 __ movl(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2084 __ cmpl(left_klass_op, right_klass_op);
2085 } else {
2086 __ movptr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
2087 __ movptr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
2088 __ cmpptr(left_klass_op, right_klass_op);
2089 }
2090
2091 __ jcc(Assembler::equal, *op->stub()->entry()); // same klass -> do slow check
2092 // fall through to L_oops_not_equal
2093 }
2094
2095 __ bind(L_oops_not_equal);
2096 move(op->not_equal_result(), op->result_opr());
2097 __ jmp(L_end);
2098
2099 __ bind(L_oops_equal);
2100 move(op->equal_result(), op->result_opr());
2101 __ jmp(L_end);
2102
2103 // We've returned from the stub. RAX contains 0x0 IFF the two
2104 // operands are not substitutable. (Don't compare against 0x1 in case the
2105 // C compiler is naughty)
2106 __ bind(*op->stub()->continuation());
2107 __ cmpl(rax, 0);
2108 __ jcc(Assembler::equal, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
2109 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
2110 // fall-through
2111 __ bind(L_end);
2112 }
2113
2114 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2115 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
2116 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
2117 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
2118 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
2119 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
2120 Register addr = op->addr()->as_register();
2121 __ lock();
2122 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
2123
2124 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
2125 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
2126 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2127 Register newval = op->new_value()->as_register();
2128 Register cmpval = op->cmp_value()->as_register();
2129 assert(cmpval == rax, "wrong register");
2130 assert(newval != NULL, "new val must be register");
2131 assert(cmpval != newval, "cmp and new values must be in different registers");
2132 assert(cmpval != addr, "cmp and addr must be in different registers");
2133 assert(newval != addr, "new value and addr must be in different registers");
2134
2135 if ( op->code() == lir_cas_obj) {
2136 #ifdef _LP64
2137 if (UseCompressedOops) {
2138 __ encode_heap_oop(cmpval);
2139 __ mov(rscratch1, newval);
2140 __ encode_heap_oop(rscratch1);
2141 __ lock();
2142 // cmpval (rax) is implicitly used by this instruction
2143 __ cmpxchgl(rscratch1, Address(addr, 0));
2144 } else
2145 #endif
2146 {
2147 __ lock();
2148 __ cmpxchgptr(newval, Address(addr, 0));
2149 }
2150 } else {
2151 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2152 __ lock();
2153 __ cmpxchgl(newval, Address(addr, 0));
2154 }
2155 #ifdef _LP64
2156 } else if (op->code() == lir_cas_long) {
2157 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2158 Register newval = op->new_value()->as_register_lo();
2159 Register cmpval = op->cmp_value()->as_register_lo();
2160 assert(cmpval == rax, "wrong register");
2161 assert(newval != NULL, "new val must be register");
2162 assert(cmpval != newval, "cmp and new values must be in different registers");
2163 assert(cmpval != addr, "cmp and addr must be in different registers");
2164 assert(newval != addr, "new value and addr must be in different registers");
2165 __ lock();
2166 __ cmpxchgq(newval, Address(addr, 0));
2167 #endif // _LP64
2168 } else {
2169 Unimplemented();
2170 }
2171 }
2172
2173 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
2174 assert(dst->is_cpu_register(), "must be");
2175 assert(dst->type() == src->type(), "must be");
2176
2177 if (src->is_cpu_register()) {
2178 reg2reg(src, dst);
2179 } else if (src->is_stack()) {
2180 stack2reg(src, dst, dst->type());
2181 } else if (src->is_constant()) {
2182 const2reg(src, dst, lir_patch_none, NULL);
2183 } else {
2184 ShouldNotReachHere();
2185 }
2186 }
2187
2188 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2189 Assembler::Condition acond, ncond;
2190 switch (condition) {
2191 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2192 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2193 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2194 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2195 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2196 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2197 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2198 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2199 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2200 ShouldNotReachHere();
2201 }
2202
2203 if (opr1->is_cpu_register()) {
2204 reg2reg(opr1, result);
2205 } else if (opr1->is_stack()) {
2206 stack2reg(opr1, result, result->type());
2207 } else if (opr1->is_constant()) {
2208 const2reg(opr1, result, lir_patch_none, NULL);
2209 } else {
2210 ShouldNotReachHere();
2211 }
2212
2213 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2214 // optimized version that does not require a branch
2215 if (opr2->is_single_cpu()) {
2216 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2217 __ cmov(ncond, result->as_register(), opr2->as_register());
2218 } else if (opr2->is_double_cpu()) {
2219 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2220 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2221 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2222 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2223 } else if (opr2->is_single_stack()) {
2224 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2225 } else if (opr2->is_double_stack()) {
2226 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2227 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2228 } else {
2229 ShouldNotReachHere();
2230 }
2231
2232 } else {
2233 Label skip;
2234 __ jcc (acond, skip);
2235 if (opr2->is_cpu_register()) {
2236 reg2reg(opr2, result);
2237 } else if (opr2->is_stack()) {
2238 stack2reg(opr2, result, result->type());
2239 } else if (opr2->is_constant()) {
2240 const2reg(opr2, result, lir_patch_none, NULL);
2241 } else {
2242 ShouldNotReachHere();
2243 }
2244 __ bind(skip);
2245 }
2246 }
2247
2248
2249 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2250 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2251
2252 if (left->is_single_cpu()) {
2253 assert(left == dest, "left and dest must be equal");
2254 Register lreg = left->as_register();
2255
2256 if (right->is_single_cpu()) {
2257 // cpu register - cpu register
2258 Register rreg = right->as_register();
2259 switch (code) {
2260 case lir_add: __ addl (lreg, rreg); break;
2261 case lir_sub: __ subl (lreg, rreg); break;
2262 case lir_mul: __ imull(lreg, rreg); break;
2263 default: ShouldNotReachHere();
2264 }
2265
2266 } else if (right->is_stack()) {
2267 // cpu register - stack
2268 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2269 switch (code) {
2270 case lir_add: __ addl(lreg, raddr); break;
2271 case lir_sub: __ subl(lreg, raddr); break;
2272 default: ShouldNotReachHere();
2273 }
2274
2275 } else if (right->is_constant()) {
2276 // cpu register - constant
2277 jint c = right->as_constant_ptr()->as_jint();
2278 switch (code) {
2279 case lir_add: {
2280 __ incrementl(lreg, c);
2281 break;
2282 }
2283 case lir_sub: {
2284 __ decrementl(lreg, c);
2285 break;
2286 }
2287 default: ShouldNotReachHere();
2288 }
2289
2290 } else {
2291 ShouldNotReachHere();
2292 }
2293
2294 } else if (left->is_double_cpu()) {
2295 assert(left == dest, "left and dest must be equal");
2296 Register lreg_lo = left->as_register_lo();
2297 Register lreg_hi = left->as_register_hi();
2298
2299 if (right->is_double_cpu()) {
2300 // cpu register - cpu register
2301 Register rreg_lo = right->as_register_lo();
2302 Register rreg_hi = right->as_register_hi();
2303 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2304 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2305 switch (code) {
2306 case lir_add:
2307 __ addptr(lreg_lo, rreg_lo);
2308 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2309 break;
2310 case lir_sub:
2311 __ subptr(lreg_lo, rreg_lo);
2312 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2313 break;
2314 case lir_mul:
2315 #ifdef _LP64
2316 __ imulq(lreg_lo, rreg_lo);
2317 #else
2318 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2319 __ imull(lreg_hi, rreg_lo);
2320 __ imull(rreg_hi, lreg_lo);
2321 __ addl (rreg_hi, lreg_hi);
2322 __ mull (rreg_lo);
2323 __ addl (lreg_hi, rreg_hi);
2324 #endif // _LP64
2325 break;
2326 default:
2327 ShouldNotReachHere();
2328 }
2329
2330 } else if (right->is_constant()) {
2331 // cpu register - constant
2332 #ifdef _LP64
2333 jlong c = right->as_constant_ptr()->as_jlong_bits();
2334 __ movptr(r10, (intptr_t) c);
2335 switch (code) {
2336 case lir_add:
2337 __ addptr(lreg_lo, r10);
2338 break;
2339 case lir_sub:
2340 __ subptr(lreg_lo, r10);
2341 break;
2342 default:
2343 ShouldNotReachHere();
2344 }
2345 #else
2346 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2347 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2348 switch (code) {
2349 case lir_add:
2350 __ addptr(lreg_lo, c_lo);
2351 __ adcl(lreg_hi, c_hi);
2352 break;
2353 case lir_sub:
2354 __ subptr(lreg_lo, c_lo);
2355 __ sbbl(lreg_hi, c_hi);
2356 break;
2357 default:
2358 ShouldNotReachHere();
2359 }
2360 #endif // _LP64
2361
2362 } else {
2363 ShouldNotReachHere();
2364 }
2365
2366 } else if (left->is_single_xmm()) {
2367 assert(left == dest, "left and dest must be equal");
2368 XMMRegister lreg = left->as_xmm_float_reg();
2369
2370 if (right->is_single_xmm()) {
2371 XMMRegister rreg = right->as_xmm_float_reg();
2372 switch (code) {
2373 case lir_add: __ addss(lreg, rreg); break;
2374 case lir_sub: __ subss(lreg, rreg); break;
2375 case lir_mul: __ mulss(lreg, rreg); break;
2376 case lir_div: __ divss(lreg, rreg); break;
2377 default: ShouldNotReachHere();
2378 }
2379 } else {
2380 Address raddr;
2381 if (right->is_single_stack()) {
2382 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2383 } else if (right->is_constant()) {
2384 // hack for now
2385 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2386 } else {
2387 ShouldNotReachHere();
2388 }
2389 switch (code) {
2390 case lir_add: __ addss(lreg, raddr); break;
2391 case lir_sub: __ subss(lreg, raddr); break;
2392 case lir_mul: __ mulss(lreg, raddr); break;
2393 case lir_div: __ divss(lreg, raddr); break;
2394 default: ShouldNotReachHere();
2395 }
2396 }
2397
2398 } else if (left->is_double_xmm()) {
2399 assert(left == dest, "left and dest must be equal");
2400
2401 XMMRegister lreg = left->as_xmm_double_reg();
2402 if (right->is_double_xmm()) {
2403 XMMRegister rreg = right->as_xmm_double_reg();
2404 switch (code) {
2405 case lir_add: __ addsd(lreg, rreg); break;
2406 case lir_sub: __ subsd(lreg, rreg); break;
2407 case lir_mul: __ mulsd(lreg, rreg); break;
2408 case lir_div: __ divsd(lreg, rreg); break;
2409 default: ShouldNotReachHere();
2410 }
2411 } else {
2412 Address raddr;
2413 if (right->is_double_stack()) {
2414 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2415 } else if (right->is_constant()) {
2416 // hack for now
2417 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2418 } else {
2419 ShouldNotReachHere();
2420 }
2421 switch (code) {
2422 case lir_add: __ addsd(lreg, raddr); break;
2423 case lir_sub: __ subsd(lreg, raddr); break;
2424 case lir_mul: __ mulsd(lreg, raddr); break;
2425 case lir_div: __ divsd(lreg, raddr); break;
2426 default: ShouldNotReachHere();
2427 }
2428 }
2429
2430 #ifndef _LP64
2431 } else if (left->is_single_fpu()) {
2432 assert(dest->is_single_fpu(), "fpu stack allocation required");
2433
2434 if (right->is_single_fpu()) {
2435 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2436
2437 } else {
2438 assert(left->fpu_regnr() == 0, "left must be on TOS");
2439 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2440
2441 Address raddr;
2442 if (right->is_single_stack()) {
2443 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2444 } else if (right->is_constant()) {
2445 address const_addr = float_constant(right->as_jfloat());
2446 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2447 // hack for now
2448 raddr = __ as_Address(InternalAddress(const_addr));
2449 } else {
2450 ShouldNotReachHere();
2451 }
2452
2453 switch (code) {
2454 case lir_add: __ fadd_s(raddr); break;
2455 case lir_sub: __ fsub_s(raddr); break;
2456 case lir_mul: __ fmul_s(raddr); break;
2457 case lir_div: __ fdiv_s(raddr); break;
2458 default: ShouldNotReachHere();
2459 }
2460 }
2461
2462 } else if (left->is_double_fpu()) {
2463 assert(dest->is_double_fpu(), "fpu stack allocation required");
2464
2465 if (code == lir_mul || code == lir_div) {
2466 // Double values require special handling for strictfp mul/div on x86
2467 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2468 __ fmulp(left->fpu_regnrLo() + 1);
2469 }
2470
2471 if (right->is_double_fpu()) {
2472 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2473
2474 } else {
2475 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2476 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2477
2478 Address raddr;
2479 if (right->is_double_stack()) {
2480 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2481 } else if (right->is_constant()) {
2482 // hack for now
2483 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2484 } else {
2485 ShouldNotReachHere();
2486 }
2487
2488 switch (code) {
2489 case lir_add: __ fadd_d(raddr); break;
2490 case lir_sub: __ fsub_d(raddr); break;
2491 case lir_mul: __ fmul_d(raddr); break;
2492 case lir_div: __ fdiv_d(raddr); break;
2493 default: ShouldNotReachHere();
2494 }
2495 }
2496
2497 if (code == lir_mul || code == lir_div) {
2498 // Double values require special handling for strictfp mul/div on x86
2499 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2500 __ fmulp(dest->fpu_regnrLo() + 1);
2501 }
2502 #endif // !_LP64
2503
2504 } else if (left->is_single_stack() || left->is_address()) {
2505 assert(left == dest, "left and dest must be equal");
2506
2507 Address laddr;
2508 if (left->is_single_stack()) {
2509 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2510 } else if (left->is_address()) {
2511 laddr = as_Address(left->as_address_ptr());
2512 } else {
2513 ShouldNotReachHere();
2514 }
2515
2516 if (right->is_single_cpu()) {
2517 Register rreg = right->as_register();
2518 switch (code) {
2519 case lir_add: __ addl(laddr, rreg); break;
2520 case lir_sub: __ subl(laddr, rreg); break;
2521 default: ShouldNotReachHere();
2522 }
2523 } else if (right->is_constant()) {
2524 jint c = right->as_constant_ptr()->as_jint();
2525 switch (code) {
2526 case lir_add: {
2527 __ incrementl(laddr, c);
2528 break;
2529 }
2530 case lir_sub: {
2531 __ decrementl(laddr, c);
2532 break;
2533 }
2534 default: ShouldNotReachHere();
2535 }
2536 } else {
2537 ShouldNotReachHere();
2538 }
2539
2540 } else {
2541 ShouldNotReachHere();
2542 }
2543 }
2544
2545 #ifndef _LP64
2546 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2547 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2548 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2549 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2550
2551 bool left_is_tos = (left_index == 0);
2552 bool dest_is_tos = (dest_index == 0);
2553 int non_tos_index = (left_is_tos ? right_index : left_index);
2554
2555 switch (code) {
2556 case lir_add:
2557 if (pop_fpu_stack) __ faddp(non_tos_index);
2558 else if (dest_is_tos) __ fadd (non_tos_index);
2559 else __ fadda(non_tos_index);
2560 break;
2561
2562 case lir_sub:
2563 if (left_is_tos) {
2564 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2565 else if (dest_is_tos) __ fsub (non_tos_index);
2566 else __ fsubra(non_tos_index);
2567 } else {
2568 if (pop_fpu_stack) __ fsubp (non_tos_index);
2569 else if (dest_is_tos) __ fsubr (non_tos_index);
2570 else __ fsuba (non_tos_index);
2571 }
2572 break;
2573
2574 case lir_mul:
2575 if (pop_fpu_stack) __ fmulp(non_tos_index);
2576 else if (dest_is_tos) __ fmul (non_tos_index);
2577 else __ fmula(non_tos_index);
2578 break;
2579
2580 case lir_div:
2581 if (left_is_tos) {
2582 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2583 else if (dest_is_tos) __ fdiv (non_tos_index);
2584 else __ fdivra(non_tos_index);
2585 } else {
2586 if (pop_fpu_stack) __ fdivp (non_tos_index);
2587 else if (dest_is_tos) __ fdivr (non_tos_index);
2588 else __ fdiva (non_tos_index);
2589 }
2590 break;
2591
2592 case lir_rem:
2593 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2594 __ fremr(noreg);
2595 break;
2596
2597 default:
2598 ShouldNotReachHere();
2599 }
2600 }
2601 #endif // _LP64
2602
2603
2604 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2605 if (value->is_double_xmm()) {
2606 switch(code) {
2607 case lir_abs :
2608 {
2609 #ifdef _LP64
2610 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2611 assert(tmp->is_valid(), "need temporary");
2612 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2613 } else
2614 #endif
2615 {
2616 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2617 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2618 }
2619 assert(!tmp->is_valid(), "do not need temporary");
2620 __ andpd(dest->as_xmm_double_reg(),
2621 ExternalAddress((address)double_signmask_pool));
2622 }
2623 }
2624 break;
2625
2626 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2627 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2628 default : ShouldNotReachHere();
2629 }
2630
2631 #ifndef _LP64
2632 } else if (value->is_double_fpu()) {
2633 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2634 switch(code) {
2635 case lir_abs : __ fabs() ; break;
2636 case lir_sqrt : __ fsqrt(); break;
2637 default : ShouldNotReachHere();
2638 }
2639 #endif // !_LP64
2640 } else {
2641 Unimplemented();
2642 }
2643 }
2644
2645 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2646 // assert(left->destroys_register(), "check");
2647 if (left->is_single_cpu()) {
2648 Register reg = left->as_register();
2649 if (right->is_constant()) {
2650 int val = right->as_constant_ptr()->as_jint();
2651 switch (code) {
2652 case lir_logic_and: __ andl (reg, val); break;
2653 case lir_logic_or: __ orl (reg, val); break;
2654 case lir_logic_xor: __ xorl (reg, val); break;
2655 default: ShouldNotReachHere();
2656 }
2657 } else if (right->is_stack()) {
2658 // added support for stack operands
2659 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2660 switch (code) {
2661 case lir_logic_and: __ andl (reg, raddr); break;
2662 case lir_logic_or: __ orl (reg, raddr); break;
2663 case lir_logic_xor: __ xorl (reg, raddr); break;
2664 default: ShouldNotReachHere();
2665 }
2666 } else {
2667 Register rright = right->as_register();
2668 switch (code) {
2669 case lir_logic_and: __ andptr (reg, rright); break;
2670 case lir_logic_or : __ orptr (reg, rright); break;
2671 case lir_logic_xor: __ xorptr (reg, rright); break;
2672 default: ShouldNotReachHere();
2673 }
2674 }
2675 move_regs(reg, dst->as_register());
2676 } else {
2677 Register l_lo = left->as_register_lo();
2678 Register l_hi = left->as_register_hi();
2679 if (right->is_constant()) {
2680 #ifdef _LP64
2681 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2682 switch (code) {
2683 case lir_logic_and:
2684 __ andq(l_lo, rscratch1);
2685 break;
2686 case lir_logic_or:
2687 __ orq(l_lo, rscratch1);
2688 break;
2689 case lir_logic_xor:
2690 __ xorq(l_lo, rscratch1);
2691 break;
2692 default: ShouldNotReachHere();
2693 }
2694 #else
2695 int r_lo = right->as_constant_ptr()->as_jint_lo();
2696 int r_hi = right->as_constant_ptr()->as_jint_hi();
2697 switch (code) {
2698 case lir_logic_and:
2699 __ andl(l_lo, r_lo);
2700 __ andl(l_hi, r_hi);
2701 break;
2702 case lir_logic_or:
2703 __ orl(l_lo, r_lo);
2704 __ orl(l_hi, r_hi);
2705 break;
2706 case lir_logic_xor:
2707 __ xorl(l_lo, r_lo);
2708 __ xorl(l_hi, r_hi);
2709 break;
2710 default: ShouldNotReachHere();
2711 }
2712 #endif // _LP64
2713 } else {
2714 #ifdef _LP64
2715 Register r_lo;
2716 if (is_reference_type(right->type())) {
2717 r_lo = right->as_register();
2718 } else {
2719 r_lo = right->as_register_lo();
2720 }
2721 #else
2722 Register r_lo = right->as_register_lo();
2723 Register r_hi = right->as_register_hi();
2724 assert(l_lo != r_hi, "overwriting registers");
2725 #endif
2726 switch (code) {
2727 case lir_logic_and:
2728 __ andptr(l_lo, r_lo);
2729 NOT_LP64(__ andptr(l_hi, r_hi);)
2730 break;
2731 case lir_logic_or:
2732 __ orptr(l_lo, r_lo);
2733 NOT_LP64(__ orptr(l_hi, r_hi);)
2734 break;
2735 case lir_logic_xor:
2736 __ xorptr(l_lo, r_lo);
2737 NOT_LP64(__ xorptr(l_hi, r_hi);)
2738 break;
2739 default: ShouldNotReachHere();
2740 }
2741 }
2742
2743 Register dst_lo = dst->as_register_lo();
2744 Register dst_hi = dst->as_register_hi();
2745
2746 #ifdef _LP64
2747 move_regs(l_lo, dst_lo);
2748 #else
2749 if (dst_lo == l_hi) {
2750 assert(dst_hi != l_lo, "overwriting registers");
2751 move_regs(l_hi, dst_hi);
2752 move_regs(l_lo, dst_lo);
2753 } else {
2754 assert(dst_lo != l_hi, "overwriting registers");
2755 move_regs(l_lo, dst_lo);
2756 move_regs(l_hi, dst_hi);
2757 }
2758 #endif // _LP64
2759 }
2760 }
2761
2762
2763 // we assume that rax, and rdx can be overwritten
2764 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2765
2766 assert(left->is_single_cpu(), "left must be register");
2767 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2768 assert(result->is_single_cpu(), "result must be register");
2769
2770 // assert(left->destroys_register(), "check");
2771 // assert(right->destroys_register(), "check");
2772
2773 Register lreg = left->as_register();
2774 Register dreg = result->as_register();
2775
2776 if (right->is_constant()) {
2777 jint divisor = right->as_constant_ptr()->as_jint();
2778 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2779 if (code == lir_idiv) {
2780 assert(lreg == rax, "must be rax,");
2781 assert(temp->as_register() == rdx, "tmp register must be rdx");
2782 __ cdql(); // sign extend into rdx:rax
2783 if (divisor == 2) {
2784 __ subl(lreg, rdx);
2785 } else {
2786 __ andl(rdx, divisor - 1);
2787 __ addl(lreg, rdx);
2788 }
2789 __ sarl(lreg, log2i_exact(divisor));
2790 move_regs(lreg, dreg);
2791 } else if (code == lir_irem) {
2792 Label done;
2793 __ mov(dreg, lreg);
2794 __ andl(dreg, 0x80000000 | (divisor - 1));
2795 __ jcc(Assembler::positive, done);
2796 __ decrement(dreg);
2797 __ orl(dreg, ~(divisor - 1));
2798 __ increment(dreg);
2799 __ bind(done);
2800 } else {
2801 ShouldNotReachHere();
2802 }
2803 } else {
2804 Register rreg = right->as_register();
2805 assert(lreg == rax, "left register must be rax,");
2806 assert(rreg != rdx, "right register must not be rdx");
2807 assert(temp->as_register() == rdx, "tmp register must be rdx");
2808
2809 move_regs(lreg, rax);
2810
2811 int idivl_offset = __ corrected_idivl(rreg);
2812 if (ImplicitDiv0Checks) {
2813 add_debug_info_for_div0(idivl_offset, info);
2814 }
2815 if (code == lir_irem) {
2816 move_regs(rdx, dreg); // result is in rdx
2817 } else {
2818 move_regs(rax, dreg);
2819 }
2820 }
2821 }
2822
2823
2824 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2825 if (opr1->is_single_cpu()) {
2826 Register reg1 = opr1->as_register();
2827 if (opr2->is_single_cpu()) {
2828 // cpu register - cpu register
2829 if (is_reference_type(opr1->type())) {
2830 __ cmpoop(reg1, opr2->as_register());
2831 } else {
2832 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2833 __ cmpl(reg1, opr2->as_register());
2834 }
2835 } else if (opr2->is_stack()) {
2836 // cpu register - stack
2837 if (is_reference_type(opr1->type())) {
2838 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2839 } else {
2840 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2841 }
2842 } else if (opr2->is_constant()) {
2843 // cpu register - constant
2844 LIR_Const* c = opr2->as_constant_ptr();
2845 if (c->type() == T_INT) {
2846 __ cmpl(reg1, c->as_jint());
2847 } else if (c->type() == T_METADATA) {
2848 // All we need for now is a comparison with NULL for equality.
2849 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2850 Metadata* m = c->as_metadata();
2851 if (m == NULL) {
2852 __ cmpptr(reg1, (int32_t)0);
2853 } else {
2854 ShouldNotReachHere();
2855 }
2856 } else if (is_reference_type(c->type())) {
2857 // In 64bit oops are single register
2858 jobject o = c->as_jobject();
2859 if (o == NULL) {
2860 __ cmpptr(reg1, (int32_t)NULL_WORD);
2861 } else {
2862 __ cmpoop(reg1, o);
2863 }
2864 } else {
2865 fatal("unexpected type: %s", basictype_to_str(c->type()));
2866 }
2867 // cpu register - address
2868 } else if (opr2->is_address()) {
2869 if (op->info() != NULL) {
2870 add_debug_info_for_null_check_here(op->info());
2871 }
2872 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2873 } else {
2874 ShouldNotReachHere();
2875 }
2876
2877 } else if(opr1->is_double_cpu()) {
2878 Register xlo = opr1->as_register_lo();
2879 Register xhi = opr1->as_register_hi();
2880 if (opr2->is_double_cpu()) {
2881 #ifdef _LP64
2882 __ cmpptr(xlo, opr2->as_register_lo());
2883 #else
2884 // cpu register - cpu register
2885 Register ylo = opr2->as_register_lo();
2886 Register yhi = opr2->as_register_hi();
2887 __ subl(xlo, ylo);
2888 __ sbbl(xhi, yhi);
2889 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2890 __ orl(xhi, xlo);
2891 }
2892 #endif // _LP64
2893 } else if (opr2->is_constant()) {
2894 // cpu register - constant 0
2895 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2896 #ifdef _LP64
2897 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2898 #else
2899 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2900 __ orl(xhi, xlo);
2901 #endif // _LP64
2902 } else {
2903 ShouldNotReachHere();
2904 }
2905
2906 } else if (opr1->is_single_xmm()) {
2907 XMMRegister reg1 = opr1->as_xmm_float_reg();
2908 if (opr2->is_single_xmm()) {
2909 // xmm register - xmm register
2910 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2911 } else if (opr2->is_stack()) {
2912 // xmm register - stack
2913 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2914 } else if (opr2->is_constant()) {
2915 // xmm register - constant
2916 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2917 } else if (opr2->is_address()) {
2918 // xmm register - address
2919 if (op->info() != NULL) {
2920 add_debug_info_for_null_check_here(op->info());
2921 }
2922 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2923 } else {
2924 ShouldNotReachHere();
2925 }
2926
2927 } else if (opr1->is_double_xmm()) {
2928 XMMRegister reg1 = opr1->as_xmm_double_reg();
2929 if (opr2->is_double_xmm()) {
2930 // xmm register - xmm register
2931 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2932 } else if (opr2->is_stack()) {
2933 // xmm register - stack
2934 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2935 } else if (opr2->is_constant()) {
2936 // xmm register - constant
2937 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2938 } else if (opr2->is_address()) {
2939 // xmm register - address
2940 if (op->info() != NULL) {
2941 add_debug_info_for_null_check_here(op->info());
2942 }
2943 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2944 } else {
2945 ShouldNotReachHere();
2946 }
2947
2948 #ifndef _LP64
2949 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2950 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2951 assert(opr2->is_fpu_register(), "both must be registers");
2952 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2953 #endif // LP64
2954
2955 } else if (opr1->is_address() && opr2->is_constant()) {
2956 LIR_Const* c = opr2->as_constant_ptr();
2957 #ifdef _LP64
2958 if (is_reference_type(c->type())) {
2959 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2960 __ movoop(rscratch1, c->as_jobject());
2961 }
2962 #endif // LP64
2963 if (op->info() != NULL) {
2964 add_debug_info_for_null_check_here(op->info());
2965 }
2966 // special case: address - constant
2967 LIR_Address* addr = opr1->as_address_ptr();
2968 if (c->type() == T_INT) {
2969 __ cmpl(as_Address(addr), c->as_jint());
2970 } else if (is_reference_type(c->type())) {
2971 #ifdef _LP64
2972 // %%% Make this explode if addr isn't reachable until we figure out a
2973 // better strategy by giving noreg as the temp for as_Address
2974 __ cmpoop(rscratch1, as_Address(addr, noreg));
2975 #else
2976 __ cmpoop(as_Address(addr), c->as_jobject());
2977 #endif // _LP64
2978 } else {
2979 ShouldNotReachHere();
2980 }
2981
2982 } else {
2983 ShouldNotReachHere();
2984 }
2985 }
2986
2987 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2988 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2989 if (left->is_single_xmm()) {
2990 assert(right->is_single_xmm(), "must match");
2991 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2992 } else if (left->is_double_xmm()) {
2993 assert(right->is_double_xmm(), "must match");
2994 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2995
2996 } else {
2997 #ifdef _LP64
2998 ShouldNotReachHere();
2999 #else
3000 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
3001 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
3002
3003 assert(left->fpu() == 0, "left must be on TOS");
3004 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
3005 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
3006 #endif // LP64
3007 }
3008 } else {
3009 assert(code == lir_cmp_l2i, "check");
3010 #ifdef _LP64
3011 Label done;
3012 Register dest = dst->as_register();
3013 __ cmpptr(left->as_register_lo(), right->as_register_lo());
3014 __ movl(dest, -1);
3015 __ jccb(Assembler::less, done);
3016 __ set_byte_if_not_zero(dest);
3017 __ movzbl(dest, dest);
3018 __ bind(done);
3019 #else
3020 __ lcmp2int(left->as_register_hi(),
3021 left->as_register_lo(),
3022 right->as_register_hi(),
3023 right->as_register_lo());
3024 move_regs(left->as_register_hi(), dst->as_register());
3025 #endif // _LP64
3026 }
3027 }
3028
3029
3030 void LIR_Assembler::align_call(LIR_Code code) {
3031 // make sure that the displacement word of the call ends up word aligned
3032 int offset = __ offset();
3033 switch (code) {
3034 case lir_static_call:
3035 case lir_optvirtual_call:
3036 case lir_dynamic_call:
3037 offset += NativeCall::displacement_offset;
3038 break;
3039 case lir_icvirtual_call:
3040 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
3041 break;
3042 default: ShouldNotReachHere();
3043 }
3044 __ align(BytesPerWord, offset);
3045 }
3046
3047
3048 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
3049 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
3050 "must be aligned");
3051 __ call(AddressLiteral(op->addr(), rtype));
3052 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3053 }
3054
3055
3056 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
3057 __ ic_call(op->addr());
3058 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
3059 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
3060 "must be aligned");
3061 }
3062
3063
3064 void LIR_Assembler::emit_static_call_stub() {
3065 address call_pc = __ pc();
3066 address stub = __ start_a_stub(call_stub_size());
3067 if (stub == NULL) {
3068 bailout("static call stub overflow");
3069 return;
3070 }
3071
3072 int start = __ offset();
3073
3074 // make sure that the displacement word of the call ends up word aligned
3075 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
3076 __ relocate(static_stub_Relocation::spec(call_pc));
3077 __ mov_metadata(rbx, (Metadata*)NULL);
3078 // must be set to -1 at code generation time
3079 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
3080 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
3081 __ jump(RuntimeAddress(__ pc()));
3082
3083 assert(__ offset() - start <= call_stub_size(), "stub too big");
3084 __ end_a_stub();
3085 }
3086
3087
3088 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
3089 assert(exceptionOop->as_register() == rax, "must match");
3090 assert(exceptionPC->as_register() == rdx, "must match");
3091
3092 // exception object is not added to oop map by LinearScan
3093 // (LinearScan assumes that no oops are in fixed registers)
3094 info->add_register_oop(exceptionOop);
3095 Runtime1::StubID unwind_id;
3096
3097 // get current pc information
3098 // pc is only needed if the method has an exception handler, the unwind code does not need it.
3099 int pc_for_athrow_offset = __ offset();
3100 InternalAddress pc_for_athrow(__ pc());
3101 __ lea(exceptionPC->as_register(), pc_for_athrow);
3102 add_call_info(pc_for_athrow_offset, info); // for exception handler
3103
3104 __ verify_not_null_oop(rax);
3105 // search an exception handler (rax: exception oop, rdx: throwing pc)
3106 if (compilation()->has_fpu_code()) {
3107 unwind_id = Runtime1::handle_exception_id;
3108 } else {
3109 unwind_id = Runtime1::handle_exception_nofpu_id;
3110 }
3111 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
3112
3113 // enough room for two byte trap
3114 __ nop();
3115 }
3116
3117
3118 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
3119 assert(exceptionOop->as_register() == rax, "must match");
3120
3121 __ jmp(_unwind_handler_entry);
3122 }
3123
3124
3125 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3126
3127 // optimized version for linear scan:
3128 // * count must be already in ECX (guaranteed by LinearScan)
3129 // * left and dest must be equal
3130 // * tmp must be unused
3131 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3132 assert(left == dest, "left and dest must be equal");
3133 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3134
3135 if (left->is_single_cpu()) {
3136 Register value = left->as_register();
3137 assert(value != SHIFT_count, "left cannot be ECX");
3138
3139 switch (code) {
3140 case lir_shl: __ shll(value); break;
3141 case lir_shr: __ sarl(value); break;
3142 case lir_ushr: __ shrl(value); break;
3143 default: ShouldNotReachHere();
3144 }
3145 } else if (left->is_double_cpu()) {
3146 Register lo = left->as_register_lo();
3147 Register hi = left->as_register_hi();
3148 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3149 #ifdef _LP64
3150 switch (code) {
3151 case lir_shl: __ shlptr(lo); break;
3152 case lir_shr: __ sarptr(lo); break;
3153 case lir_ushr: __ shrptr(lo); break;
3154 default: ShouldNotReachHere();
3155 }
3156 #else
3157
3158 switch (code) {
3159 case lir_shl: __ lshl(hi, lo); break;
3160 case lir_shr: __ lshr(hi, lo, true); break;
3161 case lir_ushr: __ lshr(hi, lo, false); break;
3162 default: ShouldNotReachHere();
3163 }
3164 #endif // LP64
3165 } else {
3166 ShouldNotReachHere();
3167 }
3168 }
3169
3170
3171 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3172 if (dest->is_single_cpu()) {
3173 // first move left into dest so that left is not destroyed by the shift
3174 Register value = dest->as_register();
3175 count = count & 0x1F; // Java spec
3176
3177 move_regs(left->as_register(), value);
3178 switch (code) {
3179 case lir_shl: __ shll(value, count); break;
3180 case lir_shr: __ sarl(value, count); break;
3181 case lir_ushr: __ shrl(value, count); break;
3182 default: ShouldNotReachHere();
3183 }
3184 } else if (dest->is_double_cpu()) {
3185 #ifndef _LP64
3186 Unimplemented();
3187 #else
3188 // first move left into dest so that left is not destroyed by the shift
3189 Register value = dest->as_register_lo();
3190 count = count & 0x1F; // Java spec
3191
3192 move_regs(left->as_register_lo(), value);
3193 switch (code) {
3194 case lir_shl: __ shlptr(value, count); break;
3195 case lir_shr: __ sarptr(value, count); break;
3196 case lir_ushr: __ shrptr(value, count); break;
3197 default: ShouldNotReachHere();
3198 }
3199 #endif // _LP64
3200 } else {
3201 ShouldNotReachHere();
3202 }
3203 }
3204
3205
3206 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3207 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3208 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3209 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3210 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3211 }
3212
3213
3214 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3215 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3216 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3217 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3218 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3219 }
3220
3221
3222 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3223 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3224 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3225 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3226 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3227 }
3228
3229
3230 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3231 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3232 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3233 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3234 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3235 }
3236
3237
3238 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
3239 if (null_check) {
3240 __ testptr(obj, obj);
3241 __ jcc(Assembler::zero, *slow_path->entry());
3242 }
3243 if (UseArrayMarkWordCheck) {
3244 if (is_dest) {
3245 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
3246 } else {
3247 __ test_flattened_array_oop(obj, tmp, *slow_path->entry());
3248 }
3249 } else {
3250 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3251 __ load_klass(tmp, obj, tmp_load_klass);
3252 __ movl(tmp, Address(tmp, Klass::layout_helper_offset()));
3253 if (is_dest) {
3254 // Take the slow path if it's a null_free destination array, in case the source array contains NULLs.
3255 __ testl(tmp, Klass::_lh_null_free_array_bit_inplace);
3256 } else {
3257 __ testl(tmp, Klass::_lh_array_tag_flat_value_bit_inplace);
3258 }
3259 __ jcc(Assembler::notZero, *slow_path->entry());
3260 }
3261 }
3262
3263
3264 // This code replaces a call to arraycopy; no exception may
3265 // be thrown in this code, they must be thrown in the System.arraycopy
3266 // activation frame; we could save some checks if this would not be the case
3267 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3268 ciArrayKlass* default_type = op->expected_type();
3269 Register src = op->src()->as_register();
3270 Register dst = op->dst()->as_register();
3271 Register src_pos = op->src_pos()->as_register();
3272 Register dst_pos = op->dst_pos()->as_register();
3273 Register length = op->length()->as_register();
3274 Register tmp = op->tmp()->as_register();
3275 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3276
3277 CodeStub* stub = op->stub();
3278 int flags = op->flags();
3279 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3280 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3281
3282 if (flags & LIR_OpArrayCopy::always_slow_path) {
3283 __ jmp(*stub->entry());
3284 __ bind(*stub->continuation());
3285 return;
3286 }
3287
3288 // if we don't know anything, just go through the generic arraycopy
3289 if (default_type == NULL) {
3290 // save outgoing arguments on stack in case call to System.arraycopy is needed
3291 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3292 // for interpreter calling conventions. Now we have to do it in new style conventions.
3293 // For the moment until C1 gets the new register allocator I just force all the
3294 // args to the right place (except the register args) and then on the back side
3295 // reload the register args properly if we go slow path. Yuck
3296
3297 // These are proper for the calling convention
3298 store_parameter(length, 2);
3299 store_parameter(dst_pos, 1);
3300 store_parameter(dst, 0);
3301
3302 // these are just temporary placements until we need to reload
3303 store_parameter(src_pos, 3);
3304 store_parameter(src, 4);
3305 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3306
3307 address copyfunc_addr = StubRoutines::generic_arraycopy();
3308 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3309
3310 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3311 #ifdef _LP64
3312 // The arguments are in java calling convention so we can trivially shift them to C
3313 // convention
3314 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3315 __ mov(c_rarg0, j_rarg0);
3316 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3317 __ mov(c_rarg1, j_rarg1);
3318 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3319 __ mov(c_rarg2, j_rarg2);
3320 assert_different_registers(c_rarg3, j_rarg4);
3321 __ mov(c_rarg3, j_rarg3);
3322 #ifdef _WIN64
3323 // Allocate abi space for args but be sure to keep stack aligned
3324 __ subptr(rsp, 6*wordSize);
3325 store_parameter(j_rarg4, 4);
3326 #ifndef PRODUCT
3327 if (PrintC1Statistics) {
3328 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3329 }
3330 #endif
3331 __ call(RuntimeAddress(copyfunc_addr));
3332 __ addptr(rsp, 6*wordSize);
3333 #else
3334 __ mov(c_rarg4, j_rarg4);
3335 #ifndef PRODUCT
3336 if (PrintC1Statistics) {
3337 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3338 }
3339 #endif
3340 __ call(RuntimeAddress(copyfunc_addr));
3341 #endif // _WIN64
3342 #else
3343 __ push(length);
3344 __ push(dst_pos);
3345 __ push(dst);
3346 __ push(src_pos);
3347 __ push(src);
3348
3349 #ifndef PRODUCT
3350 if (PrintC1Statistics) {
3351 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3352 }
3353 #endif
3354 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3355
3356 #endif // _LP64
3357
3358 __ cmpl(rax, 0);
3359 __ jcc(Assembler::equal, *stub->continuation());
3360
3361 __ mov(tmp, rax);
3362 __ xorl(tmp, -1);
3363
3364 // Reload values from the stack so they are where the stub
3365 // expects them.
3366 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3367 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3368 __ movptr (length, Address(rsp, 2*BytesPerWord));
3369 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3370 __ movptr (src, Address(rsp, 4*BytesPerWord));
3371
3372 __ subl(length, tmp);
3373 __ addl(src_pos, tmp);
3374 __ addl(dst_pos, tmp);
3375 __ jmp(*stub->entry());
3376
3377 __ bind(*stub->continuation());
3378 return;
3379 }
3380
3381 // Handle inline type arrays
3382 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
3383 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
3384 }
3385 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
3386 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
3387 }
3388
3389 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3390
3391 int elem_size = type2aelembytes(basic_type);
3392 Address::ScaleFactor scale;
3393
3394 switch (elem_size) {
3395 case 1 :
3396 scale = Address::times_1;
3397 break;
3398 case 2 :
3399 scale = Address::times_2;
3400 break;
3401 case 4 :
3402 scale = Address::times_4;
3403 break;
3404 case 8 :
3405 scale = Address::times_8;
3406 break;
3407 default:
3408 scale = Address::no_scale;
3409 ShouldNotReachHere();
3410 }
3411
3412 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3413 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3414 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3415 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3416
3417 // length and pos's are all sign extended at this point on 64bit
3418
3419 // test for NULL
3420 if (flags & LIR_OpArrayCopy::src_null_check) {
3421 __ testptr(src, src);
3422 __ jcc(Assembler::zero, *stub->entry());
3423 }
3424 if (flags & LIR_OpArrayCopy::dst_null_check) {
3425 __ testptr(dst, dst);
3426 __ jcc(Assembler::zero, *stub->entry());
3427 }
3428
3429 // If the compiler was not able to prove that exact type of the source or the destination
3430 // of the arraycopy is an array type, check at runtime if the source or the destination is
3431 // an instance type.
3432 if (flags & LIR_OpArrayCopy::type_check) {
3433 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3434 __ load_klass(tmp, dst, tmp_load_klass);
3435 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3436 __ jcc(Assembler::greaterEqual, *stub->entry());
3437 }
3438
3439 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3440 __ load_klass(tmp, src, tmp_load_klass);
3441 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3442 __ jcc(Assembler::greaterEqual, *stub->entry());
3443 }
3444 }
3445
3446 // check if negative
3447 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3448 __ testl(src_pos, src_pos);
3449 __ jcc(Assembler::less, *stub->entry());
3450 }
3451 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3452 __ testl(dst_pos, dst_pos);
3453 __ jcc(Assembler::less, *stub->entry());
3454 }
3455
3456 if (flags & LIR_OpArrayCopy::src_range_check) {
3457 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3458 __ cmpl(tmp, src_length_addr);
3459 __ jcc(Assembler::above, *stub->entry());
3460 }
3461 if (flags & LIR_OpArrayCopy::dst_range_check) {
3462 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3463 __ cmpl(tmp, dst_length_addr);
3464 __ jcc(Assembler::above, *stub->entry());
3465 }
3466
3467 if (flags & LIR_OpArrayCopy::length_positive_check) {
3468 __ testl(length, length);
3469 __ jcc(Assembler::less, *stub->entry());
3470 }
3471
3472 #ifdef _LP64
3473 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3474 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3475 #endif
3476
3477 if (flags & LIR_OpArrayCopy::type_check) {
3478 // We don't know the array types are compatible
3479 if (basic_type != T_OBJECT) {
3480 // Simple test for basic type arrays
3481 if (UseCompressedClassPointers) {
3482 __ movl(tmp, src_klass_addr);
3483 __ cmpl(tmp, dst_klass_addr);
3484 } else {
3485 __ movptr(tmp, src_klass_addr);
3486 __ cmpptr(tmp, dst_klass_addr);
3487 }
3488 __ jcc(Assembler::notEqual, *stub->entry());
3489 } else {
3490 // For object arrays, if src is a sub class of dst then we can
3491 // safely do the copy.
3492 Label cont, slow;
3493
3494 __ push(src);
3495 __ push(dst);
3496
3497 __ load_klass(src, src, tmp_load_klass);
3498 __ load_klass(dst, dst, tmp_load_klass);
3499
3500 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3501
3502 __ push(src);
3503 __ push(dst);
3504 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3505 __ pop(dst);
3506 __ pop(src);
3507
3508 __ cmpl(src, 0);
3509 __ jcc(Assembler::notEqual, cont);
3510
3511 __ bind(slow);
3512 __ pop(dst);
3513 __ pop(src);
3514
3515 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3516 if (copyfunc_addr != NULL) { // use stub if available
3517 // src is not a sub class of dst so we have to do a
3518 // per-element check.
3519
3520 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3521 if ((flags & mask) != mask) {
3522 // Check that at least both of them object arrays.
3523 assert(flags & mask, "one of the two should be known to be an object array");
3524
3525 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3526 __ load_klass(tmp, src, tmp_load_klass);
3527 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3528 __ load_klass(tmp, dst, tmp_load_klass);
3529 }
3530 int lh_offset = in_bytes(Klass::layout_helper_offset());
3531 Address klass_lh_addr(tmp, lh_offset);
3532 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3533 __ cmpl(klass_lh_addr, objArray_lh);
3534 __ jcc(Assembler::notEqual, *stub->entry());
3535 }
3536
3537 // Spill because stubs can use any register they like and it's
3538 // easier to restore just those that we care about.
3539 store_parameter(dst, 0);
3540 store_parameter(dst_pos, 1);
3541 store_parameter(length, 2);
3542 store_parameter(src_pos, 3);
3543 store_parameter(src, 4);
3544
3545 #ifndef _LP64
3546 __ movptr(tmp, dst_klass_addr);
3547 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3548 __ push(tmp);
3549 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3550 __ push(tmp);
3551 __ push(length);
3552 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3553 __ push(tmp);
3554 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3555 __ push(tmp);
3556
3557 __ call_VM_leaf(copyfunc_addr, 5);
3558 #else
3559 __ movl2ptr(length, length); //higher 32bits must be null
3560
3561 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3562 assert_different_registers(c_rarg0, dst, dst_pos, length);
3563 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3564 assert_different_registers(c_rarg1, dst, length);
3565
3566 __ mov(c_rarg2, length);
3567 assert_different_registers(c_rarg2, dst);
3568
3569 #ifdef _WIN64
3570 // Allocate abi space for args but be sure to keep stack aligned
3571 __ subptr(rsp, 6*wordSize);
3572 __ load_klass(c_rarg3, dst, tmp_load_klass);
3573 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3574 store_parameter(c_rarg3, 4);
3575 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3576 __ call(RuntimeAddress(copyfunc_addr));
3577 __ addptr(rsp, 6*wordSize);
3578 #else
3579 __ load_klass(c_rarg4, dst, tmp_load_klass);
3580 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3581 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3582 __ call(RuntimeAddress(copyfunc_addr));
3583 #endif
3584
3585 #endif
3586
3587 #ifndef PRODUCT
3588 if (PrintC1Statistics) {
3589 Label failed;
3590 __ testl(rax, rax);
3591 __ jcc(Assembler::notZero, failed);
3592 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3593 __ bind(failed);
3594 }
3595 #endif
3596
3597 __ testl(rax, rax);
3598 __ jcc(Assembler::zero, *stub->continuation());
3599
3600 #ifndef PRODUCT
3601 if (PrintC1Statistics) {
3602 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3603 }
3604 #endif
3605
3606 __ mov(tmp, rax);
3607
3608 __ xorl(tmp, -1);
3609
3610 // Restore previously spilled arguments
3611 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3612 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3613 __ movptr (length, Address(rsp, 2*BytesPerWord));
3614 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3615 __ movptr (src, Address(rsp, 4*BytesPerWord));
3616
3617
3618 __ subl(length, tmp);
3619 __ addl(src_pos, tmp);
3620 __ addl(dst_pos, tmp);
3621 }
3622
3623 __ jmp(*stub->entry());
3624
3625 __ bind(cont);
3626 __ pop(dst);
3627 __ pop(src);
3628 }
3629 }
3630
3631 #ifdef ASSERT
3632 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3633 // Sanity check the known type with the incoming class. For the
3634 // primitive case the types must match exactly with src.klass and
3635 // dst.klass each exactly matching the default type. For the
3636 // object array case, if no type check is needed then either the
3637 // dst type is exactly the expected type and the src type is a
3638 // subtype which we can't check or src is the same array as dst
3639 // but not necessarily exactly of type default_type.
3640 Label known_ok, halt;
3641 __ mov_metadata(tmp, default_type->constant_encoding());
3642 #ifdef _LP64
3643 if (UseCompressedClassPointers) {
3644 __ encode_klass_not_null(tmp, rscratch1);
3645 }
3646 #endif
3647
3648 if (basic_type != T_OBJECT) {
3649
3650 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3651 else __ cmpptr(tmp, dst_klass_addr);
3652 __ jcc(Assembler::notEqual, halt);
3653 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3654 else __ cmpptr(tmp, src_klass_addr);
3655 __ jcc(Assembler::equal, known_ok);
3656 } else {
3657 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3658 else __ cmpptr(tmp, dst_klass_addr);
3659 __ jcc(Assembler::equal, known_ok);
3660 __ cmpptr(src, dst);
3661 __ jcc(Assembler::equal, known_ok);
3662 }
3663 __ bind(halt);
3664 __ stop("incorrect type information in arraycopy");
3665 __ bind(known_ok);
3666 }
3667 #endif
3668
3669 #ifndef PRODUCT
3670 if (PrintC1Statistics) {
3671 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3672 }
3673 #endif
3674
3675 #ifdef _LP64
3676 assert_different_registers(c_rarg0, dst, dst_pos, length);
3677 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3678 assert_different_registers(c_rarg1, length);
3679 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3680 __ mov(c_rarg2, length);
3681
3682 #else
3683 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3684 store_parameter(tmp, 0);
3685 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3686 store_parameter(tmp, 1);
3687 store_parameter(length, 2);
3688 #endif // _LP64
3689
3690 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3691 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3692 const char *name;
3693 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3694 __ call_VM_leaf(entry, 0);
3695
3696 __ bind(*stub->continuation());
3697 }
3698
3699 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3700 assert(op->crc()->is_single_cpu(), "crc must be register");
3701 assert(op->val()->is_single_cpu(), "byte value must be register");
3702 assert(op->result_opr()->is_single_cpu(), "result must be register");
3703 Register crc = op->crc()->as_register();
3704 Register val = op->val()->as_register();
3705 Register res = op->result_opr()->as_register();
3706
3707 assert_different_registers(val, crc, res);
3708
3709 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3710 __ notl(crc); // ~crc
3711 __ update_byte_crc32(crc, val, res);
3712 __ notl(crc); // ~crc
3713 __ mov(res, crc);
3714 }
3715
3716 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3717 Register obj = op->obj_opr()->as_register(); // may not be an oop
3718 Register hdr = op->hdr_opr()->as_register();
3719 Register lock = op->lock_opr()->as_register();
3720 if (!UseFastLocking) {
3721 __ jmp(*op->stub()->entry());
3722 } else if (op->code() == lir_lock) {
3723 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3724 // add debug info for NullPointerException only if one is possible
3725 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
3726 if (op->info() != NULL) {
3727 add_debug_info_for_null_check(null_check_offset, op->info());
3728 }
3729 // done
3730 } else if (op->code() == lir_unlock) {
3731 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3732 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3733 } else {
3734 Unimplemented();
3735 }
3736 __ bind(*op->stub()->continuation());
3737 }
3738
3739
3740 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3741 ciMethod* method = op->profiled_method();
3742 int bci = op->profiled_bci();
3743 ciMethod* callee = op->profiled_callee();
3744 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3745
3746 // Update counter for all call types
3747 ciMethodData* md = method->method_data_or_null();
3748 assert(md != NULL, "Sanity");
3749 ciProfileData* data = md->bci_to_data(bci);
3750 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3751 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3752 Register mdo = op->mdo()->as_register();
3753 __ mov_metadata(mdo, md->constant_encoding());
3754 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3755 // Perform additional virtual call profiling for invokevirtual and
3756 // invokeinterface bytecodes
3757 if (op->should_profile_receiver_type()) {
3758 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3759 Register recv = op->recv()->as_register();
3760 assert_different_registers(mdo, recv);
3761 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3762 ciKlass* known_klass = op->known_holder();
3763 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3764 // We know the type that will be seen at this call site; we can
3765 // statically update the MethodData* rather than needing to do
3766 // dynamic tests on the receiver type
3767
3768 // NOTE: we should probably put a lock around this search to
3769 // avoid collisions by concurrent compilations
3770 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3771 uint i;
3772 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3773 ciKlass* receiver = vc_data->receiver(i);
3774 if (known_klass->equals(receiver)) {
3775 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3776 __ addptr(data_addr, DataLayout::counter_increment);
3777 return;
3778 }
3779 }
3780
3781 // Receiver type not found in profile data; select an empty slot
3782
3783 // Note that this is less efficient than it should be because it
3784 // always does a write to the receiver part of the
3785 // VirtualCallData rather than just the first time
3786 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3787 ciKlass* receiver = vc_data->receiver(i);
3788 if (receiver == NULL) {
3789 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3790 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3791 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3792 __ addptr(data_addr, DataLayout::counter_increment);
3793 return;
3794 }
3795 }
3796 } else {
3797 __ load_klass(recv, recv, tmp_load_klass);
3798 Label update_done;
3799 type_profile_helper(mdo, md, data, recv, &update_done);
3800 // Receiver did not match any saved receiver and there is no empty row for it.
3801 // Increment total counter to indicate polymorphic case.
3802 __ addptr(counter_addr, DataLayout::counter_increment);
3803
3804 __ bind(update_done);
3805 }
3806 } else {
3807 // Static call
3808 __ addptr(counter_addr, DataLayout::counter_increment);
3809 }
3810 }
3811
3812 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3813 Register obj = op->obj()->as_register();
3814 Register tmp = op->tmp()->as_pointer_register();
3815 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3816 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3817 ciKlass* exact_klass = op->exact_klass();
3818 intptr_t current_klass = op->current_klass();
3819 bool not_null = op->not_null();
3820 bool no_conflict = op->no_conflict();
3821
3822 Label update, next, none;
3823
3824 bool do_null = !not_null;
3825 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3826 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3827
3828 assert(do_null || do_update, "why are we here?");
3829 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3830
3831 __ verify_oop(obj);
3832
3833 if (tmp != obj) {
3834 __ mov(tmp, obj);
3835 }
3836 if (do_null) {
3837 __ testptr(tmp, tmp);
3838 __ jccb(Assembler::notZero, update);
3839 if (!TypeEntries::was_null_seen(current_klass)) {
3840 __ orptr(mdo_addr, TypeEntries::null_seen);
3841 }
3842 if (do_update) {
3843 #ifndef ASSERT
3844 __ jmpb(next);
3845 }
3846 #else
3847 __ jmp(next);
3848 }
3849 } else {
3850 __ testptr(tmp, tmp);
3851 __ jcc(Assembler::notZero, update);
3852 __ stop("unexpect null obj");
3853 #endif
3854 }
3855
3856 __ bind(update);
3857
3858 if (do_update) {
3859 #ifdef ASSERT
3860 if (exact_klass != NULL) {
3861 Label ok;
3862 __ load_klass(tmp, tmp, tmp_load_klass);
3863 __ push(tmp);
3864 __ mov_metadata(tmp, exact_klass->constant_encoding());
3865 __ cmpptr(tmp, Address(rsp, 0));
3866 __ jcc(Assembler::equal, ok);
3867 __ stop("exact klass and actual klass differ");
3868 __ bind(ok);
3869 __ pop(tmp);
3870 }
3871 #endif
3872 if (!no_conflict) {
3873 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3874 if (exact_klass != NULL) {
3875 __ mov_metadata(tmp, exact_klass->constant_encoding());
3876 } else {
3877 __ load_klass(tmp, tmp, tmp_load_klass);
3878 }
3879
3880 __ xorptr(tmp, mdo_addr);
3881 __ testptr(tmp, TypeEntries::type_klass_mask);
3882 // klass seen before, nothing to do. The unknown bit may have been
3883 // set already but no need to check.
3884 __ jccb(Assembler::zero, next);
3885
3886 __ testptr(tmp, TypeEntries::type_unknown);
3887 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3888
3889 if (TypeEntries::is_type_none(current_klass)) {
3890 __ cmpptr(mdo_addr, 0);
3891 __ jccb(Assembler::equal, none);
3892 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3893 __ jccb(Assembler::equal, none);
3894 // There is a chance that the checks above (re-reading profiling
3895 // data from memory) fail if another thread has just set the
3896 // profiling to this obj's klass
3897 __ xorptr(tmp, mdo_addr);
3898 __ testptr(tmp, TypeEntries::type_klass_mask);
3899 __ jccb(Assembler::zero, next);
3900 }
3901 } else {
3902 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3903 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3904
3905 __ movptr(tmp, mdo_addr);
3906 __ testptr(tmp, TypeEntries::type_unknown);
3907 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3908 }
3909
3910 // different than before. Cannot keep accurate profile.
3911 __ orptr(mdo_addr, TypeEntries::type_unknown);
3912
3913 if (TypeEntries::is_type_none(current_klass)) {
3914 __ jmpb(next);
3915
3916 __ bind(none);
3917 // first time here. Set profile type.
3918 __ movptr(mdo_addr, tmp);
3919 }
3920 } else {
3921 // There's a single possible klass at this profile point
3922 assert(exact_klass != NULL, "should be");
3923 if (TypeEntries::is_type_none(current_klass)) {
3924 __ mov_metadata(tmp, exact_klass->constant_encoding());
3925 __ xorptr(tmp, mdo_addr);
3926 __ testptr(tmp, TypeEntries::type_klass_mask);
3927 #ifdef ASSERT
3928 __ jcc(Assembler::zero, next);
3929
3930 {
3931 Label ok;
3932 __ push(tmp);
3933 __ cmpptr(mdo_addr, 0);
3934 __ jcc(Assembler::equal, ok);
3935 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3936 __ jcc(Assembler::equal, ok);
3937 // may have been set by another thread
3938 __ mov_metadata(tmp, exact_klass->constant_encoding());
3939 __ xorptr(tmp, mdo_addr);
3940 __ testptr(tmp, TypeEntries::type_mask);
3941 __ jcc(Assembler::zero, ok);
3942
3943 __ stop("unexpected profiling mismatch");
3944 __ bind(ok);
3945 __ pop(tmp);
3946 }
3947 #else
3948 __ jccb(Assembler::zero, next);
3949 #endif
3950 // first time here. Set profile type.
3951 __ movptr(mdo_addr, tmp);
3952 } else {
3953 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3954 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3955
3956 __ movptr(tmp, mdo_addr);
3957 __ testptr(tmp, TypeEntries::type_unknown);
3958 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3959
3960 __ orptr(mdo_addr, TypeEntries::type_unknown);
3961 }
3962 }
3963
3964 __ bind(next);
3965 }
3966 }
3967
3968 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3969 Register obj = op->obj()->as_register();
3970 Register tmp = op->tmp()->as_pointer_register();
3971 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3972 bool not_null = op->not_null();
3973 int flag = op->flag();
3974
3975 Label not_inline_type;
3976 if (!not_null) {
3977 __ testptr(obj, obj);
3978 __ jccb(Assembler::zero, not_inline_type);
3979 }
3980
3981 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3982
3983 __ orb(mdo_addr, flag);
3984
3985 __ bind(not_inline_type);
3986 }
3987
3988 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3989 Unimplemented();
3990 }
3991
3992
3993 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3994 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3995 }
3996
3997
3998 void LIR_Assembler::align_backward_branch_target() {
3999 __ align(BytesPerWord);
4000 }
4001
4002
4003 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
4004 if (left->is_single_cpu()) {
4005 __ negl(left->as_register());
4006 move_regs(left->as_register(), dest->as_register());
4007
4008 } else if (left->is_double_cpu()) {
4009 Register lo = left->as_register_lo();
4010 #ifdef _LP64
4011 Register dst = dest->as_register_lo();
4012 __ movptr(dst, lo);
4013 __ negptr(dst);
4014 #else
4015 Register hi = left->as_register_hi();
4016 __ lneg(hi, lo);
4017 if (dest->as_register_lo() == hi) {
4018 assert(dest->as_register_hi() != lo, "destroying register");
4019 move_regs(hi, dest->as_register_hi());
4020 move_regs(lo, dest->as_register_lo());
4021 } else {
4022 move_regs(lo, dest->as_register_lo());
4023 move_regs(hi, dest->as_register_hi());
4024 }
4025 #endif // _LP64
4026
4027 } else if (dest->is_single_xmm()) {
4028 #ifdef _LP64
4029 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4030 assert(tmp->is_valid(), "need temporary");
4031 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
4032 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
4033 }
4034 else
4035 #endif
4036 {
4037 assert(!tmp->is_valid(), "do not need temporary");
4038 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
4039 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
4040 }
4041 __ xorps(dest->as_xmm_float_reg(),
4042 ExternalAddress((address)float_signflip_pool));
4043 }
4044 } else if (dest->is_double_xmm()) {
4045 #ifdef _LP64
4046 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
4047 assert(tmp->is_valid(), "need temporary");
4048 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
4049 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
4050 }
4051 else
4052 #endif
4053 {
4054 assert(!tmp->is_valid(), "do not need temporary");
4055 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
4056 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
4057 }
4058 __ xorpd(dest->as_xmm_double_reg(),
4059 ExternalAddress((address)double_signflip_pool));
4060 }
4061 #ifndef _LP64
4062 } else if (left->is_single_fpu() || left->is_double_fpu()) {
4063 assert(left->fpu() == 0, "arg must be on TOS");
4064 assert(dest->fpu() == 0, "dest must be TOS");
4065 __ fchs();
4066 #endif // !_LP64
4067
4068 } else {
4069 ShouldNotReachHere();
4070 }
4071 }
4072
4073
4074 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
4075 assert(src->is_address(), "must be an address");
4076 assert(dest->is_register(), "must be a register");
4077
4078 PatchingStub* patch = NULL;
4079 if (patch_code != lir_patch_none) {
4080 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
4081 }
4082
4083 Register reg = dest->as_pointer_register();
4084 LIR_Address* addr = src->as_address_ptr();
4085 __ lea(reg, as_Address(addr));
4086
4087 if (patch != NULL) {
4088 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
4089 }
4090 }
4091
4092
4093
4094 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
4095 assert(!tmp->is_valid(), "don't need temporary");
4096 __ call(RuntimeAddress(dest));
4097 if (info != NULL) {
4098 add_call_info_here(info);
4099 }
4100 }
4101
4102
4103 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
4104 assert(type == T_LONG, "only for volatile long fields");
4105
4106 if (info != NULL) {
4107 add_debug_info_for_null_check_here(info);
4108 }
4109
4110 if (src->is_double_xmm()) {
4111 if (dest->is_double_cpu()) {
4112 #ifdef _LP64
4113 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
4114 #else
4115 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
4116 __ psrlq(src->as_xmm_double_reg(), 32);
4117 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
4118 #endif // _LP64
4119 } else if (dest->is_double_stack()) {
4120 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
4121 } else if (dest->is_address()) {
4122 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
4123 } else {
4124 ShouldNotReachHere();
4125 }
4126
4127 } else if (dest->is_double_xmm()) {
4128 if (src->is_double_stack()) {
4129 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
4130 } else if (src->is_address()) {
4131 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
4132 } else {
4133 ShouldNotReachHere();
4134 }
4135
4136 #ifndef _LP64
4137 } else if (src->is_double_fpu()) {
4138 assert(src->fpu_regnrLo() == 0, "must be TOS");
4139 if (dest->is_double_stack()) {
4140 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
4141 } else if (dest->is_address()) {
4142 __ fistp_d(as_Address(dest->as_address_ptr()));
4143 } else {
4144 ShouldNotReachHere();
4145 }
4146
4147 } else if (dest->is_double_fpu()) {
4148 assert(dest->fpu_regnrLo() == 0, "must be TOS");
4149 if (src->is_double_stack()) {
4150 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
4151 } else if (src->is_address()) {
4152 __ fild_d(as_Address(src->as_address_ptr()));
4153 } else {
4154 ShouldNotReachHere();
4155 }
4156 #endif // !_LP64
4157
4158 } else {
4159 ShouldNotReachHere();
4160 }
4161 }
4162
4163 #ifdef ASSERT
4164 // emit run-time assertion
4165 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
4166 assert(op->code() == lir_assert, "must be");
4167
4168 if (op->in_opr1()->is_valid()) {
4169 assert(op->in_opr2()->is_valid(), "both operands must be valid");
4170 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
4171 } else {
4172 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
4173 assert(op->condition() == lir_cond_always, "no other conditions allowed");
4174 }
4175
4176 Label ok;
4177 if (op->condition() != lir_cond_always) {
4178 Assembler::Condition acond = Assembler::zero;
4179 switch (op->condition()) {
4180 case lir_cond_equal: acond = Assembler::equal; break;
4181 case lir_cond_notEqual: acond = Assembler::notEqual; break;
4182 case lir_cond_less: acond = Assembler::less; break;
4183 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
4184 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
4185 case lir_cond_greater: acond = Assembler::greater; break;
4186 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
4187 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
4188 default: ShouldNotReachHere();
4189 }
4190 __ jcc(acond, ok);
4191 }
4192 if (op->halt()) {
4193 const char* str = __ code_string(op->msg());
4194 __ stop(str);
4195 } else {
4196 breakpoint();
4197 }
4198 __ bind(ok);
4199 }
4200 #endif
4201
4202 void LIR_Assembler::membar() {
4203 // QQQ sparc TSO uses this,
4204 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4205 }
4206
4207 void LIR_Assembler::membar_acquire() {
4208 // No x86 machines currently require load fences
4209 }
4210
4211 void LIR_Assembler::membar_release() {
4212 // No x86 machines currently require store fences
4213 }
4214
4215 void LIR_Assembler::membar_loadload() {
4216 // no-op
4217 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4218 }
4219
4220 void LIR_Assembler::membar_storestore() {
4221 // no-op
4222 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4223 }
4224
4225 void LIR_Assembler::membar_loadstore() {
4226 // no-op
4227 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4228 }
4229
4230 void LIR_Assembler::membar_storeload() {
4231 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4232 }
4233
4234 void LIR_Assembler::on_spin_wait() {
4235 __ pause ();
4236 }
4237
4238 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4239 assert(result_reg->is_register(), "check");
4240 #ifdef _LP64
4241 // __ get_thread(result_reg->as_register_lo());
4242 __ mov(result_reg->as_register(), r15_thread);
4243 #else
4244 __ get_thread(result_reg->as_register());
4245 #endif // _LP64
4246 }
4247
4248 void LIR_Assembler::check_orig_pc() {
4249 __ cmpptr(frame_map()->address_for_orig_pc_addr(), (int32_t)NULL_WORD);
4250 }
4251
4252 void LIR_Assembler::peephole(LIR_List*) {
4253 // do nothing for now
4254 }
4255
4256 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4257 assert(data == dest, "xchg/xadd uses only 2 operands");
4258
4259 if (data->type() == T_INT) {
4260 if (code == lir_xadd) {
4261 __ lock();
4262 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4263 } else {
4264 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4265 }
4266 } else if (data->is_oop()) {
4267 assert (code == lir_xchg, "xadd for oops");
4268 Register obj = data->as_register();
4269 #ifdef _LP64
4270 if (UseCompressedOops) {
4271 __ encode_heap_oop(obj);
4272 __ xchgl(obj, as_Address(src->as_address_ptr()));
4273 __ decode_heap_oop(obj);
4274 } else {
4275 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4276 }
4277 #else
4278 __ xchgl(obj, as_Address(src->as_address_ptr()));
4279 #endif
4280 } else if (data->type() == T_LONG) {
4281 #ifdef _LP64
4282 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4283 if (code == lir_xadd) {
4284 __ lock();
4285 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4286 } else {
4287 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4288 }
4289 #else
4290 ShouldNotReachHere();
4291 #endif
4292 } else {
4293 ShouldNotReachHere();
4294 }
4295 }
4296
4297 #undef __