1 /*
2 * Copyright (c) 1999, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_FrameMap.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "ci/ciUtilities.hpp"
32 #include "compiler/compilerDefinitions.inline.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/cardTable.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/collectedHeap.hpp"
37 #include "gc/shared/tlab_globals.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "memory/universe.hpp"
40 #include "nativeInst_x86.hpp"
41 #include "oops/compiledICHolder.hpp"
42 #include "oops/oop.inline.hpp"
43 #include "prims/jvmtiExport.hpp"
44 #include "register_x86.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/signature.hpp"
47 #include "runtime/stubRoutines.hpp"
48 #include "runtime/vframeArray.hpp"
49 #include "utilities/macros.hpp"
50 #include "vmreg_x86.inline.hpp"
51
52 // Implementation of StubAssembler
53
54 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
55 // setup registers
56 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
57 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
58 assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
59 assert(args_size >= 0, "illegal args_size");
60 bool align_stack = false;
61 #ifdef _LP64
62 // At a method handle call, the stack may not be properly aligned
63 // when returning with an exception.
64 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
65 #endif
66
67 #ifdef _LP64
68 mov(c_rarg0, thread);
69 set_num_rt_args(0); // Nothing on stack
70 #else
71 set_num_rt_args(1 + args_size);
72
73 // push java thread (becomes first argument of C function)
74 get_thread(thread);
75 push(thread);
76 #endif // _LP64
77
78 int call_offset = -1;
79 if (!align_stack) {
80 set_last_Java_frame(thread, noreg, rbp, nullptr, rscratch1);
81 } else {
82 address the_pc = pc();
83 call_offset = offset();
84 set_last_Java_frame(thread, noreg, rbp, the_pc, rscratch1);
85 andptr(rsp, -(StackAlignmentInBytes)); // Align stack
86 }
87
88 // do the call
89 call(RuntimeAddress(entry));
90 if (!align_stack) {
91 call_offset = offset();
92 }
93 // verify callee-saved register
94 #ifdef ASSERT
95 guarantee(thread != rax, "change this code");
96 push(rax);
97 { Label L;
98 get_thread(rax);
99 cmpptr(thread, rax);
100 jcc(Assembler::equal, L);
101 int3();
102 stop("StubAssembler::call_RT: rdi not callee saved?");
103 bind(L);
104 }
105 pop(rax);
106 #endif
107 reset_last_Java_frame(thread, true);
108
109 // discard thread and arguments
110 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
111
112 // check for pending exceptions
113 { Label L;
114 cmpptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
115 jcc(Assembler::equal, L);
116 // exception pending => remove activation and forward to exception handler
117 movptr(rax, Address(thread, Thread::pending_exception_offset()));
118 // make sure that the vm_results are cleared
119 if (oop_result1->is_valid()) {
120 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
121 }
122 if (metadata_result->is_valid()) {
123 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
124 }
125 if (frame_size() == no_frame_size) {
126 leave();
127 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
128 } else if (_stub_id == Runtime1::forward_exception_id) {
129 should_not_reach_here();
130 } else {
131 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
132 }
133 bind(L);
134 }
135 // get oop results if there are any and reset the values in the thread
136 if (oop_result1->is_valid()) {
137 get_vm_result(oop_result1, thread);
138 }
139 if (metadata_result->is_valid()) {
140 get_vm_result_2(metadata_result, thread);
141 }
142
143 assert(call_offset >= 0, "Should be set");
144 return call_offset;
145 }
146
147
148 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
149 #ifdef _LP64
150 mov(c_rarg1, arg1);
151 #else
152 push(arg1);
153 #endif // _LP64
154 return call_RT(oop_result1, metadata_result, entry, 1);
155 }
156
157
158 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
159 #ifdef _LP64
160 if (c_rarg1 == arg2) {
161 if (c_rarg2 == arg1) {
162 xchgq(arg1, arg2);
163 } else {
164 mov(c_rarg2, arg2);
165 mov(c_rarg1, arg1);
166 }
167 } else {
168 mov(c_rarg1, arg1);
169 mov(c_rarg2, arg2);
170 }
171 #else
172 push(arg2);
173 push(arg1);
174 #endif // _LP64
175 return call_RT(oop_result1, metadata_result, entry, 2);
176 }
177
178
179 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
180 #ifdef _LP64
181 // if there is any conflict use the stack
182 if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
183 arg2 == c_rarg1 || arg2 == c_rarg3 ||
184 arg3 == c_rarg1 || arg3 == c_rarg2) {
185 push(arg3);
186 push(arg2);
187 push(arg1);
188 pop(c_rarg1);
189 pop(c_rarg2);
190 pop(c_rarg3);
191 } else {
192 mov(c_rarg1, arg1);
193 mov(c_rarg2, arg2);
194 mov(c_rarg3, arg3);
195 }
196 #else
197 push(arg3);
198 push(arg2);
199 push(arg1);
200 #endif // _LP64
201 return call_RT(oop_result1, metadata_result, entry, 3);
202 }
203
204
205 // Implementation of StubFrame
206
207 class StubFrame: public StackObj {
208 private:
209 StubAssembler* _sasm;
210
211 public:
212 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
213 void load_argument(int offset_in_words, Register reg);
214
215 ~StubFrame();
216 };
217
218 void StubAssembler::prologue(const char* name, bool must_gc_arguments) {
219 set_info(name, must_gc_arguments);
220 enter();
221 }
222
223 void StubAssembler::epilogue() {
224 leave();
225 ret(0);
226 }
227
228 #define __ _sasm->
229
230 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
231 _sasm = sasm;
232 __ prologue(name, must_gc_arguments);
233 }
234
235 // load parameters that were stored with LIR_Assembler::store_parameter
236 // Note: offsets for store_parameter and load_argument must match
237 void StubFrame::load_argument(int offset_in_words, Register reg) {
238 __ load_parameter(offset_in_words, reg);
239 }
240
241
242 StubFrame::~StubFrame() {
243 __ epilogue();
244 }
245
246 #undef __
247
248
249 // Implementation of Runtime1
250
251 const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
252 const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
253
254 // Stack layout for saving/restoring all the registers needed during a runtime
255 // call (this includes deoptimization)
256 // Note: note that users of this frame may well have arguments to some runtime
257 // while these values are on the stack. These positions neglect those arguments
258 // but the code in save_live_registers will take the argument count into
259 // account.
260 //
261 #ifdef _LP64
262 #define SLOT2(x) x,
263 #define SLOT_PER_WORD 2
264 #else
265 #define SLOT2(x)
266 #define SLOT_PER_WORD 1
267 #endif // _LP64
268
269 enum reg_save_layout {
270 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
271 // happen and will assert if the stack size we create is misaligned
272 #ifdef _LP64
273 align_dummy_0, align_dummy_1,
274 #endif // _LP64
275 #ifdef _WIN64
276 // Windows always allocates space for it's argument registers (see
277 // frame::arg_reg_save_area_bytes).
278 arg_reg_save_1, arg_reg_save_1H, // 0, 4
279 arg_reg_save_2, arg_reg_save_2H, // 8, 12
280 arg_reg_save_3, arg_reg_save_3H, // 16, 20
281 arg_reg_save_4, arg_reg_save_4H, // 24, 28
282 #endif // _WIN64
283 xmm_regs_as_doubles_off, // 32
284 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
285 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
286 // fpu_state_end_off is exclusive
287 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
288 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
289 extra_space_offset, // 360
290 #ifdef _LP64
291 r15_off = extra_space_offset, r15H_off, // 360, 364
292 r14_off, r14H_off, // 368, 372
293 r13_off, r13H_off, // 376, 380
294 r12_off, r12H_off, // 384, 388
295 r11_off, r11H_off, // 392, 396
296 r10_off, r10H_off, // 400, 404
297 r9_off, r9H_off, // 408, 412
298 r8_off, r8H_off, // 416, 420
299 rdi_off, rdiH_off, // 424, 428
300 #else
301 rdi_off = extra_space_offset,
302 #endif // _LP64
303 rsi_off, SLOT2(rsiH_off) // 432, 436
304 rbp_off, SLOT2(rbpH_off) // 440, 444
305 rsp_off, SLOT2(rspH_off) // 448, 452
306 rbx_off, SLOT2(rbxH_off) // 456, 460
307 rdx_off, SLOT2(rdxH_off) // 464, 468
308 rcx_off, SLOT2(rcxH_off) // 472, 476
309 rax_off, SLOT2(raxH_off) // 480, 484
310 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
311 return_off, SLOT2(returnH_off) // 496, 500
312 reg_save_frame_size // As noted: neglects any parameters to runtime // 504
313 };
314
315 // Save off registers which might be killed by calls into the runtime.
316 // Tries to smart of about FP registers. In particular we separate
317 // saving and describing the FPU registers for deoptimization since we
318 // have to save the FPU registers twice if we describe them and on P4
319 // saving FPU registers which don't contain anything appears
320 // expensive. The deopt blob is the only thing which needs to
321 // describe FPU registers. In all other cases it should be sufficient
322 // to simply save their current value.
323 //
324 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
325 bool save_fpu_registers = true) {
326
327 // In 64bit all the args are in regs so there are no additional stack slots
328 LP64_ONLY(num_rt_args = 0);
329 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
330 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
331 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word);
332
333 // record saved value locations in an OopMap
334 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
335 OopMap* map = new OopMap(frame_size_in_slots, 0);
336 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
337 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
338 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
339 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
340 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
341 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
342 #ifdef _LP64
343 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
344 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
345 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
346 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
347 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
348 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
349 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
350 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
351
352 // This is stupid but needed.
353 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
354 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
355 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
356 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
357 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
358 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
359
360 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
361 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
362 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
363 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
364 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
365 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
366 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
367 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
368 #endif // _LP64
369
370 int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
371
372 if (save_fpu_registers) {
373 #ifndef _LP64
374 if (UseSSE < 2) {
375 int fpu_off = float_regs_as_doubles_off;
376 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
377 VMReg fpu_name_0 = FrameMap::fpu_regname(n);
378 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0);
379 // %%% This is really a waste but we'll keep things as they were for now
380 if (true) {
381 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());
382 }
383 fpu_off += 2;
384 }
385 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");
386
387 if (UseSSE == 1) {
388 int xmm_off = xmm_regs_as_doubles_off;
389 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
390 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
391 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
392 xmm_off += 2;
393 }
394 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
395 }
396 }
397 #endif // !LP64
398
399 if (UseSSE >= 2) {
400 int xmm_off = xmm_regs_as_doubles_off;
401 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
402 if (n < xmm_bypass_limit) {
403 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
404 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
405 // %%% This is really a waste but we'll keep things as they were for now
406 if (true) {
407 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
408 }
409 }
410 xmm_off += 2;
411 }
412 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
413 }
414 }
415
416 return map;
417 }
418
419 #define __ this->
420
421 void C1_MacroAssembler::save_live_registers_no_oop_map(bool save_fpu_registers) {
422 __ block_comment("save_live_registers");
423
424 __ pusha(); // integer registers
425
426 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
427 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
428
429 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
430
431 #ifdef ASSERT
432 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
433 #endif
434
435 if (save_fpu_registers) {
436 #ifndef _LP64
437 if (UseSSE < 2) {
438 // save FPU stack
439 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
440 __ fwait();
441
442 #ifdef ASSERT
443 Label ok;
444 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::x86::fpu_cntrl_wrd_std());
445 __ jccb(Assembler::equal, ok);
446 __ stop("corrupted control word detected");
447 __ bind(ok);
448 #endif
449
450 // Reset the control word to guard against exceptions being unmasked
451 // since fstp_d can cause FPU stack underflow exceptions. Write it
452 // into the on stack copy and then reload that to make sure that the
453 // current and future values are correct.
454 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::x86::fpu_cntrl_wrd_std());
455 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
456
457 // Save the FPU registers in de-opt-able form
458 int offset = 0;
459 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
460 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
461 offset += 8;
462 }
463
464 if (UseSSE == 1) {
465 // save XMM registers as float because double not supported without SSE2(num MMX == num fpu)
466 int offset = 0;
467 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
468 XMMRegister xmm_name = as_XMMRegister(n);
469 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
470 offset += 8;
471 }
472 }
473 }
474 #endif // !_LP64
475
476 if (UseSSE >= 2) {
477 // save XMM registers
478 // XMM registers can contain float or double values, but this is not known here,
479 // so always save them as doubles.
480 // note that float values are _not_ converted automatically, so for float values
481 // the second word contains only garbage data.
482 int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
483 int offset = 0;
484 for (int n = 0; n < xmm_bypass_limit; n++) {
485 XMMRegister xmm_name = as_XMMRegister(n);
486 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
487 offset += 8;
488 }
489 }
490 }
491
492 // FPU stack must be empty now
493 NOT_LP64( __ verify_FPU(0, "save_live_registers"); )
494 }
495
496 #undef __
497 #define __ sasm->
498
499 static void restore_fpu(C1_MacroAssembler* sasm, bool restore_fpu_registers) {
500 #ifdef _LP64
501 if (restore_fpu_registers) {
502 // restore XMM registers
503 int xmm_bypass_limit = FrameMap::get_num_caller_save_xmms();
504 int offset = 0;
505 for (int n = 0; n < xmm_bypass_limit; n++) {
506 XMMRegister xmm_name = as_XMMRegister(n);
507 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
508 offset += 8;
509 }
510 }
511 #else
512 if (restore_fpu_registers) {
513 if (UseSSE >= 2) {
514 // restore XMM registers
515 int xmm_bypass_limit = FrameMap::nof_xmm_regs;
516 int offset = 0;
517 for (int n = 0; n < xmm_bypass_limit; n++) {
518 XMMRegister xmm_name = as_XMMRegister(n);
519 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
520 offset += 8;
521 }
522 } else if (UseSSE == 1) {
523 // restore XMM registers(num MMX == num fpu)
524 int offset = 0;
525 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
526 XMMRegister xmm_name = as_XMMRegister(n);
527 __ movflt(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
528 offset += 8;
529 }
530 }
531
532 if (UseSSE < 2) {
533 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
534 } else {
535 // check that FPU stack is really empty
536 __ verify_FPU(0, "restore_live_registers");
537 }
538 } else {
539 // check that FPU stack is really empty
540 __ verify_FPU(0, "restore_live_registers");
541 }
542 #endif // _LP64
543
544 #ifdef ASSERT
545 {
546 Label ok;
547 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
548 __ jcc(Assembler::equal, ok);
549 __ stop("bad offsets in frame");
550 __ bind(ok);
551 }
552 #endif // ASSERT
553
554 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
555 }
556
557 #undef __
558 #define __ this->
559
560 void C1_MacroAssembler::restore_live_registers(bool restore_fpu_registers) {
561 __ block_comment("restore_live_registers");
562
563 restore_fpu(this, restore_fpu_registers);
564 __ popa();
565 }
566
567
568 void C1_MacroAssembler::restore_live_registers_except_rax(bool restore_fpu_registers) {
569 __ block_comment("restore_live_registers_except_rax");
570
571 restore_fpu(this, restore_fpu_registers);
572
573 #ifdef _LP64
574 __ movptr(r15, Address(rsp, 0));
575 __ movptr(r14, Address(rsp, wordSize));
576 __ movptr(r13, Address(rsp, 2 * wordSize));
577 __ movptr(r12, Address(rsp, 3 * wordSize));
578 __ movptr(r11, Address(rsp, 4 * wordSize));
579 __ movptr(r10, Address(rsp, 5 * wordSize));
580 __ movptr(r9, Address(rsp, 6 * wordSize));
581 __ movptr(r8, Address(rsp, 7 * wordSize));
582 __ movptr(rdi, Address(rsp, 8 * wordSize));
583 __ movptr(rsi, Address(rsp, 9 * wordSize));
584 __ movptr(rbp, Address(rsp, 10 * wordSize));
585 // skip rsp
586 __ movptr(rbx, Address(rsp, 12 * wordSize));
587 __ movptr(rdx, Address(rsp, 13 * wordSize));
588 __ movptr(rcx, Address(rsp, 14 * wordSize));
589
590 __ addptr(rsp, 16 * wordSize);
591 #else
592
593 __ pop(rdi);
594 __ pop(rsi);
595 __ pop(rbp);
596 __ pop(rbx); // skip this value
597 __ pop(rbx);
598 __ pop(rdx);
599 __ pop(rcx);
600 __ addptr(rsp, BytesPerWord);
601 #endif // _LP64
602 }
603
604 #undef __
605 #define __ sasm->
606
607 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
608 bool save_fpu_registers = true) {
609 __ save_live_registers_no_oop_map(save_fpu_registers);
610 return generate_oop_map(sasm, num_rt_args, save_fpu_registers);
611 }
612
613 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
614 __ restore_live_registers(restore_fpu_registers);
615 }
616
617 static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) {
618 sasm->restore_live_registers_except_rax(restore_fpu_registers);
619 }
620
621
622 void Runtime1::initialize_pd() {
623 // nothing to do
624 }
625
626
627 // Target: the entry point of the method that creates and posts the exception oop.
628 // has_argument: true if the exception needs arguments (passed on the stack because
629 // registers must be preserved).
630 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
631 // Preserve all registers.
632 int num_rt_args = has_argument ? (2 + 1) : 1;
633 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
634
635 // Now all registers are saved and can be used freely.
636 // Verify that no old value is used accidentally.
637 __ invalidate_registers(true, true, true, true, true, true);
638
639 // Registers used by this stub.
640 const Register temp_reg = rbx;
641
642 // Load arguments for exception that are passed as arguments into the stub.
643 if (has_argument) {
644 #ifdef _LP64
645 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
646 __ movptr(c_rarg2, Address(rbp, 3*BytesPerWord));
647 #else
648 __ movptr(temp_reg, Address(rbp, 3*BytesPerWord));
649 __ push(temp_reg);
650 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
651 __ push(temp_reg);
652 #endif // _LP64
653 }
654 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
655
656 OopMapSet* oop_maps = new OopMapSet();
657 oop_maps->add_gc_map(call_offset, oop_map);
658
659 __ stop("should not reach here");
660
661 return oop_maps;
662 }
663
664
665 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
666 __ block_comment("generate_handle_exception");
667
668 // incoming parameters
669 const Register exception_oop = rax;
670 const Register exception_pc = rdx;
671 // other registers used in this stub
672 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
673
674 // Save registers, if required.
675 OopMapSet* oop_maps = new OopMapSet();
676 OopMap* oop_map = nullptr;
677 switch (id) {
678 case forward_exception_id:
679 // We're handling an exception in the context of a compiled frame.
680 // The registers have been saved in the standard places. Perform
681 // an exception lookup in the caller and dispatch to the handler
682 // if found. Otherwise unwind and dispatch to the callers
683 // exception handler.
684 oop_map = generate_oop_map(sasm, 1 /*thread*/);
685
686 // load and clear pending exception oop into RAX
687 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
688 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
689
690 // load issuing PC (the return address for this stub) into rdx
691 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
692
693 // make sure that the vm_results are cleared (may be unnecessary)
694 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
695 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
696 break;
697 case handle_exception_nofpu_id:
698 case handle_exception_id:
699 // At this point all registers MAY be live.
700 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
701 break;
702 case handle_exception_from_callee_id: {
703 // At this point all registers except exception oop (RAX) and
704 // exception pc (RDX) are dead.
705 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord);
706 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
707 sasm->set_frame_size(frame_size);
708 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes));
709 break;
710 }
711 default: ShouldNotReachHere();
712 }
713
714 #if !defined(_LP64) && defined(COMPILER2)
715 if (UseSSE < 2 && !CompilerConfig::is_c1_only_no_jvmci()) {
716 // C2 can leave the fpu stack dirty
717 __ empty_FPU_stack();
718 }
719 #endif // !_LP64 && COMPILER2
720
721 // verify that only rax, and rdx is valid at this time
722 __ invalidate_registers(false, true, true, false, true, true);
723 // verify that rax, contains a valid exception
724 __ verify_not_null_oop(exception_oop);
725
726 // load address of JavaThread object for thread-local data
727 NOT_LP64(__ get_thread(thread);)
728
729 #ifdef ASSERT
730 // check that fields in JavaThread for exception oop and issuing pc are
731 // empty before writing to them
732 Label oop_empty;
733 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
734 __ jcc(Assembler::equal, oop_empty);
735 __ stop("exception oop already set");
736 __ bind(oop_empty);
737
738 Label pc_empty;
739 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
740 __ jcc(Assembler::equal, pc_empty);
741 __ stop("exception pc already set");
742 __ bind(pc_empty);
743 #endif
744
745 // save exception oop and issuing pc into JavaThread
746 // (exception handler will load it from here)
747 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
748 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
749
750 // patch throwing pc into return address (has bci & oop map)
751 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
752
753 // compute the exception handler.
754 // the exception oop and the throwing pc are read from the fields in JavaThread
755 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
756 oop_maps->add_gc_map(call_offset, oop_map);
757
758 // rax: handler address
759 // will be the deopt blob if nmethod was deoptimized while we looked up
760 // handler regardless of whether handler existed in the nmethod.
761
762 // only rax, is valid at this time, all other registers have been destroyed by the runtime call
763 __ invalidate_registers(false, true, true, true, true, true);
764
765 // patch the return address, this stub will directly return to the exception handler
766 __ movptr(Address(rbp, 1*BytesPerWord), rax);
767
768 switch (id) {
769 case forward_exception_id:
770 case handle_exception_nofpu_id:
771 case handle_exception_id:
772 // Restore the registers that were saved at the beginning.
773 restore_live_registers(sasm, id != handle_exception_nofpu_id);
774 break;
775 case handle_exception_from_callee_id:
776 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
777 // since we do a leave anyway.
778
779 // Pop the return address.
780 __ leave();
781 __ pop(rcx);
782 __ jmp(rcx); // jump to exception handler
783 break;
784 default: ShouldNotReachHere();
785 }
786
787 return oop_maps;
788 }
789
790
791 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
792 // incoming parameters
793 const Register exception_oop = rax;
794 // callee-saved copy of exception_oop during runtime call
795 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14);
796 // other registers used in this stub
797 const Register exception_pc = rdx;
798 const Register handler_addr = rbx;
799 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
800
801 if (AbortVMOnException) {
802 __ enter();
803 save_live_registers(sasm, 2);
804 __ call_VM_leaf(CAST_FROM_FN_PTR(address, check_abort_on_vm_exception), rax);
805 restore_live_registers(sasm);
806 __ leave();
807 }
808
809 // verify that only rax, is valid at this time
810 __ invalidate_registers(false, true, true, true, true, true);
811
812 #ifdef ASSERT
813 // check that fields in JavaThread for exception oop and issuing pc are empty
814 NOT_LP64(__ get_thread(thread);)
815 Label oop_empty;
816 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
817 __ jcc(Assembler::equal, oop_empty);
818 __ stop("exception oop must be empty");
819 __ bind(oop_empty);
820
821 Label pc_empty;
822 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
823 __ jcc(Assembler::equal, pc_empty);
824 __ stop("exception pc must be empty");
825 __ bind(pc_empty);
826 #endif
827
828 // clear the FPU stack in case any FPU results are left behind
829 NOT_LP64( __ empty_FPU_stack(); )
830
831 // save exception_oop in callee-saved register to preserve it during runtime calls
832 __ verify_not_null_oop(exception_oop);
833 __ movptr(exception_oop_callee_saved, exception_oop);
834
835 NOT_LP64(__ get_thread(thread);)
836 // Get return address (is on top of stack after leave).
837 __ movptr(exception_pc, Address(rsp, 0));
838
839 // search the exception handler address of the caller (using the return address)
840 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
841 // rax: exception handler address of the caller
842
843 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call.
844 __ invalidate_registers(false, true, true, true, false, true);
845
846 // move result of call into correct register
847 __ movptr(handler_addr, rax);
848
849 // Restore exception oop to RAX (required convention of exception handler).
850 __ movptr(exception_oop, exception_oop_callee_saved);
851
852 // verify that there is really a valid exception in rax
853 __ verify_not_null_oop(exception_oop);
854
855 // get throwing pc (= return address).
856 // rdx has been destroyed by the call, so it must be set again
857 // the pop is also necessary to simulate the effect of a ret(0)
858 __ pop(exception_pc);
859
860 // continue at exception handler (return address removed)
861 // note: do *not* remove arguments when unwinding the
862 // activation since the caller assumes having
863 // all arguments on the stack when entering the
864 // runtime to determine the exception handler
865 // (GC happens at call site with arguments!)
866 // rax: exception oop
867 // rdx: throwing pc
868 // rbx: exception handler
869 __ jmp(handler_addr);
870 }
871
872
873 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
874 // use the maximum number of runtime-arguments here because it is difficult to
875 // distinguish each RT-Call.
876 // Note: This number affects also the RT-Call in generate_handle_exception because
877 // the oop-map is shared for all calls.
878 const int num_rt_args = 2; // thread + dummy
879
880 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
881 assert(deopt_blob != nullptr, "deoptimization blob must have been created");
882
883 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
884
885 #ifdef _LP64
886 const Register thread = r15_thread;
887 // No need to worry about dummy
888 __ mov(c_rarg0, thread);
889 #else
890 __ push(rax); // push dummy
891
892 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
893 // push java thread (becomes first argument of C function)
894 __ get_thread(thread);
895 __ push(thread);
896 #endif // _LP64
897 __ set_last_Java_frame(thread, noreg, rbp, nullptr, rscratch1);
898 // do the call
899 __ call(RuntimeAddress(target));
900 OopMapSet* oop_maps = new OopMapSet();
901 oop_maps->add_gc_map(__ offset(), oop_map);
902 // verify callee-saved register
903 #ifdef ASSERT
904 guarantee(thread != rax, "change this code");
905 __ push(rax);
906 { Label L;
907 __ get_thread(rax);
908 __ cmpptr(thread, rax);
909 __ jcc(Assembler::equal, L);
910 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
911 __ bind(L);
912 }
913 __ pop(rax);
914 #endif
915 __ reset_last_Java_frame(thread, true);
916 #ifndef _LP64
917 __ pop(rcx); // discard thread arg
918 __ pop(rcx); // discard dummy
919 #endif // _LP64
920
921 // check for pending exceptions
922 { Label L;
923 __ cmpptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
924 __ jcc(Assembler::equal, L);
925 // exception pending => remove activation and forward to exception handler
926
927 __ testptr(rax, rax); // have we deoptimized?
928 __ jump_cc(Assembler::equal,
929 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
930
931 // the deopt blob expects exceptions in the special fields of
932 // JavaThread, so copy and clear pending exception.
933
934 // load and clear pending exception
935 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
936 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
937
938 // check that there is really a valid exception
939 __ verify_not_null_oop(rax);
940
941 // load throwing pc: this is the return address of the stub
942 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
943
944 #ifdef ASSERT
945 // check that fields in JavaThread for exception oop and issuing pc are empty
946 Label oop_empty;
947 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
948 __ jcc(Assembler::equal, oop_empty);
949 __ stop("exception oop must be empty");
950 __ bind(oop_empty);
951
952 Label pc_empty;
953 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
954 __ jcc(Assembler::equal, pc_empty);
955 __ stop("exception pc must be empty");
956 __ bind(pc_empty);
957 #endif
958
959 // store exception oop and throwing pc to JavaThread
960 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
961 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
962
963 restore_live_registers(sasm);
964
965 __ leave();
966 __ addptr(rsp, BytesPerWord); // remove return address from stack
967
968 // Forward the exception directly to deopt blob. We can blow no
969 // registers and must leave throwing pc on the stack. A patch may
970 // have values live in registers so the entry point with the
971 // exception in tls.
972 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls()));
973
974 __ bind(L);
975 }
976
977
978 // Runtime will return true if the nmethod has been deoptimized during
979 // the patching process. In that case we must do a deopt reexecute instead.
980
981 Label cont;
982
983 __ testptr(rax, rax); // have we deoptimized?
984 __ jcc(Assembler::equal, cont); // no
985
986 // Will reexecute. Proper return address is already on the stack we just restore
987 // registers, pop all of our frame but the return address and jump to the deopt blob
988 restore_live_registers(sasm);
989 __ leave();
990 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
991
992 __ bind(cont);
993 restore_live_registers(sasm);
994 __ leave();
995 __ ret(0);
996
997 return oop_maps;
998 }
999
1000
1001 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
1002
1003 // for better readability
1004 const bool must_gc_arguments = true;
1005 const bool dont_gc_arguments = false;
1006
1007 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu
1008 bool save_fpu_registers = true;
1009
1010 // stub code & info for the different stubs
1011 OopMapSet* oop_maps = nullptr;
1012 switch (id) {
1013 case forward_exception_id:
1014 {
1015 oop_maps = generate_handle_exception(id, sasm);
1016 __ leave();
1017 __ ret(0);
1018 }
1019 break;
1020
1021 case new_instance_id:
1022 case fast_new_instance_id:
1023 case fast_new_instance_init_check_id:
1024 {
1025 Register klass = rdx; // Incoming
1026 Register obj = rax; // Result
1027
1028 if (id == new_instance_id) {
1029 __ set_info("new_instance", dont_gc_arguments);
1030 } else if (id == fast_new_instance_id) {
1031 __ set_info("fast new_instance", dont_gc_arguments);
1032 } else {
1033 assert(id == fast_new_instance_init_check_id, "bad StubID");
1034 __ set_info("fast new_instance init check", dont_gc_arguments);
1035 }
1036
1037 __ enter();
1038 OopMap* map = save_live_registers(sasm, 2);
1039 int call_offset;
1040 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
1041 oop_maps = new OopMapSet();
1042 oop_maps->add_gc_map(call_offset, map);
1043 restore_live_registers_except_rax(sasm);
1044 __ verify_oop(obj);
1045 __ leave();
1046 __ ret(0);
1047
1048 // rax,: new instance
1049 }
1050
1051 break;
1052
1053 case counter_overflow_id:
1054 {
1055 Register bci = rax, method = rbx;
1056 __ enter();
1057 OopMap* map = save_live_registers(sasm, 3);
1058 // Retrieve bci
1059 __ movl(bci, Address(rbp, 2*BytesPerWord));
1060 // And a pointer to the Method*
1061 __ movptr(method, Address(rbp, 3*BytesPerWord));
1062 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1063 oop_maps = new OopMapSet();
1064 oop_maps->add_gc_map(call_offset, map);
1065 restore_live_registers(sasm);
1066 __ leave();
1067 __ ret(0);
1068 }
1069 break;
1070
1071 case new_type_array_id:
1072 case new_object_array_id:
1073 case new_flat_array_id:
1074 {
1075 Register length = rbx; // Incoming
1076 Register klass = rdx; // Incoming
1077 Register obj = rax; // Result
1078
1079 if (id == new_type_array_id) {
1080 __ set_info("new_type_array", dont_gc_arguments);
1081 } else if (id == new_object_array_id) {
1082 __ set_info("new_object_array", dont_gc_arguments);
1083 } else {
1084 __ set_info("new_flat_array", dont_gc_arguments);
1085 }
1086
1087 #ifdef ASSERT
1088 // assert object type is really an array of the proper kind
1089 {
1090 Label ok;
1091 Register t0 = obj;
1092 __ movl(t0, Address(klass, Klass::layout_helper_offset()));
1093 __ sarl(t0, Klass::_lh_array_tag_shift);
1094 switch (id) {
1095 case new_type_array_id:
1096 __ cmpl(t0, Klass::_lh_array_tag_type_value);
1097 __ jcc(Assembler::equal, ok);
1098 __ stop("assert(is a type array klass)");
1099 break;
1100 case new_object_array_id:
1101 __ cmpl(t0, Klass::_lh_array_tag_obj_value); // new "[Ljava/lang/Object;"
1102 __ jcc(Assembler::equal, ok);
1103 __ cmpl(t0, Klass::_lh_array_tag_vt_value); // new "[LVT;"
1104 __ jcc(Assembler::equal, ok);
1105 __ stop("assert(is an object or inline type array klass)");
1106 break;
1107 case new_flat_array_id:
1108 // TODO 8325106 Fix comment
1109 // new "[QVT;"
1110 __ cmpl(t0, Klass::_lh_array_tag_vt_value); // the array can be a flat array.
1111 __ jcc(Assembler::equal, ok);
1112 __ cmpl(t0, Klass::_lh_array_tag_obj_value); // the array cannot be a flat array (due to InlineArrayElementMaxFlatSize, etc)
1113 __ jcc(Assembler::equal, ok);
1114 __ stop("assert(is an object or inline type array klass)");
1115 break;
1116 default: ShouldNotReachHere();
1117 }
1118 __ should_not_reach_here();
1119 __ bind(ok);
1120 }
1121 #endif // ASSERT
1122
1123 __ enter();
1124 OopMap* map = save_live_registers(sasm, 3);
1125 int call_offset;
1126 if (id == new_type_array_id) {
1127 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
1128 } else if (id == new_object_array_id) {
1129 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
1130 } else {
1131 assert(id == new_flat_array_id, "must be");
1132 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_flat_array), klass, length);
1133 }
1134
1135 oop_maps = new OopMapSet();
1136 oop_maps->add_gc_map(call_offset, map);
1137 restore_live_registers_except_rax(sasm);
1138
1139 __ verify_oop(obj);
1140 __ leave();
1141 __ ret(0);
1142
1143 // rax,: new array
1144 }
1145 break;
1146
1147 case new_multi_array_id:
1148 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
1149 // rax,: klass
1150 // rbx,: rank
1151 // rcx: address of 1st dimension
1152 OopMap* map = save_live_registers(sasm, 4);
1153 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx);
1154
1155 oop_maps = new OopMapSet();
1156 oop_maps->add_gc_map(call_offset, map);
1157 restore_live_registers_except_rax(sasm);
1158
1159 // rax,: new multi array
1160 __ verify_oop(rax);
1161 }
1162 break;
1163
1164 case load_flat_array_id:
1165 {
1166 StubFrame f(sasm, "load_flat_array", dont_gc_arguments);
1167 OopMap* map = save_live_registers(sasm, 3);
1168
1169 // Called with store_parameter and not C abi
1170
1171 f.load_argument(1, rax); // rax,: array
1172 f.load_argument(0, rbx); // rbx,: index
1173 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, load_flat_array), rax, rbx);
1174
1175 oop_maps = new OopMapSet();
1176 oop_maps->add_gc_map(call_offset, map);
1177 restore_live_registers_except_rax(sasm);
1178
1179 // rax,: loaded element at array[index]
1180 __ verify_oop(rax);
1181 }
1182 break;
1183
1184 case store_flat_array_id:
1185 {
1186 StubFrame f(sasm, "store_flat_array", dont_gc_arguments);
1187 OopMap* map = save_live_registers(sasm, 4);
1188
1189 // Called with store_parameter and not C abi
1190
1191 f.load_argument(2, rax); // rax,: array
1192 f.load_argument(1, rbx); // rbx,: index
1193 f.load_argument(0, rcx); // rcx,: value
1194 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, store_flat_array), rax, rbx, rcx);
1195
1196 oop_maps = new OopMapSet();
1197 oop_maps->add_gc_map(call_offset, map);
1198 restore_live_registers_except_rax(sasm);
1199 }
1200 break;
1201
1202 case substitutability_check_id:
1203 {
1204 StubFrame f(sasm, "substitutability_check", dont_gc_arguments);
1205 OopMap* map = save_live_registers(sasm, 3);
1206
1207 // Called with store_parameter and not C abi
1208
1209 f.load_argument(1, rax); // rax,: left
1210 f.load_argument(0, rbx); // rbx,: right
1211 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, substitutability_check), rax, rbx);
1212
1213 oop_maps = new OopMapSet();
1214 oop_maps->add_gc_map(call_offset, map);
1215 restore_live_registers_except_rax(sasm);
1216
1217 // rax,: are the two operands substitutable
1218 }
1219 break;
1220
1221
1222 case buffer_inline_args_id:
1223 case buffer_inline_args_no_receiver_id:
1224 {
1225 const char* name = (id == buffer_inline_args_id) ?
1226 "buffer_inline_args" : "buffer_inline_args_no_receiver";
1227 StubFrame f(sasm, name, dont_gc_arguments);
1228 OopMap* map = save_live_registers(sasm, 2);
1229 Register method = rbx;
1230 address entry = (id == buffer_inline_args_id) ?
1231 CAST_FROM_FN_PTR(address, buffer_inline_args) :
1232 CAST_FROM_FN_PTR(address, buffer_inline_args_no_receiver);
1233 int call_offset = __ call_RT(rax, noreg, entry, method);
1234 oop_maps = new OopMapSet();
1235 oop_maps->add_gc_map(call_offset, map);
1236 restore_live_registers_except_rax(sasm);
1237 __ verify_oop(rax); // rax: an array of buffered value objects
1238 }
1239 break;
1240
1241 case register_finalizer_id:
1242 {
1243 __ set_info("register_finalizer", dont_gc_arguments);
1244
1245 // This is called via call_runtime so the arguments
1246 // will be place in C abi locations
1247
1248 #ifdef _LP64
1249 __ verify_oop(c_rarg0);
1250 __ mov(rax, c_rarg0);
1251 #else
1252 // The object is passed on the stack and we haven't pushed a
1253 // frame yet so it's one work away from top of stack.
1254 __ movptr(rax, Address(rsp, 1 * BytesPerWord));
1255 __ verify_oop(rax);
1256 #endif // _LP64
1257
1258 // load the klass and check the has finalizer flag
1259 Label register_finalizer;
1260 Register t = rsi;
1261 __ load_klass(t, rax, rscratch1);
1262 __ movl(t, Address(t, Klass::access_flags_offset()));
1263 __ testl(t, JVM_ACC_HAS_FINALIZER);
1264 __ jcc(Assembler::notZero, register_finalizer);
1265 __ ret(0);
1266
1267 __ bind(register_finalizer);
1268 __ enter();
1269 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */);
1270 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax);
1271 oop_maps = new OopMapSet();
1272 oop_maps->add_gc_map(call_offset, oop_map);
1273
1274 // Now restore all the live registers
1275 restore_live_registers(sasm);
1276
1277 __ leave();
1278 __ ret(0);
1279 }
1280 break;
1281
1282 case throw_range_check_failed_id:
1283 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
1284 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
1285 }
1286 break;
1287
1288 case throw_index_exception_id:
1289 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
1290 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
1291 }
1292 break;
1293
1294 case throw_div0_exception_id:
1295 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
1296 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
1297 }
1298 break;
1299
1300 case throw_null_pointer_exception_id:
1301 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
1302 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
1303 }
1304 break;
1305
1306 case handle_exception_nofpu_id:
1307 case handle_exception_id:
1308 { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
1309 oop_maps = generate_handle_exception(id, sasm);
1310 }
1311 break;
1312
1313 case handle_exception_from_callee_id:
1314 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
1315 oop_maps = generate_handle_exception(id, sasm);
1316 }
1317 break;
1318
1319 case unwind_exception_id:
1320 { __ set_info("unwind_exception", dont_gc_arguments);
1321 // note: no stubframe since we are about to leave the current
1322 // activation and we are calling a leaf VM function only.
1323 generate_unwind_exception(sasm);
1324 }
1325 break;
1326
1327 case throw_array_store_exception_id:
1328 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
1329 // tos + 0: link
1330 // + 1: return address
1331 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1332 }
1333 break;
1334
1335 case throw_class_cast_exception_id:
1336 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
1337 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1338 }
1339 break;
1340
1341 case throw_incompatible_class_change_error_id:
1342 { StubFrame f(sasm, "throw_incompatible_class_change_error", dont_gc_arguments);
1343 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1344 }
1345 break;
1346
1347 case throw_illegal_monitor_state_exception_id:
1348 { StubFrame f(sasm, "throw_illegal_monitor_state_exception", dont_gc_arguments);
1349 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_illegal_monitor_state_exception), false);
1350 }
1351 break;
1352
1353 case slow_subtype_check_id:
1354 {
1355 // Typical calling sequence:
1356 // __ push(klass_RInfo); // object klass or other subclass
1357 // __ push(sup_k_RInfo); // array element klass or other superclass
1358 // __ call(slow_subtype_check);
1359 // Note that the subclass is pushed first, and is therefore deepest.
1360 // Previous versions of this code reversed the names 'sub' and 'super'.
1361 // This was operationally harmless but made the code unreadable.
1362 enum layout {
1363 rax_off, SLOT2(raxH_off)
1364 rcx_off, SLOT2(rcxH_off)
1365 rsi_off, SLOT2(rsiH_off)
1366 rdi_off, SLOT2(rdiH_off)
1367 // saved_rbp_off, SLOT2(saved_rbpH_off)
1368 return_off, SLOT2(returnH_off)
1369 sup_k_off, SLOT2(sup_kH_off)
1370 klass_off, SLOT2(superH_off)
1371 framesize,
1372 result_off = klass_off // deepest argument is also the return value
1373 };
1374
1375 __ set_info("slow_subtype_check", dont_gc_arguments);
1376 __ push(rdi);
1377 __ push(rsi);
1378 __ push(rcx);
1379 __ push(rax);
1380
1381 // This is called by pushing args and not with C abi
1382 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass
1383 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass
1384
1385 Label miss;
1386 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, nullptr, &miss);
1387
1388 // fallthrough on success:
1389 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result
1390 __ pop(rax);
1391 __ pop(rcx);
1392 __ pop(rsi);
1393 __ pop(rdi);
1394 __ ret(0);
1395
1396 __ bind(miss);
1397 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result
1398 __ pop(rax);
1399 __ pop(rcx);
1400 __ pop(rsi);
1401 __ pop(rdi);
1402 __ ret(0);
1403 }
1404 break;
1405
1406 case monitorenter_nofpu_id:
1407 save_fpu_registers = false;
1408 // fall through
1409 case monitorenter_id:
1410 {
1411 StubFrame f(sasm, "monitorenter", dont_gc_arguments);
1412 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
1413
1414 // Called with store_parameter and not C abi
1415
1416 f.load_argument(1, rax); // rax,: object
1417 f.load_argument(0, rbx); // rbx,: lock address
1418
1419 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx);
1420
1421 oop_maps = new OopMapSet();
1422 oop_maps->add_gc_map(call_offset, map);
1423 restore_live_registers(sasm, save_fpu_registers);
1424 }
1425 break;
1426
1427 case monitorexit_nofpu_id:
1428 save_fpu_registers = false;
1429 // fall through
1430 case monitorexit_id:
1431 {
1432 StubFrame f(sasm, "monitorexit", dont_gc_arguments);
1433 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
1434
1435 // Called with store_parameter and not C abi
1436
1437 f.load_argument(0, rax); // rax,: lock address
1438
1439 // note: really a leaf routine but must setup last java sp
1440 // => use call_RT for now (speed can be improved by
1441 // doing last java sp setup manually)
1442 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax);
1443
1444 oop_maps = new OopMapSet();
1445 oop_maps->add_gc_map(call_offset, map);
1446 restore_live_registers(sasm, save_fpu_registers);
1447 }
1448 break;
1449
1450 case deoptimize_id:
1451 {
1452 StubFrame f(sasm, "deoptimize", dont_gc_arguments);
1453 const int num_rt_args = 2; // thread, trap_request
1454 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
1455 f.load_argument(0, rax);
1456 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), rax);
1457 oop_maps = new OopMapSet();
1458 oop_maps->add_gc_map(call_offset, oop_map);
1459 restore_live_registers(sasm);
1460 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1461 assert(deopt_blob != nullptr, "deoptimization blob must have been created");
1462 __ leave();
1463 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1464 }
1465 break;
1466
1467 case access_field_patching_id:
1468 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
1469 // we should set up register map
1470 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1471 }
1472 break;
1473
1474 case load_klass_patching_id:
1475 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
1476 // we should set up register map
1477 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1478 }
1479 break;
1480
1481 case load_mirror_patching_id:
1482 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments);
1483 // we should set up register map
1484 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1485 }
1486 break;
1487
1488 case load_appendix_patching_id:
1489 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
1490 // we should set up register map
1491 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1492 }
1493 break;
1494
1495 case dtrace_object_alloc_id:
1496 { // rax,: object
1497 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
1498 // we can't gc here so skip the oopmap but make sure that all
1499 // the live registers get saved.
1500 save_live_registers(sasm, 1);
1501
1502 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
1503 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, static_cast<int (*)(oopDesc*)>(SharedRuntime::dtrace_object_alloc))));
1504 NOT_LP64(__ pop(rax));
1505
1506 restore_live_registers(sasm);
1507 }
1508 break;
1509
1510 case fpu2long_stub_id:
1511 {
1512 #ifdef _LP64
1513 Label done;
1514 __ cvttsd2siq(rax, Address(rsp, wordSize));
1515 __ cmp64(rax, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
1516 __ jccb(Assembler::notEqual, done);
1517 __ movq(rax, Address(rsp, wordSize));
1518 __ subptr(rsp, 8);
1519 __ movq(Address(rsp, 0), rax);
1520 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
1521 __ pop(rax);
1522 __ bind(done);
1523 __ ret(0);
1524 #else
1525 // rax, and rdx are destroyed, but should be free since the result is returned there
1526 // preserve rsi,ecx
1527 __ push(rsi);
1528 __ push(rcx);
1529
1530 // check for NaN
1531 Label return0, do_return, return_min_jlong, do_convert;
1532
1533 Address value_high_word(rsp, wordSize + 4);
1534 Address value_low_word(rsp, wordSize);
1535 Address result_high_word(rsp, 3*wordSize + 4);
1536 Address result_low_word(rsp, 3*wordSize);
1537
1538 __ subptr(rsp, 32); // more than enough on 32bit
1539 __ fst_d(value_low_word);
1540 __ movl(rax, value_high_word);
1541 __ andl(rax, 0x7ff00000);
1542 __ cmpl(rax, 0x7ff00000);
1543 __ jcc(Assembler::notEqual, do_convert);
1544 __ movl(rax, value_high_word);
1545 __ andl(rax, 0xfffff);
1546 __ orl(rax, value_low_word);
1547 __ jcc(Assembler::notZero, return0);
1548
1549 __ bind(do_convert);
1550 __ fnstcw(Address(rsp, 0));
1551 __ movzwl(rax, Address(rsp, 0));
1552 __ orl(rax, 0xc00);
1553 __ movw(Address(rsp, 2), rax);
1554 __ fldcw(Address(rsp, 2));
1555 __ fwait();
1556 __ fistp_d(result_low_word);
1557 __ fldcw(Address(rsp, 0));
1558 __ fwait();
1559 // This gets the entire long in rax on 64bit
1560 __ movptr(rax, result_low_word);
1561 // testing of high bits
1562 __ movl(rdx, result_high_word);
1563 __ mov(rcx, rax);
1564 // What the heck is the point of the next instruction???
1565 __ xorl(rcx, 0x0);
1566 __ movl(rsi, 0x80000000);
1567 __ xorl(rsi, rdx);
1568 __ orl(rcx, rsi);
1569 __ jcc(Assembler::notEqual, do_return);
1570 __ fldz();
1571 __ fcomp_d(value_low_word);
1572 __ fnstsw_ax();
1573 __ sahf();
1574 __ jcc(Assembler::above, return_min_jlong);
1575 // return max_jlong
1576 __ movl(rdx, 0x7fffffff);
1577 __ movl(rax, 0xffffffff);
1578 __ jmp(do_return);
1579
1580 __ bind(return_min_jlong);
1581 __ movl(rdx, 0x80000000);
1582 __ xorl(rax, rax);
1583 __ jmp(do_return);
1584
1585 __ bind(return0);
1586 __ fpop();
1587 __ xorptr(rdx,rdx);
1588 __ xorptr(rax,rax);
1589
1590 __ bind(do_return);
1591 __ addptr(rsp, 32);
1592 __ pop(rcx);
1593 __ pop(rsi);
1594 __ ret(0);
1595 #endif // _LP64
1596 }
1597 break;
1598
1599 case predicate_failed_trap_id:
1600 {
1601 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
1602
1603 OopMap* map = save_live_registers(sasm, 1);
1604
1605 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1606 oop_maps = new OopMapSet();
1607 oop_maps->add_gc_map(call_offset, map);
1608 restore_live_registers(sasm);
1609 __ leave();
1610 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1611 assert(deopt_blob != nullptr, "deoptimization blob must have been created");
1612
1613 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1614 }
1615 break;
1616
1617 default:
1618 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
1619 __ movptr(rax, (int)id);
1620 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1621 __ should_not_reach_here();
1622 }
1623 break;
1624 }
1625 return oop_maps;
1626 }
1627
1628 #undef __
1629
1630 const char *Runtime1::pd_name_for_address(address entry) {
1631 return "<unknown function>";
1632 }