1 /* 2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_GLOBALS_X86_HPP 26 #define CPU_X86_GLOBALS_X86_HPP 27 28 #include "utilities/globalDefinitions.hpp" 29 #include "utilities/macros.hpp" 30 31 // Sets the default values for platform dependent flags used by the runtime system. 32 // (see globals.hpp) 33 34 define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks 35 define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86. 36 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast 37 38 define_pd_global(uintx, CodeCacheSegmentSize, 64 COMPILER1_AND_COMPILER2_PRESENT(+64)); // Tiered compilation has large code-entry alignment. 39 // See 4827828 for this change. There is no globals_core_i486.hpp. I can't 40 // assign a different value for C2 without touching a number of files. Use 41 // #ifdef to minimize the change as it's late in Mantis. -- FIXME. 42 // c1 doesn't have this problem because the fix to 4858033 assures us 43 // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns 44 // the uep and the vep doesn't get real alignment but just slops on by 45 // only assured that the entry instruction meets the 5 byte size requirement. 46 #if COMPILER2_OR_JVMCI 47 define_pd_global(intx, CodeEntryAlignment, 32); 48 #else 49 define_pd_global(intx, CodeEntryAlignment, 16); 50 #endif // COMPILER2_OR_JVMCI 51 define_pd_global(intx, OptoLoopAlignment, 16); 52 define_pd_global(intx, InlineSmallCode, 1000); 53 54 #define DEFAULT_STACK_YELLOW_PAGES (NOT_WINDOWS(2) WINDOWS_ONLY(3)) 55 #define DEFAULT_STACK_RED_PAGES (1) 56 #define DEFAULT_STACK_RESERVED_PAGES (NOT_WINDOWS(1) WINDOWS_ONLY(0)) 57 58 #define MIN_STACK_YELLOW_PAGES DEFAULT_STACK_YELLOW_PAGES 59 #define MIN_STACK_RED_PAGES DEFAULT_STACK_RED_PAGES 60 #define MIN_STACK_RESERVED_PAGES (0) 61 62 #ifdef _LP64 63 // Java_java_net_SocketOutputStream_socketWrite0() uses a 64k buffer on the 64 // stack if compiled for unix and LP64. To pass stack overflow tests we need 65 // 20 shadow pages. 66 #define DEFAULT_STACK_SHADOW_PAGES (NOT_WIN64(20) WIN64_ONLY(7) DEBUG_ONLY(+2)) 67 // For those clients that do not use write socket, we allow 68 // the min range value to be below that of the default 69 #define MIN_STACK_SHADOW_PAGES (NOT_WIN64(10) WIN64_ONLY(7) DEBUG_ONLY(+2)) 70 #else 71 #define DEFAULT_STACK_SHADOW_PAGES (4 DEBUG_ONLY(+5)) 72 #define MIN_STACK_SHADOW_PAGES DEFAULT_STACK_SHADOW_PAGES 73 #endif // _LP64 74 75 define_pd_global(intx, StackYellowPages, DEFAULT_STACK_YELLOW_PAGES); 76 define_pd_global(intx, StackRedPages, DEFAULT_STACK_RED_PAGES); 77 define_pd_global(intx, StackShadowPages, DEFAULT_STACK_SHADOW_PAGES); 78 define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGES); 79 80 define_pd_global(bool, RewriteBytecodes, true); 81 define_pd_global(bool, RewriteFrequentPairs, true); 82 83 define_pd_global(uintx, TypeProfileLevel, 111); 84 85 define_pd_global(bool, CompactStrings, true); 86 87 define_pd_global(bool, PreserveFramePointer, false); 88 89 define_pd_global(intx, InitArrayShortSize, 8*BytesPerLong); 90 91 define_pd_global(bool, InlineTypePassFieldsAsArgs, LP64_ONLY(true) NOT_LP64(false)); 92 define_pd_global(bool, InlineTypeReturnedAsFields, LP64_ONLY(true) NOT_LP64(false)); 93 94 #define ARCH_FLAGS(develop, \ 95 product, \ 96 notproduct, \ 97 range, \ 98 constraint) \ 99 \ 100 develop(bool, IEEEPrecision, true, \ 101 "Enables IEEE precision (for INTEL only)") \ 102 \ 103 product(bool, UseStoreImmI16, true, \ 104 "Use store immediate 16-bits value instruction on x86") \ 105 \ 106 product(intx, UseSSE, 99, \ 107 "Highest supported SSE instructions set on x86/x64") \ 108 range(0, 99) \ 109 \ 110 product(intx, UseAVX, 3, \ 111 "Highest supported AVX instructions set on x86/x64") \ 112 range(0, 99) \ 113 \ 114 product(bool, UseKNLSetting, false, DIAGNOSTIC, \ 115 "Control whether Knights platform setting should be used") \ 116 \ 117 product(bool, UseCLMUL, false, \ 118 "Control whether CLMUL instructions can be used on x86/x64") \ 119 \ 120 product(bool, UseIncDec, true, DIAGNOSTIC, \ 121 "Use INC, DEC instructions on x86") \ 122 \ 123 product(bool, UseNewLongLShift, false, \ 124 "Use optimized bitwise shift left") \ 125 \ 126 product(bool, UseAddressNop, false, \ 127 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \ 128 \ 129 product(bool, UseXmmLoadAndClearUpper, true, \ 130 "Load low part of XMM register and clear upper part") \ 131 \ 132 product(bool, UseXmmRegToRegMoveAll, false, \ 133 "Copy all XMM register bits when moving value between registers") \ 134 \ 135 product(bool, UseXmmI2D, false, \ 136 "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \ 137 \ 138 product(bool, UseXmmI2F, false, \ 139 "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \ 140 \ 141 product(bool, UseUnalignedLoadStores, false, \ 142 "Use SSE2 MOVDQU instruction for Arraycopy") \ 143 \ 144 product(bool, UseXMMForObjInit, false, \ 145 "Use XMM/YMM MOVDQU instruction for Object Initialization") \ 146 \ 147 product(bool, UseFastStosb, false, \ 148 "Use fast-string operation for zeroing: rep stosb") \ 149 \ 150 /* Use Restricted Transactional Memory for lock eliding */ \ 151 product(bool, UseRTMLocking, false, \ 152 "Enable RTM lock eliding for inflated locks in compiled code") \ 153 \ 154 product(bool, UseRTMForStackLocks, false, EXPERIMENTAL, \ 155 "Enable RTM lock eliding for stack locks in compiled code") \ 156 \ 157 product(bool, UseRTMDeopt, false, \ 158 "Perform deopt and recompilation based on RTM abort ratio") \ 159 \ 160 product(int, RTMRetryCount, 5, \ 161 "Number of RTM retries on lock abort or busy") \ 162 range(0, max_jint) \ 163 \ 164 product(int, RTMSpinLoopCount, 100, EXPERIMENTAL, \ 165 "Spin count for lock to become free before RTM retry") \ 166 range(0, max_jint) \ 167 \ 168 product(int, RTMAbortThreshold, 1000, EXPERIMENTAL, \ 169 "Calculate abort ratio after this number of aborts") \ 170 range(0, max_jint) \ 171 \ 172 product(int, RTMLockingThreshold, 10000, EXPERIMENTAL, \ 173 "Lock count at which to do RTM lock eliding without " \ 174 "abort ratio calculation") \ 175 range(0, max_jint) \ 176 \ 177 product(int, RTMAbortRatio, 50, EXPERIMENTAL, \ 178 "Lock abort ratio at which to stop use RTM lock eliding") \ 179 range(0, 100) /* natural range */ \ 180 \ 181 product(int, RTMTotalCountIncrRate, 64, EXPERIMENTAL, \ 182 "Increment total RTM attempted lock count once every n times") \ 183 range(1, max_jint) \ 184 constraint(RTMTotalCountIncrRateConstraintFunc,AfterErgo) \ 185 \ 186 product(intx, RTMLockingCalculationDelay, 0, EXPERIMENTAL, \ 187 "Number of milliseconds to wait before start calculating aborts " \ 188 "for RTM locking") \ 189 \ 190 product(bool, UseRTMXendForLockBusy, true, EXPERIMENTAL, \ 191 "Use RTM Xend instead of Xabort when lock busy") \ 192 \ 193 /* assembler */ \ 194 product(bool, UseCountLeadingZerosInstruction, false, \ 195 "Use count leading zeros instruction") \ 196 \ 197 product(bool, UseCountTrailingZerosInstruction, false, \ 198 "Use count trailing zeros instruction") \ 199 \ 200 product(bool, UseSSE42Intrinsics, false, \ 201 "SSE4.2 versions of intrinsics") \ 202 \ 203 product(bool, UseBMI1Instructions, false, \ 204 "Use BMI1 instructions") \ 205 \ 206 product(bool, UseBMI2Instructions, false, \ 207 "Use BMI2 instructions") \ 208 \ 209 product(bool, UseLibmIntrinsic, true, DIAGNOSTIC, \ 210 "Use Libm Intrinsics") \ 211 \ 212 /* Minimum array size in bytes to use AVX512 intrinsics */ \ 213 /* for copy, inflate and fill which don't bail out early based on any */ \ 214 /* condition. When this value is set to zero compare operations like */ \ 215 /* compare, vectorizedMismatch, compress can also use AVX512 intrinsics.*/\ 216 product(int, AVX3Threshold, 4096, DIAGNOSTIC, \ 217 "Minimum array size in bytes to use AVX512 intrinsics" \ 218 "for copy, inflate and fill. When this value is set as zero" \ 219 "compare operations can also use AVX512 intrinsics.") \ 220 range(0, max_jint) \ 221 constraint(AVX3ThresholdConstraintFunc,AfterErgo) \ 222 \ 223 product(bool, IntelJccErratumMitigation, true, DIAGNOSTIC, \ 224 "Turn off JVM mitigations related to Intel micro code " \ 225 "mitigations for the Intel JCC erratum") 226 227 // end of ARCH_FLAGS 228 229 #endif // CPU_X86_GLOBALS_X86_HPP